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TARGET_MTS_MDOT_F405RG/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cortex.h@145:64910690c574, 2017-06-21 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Jun 21 17:31:38 2017 +0100
- Revision:
- 145:64910690c574
- Parent:
- 128:9bcdf88f62b0
Release 145 of the mbed library.
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| bogdanm | 92:4fc01daae5a5 | 1 | /** |
| bogdanm | 92:4fc01daae5a5 | 2 | ****************************************************************************** |
| bogdanm | 92:4fc01daae5a5 | 3 | * @file stm32f4xx_hal_cortex.h |
| bogdanm | 92:4fc01daae5a5 | 4 | * @author MCD Application Team |
| AnnaBridge | 145:64910690c574 | 5 | * @version V1.7.1 |
| AnnaBridge | 145:64910690c574 | 6 | * @date 14-April-2017 |
| bogdanm | 92:4fc01daae5a5 | 7 | * @brief Header file of CORTEX HAL module. |
| bogdanm | 92:4fc01daae5a5 | 8 | ****************************************************************************** |
| bogdanm | 92:4fc01daae5a5 | 9 | * @attention |
| bogdanm | 92:4fc01daae5a5 | 10 | * |
| AnnaBridge | 145:64910690c574 | 11 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
| bogdanm | 92:4fc01daae5a5 | 12 | * |
| bogdanm | 92:4fc01daae5a5 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| bogdanm | 92:4fc01daae5a5 | 14 | * are permitted provided that the following conditions are met: |
| bogdanm | 92:4fc01daae5a5 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| bogdanm | 92:4fc01daae5a5 | 16 | * this list of conditions and the following disclaimer. |
| bogdanm | 92:4fc01daae5a5 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| bogdanm | 92:4fc01daae5a5 | 18 | * this list of conditions and the following disclaimer in the documentation |
| bogdanm | 92:4fc01daae5a5 | 19 | * and/or other materials provided with the distribution. |
| bogdanm | 92:4fc01daae5a5 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| bogdanm | 92:4fc01daae5a5 | 21 | * may be used to endorse or promote products derived from this software |
| bogdanm | 92:4fc01daae5a5 | 22 | * without specific prior written permission. |
| bogdanm | 92:4fc01daae5a5 | 23 | * |
| bogdanm | 92:4fc01daae5a5 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| bogdanm | 92:4fc01daae5a5 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| bogdanm | 92:4fc01daae5a5 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| bogdanm | 92:4fc01daae5a5 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| bogdanm | 92:4fc01daae5a5 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| bogdanm | 92:4fc01daae5a5 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| bogdanm | 92:4fc01daae5a5 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| bogdanm | 92:4fc01daae5a5 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| bogdanm | 92:4fc01daae5a5 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| bogdanm | 92:4fc01daae5a5 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| bogdanm | 92:4fc01daae5a5 | 34 | * |
| bogdanm | 92:4fc01daae5a5 | 35 | ****************************************************************************** |
| bogdanm | 92:4fc01daae5a5 | 36 | */ |
| bogdanm | 92:4fc01daae5a5 | 37 | |
| bogdanm | 92:4fc01daae5a5 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 39 | #ifndef __STM32F4xx_HAL_CORTEX_H |
| bogdanm | 92:4fc01daae5a5 | 40 | #define __STM32F4xx_HAL_CORTEX_H |
| bogdanm | 92:4fc01daae5a5 | 41 | |
| bogdanm | 92:4fc01daae5a5 | 42 | #ifdef __cplusplus |
| bogdanm | 92:4fc01daae5a5 | 43 | extern "C" { |
| bogdanm | 92:4fc01daae5a5 | 44 | #endif |
| bogdanm | 92:4fc01daae5a5 | 45 | |
| bogdanm | 92:4fc01daae5a5 | 46 | /* Includes ------------------------------------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 47 | #include "stm32f4xx_hal_def.h" |
| bogdanm | 92:4fc01daae5a5 | 48 | |
| bogdanm | 92:4fc01daae5a5 | 49 | /** @addtogroup STM32F4xx_HAL_Driver |
| bogdanm | 92:4fc01daae5a5 | 50 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 51 | */ |
| bogdanm | 92:4fc01daae5a5 | 52 | |
| bogdanm | 92:4fc01daae5a5 | 53 | /** @addtogroup CORTEX |
| bogdanm | 92:4fc01daae5a5 | 54 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 55 | */ |
| bogdanm | 92:4fc01daae5a5 | 56 | /* Exported types ------------------------------------------------------------*/ |
| Kojto | 110:165afa46840b | 57 | /** @defgroup CORTEX_Exported_Types Cortex Exported Types |
| Kojto | 110:165afa46840b | 58 | * @{ |
| Kojto | 110:165afa46840b | 59 | */ |
| Kojto | 110:165afa46840b | 60 | |
| AnnaBridge | 145:64910690c574 | 61 | #if (__MPU_PRESENT == 1U) |
| Kojto | 110:165afa46840b | 62 | /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition |
| Kojto | 110:165afa46840b | 63 | * @brief MPU Region initialization structure |
| Kojto | 110:165afa46840b | 64 | * @{ |
| Kojto | 110:165afa46840b | 65 | */ |
| Kojto | 110:165afa46840b | 66 | typedef struct |
| Kojto | 110:165afa46840b | 67 | { |
| Kojto | 110:165afa46840b | 68 | uint8_t Enable; /*!< Specifies the status of the region. |
| Kojto | 110:165afa46840b | 69 | This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ |
| Kojto | 110:165afa46840b | 70 | uint8_t Number; /*!< Specifies the number of the region to protect. |
| Kojto | 110:165afa46840b | 71 | This parameter can be a value of @ref CORTEX_MPU_Region_Number */ |
| Kojto | 110:165afa46840b | 72 | uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ |
| Kojto | 110:165afa46840b | 73 | uint8_t Size; /*!< Specifies the size of the region to protect. |
| Kojto | 110:165afa46840b | 74 | This parameter can be a value of @ref CORTEX_MPU_Region_Size */ |
| Kojto | 110:165afa46840b | 75 | uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. |
| Kojto | 110:165afa46840b | 76 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ |
| Kojto | 110:165afa46840b | 77 | uint8_t TypeExtField; /*!< Specifies the TEX field level. |
| Kojto | 110:165afa46840b | 78 | This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ |
| Kojto | 110:165afa46840b | 79 | uint8_t AccessPermission; /*!< Specifies the region access permission type. |
| Kojto | 110:165afa46840b | 80 | This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ |
| Kojto | 110:165afa46840b | 81 | uint8_t DisableExec; /*!< Specifies the instruction access status. |
| Kojto | 110:165afa46840b | 82 | This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ |
| Kojto | 110:165afa46840b | 83 | uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. |
| Kojto | 110:165afa46840b | 84 | This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ |
| Kojto | 110:165afa46840b | 85 | uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. |
| Kojto | 110:165afa46840b | 86 | This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ |
| Kojto | 110:165afa46840b | 87 | uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. |
| Kojto | 110:165afa46840b | 88 | This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ |
| Kojto | 110:165afa46840b | 89 | }MPU_Region_InitTypeDef; |
| Kojto | 110:165afa46840b | 90 | /** |
| Kojto | 110:165afa46840b | 91 | * @} |
| Kojto | 110:165afa46840b | 92 | */ |
| Kojto | 110:165afa46840b | 93 | #endif /* __MPU_PRESENT */ |
| Kojto | 110:165afa46840b | 94 | |
| Kojto | 110:165afa46840b | 95 | /** |
| Kojto | 110:165afa46840b | 96 | * @} |
| Kojto | 110:165afa46840b | 97 | */ |
| Kojto | 110:165afa46840b | 98 | |
| bogdanm | 92:4fc01daae5a5 | 99 | /* Exported constants --------------------------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 100 | |
| Kojto | 99:dbbf35b96557 | 101 | /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants |
| bogdanm | 92:4fc01daae5a5 | 102 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 103 | */ |
| bogdanm | 92:4fc01daae5a5 | 104 | |
| Kojto | 99:dbbf35b96557 | 105 | /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group |
| bogdanm | 92:4fc01daae5a5 | 106 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 107 | */ |
| AnnaBridge | 145:64910690c574 | 108 | #define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority |
| AnnaBridge | 145:64910690c574 | 109 | 4 bits for subpriority */ |
| AnnaBridge | 145:64910690c574 | 110 | #define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority |
| AnnaBridge | 145:64910690c574 | 111 | 3 bits for subpriority */ |
| AnnaBridge | 145:64910690c574 | 112 | #define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority |
| AnnaBridge | 145:64910690c574 | 113 | 2 bits for subpriority */ |
| AnnaBridge | 145:64910690c574 | 114 | #define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority |
| AnnaBridge | 145:64910690c574 | 115 | 1 bits for subpriority */ |
| AnnaBridge | 145:64910690c574 | 116 | #define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority |
| AnnaBridge | 145:64910690c574 | 117 | 0 bits for subpriority */ |
| Kojto | 99:dbbf35b96557 | 118 | /** |
| Kojto | 99:dbbf35b96557 | 119 | * @} |
| Kojto | 99:dbbf35b96557 | 120 | */ |
| bogdanm | 92:4fc01daae5a5 | 121 | |
| Kojto | 99:dbbf35b96557 | 122 | /** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source |
| Kojto | 99:dbbf35b96557 | 123 | * @{ |
| Kojto | 99:dbbf35b96557 | 124 | */ |
| AnnaBridge | 145:64910690c574 | 125 | #define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U |
| AnnaBridge | 145:64910690c574 | 126 | #define SYSTICK_CLKSOURCE_HCLK 0x00000004U |
| bogdanm | 92:4fc01daae5a5 | 127 | |
| bogdanm | 92:4fc01daae5a5 | 128 | /** |
| bogdanm | 92:4fc01daae5a5 | 129 | * @} |
| bogdanm | 92:4fc01daae5a5 | 130 | */ |
| bogdanm | 92:4fc01daae5a5 | 131 | |
| Kojto | 110:165afa46840b | 132 | #if (__MPU_PRESENT == 1) |
| Kojto | 110:165afa46840b | 133 | /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control |
| Kojto | 110:165afa46840b | 134 | * @{ |
| Kojto | 110:165afa46840b | 135 | */ |
| AnnaBridge | 145:64910690c574 | 136 | #define MPU_HFNMI_PRIVDEF_NONE 0x00000000U |
| AnnaBridge | 145:64910690c574 | 137 | #define MPU_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk |
| AnnaBridge | 145:64910690c574 | 138 | #define MPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk |
| AnnaBridge | 145:64910690c574 | 139 | #define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) |
| AnnaBridge | 145:64910690c574 | 140 | |
| Kojto | 110:165afa46840b | 141 | /** |
| Kojto | 110:165afa46840b | 142 | * @} |
| Kojto | 110:165afa46840b | 143 | */ |
| Kojto | 110:165afa46840b | 144 | |
| Kojto | 110:165afa46840b | 145 | /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable |
| Kojto | 110:165afa46840b | 146 | * @{ |
| Kojto | 110:165afa46840b | 147 | */ |
| AnnaBridge | 145:64910690c574 | 148 | #define MPU_REGION_ENABLE ((uint8_t)0x01) |
| AnnaBridge | 145:64910690c574 | 149 | #define MPU_REGION_DISABLE ((uint8_t)0x00) |
| Kojto | 110:165afa46840b | 150 | /** |
| Kojto | 110:165afa46840b | 151 | * @} |
| Kojto | 110:165afa46840b | 152 | */ |
| Kojto | 110:165afa46840b | 153 | |
| Kojto | 110:165afa46840b | 154 | /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access |
| Kojto | 110:165afa46840b | 155 | * @{ |
| Kojto | 110:165afa46840b | 156 | */ |
| AnnaBridge | 145:64910690c574 | 157 | #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) |
| AnnaBridge | 145:64910690c574 | 158 | #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) |
| Kojto | 110:165afa46840b | 159 | /** |
| Kojto | 110:165afa46840b | 160 | * @} |
| Kojto | 110:165afa46840b | 161 | */ |
| Kojto | 110:165afa46840b | 162 | |
| Kojto | 110:165afa46840b | 163 | /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable |
| Kojto | 110:165afa46840b | 164 | * @{ |
| Kojto | 110:165afa46840b | 165 | */ |
| AnnaBridge | 145:64910690c574 | 166 | #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) |
| AnnaBridge | 145:64910690c574 | 167 | #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) |
| Kojto | 110:165afa46840b | 168 | /** |
| Kojto | 110:165afa46840b | 169 | * @} |
| Kojto | 110:165afa46840b | 170 | */ |
| Kojto | 110:165afa46840b | 171 | |
| Kojto | 110:165afa46840b | 172 | /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable |
| Kojto | 110:165afa46840b | 173 | * @{ |
| Kojto | 110:165afa46840b | 174 | */ |
| AnnaBridge | 145:64910690c574 | 175 | #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) |
| AnnaBridge | 145:64910690c574 | 176 | #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) |
| Kojto | 110:165afa46840b | 177 | /** |
| Kojto | 110:165afa46840b | 178 | * @} |
| Kojto | 110:165afa46840b | 179 | */ |
| Kojto | 110:165afa46840b | 180 | |
| Kojto | 110:165afa46840b | 181 | /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable |
| Kojto | 110:165afa46840b | 182 | * @{ |
| Kojto | 110:165afa46840b | 183 | */ |
| AnnaBridge | 145:64910690c574 | 184 | #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) |
| AnnaBridge | 145:64910690c574 | 185 | #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) |
| Kojto | 110:165afa46840b | 186 | /** |
| Kojto | 110:165afa46840b | 187 | * @} |
| Kojto | 110:165afa46840b | 188 | */ |
| Kojto | 110:165afa46840b | 189 | |
| Kojto | 110:165afa46840b | 190 | /** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels |
| Kojto | 110:165afa46840b | 191 | * @{ |
| Kojto | 110:165afa46840b | 192 | */ |
| AnnaBridge | 145:64910690c574 | 193 | #define MPU_TEX_LEVEL0 ((uint8_t)0x00) |
| AnnaBridge | 145:64910690c574 | 194 | #define MPU_TEX_LEVEL1 ((uint8_t)0x01) |
| AnnaBridge | 145:64910690c574 | 195 | #define MPU_TEX_LEVEL2 ((uint8_t)0x02) |
| Kojto | 110:165afa46840b | 196 | /** |
| Kojto | 110:165afa46840b | 197 | * @} |
| Kojto | 110:165afa46840b | 198 | */ |
| Kojto | 110:165afa46840b | 199 | |
| Kojto | 110:165afa46840b | 200 | /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size |
| Kojto | 110:165afa46840b | 201 | * @{ |
| Kojto | 110:165afa46840b | 202 | */ |
| AnnaBridge | 145:64910690c574 | 203 | #define MPU_REGION_SIZE_32B ((uint8_t)0x04) |
| AnnaBridge | 145:64910690c574 | 204 | #define MPU_REGION_SIZE_64B ((uint8_t)0x05) |
| AnnaBridge | 145:64910690c574 | 205 | #define MPU_REGION_SIZE_128B ((uint8_t)0x06) |
| AnnaBridge | 145:64910690c574 | 206 | #define MPU_REGION_SIZE_256B ((uint8_t)0x07) |
| AnnaBridge | 145:64910690c574 | 207 | #define MPU_REGION_SIZE_512B ((uint8_t)0x08) |
| AnnaBridge | 145:64910690c574 | 208 | #define MPU_REGION_SIZE_1KB ((uint8_t)0x09) |
| AnnaBridge | 145:64910690c574 | 209 | #define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) |
| AnnaBridge | 145:64910690c574 | 210 | #define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) |
| AnnaBridge | 145:64910690c574 | 211 | #define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) |
| AnnaBridge | 145:64910690c574 | 212 | #define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) |
| AnnaBridge | 145:64910690c574 | 213 | #define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) |
| AnnaBridge | 145:64910690c574 | 214 | #define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) |
| AnnaBridge | 145:64910690c574 | 215 | #define MPU_REGION_SIZE_128KB ((uint8_t)0x10) |
| AnnaBridge | 145:64910690c574 | 216 | #define MPU_REGION_SIZE_256KB ((uint8_t)0x11) |
| AnnaBridge | 145:64910690c574 | 217 | #define MPU_REGION_SIZE_512KB ((uint8_t)0x12) |
| AnnaBridge | 145:64910690c574 | 218 | #define MPU_REGION_SIZE_1MB ((uint8_t)0x13) |
| AnnaBridge | 145:64910690c574 | 219 | #define MPU_REGION_SIZE_2MB ((uint8_t)0x14) |
| AnnaBridge | 145:64910690c574 | 220 | #define MPU_REGION_SIZE_4MB ((uint8_t)0x15) |
| AnnaBridge | 145:64910690c574 | 221 | #define MPU_REGION_SIZE_8MB ((uint8_t)0x16) |
| AnnaBridge | 145:64910690c574 | 222 | #define MPU_REGION_SIZE_16MB ((uint8_t)0x17) |
| AnnaBridge | 145:64910690c574 | 223 | #define MPU_REGION_SIZE_32MB ((uint8_t)0x18) |
| AnnaBridge | 145:64910690c574 | 224 | #define MPU_REGION_SIZE_64MB ((uint8_t)0x19) |
| AnnaBridge | 145:64910690c574 | 225 | #define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) |
| AnnaBridge | 145:64910690c574 | 226 | #define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) |
| AnnaBridge | 145:64910690c574 | 227 | #define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) |
| AnnaBridge | 145:64910690c574 | 228 | #define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) |
| AnnaBridge | 145:64910690c574 | 229 | #define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) |
| AnnaBridge | 145:64910690c574 | 230 | #define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) |
| Kojto | 122:f9eeca106725 | 231 | /** |
| Kojto | 110:165afa46840b | 232 | * @} |
| Kojto | 110:165afa46840b | 233 | */ |
| Kojto | 110:165afa46840b | 234 | |
| Kojto | 110:165afa46840b | 235 | /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes |
| Kojto | 110:165afa46840b | 236 | * @{ |
| Kojto | 110:165afa46840b | 237 | */ |
| AnnaBridge | 145:64910690c574 | 238 | #define MPU_REGION_NO_ACCESS ((uint8_t)0x00) |
| AnnaBridge | 145:64910690c574 | 239 | #define MPU_REGION_PRIV_RW ((uint8_t)0x01) |
| AnnaBridge | 145:64910690c574 | 240 | #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) |
| AnnaBridge | 145:64910690c574 | 241 | #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) |
| AnnaBridge | 145:64910690c574 | 242 | #define MPU_REGION_PRIV_RO ((uint8_t)0x05) |
| AnnaBridge | 145:64910690c574 | 243 | #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) |
| Kojto | 110:165afa46840b | 244 | /** |
| Kojto | 110:165afa46840b | 245 | * @} |
| Kojto | 110:165afa46840b | 246 | */ |
| Kojto | 110:165afa46840b | 247 | |
| Kojto | 110:165afa46840b | 248 | /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number |
| Kojto | 110:165afa46840b | 249 | * @{ |
| Kojto | 110:165afa46840b | 250 | */ |
| AnnaBridge | 145:64910690c574 | 251 | #define MPU_REGION_NUMBER0 ((uint8_t)0x00) |
| AnnaBridge | 145:64910690c574 | 252 | #define MPU_REGION_NUMBER1 ((uint8_t)0x01) |
| AnnaBridge | 145:64910690c574 | 253 | #define MPU_REGION_NUMBER2 ((uint8_t)0x02) |
| AnnaBridge | 145:64910690c574 | 254 | #define MPU_REGION_NUMBER3 ((uint8_t)0x03) |
| AnnaBridge | 145:64910690c574 | 255 | #define MPU_REGION_NUMBER4 ((uint8_t)0x04) |
| AnnaBridge | 145:64910690c574 | 256 | #define MPU_REGION_NUMBER5 ((uint8_t)0x05) |
| AnnaBridge | 145:64910690c574 | 257 | #define MPU_REGION_NUMBER6 ((uint8_t)0x06) |
| AnnaBridge | 145:64910690c574 | 258 | #define MPU_REGION_NUMBER7 ((uint8_t)0x07) |
| Kojto | 110:165afa46840b | 259 | /** |
| Kojto | 110:165afa46840b | 260 | * @} |
| Kojto | 110:165afa46840b | 261 | */ |
| Kojto | 110:165afa46840b | 262 | #endif /* __MPU_PRESENT */ |
| Kojto | 110:165afa46840b | 263 | |
| bogdanm | 92:4fc01daae5a5 | 264 | /** |
| bogdanm | 92:4fc01daae5a5 | 265 | * @} |
| bogdanm | 92:4fc01daae5a5 | 266 | */ |
| bogdanm | 92:4fc01daae5a5 | 267 | |
| Kojto | 99:dbbf35b96557 | 268 | |
| bogdanm | 92:4fc01daae5a5 | 269 | /* Exported Macros -----------------------------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 270 | |
| bogdanm | 92:4fc01daae5a5 | 271 | /* Exported functions --------------------------------------------------------*/ |
| Kojto | 99:dbbf35b96557 | 272 | /** @addtogroup CORTEX_Exported_Functions |
| Kojto | 99:dbbf35b96557 | 273 | * @{ |
| Kojto | 99:dbbf35b96557 | 274 | */ |
| Kojto | 99:dbbf35b96557 | 275 | |
| Kojto | 99:dbbf35b96557 | 276 | /** @addtogroup CORTEX_Exported_Functions_Group1 |
| AnnaBridge | 145:64910690c574 | 277 | * @{ |
| AnnaBridge | 145:64910690c574 | 278 | */ |
| Kojto | 99:dbbf35b96557 | 279 | /* Initialization and de-initialization functions *****************************/ |
| bogdanm | 92:4fc01daae5a5 | 280 | void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); |
| bogdanm | 92:4fc01daae5a5 | 281 | void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); |
| bogdanm | 92:4fc01daae5a5 | 282 | void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); |
| bogdanm | 92:4fc01daae5a5 | 283 | void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); |
| bogdanm | 92:4fc01daae5a5 | 284 | void HAL_NVIC_SystemReset(void); |
| bogdanm | 92:4fc01daae5a5 | 285 | uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); |
| Kojto | 99:dbbf35b96557 | 286 | /** |
| Kojto | 99:dbbf35b96557 | 287 | * @} |
| Kojto | 99:dbbf35b96557 | 288 | */ |
| bogdanm | 92:4fc01daae5a5 | 289 | |
| Kojto | 99:dbbf35b96557 | 290 | /** @addtogroup CORTEX_Exported_Functions_Group2 |
| AnnaBridge | 145:64910690c574 | 291 | * @{ |
| AnnaBridge | 145:64910690c574 | 292 | */ |
| Kojto | 99:dbbf35b96557 | 293 | /* Peripheral Control functions ***********************************************/ |
| bogdanm | 92:4fc01daae5a5 | 294 | uint32_t HAL_NVIC_GetPriorityGrouping(void); |
| bogdanm | 92:4fc01daae5a5 | 295 | void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); |
| bogdanm | 92:4fc01daae5a5 | 296 | uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); |
| bogdanm | 92:4fc01daae5a5 | 297 | void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); |
| bogdanm | 92:4fc01daae5a5 | 298 | void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); |
| bogdanm | 92:4fc01daae5a5 | 299 | uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); |
| bogdanm | 92:4fc01daae5a5 | 300 | void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); |
| bogdanm | 92:4fc01daae5a5 | 301 | void HAL_SYSTICK_IRQHandler(void); |
| bogdanm | 92:4fc01daae5a5 | 302 | void HAL_SYSTICK_Callback(void); |
| AnnaBridge | 145:64910690c574 | 303 | |
| AnnaBridge | 145:64910690c574 | 304 | #if (__MPU_PRESENT == 1U) |
| AnnaBridge | 145:64910690c574 | 305 | void HAL_MPU_Enable(uint32_t MPU_Control); |
| AnnaBridge | 145:64910690c574 | 306 | void HAL_MPU_Disable(void); |
| AnnaBridge | 145:64910690c574 | 307 | void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); |
| AnnaBridge | 145:64910690c574 | 308 | #endif /* __MPU_PRESENT */ |
| Kojto | 99:dbbf35b96557 | 309 | /** |
| Kojto | 99:dbbf35b96557 | 310 | * @} |
| Kojto | 99:dbbf35b96557 | 311 | */ |
| Kojto | 99:dbbf35b96557 | 312 | |
| Kojto | 99:dbbf35b96557 | 313 | /** |
| Kojto | 99:dbbf35b96557 | 314 | * @} |
| Kojto | 99:dbbf35b96557 | 315 | */ |
| Kojto | 99:dbbf35b96557 | 316 | |
| Kojto | 122:f9eeca106725 | 317 | /* Private types -------------------------------------------------------------*/ |
| Kojto | 99:dbbf35b96557 | 318 | /* Private variables ---------------------------------------------------------*/ |
| Kojto | 99:dbbf35b96557 | 319 | /* Private constants ---------------------------------------------------------*/ |
| Kojto | 99:dbbf35b96557 | 320 | /* Private macros ------------------------------------------------------------*/ |
| Kojto | 99:dbbf35b96557 | 321 | /** @defgroup CORTEX_Private_Macros CORTEX Private Macros |
| Kojto | 99:dbbf35b96557 | 322 | * @{ |
| Kojto | 99:dbbf35b96557 | 323 | */ |
| Kojto | 99:dbbf35b96557 | 324 | #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ |
| Kojto | 99:dbbf35b96557 | 325 | ((GROUP) == NVIC_PRIORITYGROUP_1) || \ |
| Kojto | 99:dbbf35b96557 | 326 | ((GROUP) == NVIC_PRIORITYGROUP_2) || \ |
| Kojto | 99:dbbf35b96557 | 327 | ((GROUP) == NVIC_PRIORITYGROUP_3) || \ |
| Kojto | 99:dbbf35b96557 | 328 | ((GROUP) == NVIC_PRIORITYGROUP_4)) |
| Kojto | 99:dbbf35b96557 | 329 | |
| Kojto | 122:f9eeca106725 | 330 | #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) |
| Kojto | 99:dbbf35b96557 | 331 | |
| Kojto | 122:f9eeca106725 | 332 | #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) |
| Kojto | 99:dbbf35b96557 | 333 | |
| Kojto | 122:f9eeca106725 | 334 | #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U) |
| Kojto | 99:dbbf35b96557 | 335 | |
| Kojto | 99:dbbf35b96557 | 336 | #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ |
| Kojto | 99:dbbf35b96557 | 337 | ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) |
| Kojto | 110:165afa46840b | 338 | |
| Kojto | 122:f9eeca106725 | 339 | #if (__MPU_PRESENT == 1U) |
| Kojto | 110:165afa46840b | 340 | #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ |
| Kojto | 110:165afa46840b | 341 | ((STATE) == MPU_REGION_DISABLE)) |
| Kojto | 110:165afa46840b | 342 | |
| Kojto | 110:165afa46840b | 343 | #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ |
| Kojto | 110:165afa46840b | 344 | ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) |
| Kojto | 110:165afa46840b | 345 | |
| Kojto | 110:165afa46840b | 346 | #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ |
| Kojto | 110:165afa46840b | 347 | ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) |
| Kojto | 110:165afa46840b | 348 | |
| Kojto | 110:165afa46840b | 349 | #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ |
| Kojto | 110:165afa46840b | 350 | ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) |
| Kojto | 110:165afa46840b | 351 | |
| Kojto | 110:165afa46840b | 352 | #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ |
| Kojto | 110:165afa46840b | 353 | ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) |
| Kojto | 110:165afa46840b | 354 | |
| Kojto | 110:165afa46840b | 355 | #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ |
| Kojto | 110:165afa46840b | 356 | ((TYPE) == MPU_TEX_LEVEL1) || \ |
| Kojto | 110:165afa46840b | 357 | ((TYPE) == MPU_TEX_LEVEL2)) |
| Kojto | 110:165afa46840b | 358 | |
| Kojto | 110:165afa46840b | 359 | #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ |
| Kojto | 110:165afa46840b | 360 | ((TYPE) == MPU_REGION_PRIV_RW) || \ |
| Kojto | 110:165afa46840b | 361 | ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ |
| Kojto | 110:165afa46840b | 362 | ((TYPE) == MPU_REGION_FULL_ACCESS) || \ |
| Kojto | 110:165afa46840b | 363 | ((TYPE) == MPU_REGION_PRIV_RO) || \ |
| Kojto | 110:165afa46840b | 364 | ((TYPE) == MPU_REGION_PRIV_RO_URO)) |
| Kojto | 110:165afa46840b | 365 | |
| Kojto | 110:165afa46840b | 366 | #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ |
| Kojto | 110:165afa46840b | 367 | ((NUMBER) == MPU_REGION_NUMBER1) || \ |
| Kojto | 110:165afa46840b | 368 | ((NUMBER) == MPU_REGION_NUMBER2) || \ |
| Kojto | 110:165afa46840b | 369 | ((NUMBER) == MPU_REGION_NUMBER3) || \ |
| Kojto | 110:165afa46840b | 370 | ((NUMBER) == MPU_REGION_NUMBER4) || \ |
| Kojto | 110:165afa46840b | 371 | ((NUMBER) == MPU_REGION_NUMBER5) || \ |
| Kojto | 110:165afa46840b | 372 | ((NUMBER) == MPU_REGION_NUMBER6) || \ |
| Kojto | 110:165afa46840b | 373 | ((NUMBER) == MPU_REGION_NUMBER7)) |
| Kojto | 110:165afa46840b | 374 | |
| Kojto | 110:165afa46840b | 375 | #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ |
| Kojto | 110:165afa46840b | 376 | ((SIZE) == MPU_REGION_SIZE_64B) || \ |
| Kojto | 110:165afa46840b | 377 | ((SIZE) == MPU_REGION_SIZE_128B) || \ |
| Kojto | 110:165afa46840b | 378 | ((SIZE) == MPU_REGION_SIZE_256B) || \ |
| Kojto | 110:165afa46840b | 379 | ((SIZE) == MPU_REGION_SIZE_512B) || \ |
| Kojto | 110:165afa46840b | 380 | ((SIZE) == MPU_REGION_SIZE_1KB) || \ |
| Kojto | 110:165afa46840b | 381 | ((SIZE) == MPU_REGION_SIZE_2KB) || \ |
| Kojto | 110:165afa46840b | 382 | ((SIZE) == MPU_REGION_SIZE_4KB) || \ |
| Kojto | 110:165afa46840b | 383 | ((SIZE) == MPU_REGION_SIZE_8KB) || \ |
| Kojto | 110:165afa46840b | 384 | ((SIZE) == MPU_REGION_SIZE_16KB) || \ |
| Kojto | 110:165afa46840b | 385 | ((SIZE) == MPU_REGION_SIZE_32KB) || \ |
| Kojto | 110:165afa46840b | 386 | ((SIZE) == MPU_REGION_SIZE_64KB) || \ |
| Kojto | 110:165afa46840b | 387 | ((SIZE) == MPU_REGION_SIZE_128KB) || \ |
| Kojto | 110:165afa46840b | 388 | ((SIZE) == MPU_REGION_SIZE_256KB) || \ |
| Kojto | 110:165afa46840b | 389 | ((SIZE) == MPU_REGION_SIZE_512KB) || \ |
| Kojto | 110:165afa46840b | 390 | ((SIZE) == MPU_REGION_SIZE_1MB) || \ |
| Kojto | 110:165afa46840b | 391 | ((SIZE) == MPU_REGION_SIZE_2MB) || \ |
| Kojto | 110:165afa46840b | 392 | ((SIZE) == MPU_REGION_SIZE_4MB) || \ |
| Kojto | 110:165afa46840b | 393 | ((SIZE) == MPU_REGION_SIZE_8MB) || \ |
| Kojto | 110:165afa46840b | 394 | ((SIZE) == MPU_REGION_SIZE_16MB) || \ |
| Kojto | 110:165afa46840b | 395 | ((SIZE) == MPU_REGION_SIZE_32MB) || \ |
| Kojto | 110:165afa46840b | 396 | ((SIZE) == MPU_REGION_SIZE_64MB) || \ |
| Kojto | 110:165afa46840b | 397 | ((SIZE) == MPU_REGION_SIZE_128MB) || \ |
| Kojto | 110:165afa46840b | 398 | ((SIZE) == MPU_REGION_SIZE_256MB) || \ |
| Kojto | 110:165afa46840b | 399 | ((SIZE) == MPU_REGION_SIZE_512MB) || \ |
| Kojto | 110:165afa46840b | 400 | ((SIZE) == MPU_REGION_SIZE_1GB) || \ |
| Kojto | 110:165afa46840b | 401 | ((SIZE) == MPU_REGION_SIZE_2GB) || \ |
| Kojto | 110:165afa46840b | 402 | ((SIZE) == MPU_REGION_SIZE_4GB)) |
| Kojto | 110:165afa46840b | 403 | |
| AnnaBridge | 145:64910690c574 | 404 | #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) |
| Kojto | 110:165afa46840b | 405 | #endif /* __MPU_PRESENT */ |
| Kojto | 110:165afa46840b | 406 | |
| Kojto | 110:165afa46840b | 407 | /** |
| Kojto | 110:165afa46840b | 408 | * @} |
| Kojto | 110:165afa46840b | 409 | */ |
| Kojto | 110:165afa46840b | 410 | |
| AnnaBridge | 145:64910690c574 | 411 | /* Private functions ---------------------------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 412 | |
| bogdanm | 92:4fc01daae5a5 | 413 | /** |
| bogdanm | 92:4fc01daae5a5 | 414 | * @} |
| bogdanm | 92:4fc01daae5a5 | 415 | */ |
| bogdanm | 92:4fc01daae5a5 | 416 | |
| bogdanm | 92:4fc01daae5a5 | 417 | /** |
| bogdanm | 92:4fc01daae5a5 | 418 | * @} |
| bogdanm | 92:4fc01daae5a5 | 419 | */ |
| bogdanm | 92:4fc01daae5a5 | 420 | |
| bogdanm | 92:4fc01daae5a5 | 421 | #ifdef __cplusplus |
| bogdanm | 92:4fc01daae5a5 | 422 | } |
| bogdanm | 92:4fc01daae5a5 | 423 | #endif |
| bogdanm | 92:4fc01daae5a5 | 424 | |
| bogdanm | 92:4fc01daae5a5 | 425 | #endif /* __STM32F4xx_HAL_CORTEX_H */ |
| bogdanm | 92:4fc01daae5a5 | 426 | |
| bogdanm | 92:4fc01daae5a5 | 427 | |
| bogdanm | 92:4fc01daae5a5 | 428 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
