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TARGET_DISCO_F469NI/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc.h@145:64910690c574, 2017-06-21 (annotated)

Committer:
AnnaBridge
Date:
Wed Jun 21 17:31:38 2017 +0100
Revision:
145:64910690c574
Parent:
128:9bcdf88f62b0 
Release 145 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 89:552587b429a1 1 /**
bogdanm 89:552587b429a1 2 ******************************************************************************
bogdanm 89:552587b429a1 3 * @file stm32f4xx_hal_rcc.h
bogdanm 89:552587b429a1 4 * @author MCD Application Team
AnnaBridge 145:64910690c574 5 * @version V1.7.1
AnnaBridge 145:64910690c574 6 * @date 14-April-2017
bogdanm 89:552587b429a1 7 * @brief Header file of RCC HAL module.
bogdanm 89:552587b429a1 8 ******************************************************************************
bogdanm 89:552587b429a1 9 * @attention
bogdanm 89:552587b429a1 10 *
AnnaBridge 145:64910690c574 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
bogdanm 89:552587b429a1 12 *
bogdanm 89:552587b429a1 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 89:552587b429a1 14 * are permitted provided that the following conditions are met:
bogdanm 89:552587b429a1 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 89:552587b429a1 16 * this list of conditions and the following disclaimer.
bogdanm 89:552587b429a1 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 89:552587b429a1 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 89:552587b429a1 19 * and/or other materials provided with the distribution.
bogdanm 89:552587b429a1 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 89:552587b429a1 21 * may be used to endorse or promote products derived from this software
bogdanm 89:552587b429a1 22 * without specific prior written permission.
bogdanm 89:552587b429a1 23 *
bogdanm 89:552587b429a1 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 89:552587b429a1 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 89:552587b429a1 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 89:552587b429a1 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 89:552587b429a1 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 89:552587b429a1 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 89:552587b429a1 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 89:552587b429a1 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 89:552587b429a1 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 89:552587b429a1 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 89:552587b429a1 34 *
bogdanm 89:552587b429a1 35 ******************************************************************************
bogdanm 89:552587b429a1 36 */
bogdanm 89:552587b429a1 37
bogdanm 89:552587b429a1 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 89:552587b429a1 39 #ifndef __STM32F4xx_HAL_RCC_H
bogdanm 89:552587b429a1 40 #define __STM32F4xx_HAL_RCC_H
bogdanm 89:552587b429a1 41
bogdanm 89:552587b429a1 42 #ifdef __cplusplus
bogdanm 89:552587b429a1 43 extern "C" {
bogdanm 89:552587b429a1 44 #endif
bogdanm 89:552587b429a1 45
bogdanm 89:552587b429a1 46 /* Includes ------------------------------------------------------------------*/
bogdanm 89:552587b429a1 47 #include "stm32f4xx_hal_def.h"
bogdanm 89:552587b429a1 48
Kojto 99:dbbf35b96557 49 /* Include RCC HAL Extended module */
Kojto 99:dbbf35b96557 50 /* (include on top of file since RCC structures are defined in extended file) */
Kojto 99:dbbf35b96557 51 #include "stm32f4xx_hal_rcc_ex.h"
Kojto 99:dbbf35b96557 52
bogdanm 89:552587b429a1 53 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 89:552587b429a1 54 * @{
bogdanm 89:552587b429a1 55 */
bogdanm 89:552587b429a1 56
Kojto 99:dbbf35b96557 57 /** @addtogroup RCC
bogdanm 89:552587b429a1 58 * @{
bogdanm 89:552587b429a1 59 */
bogdanm 89:552587b429a1 60
Kojto 99:dbbf35b96557 61 /* Exported types ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 62 /** @defgroup RCC_Exported_Types RCC Exported Types
Kojto 99:dbbf35b96557 63 * @{
bogdanm 89:552587b429a1 64 */
Kojto 99:dbbf35b96557 65
bogdanm 89:552587b429a1 66 /**
bogdanm 89:552587b429a1 67 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
bogdanm 89:552587b429a1 68 */
bogdanm 89:552587b429a1 69 typedef struct
bogdanm 89:552587b429a1 70 {
bogdanm 89:552587b429a1 71 uint32_t OscillatorType; /*!< The oscillators to be configured.
bogdanm 89:552587b429a1 72 This parameter can be a value of @ref RCC_Oscillator_Type */
bogdanm 89:552587b429a1 73
bogdanm 89:552587b429a1 74 uint32_t HSEState; /*!< The new state of the HSE.
bogdanm 89:552587b429a1 75 This parameter can be a value of @ref RCC_HSE_Config */
bogdanm 89:552587b429a1 76
bogdanm 89:552587b429a1 77 uint32_t LSEState; /*!< The new state of the LSE.
bogdanm 89:552587b429a1 78 This parameter can be a value of @ref RCC_LSE_Config */
Kojto 122:f9eeca106725 79
bogdanm 89:552587b429a1 80 uint32_t HSIState; /*!< The new state of the HSI.
bogdanm 89:552587b429a1 81 This parameter can be a value of @ref RCC_HSI_Config */
bogdanm 89:552587b429a1 82
Kojto 122:f9eeca106725 83 uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
Kojto 122:f9eeca106725 84 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
Kojto 122:f9eeca106725 85
bogdanm 89:552587b429a1 86 uint32_t LSIState; /*!< The new state of the LSI.
bogdanm 89:552587b429a1 87 This parameter can be a value of @ref RCC_LSI_Config */
bogdanm 89:552587b429a1 88
Kojto 122:f9eeca106725 89 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
bogdanm 89:552587b429a1 90 }RCC_OscInitTypeDef;
bogdanm 89:552587b429a1 91
bogdanm 89:552587b429a1 92 /**
bogdanm 89:552587b429a1 93 * @brief RCC System, AHB and APB busses clock configuration structure definition
bogdanm 89:552587b429a1 94 */
bogdanm 89:552587b429a1 95 typedef struct
bogdanm 89:552587b429a1 96 {
bogdanm 89:552587b429a1 97 uint32_t ClockType; /*!< The clock to be configured.
bogdanm 89:552587b429a1 98 This parameter can be a value of @ref RCC_System_Clock_Type */
bogdanm 89:552587b429a1 99
bogdanm 89:552587b429a1 100 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
bogdanm 89:552587b429a1 101 This parameter can be a value of @ref RCC_System_Clock_Source */
bogdanm 89:552587b429a1 102
bogdanm 89:552587b429a1 103 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
bogdanm 89:552587b429a1 104 This parameter can be a value of @ref RCC_AHB_Clock_Source */
bogdanm 89:552587b429a1 105
bogdanm 89:552587b429a1 106 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
bogdanm 89:552587b429a1 107 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
bogdanm 89:552587b429a1 108
bogdanm 89:552587b429a1 109 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
bogdanm 89:552587b429a1 110 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
bogdanm 89:552587b429a1 111
bogdanm 89:552587b429a1 112 }RCC_ClkInitTypeDef;
bogdanm 89:552587b429a1 113
bogdanm 89:552587b429a1 114 /**
bogdanm 89:552587b429a1 115 * @}
bogdanm 89:552587b429a1 116 */
bogdanm 89:552587b429a1 117
Kojto 99:dbbf35b96557 118 /* Exported constants --------------------------------------------------------*/
Kojto 99:dbbf35b96557 119 /** @defgroup RCC_Exported_Constants RCC Exported Constants
Kojto 99:dbbf35b96557 120 * @{
Kojto 99:dbbf35b96557 121 */
Kojto 99:dbbf35b96557 122
Kojto 99:dbbf35b96557 123 /** @defgroup RCC_Oscillator_Type Oscillator Type
bogdanm 89:552587b429a1 124 * @{
bogdanm 89:552587b429a1 125 */
AnnaBridge 145:64910690c574 126 #define RCC_OSCILLATORTYPE_NONE 0x00000000U
AnnaBridge 145:64910690c574 127 #define RCC_OSCILLATORTYPE_HSE 0x00000001U
AnnaBridge 145:64910690c574 128 #define RCC_OSCILLATORTYPE_HSI 0x00000002U
AnnaBridge 145:64910690c574 129 #define RCC_OSCILLATORTYPE_LSE 0x00000004U
AnnaBridge 145:64910690c574 130 #define RCC_OSCILLATORTYPE_LSI 0x00000008U
bogdanm 89:552587b429a1 131 /**
bogdanm 89:552587b429a1 132 * @}
bogdanm 89:552587b429a1 133 */
bogdanm 89:552587b429a1 134
Kojto 99:dbbf35b96557 135 /** @defgroup RCC_HSE_Config HSE Config
bogdanm 89:552587b429a1 136 * @{
bogdanm 89:552587b429a1 137 */
AnnaBridge 145:64910690c574 138 #define RCC_HSE_OFF 0x00000000U
AnnaBridge 145:64910690c574 139 #define RCC_HSE_ON RCC_CR_HSEON
AnnaBridge 145:64910690c574 140 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
bogdanm 89:552587b429a1 141 /**
bogdanm 89:552587b429a1 142 * @}
bogdanm 89:552587b429a1 143 */
bogdanm 89:552587b429a1 144
Kojto 99:dbbf35b96557 145 /** @defgroup RCC_LSE_Config LSE Config
bogdanm 89:552587b429a1 146 * @{
bogdanm 89:552587b429a1 147 */
AnnaBridge 145:64910690c574 148 #define RCC_LSE_OFF 0x00000000U
AnnaBridge 145:64910690c574 149 #define RCC_LSE_ON RCC_BDCR_LSEON
AnnaBridge 145:64910690c574 150 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
bogdanm 89:552587b429a1 151 /**
bogdanm 89:552587b429a1 152 * @}
bogdanm 89:552587b429a1 153 */
bogdanm 89:552587b429a1 154
Kojto 99:dbbf35b96557 155 /** @defgroup RCC_HSI_Config HSI Config
bogdanm 89:552587b429a1 156 * @{
bogdanm 89:552587b429a1 157 */
AnnaBridge 145:64910690c574 158 #define RCC_HSI_OFF ((uint8_t)0x00)
AnnaBridge 145:64910690c574 159 #define RCC_HSI_ON ((uint8_t)0x01)
Kojto 122:f9eeca106725 160
AnnaBridge 145:64910690c574 161 #define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */
bogdanm 89:552587b429a1 162 /**
bogdanm 89:552587b429a1 163 * @}
bogdanm 89:552587b429a1 164 */
bogdanm 89:552587b429a1 165
Kojto 99:dbbf35b96557 166 /** @defgroup RCC_LSI_Config LSI Config
bogdanm 89:552587b429a1 167 * @{
bogdanm 89:552587b429a1 168 */
AnnaBridge 145:64910690c574 169 #define RCC_LSI_OFF ((uint8_t)0x00)
AnnaBridge 145:64910690c574 170 #define RCC_LSI_ON ((uint8_t)0x01)
bogdanm 89:552587b429a1 171 /**
bogdanm 89:552587b429a1 172 * @}
bogdanm 89:552587b429a1 173 */
bogdanm 89:552587b429a1 174
Kojto 99:dbbf35b96557 175 /** @defgroup RCC_PLL_Config PLL Config
bogdanm 89:552587b429a1 176 * @{
bogdanm 89:552587b429a1 177 */
AnnaBridge 145:64910690c574 178 #define RCC_PLL_NONE ((uint8_t)0x00)
AnnaBridge 145:64910690c574 179 #define RCC_PLL_OFF ((uint8_t)0x01)
AnnaBridge 145:64910690c574 180 #define RCC_PLL_ON ((uint8_t)0x02)
bogdanm 89:552587b429a1 181 /**
bogdanm 89:552587b429a1 182 * @}
bogdanm 89:552587b429a1 183 */
bogdanm 89:552587b429a1 184
Kojto 99:dbbf35b96557 185 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
bogdanm 89:552587b429a1 186 * @{
bogdanm 89:552587b429a1 187 */
AnnaBridge 145:64910690c574 188 #define RCC_PLLP_DIV2 0x00000002U
AnnaBridge 145:64910690c574 189 #define RCC_PLLP_DIV4 0x00000004U
AnnaBridge 145:64910690c574 190 #define RCC_PLLP_DIV6 0x00000006U
AnnaBridge 145:64910690c574 191 #define RCC_PLLP_DIV8 0x00000008U
bogdanm 89:552587b429a1 192 /**
bogdanm 89:552587b429a1 193 * @}
bogdanm 89:552587b429a1 194 */
bogdanm 89:552587b429a1 195
Kojto 99:dbbf35b96557 196 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
bogdanm 89:552587b429a1 197 * @{
bogdanm 89:552587b429a1 198 */
bogdanm 89:552587b429a1 199 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
bogdanm 89:552587b429a1 200 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
bogdanm 89:552587b429a1 201 /**
bogdanm 89:552587b429a1 202 * @}
bogdanm 89:552587b429a1 203 */
bogdanm 89:552587b429a1 204
Kojto 99:dbbf35b96557 205 /** @defgroup RCC_System_Clock_Type System Clock Type
bogdanm 89:552587b429a1 206 * @{
bogdanm 89:552587b429a1 207 */
AnnaBridge 145:64910690c574 208 #define RCC_CLOCKTYPE_SYSCLK 0x00000001U
AnnaBridge 145:64910690c574 209 #define RCC_CLOCKTYPE_HCLK 0x00000002U
AnnaBridge 145:64910690c574 210 #define RCC_CLOCKTYPE_PCLK1 0x00000004U
AnnaBridge 145:64910690c574 211 #define RCC_CLOCKTYPE_PCLK2 0x00000008U
bogdanm 89:552587b429a1 212 /**
bogdanm 89:552587b429a1 213 * @}
bogdanm 89:552587b429a1 214 */
bogdanm 89:552587b429a1 215
Kojto 99:dbbf35b96557 216 /** @defgroup RCC_System_Clock_Source System Clock Source
AnnaBridge 145:64910690c574 217 * @note The RCC_SYSCLKSOURCE_PLLRCLK parameter is available only for
AnnaBridge 145:64910690c574 218 * STM32F446xx devices.
bogdanm 89:552587b429a1 219 * @{
bogdanm 89:552587b429a1 220 */
bogdanm 89:552587b429a1 221 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
bogdanm 89:552587b429a1 222 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
bogdanm 89:552587b429a1 223 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
Kojto 99:dbbf35b96557 224 #define RCC_SYSCLKSOURCE_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1))
bogdanm 89:552587b429a1 225 /**
bogdanm 89:552587b429a1 226 * @}
Kojto 99:dbbf35b96557 227 */
bogdanm 89:552587b429a1 228
Kojto 99:dbbf35b96557 229 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
AnnaBridge 145:64910690c574 230 * @note The RCC_SYSCLKSOURCE_STATUS_PLLRCLK parameter is available only for
AnnaBridge 145:64910690c574 231 * STM32F446xx devices.
Kojto 99:dbbf35b96557 232 * @{
Kojto 99:dbbf35b96557 233 */
Kojto 99:dbbf35b96557 234 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
Kojto 99:dbbf35b96557 235 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
Kojto 99:dbbf35b96557 236 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
Kojto 122:f9eeca106725 237 #define RCC_SYSCLKSOURCE_STATUS_PLLRCLK ((uint32_t)(RCC_CFGR_SWS_0 | RCC_CFGR_SWS_1)) /*!< PLLR used as system clock */
Kojto 99:dbbf35b96557 238 /**
Kojto 99:dbbf35b96557 239 * @}
Kojto 99:dbbf35b96557 240 */
Kojto 99:dbbf35b96557 241
Kojto 99:dbbf35b96557 242 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source
bogdanm 89:552587b429a1 243 * @{
bogdanm 89:552587b429a1 244 */
bogdanm 89:552587b429a1 245 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
bogdanm 89:552587b429a1 246 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
bogdanm 89:552587b429a1 247 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
bogdanm 89:552587b429a1 248 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
bogdanm 89:552587b429a1 249 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
bogdanm 89:552587b429a1 250 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
bogdanm 89:552587b429a1 251 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
bogdanm 89:552587b429a1 252 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
bogdanm 89:552587b429a1 253 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
bogdanm 89:552587b429a1 254 /**
bogdanm 89:552587b429a1 255 * @}
bogdanm 89:552587b429a1 256 */
bogdanm 89:552587b429a1 257
Kojto 99:dbbf35b96557 258 /** @defgroup RCC_APB1_APB2_Clock_Source APB1/APB2 Clock Source
bogdanm 89:552587b429a1 259 * @{
bogdanm 89:552587b429a1 260 */
bogdanm 89:552587b429a1 261 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
bogdanm 89:552587b429a1 262 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
bogdanm 89:552587b429a1 263 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
bogdanm 89:552587b429a1 264 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
bogdanm 89:552587b429a1 265 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
bogdanm 89:552587b429a1 266 /**
bogdanm 89:552587b429a1 267 * @}
bogdanm 89:552587b429a1 268 */
bogdanm 89:552587b429a1 269
Kojto 99:dbbf35b96557 270 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source
bogdanm 89:552587b429a1 271 * @{
bogdanm 89:552587b429a1 272 */
AnnaBridge 145:64910690c574 273 #define RCC_RTCCLKSOURCE_LSE 0x00000100U
AnnaBridge 145:64910690c574 274 #define RCC_RTCCLKSOURCE_LSI 0x00000200U
AnnaBridge 145:64910690c574 275 #define RCC_RTCCLKSOURCE_HSE_DIV2 0x00020300U
AnnaBridge 145:64910690c574 276 #define RCC_RTCCLKSOURCE_HSE_DIV3 0x00030300U
AnnaBridge 145:64910690c574 277 #define RCC_RTCCLKSOURCE_HSE_DIV4 0x00040300U
AnnaBridge 145:64910690c574 278 #define RCC_RTCCLKSOURCE_HSE_DIV5 0x00050300U
AnnaBridge 145:64910690c574 279 #define RCC_RTCCLKSOURCE_HSE_DIV6 0x00060300U
AnnaBridge 145:64910690c574 280 #define RCC_RTCCLKSOURCE_HSE_DIV7 0x00070300U
AnnaBridge 145:64910690c574 281 #define RCC_RTCCLKSOURCE_HSE_DIV8 0x00080300U
AnnaBridge 145:64910690c574 282 #define RCC_RTCCLKSOURCE_HSE_DIV9 0x00090300U
AnnaBridge 145:64910690c574 283 #define RCC_RTCCLKSOURCE_HSE_DIV10 0x000A0300U
AnnaBridge 145:64910690c574 284 #define RCC_RTCCLKSOURCE_HSE_DIV11 0x000B0300U
AnnaBridge 145:64910690c574 285 #define RCC_RTCCLKSOURCE_HSE_DIV12 0x000C0300U
AnnaBridge 145:64910690c574 286 #define RCC_RTCCLKSOURCE_HSE_DIV13 0x000D0300U
AnnaBridge 145:64910690c574 287 #define RCC_RTCCLKSOURCE_HSE_DIV14 0x000E0300U
AnnaBridge 145:64910690c574 288 #define RCC_RTCCLKSOURCE_HSE_DIV15 0x000F0300U
AnnaBridge 145:64910690c574 289 #define RCC_RTCCLKSOURCE_HSE_DIV16 0x00100300U
AnnaBridge 145:64910690c574 290 #define RCC_RTCCLKSOURCE_HSE_DIV17 0x00110300U
AnnaBridge 145:64910690c574 291 #define RCC_RTCCLKSOURCE_HSE_DIV18 0x00120300U
AnnaBridge 145:64910690c574 292 #define RCC_RTCCLKSOURCE_HSE_DIV19 0x00130300U
AnnaBridge 145:64910690c574 293 #define RCC_RTCCLKSOURCE_HSE_DIV20 0x00140300U
AnnaBridge 145:64910690c574 294 #define RCC_RTCCLKSOURCE_HSE_DIV21 0x00150300U
AnnaBridge 145:64910690c574 295 #define RCC_RTCCLKSOURCE_HSE_DIV22 0x00160300U
AnnaBridge 145:64910690c574 296 #define RCC_RTCCLKSOURCE_HSE_DIV23 0x00170300U
AnnaBridge 145:64910690c574 297 #define RCC_RTCCLKSOURCE_HSE_DIV24 0x00180300U
AnnaBridge 145:64910690c574 298 #define RCC_RTCCLKSOURCE_HSE_DIV25 0x00190300U
AnnaBridge 145:64910690c574 299 #define RCC_RTCCLKSOURCE_HSE_DIV26 0x001A0300U
AnnaBridge 145:64910690c574 300 #define RCC_RTCCLKSOURCE_HSE_DIV27 0x001B0300U
AnnaBridge 145:64910690c574 301 #define RCC_RTCCLKSOURCE_HSE_DIV28 0x001C0300U
AnnaBridge 145:64910690c574 302 #define RCC_RTCCLKSOURCE_HSE_DIV29 0x001D0300U
AnnaBridge 145:64910690c574 303 #define RCC_RTCCLKSOURCE_HSE_DIV30 0x001E0300U
AnnaBridge 145:64910690c574 304 #define RCC_RTCCLKSOURCE_HSE_DIV31 0x001F0300U
bogdanm 89:552587b429a1 305 /**
bogdanm 89:552587b429a1 306 * @}
bogdanm 89:552587b429a1 307 */
bogdanm 89:552587b429a1 308
Kojto 99:dbbf35b96557 309 /** @defgroup RCC_MCO_Index MCO Index
bogdanm 89:552587b429a1 310 * @{
bogdanm 89:552587b429a1 311 */
AnnaBridge 145:64910690c574 312 #define RCC_MCO1 0x00000000U
AnnaBridge 145:64910690c574 313 #define RCC_MCO2 0x00000001U
bogdanm 89:552587b429a1 314 /**
bogdanm 89:552587b429a1 315 * @}
bogdanm 89:552587b429a1 316 */
bogdanm 89:552587b429a1 317
Kojto 99:dbbf35b96557 318 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
bogdanm 89:552587b429a1 319 * @{
bogdanm 89:552587b429a1 320 */
AnnaBridge 145:64910690c574 321 #define RCC_MCO1SOURCE_HSI 0x00000000U
bogdanm 89:552587b429a1 322 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
bogdanm 89:552587b429a1 323 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
bogdanm 89:552587b429a1 324 #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
bogdanm 89:552587b429a1 325 /**
bogdanm 89:552587b429a1 326 * @}
bogdanm 89:552587b429a1 327 */
bogdanm 89:552587b429a1 328
Kojto 99:dbbf35b96557 329 /** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler
bogdanm 89:552587b429a1 330 * @{
bogdanm 89:552587b429a1 331 */
AnnaBridge 145:64910690c574 332 #define RCC_MCODIV_1 0x00000000U
bogdanm 89:552587b429a1 333 #define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
bogdanm 89:552587b429a1 334 #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
bogdanm 89:552587b429a1 335 #define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
bogdanm 89:552587b429a1 336 #define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
bogdanm 89:552587b429a1 337 /**
bogdanm 89:552587b429a1 338 * @}
bogdanm 89:552587b429a1 339 */
bogdanm 89:552587b429a1 340
Kojto 99:dbbf35b96557 341 /** @defgroup RCC_Interrupt Interrupts
bogdanm 89:552587b429a1 342 * @{
bogdanm 89:552587b429a1 343 */
AnnaBridge 145:64910690c574 344 #define RCC_IT_LSIRDY ((uint8_t)0x01)
AnnaBridge 145:64910690c574 345 #define RCC_IT_LSERDY ((uint8_t)0x02)
AnnaBridge 145:64910690c574 346 #define RCC_IT_HSIRDY ((uint8_t)0x04)
AnnaBridge 145:64910690c574 347 #define RCC_IT_HSERDY ((uint8_t)0x08)
AnnaBridge 145:64910690c574 348 #define RCC_IT_PLLRDY ((uint8_t)0x10)
AnnaBridge 145:64910690c574 349 #define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
AnnaBridge 145:64910690c574 350 #define RCC_IT_CSS ((uint8_t)0x80)
bogdanm 89:552587b429a1 351 /**
bogdanm 89:552587b429a1 352 * @}
bogdanm 89:552587b429a1 353 */
bogdanm 89:552587b429a1 354
Kojto 99:dbbf35b96557 355 /** @defgroup RCC_Flag Flags
bogdanm 89:552587b429a1 356 * Elements values convention: 0XXYYYYYb
bogdanm 89:552587b429a1 357 * - YYYYY : Flag position in the register
bogdanm 89:552587b429a1 358 * - 0XX : Register index
bogdanm 89:552587b429a1 359 * - 01: CR register
bogdanm 89:552587b429a1 360 * - 10: BDCR register
bogdanm 89:552587b429a1 361 * - 11: CSR register
bogdanm 89:552587b429a1 362 * @{
bogdanm 89:552587b429a1 363 */
bogdanm 89:552587b429a1 364 /* Flags in the CR register */
AnnaBridge 145:64910690c574 365 #define RCC_FLAG_HSIRDY ((uint8_t)0x21)
AnnaBridge 145:64910690c574 366 #define RCC_FLAG_HSERDY ((uint8_t)0x31)
AnnaBridge 145:64910690c574 367 #define RCC_FLAG_PLLRDY ((uint8_t)0x39)
AnnaBridge 145:64910690c574 368 #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
bogdanm 89:552587b429a1 369
bogdanm 89:552587b429a1 370 /* Flags in the BDCR register */
AnnaBridge 145:64910690c574 371 #define RCC_FLAG_LSERDY ((uint8_t)0x41)
bogdanm 89:552587b429a1 372
bogdanm 89:552587b429a1 373 /* Flags in the CSR register */
AnnaBridge 145:64910690c574 374 #define RCC_FLAG_LSIRDY ((uint8_t)0x61)
AnnaBridge 145:64910690c574 375 #define RCC_FLAG_BORRST ((uint8_t)0x79)
AnnaBridge 145:64910690c574 376 #define RCC_FLAG_PINRST ((uint8_t)0x7A)
AnnaBridge 145:64910690c574 377 #define RCC_FLAG_PORRST ((uint8_t)0x7B)
AnnaBridge 145:64910690c574 378 #define RCC_FLAG_SFTRST ((uint8_t)0x7C)
AnnaBridge 145:64910690c574 379 #define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
AnnaBridge 145:64910690c574 380 #define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
AnnaBridge 145:64910690c574 381 #define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
bogdanm 89:552587b429a1 382 /**
bogdanm 89:552587b429a1 383 * @}
bogdanm 89:552587b429a1 384 */
bogdanm 89:552587b429a1 385
bogdanm 89:552587b429a1 386 /**
bogdanm 89:552587b429a1 387 * @}
Kojto 99:dbbf35b96557 388 */
Kojto 99:dbbf35b96557 389
bogdanm 89:552587b429a1 390 /* Exported macro ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 391 /** @defgroup RCC_Exported_Macros RCC Exported Macros
Kojto 99:dbbf35b96557 392 * @{
Kojto 99:dbbf35b96557 393 */
bogdanm 89:552587b429a1 394
Kojto 99:dbbf35b96557 395 /** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
Kojto 99:dbbf35b96557 396 * @brief Enable or disable the AHB1 peripheral clock.
bogdanm 89:552587b429a1 397 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 89:552587b429a1 398 * is disabled and the application software has to enable this clock before
bogdanm 89:552587b429a1 399 * using it.
Kojto 99:dbbf35b96557 400 * @{
bogdanm 89:552587b429a1 401 */
Kojto 122:f9eeca106725 402 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 403 __IO uint32_t tmpreg = 0x00U; \
Kojto 99:dbbf35b96557 404 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
Kojto 99:dbbf35b96557 405 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 406 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
Kojto 99:dbbf35b96557 407 UNUSED(tmpreg); \
AnnaBridge 145:64910690c574 408 } while(0U)
Kojto 122:f9eeca106725 409 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 410 __IO uint32_t tmpreg = 0x00U; \
Kojto 99:dbbf35b96557 411 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
Kojto 99:dbbf35b96557 412 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 413 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
Kojto 99:dbbf35b96557 414 UNUSED(tmpreg); \
AnnaBridge 145:64910690c574 415 } while(0U)
Kojto 122:f9eeca106725 416 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 417 __IO uint32_t tmpreg = 0x00U; \
Kojto 99:dbbf35b96557 418 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
Kojto 99:dbbf35b96557 419 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 420 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
Kojto 99:dbbf35b96557 421 UNUSED(tmpreg); \
AnnaBridge 145:64910690c574 422 } while(0U)
Kojto 122:f9eeca106725 423 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 424 __IO uint32_t tmpreg = 0x00U; \
Kojto 99:dbbf35b96557 425 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
Kojto 99:dbbf35b96557 426 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 427 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
Kojto 99:dbbf35b96557 428 UNUSED(tmpreg); \
AnnaBridge 145:64910690c574 429 } while(0U)
Kojto 122:f9eeca106725 430 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 431 __IO uint32_t tmpreg = 0x00U; \
Kojto 99:dbbf35b96557 432 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
Kojto 99:dbbf35b96557 433 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 434 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
Kojto 99:dbbf35b96557 435 UNUSED(tmpreg); \
AnnaBridge 145:64910690c574 436 } while(0U)
Kojto 99:dbbf35b96557 437 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 438 __IO uint32_t tmpreg = 0x00U; \
Kojto 99:dbbf35b96557 439 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
Kojto 99:dbbf35b96557 440 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 441 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
Kojto 99:dbbf35b96557 442 UNUSED(tmpreg); \
AnnaBridge 145:64910690c574 443 } while(0U)
bogdanm 89:552587b429a1 444
Kojto 99:dbbf35b96557 445 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
Kojto 99:dbbf35b96557 446 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
Kojto 99:dbbf35b96557 447 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
Kojto 99:dbbf35b96557 448 #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
Kojto 99:dbbf35b96557 449 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
Kojto 99:dbbf35b96557 450 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
Kojto 99:dbbf35b96557 451 /**
Kojto 99:dbbf35b96557 452 * @}
Kojto 99:dbbf35b96557 453 */
Kojto 99:dbbf35b96557 454
Kojto 122:f9eeca106725 455 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
Kojto 122:f9eeca106725 456 * @brief Get the enable or disable status of the AHB1 peripheral clock.
Kojto 122:f9eeca106725 457 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 122:f9eeca106725 458 * is disabled and the application software has to enable this clock before
Kojto 122:f9eeca106725 459 * using it.
Kojto 122:f9eeca106725 460 * @{
Kojto 122:f9eeca106725 461 */
Kojto 122:f9eeca106725 462 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) != RESET)
Kojto 122:f9eeca106725 463 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) != RESET)
Kojto 122:f9eeca106725 464 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) != RESET)
Kojto 122:f9eeca106725 465 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) != RESET)
Kojto 122:f9eeca106725 466 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) != RESET)
Kojto 122:f9eeca106725 467 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) != RESET)
Kojto 122:f9eeca106725 468
Kojto 122:f9eeca106725 469 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) == RESET)
Kojto 122:f9eeca106725 470 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) == RESET)
Kojto 122:f9eeca106725 471 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) == RESET)
Kojto 122:f9eeca106725 472 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) == RESET)
Kojto 122:f9eeca106725 473 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) == RESET)
Kojto 122:f9eeca106725 474 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) == RESET)
Kojto 122:f9eeca106725 475 /**
Kojto 122:f9eeca106725 476 * @}
Kojto 122:f9eeca106725 477 */
Kojto 122:f9eeca106725 478
Kojto 99:dbbf35b96557 479 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
Kojto 99:dbbf35b96557 480 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
bogdanm 89:552587b429a1 481 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 89:552587b429a1 482 * is disabled and the application software has to enable this clock before
bogdanm 89:552587b429a1 483 * using it.
Kojto 99:dbbf35b96557 484 * @{
bogdanm 89:552587b429a1 485 */
Kojto 99:dbbf35b96557 486 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 487 __IO uint32_t tmpreg = 0x00U; \
Kojto 99:dbbf35b96557 488 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
Kojto 99:dbbf35b96557 489 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 490 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
Kojto 99:dbbf35b96557 491 UNUSED(tmpreg); \
AnnaBridge 145:64910690c574 492 } while(0U)
Kojto 99:dbbf35b96557 493 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 494 __IO uint32_t tmpreg = 0x00U; \
Kojto 99:dbbf35b96557 495 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
Kojto 99:dbbf35b96557 496 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 497 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
Kojto 99:dbbf35b96557 498 UNUSED(tmpreg); \
AnnaBridge 145:64910690c574 499 } while(0U)
Kojto 99:dbbf35b96557 500 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 501 __IO uint32_t tmpreg = 0x00U; \
Kojto 99:dbbf35b96557 502 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
Kojto 99:dbbf35b96557 503 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 504 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
Kojto 99:dbbf35b96557 505 UNUSED(tmpreg); \
AnnaBridge 145:64910690c574 506 } while(0U)
Kojto 99:dbbf35b96557 507 #define __HAL_RCC_USART2_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 508 __IO uint32_t tmpreg = 0x00U; \
Kojto 99:dbbf35b96557 509 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
Kojto 99:dbbf35b96557 510 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 511 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
Kojto 99:dbbf35b96557 512 UNUSED(tmpreg); \
AnnaBridge 145:64910690c574 513 } while(0U)
Kojto 99:dbbf35b96557 514 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 515 __IO uint32_t tmpreg = 0x00U; \
Kojto 99:dbbf35b96557 516 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
Kojto 99:dbbf35b96557 517 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 518 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
Kojto 99:dbbf35b96557 519 UNUSED(tmpreg); \
AnnaBridge 145:64910690c574 520 } while(0U)
Kojto 99:dbbf35b96557 521 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 522 __IO uint32_t tmpreg = 0x00U; \
Kojto 99:dbbf35b96557 523 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
Kojto 99:dbbf35b96557 524 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 525 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
Kojto 99:dbbf35b96557 526 UNUSED(tmpreg); \
AnnaBridge 145:64910690c574 527 } while(0U)
Kojto 99:dbbf35b96557 528 #define __HAL_RCC_PWR_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 529 __IO uint32_t tmpreg = 0x00U; \
Kojto 99:dbbf35b96557 530 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
Kojto 99:dbbf35b96557 531 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 532 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
Kojto 99:dbbf35b96557 533 UNUSED(tmpreg); \
AnnaBridge 145:64910690c574 534 } while(0U)
Kojto 110:165afa46840b 535
Kojto 99:dbbf35b96557 536 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
Kojto 99:dbbf35b96557 537 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
Kojto 99:dbbf35b96557 538 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
Kojto 99:dbbf35b96557 539 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
Kojto 99:dbbf35b96557 540 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
Kojto 99:dbbf35b96557 541 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
Kojto 99:dbbf35b96557 542 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
Kojto 99:dbbf35b96557 543 /**
Kojto 99:dbbf35b96557 544 * @}
Kojto 99:dbbf35b96557 545 */
bogdanm 89:552587b429a1 546
Kojto 122:f9eeca106725 547 /** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
Kojto 122:f9eeca106725 548 * @brief Get the enable or disable status of the APB1 peripheral clock.
Kojto 122:f9eeca106725 549 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 122:f9eeca106725 550 * is disabled and the application software has to enable this clock before
Kojto 122:f9eeca106725 551 * using it.
Kojto 122:f9eeca106725 552 * @{
Kojto 122:f9eeca106725 553 */
Kojto 122:f9eeca106725 554 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
Kojto 122:f9eeca106725 555 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
Kojto 122:f9eeca106725 556 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
Kojto 122:f9eeca106725 557 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
Kojto 122:f9eeca106725 558 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
Kojto 122:f9eeca106725 559 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
Kojto 122:f9eeca106725 560 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
Kojto 122:f9eeca106725 561
Kojto 122:f9eeca106725 562 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
Kojto 122:f9eeca106725 563 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
Kojto 122:f9eeca106725 564 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
Kojto 122:f9eeca106725 565 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
Kojto 122:f9eeca106725 566 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
Kojto 122:f9eeca106725 567 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
Kojto 122:f9eeca106725 568 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
Kojto 122:f9eeca106725 569 /**
Kojto 122:f9eeca106725 570 * @}
Kojto 122:f9eeca106725 571 */
Kojto 122:f9eeca106725 572
Kojto 122:f9eeca106725 573 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
Kojto 99:dbbf35b96557 574 * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
bogdanm 89:552587b429a1 575 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 89:552587b429a1 576 * is disabled and the application software has to enable this clock before
bogdanm 89:552587b429a1 577 * using it.
Kojto 99:dbbf35b96557 578 * @{
bogdanm 89:552587b429a1 579 */
Kojto 99:dbbf35b96557 580 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 581 __IO uint32_t tmpreg = 0x00U; \
Kojto 99:dbbf35b96557 582 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
Kojto 99:dbbf35b96557 583 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 584 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
Kojto 99:dbbf35b96557 585 UNUSED(tmpreg); \
AnnaBridge 145:64910690c574 586 } while(0U)
Kojto 99:dbbf35b96557 587 #define __HAL_RCC_USART1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 588 __IO uint32_t tmpreg = 0x00U; \
Kojto 99:dbbf35b96557 589 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
Kojto 99:dbbf35b96557 590 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 591 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
Kojto 99:dbbf35b96557 592 UNUSED(tmpreg); \
AnnaBridge 145:64910690c574 593 } while(0U)
Kojto 99:dbbf35b96557 594 #define __HAL_RCC_USART6_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 595 __IO uint32_t tmpreg = 0x00U; \
Kojto 99:dbbf35b96557 596 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
Kojto 99:dbbf35b96557 597 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 598 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
Kojto 99:dbbf35b96557 599 UNUSED(tmpreg); \
AnnaBridge 145:64910690c574 600 } while(0U)
Kojto 99:dbbf35b96557 601 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 602 __IO uint32_t tmpreg = 0x00U; \
Kojto 99:dbbf35b96557 603 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
Kojto 99:dbbf35b96557 604 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 605 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
Kojto 99:dbbf35b96557 606 UNUSED(tmpreg); \
AnnaBridge 145:64910690c574 607 } while(0U)
Kojto 99:dbbf35b96557 608 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 609 __IO uint32_t tmpreg = 0x00U; \
Kojto 99:dbbf35b96557 610 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
Kojto 99:dbbf35b96557 611 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 612 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
Kojto 99:dbbf35b96557 613 UNUSED(tmpreg); \
AnnaBridge 145:64910690c574 614 } while(0U)
Kojto 99:dbbf35b96557 615 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 616 __IO uint32_t tmpreg = 0x00U; \
Kojto 99:dbbf35b96557 617 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
Kojto 99:dbbf35b96557 618 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 619 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
Kojto 99:dbbf35b96557 620 UNUSED(tmpreg); \
AnnaBridge 145:64910690c574 621 } while(0U)
Kojto 99:dbbf35b96557 622 #define __HAL_RCC_TIM9_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 623 __IO uint32_t tmpreg = 0x00U; \
Kojto 99:dbbf35b96557 624 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
Kojto 99:dbbf35b96557 625 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 626 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
Kojto 99:dbbf35b96557 627 UNUSED(tmpreg); \
AnnaBridge 145:64910690c574 628 } while(0U)
Kojto 99:dbbf35b96557 629 #define __HAL_RCC_TIM11_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 630 __IO uint32_t tmpreg = 0x00U; \
Kojto 99:dbbf35b96557 631 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
Kojto 99:dbbf35b96557 632 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 633 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
Kojto 99:dbbf35b96557 634 UNUSED(tmpreg); \
AnnaBridge 145:64910690c574 635 } while(0U)
bogdanm 89:552587b429a1 636
Kojto 99:dbbf35b96557 637 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
Kojto 99:dbbf35b96557 638 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
Kojto 99:dbbf35b96557 639 #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
Kojto 99:dbbf35b96557 640 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
Kojto 99:dbbf35b96557 641 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
Kojto 99:dbbf35b96557 642 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
Kojto 99:dbbf35b96557 643 #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
Kojto 99:dbbf35b96557 644 #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
Kojto 99:dbbf35b96557 645 /**
Kojto 99:dbbf35b96557 646 * @}
Kojto 99:dbbf35b96557 647 */
bogdanm 89:552587b429a1 648
Kojto 122:f9eeca106725 649 /** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
Kojto 122:f9eeca106725 650 * @brief Get the enable or disable status of the APB2 peripheral clock.
Kojto 122:f9eeca106725 651 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 122:f9eeca106725 652 * is disabled and the application software has to enable this clock before
Kojto 122:f9eeca106725 653 * using it.
Kojto 122:f9eeca106725 654 * @{
Kojto 122:f9eeca106725 655 */
Kojto 122:f9eeca106725 656 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
Kojto 122:f9eeca106725 657 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
Kojto 122:f9eeca106725 658 #define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
Kojto 122:f9eeca106725 659 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
Kojto 122:f9eeca106725 660 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
Kojto 122:f9eeca106725 661 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
Kojto 122:f9eeca106725 662 #define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
Kojto 122:f9eeca106725 663 #define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
Kojto 122:f9eeca106725 664
Kojto 122:f9eeca106725 665 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
Kojto 122:f9eeca106725 666 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
Kojto 122:f9eeca106725 667 #define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
Kojto 122:f9eeca106725 668 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
Kojto 122:f9eeca106725 669 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
Kojto 122:f9eeca106725 670 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
Kojto 122:f9eeca106725 671 #define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
Kojto 122:f9eeca106725 672 #define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
Kojto 122:f9eeca106725 673 /**
Kojto 122:f9eeca106725 674 * @}
Kojto 122:f9eeca106725 675 */
Kojto 122:f9eeca106725 676
Kojto 99:dbbf35b96557 677 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset
Kojto 99:dbbf35b96557 678 * @brief Force or release AHB1 peripheral reset.
Kojto 99:dbbf35b96557 679 * @{
bogdanm 89:552587b429a1 680 */
Kojto 122:f9eeca106725 681 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)
Kojto 99:dbbf35b96557 682 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
Kojto 99:dbbf35b96557 683 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
Kojto 99:dbbf35b96557 684 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
Kojto 99:dbbf35b96557 685 #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
Kojto 99:dbbf35b96557 686 #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
Kojto 99:dbbf35b96557 687 #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
bogdanm 89:552587b429a1 688
Kojto 122:f9eeca106725 689 #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)
Kojto 99:dbbf35b96557 690 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
Kojto 99:dbbf35b96557 691 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
Kojto 99:dbbf35b96557 692 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
Kojto 99:dbbf35b96557 693 #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
Kojto 99:dbbf35b96557 694 #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
Kojto 99:dbbf35b96557 695 #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
Kojto 99:dbbf35b96557 696 /**
Kojto 99:dbbf35b96557 697 * @}
Kojto 99:dbbf35b96557 698 */
bogdanm 89:552587b429a1 699
Kojto 99:dbbf35b96557 700 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
Kojto 99:dbbf35b96557 701 * @brief Force or release APB1 peripheral reset.
Kojto 99:dbbf35b96557 702 * @{
Kojto 99:dbbf35b96557 703 */
Kojto 122:f9eeca106725 704 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
Kojto 99:dbbf35b96557 705 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
Kojto 99:dbbf35b96557 706 #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
Kojto 99:dbbf35b96557 707 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
Kojto 99:dbbf35b96557 708 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
Kojto 99:dbbf35b96557 709 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
Kojto 99:dbbf35b96557 710 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
Kojto 99:dbbf35b96557 711 #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
bogdanm 89:552587b429a1 712
Kojto 122:f9eeca106725 713 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U)
Kojto 99:dbbf35b96557 714 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
Kojto 99:dbbf35b96557 715 #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
Kojto 99:dbbf35b96557 716 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
Kojto 99:dbbf35b96557 717 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
Kojto 99:dbbf35b96557 718 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
Kojto 99:dbbf35b96557 719 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
Kojto 99:dbbf35b96557 720 #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
Kojto 99:dbbf35b96557 721 /**
Kojto 99:dbbf35b96557 722 * @}
Kojto 99:dbbf35b96557 723 */
bogdanm 89:552587b429a1 724
Kojto 99:dbbf35b96557 725 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
Kojto 99:dbbf35b96557 726 * @brief Force or release APB2 peripheral reset.
Kojto 99:dbbf35b96557 727 * @{
bogdanm 89:552587b429a1 728 */
Kojto 122:f9eeca106725 729 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
Kojto 99:dbbf35b96557 730 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
Kojto 99:dbbf35b96557 731 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
Kojto 99:dbbf35b96557 732 #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
Kojto 99:dbbf35b96557 733 #define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
Kojto 99:dbbf35b96557 734 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
Kojto 99:dbbf35b96557 735 #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
Kojto 99:dbbf35b96557 736 #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
Kojto 99:dbbf35b96557 737 #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
bogdanm 89:552587b429a1 738
Kojto 122:f9eeca106725 739 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)
Kojto 99:dbbf35b96557 740 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
Kojto 99:dbbf35b96557 741 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
Kojto 99:dbbf35b96557 742 #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
Kojto 99:dbbf35b96557 743 #define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
Kojto 99:dbbf35b96557 744 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
Kojto 99:dbbf35b96557 745 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
Kojto 99:dbbf35b96557 746 #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
Kojto 99:dbbf35b96557 747 #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
Kojto 99:dbbf35b96557 748 /**
Kojto 99:dbbf35b96557 749 * @}
Kojto 99:dbbf35b96557 750 */
bogdanm 89:552587b429a1 751
Kojto 99:dbbf35b96557 752 /** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
Kojto 99:dbbf35b96557 753 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
bogdanm 89:552587b429a1 754 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm 89:552587b429a1 755 * power consumption.
Kojto 99:dbbf35b96557 756 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
bogdanm 89:552587b429a1 757 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 99:dbbf35b96557 758 * @{
bogdanm 89:552587b429a1 759 */
Kojto 99:dbbf35b96557 760 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
Kojto 99:dbbf35b96557 761 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
Kojto 99:dbbf35b96557 762 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
Kojto 99:dbbf35b96557 763 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
Kojto 99:dbbf35b96557 764 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
Kojto 99:dbbf35b96557 765 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
bogdanm 89:552587b429a1 766
Kojto 99:dbbf35b96557 767 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
Kojto 99:dbbf35b96557 768 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
Kojto 99:dbbf35b96557 769 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
Kojto 99:dbbf35b96557 770 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
Kojto 99:dbbf35b96557 771 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
Kojto 99:dbbf35b96557 772 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
Kojto 99:dbbf35b96557 773 /**
Kojto 99:dbbf35b96557 774 * @}
Kojto 99:dbbf35b96557 775 */
bogdanm 89:552587b429a1 776
Kojto 99:dbbf35b96557 777 /** @defgroup RCC_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
Kojto 99:dbbf35b96557 778 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
bogdanm 89:552587b429a1 779 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm 89:552587b429a1 780 * power consumption.
Kojto 99:dbbf35b96557 781 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
bogdanm 89:552587b429a1 782 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 99:dbbf35b96557 783 * @{
bogdanm 89:552587b429a1 784 */
Kojto 99:dbbf35b96557 785 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
Kojto 99:dbbf35b96557 786 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
Kojto 99:dbbf35b96557 787 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
Kojto 99:dbbf35b96557 788 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
Kojto 99:dbbf35b96557 789 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
Kojto 99:dbbf35b96557 790 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
Kojto 99:dbbf35b96557 791 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
bogdanm 89:552587b429a1 792
Kojto 99:dbbf35b96557 793 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
Kojto 99:dbbf35b96557 794 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
Kojto 99:dbbf35b96557 795 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
Kojto 99:dbbf35b96557 796 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
Kojto 99:dbbf35b96557 797 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
Kojto 99:dbbf35b96557 798 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
Kojto 99:dbbf35b96557 799 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
Kojto 99:dbbf35b96557 800 /**
Kojto 99:dbbf35b96557 801 * @}
Kojto 99:dbbf35b96557 802 */
bogdanm 89:552587b429a1 803
Kojto 99:dbbf35b96557 804 /** @defgroup RCC_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
Kojto 99:dbbf35b96557 805 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
bogdanm 89:552587b429a1 806 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm 89:552587b429a1 807 * power consumption.
Kojto 99:dbbf35b96557 808 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
bogdanm 89:552587b429a1 809 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 99:dbbf35b96557 810 * @{
bogdanm 89:552587b429a1 811 */
Kojto 99:dbbf35b96557 812 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
Kojto 99:dbbf35b96557 813 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
Kojto 99:dbbf35b96557 814 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
Kojto 99:dbbf35b96557 815 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
Kojto 99:dbbf35b96557 816 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
Kojto 99:dbbf35b96557 817 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
Kojto 99:dbbf35b96557 818 #define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
Kojto 99:dbbf35b96557 819 #define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
bogdanm 89:552587b429a1 820
Kojto 99:dbbf35b96557 821 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
Kojto 99:dbbf35b96557 822 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
Kojto 99:dbbf35b96557 823 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
Kojto 99:dbbf35b96557 824 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
Kojto 99:dbbf35b96557 825 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
Kojto 99:dbbf35b96557 826 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
Kojto 99:dbbf35b96557 827 #define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
Kojto 99:dbbf35b96557 828 #define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
Kojto 99:dbbf35b96557 829 /**
Kojto 99:dbbf35b96557 830 * @}
Kojto 99:dbbf35b96557 831 */
bogdanm 89:552587b429a1 832
Kojto 99:dbbf35b96557 833 /** @defgroup RCC_HSI_Configuration HSI Configuration
Kojto 99:dbbf35b96557 834 * @{
Kojto 99:dbbf35b96557 835 */
Kojto 99:dbbf35b96557 836
bogdanm 89:552587b429a1 837 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
bogdanm 89:552587b429a1 838 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
bogdanm 89:552587b429a1 839 * It is used (enabled by hardware) as system clock source after startup
Kojto 99:dbbf35b96557 840 * from Reset, wake-up from STOP and STANDBY mode, or in case of failure
bogdanm 89:552587b429a1 841 * of the HSE used directly or indirectly as system clock (if the Clock
bogdanm 89:552587b429a1 842 * Security System CSS is enabled).
bogdanm 89:552587b429a1 843 * @note HSI can not be stopped if it is used as system clock source. In this case,
bogdanm 89:552587b429a1 844 * you have to select another source of the system clock then stop the HSI.
bogdanm 89:552587b429a1 845 * @note After enabling the HSI, the application software should wait on HSIRDY
bogdanm 89:552587b429a1 846 * flag to be set indicating that HSI clock is stable and can be used as
bogdanm 89:552587b429a1 847 * system clock source.
bogdanm 89:552587b429a1 848 * This parameter can be: ENABLE or DISABLE.
bogdanm 89:552587b429a1 849 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
bogdanm 89:552587b429a1 850 * clock cycles.
bogdanm 89:552587b429a1 851 */
Kojto 99:dbbf35b96557 852 #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
Kojto 99:dbbf35b96557 853 #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
bogdanm 89:552587b429a1 854
bogdanm 89:552587b429a1 855 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
bogdanm 89:552587b429a1 856 * @note The calibration is used to compensate for the variations in voltage
bogdanm 89:552587b429a1 857 * and temperature that influence the frequency of the internal HSI RC.
bogdanm 89:552587b429a1 858 * @param __HSICalibrationValue__: specifies the calibration trimming value.
Kojto 122:f9eeca106725 859 * (default is RCC_HSICALIBRATION_DEFAULT).
bogdanm 89:552587b429a1 860 * This parameter must be a number between 0 and 0x1F.
bogdanm 89:552587b429a1 861 */
bogdanm 89:552587b429a1 862 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
bogdanm 89:552587b429a1 863 RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM)))
Kojto 99:dbbf35b96557 864 /**
Kojto 99:dbbf35b96557 865 * @}
Kojto 99:dbbf35b96557 866 */
Kojto 99:dbbf35b96557 867
Kojto 99:dbbf35b96557 868 /** @defgroup RCC_LSI_Configuration LSI Configuration
Kojto 99:dbbf35b96557 869 * @{
Kojto 99:dbbf35b96557 870 */
bogdanm 89:552587b429a1 871
bogdanm 89:552587b429a1 872 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
bogdanm 89:552587b429a1 873 * @note After enabling the LSI, the application software should wait on
bogdanm 89:552587b429a1 874 * LSIRDY flag to be set indicating that LSI clock is stable and can
bogdanm 89:552587b429a1 875 * be used to clock the IWDG and/or the RTC.
bogdanm 89:552587b429a1 876 * @note LSI can not be disabled if the IWDG is running.
bogdanm 89:552587b429a1 877 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
bogdanm 89:552587b429a1 878 * clock cycles.
bogdanm 89:552587b429a1 879 */
Kojto 99:dbbf35b96557 880 #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
Kojto 99:dbbf35b96557 881 #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
Kojto 99:dbbf35b96557 882 /**
Kojto 99:dbbf35b96557 883 * @}
Kojto 99:dbbf35b96557 884 */
Kojto 99:dbbf35b96557 885
Kojto 99:dbbf35b96557 886 /** @defgroup RCC_HSE_Configuration HSE Configuration
Kojto 99:dbbf35b96557 887 * @{
Kojto 99:dbbf35b96557 888 */
bogdanm 89:552587b429a1 889
bogdanm 89:552587b429a1 890 /**
bogdanm 89:552587b429a1 891 * @brief Macro to configure the External High Speed oscillator (HSE).
Kojto 99:dbbf35b96557 892 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro.
Kojto 99:dbbf35b96557 893 * User should request a transition to HSE Off first and then HSE On or HSE Bypass.
bogdanm 89:552587b429a1 894 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
bogdanm 89:552587b429a1 895 * software should wait on HSERDY flag to be set indicating that HSE clock
bogdanm 89:552587b429a1 896 * is stable and can be used to clock the PLL and/or system clock.
bogdanm 89:552587b429a1 897 * @note HSE state can not be changed if it is used directly or through the
bogdanm 89:552587b429a1 898 * PLL as system clock. In this case, you have to select another source
bogdanm 89:552587b429a1 899 * of the system clock then change the HSE state (ex. disable it).
bogdanm 89:552587b429a1 900 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
bogdanm 89:552587b429a1 901 * @note This function reset the CSSON bit, so if the clock security system(CSS)
bogdanm 89:552587b429a1 902 * was previously enabled you have to enable it again after calling this
bogdanm 89:552587b429a1 903 * function.
bogdanm 89:552587b429a1 904 * @param __STATE__: specifies the new state of the HSE.
bogdanm 89:552587b429a1 905 * This parameter can be one of the following values:
bogdanm 89:552587b429a1 906 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
bogdanm 89:552587b429a1 907 * 6 HSE oscillator clock cycles.
bogdanm 89:552587b429a1 908 * @arg RCC_HSE_ON: turn ON the HSE oscillator.
bogdanm 89:552587b429a1 909 * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
bogdanm 89:552587b429a1 910 */
AnnaBridge 145:64910690c574 911 #define __HAL_RCC_HSE_CONFIG(__STATE__) \
AnnaBridge 145:64910690c574 912 do { \
AnnaBridge 145:64910690c574 913 if ((__STATE__) == RCC_HSE_ON) \
AnnaBridge 145:64910690c574 914 { \
AnnaBridge 145:64910690c574 915 SET_BIT(RCC->CR, RCC_CR_HSEON); \
AnnaBridge 145:64910690c574 916 } \
AnnaBridge 145:64910690c574 917 else if ((__STATE__) == RCC_HSE_BYPASS) \
AnnaBridge 145:64910690c574 918 { \
AnnaBridge 145:64910690c574 919 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
AnnaBridge 145:64910690c574 920 SET_BIT(RCC->CR, RCC_CR_HSEON); \
AnnaBridge 145:64910690c574 921 } \
AnnaBridge 145:64910690c574 922 else \
AnnaBridge 145:64910690c574 923 { \
AnnaBridge 145:64910690c574 924 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
AnnaBridge 145:64910690c574 925 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
AnnaBridge 145:64910690c574 926 } \
AnnaBridge 145:64910690c574 927 } while(0U)
Kojto 99:dbbf35b96557 928 /**
Kojto 99:dbbf35b96557 929 * @}
Kojto 99:dbbf35b96557 930 */
Kojto 99:dbbf35b96557 931
Kojto 99:dbbf35b96557 932 /** @defgroup RCC_LSE_Configuration LSE Configuration
Kojto 99:dbbf35b96557 933 * @{
Kojto 99:dbbf35b96557 934 */
bogdanm 89:552587b429a1 935
bogdanm 89:552587b429a1 936 /**
bogdanm 89:552587b429a1 937 * @brief Macro to configure the External Low Speed oscillator (LSE).
Kojto 99:dbbf35b96557 938 * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
Kojto 99:dbbf35b96557 939 * User should request a transition to LSE Off first and then LSE On or LSE Bypass.
bogdanm 89:552587b429a1 940 * @note As the LSE is in the Backup domain and write access is denied to
bogdanm 89:552587b429a1 941 * this domain after reset, you have to enable write access using
bogdanm 89:552587b429a1 942 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
bogdanm 89:552587b429a1 943 * (to be done once after reset).
bogdanm 89:552587b429a1 944 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
bogdanm 89:552587b429a1 945 * software should wait on LSERDY flag to be set indicating that LSE clock
bogdanm 89:552587b429a1 946 * is stable and can be used to clock the RTC.
bogdanm 89:552587b429a1 947 * @param __STATE__: specifies the new state of the LSE.
bogdanm 89:552587b429a1 948 * This parameter can be one of the following values:
bogdanm 89:552587b429a1 949 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
bogdanm 89:552587b429a1 950 * 6 LSE oscillator clock cycles.
bogdanm 89:552587b429a1 951 * @arg RCC_LSE_ON: turn ON the LSE oscillator.
bogdanm 89:552587b429a1 952 * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
bogdanm 89:552587b429a1 953 */
AnnaBridge 145:64910690c574 954 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
AnnaBridge 145:64910690c574 955 do { \
AnnaBridge 145:64910690c574 956 if((__STATE__) == RCC_LSE_ON) \
AnnaBridge 145:64910690c574 957 { \
AnnaBridge 145:64910690c574 958 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
AnnaBridge 145:64910690c574 959 } \
AnnaBridge 145:64910690c574 960 else if((__STATE__) == RCC_LSE_BYPASS) \
AnnaBridge 145:64910690c574 961 { \
AnnaBridge 145:64910690c574 962 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
AnnaBridge 145:64910690c574 963 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
AnnaBridge 145:64910690c574 964 } \
AnnaBridge 145:64910690c574 965 else \
AnnaBridge 145:64910690c574 966 { \
AnnaBridge 145:64910690c574 967 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
AnnaBridge 145:64910690c574 968 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
AnnaBridge 145:64910690c574 969 } \
AnnaBridge 145:64910690c574 970 } while(0U)
Kojto 99:dbbf35b96557 971 /**
Kojto 99:dbbf35b96557 972 * @}
Kojto 99:dbbf35b96557 973 */
bogdanm 89:552587b429a1 974
Kojto 99:dbbf35b96557 975 /** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration
Kojto 99:dbbf35b96557 976 * @{
Kojto 99:dbbf35b96557 977 */
Kojto 99:dbbf35b96557 978
Kojto 99:dbbf35b96557 979 /** @brief Macros to enable or disable the RTC clock.
bogdanm 89:552587b429a1 980 * @note These macros must be used only after the RTC clock source was selected.
bogdanm 89:552587b429a1 981 */
Kojto 99:dbbf35b96557 982 #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
Kojto 99:dbbf35b96557 983 #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
bogdanm 89:552587b429a1 984
bogdanm 89:552587b429a1 985 /** @brief Macros to configure the RTC clock (RTCCLK).
bogdanm 89:552587b429a1 986 * @note As the RTC clock configuration bits are in the Backup domain and write
bogdanm 89:552587b429a1 987 * access is denied to this domain after reset, you have to enable write
bogdanm 89:552587b429a1 988 * access using the Power Backup Access macro before to configure
bogdanm 89:552587b429a1 989 * the RTC clock source (to be done once after reset).
bogdanm 89:552587b429a1 990 * @note Once the RTC clock is configured it can't be changed unless the
bogdanm 89:552587b429a1 991 * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
bogdanm 89:552587b429a1 992 * a Power On Reset (POR).
bogdanm 89:552587b429a1 993 * @param __RTCCLKSource__: specifies the RTC clock source.
bogdanm 89:552587b429a1 994 * This parameter can be one of the following values:
bogdanm 89:552587b429a1 995 * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
bogdanm 89:552587b429a1 996 * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
bogdanm 89:552587b429a1 997 * @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
bogdanm 89:552587b429a1 998 * as RTC clock, where x:[2,31]
bogdanm 89:552587b429a1 999 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
Kojto 99:dbbf35b96557 1000 * work in STOP and STANDBY modes, and can be used as wake-up source.
bogdanm 89:552587b429a1 1001 * However, when the HSE clock is used as RTC clock source, the RTC
bogdanm 89:552587b429a1 1002 * cannot be used in STOP and STANDBY modes.
bogdanm 89:552587b429a1 1003 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
bogdanm 89:552587b429a1 1004 * RTC clock source).
bogdanm 89:552587b429a1 1005 */
bogdanm 89:552587b429a1 1006 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
Kojto 122:f9eeca106725 1007 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFFU)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
bogdanm 89:552587b429a1 1008
bogdanm 89:552587b429a1 1009 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
Kojto 122:f9eeca106725 1010 RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU); \
AnnaBridge 145:64910690c574 1011 } while(0U)
bogdanm 89:552587b429a1 1012
bogdanm 89:552587b429a1 1013 /** @brief Macros to force or release the Backup domain reset.
bogdanm 89:552587b429a1 1014 * @note This function resets the RTC peripheral (including the backup registers)
bogdanm 89:552587b429a1 1015 * and the RTC clock source selection in RCC_CSR register.
bogdanm 89:552587b429a1 1016 * @note The BKPSRAM is not affected by this reset.
bogdanm 89:552587b429a1 1017 */
Kojto 99:dbbf35b96557 1018 #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
Kojto 99:dbbf35b96557 1019 #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
Kojto 99:dbbf35b96557 1020 /**
Kojto 99:dbbf35b96557 1021 * @}
Kojto 99:dbbf35b96557 1022 */
Kojto 99:dbbf35b96557 1023
Kojto 99:dbbf35b96557 1024 /** @defgroup RCC_PLL_Configuration PLL Configuration
Kojto 99:dbbf35b96557 1025 * @{
Kojto 99:dbbf35b96557 1026 */
bogdanm 89:552587b429a1 1027
bogdanm 89:552587b429a1 1028 /** @brief Macros to enable or disable the main PLL.
bogdanm 89:552587b429a1 1029 * @note After enabling the main PLL, the application software should wait on
bogdanm 89:552587b429a1 1030 * PLLRDY flag to be set indicating that PLL clock is stable and can
bogdanm 89:552587b429a1 1031 * be used as system clock source.
bogdanm 89:552587b429a1 1032 * @note The main PLL can not be disabled if it is used as system clock source
bogdanm 89:552587b429a1 1033 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
bogdanm 89:552587b429a1 1034 */
Kojto 99:dbbf35b96557 1035 #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
Kojto 99:dbbf35b96557 1036 #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
bogdanm 89:552587b429a1 1037
Kojto 99:dbbf35b96557 1038 /** @brief Macro to configure the PLL clock source.
bogdanm 89:552587b429a1 1039 * @note This function must be used only when the main PLL is disabled.
Kojto 99:dbbf35b96557 1040 * @param __PLLSOURCE__: specifies the PLL entry clock source.
bogdanm 89:552587b429a1 1041 * This parameter can be one of the following values:
bogdanm 89:552587b429a1 1042 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
bogdanm 89:552587b429a1 1043 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Kojto 99:dbbf35b96557 1044 *
Kojto 99:dbbf35b96557 1045 */
Kojto 99:dbbf35b96557 1046 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
Kojto 99:dbbf35b96557 1047
Kojto 99:dbbf35b96557 1048 /** @brief Macro to configure the PLL multiplication factor.
Kojto 99:dbbf35b96557 1049 * @note This function must be used only when the main PLL is disabled.
bogdanm 89:552587b429a1 1050 * @param __PLLM__: specifies the division factor for PLL VCO input clock
bogdanm 89:552587b429a1 1051 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
bogdanm 89:552587b429a1 1052 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
bogdanm 89:552587b429a1 1053 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
bogdanm 89:552587b429a1 1054 * of 2 MHz to limit PLL jitter.
Kojto 99:dbbf35b96557 1055 *
bogdanm 89:552587b429a1 1056 */
Kojto 99:dbbf35b96557 1057 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
Kojto 99:dbbf35b96557 1058 /**
Kojto 99:dbbf35b96557 1059 * @}
Kojto 122:f9eeca106725 1060 */
Kojto 122:f9eeca106725 1061
Kojto 99:dbbf35b96557 1062 /** @defgroup RCC_Get_Clock_source Get Clock source
Kojto 99:dbbf35b96557 1063 * @{
bogdanm 89:552587b429a1 1064 */
Kojto 99:dbbf35b96557 1065 /**
Kojto 99:dbbf35b96557 1066 * @brief Macro to configure the system clock source.
Kojto 99:dbbf35b96557 1067 * @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
Kojto 99:dbbf35b96557 1068 * This parameter can be one of the following values:
Kojto 99:dbbf35b96557 1069 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
Kojto 99:dbbf35b96557 1070 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
Kojto 99:dbbf35b96557 1071 * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
AnnaBridge 145:64910690c574 1072 * - RCC_SYSCLKSOURCE_PLLRCLK: PLLR output is used as system clock source. This
AnnaBridge 145:64910690c574 1073 * parameter is available only for STM32F446xx devices.
Kojto 99:dbbf35b96557 1074 */
Kojto 99:dbbf35b96557 1075 #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
bogdanm 89:552587b429a1 1076
bogdanm 89:552587b429a1 1077 /** @brief Macro to get the clock source used as system clock.
bogdanm 89:552587b429a1 1078 * @retval The clock source used as system clock. The returned value can be one
bogdanm 89:552587b429a1 1079 * of the following:
Kojto 99:dbbf35b96557 1080 * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
Kojto 99:dbbf35b96557 1081 * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
Kojto 99:dbbf35b96557 1082 * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
AnnaBridge 145:64910690c574 1083 * - RCC_SYSCLKSOURCE_STATUS_PLLRCLK: PLLR used as system clock. This parameter
AnnaBridge 145:64910690c574 1084 * is available only for STM32F446xx devices.
bogdanm 89:552587b429a1 1085 */
bogdanm 89:552587b429a1 1086 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
bogdanm 89:552587b429a1 1087
bogdanm 89:552587b429a1 1088 /** @brief Macro to get the oscillator used as PLL clock source.
bogdanm 89:552587b429a1 1089 * @retval The oscillator used as PLL clock source. The returned value can be one
bogdanm 89:552587b429a1 1090 * of the following:
bogdanm 89:552587b429a1 1091 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
bogdanm 89:552587b429a1 1092 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
bogdanm 89:552587b429a1 1093 */
bogdanm 89:552587b429a1 1094 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
Kojto 99:dbbf35b96557 1095 /**
Kojto 99:dbbf35b96557 1096 * @}
Kojto 99:dbbf35b96557 1097 */
Kojto 99:dbbf35b96557 1098
Kojto 110:165afa46840b 1099 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
Kojto 110:165afa46840b 1100 * @{
Kojto 110:165afa46840b 1101 */
Kojto 110:165afa46840b 1102
Kojto 110:165afa46840b 1103 /** @brief Macro to configure the MCO1 clock.
Kojto 110:165afa46840b 1104 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
Kojto 110:165afa46840b 1105 * This parameter can be one of the following values:
Kojto 110:165afa46840b 1106 * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
Kojto 110:165afa46840b 1107 * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
Kojto 110:165afa46840b 1108 * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
Kojto 110:165afa46840b 1109 * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
Kojto 110:165afa46840b 1110 * @param __MCODIV__ specifies the MCO clock prescaler.
Kojto 110:165afa46840b 1111 * This parameter can be one of the following values:
Kojto 110:165afa46840b 1112 * @arg RCC_MCODIV_1: no division applied to MCOx clock
Kojto 110:165afa46840b 1113 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
Kojto 110:165afa46840b 1114 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
Kojto 110:165afa46840b 1115 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
Kojto 110:165afa46840b 1116 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
Kojto 110:165afa46840b 1117 */
Kojto 110:165afa46840b 1118 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
Kojto 110:165afa46840b 1119 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
Kojto 122:f9eeca106725 1120
Kojto 110:165afa46840b 1121 /** @brief Macro to configure the MCO2 clock.
Kojto 110:165afa46840b 1122 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
Kojto 110:165afa46840b 1123 * This parameter can be one of the following values:
Kojto 110:165afa46840b 1124 * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
Kojto 110:165afa46840b 1125 * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx
Kojto 110:165afa46840b 1126 * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices
Kojto 110:165afa46840b 1127 * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
Kojto 110:165afa46840b 1128 * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
Kojto 110:165afa46840b 1129 * @param __MCODIV__ specifies the MCO clock prescaler.
Kojto 110:165afa46840b 1130 * This parameter can be one of the following values:
Kojto 110:165afa46840b 1131 * @arg RCC_MCODIV_1: no division applied to MCOx clock
Kojto 110:165afa46840b 1132 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
Kojto 110:165afa46840b 1133 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
Kojto 110:165afa46840b 1134 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
Kojto 110:165afa46840b 1135 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
Kojto 122:f9eeca106725 1136 * @note For STM32F410Rx devices, to output I2SCLK clock on MCO2, you should have
Kojto 122:f9eeca106725 1137 * at least one of the SPI clocks enabled (SPI1, SPI2 or SPI5).
Kojto 110:165afa46840b 1138 */
Kojto 110:165afa46840b 1139 #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
Kojto 122:f9eeca106725 1140 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3U)));
Kojto 110:165afa46840b 1141 /**
Kojto 110:165afa46840b 1142 * @}
Kojto 110:165afa46840b 1143 */
Kojto 110:165afa46840b 1144
Kojto 99:dbbf35b96557 1145 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
Kojto 99:dbbf35b96557 1146 * @brief macros to manage the specified RCC Flags and interrupts.
Kojto 99:dbbf35b96557 1147 * @{
Kojto 99:dbbf35b96557 1148 */
bogdanm 89:552587b429a1 1149
bogdanm 89:552587b429a1 1150 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
bogdanm 89:552587b429a1 1151 * the selected interrupts).
bogdanm 89:552587b429a1 1152 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
bogdanm 89:552587b429a1 1153 * This parameter can be any combination of the following values:
bogdanm 89:552587b429a1 1154 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
bogdanm 89:552587b429a1 1155 * @arg RCC_IT_LSERDY: LSE ready interrupt.
bogdanm 89:552587b429a1 1156 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
bogdanm 89:552587b429a1 1157 * @arg RCC_IT_HSERDY: HSE ready interrupt.
bogdanm 89:552587b429a1 1158 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
bogdanm 89:552587b429a1 1159 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
bogdanm 89:552587b429a1 1160 */
Kojto 99:dbbf35b96557 1161 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
bogdanm 89:552587b429a1 1162
bogdanm 89:552587b429a1 1163 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
bogdanm 89:552587b429a1 1164 * the selected interrupts).
bogdanm 89:552587b429a1 1165 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
bogdanm 89:552587b429a1 1166 * This parameter can be any combination of the following values:
bogdanm 89:552587b429a1 1167 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
bogdanm 89:552587b429a1 1168 * @arg RCC_IT_LSERDY: LSE ready interrupt.
bogdanm 89:552587b429a1 1169 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
bogdanm 89:552587b429a1 1170 * @arg RCC_IT_HSERDY: HSE ready interrupt.
bogdanm 89:552587b429a1 1171 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
bogdanm 89:552587b429a1 1172 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
bogdanm 89:552587b429a1 1173 */
Kojto 122:f9eeca106725 1174 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
bogdanm 89:552587b429a1 1175
bogdanm 89:552587b429a1 1176 /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
bogdanm 89:552587b429a1 1177 * bits to clear the selected interrupt pending bits.
bogdanm 89:552587b429a1 1178 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
bogdanm 89:552587b429a1 1179 * This parameter can be any combination of the following values:
bogdanm 89:552587b429a1 1180 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
bogdanm 89:552587b429a1 1181 * @arg RCC_IT_LSERDY: LSE ready interrupt.
bogdanm 89:552587b429a1 1182 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
bogdanm 89:552587b429a1 1183 * @arg RCC_IT_HSERDY: HSE ready interrupt.
bogdanm 89:552587b429a1 1184 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
bogdanm 89:552587b429a1 1185 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
bogdanm 89:552587b429a1 1186 * @arg RCC_IT_CSS: Clock Security System interrupt
bogdanm 89:552587b429a1 1187 */
Kojto 99:dbbf35b96557 1188 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
bogdanm 89:552587b429a1 1189
bogdanm 89:552587b429a1 1190 /** @brief Check the RCC's interrupt has occurred or not.
bogdanm 89:552587b429a1 1191 * @param __INTERRUPT__: specifies the RCC interrupt source to check.
bogdanm 89:552587b429a1 1192 * This parameter can be one of the following values:
bogdanm 89:552587b429a1 1193 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
bogdanm 89:552587b429a1 1194 * @arg RCC_IT_LSERDY: LSE ready interrupt.
bogdanm 89:552587b429a1 1195 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
bogdanm 89:552587b429a1 1196 * @arg RCC_IT_HSERDY: HSE ready interrupt.
bogdanm 89:552587b429a1 1197 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
bogdanm 89:552587b429a1 1198 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
bogdanm 89:552587b429a1 1199 * @arg RCC_IT_CSS: Clock Security System interrupt
bogdanm 89:552587b429a1 1200 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
bogdanm 89:552587b429a1 1201 */
bogdanm 89:552587b429a1 1202 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
bogdanm 89:552587b429a1 1203
bogdanm 89:552587b429a1 1204 /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
bogdanm 89:552587b429a1 1205 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
bogdanm 89:552587b429a1 1206 */
bogdanm 89:552587b429a1 1207 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
bogdanm 89:552587b429a1 1208
bogdanm 89:552587b429a1 1209 /** @brief Check RCC flag is set or not.
bogdanm 89:552587b429a1 1210 * @param __FLAG__: specifies the flag to check.
bogdanm 89:552587b429a1 1211 * This parameter can be one of the following values:
bogdanm 89:552587b429a1 1212 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
bogdanm 89:552587b429a1 1213 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
bogdanm 89:552587b429a1 1214 * @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
bogdanm 89:552587b429a1 1215 * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
bogdanm 89:552587b429a1 1216 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
bogdanm 89:552587b429a1 1217 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
bogdanm 89:552587b429a1 1218 * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
bogdanm 89:552587b429a1 1219 * @arg RCC_FLAG_PINRST: Pin reset.
bogdanm 89:552587b429a1 1220 * @arg RCC_FLAG_PORRST: POR/PDR reset.
bogdanm 89:552587b429a1 1221 * @arg RCC_FLAG_SFTRST: Software reset.
bogdanm 89:552587b429a1 1222 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
bogdanm 89:552587b429a1 1223 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
bogdanm 89:552587b429a1 1224 * @arg RCC_FLAG_LPWRRST: Low Power reset.
bogdanm 89:552587b429a1 1225 * @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm 89:552587b429a1 1226 */
Kojto 122:f9eeca106725 1227 #define RCC_FLAG_MASK ((uint8_t)0x1FU)
AnnaBridge 145:64910690c574 1228 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :((((__FLAG__) >> 5U) == 3U)? RCC->CSR :RCC->CIR))) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
bogdanm 89:552587b429a1 1229
Kojto 99:dbbf35b96557 1230 /**
Kojto 99:dbbf35b96557 1231 * @}
Kojto 99:dbbf35b96557 1232 */
Kojto 99:dbbf35b96557 1233
Kojto 99:dbbf35b96557 1234 /**
Kojto 99:dbbf35b96557 1235 * @}
Kojto 99:dbbf35b96557 1236 */
bogdanm 89:552587b429a1 1237
bogdanm 89:552587b429a1 1238 /* Exported functions --------------------------------------------------------*/
Kojto 99:dbbf35b96557 1239 /** @addtogroup RCC_Exported_Functions
Kojto 99:dbbf35b96557 1240 * @{
Kojto 99:dbbf35b96557 1241 */
Kojto 99:dbbf35b96557 1242
Kojto 99:dbbf35b96557 1243 /** @addtogroup RCC_Exported_Functions_Group1
Kojto 99:dbbf35b96557 1244 * @{
Kojto 99:dbbf35b96557 1245 */
bogdanm 89:552587b429a1 1246 /* Initialization and de-initialization functions ******************************/
bogdanm 89:552587b429a1 1247 void HAL_RCC_DeInit(void);
bogdanm 89:552587b429a1 1248 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
bogdanm 89:552587b429a1 1249 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
Kojto 99:dbbf35b96557 1250 /**
Kojto 99:dbbf35b96557 1251 * @}
Kojto 99:dbbf35b96557 1252 */
bogdanm 89:552587b429a1 1253
Kojto 99:dbbf35b96557 1254 /** @addtogroup RCC_Exported_Functions_Group2
Kojto 99:dbbf35b96557 1255 * @{
Kojto 99:dbbf35b96557 1256 */
bogdanm 89:552587b429a1 1257 /* Peripheral Control functions ************************************************/
bogdanm 89:552587b429a1 1258 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
bogdanm 89:552587b429a1 1259 void HAL_RCC_EnableCSS(void);
bogdanm 89:552587b429a1 1260 void HAL_RCC_DisableCSS(void);
bogdanm 89:552587b429a1 1261 uint32_t HAL_RCC_GetSysClockFreq(void);
bogdanm 89:552587b429a1 1262 uint32_t HAL_RCC_GetHCLKFreq(void);
bogdanm 89:552587b429a1 1263 uint32_t HAL_RCC_GetPCLK1Freq(void);
bogdanm 89:552587b429a1 1264 uint32_t HAL_RCC_GetPCLK2Freq(void);
bogdanm 89:552587b429a1 1265 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
bogdanm 89:552587b429a1 1266 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
bogdanm 89:552587b429a1 1267
bogdanm 89:552587b429a1 1268 /* CSS NMI IRQ handler */
bogdanm 89:552587b429a1 1269 void HAL_RCC_NMI_IRQHandler(void);
bogdanm 89:552587b429a1 1270
bogdanm 89:552587b429a1 1271 /* User Callbacks in non blocking mode (IT mode) */
Kojto 99:dbbf35b96557 1272 void HAL_RCC_CSSCallback(void);
Kojto 99:dbbf35b96557 1273
Kojto 99:dbbf35b96557 1274 /**
Kojto 99:dbbf35b96557 1275 * @}
Kojto 99:dbbf35b96557 1276 */
Kojto 99:dbbf35b96557 1277
Kojto 99:dbbf35b96557 1278 /**
Kojto 99:dbbf35b96557 1279 * @}
Kojto 99:dbbf35b96557 1280 */
Kojto 99:dbbf35b96557 1281
Kojto 99:dbbf35b96557 1282 /* Private types -------------------------------------------------------------*/
Kojto 99:dbbf35b96557 1283 /* Private variables ---------------------------------------------------------*/
Kojto 99:dbbf35b96557 1284 /* Private constants ---------------------------------------------------------*/
Kojto 99:dbbf35b96557 1285 /** @defgroup RCC_Private_Constants RCC Private Constants
Kojto 99:dbbf35b96557 1286 * @{
Kojto 99:dbbf35b96557 1287 */
Kojto 99:dbbf35b96557 1288
Kojto 99:dbbf35b96557 1289 /** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
Kojto 99:dbbf35b96557 1290 * @brief RCC registers bit address in the alias region
Kojto 99:dbbf35b96557 1291 * @{
Kojto 99:dbbf35b96557 1292 */
Kojto 99:dbbf35b96557 1293 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
Kojto 99:dbbf35b96557 1294 /* --- CR Register ---*/
Kojto 99:dbbf35b96557 1295 /* Alias word address of HSION bit */
Kojto 122:f9eeca106725 1296 #define RCC_CR_OFFSET (RCC_OFFSET + 0x00U)
Kojto 122:f9eeca106725 1297 #define RCC_HSION_BIT_NUMBER 0x00U
Kojto 122:f9eeca106725 1298 #define RCC_CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_HSION_BIT_NUMBER * 4U))
Kojto 99:dbbf35b96557 1299 /* Alias word address of CSSON bit */
Kojto 122:f9eeca106725 1300 #define RCC_CSSON_BIT_NUMBER 0x13U
Kojto 122:f9eeca106725 1301 #define RCC_CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))
Kojto 99:dbbf35b96557 1302 /* Alias word address of PLLON bit */
Kojto 122:f9eeca106725 1303 #define RCC_PLLON_BIT_NUMBER 0x18U
Kojto 122:f9eeca106725 1304 #define RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))
Kojto 99:dbbf35b96557 1305
Kojto 99:dbbf35b96557 1306 /* --- BDCR Register ---*/
Kojto 99:dbbf35b96557 1307 /* Alias word address of RTCEN bit */
Kojto 122:f9eeca106725 1308 #define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70U)
Kojto 122:f9eeca106725 1309 #define RCC_RTCEN_BIT_NUMBER 0x0FU
Kojto 122:f9eeca106725 1310 #define RCC_BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))
Kojto 99:dbbf35b96557 1311 /* Alias word address of BDRST bit */
Kojto 122:f9eeca106725 1312 #define RCC_BDRST_BIT_NUMBER 0x10U
Kojto 122:f9eeca106725 1313 #define RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))
Kojto 99:dbbf35b96557 1314
Kojto 99:dbbf35b96557 1315 /* --- CSR Register ---*/
Kojto 99:dbbf35b96557 1316 /* Alias word address of LSION bit */
Kojto 122:f9eeca106725 1317 #define RCC_CSR_OFFSET (RCC_OFFSET + 0x74U)
Kojto 122:f9eeca106725 1318 #define RCC_LSION_BIT_NUMBER 0x00U
Kojto 122:f9eeca106725 1319 #define RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32U) + (RCC_LSION_BIT_NUMBER * 4U))
Kojto 99:dbbf35b96557 1320
Kojto 99:dbbf35b96557 1321 /* CR register byte 3 (Bits[23:16]) base address */
AnnaBridge 145:64910690c574 1322 #define RCC_CR_BYTE2_ADDRESS 0x40023802U
Kojto 99:dbbf35b96557 1323
Kojto 99:dbbf35b96557 1324 /* CIR register byte 2 (Bits[15:8]) base address */
Kojto 122:f9eeca106725 1325 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x01U))
Kojto 99:dbbf35b96557 1326
Kojto 99:dbbf35b96557 1327 /* CIR register byte 3 (Bits[23:16]) base address */
Kojto 122:f9eeca106725 1328 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x02U))
Kojto 99:dbbf35b96557 1329
Kojto 99:dbbf35b96557 1330 /* BDCR register base address */
Kojto 99:dbbf35b96557 1331 #define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
Kojto 99:dbbf35b96557 1332
AnnaBridge 145:64910690c574 1333 #define RCC_DBP_TIMEOUT_VALUE 2U
Kojto 122:f9eeca106725 1334 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
Kojto 99:dbbf35b96557 1335
Kojto 99:dbbf35b96557 1336 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
AnnaBridge 145:64910690c574 1337 #define HSI_TIMEOUT_VALUE 2U /* 2 ms */
AnnaBridge 145:64910690c574 1338 #define LSI_TIMEOUT_VALUE 2U /* 2 ms */
Kojto 99:dbbf35b96557 1339
Kojto 99:dbbf35b96557 1340 /**
Kojto 99:dbbf35b96557 1341 * @}
Kojto 99:dbbf35b96557 1342 */
Kojto 99:dbbf35b96557 1343
Kojto 99:dbbf35b96557 1344 /**
Kojto 99:dbbf35b96557 1345 * @}
Kojto 99:dbbf35b96557 1346 */
Kojto 99:dbbf35b96557 1347
Kojto 99:dbbf35b96557 1348 /* Private macros ------------------------------------------------------------*/
Kojto 122:f9eeca106725 1349 /** @defgroup RCC_Private_Macros RCC Private Macros
Kojto 99:dbbf35b96557 1350 * @{
Kojto 99:dbbf35b96557 1351 */
Kojto 99:dbbf35b96557 1352
Kojto 99:dbbf35b96557 1353 /** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
Kojto 99:dbbf35b96557 1354 * @{
Kojto 99:dbbf35b96557 1355 */
Kojto 122:f9eeca106725 1356 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15U)
Kojto 99:dbbf35b96557 1357
Kojto 99:dbbf35b96557 1358 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
Kojto 99:dbbf35b96557 1359 ((HSE) == RCC_HSE_BYPASS))
Kojto 99:dbbf35b96557 1360
Kojto 99:dbbf35b96557 1361 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
Kojto 99:dbbf35b96557 1362 ((LSE) == RCC_LSE_BYPASS))
Kojto 99:dbbf35b96557 1363
Kojto 99:dbbf35b96557 1364 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
Kojto 99:dbbf35b96557 1365
Kojto 99:dbbf35b96557 1366 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
Kojto 99:dbbf35b96557 1367
Kojto 99:dbbf35b96557 1368 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
Kojto 99:dbbf35b96557 1369
Kojto 99:dbbf35b96557 1370 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
Kojto 99:dbbf35b96557 1371 ((SOURCE) == RCC_PLLSOURCE_HSE))
Kojto 99:dbbf35b96557 1372
Kojto 99:dbbf35b96557 1373 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
Kojto 99:dbbf35b96557 1374 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
Kojto 99:dbbf35b96557 1375 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \
Kojto 99:dbbf35b96557 1376 ((SOURCE) == RCC_SYSCLKSOURCE_PLLRCLK))
Kojto 99:dbbf35b96557 1377
Kojto 122:f9eeca106725 1378 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
Kojto 122:f9eeca106725 1379 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
Kojto 122:f9eeca106725 1380 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \
Kojto 122:f9eeca106725 1381 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3) || \
Kojto 122:f9eeca106725 1382 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \
Kojto 122:f9eeca106725 1383 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV5) || \
Kojto 122:f9eeca106725 1384 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV6) || \
Kojto 122:f9eeca106725 1385 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV7) || \
Kojto 122:f9eeca106725 1386 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \
Kojto 122:f9eeca106725 1387 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV9) || \
Kojto 122:f9eeca106725 1388 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV10) || \
Kojto 122:f9eeca106725 1389 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV11) || \
Kojto 122:f9eeca106725 1390 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV12) || \
Kojto 122:f9eeca106725 1391 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV13) || \
Kojto 122:f9eeca106725 1392 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV14) || \
Kojto 122:f9eeca106725 1393 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV15) || \
Kojto 122:f9eeca106725 1394 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16) || \
Kojto 122:f9eeca106725 1395 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV17) || \
Kojto 122:f9eeca106725 1396 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV18) || \
Kojto 122:f9eeca106725 1397 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV19) || \
Kojto 122:f9eeca106725 1398 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV20) || \
Kojto 122:f9eeca106725 1399 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV21) || \
Kojto 122:f9eeca106725 1400 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV22) || \
Kojto 122:f9eeca106725 1401 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV23) || \
Kojto 122:f9eeca106725 1402 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV24) || \
Kojto 122:f9eeca106725 1403 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV25) || \
Kojto 122:f9eeca106725 1404 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV26) || \
Kojto 122:f9eeca106725 1405 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV27) || \
Kojto 122:f9eeca106725 1406 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV28) || \
Kojto 122:f9eeca106725 1407 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV29) || \
Kojto 122:f9eeca106725 1408 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) || \
Kojto 122:f9eeca106725 1409 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31))
Kojto 122:f9eeca106725 1410
Kojto 122:f9eeca106725 1411 #define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63U)
Kojto 99:dbbf35b96557 1412
Kojto 122:f9eeca106725 1413 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || ((VALUE) == 6U) || ((VALUE) == 8U))
Kojto 99:dbbf35b96557 1414
AnnaBridge 145:64910690c574 1415 #define IS_RCC_PLLQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
Kojto 99:dbbf35b96557 1416
Kojto 99:dbbf35b96557 1417 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \
Kojto 99:dbbf35b96557 1418 ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \
Kojto 99:dbbf35b96557 1419 ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \
Kojto 99:dbbf35b96557 1420 ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
Kojto 99:dbbf35b96557 1421 ((HCLK) == RCC_SYSCLK_DIV512))
Kojto 99:dbbf35b96557 1422
Kojto 122:f9eeca106725 1423 #define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 15U))
Kojto 99:dbbf35b96557 1424
Kojto 99:dbbf35b96557 1425 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
Kojto 99:dbbf35b96557 1426 ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
Kojto 99:dbbf35b96557 1427 ((PCLK) == RCC_HCLK_DIV16))
Kojto 99:dbbf35b96557 1428
Kojto 99:dbbf35b96557 1429 #define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
Kojto 99:dbbf35b96557 1430
Kojto 99:dbbf35b96557 1431 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
Kojto 99:dbbf35b96557 1432 ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
Kojto 99:dbbf35b96557 1433
Kojto 99:dbbf35b96557 1434 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
Kojto 99:dbbf35b96557 1435 ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
Kojto 99:dbbf35b96557 1436 ((DIV) == RCC_MCODIV_5))
Kojto 122:f9eeca106725 1437 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU)
Kojto 99:dbbf35b96557 1438
Kojto 99:dbbf35b96557 1439 /**
Kojto 99:dbbf35b96557 1440 * @}
Kojto 99:dbbf35b96557 1441 */
Kojto 99:dbbf35b96557 1442
Kojto 99:dbbf35b96557 1443 /**
Kojto 99:dbbf35b96557 1444 * @}
Kojto 99:dbbf35b96557 1445 */
bogdanm 89:552587b429a1 1446
bogdanm 89:552587b429a1 1447 /**
bogdanm 89:552587b429a1 1448 * @}
bogdanm 89:552587b429a1 1449 */
bogdanm 89:552587b429a1 1450
bogdanm 89:552587b429a1 1451 /**
bogdanm 89:552587b429a1 1452 * @}
bogdanm 89:552587b429a1 1453 */
bogdanm 89:552587b429a1 1454
bogdanm 89:552587b429a1 1455 #ifdef __cplusplus
bogdanm 89:552587b429a1 1456 }
bogdanm 89:552587b429a1 1457 #endif
bogdanm 89:552587b429a1 1458
bogdanm 89:552587b429a1 1459 #endif /* __STM32F4xx_HAL_RCC_H */
bogdanm 89:552587b429a1 1460
bogdanm 89:552587b429a1 1461 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/