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LPC1768/GCC_CR/system_LPC17xx.h@33:5364839841bd, 2012-01-10 (annotated)

Committer:
emilmont
Date:
Tue Jan 10 12:00:50 2012 +0000
Revision:
33:5364839841bd
Parent:
27:7110ebee3484 
[10 January 2012] CAN::attach template. CMSIS updates.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 27:7110ebee3484 1 /******************************************************************************
emilmont 27:7110ebee3484 2 * @file: system_LPC17xx.h
emilmont 27:7110ebee3484 3 * @purpose: CMSIS Cortex-M3 Device Peripheral Access Layer Header File
emilmont 27:7110ebee3484 4 * for the NXP LPC17xx Device Series
emilmont 27:7110ebee3484 5 * @version: V1.02
emilmont 27:7110ebee3484 6 * @date: 27. July 2009
emilmont 27:7110ebee3484 7 *----------------------------------------------------------------------------
emilmont 27:7110ebee3484 8 *
emilmont 27:7110ebee3484 9 * Copyright (C) 2009 ARM Limited. All rights reserved.
emilmont 27:7110ebee3484 10 *
emilmont 27:7110ebee3484 11 * ARM Limited (ARM) is supplying this software for use with Cortex-M3
emilmont 27:7110ebee3484 12 * processor based microcontrollers. This file can be freely distributed
emilmont 27:7110ebee3484 13 * within development tools that are supporting such ARM based processors.
emilmont 27:7110ebee3484 14 *
emilmont 27:7110ebee3484 15 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
emilmont 27:7110ebee3484 16 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
emilmont 27:7110ebee3484 17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
emilmont 27:7110ebee3484 18 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
emilmont 27:7110ebee3484 19 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
emilmont 27:7110ebee3484 20 *
emilmont 27:7110ebee3484 21 ******************************************************************************/
emilmont 27:7110ebee3484 22
emilmont 27:7110ebee3484 23
emilmont 27:7110ebee3484 24 #ifndef __SYSTEM_LPC17xx_H
emilmont 27:7110ebee3484 25 #define __SYSTEM_LPC17xx_H
emilmont 27:7110ebee3484 26
emilmont 27:7110ebee3484 27 #ifdef __cplusplus
emilmont 27:7110ebee3484 28 extern "C" {
emilmont 27:7110ebee3484 29 #endif
emilmont 27:7110ebee3484 30
emilmont 27:7110ebee3484 31 extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
emilmont 27:7110ebee3484 32
emilmont 27:7110ebee3484 33
emilmont 27:7110ebee3484 34 /**
emilmont 27:7110ebee3484 35 * Initialize the system
emilmont 27:7110ebee3484 36 *
emilmont 27:7110ebee3484 37 * @param none
emilmont 27:7110ebee3484 38 * @return none
emilmont 27:7110ebee3484 39 *
emilmont 27:7110ebee3484 40 * @brief Setup the microcontroller system.
emilmont 27:7110ebee3484 41 * Initialize the System and update the SystemCoreClock variable.
emilmont 27:7110ebee3484 42 */
emilmont 27:7110ebee3484 43 extern void SystemInit (void);
emilmont 27:7110ebee3484 44
emilmont 27:7110ebee3484 45 /**
emilmont 27:7110ebee3484 46 * Update SystemCoreClock variable
emilmont 27:7110ebee3484 47 *
emilmont 27:7110ebee3484 48 * @param none
emilmont 27:7110ebee3484 49 * @return none
emilmont 27:7110ebee3484 50 *
emilmont 27:7110ebee3484 51 * @brief Updates the SystemCoreClock with current core Clock
emilmont 27:7110ebee3484 52 * retrieved from cpu registers.
emilmont 27:7110ebee3484 53 */
emilmont 27:7110ebee3484 54 extern void SystemCoreClockUpdate (void);
emilmont 27:7110ebee3484 55
emilmont 27:7110ebee3484 56 #ifdef __cplusplus
emilmont 27:7110ebee3484 57 }
emilmont 27:7110ebee3484 58 #endif
emilmont 27:7110ebee3484 59
emilmont 27:7110ebee3484 60 #endif /* __SYSTEM_LPC17xx_H */