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TARGET_LPC54114/TOOLCHAIN_IAR/LPC54114_cm4.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
Parent:
TARGET_LPC54114/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/device/TARGET_LPC54114_M4/LPC54114_cm4.h@148:fd96258d940d 
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 148:fd96258d940d 1 /*
Kojto 148:fd96258d940d 2 ** ###################################################################
Kojto 148:fd96258d940d 3 ** Processors: LPC54114J256BD64_cm4
Kojto 148:fd96258d940d 4 ** LPC54114J256UK49_cm4
Kojto 148:fd96258d940d 5 **
Kojto 148:fd96258d940d 6 ** Compilers: Keil ARM C/C++ Compiler
Kojto 148:fd96258d940d 7 ** GNU C Compiler
Kojto 148:fd96258d940d 8 ** IAR ANSI C/C++ Compiler for ARM
Kojto 148:fd96258d940d 9 **
Kojto 148:fd96258d940d 10 ** Reference manual: LPC5411x User manual Rev. 1.1 25 May 2016
Kojto 148:fd96258d940d 11 ** Version: rev. 1.0, 2016-04-29
Kojto 148:fd96258d940d 12 ** Build: b160922
Kojto 148:fd96258d940d 13 **
Kojto 148:fd96258d940d 14 ** Abstract:
Kojto 148:fd96258d940d 15 ** CMSIS Peripheral Access Layer for LPC54114_cm4
Kojto 148:fd96258d940d 16 **
Kojto 148:fd96258d940d 17 ** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc.
Kojto 148:fd96258d940d 18 ** All rights reserved.
Kojto 148:fd96258d940d 19 **
Kojto 148:fd96258d940d 20 ** Redistribution and use in source and binary forms, with or without modification,
Kojto 148:fd96258d940d 21 ** are permitted provided that the following conditions are met:
Kojto 148:fd96258d940d 22 **
Kojto 148:fd96258d940d 23 ** o Redistributions of source code must retain the above copyright notice, this list
Kojto 148:fd96258d940d 24 ** of conditions and the following disclaimer.
Kojto 148:fd96258d940d 25 **
Kojto 148:fd96258d940d 26 ** o Redistributions in binary form must reproduce the above copyright notice, this
Kojto 148:fd96258d940d 27 ** list of conditions and the following disclaimer in the documentation and/or
Kojto 148:fd96258d940d 28 ** other materials provided with the distribution.
Kojto 148:fd96258d940d 29 **
Kojto 148:fd96258d940d 30 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
Kojto 148:fd96258d940d 31 ** contributors may be used to endorse or promote products derived from this
Kojto 148:fd96258d940d 32 ** software without specific prior written permission.
Kojto 148:fd96258d940d 33 **
Kojto 148:fd96258d940d 34 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
Kojto 148:fd96258d940d 35 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
Kojto 148:fd96258d940d 36 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 148:fd96258d940d 37 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
Kojto 148:fd96258d940d 38 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
Kojto 148:fd96258d940d 39 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
Kojto 148:fd96258d940d 40 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
Kojto 148:fd96258d940d 41 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
Kojto 148:fd96258d940d 42 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
Kojto 148:fd96258d940d 43 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 148:fd96258d940d 44 **
Kojto 148:fd96258d940d 45 ** http: www.freescale.com
Kojto 148:fd96258d940d 46 ** mail: support@freescale.com
Kojto 148:fd96258d940d 47 **
Kojto 148:fd96258d940d 48 ** Revisions:
Kojto 148:fd96258d940d 49 ** - rev. 1.0 (2016-04-29)
Kojto 148:fd96258d940d 50 ** Initial version.
Kojto 148:fd96258d940d 51 **
Kojto 148:fd96258d940d 52 ** ###################################################################
Kojto 148:fd96258d940d 53 */
Kojto 148:fd96258d940d 54
Kojto 148:fd96258d940d 55 /*!
Kojto 148:fd96258d940d 56 * @file LPC54114_cm4.h
Kojto 148:fd96258d940d 57 * @version 1.0
Kojto 148:fd96258d940d 58 * @date 2016-04-29
Kojto 148:fd96258d940d 59 * @brief CMSIS Peripheral Access Layer for LPC54114_cm4
Kojto 148:fd96258d940d 60 *
Kojto 148:fd96258d940d 61 * CMSIS Peripheral Access Layer for LPC54114_cm4
Kojto 148:fd96258d940d 62 */
Kojto 148:fd96258d940d 63
Kojto 148:fd96258d940d 64 #ifndef _LPC54114_CM4_H_
Kojto 148:fd96258d940d 65 #define _LPC54114_CM4_H_ /**< Symbol preventing repeated inclusion */
Kojto 148:fd96258d940d 66
Kojto 148:fd96258d940d 67 /** Memory map major version (memory maps with equal major version number are
Kojto 148:fd96258d940d 68 * compatible) */
Kojto 148:fd96258d940d 69 #define MCU_MEM_MAP_VERSION 0x0100U
Kojto 148:fd96258d940d 70 /** Memory map minor version */
Kojto 148:fd96258d940d 71 #define MCU_MEM_MAP_VERSION_MINOR 0x0000U
Kojto 148:fd96258d940d 72
Kojto 148:fd96258d940d 73
Kojto 148:fd96258d940d 74 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 75 -- Interrupt vector numbers
Kojto 148:fd96258d940d 76 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 77
Kojto 148:fd96258d940d 78 /*!
Kojto 148:fd96258d940d 79 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
Kojto 148:fd96258d940d 80 * @{
Kojto 148:fd96258d940d 81 */
Kojto 148:fd96258d940d 82
Kojto 148:fd96258d940d 83 /** Interrupt Number Definitions */
Kojto 148:fd96258d940d 84 #define NUMBER_OF_INT_VECTORS 56 /**< Number of interrupts in the Vector table */
Kojto 148:fd96258d940d 85
Kojto 148:fd96258d940d 86 typedef enum IRQn {
Kojto 148:fd96258d940d 87 /* Auxiliary constants */
Kojto 148:fd96258d940d 88 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
Kojto 148:fd96258d940d 89
Kojto 148:fd96258d940d 90 /* Core interrupts */
Kojto 148:fd96258d940d 91 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
Kojto 148:fd96258d940d 92 HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
Kojto 148:fd96258d940d 93 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
Kojto 148:fd96258d940d 94 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
Kojto 148:fd96258d940d 95 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
Kojto 148:fd96258d940d 96 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
Kojto 148:fd96258d940d 97 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
Kojto 148:fd96258d940d 98 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
Kojto 148:fd96258d940d 99 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
Kojto 148:fd96258d940d 100
Kojto 148:fd96258d940d 101 /* Device specific interrupts */
Kojto 148:fd96258d940d 102 WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect */
Kojto 148:fd96258d940d 103 DMA0_IRQn = 1, /**< DMA controller */
Kojto 148:fd96258d940d 104 GINT0_IRQn = 2, /**< GPIO group 0 */
Kojto 148:fd96258d940d 105 GINT1_IRQn = 3, /**< GPIO group 1 */
Kojto 148:fd96258d940d 106 PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */
Kojto 148:fd96258d940d 107 PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */
Kojto 148:fd96258d940d 108 PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */
Kojto 148:fd96258d940d 109 PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */
Kojto 148:fd96258d940d 110 UTICK0_IRQn = 8, /**< Micro-tick Timer */
Kojto 148:fd96258d940d 111 MRT0_IRQn = 9, /**< Multi-rate timer */
Kojto 148:fd96258d940d 112 CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */
Kojto 148:fd96258d940d 113 CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */
Kojto 148:fd96258d940d 114 SCT0_IRQn = 12, /**< SCTimer/PWM */
Kojto 148:fd96258d940d 115 CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */
Kojto 148:fd96258d940d 116 FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C) */
Kojto 148:fd96258d940d 117 FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C) */
Kojto 148:fd96258d940d 118 FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C) */
Kojto 148:fd96258d940d 119 FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C) */
Kojto 148:fd96258d940d 120 FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C) */
Kojto 148:fd96258d940d 121 FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C) */
Kojto 148:fd96258d940d 122 FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S) */
Kojto 148:fd96258d940d 123 FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S) */
Kojto 148:fd96258d940d 124 ADC0_SEQA_IRQn = 22, /**< ADC0 sequence A completion. */
Kojto 148:fd96258d940d 125 ADC0_SEQB_IRQn = 23, /**< ADC0 sequence B completion. */
Kojto 148:fd96258d940d 126 ADC0_THCMP_IRQn = 24, /**< ADC0 threshold compare and error. */
Kojto 148:fd96258d940d 127 DMIC0_IRQn = 25, /**< Digital microphone and DMIC subsystem */
Kojto 148:fd96258d940d 128 HWVAD0_IRQn = 26, /**< Hardware Voice Activity Detector */
Kojto 148:fd96258d940d 129 USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */
Kojto 148:fd96258d940d 130 USB0_IRQn = 28, /**< USB device */
Kojto 148:fd96258d940d 131 RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */
Kojto 148:fd96258d940d 132 IOH_IRQn = 30, /**< IOH */
Kojto 148:fd96258d940d 133 MAILBOX_IRQn = 31, /**< Mailbox interrupt (present on selected devices) */
Kojto 148:fd96258d940d 134 PIN_INT4_IRQn = 32, /**< Pin interrupt 4 or pattern match engine slice 4 int */
Kojto 148:fd96258d940d 135 PIN_INT5_IRQn = 33, /**< Pin interrupt 5 or pattern match engine slice 5 int */
Kojto 148:fd96258d940d 136 PIN_INT6_IRQn = 34, /**< Pin interrupt 6 or pattern match engine slice 6 int */
Kojto 148:fd96258d940d 137 PIN_INT7_IRQn = 35, /**< Pin interrupt 7 or pattern match engine slice 7 int */
Kojto 148:fd96258d940d 138 CTIMER2_IRQn = 36, /**< Standard counter/timer CTIMER2 */
Kojto 148:fd96258d940d 139 CTIMER4_IRQn = 37, /**< Standard counter/timer CTIMER4 */
Kojto 148:fd96258d940d 140 Reserved54_IRQn = 38, /**< Reserved interrupt */
Kojto 148:fd96258d940d 141 SPIFI0_IRQn = 39 /**< SPI flash interface */
Kojto 148:fd96258d940d 142 } IRQn_Type;
Kojto 148:fd96258d940d 143
Kojto 148:fd96258d940d 144 /*!
Kojto 148:fd96258d940d 145 * @}
Kojto 148:fd96258d940d 146 */ /* end of group Interrupt_vector_numbers */
Kojto 148:fd96258d940d 147
Kojto 148:fd96258d940d 148
Kojto 148:fd96258d940d 149 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 150 -- Cortex M4 Core Configuration
Kojto 148:fd96258d940d 151 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 152
Kojto 148:fd96258d940d 153 /*!
Kojto 148:fd96258d940d 154 * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
Kojto 148:fd96258d940d 155 * @{
Kojto 148:fd96258d940d 156 */
Kojto 148:fd96258d940d 157
Kojto 148:fd96258d940d 158 #define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
Kojto 148:fd96258d940d 159 #define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */
Kojto 148:fd96258d940d 160 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
Kojto 148:fd96258d940d 161 #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
Kojto 148:fd96258d940d 162
Kojto 148:fd96258d940d 163 #include "core_cm4.h" /* Core Peripheral Access Layer */
Kojto 148:fd96258d940d 164 #include "system_LPC54114_cm4.h" /* Device specific configuration file */
Kojto 148:fd96258d940d 165
Kojto 148:fd96258d940d 166 /*!
Kojto 148:fd96258d940d 167 * @}
Kojto 148:fd96258d940d 168 */ /* end of group Cortex_Core_Configuration */
Kojto 148:fd96258d940d 169
Kojto 148:fd96258d940d 170
Kojto 148:fd96258d940d 171 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 172 -- Mapping Information
Kojto 148:fd96258d940d 173 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 174
Kojto 148:fd96258d940d 175 /*!
Kojto 148:fd96258d940d 176 * @addtogroup Mapping_Information Mapping Information
Kojto 148:fd96258d940d 177 * @{
Kojto 148:fd96258d940d 178 */
Kojto 148:fd96258d940d 179
Kojto 148:fd96258d940d 180 /** Mapping Information */
Kojto 148:fd96258d940d 181
Kojto 148:fd96258d940d 182 /*!
Kojto 148:fd96258d940d 183 * @}
Kojto 148:fd96258d940d 184 */ /* end of group Mapping_Information */
Kojto 148:fd96258d940d 185
Kojto 148:fd96258d940d 186
Kojto 148:fd96258d940d 187 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 188 -- Device Peripheral Access Layer
Kojto 148:fd96258d940d 189 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 190
Kojto 148:fd96258d940d 191 /*!
Kojto 148:fd96258d940d 192 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
Kojto 148:fd96258d940d 193 * @{
Kojto 148:fd96258d940d 194 */
Kojto 148:fd96258d940d 195
Kojto 148:fd96258d940d 196
Kojto 148:fd96258d940d 197 /*
Kojto 148:fd96258d940d 198 ** Start of section using anonymous unions
Kojto 148:fd96258d940d 199 */
Kojto 148:fd96258d940d 200
Kojto 148:fd96258d940d 201 #if defined(__ARMCC_VERSION)
Kojto 148:fd96258d940d 202 #pragma push
Kojto 148:fd96258d940d 203 #pragma anon_unions
Kojto 148:fd96258d940d 204 #elif defined(__GNUC__)
Kojto 148:fd96258d940d 205 /* anonymous unions are enabled by default */
Kojto 148:fd96258d940d 206 #elif defined(__IAR_SYSTEMS_ICC__)
Kojto 148:fd96258d940d 207 #pragma language=extended
Kojto 148:fd96258d940d 208 #else
Kojto 148:fd96258d940d 209 #error Not supported compiler type
Kojto 148:fd96258d940d 210 #endif
Kojto 148:fd96258d940d 211
Kojto 148:fd96258d940d 212 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 213 -- ADC Peripheral Access Layer
Kojto 148:fd96258d940d 214 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 215
Kojto 148:fd96258d940d 216 /*!
Kojto 148:fd96258d940d 217 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
Kojto 148:fd96258d940d 218 * @{
Kojto 148:fd96258d940d 219 */
Kojto 148:fd96258d940d 220
Kojto 148:fd96258d940d 221 /** ADC - Register Layout Typedef */
Kojto 148:fd96258d940d 222 typedef struct {
Kojto 148:fd96258d940d 223 __IO uint32_t CTRL; /**< ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls., offset: 0x0 */
Kojto 148:fd96258d940d 224 __IO uint32_t INSEL; /**< Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0., offset: 0x4 */
Kojto 148:fd96258d940d 225 __IO uint32_t SEQ_CTRL[2]; /**< ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n., array offset: 0x8, array step: 0x4 */
Kojto 148:fd96258d940d 226 __I uint32_t SEQ_GDAT[2]; /**< ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n., array offset: 0x10, array step: 0x4 */
Kojto 148:fd96258d940d 227 uint8_t RESERVED_0[8];
Kojto 148:fd96258d940d 228 __I uint32_t DAT[12]; /**< ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0., array offset: 0x20, array step: 0x4 */
Kojto 148:fd96258d940d 229 __IO uint32_t THR0_LOW; /**< ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x50 */
Kojto 148:fd96258d940d 230 __IO uint32_t THR1_LOW; /**< ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x54 */
Kojto 148:fd96258d940d 231 __IO uint32_t THR0_HIGH; /**< ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x58 */
Kojto 148:fd96258d940d 232 __IO uint32_t THR1_HIGH; /**< ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x5C */
Kojto 148:fd96258d940d 233 __IO uint32_t CHAN_THRSEL; /**< ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel, offset: 0x60 */
Kojto 148:fd96258d940d 234 __IO uint32_t INTEN; /**< ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated., offset: 0x64 */
Kojto 148:fd96258d940d 235 __IO uint32_t FLAGS; /**< ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers)., offset: 0x68 */
Kojto 148:fd96258d940d 236 __IO uint32_t STARTUP; /**< ADC Startup register., offset: 0x6C */
Kojto 148:fd96258d940d 237 __IO uint32_t CALIB; /**< ADC Calibration register., offset: 0x70 */
Kojto 148:fd96258d940d 238 } ADC_Type;
Kojto 148:fd96258d940d 239
Kojto 148:fd96258d940d 240 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 241 -- ADC Register Masks
Kojto 148:fd96258d940d 242 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 243
Kojto 148:fd96258d940d 244 /*!
Kojto 148:fd96258d940d 245 * @addtogroup ADC_Register_Masks ADC Register Masks
Kojto 148:fd96258d940d 246 * @{
Kojto 148:fd96258d940d 247 */
Kojto 148:fd96258d940d 248
Kojto 148:fd96258d940d 249 /*! @name CTRL - ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls. */
Kojto 148:fd96258d940d 250 #define ADC_CTRL_CLKDIV_MASK (0xFFU)
Kojto 148:fd96258d940d 251 #define ADC_CTRL_CLKDIV_SHIFT (0U)
Kojto 148:fd96258d940d 252 #define ADC_CTRL_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CLKDIV_SHIFT)) & ADC_CTRL_CLKDIV_MASK)
Kojto 148:fd96258d940d 253 #define ADC_CTRL_ASYNMODE_MASK (0x100U)
Kojto 148:fd96258d940d 254 #define ADC_CTRL_ASYNMODE_SHIFT (8U)
Kojto 148:fd96258d940d 255 #define ADC_CTRL_ASYNMODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ASYNMODE_SHIFT)) & ADC_CTRL_ASYNMODE_MASK)
Kojto 148:fd96258d940d 256 #define ADC_CTRL_RESOL_MASK (0x600U)
Kojto 148:fd96258d940d 257 #define ADC_CTRL_RESOL_SHIFT (9U)
Kojto 148:fd96258d940d 258 #define ADC_CTRL_RESOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RESOL_SHIFT)) & ADC_CTRL_RESOL_MASK)
Kojto 148:fd96258d940d 259 #define ADC_CTRL_BYPASSCAL_MASK (0x800U)
Kojto 148:fd96258d940d 260 #define ADC_CTRL_BYPASSCAL_SHIFT (11U)
Kojto 148:fd96258d940d 261 #define ADC_CTRL_BYPASSCAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_BYPASSCAL_SHIFT)) & ADC_CTRL_BYPASSCAL_MASK)
Kojto 148:fd96258d940d 262 #define ADC_CTRL_TSAMP_MASK (0x7000U)
Kojto 148:fd96258d940d 263 #define ADC_CTRL_TSAMP_SHIFT (12U)
Kojto 148:fd96258d940d 264 #define ADC_CTRL_TSAMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_TSAMP_SHIFT)) & ADC_CTRL_TSAMP_MASK)
Kojto 148:fd96258d940d 265
Kojto 148:fd96258d940d 266 /*! @name INSEL - Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0. */
Kojto 148:fd96258d940d 267 #define ADC_INSEL_SEL_MASK (0x3U)
Kojto 148:fd96258d940d 268 #define ADC_INSEL_SEL_SHIFT (0U)
Kojto 148:fd96258d940d 269 #define ADC_INSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_INSEL_SEL_SHIFT)) & ADC_INSEL_SEL_MASK)
Kojto 148:fd96258d940d 270
Kojto 148:fd96258d940d 271 /*! @name SEQ_CTRL - ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n. */
Kojto 148:fd96258d940d 272 #define ADC_SEQ_CTRL_CHANNELS_MASK (0xFFFU)
Kojto 148:fd96258d940d 273 #define ADC_SEQ_CTRL_CHANNELS_SHIFT (0U)
Kojto 148:fd96258d940d 274 #define ADC_SEQ_CTRL_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_CHANNELS_SHIFT)) & ADC_SEQ_CTRL_CHANNELS_MASK)
Kojto 148:fd96258d940d 275 #define ADC_SEQ_CTRL_TRIGGER_MASK (0x3F000U)
Kojto 148:fd96258d940d 276 #define ADC_SEQ_CTRL_TRIGGER_SHIFT (12U)
Kojto 148:fd96258d940d 277 #define ADC_SEQ_CTRL_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGGER_SHIFT)) & ADC_SEQ_CTRL_TRIGGER_MASK)
Kojto 148:fd96258d940d 278 #define ADC_SEQ_CTRL_TRIGPOL_MASK (0x40000U)
Kojto 148:fd96258d940d 279 #define ADC_SEQ_CTRL_TRIGPOL_SHIFT (18U)
Kojto 148:fd96258d940d 280 #define ADC_SEQ_CTRL_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGPOL_SHIFT)) & ADC_SEQ_CTRL_TRIGPOL_MASK)
Kojto 148:fd96258d940d 281 #define ADC_SEQ_CTRL_SYNCBYPASS_MASK (0x80000U)
Kojto 148:fd96258d940d 282 #define ADC_SEQ_CTRL_SYNCBYPASS_SHIFT (19U)
Kojto 148:fd96258d940d 283 #define ADC_SEQ_CTRL_SYNCBYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SYNCBYPASS_SHIFT)) & ADC_SEQ_CTRL_SYNCBYPASS_MASK)
Kojto 148:fd96258d940d 284 #define ADC_SEQ_CTRL_START_MASK (0x4000000U)
Kojto 148:fd96258d940d 285 #define ADC_SEQ_CTRL_START_SHIFT (26U)
Kojto 148:fd96258d940d 286 #define ADC_SEQ_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_START_SHIFT)) & ADC_SEQ_CTRL_START_MASK)
Kojto 148:fd96258d940d 287 #define ADC_SEQ_CTRL_BURST_MASK (0x8000000U)
Kojto 148:fd96258d940d 288 #define ADC_SEQ_CTRL_BURST_SHIFT (27U)
Kojto 148:fd96258d940d 289 #define ADC_SEQ_CTRL_BURST(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_BURST_SHIFT)) & ADC_SEQ_CTRL_BURST_MASK)
Kojto 148:fd96258d940d 290 #define ADC_SEQ_CTRL_SINGLESTEP_MASK (0x10000000U)
Kojto 148:fd96258d940d 291 #define ADC_SEQ_CTRL_SINGLESTEP_SHIFT (28U)
Kojto 148:fd96258d940d 292 #define ADC_SEQ_CTRL_SINGLESTEP(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SINGLESTEP_SHIFT)) & ADC_SEQ_CTRL_SINGLESTEP_MASK)
Kojto 148:fd96258d940d 293 #define ADC_SEQ_CTRL_LOWPRIO_MASK (0x20000000U)
Kojto 148:fd96258d940d 294 #define ADC_SEQ_CTRL_LOWPRIO_SHIFT (29U)
Kojto 148:fd96258d940d 295 #define ADC_SEQ_CTRL_LOWPRIO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_LOWPRIO_SHIFT)) & ADC_SEQ_CTRL_LOWPRIO_MASK)
Kojto 148:fd96258d940d 296 #define ADC_SEQ_CTRL_MODE_MASK (0x40000000U)
Kojto 148:fd96258d940d 297 #define ADC_SEQ_CTRL_MODE_SHIFT (30U)
Kojto 148:fd96258d940d 298 #define ADC_SEQ_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_MODE_SHIFT)) & ADC_SEQ_CTRL_MODE_MASK)
Kojto 148:fd96258d940d 299 #define ADC_SEQ_CTRL_SEQ_ENA_MASK (0x80000000U)
Kojto 148:fd96258d940d 300 #define ADC_SEQ_CTRL_SEQ_ENA_SHIFT (31U)
Kojto 148:fd96258d940d 301 #define ADC_SEQ_CTRL_SEQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SEQ_ENA_SHIFT)) & ADC_SEQ_CTRL_SEQ_ENA_MASK)
Kojto 148:fd96258d940d 302
Kojto 148:fd96258d940d 303 /* The count of ADC_SEQ_CTRL */
Kojto 148:fd96258d940d 304 #define ADC_SEQ_CTRL_COUNT (2U)
Kojto 148:fd96258d940d 305
Kojto 148:fd96258d940d 306 /*! @name SEQ_GDAT - ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n. */
Kojto 148:fd96258d940d 307 #define ADC_SEQ_GDAT_RESULT_MASK (0xFFF0U)
Kojto 148:fd96258d940d 308 #define ADC_SEQ_GDAT_RESULT_SHIFT (4U)
Kojto 148:fd96258d940d 309 #define ADC_SEQ_GDAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_RESULT_SHIFT)) & ADC_SEQ_GDAT_RESULT_MASK)
Kojto 148:fd96258d940d 310 #define ADC_SEQ_GDAT_THCMPRANGE_MASK (0x30000U)
Kojto 148:fd96258d940d 311 #define ADC_SEQ_GDAT_THCMPRANGE_SHIFT (16U)
Kojto 148:fd96258d940d 312 #define ADC_SEQ_GDAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPRANGE_SHIFT)) & ADC_SEQ_GDAT_THCMPRANGE_MASK)
Kojto 148:fd96258d940d 313 #define ADC_SEQ_GDAT_THCMPCROSS_MASK (0xC0000U)
Kojto 148:fd96258d940d 314 #define ADC_SEQ_GDAT_THCMPCROSS_SHIFT (18U)
Kojto 148:fd96258d940d 315 #define ADC_SEQ_GDAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPCROSS_SHIFT)) & ADC_SEQ_GDAT_THCMPCROSS_MASK)
Kojto 148:fd96258d940d 316 #define ADC_SEQ_GDAT_CHN_MASK (0x3C000000U)
Kojto 148:fd96258d940d 317 #define ADC_SEQ_GDAT_CHN_SHIFT (26U)
Kojto 148:fd96258d940d 318 #define ADC_SEQ_GDAT_CHN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_CHN_SHIFT)) & ADC_SEQ_GDAT_CHN_MASK)
Kojto 148:fd96258d940d 319 #define ADC_SEQ_GDAT_OVERRUN_MASK (0x40000000U)
Kojto 148:fd96258d940d 320 #define ADC_SEQ_GDAT_OVERRUN_SHIFT (30U)
Kojto 148:fd96258d940d 321 #define ADC_SEQ_GDAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_OVERRUN_SHIFT)) & ADC_SEQ_GDAT_OVERRUN_MASK)
Kojto 148:fd96258d940d 322 #define ADC_SEQ_GDAT_DATAVALID_MASK (0x80000000U)
Kojto 148:fd96258d940d 323 #define ADC_SEQ_GDAT_DATAVALID_SHIFT (31U)
Kojto 148:fd96258d940d 324 #define ADC_SEQ_GDAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_DATAVALID_SHIFT)) & ADC_SEQ_GDAT_DATAVALID_MASK)
Kojto 148:fd96258d940d 325
Kojto 148:fd96258d940d 326 /* The count of ADC_SEQ_GDAT */
Kojto 148:fd96258d940d 327 #define ADC_SEQ_GDAT_COUNT (2U)
Kojto 148:fd96258d940d 328
Kojto 148:fd96258d940d 329 /*! @name DAT - ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0. */
Kojto 148:fd96258d940d 330 #define ADC_DAT_RESULT_MASK (0xFFF0U)
Kojto 148:fd96258d940d 331 #define ADC_DAT_RESULT_SHIFT (4U)
Kojto 148:fd96258d940d 332 #define ADC_DAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_RESULT_SHIFT)) & ADC_DAT_RESULT_MASK)
Kojto 148:fd96258d940d 333 #define ADC_DAT_THCMPRANGE_MASK (0x30000U)
Kojto 148:fd96258d940d 334 #define ADC_DAT_THCMPRANGE_SHIFT (16U)
Kojto 148:fd96258d940d 335 #define ADC_DAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPRANGE_SHIFT)) & ADC_DAT_THCMPRANGE_MASK)
Kojto 148:fd96258d940d 336 #define ADC_DAT_THCMPCROSS_MASK (0xC0000U)
Kojto 148:fd96258d940d 337 #define ADC_DAT_THCMPCROSS_SHIFT (18U)
Kojto 148:fd96258d940d 338 #define ADC_DAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPCROSS_SHIFT)) & ADC_DAT_THCMPCROSS_MASK)
Kojto 148:fd96258d940d 339 #define ADC_DAT_CHANNEL_MASK (0x3C000000U)
Kojto 148:fd96258d940d 340 #define ADC_DAT_CHANNEL_SHIFT (26U)
Kojto 148:fd96258d940d 341 #define ADC_DAT_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_CHANNEL_SHIFT)) & ADC_DAT_CHANNEL_MASK)
Kojto 148:fd96258d940d 342 #define ADC_DAT_OVERRUN_MASK (0x40000000U)
Kojto 148:fd96258d940d 343 #define ADC_DAT_OVERRUN_SHIFT (30U)
Kojto 148:fd96258d940d 344 #define ADC_DAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_OVERRUN_SHIFT)) & ADC_DAT_OVERRUN_MASK)
Kojto 148:fd96258d940d 345 #define ADC_DAT_DATAVALID_MASK (0x80000000U)
Kojto 148:fd96258d940d 346 #define ADC_DAT_DATAVALID_SHIFT (31U)
Kojto 148:fd96258d940d 347 #define ADC_DAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_DATAVALID_SHIFT)) & ADC_DAT_DATAVALID_MASK)
Kojto 148:fd96258d940d 348
Kojto 148:fd96258d940d 349 /* The count of ADC_DAT */
Kojto 148:fd96258d940d 350 #define ADC_DAT_COUNT (12U)
Kojto 148:fd96258d940d 351
Kojto 148:fd96258d940d 352 /*! @name THR0_LOW - ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */
Kojto 148:fd96258d940d 353 #define ADC_THR0_LOW_THRLOW_MASK (0xFFF0U)
Kojto 148:fd96258d940d 354 #define ADC_THR0_LOW_THRLOW_SHIFT (4U)
Kojto 148:fd96258d940d 355 #define ADC_THR0_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_LOW_THRLOW_SHIFT)) & ADC_THR0_LOW_THRLOW_MASK)
Kojto 148:fd96258d940d 356
Kojto 148:fd96258d940d 357 /*! @name THR1_LOW - ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */
Kojto 148:fd96258d940d 358 #define ADC_THR1_LOW_THRLOW_MASK (0xFFF0U)
Kojto 148:fd96258d940d 359 #define ADC_THR1_LOW_THRLOW_SHIFT (4U)
Kojto 148:fd96258d940d 360 #define ADC_THR1_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_LOW_THRLOW_SHIFT)) & ADC_THR1_LOW_THRLOW_MASK)
Kojto 148:fd96258d940d 361
Kojto 148:fd96258d940d 362 /*! @name THR0_HIGH - ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */
Kojto 148:fd96258d940d 363 #define ADC_THR0_HIGH_THRHIGH_MASK (0xFFF0U)
Kojto 148:fd96258d940d 364 #define ADC_THR0_HIGH_THRHIGH_SHIFT (4U)
Kojto 148:fd96258d940d 365 #define ADC_THR0_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_HIGH_THRHIGH_SHIFT)) & ADC_THR0_HIGH_THRHIGH_MASK)
Kojto 148:fd96258d940d 366
Kojto 148:fd96258d940d 367 /*! @name THR1_HIGH - ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */
Kojto 148:fd96258d940d 368 #define ADC_THR1_HIGH_THRHIGH_MASK (0xFFF0U)
Kojto 148:fd96258d940d 369 #define ADC_THR1_HIGH_THRHIGH_SHIFT (4U)
Kojto 148:fd96258d940d 370 #define ADC_THR1_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_HIGH_THRHIGH_SHIFT)) & ADC_THR1_HIGH_THRHIGH_MASK)
Kojto 148:fd96258d940d 371
Kojto 148:fd96258d940d 372 /*! @name CHAN_THRSEL - ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel */
Kojto 148:fd96258d940d 373 #define ADC_CHAN_THRSEL_CH0_THRSEL_MASK (0x1U)
Kojto 148:fd96258d940d 374 #define ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT (0U)
Kojto 148:fd96258d940d 375 #define ADC_CHAN_THRSEL_CH0_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH0_THRSEL_MASK)
Kojto 148:fd96258d940d 376 #define ADC_CHAN_THRSEL_CH1_THRSEL_MASK (0x2U)
Kojto 148:fd96258d940d 377 #define ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT (1U)
Kojto 148:fd96258d940d 378 #define ADC_CHAN_THRSEL_CH1_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH1_THRSEL_MASK)
Kojto 148:fd96258d940d 379 #define ADC_CHAN_THRSEL_CH2_THRSEL_MASK (0x4U)
Kojto 148:fd96258d940d 380 #define ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT (2U)
Kojto 148:fd96258d940d 381 #define ADC_CHAN_THRSEL_CH2_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH2_THRSEL_MASK)
Kojto 148:fd96258d940d 382 #define ADC_CHAN_THRSEL_CH3_THRSEL_MASK (0x8U)
Kojto 148:fd96258d940d 383 #define ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT (3U)
Kojto 148:fd96258d940d 384 #define ADC_CHAN_THRSEL_CH3_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH3_THRSEL_MASK)
Kojto 148:fd96258d940d 385 #define ADC_CHAN_THRSEL_CH4_THRSEL_MASK (0x10U)
Kojto 148:fd96258d940d 386 #define ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT (4U)
Kojto 148:fd96258d940d 387 #define ADC_CHAN_THRSEL_CH4_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH4_THRSEL_MASK)
Kojto 148:fd96258d940d 388 #define ADC_CHAN_THRSEL_CH5_THRSEL_MASK (0x20U)
Kojto 148:fd96258d940d 389 #define ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT (5U)
Kojto 148:fd96258d940d 390 #define ADC_CHAN_THRSEL_CH5_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH5_THRSEL_MASK)
Kojto 148:fd96258d940d 391 #define ADC_CHAN_THRSEL_CH6_THRSEL_MASK (0x40U)
Kojto 148:fd96258d940d 392 #define ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT (6U)
Kojto 148:fd96258d940d 393 #define ADC_CHAN_THRSEL_CH6_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH6_THRSEL_MASK)
Kojto 148:fd96258d940d 394 #define ADC_CHAN_THRSEL_CH7_THRSEL_MASK (0x80U)
Kojto 148:fd96258d940d 395 #define ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT (7U)
Kojto 148:fd96258d940d 396 #define ADC_CHAN_THRSEL_CH7_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH7_THRSEL_MASK)
Kojto 148:fd96258d940d 397 #define ADC_CHAN_THRSEL_CH8_THRSEL_MASK (0x100U)
Kojto 148:fd96258d940d 398 #define ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT (8U)
Kojto 148:fd96258d940d 399 #define ADC_CHAN_THRSEL_CH8_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH8_THRSEL_MASK)
Kojto 148:fd96258d940d 400 #define ADC_CHAN_THRSEL_CH9_THRSEL_MASK (0x200U)
Kojto 148:fd96258d940d 401 #define ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT (9U)
Kojto 148:fd96258d940d 402 #define ADC_CHAN_THRSEL_CH9_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH9_THRSEL_MASK)
Kojto 148:fd96258d940d 403 #define ADC_CHAN_THRSEL_CH10_THRSEL_MASK (0x400U)
Kojto 148:fd96258d940d 404 #define ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT (10U)
Kojto 148:fd96258d940d 405 #define ADC_CHAN_THRSEL_CH10_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH10_THRSEL_MASK)
Kojto 148:fd96258d940d 406 #define ADC_CHAN_THRSEL_CH11_THRSEL_MASK (0x800U)
Kojto 148:fd96258d940d 407 #define ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT (11U)
Kojto 148:fd96258d940d 408 #define ADC_CHAN_THRSEL_CH11_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH11_THRSEL_MASK)
Kojto 148:fd96258d940d 409
Kojto 148:fd96258d940d 410 /*! @name INTEN - ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated. */
Kojto 148:fd96258d940d 411 #define ADC_INTEN_SEQA_INTEN_MASK (0x1U)
Kojto 148:fd96258d940d 412 #define ADC_INTEN_SEQA_INTEN_SHIFT (0U)
Kojto 148:fd96258d940d 413 #define ADC_INTEN_SEQA_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQA_INTEN_SHIFT)) & ADC_INTEN_SEQA_INTEN_MASK)
Kojto 148:fd96258d940d 414 #define ADC_INTEN_SEQB_INTEN_MASK (0x2U)
Kojto 148:fd96258d940d 415 #define ADC_INTEN_SEQB_INTEN_SHIFT (1U)
Kojto 148:fd96258d940d 416 #define ADC_INTEN_SEQB_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQB_INTEN_SHIFT)) & ADC_INTEN_SEQB_INTEN_MASK)
Kojto 148:fd96258d940d 417 #define ADC_INTEN_OVR_INTEN_MASK (0x4U)
Kojto 148:fd96258d940d 418 #define ADC_INTEN_OVR_INTEN_SHIFT (2U)
Kojto 148:fd96258d940d 419 #define ADC_INTEN_OVR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_OVR_INTEN_SHIFT)) & ADC_INTEN_OVR_INTEN_MASK)
Kojto 148:fd96258d940d 420 #define ADC_INTEN_ADCMPINTEN0_MASK (0x18U)
Kojto 148:fd96258d940d 421 #define ADC_INTEN_ADCMPINTEN0_SHIFT (3U)
Kojto 148:fd96258d940d 422 #define ADC_INTEN_ADCMPINTEN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN0_SHIFT)) & ADC_INTEN_ADCMPINTEN0_MASK)
Kojto 148:fd96258d940d 423 #define ADC_INTEN_ADCMPINTEN1_MASK (0x60U)
Kojto 148:fd96258d940d 424 #define ADC_INTEN_ADCMPINTEN1_SHIFT (5U)
Kojto 148:fd96258d940d 425 #define ADC_INTEN_ADCMPINTEN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN1_SHIFT)) & ADC_INTEN_ADCMPINTEN1_MASK)
Kojto 148:fd96258d940d 426 #define ADC_INTEN_ADCMPINTEN2_MASK (0x180U)
Kojto 148:fd96258d940d 427 #define ADC_INTEN_ADCMPINTEN2_SHIFT (7U)
Kojto 148:fd96258d940d 428 #define ADC_INTEN_ADCMPINTEN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN2_SHIFT)) & ADC_INTEN_ADCMPINTEN2_MASK)
Kojto 148:fd96258d940d 429 #define ADC_INTEN_ADCMPINTEN3_MASK (0x600U)
Kojto 148:fd96258d940d 430 #define ADC_INTEN_ADCMPINTEN3_SHIFT (9U)
Kojto 148:fd96258d940d 431 #define ADC_INTEN_ADCMPINTEN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN3_SHIFT)) & ADC_INTEN_ADCMPINTEN3_MASK)
Kojto 148:fd96258d940d 432 #define ADC_INTEN_ADCMPINTEN4_MASK (0x1800U)
Kojto 148:fd96258d940d 433 #define ADC_INTEN_ADCMPINTEN4_SHIFT (11U)
Kojto 148:fd96258d940d 434 #define ADC_INTEN_ADCMPINTEN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN4_SHIFT)) & ADC_INTEN_ADCMPINTEN4_MASK)
Kojto 148:fd96258d940d 435 #define ADC_INTEN_ADCMPINTEN5_MASK (0x6000U)
Kojto 148:fd96258d940d 436 #define ADC_INTEN_ADCMPINTEN5_SHIFT (13U)
Kojto 148:fd96258d940d 437 #define ADC_INTEN_ADCMPINTEN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN5_SHIFT)) & ADC_INTEN_ADCMPINTEN5_MASK)
Kojto 148:fd96258d940d 438 #define ADC_INTEN_ADCMPINTEN6_MASK (0x18000U)
Kojto 148:fd96258d940d 439 #define ADC_INTEN_ADCMPINTEN6_SHIFT (15U)
Kojto 148:fd96258d940d 440 #define ADC_INTEN_ADCMPINTEN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN6_SHIFT)) & ADC_INTEN_ADCMPINTEN6_MASK)
Kojto 148:fd96258d940d 441 #define ADC_INTEN_ADCMPINTEN7_MASK (0x60000U)
Kojto 148:fd96258d940d 442 #define ADC_INTEN_ADCMPINTEN7_SHIFT (17U)
Kojto 148:fd96258d940d 443 #define ADC_INTEN_ADCMPINTEN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN7_SHIFT)) & ADC_INTEN_ADCMPINTEN7_MASK)
Kojto 148:fd96258d940d 444 #define ADC_INTEN_ADCMPINTEN8_MASK (0x180000U)
Kojto 148:fd96258d940d 445 #define ADC_INTEN_ADCMPINTEN8_SHIFT (19U)
Kojto 148:fd96258d940d 446 #define ADC_INTEN_ADCMPINTEN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN8_SHIFT)) & ADC_INTEN_ADCMPINTEN8_MASK)
Kojto 148:fd96258d940d 447 #define ADC_INTEN_ADCMPINTEN9_MASK (0x600000U)
Kojto 148:fd96258d940d 448 #define ADC_INTEN_ADCMPINTEN9_SHIFT (21U)
Kojto 148:fd96258d940d 449 #define ADC_INTEN_ADCMPINTEN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN9_SHIFT)) & ADC_INTEN_ADCMPINTEN9_MASK)
Kojto 148:fd96258d940d 450 #define ADC_INTEN_ADCMPINTEN10_MASK (0x1800000U)
Kojto 148:fd96258d940d 451 #define ADC_INTEN_ADCMPINTEN10_SHIFT (23U)
Kojto 148:fd96258d940d 452 #define ADC_INTEN_ADCMPINTEN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN10_SHIFT)) & ADC_INTEN_ADCMPINTEN10_MASK)
Kojto 148:fd96258d940d 453 #define ADC_INTEN_ADCMPINTEN11_MASK (0x6000000U)
Kojto 148:fd96258d940d 454 #define ADC_INTEN_ADCMPINTEN11_SHIFT (25U)
Kojto 148:fd96258d940d 455 #define ADC_INTEN_ADCMPINTEN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN11_SHIFT)) & ADC_INTEN_ADCMPINTEN11_MASK)
Kojto 148:fd96258d940d 456
Kojto 148:fd96258d940d 457 /*! @name FLAGS - ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers). */
Kojto 148:fd96258d940d 458 #define ADC_FLAGS_THCMP0_MASK (0x1U)
Kojto 148:fd96258d940d 459 #define ADC_FLAGS_THCMP0_SHIFT (0U)
Kojto 148:fd96258d940d 460 #define ADC_FLAGS_THCMP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP0_SHIFT)) & ADC_FLAGS_THCMP0_MASK)
Kojto 148:fd96258d940d 461 #define ADC_FLAGS_THCMP1_MASK (0x2U)
Kojto 148:fd96258d940d 462 #define ADC_FLAGS_THCMP1_SHIFT (1U)
Kojto 148:fd96258d940d 463 #define ADC_FLAGS_THCMP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP1_SHIFT)) & ADC_FLAGS_THCMP1_MASK)
Kojto 148:fd96258d940d 464 #define ADC_FLAGS_THCMP2_MASK (0x4U)
Kojto 148:fd96258d940d 465 #define ADC_FLAGS_THCMP2_SHIFT (2U)
Kojto 148:fd96258d940d 466 #define ADC_FLAGS_THCMP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP2_SHIFT)) & ADC_FLAGS_THCMP2_MASK)
Kojto 148:fd96258d940d 467 #define ADC_FLAGS_THCMP3_MASK (0x8U)
Kojto 148:fd96258d940d 468 #define ADC_FLAGS_THCMP3_SHIFT (3U)
Kojto 148:fd96258d940d 469 #define ADC_FLAGS_THCMP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP3_SHIFT)) & ADC_FLAGS_THCMP3_MASK)
Kojto 148:fd96258d940d 470 #define ADC_FLAGS_THCMP4_MASK (0x10U)
Kojto 148:fd96258d940d 471 #define ADC_FLAGS_THCMP4_SHIFT (4U)
Kojto 148:fd96258d940d 472 #define ADC_FLAGS_THCMP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP4_SHIFT)) & ADC_FLAGS_THCMP4_MASK)
Kojto 148:fd96258d940d 473 #define ADC_FLAGS_THCMP5_MASK (0x20U)
Kojto 148:fd96258d940d 474 #define ADC_FLAGS_THCMP5_SHIFT (5U)
Kojto 148:fd96258d940d 475 #define ADC_FLAGS_THCMP5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP5_SHIFT)) & ADC_FLAGS_THCMP5_MASK)
Kojto 148:fd96258d940d 476 #define ADC_FLAGS_THCMP6_MASK (0x40U)
Kojto 148:fd96258d940d 477 #define ADC_FLAGS_THCMP6_SHIFT (6U)
Kojto 148:fd96258d940d 478 #define ADC_FLAGS_THCMP6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP6_SHIFT)) & ADC_FLAGS_THCMP6_MASK)
Kojto 148:fd96258d940d 479 #define ADC_FLAGS_THCMP7_MASK (0x80U)
Kojto 148:fd96258d940d 480 #define ADC_FLAGS_THCMP7_SHIFT (7U)
Kojto 148:fd96258d940d 481 #define ADC_FLAGS_THCMP7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP7_SHIFT)) & ADC_FLAGS_THCMP7_MASK)
Kojto 148:fd96258d940d 482 #define ADC_FLAGS_THCMP8_MASK (0x100U)
Kojto 148:fd96258d940d 483 #define ADC_FLAGS_THCMP8_SHIFT (8U)
Kojto 148:fd96258d940d 484 #define ADC_FLAGS_THCMP8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP8_SHIFT)) & ADC_FLAGS_THCMP8_MASK)
Kojto 148:fd96258d940d 485 #define ADC_FLAGS_THCMP9_MASK (0x200U)
Kojto 148:fd96258d940d 486 #define ADC_FLAGS_THCMP9_SHIFT (9U)
Kojto 148:fd96258d940d 487 #define ADC_FLAGS_THCMP9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP9_SHIFT)) & ADC_FLAGS_THCMP9_MASK)
Kojto 148:fd96258d940d 488 #define ADC_FLAGS_THCMP10_MASK (0x400U)
Kojto 148:fd96258d940d 489 #define ADC_FLAGS_THCMP10_SHIFT (10U)
Kojto 148:fd96258d940d 490 #define ADC_FLAGS_THCMP10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP10_SHIFT)) & ADC_FLAGS_THCMP10_MASK)
Kojto 148:fd96258d940d 491 #define ADC_FLAGS_THCMP11_MASK (0x800U)
Kojto 148:fd96258d940d 492 #define ADC_FLAGS_THCMP11_SHIFT (11U)
Kojto 148:fd96258d940d 493 #define ADC_FLAGS_THCMP11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP11_SHIFT)) & ADC_FLAGS_THCMP11_MASK)
Kojto 148:fd96258d940d 494 #define ADC_FLAGS_OVERRUN0_MASK (0x1000U)
Kojto 148:fd96258d940d 495 #define ADC_FLAGS_OVERRUN0_SHIFT (12U)
Kojto 148:fd96258d940d 496 #define ADC_FLAGS_OVERRUN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN0_SHIFT)) & ADC_FLAGS_OVERRUN0_MASK)
Kojto 148:fd96258d940d 497 #define ADC_FLAGS_OVERRUN1_MASK (0x2000U)
Kojto 148:fd96258d940d 498 #define ADC_FLAGS_OVERRUN1_SHIFT (13U)
Kojto 148:fd96258d940d 499 #define ADC_FLAGS_OVERRUN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN1_SHIFT)) & ADC_FLAGS_OVERRUN1_MASK)
Kojto 148:fd96258d940d 500 #define ADC_FLAGS_OVERRUN2_MASK (0x4000U)
Kojto 148:fd96258d940d 501 #define ADC_FLAGS_OVERRUN2_SHIFT (14U)
Kojto 148:fd96258d940d 502 #define ADC_FLAGS_OVERRUN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN2_SHIFT)) & ADC_FLAGS_OVERRUN2_MASK)
Kojto 148:fd96258d940d 503 #define ADC_FLAGS_OVERRUN3_MASK (0x8000U)
Kojto 148:fd96258d940d 504 #define ADC_FLAGS_OVERRUN3_SHIFT (15U)
Kojto 148:fd96258d940d 505 #define ADC_FLAGS_OVERRUN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN3_SHIFT)) & ADC_FLAGS_OVERRUN3_MASK)
Kojto 148:fd96258d940d 506 #define ADC_FLAGS_OVERRUN4_MASK (0x10000U)
Kojto 148:fd96258d940d 507 #define ADC_FLAGS_OVERRUN4_SHIFT (16U)
Kojto 148:fd96258d940d 508 #define ADC_FLAGS_OVERRUN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN4_SHIFT)) & ADC_FLAGS_OVERRUN4_MASK)
Kojto 148:fd96258d940d 509 #define ADC_FLAGS_OVERRUN5_MASK (0x20000U)
Kojto 148:fd96258d940d 510 #define ADC_FLAGS_OVERRUN5_SHIFT (17U)
Kojto 148:fd96258d940d 511 #define ADC_FLAGS_OVERRUN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN5_SHIFT)) & ADC_FLAGS_OVERRUN5_MASK)
Kojto 148:fd96258d940d 512 #define ADC_FLAGS_OVERRUN6_MASK (0x40000U)
Kojto 148:fd96258d940d 513 #define ADC_FLAGS_OVERRUN6_SHIFT (18U)
Kojto 148:fd96258d940d 514 #define ADC_FLAGS_OVERRUN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN6_SHIFT)) & ADC_FLAGS_OVERRUN6_MASK)
Kojto 148:fd96258d940d 515 #define ADC_FLAGS_OVERRUN7_MASK (0x80000U)
Kojto 148:fd96258d940d 516 #define ADC_FLAGS_OVERRUN7_SHIFT (19U)
Kojto 148:fd96258d940d 517 #define ADC_FLAGS_OVERRUN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN7_SHIFT)) & ADC_FLAGS_OVERRUN7_MASK)
Kojto 148:fd96258d940d 518 #define ADC_FLAGS_OVERRUN8_MASK (0x100000U)
Kojto 148:fd96258d940d 519 #define ADC_FLAGS_OVERRUN8_SHIFT (20U)
Kojto 148:fd96258d940d 520 #define ADC_FLAGS_OVERRUN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN8_SHIFT)) & ADC_FLAGS_OVERRUN8_MASK)
Kojto 148:fd96258d940d 521 #define ADC_FLAGS_OVERRUN9_MASK (0x200000U)
Kojto 148:fd96258d940d 522 #define ADC_FLAGS_OVERRUN9_SHIFT (21U)
Kojto 148:fd96258d940d 523 #define ADC_FLAGS_OVERRUN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN9_SHIFT)) & ADC_FLAGS_OVERRUN9_MASK)
Kojto 148:fd96258d940d 524 #define ADC_FLAGS_OVERRUN10_MASK (0x400000U)
Kojto 148:fd96258d940d 525 #define ADC_FLAGS_OVERRUN10_SHIFT (22U)
Kojto 148:fd96258d940d 526 #define ADC_FLAGS_OVERRUN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN10_SHIFT)) & ADC_FLAGS_OVERRUN10_MASK)
Kojto 148:fd96258d940d 527 #define ADC_FLAGS_OVERRUN11_MASK (0x800000U)
Kojto 148:fd96258d940d 528 #define ADC_FLAGS_OVERRUN11_SHIFT (23U)
Kojto 148:fd96258d940d 529 #define ADC_FLAGS_OVERRUN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN11_SHIFT)) & ADC_FLAGS_OVERRUN11_MASK)
Kojto 148:fd96258d940d 530 #define ADC_FLAGS_SEQA_OVR_MASK (0x1000000U)
Kojto 148:fd96258d940d 531 #define ADC_FLAGS_SEQA_OVR_SHIFT (24U)
Kojto 148:fd96258d940d 532 #define ADC_FLAGS_SEQA_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_OVR_SHIFT)) & ADC_FLAGS_SEQA_OVR_MASK)
Kojto 148:fd96258d940d 533 #define ADC_FLAGS_SEQB_OVR_MASK (0x2000000U)
Kojto 148:fd96258d940d 534 #define ADC_FLAGS_SEQB_OVR_SHIFT (25U)
Kojto 148:fd96258d940d 535 #define ADC_FLAGS_SEQB_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_OVR_SHIFT)) & ADC_FLAGS_SEQB_OVR_MASK)
Kojto 148:fd96258d940d 536 #define ADC_FLAGS_SEQA_INT_MASK (0x10000000U)
Kojto 148:fd96258d940d 537 #define ADC_FLAGS_SEQA_INT_SHIFT (28U)
Kojto 148:fd96258d940d 538 #define ADC_FLAGS_SEQA_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_INT_SHIFT)) & ADC_FLAGS_SEQA_INT_MASK)
Kojto 148:fd96258d940d 539 #define ADC_FLAGS_SEQB_INT_MASK (0x20000000U)
Kojto 148:fd96258d940d 540 #define ADC_FLAGS_SEQB_INT_SHIFT (29U)
Kojto 148:fd96258d940d 541 #define ADC_FLAGS_SEQB_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_INT_SHIFT)) & ADC_FLAGS_SEQB_INT_MASK)
Kojto 148:fd96258d940d 542 #define ADC_FLAGS_THCMP_INT_MASK (0x40000000U)
Kojto 148:fd96258d940d 543 #define ADC_FLAGS_THCMP_INT_SHIFT (30U)
Kojto 148:fd96258d940d 544 #define ADC_FLAGS_THCMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP_INT_SHIFT)) & ADC_FLAGS_THCMP_INT_MASK)
Kojto 148:fd96258d940d 545 #define ADC_FLAGS_OVR_INT_MASK (0x80000000U)
Kojto 148:fd96258d940d 546 #define ADC_FLAGS_OVR_INT_SHIFT (31U)
Kojto 148:fd96258d940d 547 #define ADC_FLAGS_OVR_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVR_INT_SHIFT)) & ADC_FLAGS_OVR_INT_MASK)
Kojto 148:fd96258d940d 548
Kojto 148:fd96258d940d 549 /*! @name STARTUP - ADC Startup register. */
Kojto 148:fd96258d940d 550 #define ADC_STARTUP_ADC_ENA_MASK (0x1U)
Kojto 148:fd96258d940d 551 #define ADC_STARTUP_ADC_ENA_SHIFT (0U)
Kojto 148:fd96258d940d 552 #define ADC_STARTUP_ADC_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_ENA_SHIFT)) & ADC_STARTUP_ADC_ENA_MASK)
Kojto 148:fd96258d940d 553 #define ADC_STARTUP_ADC_INIT_MASK (0x2U)
Kojto 148:fd96258d940d 554 #define ADC_STARTUP_ADC_INIT_SHIFT (1U)
Kojto 148:fd96258d940d 555 #define ADC_STARTUP_ADC_INIT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_INIT_SHIFT)) & ADC_STARTUP_ADC_INIT_MASK)
Kojto 148:fd96258d940d 556
Kojto 148:fd96258d940d 557 /*! @name CALIB - ADC Calibration register. */
Kojto 148:fd96258d940d 558 #define ADC_CALIB_CALIB_MASK (0x1U)
Kojto 148:fd96258d940d 559 #define ADC_CALIB_CALIB_SHIFT (0U)
Kojto 148:fd96258d940d 560 #define ADC_CALIB_CALIB(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALIB_SHIFT)) & ADC_CALIB_CALIB_MASK)
Kojto 148:fd96258d940d 561 #define ADC_CALIB_CALREQD_MASK (0x2U)
Kojto 148:fd96258d940d 562 #define ADC_CALIB_CALREQD_SHIFT (1U)
Kojto 148:fd96258d940d 563 #define ADC_CALIB_CALREQD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALREQD_SHIFT)) & ADC_CALIB_CALREQD_MASK)
Kojto 148:fd96258d940d 564 #define ADC_CALIB_CALVALUE_MASK (0x1FCU)
Kojto 148:fd96258d940d 565 #define ADC_CALIB_CALVALUE_SHIFT (2U)
Kojto 148:fd96258d940d 566 #define ADC_CALIB_CALVALUE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALVALUE_SHIFT)) & ADC_CALIB_CALVALUE_MASK)
Kojto 148:fd96258d940d 567
Kojto 148:fd96258d940d 568
Kojto 148:fd96258d940d 569 /*!
Kojto 148:fd96258d940d 570 * @}
Kojto 148:fd96258d940d 571 */ /* end of group ADC_Register_Masks */
Kojto 148:fd96258d940d 572
Kojto 148:fd96258d940d 573
Kojto 148:fd96258d940d 574 /* ADC - Peripheral instance base addresses */
Kojto 148:fd96258d940d 575 /** Peripheral ADC0 base address */
Kojto 148:fd96258d940d 576 #define ADC0_BASE (0x400A0000u)
Kojto 148:fd96258d940d 577 /** Peripheral ADC0 base pointer */
Kojto 148:fd96258d940d 578 #define ADC0 ((ADC_Type *)ADC0_BASE)
Kojto 148:fd96258d940d 579 /** Array initializer of ADC peripheral base addresses */
Kojto 148:fd96258d940d 580 #define ADC_BASE_ADDRS { ADC0_BASE }
Kojto 148:fd96258d940d 581 /** Array initializer of ADC peripheral base pointers */
Kojto 148:fd96258d940d 582 #define ADC_BASE_PTRS { ADC0 }
Kojto 148:fd96258d940d 583 /** Interrupt vectors for the ADC peripheral type */
Kojto 148:fd96258d940d 584 #define ADC_SEQ_IRQS { ADC0_SEQA_IRQn, ADC0_SEQB_IRQn }
Kojto 148:fd96258d940d 585 #define ADC_THCMP_IRQS { ADC0_THCMP_IRQn }
Kojto 148:fd96258d940d 586
Kojto 148:fd96258d940d 587 /*!
Kojto 148:fd96258d940d 588 * @}
Kojto 148:fd96258d940d 589 */ /* end of group ADC_Peripheral_Access_Layer */
Kojto 148:fd96258d940d 590
Kojto 148:fd96258d940d 591
Kojto 148:fd96258d940d 592 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 593 -- ASYNC_SYSCON Peripheral Access Layer
Kojto 148:fd96258d940d 594 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 595
Kojto 148:fd96258d940d 596 /*!
Kojto 148:fd96258d940d 597 * @addtogroup ASYNC_SYSCON_Peripheral_Access_Layer ASYNC_SYSCON Peripheral Access Layer
Kojto 148:fd96258d940d 598 * @{
Kojto 148:fd96258d940d 599 */
Kojto 148:fd96258d940d 600
Kojto 148:fd96258d940d 601 /** ASYNC_SYSCON - Register Layout Typedef */
Kojto 148:fd96258d940d 602 typedef struct {
Kojto 148:fd96258d940d 603 __IO uint32_t ASYNCPRESETCTRL; /**< Async peripheral reset control, offset: 0x0 */
Kojto 148:fd96258d940d 604 __O uint32_t ASYNCPRESETCTRLSET; /**< Set bits in ASYNCPRESETCTRL, offset: 0x4 */
Kojto 148:fd96258d940d 605 __O uint32_t ASYNCPRESETCTRLCLR; /**< Clear bits in ASYNCPRESETCTRL, offset: 0x8 */
Kojto 148:fd96258d940d 606 uint8_t RESERVED_0[4];
Kojto 148:fd96258d940d 607 __IO uint32_t ASYNCAPBCLKCTRL; /**< Async peripheral clock control, offset: 0x10 */
Kojto 148:fd96258d940d 608 __O uint32_t ASYNCAPBCLKCTRLSET; /**< Set bits in ASYNCAPBCLKCTRL, offset: 0x14 */
Kojto 148:fd96258d940d 609 __O uint32_t ASYNCAPBCLKCTRLCLR; /**< Clear bits in ASYNCAPBCLKCTRL, offset: 0x18 */
Kojto 148:fd96258d940d 610 uint8_t RESERVED_1[4];
Kojto 148:fd96258d940d 611 __IO uint32_t ASYNCAPBCLKSELA; /**< Async APB clock source select A, offset: 0x20 */
Kojto 148:fd96258d940d 612 } ASYNC_SYSCON_Type;
Kojto 148:fd96258d940d 613
Kojto 148:fd96258d940d 614 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 615 -- ASYNC_SYSCON Register Masks
Kojto 148:fd96258d940d 616 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 617
Kojto 148:fd96258d940d 618 /*!
Kojto 148:fd96258d940d 619 * @addtogroup ASYNC_SYSCON_Register_Masks ASYNC_SYSCON Register Masks
Kojto 148:fd96258d940d 620 * @{
Kojto 148:fd96258d940d 621 */
Kojto 148:fd96258d940d 622
Kojto 148:fd96258d940d 623 /*! @name ASYNCPRESETCTRL - Async peripheral reset control */
Kojto 148:fd96258d940d 624 #define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK (0x2000U)
Kojto 148:fd96258d940d 625 #define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT (13U)
Kojto 148:fd96258d940d 626 #define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK)
Kojto 148:fd96258d940d 627 #define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK (0x4000U)
Kojto 148:fd96258d940d 628 #define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT (14U)
Kojto 148:fd96258d940d 629 #define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK)
Kojto 148:fd96258d940d 630
Kojto 148:fd96258d940d 631 /*! @name ASYNCPRESETCTRLSET - Set bits in ASYNCPRESETCTRL */
Kojto 148:fd96258d940d 632 #define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 633 #define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT (0U)
Kojto 148:fd96258d940d 634 #define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK)
Kojto 148:fd96258d940d 635
Kojto 148:fd96258d940d 636 /*! @name ASYNCPRESETCTRLCLR - Clear bits in ASYNCPRESETCTRL */
Kojto 148:fd96258d940d 637 #define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 638 #define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT (0U)
Kojto 148:fd96258d940d 639 #define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK)
Kojto 148:fd96258d940d 640
Kojto 148:fd96258d940d 641 /*! @name ASYNCAPBCLKCTRL - Async peripheral clock control */
Kojto 148:fd96258d940d 642 #define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK (0x2000U)
Kojto 148:fd96258d940d 643 #define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT (13U)
Kojto 148:fd96258d940d 644 #define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK)
Kojto 148:fd96258d940d 645 #define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK (0x4000U)
Kojto 148:fd96258d940d 646 #define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT (14U)
Kojto 148:fd96258d940d 647 #define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK)
Kojto 148:fd96258d940d 648
Kojto 148:fd96258d940d 649 /*! @name ASYNCAPBCLKCTRLSET - Set bits in ASYNCAPBCLKCTRL */
Kojto 148:fd96258d940d 650 #define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 651 #define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT (0U)
Kojto 148:fd96258d940d 652 #define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK)
Kojto 148:fd96258d940d 653
Kojto 148:fd96258d940d 654 /*! @name ASYNCAPBCLKCTRLCLR - Clear bits in ASYNCAPBCLKCTRL */
Kojto 148:fd96258d940d 655 #define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 656 #define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT (0U)
Kojto 148:fd96258d940d 657 #define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK)
Kojto 148:fd96258d940d 658
Kojto 148:fd96258d940d 659 /*! @name ASYNCAPBCLKSELA - Async APB clock source select A */
Kojto 148:fd96258d940d 660 #define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK (0x3U)
Kojto 148:fd96258d940d 661 #define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT (0U)
Kojto 148:fd96258d940d 662 #define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK)
Kojto 148:fd96258d940d 663
Kojto 148:fd96258d940d 664
Kojto 148:fd96258d940d 665 /*!
Kojto 148:fd96258d940d 666 * @}
Kojto 148:fd96258d940d 667 */ /* end of group ASYNC_SYSCON_Register_Masks */
Kojto 148:fd96258d940d 668
Kojto 148:fd96258d940d 669
Kojto 148:fd96258d940d 670 /* ASYNC_SYSCON - Peripheral instance base addresses */
Kojto 148:fd96258d940d 671 /** Peripheral ASYNC_SYSCON base address */
Kojto 148:fd96258d940d 672 #define ASYNC_SYSCON_BASE (0x40040000u)
Kojto 148:fd96258d940d 673 /** Peripheral ASYNC_SYSCON base pointer */
Kojto 148:fd96258d940d 674 #define ASYNC_SYSCON ((ASYNC_SYSCON_Type *)ASYNC_SYSCON_BASE)
Kojto 148:fd96258d940d 675 /** Array initializer of ASYNC_SYSCON peripheral base addresses */
Kojto 148:fd96258d940d 676 #define ASYNC_SYSCON_BASE_ADDRS { ASYNC_SYSCON_BASE }
Kojto 148:fd96258d940d 677 /** Array initializer of ASYNC_SYSCON peripheral base pointers */
Kojto 148:fd96258d940d 678 #define ASYNC_SYSCON_BASE_PTRS { ASYNC_SYSCON }
Kojto 148:fd96258d940d 679
Kojto 148:fd96258d940d 680 /*!
Kojto 148:fd96258d940d 681 * @}
Kojto 148:fd96258d940d 682 */ /* end of group ASYNC_SYSCON_Peripheral_Access_Layer */
Kojto 148:fd96258d940d 683
Kojto 148:fd96258d940d 684
Kojto 148:fd96258d940d 685 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 686 -- CRC Peripheral Access Layer
Kojto 148:fd96258d940d 687 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 688
Kojto 148:fd96258d940d 689 /*!
Kojto 148:fd96258d940d 690 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
Kojto 148:fd96258d940d 691 * @{
Kojto 148:fd96258d940d 692 */
Kojto 148:fd96258d940d 693
Kojto 148:fd96258d940d 694 /** CRC - Register Layout Typedef */
Kojto 148:fd96258d940d 695 typedef struct {
Kojto 148:fd96258d940d 696 __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */
Kojto 148:fd96258d940d 697 __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */
Kojto 148:fd96258d940d 698 union { /* offset: 0x8 */
Kojto 148:fd96258d940d 699 __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */
Kojto 148:fd96258d940d 700 __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */
Kojto 148:fd96258d940d 701 };
Kojto 148:fd96258d940d 702 } CRC_Type;
Kojto 148:fd96258d940d 703
Kojto 148:fd96258d940d 704 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 705 -- CRC Register Masks
Kojto 148:fd96258d940d 706 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 707
Kojto 148:fd96258d940d 708 /*!
Kojto 148:fd96258d940d 709 * @addtogroup CRC_Register_Masks CRC Register Masks
Kojto 148:fd96258d940d 710 * @{
Kojto 148:fd96258d940d 711 */
Kojto 148:fd96258d940d 712
Kojto 148:fd96258d940d 713 /*! @name MODE - CRC mode register */
Kojto 148:fd96258d940d 714 #define CRC_MODE_CRC_POLY_MASK (0x3U)
Kojto 148:fd96258d940d 715 #define CRC_MODE_CRC_POLY_SHIFT (0U)
Kojto 148:fd96258d940d 716 #define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK)
Kojto 148:fd96258d940d 717 #define CRC_MODE_BIT_RVS_WR_MASK (0x4U)
Kojto 148:fd96258d940d 718 #define CRC_MODE_BIT_RVS_WR_SHIFT (2U)
Kojto 148:fd96258d940d 719 #define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK)
Kojto 148:fd96258d940d 720 #define CRC_MODE_CMPL_WR_MASK (0x8U)
Kojto 148:fd96258d940d 721 #define CRC_MODE_CMPL_WR_SHIFT (3U)
Kojto 148:fd96258d940d 722 #define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK)
Kojto 148:fd96258d940d 723 #define CRC_MODE_BIT_RVS_SUM_MASK (0x10U)
Kojto 148:fd96258d940d 724 #define CRC_MODE_BIT_RVS_SUM_SHIFT (4U)
Kojto 148:fd96258d940d 725 #define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK)
Kojto 148:fd96258d940d 726 #define CRC_MODE_CMPL_SUM_MASK (0x20U)
Kojto 148:fd96258d940d 727 #define CRC_MODE_CMPL_SUM_SHIFT (5U)
Kojto 148:fd96258d940d 728 #define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK)
Kojto 148:fd96258d940d 729
Kojto 148:fd96258d940d 730 /*! @name SEED - CRC seed register */
Kojto 148:fd96258d940d 731 #define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 732 #define CRC_SEED_CRC_SEED_SHIFT (0U)
Kojto 148:fd96258d940d 733 #define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK)
Kojto 148:fd96258d940d 734
Kojto 148:fd96258d940d 735 /*! @name SUM - CRC checksum register */
Kojto 148:fd96258d940d 736 #define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 737 #define CRC_SUM_CRC_SUM_SHIFT (0U)
Kojto 148:fd96258d940d 738 #define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK)
Kojto 148:fd96258d940d 739
Kojto 148:fd96258d940d 740 /*! @name WR_DATA - CRC data register */
Kojto 148:fd96258d940d 741 #define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 742 #define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U)
Kojto 148:fd96258d940d 743 #define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK)
Kojto 148:fd96258d940d 744
Kojto 148:fd96258d940d 745
Kojto 148:fd96258d940d 746 /*!
Kojto 148:fd96258d940d 747 * @}
Kojto 148:fd96258d940d 748 */ /* end of group CRC_Register_Masks */
Kojto 148:fd96258d940d 749
Kojto 148:fd96258d940d 750
Kojto 148:fd96258d940d 751 /* CRC - Peripheral instance base addresses */
Kojto 148:fd96258d940d 752 /** Peripheral CRC_ENGINE base address */
Kojto 148:fd96258d940d 753 #define CRC_ENGINE_BASE (0x40095000u)
Kojto 148:fd96258d940d 754 /** Peripheral CRC_ENGINE base pointer */
Kojto 148:fd96258d940d 755 #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE)
Kojto 148:fd96258d940d 756 /** Array initializer of CRC peripheral base addresses */
Kojto 148:fd96258d940d 757 #define CRC_BASE_ADDRS { CRC_ENGINE_BASE }
Kojto 148:fd96258d940d 758 /** Array initializer of CRC peripheral base pointers */
Kojto 148:fd96258d940d 759 #define CRC_BASE_PTRS { CRC_ENGINE }
Kojto 148:fd96258d940d 760
Kojto 148:fd96258d940d 761 /*!
Kojto 148:fd96258d940d 762 * @}
Kojto 148:fd96258d940d 763 */ /* end of group CRC_Peripheral_Access_Layer */
Kojto 148:fd96258d940d 764
Kojto 148:fd96258d940d 765
Kojto 148:fd96258d940d 766 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 767 -- CTIMER Peripheral Access Layer
Kojto 148:fd96258d940d 768 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 769
Kojto 148:fd96258d940d 770 /*!
Kojto 148:fd96258d940d 771 * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer
Kojto 148:fd96258d940d 772 * @{
Kojto 148:fd96258d940d 773 */
Kojto 148:fd96258d940d 774
Kojto 148:fd96258d940d 775 /** CTIMER - Register Layout Typedef */
Kojto 148:fd96258d940d 776 typedef struct {
Kojto 148:fd96258d940d 777 __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */
Kojto 148:fd96258d940d 778 __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */
Kojto 148:fd96258d940d 779 __IO uint32_t TC; /**< Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR., offset: 0x8 */
Kojto 148:fd96258d940d 780 __IO uint32_t PR; /**< Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC., offset: 0xC */
Kojto 148:fd96258d940d 781 __IO uint32_t PC; /**< Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface., offset: 0x10 */
Kojto 148:fd96258d940d 782 __IO uint32_t MCR; /**< Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs., offset: 0x14 */
Kojto 148:fd96258d940d 783 __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */
Kojto 148:fd96258d940d 784 __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */
Kojto 148:fd96258d940d 785 __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */
Kojto 148:fd96258d940d 786 __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */
Kojto 148:fd96258d940d 787 uint8_t RESERVED_0[48];
Kojto 148:fd96258d940d 788 __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */
Kojto 148:fd96258d940d 789 __IO uint32_t PWMC; /**< PWM Control Register. The PWMCON enables PWM mode for the external match pins., offset: 0x74 */
Kojto 148:fd96258d940d 790 } CTIMER_Type;
Kojto 148:fd96258d940d 791
Kojto 148:fd96258d940d 792 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 793 -- CTIMER Register Masks
Kojto 148:fd96258d940d 794 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 795
Kojto 148:fd96258d940d 796 /*!
Kojto 148:fd96258d940d 797 * @addtogroup CTIMER_Register_Masks CTIMER Register Masks
Kojto 148:fd96258d940d 798 * @{
Kojto 148:fd96258d940d 799 */
Kojto 148:fd96258d940d 800
Kojto 148:fd96258d940d 801 /*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
Kojto 148:fd96258d940d 802 #define CTIMER_IR_MR0INT_MASK (0x1U)
Kojto 148:fd96258d940d 803 #define CTIMER_IR_MR0INT_SHIFT (0U)
Kojto 148:fd96258d940d 804 #define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK)
Kojto 148:fd96258d940d 805 #define CTIMER_IR_MR1INT_MASK (0x2U)
Kojto 148:fd96258d940d 806 #define CTIMER_IR_MR1INT_SHIFT (1U)
Kojto 148:fd96258d940d 807 #define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK)
Kojto 148:fd96258d940d 808 #define CTIMER_IR_MR2INT_MASK (0x4U)
Kojto 148:fd96258d940d 809 #define CTIMER_IR_MR2INT_SHIFT (2U)
Kojto 148:fd96258d940d 810 #define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK)
Kojto 148:fd96258d940d 811 #define CTIMER_IR_MR3INT_MASK (0x8U)
Kojto 148:fd96258d940d 812 #define CTIMER_IR_MR3INT_SHIFT (3U)
Kojto 148:fd96258d940d 813 #define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK)
Kojto 148:fd96258d940d 814 #define CTIMER_IR_CR0INT_MASK (0x10U)
Kojto 148:fd96258d940d 815 #define CTIMER_IR_CR0INT_SHIFT (4U)
Kojto 148:fd96258d940d 816 #define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK)
Kojto 148:fd96258d940d 817 #define CTIMER_IR_CR1INT_MASK (0x20U)
Kojto 148:fd96258d940d 818 #define CTIMER_IR_CR1INT_SHIFT (5U)
Kojto 148:fd96258d940d 819 #define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK)
Kojto 148:fd96258d940d 820 #define CTIMER_IR_CR2INT_MASK (0x40U)
Kojto 148:fd96258d940d 821 #define CTIMER_IR_CR2INT_SHIFT (6U)
Kojto 148:fd96258d940d 822 #define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK)
Kojto 148:fd96258d940d 823 #define CTIMER_IR_CR3INT_MASK (0x80U)
Kojto 148:fd96258d940d 824 #define CTIMER_IR_CR3INT_SHIFT (7U)
Kojto 148:fd96258d940d 825 #define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK)
Kojto 148:fd96258d940d 826
Kojto 148:fd96258d940d 827 /*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
Kojto 148:fd96258d940d 828 #define CTIMER_TCR_CEN_MASK (0x1U)
Kojto 148:fd96258d940d 829 #define CTIMER_TCR_CEN_SHIFT (0U)
Kojto 148:fd96258d940d 830 #define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK)
Kojto 148:fd96258d940d 831 #define CTIMER_TCR_CRST_MASK (0x2U)
Kojto 148:fd96258d940d 832 #define CTIMER_TCR_CRST_SHIFT (1U)
Kojto 148:fd96258d940d 833 #define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK)
Kojto 148:fd96258d940d 834
Kojto 148:fd96258d940d 835 /*! @name TC - Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR. */
Kojto 148:fd96258d940d 836 #define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 837 #define CTIMER_TC_TCVAL_SHIFT (0U)
Kojto 148:fd96258d940d 838 #define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK)
Kojto 148:fd96258d940d 839
Kojto 148:fd96258d940d 840 /*! @name PR - Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC. */
Kojto 148:fd96258d940d 841 #define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 842 #define CTIMER_PR_PRVAL_SHIFT (0U)
Kojto 148:fd96258d940d 843 #define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK)
Kojto 148:fd96258d940d 844
Kojto 148:fd96258d940d 845 /*! @name PC - Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
Kojto 148:fd96258d940d 846 #define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 847 #define CTIMER_PC_PCVAL_SHIFT (0U)
Kojto 148:fd96258d940d 848 #define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK)
Kojto 148:fd96258d940d 849
Kojto 148:fd96258d940d 850 /*! @name MCR - Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
Kojto 148:fd96258d940d 851 #define CTIMER_MCR_MR0I_MASK (0x1U)
Kojto 148:fd96258d940d 852 #define CTIMER_MCR_MR0I_SHIFT (0U)
Kojto 148:fd96258d940d 853 #define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
Kojto 148:fd96258d940d 854 #define CTIMER_MCR_MR0R_MASK (0x2U)
Kojto 148:fd96258d940d 855 #define CTIMER_MCR_MR0R_SHIFT (1U)
Kojto 148:fd96258d940d 856 #define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK)
Kojto 148:fd96258d940d 857 #define CTIMER_MCR_MR0S_MASK (0x4U)
Kojto 148:fd96258d940d 858 #define CTIMER_MCR_MR0S_SHIFT (2U)
Kojto 148:fd96258d940d 859 #define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK)
Kojto 148:fd96258d940d 860 #define CTIMER_MCR_MR1I_MASK (0x8U)
Kojto 148:fd96258d940d 861 #define CTIMER_MCR_MR1I_SHIFT (3U)
Kojto 148:fd96258d940d 862 #define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK)
Kojto 148:fd96258d940d 863 #define CTIMER_MCR_MR1R_MASK (0x10U)
Kojto 148:fd96258d940d 864 #define CTIMER_MCR_MR1R_SHIFT (4U)
Kojto 148:fd96258d940d 865 #define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK)
Kojto 148:fd96258d940d 866 #define CTIMER_MCR_MR1S_MASK (0x20U)
Kojto 148:fd96258d940d 867 #define CTIMER_MCR_MR1S_SHIFT (5U)
Kojto 148:fd96258d940d 868 #define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK)
Kojto 148:fd96258d940d 869 #define CTIMER_MCR_MR2I_MASK (0x40U)
Kojto 148:fd96258d940d 870 #define CTIMER_MCR_MR2I_SHIFT (6U)
Kojto 148:fd96258d940d 871 #define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK)
Kojto 148:fd96258d940d 872 #define CTIMER_MCR_MR2R_MASK (0x80U)
Kojto 148:fd96258d940d 873 #define CTIMER_MCR_MR2R_SHIFT (7U)
Kojto 148:fd96258d940d 874 #define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK)
Kojto 148:fd96258d940d 875 #define CTIMER_MCR_MR2S_MASK (0x100U)
Kojto 148:fd96258d940d 876 #define CTIMER_MCR_MR2S_SHIFT (8U)
Kojto 148:fd96258d940d 877 #define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK)
Kojto 148:fd96258d940d 878 #define CTIMER_MCR_MR3I_MASK (0x200U)
Kojto 148:fd96258d940d 879 #define CTIMER_MCR_MR3I_SHIFT (9U)
Kojto 148:fd96258d940d 880 #define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK)
Kojto 148:fd96258d940d 881 #define CTIMER_MCR_MR3R_MASK (0x400U)
Kojto 148:fd96258d940d 882 #define CTIMER_MCR_MR3R_SHIFT (10U)
Kojto 148:fd96258d940d 883 #define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK)
Kojto 148:fd96258d940d 884 #define CTIMER_MCR_MR3S_MASK (0x800U)
Kojto 148:fd96258d940d 885 #define CTIMER_MCR_MR3S_SHIFT (11U)
Kojto 148:fd96258d940d 886 #define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK)
Kojto 148:fd96258d940d 887
Kojto 148:fd96258d940d 888 /*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
Kojto 148:fd96258d940d 889 #define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 890 #define CTIMER_MR_MATCH_SHIFT (0U)
Kojto 148:fd96258d940d 891 #define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK)
Kojto 148:fd96258d940d 892
Kojto 148:fd96258d940d 893 /* The count of CTIMER_MR */
Kojto 148:fd96258d940d 894 #define CTIMER_MR_COUNT (4U)
Kojto 148:fd96258d940d 895
Kojto 148:fd96258d940d 896 /*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
Kojto 148:fd96258d940d 897 #define CTIMER_CCR_CAP0RE_MASK (0x1U)
Kojto 148:fd96258d940d 898 #define CTIMER_CCR_CAP0RE_SHIFT (0U)
Kojto 148:fd96258d940d 899 #define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK)
Kojto 148:fd96258d940d 900 #define CTIMER_CCR_CAP0FE_MASK (0x2U)
Kojto 148:fd96258d940d 901 #define CTIMER_CCR_CAP0FE_SHIFT (1U)
Kojto 148:fd96258d940d 902 #define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK)
Kojto 148:fd96258d940d 903 #define CTIMER_CCR_CAP0I_MASK (0x4U)
Kojto 148:fd96258d940d 904 #define CTIMER_CCR_CAP0I_SHIFT (2U)
Kojto 148:fd96258d940d 905 #define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
Kojto 148:fd96258d940d 906 #define CTIMER_CCR_CAP1RE_MASK (0x8U)
Kojto 148:fd96258d940d 907 #define CTIMER_CCR_CAP1RE_SHIFT (3U)
Kojto 148:fd96258d940d 908 #define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK)
Kojto 148:fd96258d940d 909 #define CTIMER_CCR_CAP1FE_MASK (0x10U)
Kojto 148:fd96258d940d 910 #define CTIMER_CCR_CAP1FE_SHIFT (4U)
Kojto 148:fd96258d940d 911 #define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK)
Kojto 148:fd96258d940d 912 #define CTIMER_CCR_CAP1I_MASK (0x20U)
Kojto 148:fd96258d940d 913 #define CTIMER_CCR_CAP1I_SHIFT (5U)
Kojto 148:fd96258d940d 914 #define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK)
Kojto 148:fd96258d940d 915 #define CTIMER_CCR_CAP2RE_MASK (0x40U)
Kojto 148:fd96258d940d 916 #define CTIMER_CCR_CAP2RE_SHIFT (6U)
Kojto 148:fd96258d940d 917 #define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK)
Kojto 148:fd96258d940d 918 #define CTIMER_CCR_CAP2FE_MASK (0x80U)
Kojto 148:fd96258d940d 919 #define CTIMER_CCR_CAP2FE_SHIFT (7U)
Kojto 148:fd96258d940d 920 #define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK)
Kojto 148:fd96258d940d 921 #define CTIMER_CCR_CAP2I_MASK (0x100U)
Kojto 148:fd96258d940d 922 #define CTIMER_CCR_CAP2I_SHIFT (8U)
Kojto 148:fd96258d940d 923 #define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK)
Kojto 148:fd96258d940d 924 #define CTIMER_CCR_CAP3RE_MASK (0x200U)
Kojto 148:fd96258d940d 925 #define CTIMER_CCR_CAP3RE_SHIFT (9U)
Kojto 148:fd96258d940d 926 #define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK)
Kojto 148:fd96258d940d 927 #define CTIMER_CCR_CAP3FE_MASK (0x400U)
Kojto 148:fd96258d940d 928 #define CTIMER_CCR_CAP3FE_SHIFT (10U)
Kojto 148:fd96258d940d 929 #define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK)
Kojto 148:fd96258d940d 930 #define CTIMER_CCR_CAP3I_MASK (0x800U)
Kojto 148:fd96258d940d 931 #define CTIMER_CCR_CAP3I_SHIFT (11U)
Kojto 148:fd96258d940d 932 #define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK)
Kojto 148:fd96258d940d 933
Kojto 148:fd96258d940d 934 /*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */
Kojto 148:fd96258d940d 935 #define CTIMER_CR_CAP_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 936 #define CTIMER_CR_CAP_SHIFT (0U)
Kojto 148:fd96258d940d 937 #define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK)
Kojto 148:fd96258d940d 938
Kojto 148:fd96258d940d 939 /* The count of CTIMER_CR */
Kojto 148:fd96258d940d 940 #define CTIMER_CR_COUNT (4U)
Kojto 148:fd96258d940d 941
Kojto 148:fd96258d940d 942 /*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */
Kojto 148:fd96258d940d 943 #define CTIMER_EMR_EM0_MASK (0x1U)
Kojto 148:fd96258d940d 944 #define CTIMER_EMR_EM0_SHIFT (0U)
Kojto 148:fd96258d940d 945 #define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK)
Kojto 148:fd96258d940d 946 #define CTIMER_EMR_EM1_MASK (0x2U)
Kojto 148:fd96258d940d 947 #define CTIMER_EMR_EM1_SHIFT (1U)
Kojto 148:fd96258d940d 948 #define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK)
Kojto 148:fd96258d940d 949 #define CTIMER_EMR_EM2_MASK (0x4U)
Kojto 148:fd96258d940d 950 #define CTIMER_EMR_EM2_SHIFT (2U)
Kojto 148:fd96258d940d 951 #define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK)
Kojto 148:fd96258d940d 952 #define CTIMER_EMR_EM3_MASK (0x8U)
Kojto 148:fd96258d940d 953 #define CTIMER_EMR_EM3_SHIFT (3U)
Kojto 148:fd96258d940d 954 #define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK)
Kojto 148:fd96258d940d 955 #define CTIMER_EMR_EMC0_MASK (0x30U)
Kojto 148:fd96258d940d 956 #define CTIMER_EMR_EMC0_SHIFT (4U)
Kojto 148:fd96258d940d 957 #define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK)
Kojto 148:fd96258d940d 958 #define CTIMER_EMR_EMC1_MASK (0xC0U)
Kojto 148:fd96258d940d 959 #define CTIMER_EMR_EMC1_SHIFT (6U)
Kojto 148:fd96258d940d 960 #define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK)
Kojto 148:fd96258d940d 961 #define CTIMER_EMR_EMC2_MASK (0x300U)
Kojto 148:fd96258d940d 962 #define CTIMER_EMR_EMC2_SHIFT (8U)
Kojto 148:fd96258d940d 963 #define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK)
Kojto 148:fd96258d940d 964 #define CTIMER_EMR_EMC3_MASK (0xC00U)
Kojto 148:fd96258d940d 965 #define CTIMER_EMR_EMC3_SHIFT (10U)
Kojto 148:fd96258d940d 966 #define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK)
Kojto 148:fd96258d940d 967
Kojto 148:fd96258d940d 968 /*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
Kojto 148:fd96258d940d 969 #define CTIMER_CTCR_CTMODE_MASK (0x3U)
Kojto 148:fd96258d940d 970 #define CTIMER_CTCR_CTMODE_SHIFT (0U)
Kojto 148:fd96258d940d 971 #define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK)
Kojto 148:fd96258d940d 972 #define CTIMER_CTCR_CINSEL_MASK (0xCU)
Kojto 148:fd96258d940d 973 #define CTIMER_CTCR_CINSEL_SHIFT (2U)
Kojto 148:fd96258d940d 974 #define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK)
Kojto 148:fd96258d940d 975 #define CTIMER_CTCR_ENCC_MASK (0x10U)
Kojto 148:fd96258d940d 976 #define CTIMER_CTCR_ENCC_SHIFT (4U)
Kojto 148:fd96258d940d 977 #define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK)
Kojto 148:fd96258d940d 978 #define CTIMER_CTCR_SELCC_MASK (0xE0U)
Kojto 148:fd96258d940d 979 #define CTIMER_CTCR_SELCC_SHIFT (5U)
Kojto 148:fd96258d940d 980 #define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK)
Kojto 148:fd96258d940d 981
Kojto 148:fd96258d940d 982 /*! @name PWMC - PWM Control Register. The PWMCON enables PWM mode for the external match pins. */
Kojto 148:fd96258d940d 983 #define CTIMER_PWMC_PWMEN0_MASK (0x1U)
Kojto 148:fd96258d940d 984 #define CTIMER_PWMC_PWMEN0_SHIFT (0U)
Kojto 148:fd96258d940d 985 #define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK)
Kojto 148:fd96258d940d 986 #define CTIMER_PWMC_PWMEN1_MASK (0x2U)
Kojto 148:fd96258d940d 987 #define CTIMER_PWMC_PWMEN1_SHIFT (1U)
Kojto 148:fd96258d940d 988 #define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK)
Kojto 148:fd96258d940d 989 #define CTIMER_PWMC_PWMEN2_MASK (0x4U)
Kojto 148:fd96258d940d 990 #define CTIMER_PWMC_PWMEN2_SHIFT (2U)
Kojto 148:fd96258d940d 991 #define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK)
Kojto 148:fd96258d940d 992 #define CTIMER_PWMC_PWMEN3_MASK (0x8U)
Kojto 148:fd96258d940d 993 #define CTIMER_PWMC_PWMEN3_SHIFT (3U)
Kojto 148:fd96258d940d 994 #define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK)
Kojto 148:fd96258d940d 995
Kojto 148:fd96258d940d 996
Kojto 148:fd96258d940d 997 /*!
Kojto 148:fd96258d940d 998 * @}
Kojto 148:fd96258d940d 999 */ /* end of group CTIMER_Register_Masks */
Kojto 148:fd96258d940d 1000
Kojto 148:fd96258d940d 1001
Kojto 148:fd96258d940d 1002 /* CTIMER - Peripheral instance base addresses */
Kojto 148:fd96258d940d 1003 /** Peripheral CTIMER0 base address */
Kojto 148:fd96258d940d 1004 #define CTIMER0_BASE (0x40008000u)
Kojto 148:fd96258d940d 1005 /** Peripheral CTIMER0 base pointer */
Kojto 148:fd96258d940d 1006 #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE)
Kojto 148:fd96258d940d 1007 /** Peripheral CTIMER1 base address */
Kojto 148:fd96258d940d 1008 #define CTIMER1_BASE (0x40009000u)
Kojto 148:fd96258d940d 1009 /** Peripheral CTIMER1 base pointer */
Kojto 148:fd96258d940d 1010 #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE)
Kojto 148:fd96258d940d 1011 /** Peripheral CTIMER2 base address */
Kojto 148:fd96258d940d 1012 #define CTIMER2_BASE (0x40028000u)
Kojto 148:fd96258d940d 1013 /** Peripheral CTIMER2 base pointer */
Kojto 148:fd96258d940d 1014 #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE)
Kojto 148:fd96258d940d 1015 /** Peripheral CTIMER3 base address */
Kojto 148:fd96258d940d 1016 #define CTIMER3_BASE (0x40048000u)
Kojto 148:fd96258d940d 1017 /** Peripheral CTIMER3 base pointer */
Kojto 148:fd96258d940d 1018 #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE)
Kojto 148:fd96258d940d 1019 /** Peripheral CTIMER4 base address */
Kojto 148:fd96258d940d 1020 #define CTIMER4_BASE (0x40049000u)
Kojto 148:fd96258d940d 1021 /** Peripheral CTIMER4 base pointer */
Kojto 148:fd96258d940d 1022 #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE)
Kojto 148:fd96258d940d 1023 /** Array initializer of CTIMER peripheral base addresses */
Kojto 148:fd96258d940d 1024 #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE }
Kojto 148:fd96258d940d 1025 /** Array initializer of CTIMER peripheral base pointers */
Kojto 148:fd96258d940d 1026 #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 }
Kojto 148:fd96258d940d 1027 /** Interrupt vectors for the CTIMER peripheral type */
Kojto 148:fd96258d940d 1028 #define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn }
Kojto 148:fd96258d940d 1029
Kojto 148:fd96258d940d 1030 /*!
Kojto 148:fd96258d940d 1031 * @}
Kojto 148:fd96258d940d 1032 */ /* end of group CTIMER_Peripheral_Access_Layer */
Kojto 148:fd96258d940d 1033
Kojto 148:fd96258d940d 1034
Kojto 148:fd96258d940d 1035 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 1036 -- DMA Peripheral Access Layer
Kojto 148:fd96258d940d 1037 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 1038
Kojto 148:fd96258d940d 1039 /*!
Kojto 148:fd96258d940d 1040 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
Kojto 148:fd96258d940d 1041 * @{
Kojto 148:fd96258d940d 1042 */
Kojto 148:fd96258d940d 1043
Kojto 148:fd96258d940d 1044 /** DMA - Register Layout Typedef */
Kojto 148:fd96258d940d 1045 typedef struct {
Kojto 148:fd96258d940d 1046 __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */
Kojto 148:fd96258d940d 1047 __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */
Kojto 148:fd96258d940d 1048 __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */
Kojto 148:fd96258d940d 1049 uint8_t RESERVED_0[20];
Kojto 148:fd96258d940d 1050 struct { /* offset: 0x20, array step: 0x5C */
Kojto 148:fd96258d940d 1051 __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */
Kojto 148:fd96258d940d 1052 uint8_t RESERVED_0[4];
Kojto 148:fd96258d940d 1053 __O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */
Kojto 148:fd96258d940d 1054 uint8_t RESERVED_1[4];
Kojto 148:fd96258d940d 1055 __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */
Kojto 148:fd96258d940d 1056 uint8_t RESERVED_2[4];
Kojto 148:fd96258d940d 1057 __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */
Kojto 148:fd96258d940d 1058 uint8_t RESERVED_3[4];
Kojto 148:fd96258d940d 1059 __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */
Kojto 148:fd96258d940d 1060 uint8_t RESERVED_4[4];
Kojto 148:fd96258d940d 1061 __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */
Kojto 148:fd96258d940d 1062 uint8_t RESERVED_5[4];
Kojto 148:fd96258d940d 1063 __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */
Kojto 148:fd96258d940d 1064 uint8_t RESERVED_6[4];
Kojto 148:fd96258d940d 1065 __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */
Kojto 148:fd96258d940d 1066 uint8_t RESERVED_7[4];
Kojto 148:fd96258d940d 1067 __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */
Kojto 148:fd96258d940d 1068 uint8_t RESERVED_8[4];
Kojto 148:fd96258d940d 1069 __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */
Kojto 148:fd96258d940d 1070 uint8_t RESERVED_9[4];
Kojto 148:fd96258d940d 1071 __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */
Kojto 148:fd96258d940d 1072 uint8_t RESERVED_10[4];
Kojto 148:fd96258d940d 1073 __O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */
Kojto 148:fd96258d940d 1074 } COMMON[1];
Kojto 148:fd96258d940d 1075 uint8_t RESERVED_1[900];
Kojto 148:fd96258d940d 1076 struct { /* offset: 0x400, array step: 0x10 */
Kojto 148:fd96258d940d 1077 __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */
Kojto 148:fd96258d940d 1078 __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */
Kojto 148:fd96258d940d 1079 __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */
Kojto 148:fd96258d940d 1080 uint8_t RESERVED_0[4];
Kojto 148:fd96258d940d 1081 } CHANNEL[20];
Kojto 148:fd96258d940d 1082 } DMA_Type;
Kojto 148:fd96258d940d 1083
Kojto 148:fd96258d940d 1084 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 1085 -- DMA Register Masks
Kojto 148:fd96258d940d 1086 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 1087
Kojto 148:fd96258d940d 1088 /*!
Kojto 148:fd96258d940d 1089 * @addtogroup DMA_Register_Masks DMA Register Masks
Kojto 148:fd96258d940d 1090 * @{
Kojto 148:fd96258d940d 1091 */
Kojto 148:fd96258d940d 1092
Kojto 148:fd96258d940d 1093 /*! @name CTRL - DMA control. */
Kojto 148:fd96258d940d 1094 #define DMA_CTRL_ENABLE_MASK (0x1U)
Kojto 148:fd96258d940d 1095 #define DMA_CTRL_ENABLE_SHIFT (0U)
Kojto 148:fd96258d940d 1096 #define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK)
Kojto 148:fd96258d940d 1097
Kojto 148:fd96258d940d 1098 /*! @name INTSTAT - Interrupt status. */
Kojto 148:fd96258d940d 1099 #define DMA_INTSTAT_ACTIVEINT_MASK (0x2U)
Kojto 148:fd96258d940d 1100 #define DMA_INTSTAT_ACTIVEINT_SHIFT (1U)
Kojto 148:fd96258d940d 1101 #define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK)
Kojto 148:fd96258d940d 1102 #define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U)
Kojto 148:fd96258d940d 1103 #define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U)
Kojto 148:fd96258d940d 1104 #define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK)
Kojto 148:fd96258d940d 1105
Kojto 148:fd96258d940d 1106 /*! @name SRAMBASE - SRAM address of the channel configuration table. */
Kojto 148:fd96258d940d 1107 #define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U)
Kojto 148:fd96258d940d 1108 #define DMA_SRAMBASE_OFFSET_SHIFT (9U)
Kojto 148:fd96258d940d 1109 #define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK)
Kojto 148:fd96258d940d 1110
Kojto 148:fd96258d940d 1111 /*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */
Kojto 148:fd96258d940d 1112 #define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 1113 #define DMA_COMMON_ENABLESET_ENA_SHIFT (0U)
Kojto 148:fd96258d940d 1114 #define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK)
Kojto 148:fd96258d940d 1115
Kojto 148:fd96258d940d 1116 /* The count of DMA_COMMON_ENABLESET */
Kojto 148:fd96258d940d 1117 #define DMA_COMMON_ENABLESET_COUNT (1U)
Kojto 148:fd96258d940d 1118
Kojto 148:fd96258d940d 1119 /*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */
Kojto 148:fd96258d940d 1120 #define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 1121 #define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U)
Kojto 148:fd96258d940d 1122 #define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK)
Kojto 148:fd96258d940d 1123
Kojto 148:fd96258d940d 1124 /* The count of DMA_COMMON_ENABLECLR */
Kojto 148:fd96258d940d 1125 #define DMA_COMMON_ENABLECLR_COUNT (1U)
Kojto 148:fd96258d940d 1126
Kojto 148:fd96258d940d 1127 /*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */
Kojto 148:fd96258d940d 1128 #define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 1129 #define DMA_COMMON_ACTIVE_ACT_SHIFT (0U)
Kojto 148:fd96258d940d 1130 #define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK)
Kojto 148:fd96258d940d 1131
Kojto 148:fd96258d940d 1132 /* The count of DMA_COMMON_ACTIVE */
Kojto 148:fd96258d940d 1133 #define DMA_COMMON_ACTIVE_COUNT (1U)
Kojto 148:fd96258d940d 1134
Kojto 148:fd96258d940d 1135 /*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */
Kojto 148:fd96258d940d 1136 #define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 1137 #define DMA_COMMON_BUSY_BSY_SHIFT (0U)
Kojto 148:fd96258d940d 1138 #define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK)
Kojto 148:fd96258d940d 1139
Kojto 148:fd96258d940d 1140 /* The count of DMA_COMMON_BUSY */
Kojto 148:fd96258d940d 1141 #define DMA_COMMON_BUSY_COUNT (1U)
Kojto 148:fd96258d940d 1142
Kojto 148:fd96258d940d 1143 /*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */
Kojto 148:fd96258d940d 1144 #define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 1145 #define DMA_COMMON_ERRINT_ERR_SHIFT (0U)
Kojto 148:fd96258d940d 1146 #define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK)
Kojto 148:fd96258d940d 1147
Kojto 148:fd96258d940d 1148 /* The count of DMA_COMMON_ERRINT */
Kojto 148:fd96258d940d 1149 #define DMA_COMMON_ERRINT_COUNT (1U)
Kojto 148:fd96258d940d 1150
Kojto 148:fd96258d940d 1151 /*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */
Kojto 148:fd96258d940d 1152 #define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 1153 #define DMA_COMMON_INTENSET_INTEN_SHIFT (0U)
Kojto 148:fd96258d940d 1154 #define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK)
Kojto 148:fd96258d940d 1155
Kojto 148:fd96258d940d 1156 /* The count of DMA_COMMON_INTENSET */
Kojto 148:fd96258d940d 1157 #define DMA_COMMON_INTENSET_COUNT (1U)
Kojto 148:fd96258d940d 1158
Kojto 148:fd96258d940d 1159 /*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */
Kojto 148:fd96258d940d 1160 #define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 1161 #define DMA_COMMON_INTENCLR_CLR_SHIFT (0U)
Kojto 148:fd96258d940d 1162 #define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK)
Kojto 148:fd96258d940d 1163
Kojto 148:fd96258d940d 1164 /* The count of DMA_COMMON_INTENCLR */
Kojto 148:fd96258d940d 1165 #define DMA_COMMON_INTENCLR_COUNT (1U)
Kojto 148:fd96258d940d 1166
Kojto 148:fd96258d940d 1167 /*! @name COMMON_INTA - Interrupt A status for all DMA channels. */
Kojto 148:fd96258d940d 1168 #define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 1169 #define DMA_COMMON_INTA_IA_SHIFT (0U)
Kojto 148:fd96258d940d 1170 #define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK)
Kojto 148:fd96258d940d 1171
Kojto 148:fd96258d940d 1172 /* The count of DMA_COMMON_INTA */
Kojto 148:fd96258d940d 1173 #define DMA_COMMON_INTA_COUNT (1U)
Kojto 148:fd96258d940d 1174
Kojto 148:fd96258d940d 1175 /*! @name COMMON_INTB - Interrupt B status for all DMA channels. */
Kojto 148:fd96258d940d 1176 #define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 1177 #define DMA_COMMON_INTB_IB_SHIFT (0U)
Kojto 148:fd96258d940d 1178 #define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK)
Kojto 148:fd96258d940d 1179
Kojto 148:fd96258d940d 1180 /* The count of DMA_COMMON_INTB */
Kojto 148:fd96258d940d 1181 #define DMA_COMMON_INTB_COUNT (1U)
Kojto 148:fd96258d940d 1182
Kojto 148:fd96258d940d 1183 /*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */
Kojto 148:fd96258d940d 1184 #define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 1185 #define DMA_COMMON_SETVALID_SV_SHIFT (0U)
Kojto 148:fd96258d940d 1186 #define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK)
Kojto 148:fd96258d940d 1187
Kojto 148:fd96258d940d 1188 /* The count of DMA_COMMON_SETVALID */
Kojto 148:fd96258d940d 1189 #define DMA_COMMON_SETVALID_COUNT (1U)
Kojto 148:fd96258d940d 1190
Kojto 148:fd96258d940d 1191 /*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */
Kojto 148:fd96258d940d 1192 #define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 1193 #define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U)
Kojto 148:fd96258d940d 1194 #define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK)
Kojto 148:fd96258d940d 1195
Kojto 148:fd96258d940d 1196 /* The count of DMA_COMMON_SETTRIG */
Kojto 148:fd96258d940d 1197 #define DMA_COMMON_SETTRIG_COUNT (1U)
Kojto 148:fd96258d940d 1198
Kojto 148:fd96258d940d 1199 /*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */
Kojto 148:fd96258d940d 1200 #define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 1201 #define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U)
Kojto 148:fd96258d940d 1202 #define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK)
Kojto 148:fd96258d940d 1203
Kojto 148:fd96258d940d 1204 /* The count of DMA_COMMON_ABORT */
Kojto 148:fd96258d940d 1205 #define DMA_COMMON_ABORT_COUNT (1U)
Kojto 148:fd96258d940d 1206
Kojto 148:fd96258d940d 1207 /*! @name CHANNEL_CFG - Configuration register for DMA channel . */
Kojto 148:fd96258d940d 1208 #define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U)
Kojto 148:fd96258d940d 1209 #define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U)
Kojto 148:fd96258d940d 1210 #define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK)
Kojto 148:fd96258d940d 1211 #define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U)
Kojto 148:fd96258d940d 1212 #define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U)
Kojto 148:fd96258d940d 1213 #define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK)
Kojto 148:fd96258d940d 1214 #define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U)
Kojto 148:fd96258d940d 1215 #define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U)
Kojto 148:fd96258d940d 1216 #define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK)
Kojto 148:fd96258d940d 1217 #define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U)
Kojto 148:fd96258d940d 1218 #define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U)
Kojto 148:fd96258d940d 1219 #define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK)
Kojto 148:fd96258d940d 1220 #define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U)
Kojto 148:fd96258d940d 1221 #define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U)
Kojto 148:fd96258d940d 1222 #define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK)
Kojto 148:fd96258d940d 1223 #define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U)
Kojto 148:fd96258d940d 1224 #define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U)
Kojto 148:fd96258d940d 1225 #define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK)
Kojto 148:fd96258d940d 1226 #define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U)
Kojto 148:fd96258d940d 1227 #define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U)
Kojto 148:fd96258d940d 1228 #define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK)
Kojto 148:fd96258d940d 1229 #define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U)
Kojto 148:fd96258d940d 1230 #define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U)
Kojto 148:fd96258d940d 1231 #define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK)
Kojto 148:fd96258d940d 1232 #define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U)
Kojto 148:fd96258d940d 1233 #define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U)
Kojto 148:fd96258d940d 1234 #define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK)
Kojto 148:fd96258d940d 1235
Kojto 148:fd96258d940d 1236 /* The count of DMA_CHANNEL_CFG */
Kojto 148:fd96258d940d 1237 #define DMA_CHANNEL_CFG_COUNT (20U)
Kojto 148:fd96258d940d 1238
Kojto 148:fd96258d940d 1239 /*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */
Kojto 148:fd96258d940d 1240 #define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U)
Kojto 148:fd96258d940d 1241 #define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U)
Kojto 148:fd96258d940d 1242 #define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK)
Kojto 148:fd96258d940d 1243 #define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U)
Kojto 148:fd96258d940d 1244 #define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U)
Kojto 148:fd96258d940d 1245 #define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK)
Kojto 148:fd96258d940d 1246
Kojto 148:fd96258d940d 1247 /* The count of DMA_CHANNEL_CTLSTAT */
Kojto 148:fd96258d940d 1248 #define DMA_CHANNEL_CTLSTAT_COUNT (20U)
Kojto 148:fd96258d940d 1249
Kojto 148:fd96258d940d 1250 /*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */
Kojto 148:fd96258d940d 1251 #define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U)
Kojto 148:fd96258d940d 1252 #define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U)
Kojto 148:fd96258d940d 1253 #define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK)
Kojto 148:fd96258d940d 1254 #define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U)
Kojto 148:fd96258d940d 1255 #define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U)
Kojto 148:fd96258d940d 1256 #define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK)
Kojto 148:fd96258d940d 1257 #define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U)
Kojto 148:fd96258d940d 1258 #define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U)
Kojto 148:fd96258d940d 1259 #define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK)
Kojto 148:fd96258d940d 1260 #define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U)
Kojto 148:fd96258d940d 1261 #define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U)
Kojto 148:fd96258d940d 1262 #define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK)
Kojto 148:fd96258d940d 1263 #define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U)
Kojto 148:fd96258d940d 1264 #define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U)
Kojto 148:fd96258d940d 1265 #define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK)
Kojto 148:fd96258d940d 1266 #define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U)
Kojto 148:fd96258d940d 1267 #define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U)
Kojto 148:fd96258d940d 1268 #define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK)
Kojto 148:fd96258d940d 1269 #define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U)
Kojto 148:fd96258d940d 1270 #define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U)
Kojto 148:fd96258d940d 1271 #define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK)
Kojto 148:fd96258d940d 1272 #define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U)
Kojto 148:fd96258d940d 1273 #define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U)
Kojto 148:fd96258d940d 1274 #define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK)
Kojto 148:fd96258d940d 1275 #define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U)
Kojto 148:fd96258d940d 1276 #define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U)
Kojto 148:fd96258d940d 1277 #define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK)
Kojto 148:fd96258d940d 1278 #define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U)
Kojto 148:fd96258d940d 1279 #define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U)
Kojto 148:fd96258d940d 1280 #define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK)
Kojto 148:fd96258d940d 1281
Kojto 148:fd96258d940d 1282 /* The count of DMA_CHANNEL_XFERCFG */
Kojto 148:fd96258d940d 1283 #define DMA_CHANNEL_XFERCFG_COUNT (20U)
Kojto 148:fd96258d940d 1284
Kojto 148:fd96258d940d 1285
Kojto 148:fd96258d940d 1286 /*!
Kojto 148:fd96258d940d 1287 * @}
Kojto 148:fd96258d940d 1288 */ /* end of group DMA_Register_Masks */
Kojto 148:fd96258d940d 1289
Kojto 148:fd96258d940d 1290
Kojto 148:fd96258d940d 1291 /* DMA - Peripheral instance base addresses */
Kojto 148:fd96258d940d 1292 /** Peripheral DMA0 base address */
Kojto 148:fd96258d940d 1293 #define DMA0_BASE (0x40082000u)
Kojto 148:fd96258d940d 1294 /** Peripheral DMA0 base pointer */
Kojto 148:fd96258d940d 1295 #define DMA0 ((DMA_Type *)DMA0_BASE)
Kojto 148:fd96258d940d 1296 /** Array initializer of DMA peripheral base addresses */
Kojto 148:fd96258d940d 1297 #define DMA_BASE_ADDRS { DMA0_BASE }
Kojto 148:fd96258d940d 1298 /** Array initializer of DMA peripheral base pointers */
Kojto 148:fd96258d940d 1299 #define DMA_BASE_PTRS { DMA0 }
Kojto 148:fd96258d940d 1300 /** Interrupt vectors for the DMA peripheral type */
Kojto 148:fd96258d940d 1301 #define DMA_IRQS { DMA0_IRQn }
Kojto 148:fd96258d940d 1302
Kojto 148:fd96258d940d 1303 /*!
Kojto 148:fd96258d940d 1304 * @}
Kojto 148:fd96258d940d 1305 */ /* end of group DMA_Peripheral_Access_Layer */
Kojto 148:fd96258d940d 1306
Kojto 148:fd96258d940d 1307
Kojto 148:fd96258d940d 1308 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 1309 -- DMIC Peripheral Access Layer
Kojto 148:fd96258d940d 1310 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 1311
Kojto 148:fd96258d940d 1312 /*!
Kojto 148:fd96258d940d 1313 * @addtogroup DMIC_Peripheral_Access_Layer DMIC Peripheral Access Layer
Kojto 148:fd96258d940d 1314 * @{
Kojto 148:fd96258d940d 1315 */
Kojto 148:fd96258d940d 1316
Kojto 148:fd96258d940d 1317 /** DMIC - Register Layout Typedef */
Kojto 148:fd96258d940d 1318 typedef struct {
Kojto 148:fd96258d940d 1319 struct { /* offset: 0x0, array step: 0x100 */
Kojto 148:fd96258d940d 1320 __IO uint32_t OSR; /**< Oversample Rate register 0, array offset: 0x0, array step: 0x100 */
Kojto 148:fd96258d940d 1321 __IO uint32_t DIVHFCLK; /**< DMIC Clock Register 0, array offset: 0x4, array step: 0x100 */
Kojto 148:fd96258d940d 1322 __IO uint32_t PREAC2FSCOEF; /**< Pre-Emphasis Filter Coefficient for 2 FS register, array offset: 0x8, array step: 0x100 */
Kojto 148:fd96258d940d 1323 __IO uint32_t PREAC4FSCOEF; /**< Pre-Emphasis Filter Coefficient for 4 FS register, array offset: 0xC, array step: 0x100 */
Kojto 148:fd96258d940d 1324 __IO uint32_t GAINSHIFT; /**< Decimator Gain Shift register, array offset: 0x10, array step: 0x100 */
Kojto 148:fd96258d940d 1325 uint8_t RESERVED_0[108];
Kojto 148:fd96258d940d 1326 __IO uint32_t FIFO_CTRL; /**< FIFO Control register 0, array offset: 0x80, array step: 0x100 */
Kojto 148:fd96258d940d 1327 __IO uint32_t FIFO_STATUS; /**< FIFO Status register 0, array offset: 0x84, array step: 0x100 */
Kojto 148:fd96258d940d 1328 __IO uint32_t FIFO_DATA; /**< FIFO Data Register 0, array offset: 0x88, array step: 0x100 */
Kojto 148:fd96258d940d 1329 __IO uint32_t PHY_CTRL; /**< PDM Source Configuration register 0, array offset: 0x8C, array step: 0x100 */
Kojto 148:fd96258d940d 1330 __IO uint32_t DC_CTRL; /**< DC Control register 0, array offset: 0x90, array step: 0x100 */
Kojto 148:fd96258d940d 1331 uint8_t RESERVED_1[108];
Kojto 148:fd96258d940d 1332 } CHANNEL[2];
Kojto 148:fd96258d940d 1333 uint8_t RESERVED_0[3328];
Kojto 148:fd96258d940d 1334 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */
Kojto 148:fd96258d940d 1335 uint8_t RESERVED_1[8];
Kojto 148:fd96258d940d 1336 __IO uint32_t IOCFG; /**< I/O Configuration register, offset: 0xF0C */
Kojto 148:fd96258d940d 1337 __IO uint32_t USE2FS; /**< Use 2FS register, offset: 0xF10 */
Kojto 148:fd96258d940d 1338 uint8_t RESERVED_2[108];
Kojto 148:fd96258d940d 1339 __IO uint32_t HWVADGAIN; /**< HWVAD input gain register, offset: 0xF80 */
Kojto 148:fd96258d940d 1340 __IO uint32_t HWVADHPFS; /**< HWVAD filter control register, offset: 0xF84 */
Kojto 148:fd96258d940d 1341 __IO uint32_t HWVADST10; /**< HWVAD control register, offset: 0xF88 */
Kojto 148:fd96258d940d 1342 __IO uint32_t HWVADRSTT; /**< HWVAD filter reset register, offset: 0xF8C */
Kojto 148:fd96258d940d 1343 __IO uint32_t HWVADTHGN; /**< HWVAD noise estimator gain register, offset: 0xF90 */
Kojto 148:fd96258d940d 1344 __IO uint32_t HWVADTHGS; /**< HWVAD signal estimator gain register, offset: 0xF94 */
Kojto 148:fd96258d940d 1345 __I uint32_t HWVADLOWZ; /**< HWVAD noise envelope estimator register, offset: 0xF98 */
Kojto 148:fd96258d940d 1346 uint8_t RESERVED_3[96];
Kojto 148:fd96258d940d 1347 __I uint32_t ID; /**< Module Identification register, offset: 0xFFC */
Kojto 148:fd96258d940d 1348 } DMIC_Type;
Kojto 148:fd96258d940d 1349
Kojto 148:fd96258d940d 1350 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 1351 -- DMIC Register Masks
Kojto 148:fd96258d940d 1352 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 1353
Kojto 148:fd96258d940d 1354 /*!
Kojto 148:fd96258d940d 1355 * @addtogroup DMIC_Register_Masks DMIC Register Masks
Kojto 148:fd96258d940d 1356 * @{
Kojto 148:fd96258d940d 1357 */
Kojto 148:fd96258d940d 1358
Kojto 148:fd96258d940d 1359 /*! @name CHANNEL_OSR - Oversample Rate register 0 */
Kojto 148:fd96258d940d 1360 #define DMIC_CHANNEL_OSR_OSR_MASK (0xFFU)
Kojto 148:fd96258d940d 1361 #define DMIC_CHANNEL_OSR_OSR_SHIFT (0U)
Kojto 148:fd96258d940d 1362 #define DMIC_CHANNEL_OSR_OSR(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_OSR_OSR_SHIFT)) & DMIC_CHANNEL_OSR_OSR_MASK)
Kojto 148:fd96258d940d 1363
Kojto 148:fd96258d940d 1364 /* The count of DMIC_CHANNEL_OSR */
Kojto 148:fd96258d940d 1365 #define DMIC_CHANNEL_OSR_COUNT (2U)
Kojto 148:fd96258d940d 1366
Kojto 148:fd96258d940d 1367 /*! @name CHANNEL_DIVHFCLK - DMIC Clock Register 0 */
Kojto 148:fd96258d940d 1368 #define DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK (0xFU)
Kojto 148:fd96258d940d 1369 #define DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT (0U)
Kojto 148:fd96258d940d 1370 #define DMIC_CHANNEL_DIVHFCLK_PDMDIV(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT)) & DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK)
Kojto 148:fd96258d940d 1371
Kojto 148:fd96258d940d 1372 /* The count of DMIC_CHANNEL_DIVHFCLK */
Kojto 148:fd96258d940d 1373 #define DMIC_CHANNEL_DIVHFCLK_COUNT (2U)
Kojto 148:fd96258d940d 1374
Kojto 148:fd96258d940d 1375 /*! @name CHANNEL_PREAC2FSCOEF - Pre-Emphasis Filter Coefficient for 2 FS register */
Kojto 148:fd96258d940d 1376 #define DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK (0x3U)
Kojto 148:fd96258d940d 1377 #define DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT (0U)
Kojto 148:fd96258d940d 1378 #define DMIC_CHANNEL_PREAC2FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK)
Kojto 148:fd96258d940d 1379
Kojto 148:fd96258d940d 1380 /* The count of DMIC_CHANNEL_PREAC2FSCOEF */
Kojto 148:fd96258d940d 1381 #define DMIC_CHANNEL_PREAC2FSCOEF_COUNT (2U)
Kojto 148:fd96258d940d 1382
Kojto 148:fd96258d940d 1383 /*! @name CHANNEL_PREAC4FSCOEF - Pre-Emphasis Filter Coefficient for 4 FS register */
Kojto 148:fd96258d940d 1384 #define DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK (0x3U)
Kojto 148:fd96258d940d 1385 #define DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT (0U)
Kojto 148:fd96258d940d 1386 #define DMIC_CHANNEL_PREAC4FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK)
Kojto 148:fd96258d940d 1387
Kojto 148:fd96258d940d 1388 /* The count of DMIC_CHANNEL_PREAC4FSCOEF */
Kojto 148:fd96258d940d 1389 #define DMIC_CHANNEL_PREAC4FSCOEF_COUNT (2U)
Kojto 148:fd96258d940d 1390
Kojto 148:fd96258d940d 1391 /*! @name CHANNEL_GAINSHIFT - Decimator Gain Shift register */
Kojto 148:fd96258d940d 1392 #define DMIC_CHANNEL_GAINSHIFT_GAIN_MASK (0x3FU)
Kojto 148:fd96258d940d 1393 #define DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT (0U)
Kojto 148:fd96258d940d 1394 #define DMIC_CHANNEL_GAINSHIFT_GAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT)) & DMIC_CHANNEL_GAINSHIFT_GAIN_MASK)
Kojto 148:fd96258d940d 1395
Kojto 148:fd96258d940d 1396 /* The count of DMIC_CHANNEL_GAINSHIFT */
Kojto 148:fd96258d940d 1397 #define DMIC_CHANNEL_GAINSHIFT_COUNT (2U)
Kojto 148:fd96258d940d 1398
Kojto 148:fd96258d940d 1399 /*! @name CHANNEL_FIFO_CTRL - FIFO Control register 0 */
Kojto 148:fd96258d940d 1400 #define DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK (0x1U)
Kojto 148:fd96258d940d 1401 #define DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT (0U)
Kojto 148:fd96258d940d 1402 #define DMIC_CHANNEL_FIFO_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK)
Kojto 148:fd96258d940d 1403 #define DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK (0x2U)
Kojto 148:fd96258d940d 1404 #define DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT (1U)
Kojto 148:fd96258d940d 1405 #define DMIC_CHANNEL_FIFO_CTRL_RESETN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK)
Kojto 148:fd96258d940d 1406 #define DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK (0x4U)
Kojto 148:fd96258d940d 1407 #define DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT (2U)
Kojto 148:fd96258d940d 1408 #define DMIC_CHANNEL_FIFO_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK)
Kojto 148:fd96258d940d 1409 #define DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK (0x8U)
Kojto 148:fd96258d940d 1410 #define DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT (3U)
Kojto 148:fd96258d940d 1411 #define DMIC_CHANNEL_FIFO_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK)
Kojto 148:fd96258d940d 1412 #define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK (0x1F0000U)
Kojto 148:fd96258d940d 1413 #define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT (16U)
Kojto 148:fd96258d940d 1414 #define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK)
Kojto 148:fd96258d940d 1415
Kojto 148:fd96258d940d 1416 /* The count of DMIC_CHANNEL_FIFO_CTRL */
Kojto 148:fd96258d940d 1417 #define DMIC_CHANNEL_FIFO_CTRL_COUNT (2U)
Kojto 148:fd96258d940d 1418
Kojto 148:fd96258d940d 1419 /*! @name CHANNEL_FIFO_STATUS - FIFO Status register 0 */
Kojto 148:fd96258d940d 1420 #define DMIC_CHANNEL_FIFO_STATUS_INT_MASK (0x1U)
Kojto 148:fd96258d940d 1421 #define DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT (0U)
Kojto 148:fd96258d940d 1422 #define DMIC_CHANNEL_FIFO_STATUS_INT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_INT_MASK)
Kojto 148:fd96258d940d 1423 #define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK (0x2U)
Kojto 148:fd96258d940d 1424 #define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT (1U)
Kojto 148:fd96258d940d 1425 #define DMIC_CHANNEL_FIFO_STATUS_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK)
Kojto 148:fd96258d940d 1426 #define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK (0x4U)
Kojto 148:fd96258d940d 1427 #define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT (2U)
Kojto 148:fd96258d940d 1428 #define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK)
Kojto 148:fd96258d940d 1429
Kojto 148:fd96258d940d 1430 /* The count of DMIC_CHANNEL_FIFO_STATUS */
Kojto 148:fd96258d940d 1431 #define DMIC_CHANNEL_FIFO_STATUS_COUNT (2U)
Kojto 148:fd96258d940d 1432
Kojto 148:fd96258d940d 1433 /*! @name CHANNEL_FIFO_DATA - FIFO Data Register 0 */
Kojto 148:fd96258d940d 1434 #define DMIC_CHANNEL_FIFO_DATA_DATA_MASK (0xFFFFFFU)
Kojto 148:fd96258d940d 1435 #define DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT (0U)
Kojto 148:fd96258d940d 1436 #define DMIC_CHANNEL_FIFO_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT)) & DMIC_CHANNEL_FIFO_DATA_DATA_MASK)
Kojto 148:fd96258d940d 1437
Kojto 148:fd96258d940d 1438 /* The count of DMIC_CHANNEL_FIFO_DATA */
Kojto 148:fd96258d940d 1439 #define DMIC_CHANNEL_FIFO_DATA_COUNT (2U)
Kojto 148:fd96258d940d 1440
Kojto 148:fd96258d940d 1441 /*! @name CHANNEL_PHY_CTRL - PDM Source Configuration register 0 */
Kojto 148:fd96258d940d 1442 #define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK (0x1U)
Kojto 148:fd96258d940d 1443 #define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT (0U)
Kojto 148:fd96258d940d 1444 #define DMIC_CHANNEL_PHY_CTRL_PHY_FALL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK)
Kojto 148:fd96258d940d 1445 #define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK (0x2U)
Kojto 148:fd96258d940d 1446 #define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT (1U)
Kojto 148:fd96258d940d 1447 #define DMIC_CHANNEL_PHY_CTRL_PHY_HALF(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK)
Kojto 148:fd96258d940d 1448
Kojto 148:fd96258d940d 1449 /* The count of DMIC_CHANNEL_PHY_CTRL */
Kojto 148:fd96258d940d 1450 #define DMIC_CHANNEL_PHY_CTRL_COUNT (2U)
Kojto 148:fd96258d940d 1451
Kojto 148:fd96258d940d 1452 /*! @name CHANNEL_DC_CTRL - DC Control register 0 */
Kojto 148:fd96258d940d 1453 #define DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK (0x3U)
Kojto 148:fd96258d940d 1454 #define DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT (0U)
Kojto 148:fd96258d940d 1455 #define DMIC_CHANNEL_DC_CTRL_DCPOLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK)
Kojto 148:fd96258d940d 1456 #define DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK (0xF0U)
Kojto 148:fd96258d940d 1457 #define DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT (4U)
Kojto 148:fd96258d940d 1458 #define DMIC_CHANNEL_DC_CTRL_DCGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK)
Kojto 148:fd96258d940d 1459 #define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK (0x100U)
Kojto 148:fd96258d940d 1460 #define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT (8U)
Kojto 148:fd96258d940d 1461 #define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT)) & DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK)
Kojto 148:fd96258d940d 1462
Kojto 148:fd96258d940d 1463 /* The count of DMIC_CHANNEL_DC_CTRL */
Kojto 148:fd96258d940d 1464 #define DMIC_CHANNEL_DC_CTRL_COUNT (2U)
Kojto 148:fd96258d940d 1465
Kojto 148:fd96258d940d 1466 /*! @name CHANEN - Channel Enable register */
Kojto 148:fd96258d940d 1467 #define DMIC_CHANEN_EN_CH0_MASK (0x1U)
Kojto 148:fd96258d940d 1468 #define DMIC_CHANEN_EN_CH0_SHIFT (0U)
Kojto 148:fd96258d940d 1469 #define DMIC_CHANEN_EN_CH0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH0_SHIFT)) & DMIC_CHANEN_EN_CH0_MASK)
Kojto 148:fd96258d940d 1470 #define DMIC_CHANEN_EN_CH1_MASK (0x2U)
Kojto 148:fd96258d940d 1471 #define DMIC_CHANEN_EN_CH1_SHIFT (1U)
Kojto 148:fd96258d940d 1472 #define DMIC_CHANEN_EN_CH1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH1_SHIFT)) & DMIC_CHANEN_EN_CH1_MASK)
Kojto 148:fd96258d940d 1473
Kojto 148:fd96258d940d 1474 /*! @name IOCFG - I/O Configuration register */
Kojto 148:fd96258d940d 1475 #define DMIC_IOCFG_CLK_BYPASS0_MASK (0x1U)
Kojto 148:fd96258d940d 1476 #define DMIC_IOCFG_CLK_BYPASS0_SHIFT (0U)
Kojto 148:fd96258d940d 1477 #define DMIC_IOCFG_CLK_BYPASS0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS0_SHIFT)) & DMIC_IOCFG_CLK_BYPASS0_MASK)
Kojto 148:fd96258d940d 1478 #define DMIC_IOCFG_CLK_BYPASS1_MASK (0x2U)
Kojto 148:fd96258d940d 1479 #define DMIC_IOCFG_CLK_BYPASS1_SHIFT (1U)
Kojto 148:fd96258d940d 1480 #define DMIC_IOCFG_CLK_BYPASS1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS1_SHIFT)) & DMIC_IOCFG_CLK_BYPASS1_MASK)
Kojto 148:fd96258d940d 1481 #define DMIC_IOCFG_STEREO_DATA0_MASK (0x4U)
Kojto 148:fd96258d940d 1482 #define DMIC_IOCFG_STEREO_DATA0_SHIFT (2U)
Kojto 148:fd96258d940d 1483 #define DMIC_IOCFG_STEREO_DATA0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_STEREO_DATA0_SHIFT)) & DMIC_IOCFG_STEREO_DATA0_MASK)
Kojto 148:fd96258d940d 1484
Kojto 148:fd96258d940d 1485 /*! @name USE2FS - Use 2FS register */
Kojto 148:fd96258d940d 1486 #define DMIC_USE2FS_USE2FS_MASK (0x1U)
Kojto 148:fd96258d940d 1487 #define DMIC_USE2FS_USE2FS_SHIFT (0U)
Kojto 148:fd96258d940d 1488 #define DMIC_USE2FS_USE2FS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_USE2FS_USE2FS_SHIFT)) & DMIC_USE2FS_USE2FS_MASK)
Kojto 148:fd96258d940d 1489
Kojto 148:fd96258d940d 1490 /*! @name HWVADGAIN - HWVAD input gain register */
Kojto 148:fd96258d940d 1491 #define DMIC_HWVADGAIN_INPUTGAIN_MASK (0xFU)
Kojto 148:fd96258d940d 1492 #define DMIC_HWVADGAIN_INPUTGAIN_SHIFT (0U)
Kojto 148:fd96258d940d 1493 #define DMIC_HWVADGAIN_INPUTGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADGAIN_INPUTGAIN_SHIFT)) & DMIC_HWVADGAIN_INPUTGAIN_MASK)
Kojto 148:fd96258d940d 1494
Kojto 148:fd96258d940d 1495 /*! @name HWVADHPFS - HWVAD filter control register */
Kojto 148:fd96258d940d 1496 #define DMIC_HWVADHPFS_HPFS_MASK (0x3U)
Kojto 148:fd96258d940d 1497 #define DMIC_HWVADHPFS_HPFS_SHIFT (0U)
Kojto 148:fd96258d940d 1498 #define DMIC_HWVADHPFS_HPFS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADHPFS_HPFS_SHIFT)) & DMIC_HWVADHPFS_HPFS_MASK)
Kojto 148:fd96258d940d 1499
Kojto 148:fd96258d940d 1500 /*! @name HWVADST10 - HWVAD control register */
Kojto 148:fd96258d940d 1501 #define DMIC_HWVADST10_ST10_MASK (0x1U)
Kojto 148:fd96258d940d 1502 #define DMIC_HWVADST10_ST10_SHIFT (0U)
Kojto 148:fd96258d940d 1503 #define DMIC_HWVADST10_ST10(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADST10_ST10_SHIFT)) & DMIC_HWVADST10_ST10_MASK)
Kojto 148:fd96258d940d 1504
Kojto 148:fd96258d940d 1505 /*! @name HWVADRSTT - HWVAD filter reset register */
Kojto 148:fd96258d940d 1506 #define DMIC_HWVADRSTT_RSTT_MASK (0x1U)
Kojto 148:fd96258d940d 1507 #define DMIC_HWVADRSTT_RSTT_SHIFT (0U)
Kojto 148:fd96258d940d 1508 #define DMIC_HWVADRSTT_RSTT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADRSTT_RSTT_SHIFT)) & DMIC_HWVADRSTT_RSTT_MASK)
Kojto 148:fd96258d940d 1509
Kojto 148:fd96258d940d 1510 /*! @name HWVADTHGN - HWVAD noise estimator gain register */
Kojto 148:fd96258d940d 1511 #define DMIC_HWVADTHGN_THGN_MASK (0xFU)
Kojto 148:fd96258d940d 1512 #define DMIC_HWVADTHGN_THGN_SHIFT (0U)
Kojto 148:fd96258d940d 1513 #define DMIC_HWVADTHGN_THGN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGN_THGN_SHIFT)) & DMIC_HWVADTHGN_THGN_MASK)
Kojto 148:fd96258d940d 1514
Kojto 148:fd96258d940d 1515 /*! @name HWVADTHGS - HWVAD signal estimator gain register */
Kojto 148:fd96258d940d 1516 #define DMIC_HWVADTHGS_THGS_MASK (0xFU)
Kojto 148:fd96258d940d 1517 #define DMIC_HWVADTHGS_THGS_SHIFT (0U)
Kojto 148:fd96258d940d 1518 #define DMIC_HWVADTHGS_THGS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGS_THGS_SHIFT)) & DMIC_HWVADTHGS_THGS_MASK)
Kojto 148:fd96258d940d 1519
Kojto 148:fd96258d940d 1520 /*! @name HWVADLOWZ - HWVAD noise envelope estimator register */
Kojto 148:fd96258d940d 1521 #define DMIC_HWVADLOWZ_LOWZ_MASK (0xFFFFU)
Kojto 148:fd96258d940d 1522 #define DMIC_HWVADLOWZ_LOWZ_SHIFT (0U)
Kojto 148:fd96258d940d 1523 #define DMIC_HWVADLOWZ_LOWZ(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADLOWZ_LOWZ_SHIFT)) & DMIC_HWVADLOWZ_LOWZ_MASK)
Kojto 148:fd96258d940d 1524
Kojto 148:fd96258d940d 1525 /*! @name ID - Module Identification register */
Kojto 148:fd96258d940d 1526 #define DMIC_ID_ID_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 1527 #define DMIC_ID_ID_SHIFT (0U)
Kojto 148:fd96258d940d 1528 #define DMIC_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DMIC_ID_ID_SHIFT)) & DMIC_ID_ID_MASK)
Kojto 148:fd96258d940d 1529
Kojto 148:fd96258d940d 1530
Kojto 148:fd96258d940d 1531 /*!
Kojto 148:fd96258d940d 1532 * @}
Kojto 148:fd96258d940d 1533 */ /* end of group DMIC_Register_Masks */
Kojto 148:fd96258d940d 1534
Kojto 148:fd96258d940d 1535
Kojto 148:fd96258d940d 1536 /* DMIC - Peripheral instance base addresses */
Kojto 148:fd96258d940d 1537 /** Peripheral DMIC0 base address */
Kojto 148:fd96258d940d 1538 #define DMIC0_BASE (0x40090000u)
Kojto 148:fd96258d940d 1539 /** Peripheral DMIC0 base pointer */
Kojto 148:fd96258d940d 1540 #define DMIC0 ((DMIC_Type *)DMIC0_BASE)
Kojto 148:fd96258d940d 1541 /** Array initializer of DMIC peripheral base addresses */
Kojto 148:fd96258d940d 1542 #define DMIC_BASE_ADDRS { DMIC0_BASE }
Kojto 148:fd96258d940d 1543 /** Array initializer of DMIC peripheral base pointers */
Kojto 148:fd96258d940d 1544 #define DMIC_BASE_PTRS { DMIC0 }
Kojto 148:fd96258d940d 1545 /** Interrupt vectors for the DMIC peripheral type */
Kojto 148:fd96258d940d 1546 #define DMIC_IRQS { DMIC0_IRQn }
Kojto 148:fd96258d940d 1547 #define DMIC_HWVAD_IRQS { HWVAD0_IRQn }
Kojto 148:fd96258d940d 1548
Kojto 148:fd96258d940d 1549 /*!
Kojto 148:fd96258d940d 1550 * @}
Kojto 148:fd96258d940d 1551 */ /* end of group DMIC_Peripheral_Access_Layer */
Kojto 148:fd96258d940d 1552
Kojto 148:fd96258d940d 1553
Kojto 148:fd96258d940d 1554 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 1555 -- FLEXCOMM Peripheral Access Layer
Kojto 148:fd96258d940d 1556 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 1557
Kojto 148:fd96258d940d 1558 /*!
Kojto 148:fd96258d940d 1559 * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer
Kojto 148:fd96258d940d 1560 * @{
Kojto 148:fd96258d940d 1561 */
Kojto 148:fd96258d940d 1562
Kojto 148:fd96258d940d 1563 /** FLEXCOMM - Register Layout Typedef */
Kojto 148:fd96258d940d 1564 typedef struct {
Kojto 148:fd96258d940d 1565 uint8_t RESERVED_0[4088];
Kojto 148:fd96258d940d 1566 __IO uint32_t PSELID; /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */
Kojto 148:fd96258d940d 1567 __I uint32_t PID; /**< Peripheral identification register., offset: 0xFFC */
Kojto 148:fd96258d940d 1568 } FLEXCOMM_Type;
Kojto 148:fd96258d940d 1569
Kojto 148:fd96258d940d 1570 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 1571 -- FLEXCOMM Register Masks
Kojto 148:fd96258d940d 1572 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 1573
Kojto 148:fd96258d940d 1574 /*!
Kojto 148:fd96258d940d 1575 * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks
Kojto 148:fd96258d940d 1576 * @{
Kojto 148:fd96258d940d 1577 */
Kojto 148:fd96258d940d 1578
Kojto 148:fd96258d940d 1579 /*! @name PSELID - Peripheral Select and Flexcomm ID register. */
Kojto 148:fd96258d940d 1580 #define FLEXCOMM_PSELID_PERSEL_MASK (0x7U)
Kojto 148:fd96258d940d 1581 #define FLEXCOMM_PSELID_PERSEL_SHIFT (0U)
Kojto 148:fd96258d940d 1582 #define FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK)
Kojto 148:fd96258d940d 1583 #define FLEXCOMM_PSELID_LOCK_MASK (0x8U)
Kojto 148:fd96258d940d 1584 #define FLEXCOMM_PSELID_LOCK_SHIFT (3U)
Kojto 148:fd96258d940d 1585 #define FLEXCOMM_PSELID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK)
Kojto 148:fd96258d940d 1586 #define FLEXCOMM_PSELID_USARTPRESENT_MASK (0x10U)
Kojto 148:fd96258d940d 1587 #define FLEXCOMM_PSELID_USARTPRESENT_SHIFT (4U)
Kojto 148:fd96258d940d 1588 #define FLEXCOMM_PSELID_USARTPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK)
Kojto 148:fd96258d940d 1589 #define FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U)
Kojto 148:fd96258d940d 1590 #define FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U)
Kojto 148:fd96258d940d 1591 #define FLEXCOMM_PSELID_SPIPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK)
Kojto 148:fd96258d940d 1592 #define FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U)
Kojto 148:fd96258d940d 1593 #define FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U)
Kojto 148:fd96258d940d 1594 #define FLEXCOMM_PSELID_I2CPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK)
Kojto 148:fd96258d940d 1595 #define FLEXCOMM_PSELID_I2SPRESENT_MASK (0x80U)
Kojto 148:fd96258d940d 1596 #define FLEXCOMM_PSELID_I2SPRESENT_SHIFT (7U)
Kojto 148:fd96258d940d 1597 #define FLEXCOMM_PSELID_I2SPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK)
Kojto 148:fd96258d940d 1598 #define FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U)
Kojto 148:fd96258d940d 1599 #define FLEXCOMM_PSELID_ID_SHIFT (12U)
Kojto 148:fd96258d940d 1600 #define FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK)
Kojto 148:fd96258d940d 1601
Kojto 148:fd96258d940d 1602 /*! @name PID - Peripheral identification register. */
Kojto 148:fd96258d940d 1603 #define FLEXCOMM_PID_Minor_Rev_MASK (0xF00U)
Kojto 148:fd96258d940d 1604 #define FLEXCOMM_PID_Minor_Rev_SHIFT (8U)
Kojto 148:fd96258d940d 1605 #define FLEXCOMM_PID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Minor_Rev_SHIFT)) & FLEXCOMM_PID_Minor_Rev_MASK)
Kojto 148:fd96258d940d 1606 #define FLEXCOMM_PID_Major_Rev_MASK (0xF000U)
Kojto 148:fd96258d940d 1607 #define FLEXCOMM_PID_Major_Rev_SHIFT (12U)
Kojto 148:fd96258d940d 1608 #define FLEXCOMM_PID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Major_Rev_SHIFT)) & FLEXCOMM_PID_Major_Rev_MASK)
Kojto 148:fd96258d940d 1609 #define FLEXCOMM_PID_ID_MASK (0xFFFF0000U)
Kojto 148:fd96258d940d 1610 #define FLEXCOMM_PID_ID_SHIFT (16U)
Kojto 148:fd96258d940d 1611 #define FLEXCOMM_PID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK)
Kojto 148:fd96258d940d 1612
Kojto 148:fd96258d940d 1613
Kojto 148:fd96258d940d 1614 /*!
Kojto 148:fd96258d940d 1615 * @}
Kojto 148:fd96258d940d 1616 */ /* end of group FLEXCOMM_Register_Masks */
Kojto 148:fd96258d940d 1617
Kojto 148:fd96258d940d 1618
Kojto 148:fd96258d940d 1619 /* FLEXCOMM - Peripheral instance base addresses */
Kojto 148:fd96258d940d 1620 /** Peripheral FLEXCOMM0 base address */
Kojto 148:fd96258d940d 1621 #define FLEXCOMM0_BASE (0x40086000u)
Kojto 148:fd96258d940d 1622 /** Peripheral FLEXCOMM0 base pointer */
Kojto 148:fd96258d940d 1623 #define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE)
Kojto 148:fd96258d940d 1624 /** Peripheral FLEXCOMM1 base address */
Kojto 148:fd96258d940d 1625 #define FLEXCOMM1_BASE (0x40087000u)
Kojto 148:fd96258d940d 1626 /** Peripheral FLEXCOMM1 base pointer */
Kojto 148:fd96258d940d 1627 #define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE)
Kojto 148:fd96258d940d 1628 /** Peripheral FLEXCOMM2 base address */
Kojto 148:fd96258d940d 1629 #define FLEXCOMM2_BASE (0x40088000u)
Kojto 148:fd96258d940d 1630 /** Peripheral FLEXCOMM2 base pointer */
Kojto 148:fd96258d940d 1631 #define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE)
Kojto 148:fd96258d940d 1632 /** Peripheral FLEXCOMM3 base address */
Kojto 148:fd96258d940d 1633 #define FLEXCOMM3_BASE (0x40089000u)
Kojto 148:fd96258d940d 1634 /** Peripheral FLEXCOMM3 base pointer */
Kojto 148:fd96258d940d 1635 #define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE)
Kojto 148:fd96258d940d 1636 /** Peripheral FLEXCOMM4 base address */
Kojto 148:fd96258d940d 1637 #define FLEXCOMM4_BASE (0x4008A000u)
Kojto 148:fd96258d940d 1638 /** Peripheral FLEXCOMM4 base pointer */
Kojto 148:fd96258d940d 1639 #define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE)
Kojto 148:fd96258d940d 1640 /** Peripheral FLEXCOMM5 base address */
Kojto 148:fd96258d940d 1641 #define FLEXCOMM5_BASE (0x40096000u)
Kojto 148:fd96258d940d 1642 /** Peripheral FLEXCOMM5 base pointer */
Kojto 148:fd96258d940d 1643 #define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE)
Kojto 148:fd96258d940d 1644 /** Peripheral FLEXCOMM6 base address */
Kojto 148:fd96258d940d 1645 #define FLEXCOMM6_BASE (0x40097000u)
Kojto 148:fd96258d940d 1646 /** Peripheral FLEXCOMM6 base pointer */
Kojto 148:fd96258d940d 1647 #define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE)
Kojto 148:fd96258d940d 1648 /** Peripheral FLEXCOMM7 base address */
Kojto 148:fd96258d940d 1649 #define FLEXCOMM7_BASE (0x40098000u)
Kojto 148:fd96258d940d 1650 /** Peripheral FLEXCOMM7 base pointer */
Kojto 148:fd96258d940d 1651 #define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE)
Kojto 148:fd96258d940d 1652 /** Array initializer of FLEXCOMM peripheral base addresses */
Kojto 148:fd96258d940d 1653 #define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE }
Kojto 148:fd96258d940d 1654 /** Array initializer of FLEXCOMM peripheral base pointers */
Kojto 148:fd96258d940d 1655 #define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7 }
Kojto 148:fd96258d940d 1656 /** Interrupt vectors for the FLEXCOMM peripheral type */
Kojto 148:fd96258d940d 1657 #define FLEXCOMM_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn }
Kojto 148:fd96258d940d 1658
Kojto 148:fd96258d940d 1659 /*!
Kojto 148:fd96258d940d 1660 * @}
Kojto 148:fd96258d940d 1661 */ /* end of group FLEXCOMM_Peripheral_Access_Layer */
Kojto 148:fd96258d940d 1662
Kojto 148:fd96258d940d 1663
Kojto 148:fd96258d940d 1664 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 1665 -- GINT Peripheral Access Layer
Kojto 148:fd96258d940d 1666 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 1667
Kojto 148:fd96258d940d 1668 /*!
Kojto 148:fd96258d940d 1669 * @addtogroup GINT_Peripheral_Access_Layer GINT Peripheral Access Layer
Kojto 148:fd96258d940d 1670 * @{
Kojto 148:fd96258d940d 1671 */
Kojto 148:fd96258d940d 1672
Kojto 148:fd96258d940d 1673 /** GINT - Register Layout Typedef */
Kojto 148:fd96258d940d 1674 typedef struct {
Kojto 148:fd96258d940d 1675 __IO uint32_t CTRL; /**< GPIO grouped interrupt control register, offset: 0x0 */
Kojto 148:fd96258d940d 1676 uint8_t RESERVED_0[28];
Kojto 148:fd96258d940d 1677 __IO uint32_t PORT_POL[2]; /**< GPIO grouped interrupt port 0 polarity register, array offset: 0x20, array step: 0x4 */
Kojto 148:fd96258d940d 1678 uint8_t RESERVED_1[24];
Kojto 148:fd96258d940d 1679 __IO uint32_t PORT_ENA[2]; /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */
Kojto 148:fd96258d940d 1680 } GINT_Type;
Kojto 148:fd96258d940d 1681
Kojto 148:fd96258d940d 1682 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 1683 -- GINT Register Masks
Kojto 148:fd96258d940d 1684 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 1685
Kojto 148:fd96258d940d 1686 /*!
Kojto 148:fd96258d940d 1687 * @addtogroup GINT_Register_Masks GINT Register Masks
Kojto 148:fd96258d940d 1688 * @{
Kojto 148:fd96258d940d 1689 */
Kojto 148:fd96258d940d 1690
Kojto 148:fd96258d940d 1691 /*! @name CTRL - GPIO grouped interrupt control register */
Kojto 148:fd96258d940d 1692 #define GINT_CTRL_INT_MASK (0x1U)
Kojto 148:fd96258d940d 1693 #define GINT_CTRL_INT_SHIFT (0U)
Kojto 148:fd96258d940d 1694 #define GINT_CTRL_INT(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK)
Kojto 148:fd96258d940d 1695 #define GINT_CTRL_COMB_MASK (0x2U)
Kojto 148:fd96258d940d 1696 #define GINT_CTRL_COMB_SHIFT (1U)
Kojto 148:fd96258d940d 1697 #define GINT_CTRL_COMB(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK)
Kojto 148:fd96258d940d 1698 #define GINT_CTRL_TRIG_MASK (0x4U)
Kojto 148:fd96258d940d 1699 #define GINT_CTRL_TRIG_SHIFT (2U)
Kojto 148:fd96258d940d 1700 #define GINT_CTRL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK)
Kojto 148:fd96258d940d 1701
Kojto 148:fd96258d940d 1702 /*! @name PORT_POL - GPIO grouped interrupt port 0 polarity register */
Kojto 148:fd96258d940d 1703 #define GINT_PORT_POL_POL_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 1704 #define GINT_PORT_POL_POL_SHIFT (0U)
Kojto 148:fd96258d940d 1705 #define GINT_PORT_POL_POL(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK)
Kojto 148:fd96258d940d 1706
Kojto 148:fd96258d940d 1707 /* The count of GINT_PORT_POL */
Kojto 148:fd96258d940d 1708 #define GINT_PORT_POL_COUNT (2U)
Kojto 148:fd96258d940d 1709
Kojto 148:fd96258d940d 1710 /*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */
Kojto 148:fd96258d940d 1711 #define GINT_PORT_ENA_ENA_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 1712 #define GINT_PORT_ENA_ENA_SHIFT (0U)
Kojto 148:fd96258d940d 1713 #define GINT_PORT_ENA_ENA(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK)
Kojto 148:fd96258d940d 1714
Kojto 148:fd96258d940d 1715 /* The count of GINT_PORT_ENA */
Kojto 148:fd96258d940d 1716 #define GINT_PORT_ENA_COUNT (2U)
Kojto 148:fd96258d940d 1717
Kojto 148:fd96258d940d 1718
Kojto 148:fd96258d940d 1719 /*!
Kojto 148:fd96258d940d 1720 * @}
Kojto 148:fd96258d940d 1721 */ /* end of group GINT_Register_Masks */
Kojto 148:fd96258d940d 1722
Kojto 148:fd96258d940d 1723
Kojto 148:fd96258d940d 1724 /* GINT - Peripheral instance base addresses */
Kojto 148:fd96258d940d 1725 /** Peripheral GINT0 base address */
Kojto 148:fd96258d940d 1726 #define GINT0_BASE (0x40002000u)
Kojto 148:fd96258d940d 1727 /** Peripheral GINT0 base pointer */
Kojto 148:fd96258d940d 1728 #define GINT0 ((GINT_Type *)GINT0_BASE)
Kojto 148:fd96258d940d 1729 /** Peripheral GINT1 base address */
Kojto 148:fd96258d940d 1730 #define GINT1_BASE (0x40003000u)
Kojto 148:fd96258d940d 1731 /** Peripheral GINT1 base pointer */
Kojto 148:fd96258d940d 1732 #define GINT1 ((GINT_Type *)GINT1_BASE)
Kojto 148:fd96258d940d 1733 /** Array initializer of GINT peripheral base addresses */
Kojto 148:fd96258d940d 1734 #define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE }
Kojto 148:fd96258d940d 1735 /** Array initializer of GINT peripheral base pointers */
Kojto 148:fd96258d940d 1736 #define GINT_BASE_PTRS { GINT0, GINT1 }
Kojto 148:fd96258d940d 1737 /** Interrupt vectors for the GINT peripheral type */
Kojto 148:fd96258d940d 1738 #define GINT_IRQS { GINT0_IRQn, GINT1_IRQn }
Kojto 148:fd96258d940d 1739
Kojto 148:fd96258d940d 1740 /*!
Kojto 148:fd96258d940d 1741 * @}
Kojto 148:fd96258d940d 1742 */ /* end of group GINT_Peripheral_Access_Layer */
Kojto 148:fd96258d940d 1743
Kojto 148:fd96258d940d 1744
Kojto 148:fd96258d940d 1745 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 1746 -- GPIO Peripheral Access Layer
Kojto 148:fd96258d940d 1747 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 1748
Kojto 148:fd96258d940d 1749 /*!
Kojto 148:fd96258d940d 1750 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
Kojto 148:fd96258d940d 1751 * @{
Kojto 148:fd96258d940d 1752 */
Kojto 148:fd96258d940d 1753
Kojto 148:fd96258d940d 1754 /** GPIO - Register Layout Typedef */
Kojto 148:fd96258d940d 1755 typedef struct {
Kojto 148:fd96258d940d 1756 __IO uint8_t B[2][32]; /**< Byte pin registers for all port 0 and 1 GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */
Kojto 148:fd96258d940d 1757 uint8_t RESERVED_0[4032];
Kojto 148:fd96258d940d 1758 __IO uint32_t W[2][32]; /**< Word pin registers for all port 0 and 1 GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */
Kojto 148:fd96258d940d 1759 uint8_t RESERVED_1[3840];
Kojto 148:fd96258d940d 1760 __IO uint32_t DIR[2]; /**< Direction registers, array offset: 0x2000, array step: 0x4 */
Kojto 148:fd96258d940d 1761 uint8_t RESERVED_2[120];
Kojto 148:fd96258d940d 1762 __IO uint32_t MASK[2]; /**< Mask register, array offset: 0x2080, array step: 0x4 */
Kojto 148:fd96258d940d 1763 uint8_t RESERVED_3[120];
Kojto 148:fd96258d940d 1764 __IO uint32_t PIN[2]; /**< Port pin register, array offset: 0x2100, array step: 0x4 */
Kojto 148:fd96258d940d 1765 uint8_t RESERVED_4[120];
Kojto 148:fd96258d940d 1766 __IO uint32_t MPIN[2]; /**< Masked port register, array offset: 0x2180, array step: 0x4 */
Kojto 148:fd96258d940d 1767 uint8_t RESERVED_5[120];
Kojto 148:fd96258d940d 1768 __IO uint32_t SET[2]; /**< Write: Set register for port Read: output bits for port, array offset: 0x2200, array step: 0x4 */
Kojto 148:fd96258d940d 1769 uint8_t RESERVED_6[120];
Kojto 148:fd96258d940d 1770 __O uint32_t CLR[2]; /**< Clear port, array offset: 0x2280, array step: 0x4 */
Kojto 148:fd96258d940d 1771 uint8_t RESERVED_7[120];
Kojto 148:fd96258d940d 1772 __O uint32_t NOT[2]; /**< Toggle port, array offset: 0x2300, array step: 0x4 */
Kojto 148:fd96258d940d 1773 uint8_t RESERVED_8[120];
Kojto 148:fd96258d940d 1774 __O uint32_t DIRSET[2]; /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */
Kojto 148:fd96258d940d 1775 uint8_t RESERVED_9[120];
Kojto 148:fd96258d940d 1776 __O uint32_t DIRCLR[2]; /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */
Kojto 148:fd96258d940d 1777 uint8_t RESERVED_10[120];
Kojto 148:fd96258d940d 1778 __O uint32_t DIRNOT[2]; /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */
Kojto 148:fd96258d940d 1779 } GPIO_Type;
Kojto 148:fd96258d940d 1780
Kojto 148:fd96258d940d 1781 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 1782 -- GPIO Register Masks
Kojto 148:fd96258d940d 1783 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 1784
Kojto 148:fd96258d940d 1785 /*!
Kojto 148:fd96258d940d 1786 * @addtogroup GPIO_Register_Masks GPIO Register Masks
Kojto 148:fd96258d940d 1787 * @{
Kojto 148:fd96258d940d 1788 */
Kojto 148:fd96258d940d 1789
Kojto 148:fd96258d940d 1790 /*! @name B - Byte pin registers for all port 0 and 1 GPIO pins */
Kojto 148:fd96258d940d 1791 #define GPIO_B_PBYTE_MASK (0x1U)
Kojto 148:fd96258d940d 1792 #define GPIO_B_PBYTE_SHIFT (0U)
Kojto 148:fd96258d940d 1793 #define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK)
Kojto 148:fd96258d940d 1794
Kojto 148:fd96258d940d 1795 /* The count of GPIO_B */
Kojto 148:fd96258d940d 1796 #define GPIO_B_COUNT (2U)
Kojto 148:fd96258d940d 1797
Kojto 148:fd96258d940d 1798 /* The count of GPIO_B */
Kojto 148:fd96258d940d 1799 #define GPIO_B_COUNT2 (32U)
Kojto 148:fd96258d940d 1800
Kojto 148:fd96258d940d 1801 /*! @name W - Word pin registers for all port 0 and 1 GPIO pins */
Kojto 148:fd96258d940d 1802 #define GPIO_W_PWORD_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 1803 #define GPIO_W_PWORD_SHIFT (0U)
Kojto 148:fd96258d940d 1804 #define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK)
Kojto 148:fd96258d940d 1805
Kojto 148:fd96258d940d 1806 /* The count of GPIO_W */
Kojto 148:fd96258d940d 1807 #define GPIO_W_COUNT (2U)
Kojto 148:fd96258d940d 1808
Kojto 148:fd96258d940d 1809 /* The count of GPIO_W */
Kojto 148:fd96258d940d 1810 #define GPIO_W_COUNT2 (32U)
Kojto 148:fd96258d940d 1811
Kojto 148:fd96258d940d 1812 /*! @name DIR - Direction registers */
Kojto 148:fd96258d940d 1813 #define GPIO_DIR_DIRP_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 1814 #define GPIO_DIR_DIRP_SHIFT (0U)
Kojto 148:fd96258d940d 1815 #define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK)
Kojto 148:fd96258d940d 1816
Kojto 148:fd96258d940d 1817 /* The count of GPIO_DIR */
Kojto 148:fd96258d940d 1818 #define GPIO_DIR_COUNT (2U)
Kojto 148:fd96258d940d 1819
Kojto 148:fd96258d940d 1820 /*! @name MASK - Mask register */
Kojto 148:fd96258d940d 1821 #define GPIO_MASK_MASKP_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 1822 #define GPIO_MASK_MASKP_SHIFT (0U)
Kojto 148:fd96258d940d 1823 #define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK)
Kojto 148:fd96258d940d 1824
Kojto 148:fd96258d940d 1825 /* The count of GPIO_MASK */
Kojto 148:fd96258d940d 1826 #define GPIO_MASK_COUNT (2U)
Kojto 148:fd96258d940d 1827
Kojto 148:fd96258d940d 1828 /*! @name PIN - Port pin register */
Kojto 148:fd96258d940d 1829 #define GPIO_PIN_PORT_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 1830 #define GPIO_PIN_PORT_SHIFT (0U)
Kojto 148:fd96258d940d 1831 #define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK)
Kojto 148:fd96258d940d 1832
Kojto 148:fd96258d940d 1833 /* The count of GPIO_PIN */
Kojto 148:fd96258d940d 1834 #define GPIO_PIN_COUNT (2U)
Kojto 148:fd96258d940d 1835
Kojto 148:fd96258d940d 1836 /*! @name MPIN - Masked port register */
Kojto 148:fd96258d940d 1837 #define GPIO_MPIN_MPORTP_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 1838 #define GPIO_MPIN_MPORTP_SHIFT (0U)
Kojto 148:fd96258d940d 1839 #define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK)
Kojto 148:fd96258d940d 1840
Kojto 148:fd96258d940d 1841 /* The count of GPIO_MPIN */
Kojto 148:fd96258d940d 1842 #define GPIO_MPIN_COUNT (2U)
Kojto 148:fd96258d940d 1843
Kojto 148:fd96258d940d 1844 /*! @name SET - Write: Set register for port Read: output bits for port */
Kojto 148:fd96258d940d 1845 #define GPIO_SET_SETP_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 1846 #define GPIO_SET_SETP_SHIFT (0U)
Kojto 148:fd96258d940d 1847 #define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK)
Kojto 148:fd96258d940d 1848
Kojto 148:fd96258d940d 1849 /* The count of GPIO_SET */
Kojto 148:fd96258d940d 1850 #define GPIO_SET_COUNT (2U)
Kojto 148:fd96258d940d 1851
Kojto 148:fd96258d940d 1852 /*! @name CLR - Clear port */
Kojto 148:fd96258d940d 1853 #define GPIO_CLR_CLRP_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 1854 #define GPIO_CLR_CLRP_SHIFT (0U)
Kojto 148:fd96258d940d 1855 #define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK)
Kojto 148:fd96258d940d 1856
Kojto 148:fd96258d940d 1857 /* The count of GPIO_CLR */
Kojto 148:fd96258d940d 1858 #define GPIO_CLR_COUNT (2U)
Kojto 148:fd96258d940d 1859
Kojto 148:fd96258d940d 1860 /*! @name NOT - Toggle port */
Kojto 148:fd96258d940d 1861 #define GPIO_NOT_NOTP_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 1862 #define GPIO_NOT_NOTP_SHIFT (0U)
Kojto 148:fd96258d940d 1863 #define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK)
Kojto 148:fd96258d940d 1864
Kojto 148:fd96258d940d 1865 /* The count of GPIO_NOT */
Kojto 148:fd96258d940d 1866 #define GPIO_NOT_COUNT (2U)
Kojto 148:fd96258d940d 1867
Kojto 148:fd96258d940d 1868 /*! @name DIRSET - Set pin direction bits for port */
Kojto 148:fd96258d940d 1869 #define GPIO_DIRSET_DIRSETP_MASK (0x1FFFFFFFU)
Kojto 148:fd96258d940d 1870 #define GPIO_DIRSET_DIRSETP_SHIFT (0U)
Kojto 148:fd96258d940d 1871 #define GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK)
Kojto 148:fd96258d940d 1872
Kojto 148:fd96258d940d 1873 /* The count of GPIO_DIRSET */
Kojto 148:fd96258d940d 1874 #define GPIO_DIRSET_COUNT (2U)
Kojto 148:fd96258d940d 1875
Kojto 148:fd96258d940d 1876 /*! @name DIRCLR - Clear pin direction bits for port */
Kojto 148:fd96258d940d 1877 #define GPIO_DIRCLR_DIRCLRP_MASK (0x1FFFFFFFU)
Kojto 148:fd96258d940d 1878 #define GPIO_DIRCLR_DIRCLRP_SHIFT (0U)
Kojto 148:fd96258d940d 1879 #define GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK)
Kojto 148:fd96258d940d 1880
Kojto 148:fd96258d940d 1881 /* The count of GPIO_DIRCLR */
Kojto 148:fd96258d940d 1882 #define GPIO_DIRCLR_COUNT (2U)
Kojto 148:fd96258d940d 1883
Kojto 148:fd96258d940d 1884 /*! @name DIRNOT - Toggle pin direction bits for port */
Kojto 148:fd96258d940d 1885 #define GPIO_DIRNOT_DIRNOTP_MASK (0x1FFFFFFFU)
Kojto 148:fd96258d940d 1886 #define GPIO_DIRNOT_DIRNOTP_SHIFT (0U)
Kojto 148:fd96258d940d 1887 #define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK)
Kojto 148:fd96258d940d 1888
Kojto 148:fd96258d940d 1889 /* The count of GPIO_DIRNOT */
Kojto 148:fd96258d940d 1890 #define GPIO_DIRNOT_COUNT (2U)
Kojto 148:fd96258d940d 1891
Kojto 148:fd96258d940d 1892
Kojto 148:fd96258d940d 1893 /*!
Kojto 148:fd96258d940d 1894 * @}
Kojto 148:fd96258d940d 1895 */ /* end of group GPIO_Register_Masks */
Kojto 148:fd96258d940d 1896
Kojto 148:fd96258d940d 1897
Kojto 148:fd96258d940d 1898 /* GPIO - Peripheral instance base addresses */
Kojto 148:fd96258d940d 1899 /** Peripheral GPIO base address */
Kojto 148:fd96258d940d 1900 #define GPIO_BASE (0x4008C000u)
Kojto 148:fd96258d940d 1901 /** Peripheral GPIO base pointer */
Kojto 148:fd96258d940d 1902 #define GPIO ((GPIO_Type *)GPIO_BASE)
Kojto 148:fd96258d940d 1903 /** Array initializer of GPIO peripheral base addresses */
Kojto 148:fd96258d940d 1904 #define GPIO_BASE_ADDRS { GPIO_BASE }
Kojto 148:fd96258d940d 1905 /** Array initializer of GPIO peripheral base pointers */
Kojto 148:fd96258d940d 1906 #define GPIO_BASE_PTRS { GPIO }
Kojto 148:fd96258d940d 1907
Kojto 148:fd96258d940d 1908 /*!
Kojto 148:fd96258d940d 1909 * @}
Kojto 148:fd96258d940d 1910 */ /* end of group GPIO_Peripheral_Access_Layer */
Kojto 148:fd96258d940d 1911
Kojto 148:fd96258d940d 1912
Kojto 148:fd96258d940d 1913 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 1914 -- I2C Peripheral Access Layer
Kojto 148:fd96258d940d 1915 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 1916
Kojto 148:fd96258d940d 1917 /*!
Kojto 148:fd96258d940d 1918 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
Kojto 148:fd96258d940d 1919 * @{
Kojto 148:fd96258d940d 1920 */
Kojto 148:fd96258d940d 1921
Kojto 148:fd96258d940d 1922 /** I2C - Register Layout Typedef */
Kojto 148:fd96258d940d 1923 typedef struct {
Kojto 148:fd96258d940d 1924 uint8_t RESERVED_0[2048];
Kojto 148:fd96258d940d 1925 __IO uint32_t CFG; /**< Configuration for shared functions., offset: 0x800 */
Kojto 148:fd96258d940d 1926 __IO uint32_t STAT; /**< Status register for Master, Slave, and Monitor functions., offset: 0x804 */
Kojto 148:fd96258d940d 1927 __IO uint32_t INTENSET; /**< Interrupt Enable Set and read register., offset: 0x808 */
Kojto 148:fd96258d940d 1928 __O uint32_t INTENCLR; /**< Interrupt Enable Clear register., offset: 0x80C */
Kojto 148:fd96258d940d 1929 __IO uint32_t TIMEOUT; /**< Time-out value register., offset: 0x810 */
Kojto 148:fd96258d940d 1930 __IO uint32_t CLKDIV; /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x814 */
Kojto 148:fd96258d940d 1931 __I uint32_t INTSTAT; /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x818 */
Kojto 148:fd96258d940d 1932 uint8_t RESERVED_1[4];
Kojto 148:fd96258d940d 1933 __IO uint32_t MSTCTL; /**< Master control register., offset: 0x820 */
Kojto 148:fd96258d940d 1934 __IO uint32_t MSTTIME; /**< Master timing configuration., offset: 0x824 */
Kojto 148:fd96258d940d 1935 __IO uint32_t MSTDAT; /**< Combined Master receiver and transmitter data register., offset: 0x828 */
Kojto 148:fd96258d940d 1936 uint8_t RESERVED_2[20];
Kojto 148:fd96258d940d 1937 __IO uint32_t SLVCTL; /**< Slave control register., offset: 0x840 */
Kojto 148:fd96258d940d 1938 __IO uint32_t SLVDAT; /**< Combined Slave receiver and transmitter data register., offset: 0x844 */
Kojto 148:fd96258d940d 1939 __IO uint32_t SLVADR[4]; /**< Slave address register., array offset: 0x848, array step: 0x4 */
Kojto 148:fd96258d940d 1940 __IO uint32_t SLVQUAL0; /**< Slave Qualification for address 0., offset: 0x858 */
Kojto 148:fd96258d940d 1941 uint8_t RESERVED_3[36];
Kojto 148:fd96258d940d 1942 __I uint32_t MONRXDAT; /**< Monitor receiver data register., offset: 0x880 */
Kojto 148:fd96258d940d 1943 } I2C_Type;
Kojto 148:fd96258d940d 1944
Kojto 148:fd96258d940d 1945 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 1946 -- I2C Register Masks
Kojto 148:fd96258d940d 1947 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 1948
Kojto 148:fd96258d940d 1949 /*!
Kojto 148:fd96258d940d 1950 * @addtogroup I2C_Register_Masks I2C Register Masks
Kojto 148:fd96258d940d 1951 * @{
Kojto 148:fd96258d940d 1952 */
Kojto 148:fd96258d940d 1953
Kojto 148:fd96258d940d 1954 /*! @name CFG - Configuration for shared functions. */
Kojto 148:fd96258d940d 1955 #define I2C_CFG_MSTEN_MASK (0x1U)
Kojto 148:fd96258d940d 1956 #define I2C_CFG_MSTEN_SHIFT (0U)
Kojto 148:fd96258d940d 1957 #define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK)
Kojto 148:fd96258d940d 1958 #define I2C_CFG_SLVEN_MASK (0x2U)
Kojto 148:fd96258d940d 1959 #define I2C_CFG_SLVEN_SHIFT (1U)
Kojto 148:fd96258d940d 1960 #define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK)
Kojto 148:fd96258d940d 1961 #define I2C_CFG_MONEN_MASK (0x4U)
Kojto 148:fd96258d940d 1962 #define I2C_CFG_MONEN_SHIFT (2U)
Kojto 148:fd96258d940d 1963 #define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK)
Kojto 148:fd96258d940d 1964 #define I2C_CFG_TIMEOUTEN_MASK (0x8U)
Kojto 148:fd96258d940d 1965 #define I2C_CFG_TIMEOUTEN_SHIFT (3U)
Kojto 148:fd96258d940d 1966 #define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK)
Kojto 148:fd96258d940d 1967 #define I2C_CFG_MONCLKSTR_MASK (0x10U)
Kojto 148:fd96258d940d 1968 #define I2C_CFG_MONCLKSTR_SHIFT (4U)
Kojto 148:fd96258d940d 1969 #define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK)
Kojto 148:fd96258d940d 1970 #define I2C_CFG_HSCAPABLE_MASK (0x20U)
Kojto 148:fd96258d940d 1971 #define I2C_CFG_HSCAPABLE_SHIFT (5U)
Kojto 148:fd96258d940d 1972 #define I2C_CFG_HSCAPABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK)
Kojto 148:fd96258d940d 1973
Kojto 148:fd96258d940d 1974 /*! @name STAT - Status register for Master, Slave, and Monitor functions. */
Kojto 148:fd96258d940d 1975 #define I2C_STAT_MSTPENDING_MASK (0x1U)
Kojto 148:fd96258d940d 1976 #define I2C_STAT_MSTPENDING_SHIFT (0U)
Kojto 148:fd96258d940d 1977 #define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK)
Kojto 148:fd96258d940d 1978 #define I2C_STAT_MSTSTATE_MASK (0xEU)
Kojto 148:fd96258d940d 1979 #define I2C_STAT_MSTSTATE_SHIFT (1U)
Kojto 148:fd96258d940d 1980 #define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK)
Kojto 148:fd96258d940d 1981 #define I2C_STAT_MSTARBLOSS_MASK (0x10U)
Kojto 148:fd96258d940d 1982 #define I2C_STAT_MSTARBLOSS_SHIFT (4U)
Kojto 148:fd96258d940d 1983 #define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK)
Kojto 148:fd96258d940d 1984 #define I2C_STAT_MSTSTSTPERR_MASK (0x40U)
Kojto 148:fd96258d940d 1985 #define I2C_STAT_MSTSTSTPERR_SHIFT (6U)
Kojto 148:fd96258d940d 1986 #define I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK)
Kojto 148:fd96258d940d 1987 #define I2C_STAT_SLVPENDING_MASK (0x100U)
Kojto 148:fd96258d940d 1988 #define I2C_STAT_SLVPENDING_SHIFT (8U)
Kojto 148:fd96258d940d 1989 #define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK)
Kojto 148:fd96258d940d 1990 #define I2C_STAT_SLVSTATE_MASK (0x600U)
Kojto 148:fd96258d940d 1991 #define I2C_STAT_SLVSTATE_SHIFT (9U)
Kojto 148:fd96258d940d 1992 #define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK)
Kojto 148:fd96258d940d 1993 #define I2C_STAT_SLVNOTSTR_MASK (0x800U)
Kojto 148:fd96258d940d 1994 #define I2C_STAT_SLVNOTSTR_SHIFT (11U)
Kojto 148:fd96258d940d 1995 #define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK)
Kojto 148:fd96258d940d 1996 #define I2C_STAT_SLVIDX_MASK (0x3000U)
Kojto 148:fd96258d940d 1997 #define I2C_STAT_SLVIDX_SHIFT (12U)
Kojto 148:fd96258d940d 1998 #define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK)
Kojto 148:fd96258d940d 1999 #define I2C_STAT_SLVSEL_MASK (0x4000U)
Kojto 148:fd96258d940d 2000 #define I2C_STAT_SLVSEL_SHIFT (14U)
Kojto 148:fd96258d940d 2001 #define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK)
Kojto 148:fd96258d940d 2002 #define I2C_STAT_SLVDESEL_MASK (0x8000U)
Kojto 148:fd96258d940d 2003 #define I2C_STAT_SLVDESEL_SHIFT (15U)
Kojto 148:fd96258d940d 2004 #define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK)
Kojto 148:fd96258d940d 2005 #define I2C_STAT_MONRDY_MASK (0x10000U)
Kojto 148:fd96258d940d 2006 #define I2C_STAT_MONRDY_SHIFT (16U)
Kojto 148:fd96258d940d 2007 #define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK)
Kojto 148:fd96258d940d 2008 #define I2C_STAT_MONOV_MASK (0x20000U)
Kojto 148:fd96258d940d 2009 #define I2C_STAT_MONOV_SHIFT (17U)
Kojto 148:fd96258d940d 2010 #define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK)
Kojto 148:fd96258d940d 2011 #define I2C_STAT_MONACTIVE_MASK (0x40000U)
Kojto 148:fd96258d940d 2012 #define I2C_STAT_MONACTIVE_SHIFT (18U)
Kojto 148:fd96258d940d 2013 #define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK)
Kojto 148:fd96258d940d 2014 #define I2C_STAT_MONIDLE_MASK (0x80000U)
Kojto 148:fd96258d940d 2015 #define I2C_STAT_MONIDLE_SHIFT (19U)
Kojto 148:fd96258d940d 2016 #define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK)
Kojto 148:fd96258d940d 2017 #define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U)
Kojto 148:fd96258d940d 2018 #define I2C_STAT_EVENTTIMEOUT_SHIFT (24U)
Kojto 148:fd96258d940d 2019 #define I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK)
Kojto 148:fd96258d940d 2020 #define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U)
Kojto 148:fd96258d940d 2021 #define I2C_STAT_SCLTIMEOUT_SHIFT (25U)
Kojto 148:fd96258d940d 2022 #define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK)
Kojto 148:fd96258d940d 2023
Kojto 148:fd96258d940d 2024 /*! @name INTENSET - Interrupt Enable Set and read register. */
Kojto 148:fd96258d940d 2025 #define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U)
Kojto 148:fd96258d940d 2026 #define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U)
Kojto 148:fd96258d940d 2027 #define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK)
Kojto 148:fd96258d940d 2028 #define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U)
Kojto 148:fd96258d940d 2029 #define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U)
Kojto 148:fd96258d940d 2030 #define I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK)
Kojto 148:fd96258d940d 2031 #define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U)
Kojto 148:fd96258d940d 2032 #define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U)
Kojto 148:fd96258d940d 2033 #define I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK)
Kojto 148:fd96258d940d 2034 #define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U)
Kojto 148:fd96258d940d 2035 #define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U)
Kojto 148:fd96258d940d 2036 #define I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK)
Kojto 148:fd96258d940d 2037 #define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U)
Kojto 148:fd96258d940d 2038 #define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U)
Kojto 148:fd96258d940d 2039 #define I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK)
Kojto 148:fd96258d940d 2040 #define I2C_INTENSET_SLVDESELEN_MASK (0x8000U)
Kojto 148:fd96258d940d 2041 #define I2C_INTENSET_SLVDESELEN_SHIFT (15U)
Kojto 148:fd96258d940d 2042 #define I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK)
Kojto 148:fd96258d940d 2043 #define I2C_INTENSET_MONRDYEN_MASK (0x10000U)
Kojto 148:fd96258d940d 2044 #define I2C_INTENSET_MONRDYEN_SHIFT (16U)
Kojto 148:fd96258d940d 2045 #define I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK)
Kojto 148:fd96258d940d 2046 #define I2C_INTENSET_MONOVEN_MASK (0x20000U)
Kojto 148:fd96258d940d 2047 #define I2C_INTENSET_MONOVEN_SHIFT (17U)
Kojto 148:fd96258d940d 2048 #define I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK)
Kojto 148:fd96258d940d 2049 #define I2C_INTENSET_MONIDLEEN_MASK (0x80000U)
Kojto 148:fd96258d940d 2050 #define I2C_INTENSET_MONIDLEEN_SHIFT (19U)
Kojto 148:fd96258d940d 2051 #define I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK)
Kojto 148:fd96258d940d 2052 #define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U)
Kojto 148:fd96258d940d 2053 #define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U)
Kojto 148:fd96258d940d 2054 #define I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK)
Kojto 148:fd96258d940d 2055 #define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U)
Kojto 148:fd96258d940d 2056 #define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U)
Kojto 148:fd96258d940d 2057 #define I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK)
Kojto 148:fd96258d940d 2058
Kojto 148:fd96258d940d 2059 /*! @name INTENCLR - Interrupt Enable Clear register. */
Kojto 148:fd96258d940d 2060 #define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U)
Kojto 148:fd96258d940d 2061 #define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U)
Kojto 148:fd96258d940d 2062 #define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK)
Kojto 148:fd96258d940d 2063 #define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U)
Kojto 148:fd96258d940d 2064 #define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U)
Kojto 148:fd96258d940d 2065 #define I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK)
Kojto 148:fd96258d940d 2066 #define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U)
Kojto 148:fd96258d940d 2067 #define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U)
Kojto 148:fd96258d940d 2068 #define I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK)
Kojto 148:fd96258d940d 2069 #define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U)
Kojto 148:fd96258d940d 2070 #define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U)
Kojto 148:fd96258d940d 2071 #define I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK)
Kojto 148:fd96258d940d 2072 #define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U)
Kojto 148:fd96258d940d 2073 #define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U)
Kojto 148:fd96258d940d 2074 #define I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK)
Kojto 148:fd96258d940d 2075 #define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U)
Kojto 148:fd96258d940d 2076 #define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U)
Kojto 148:fd96258d940d 2077 #define I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK)
Kojto 148:fd96258d940d 2078 #define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U)
Kojto 148:fd96258d940d 2079 #define I2C_INTENCLR_MONRDYCLR_SHIFT (16U)
Kojto 148:fd96258d940d 2080 #define I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK)
Kojto 148:fd96258d940d 2081 #define I2C_INTENCLR_MONOVCLR_MASK (0x20000U)
Kojto 148:fd96258d940d 2082 #define I2C_INTENCLR_MONOVCLR_SHIFT (17U)
Kojto 148:fd96258d940d 2083 #define I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK)
Kojto 148:fd96258d940d 2084 #define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U)
Kojto 148:fd96258d940d 2085 #define I2C_INTENCLR_MONIDLECLR_SHIFT (19U)
Kojto 148:fd96258d940d 2086 #define I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK)
Kojto 148:fd96258d940d 2087 #define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U)
Kojto 148:fd96258d940d 2088 #define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U)
Kojto 148:fd96258d940d 2089 #define I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK)
Kojto 148:fd96258d940d 2090 #define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U)
Kojto 148:fd96258d940d 2091 #define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U)
Kojto 148:fd96258d940d 2092 #define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK)
Kojto 148:fd96258d940d 2093
Kojto 148:fd96258d940d 2094 /*! @name TIMEOUT - Time-out value register. */
Kojto 148:fd96258d940d 2095 #define I2C_TIMEOUT_TOMIN_MASK (0xFU)
Kojto 148:fd96258d940d 2096 #define I2C_TIMEOUT_TOMIN_SHIFT (0U)
Kojto 148:fd96258d940d 2097 #define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK)
Kojto 148:fd96258d940d 2098 #define I2C_TIMEOUT_TO_MASK (0xFFF0U)
Kojto 148:fd96258d940d 2099 #define I2C_TIMEOUT_TO_SHIFT (4U)
Kojto 148:fd96258d940d 2100 #define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK)
Kojto 148:fd96258d940d 2101
Kojto 148:fd96258d940d 2102 /*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */
Kojto 148:fd96258d940d 2103 #define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU)
Kojto 148:fd96258d940d 2104 #define I2C_CLKDIV_DIVVAL_SHIFT (0U)
Kojto 148:fd96258d940d 2105 #define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK)
Kojto 148:fd96258d940d 2106
Kojto 148:fd96258d940d 2107 /*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */
Kojto 148:fd96258d940d 2108 #define I2C_INTSTAT_MSTPENDING_MASK (0x1U)
Kojto 148:fd96258d940d 2109 #define I2C_INTSTAT_MSTPENDING_SHIFT (0U)
Kojto 148:fd96258d940d 2110 #define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK)
Kojto 148:fd96258d940d 2111 #define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U)
Kojto 148:fd96258d940d 2112 #define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U)
Kojto 148:fd96258d940d 2113 #define I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK)
Kojto 148:fd96258d940d 2114 #define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U)
Kojto 148:fd96258d940d 2115 #define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U)
Kojto 148:fd96258d940d 2116 #define I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK)
Kojto 148:fd96258d940d 2117 #define I2C_INTSTAT_SLVPENDING_MASK (0x100U)
Kojto 148:fd96258d940d 2118 #define I2C_INTSTAT_SLVPENDING_SHIFT (8U)
Kojto 148:fd96258d940d 2119 #define I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK)
Kojto 148:fd96258d940d 2120 #define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U)
Kojto 148:fd96258d940d 2121 #define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U)
Kojto 148:fd96258d940d 2122 #define I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK)
Kojto 148:fd96258d940d 2123 #define I2C_INTSTAT_SLVDESEL_MASK (0x8000U)
Kojto 148:fd96258d940d 2124 #define I2C_INTSTAT_SLVDESEL_SHIFT (15U)
Kojto 148:fd96258d940d 2125 #define I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK)
Kojto 148:fd96258d940d 2126 #define I2C_INTSTAT_MONRDY_MASK (0x10000U)
Kojto 148:fd96258d940d 2127 #define I2C_INTSTAT_MONRDY_SHIFT (16U)
Kojto 148:fd96258d940d 2128 #define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK)
Kojto 148:fd96258d940d 2129 #define I2C_INTSTAT_MONOV_MASK (0x20000U)
Kojto 148:fd96258d940d 2130 #define I2C_INTSTAT_MONOV_SHIFT (17U)
Kojto 148:fd96258d940d 2131 #define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK)
Kojto 148:fd96258d940d 2132 #define I2C_INTSTAT_MONIDLE_MASK (0x80000U)
Kojto 148:fd96258d940d 2133 #define I2C_INTSTAT_MONIDLE_SHIFT (19U)
Kojto 148:fd96258d940d 2134 #define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK)
Kojto 148:fd96258d940d 2135 #define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U)
Kojto 148:fd96258d940d 2136 #define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U)
Kojto 148:fd96258d940d 2137 #define I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK)
Kojto 148:fd96258d940d 2138 #define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U)
Kojto 148:fd96258d940d 2139 #define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U)
Kojto 148:fd96258d940d 2140 #define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK)
Kojto 148:fd96258d940d 2141
Kojto 148:fd96258d940d 2142 /*! @name MSTCTL - Master control register. */
Kojto 148:fd96258d940d 2143 #define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U)
Kojto 148:fd96258d940d 2144 #define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U)
Kojto 148:fd96258d940d 2145 #define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK)
Kojto 148:fd96258d940d 2146 #define I2C_MSTCTL_MSTSTART_MASK (0x2U)
Kojto 148:fd96258d940d 2147 #define I2C_MSTCTL_MSTSTART_SHIFT (1U)
Kojto 148:fd96258d940d 2148 #define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK)
Kojto 148:fd96258d940d 2149 #define I2C_MSTCTL_MSTSTOP_MASK (0x4U)
Kojto 148:fd96258d940d 2150 #define I2C_MSTCTL_MSTSTOP_SHIFT (2U)
Kojto 148:fd96258d940d 2151 #define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK)
Kojto 148:fd96258d940d 2152 #define I2C_MSTCTL_MSTDMA_MASK (0x8U)
Kojto 148:fd96258d940d 2153 #define I2C_MSTCTL_MSTDMA_SHIFT (3U)
Kojto 148:fd96258d940d 2154 #define I2C_MSTCTL_MSTDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK)
Kojto 148:fd96258d940d 2155
Kojto 148:fd96258d940d 2156 /*! @name MSTTIME - Master timing configuration. */
Kojto 148:fd96258d940d 2157 #define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U)
Kojto 148:fd96258d940d 2158 #define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U)
Kojto 148:fd96258d940d 2159 #define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK)
Kojto 148:fd96258d940d 2160 #define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U)
Kojto 148:fd96258d940d 2161 #define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U)
Kojto 148:fd96258d940d 2162 #define I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK)
Kojto 148:fd96258d940d 2163
Kojto 148:fd96258d940d 2164 /*! @name MSTDAT - Combined Master receiver and transmitter data register. */
Kojto 148:fd96258d940d 2165 #define I2C_MSTDAT_DATA_MASK (0xFFU)
Kojto 148:fd96258d940d 2166 #define I2C_MSTDAT_DATA_SHIFT (0U)
Kojto 148:fd96258d940d 2167 #define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK)
Kojto 148:fd96258d940d 2168
Kojto 148:fd96258d940d 2169 /*! @name SLVCTL - Slave control register. */
Kojto 148:fd96258d940d 2170 #define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U)
Kojto 148:fd96258d940d 2171 #define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U)
Kojto 148:fd96258d940d 2172 #define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK)
Kojto 148:fd96258d940d 2173 #define I2C_SLVCTL_SLVNACK_MASK (0x2U)
Kojto 148:fd96258d940d 2174 #define I2C_SLVCTL_SLVNACK_SHIFT (1U)
Kojto 148:fd96258d940d 2175 #define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK)
Kojto 148:fd96258d940d 2176 #define I2C_SLVCTL_SLVDMA_MASK (0x8U)
Kojto 148:fd96258d940d 2177 #define I2C_SLVCTL_SLVDMA_SHIFT (3U)
Kojto 148:fd96258d940d 2178 #define I2C_SLVCTL_SLVDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK)
Kojto 148:fd96258d940d 2179 #define I2C_SLVCTL_AUTOACK_MASK (0x100U)
Kojto 148:fd96258d940d 2180 #define I2C_SLVCTL_AUTOACK_SHIFT (8U)
Kojto 148:fd96258d940d 2181 #define I2C_SLVCTL_AUTOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK)
Kojto 148:fd96258d940d 2182 #define I2C_SLVCTL_AUTOMATCHREAD_MASK (0x200U)
Kojto 148:fd96258d940d 2183 #define I2C_SLVCTL_AUTOMATCHREAD_SHIFT (9U)
Kojto 148:fd96258d940d 2184 #define I2C_SLVCTL_AUTOMATCHREAD(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK)
Kojto 148:fd96258d940d 2185
Kojto 148:fd96258d940d 2186 /*! @name SLVDAT - Combined Slave receiver and transmitter data register. */
Kojto 148:fd96258d940d 2187 #define I2C_SLVDAT_DATA_MASK (0xFFU)
Kojto 148:fd96258d940d 2188 #define I2C_SLVDAT_DATA_SHIFT (0U)
Kojto 148:fd96258d940d 2189 #define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK)
Kojto 148:fd96258d940d 2190
Kojto 148:fd96258d940d 2191 /*! @name SLVADR - Slave address register. */
Kojto 148:fd96258d940d 2192 #define I2C_SLVADR_SADISABLE_MASK (0x1U)
Kojto 148:fd96258d940d 2193 #define I2C_SLVADR_SADISABLE_SHIFT (0U)
Kojto 148:fd96258d940d 2194 #define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK)
Kojto 148:fd96258d940d 2195 #define I2C_SLVADR_SLVADR_MASK (0xFEU)
Kojto 148:fd96258d940d 2196 #define I2C_SLVADR_SLVADR_SHIFT (1U)
Kojto 148:fd96258d940d 2197 #define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK)
Kojto 148:fd96258d940d 2198 #define I2C_SLVADR_AUTONACK_MASK (0x8000U)
Kojto 148:fd96258d940d 2199 #define I2C_SLVADR_AUTONACK_SHIFT (15U)
Kojto 148:fd96258d940d 2200 #define I2C_SLVADR_AUTONACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK)
Kojto 148:fd96258d940d 2201
Kojto 148:fd96258d940d 2202 /* The count of I2C_SLVADR */
Kojto 148:fd96258d940d 2203 #define I2C_SLVADR_COUNT (4U)
Kojto 148:fd96258d940d 2204
Kojto 148:fd96258d940d 2205 /*! @name SLVQUAL0 - Slave Qualification for address 0. */
Kojto 148:fd96258d940d 2206 #define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U)
Kojto 148:fd96258d940d 2207 #define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U)
Kojto 148:fd96258d940d 2208 #define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK)
Kojto 148:fd96258d940d 2209 #define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU)
Kojto 148:fd96258d940d 2210 #define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U)
Kojto 148:fd96258d940d 2211 #define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK)
Kojto 148:fd96258d940d 2212
Kojto 148:fd96258d940d 2213 /*! @name MONRXDAT - Monitor receiver data register. */
Kojto 148:fd96258d940d 2214 #define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU)
Kojto 148:fd96258d940d 2215 #define I2C_MONRXDAT_MONRXDAT_SHIFT (0U)
Kojto 148:fd96258d940d 2216 #define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK)
Kojto 148:fd96258d940d 2217 #define I2C_MONRXDAT_MONSTART_MASK (0x100U)
Kojto 148:fd96258d940d 2218 #define I2C_MONRXDAT_MONSTART_SHIFT (8U)
Kojto 148:fd96258d940d 2219 #define I2C_MONRXDAT_MONSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK)
Kojto 148:fd96258d940d 2220 #define I2C_MONRXDAT_MONRESTART_MASK (0x200U)
Kojto 148:fd96258d940d 2221 #define I2C_MONRXDAT_MONRESTART_SHIFT (9U)
Kojto 148:fd96258d940d 2222 #define I2C_MONRXDAT_MONRESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK)
Kojto 148:fd96258d940d 2223 #define I2C_MONRXDAT_MONNACK_MASK (0x400U)
Kojto 148:fd96258d940d 2224 #define I2C_MONRXDAT_MONNACK_SHIFT (10U)
Kojto 148:fd96258d940d 2225 #define I2C_MONRXDAT_MONNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK)
Kojto 148:fd96258d940d 2226
Kojto 148:fd96258d940d 2227
Kojto 148:fd96258d940d 2228 /*!
Kojto 148:fd96258d940d 2229 * @}
Kojto 148:fd96258d940d 2230 */ /* end of group I2C_Register_Masks */
Kojto 148:fd96258d940d 2231
Kojto 148:fd96258d940d 2232
Kojto 148:fd96258d940d 2233 /* I2C - Peripheral instance base addresses */
Kojto 148:fd96258d940d 2234 /** Peripheral I2C0 base address */
Kojto 148:fd96258d940d 2235 #define I2C0_BASE (0x40086000u)
Kojto 148:fd96258d940d 2236 /** Peripheral I2C0 base pointer */
Kojto 148:fd96258d940d 2237 #define I2C0 ((I2C_Type *)I2C0_BASE)
Kojto 148:fd96258d940d 2238 /** Peripheral I2C1 base address */
Kojto 148:fd96258d940d 2239 #define I2C1_BASE (0x40087000u)
Kojto 148:fd96258d940d 2240 /** Peripheral I2C1 base pointer */
Kojto 148:fd96258d940d 2241 #define I2C1 ((I2C_Type *)I2C1_BASE)
Kojto 148:fd96258d940d 2242 /** Peripheral I2C2 base address */
Kojto 148:fd96258d940d 2243 #define I2C2_BASE (0x40088000u)
Kojto 148:fd96258d940d 2244 /** Peripheral I2C2 base pointer */
Kojto 148:fd96258d940d 2245 #define I2C2 ((I2C_Type *)I2C2_BASE)
Kojto 148:fd96258d940d 2246 /** Peripheral I2C3 base address */
Kojto 148:fd96258d940d 2247 #define I2C3_BASE (0x40089000u)
Kojto 148:fd96258d940d 2248 /** Peripheral I2C3 base pointer */
Kojto 148:fd96258d940d 2249 #define I2C3 ((I2C_Type *)I2C3_BASE)
Kojto 148:fd96258d940d 2250 /** Peripheral I2C4 base address */
Kojto 148:fd96258d940d 2251 #define I2C4_BASE (0x4008A000u)
Kojto 148:fd96258d940d 2252 /** Peripheral I2C4 base pointer */
Kojto 148:fd96258d940d 2253 #define I2C4 ((I2C_Type *)I2C4_BASE)
Kojto 148:fd96258d940d 2254 /** Peripheral I2C5 base address */
Kojto 148:fd96258d940d 2255 #define I2C5_BASE (0x40096000u)
Kojto 148:fd96258d940d 2256 /** Peripheral I2C5 base pointer */
Kojto 148:fd96258d940d 2257 #define I2C5 ((I2C_Type *)I2C5_BASE)
Kojto 148:fd96258d940d 2258 /** Peripheral I2C6 base address */
Kojto 148:fd96258d940d 2259 #define I2C6_BASE (0x40097000u)
Kojto 148:fd96258d940d 2260 /** Peripheral I2C6 base pointer */
Kojto 148:fd96258d940d 2261 #define I2C6 ((I2C_Type *)I2C6_BASE)
Kojto 148:fd96258d940d 2262 /** Peripheral I2C7 base address */
Kojto 148:fd96258d940d 2263 #define I2C7_BASE (0x40098000u)
Kojto 148:fd96258d940d 2264 /** Peripheral I2C7 base pointer */
Kojto 148:fd96258d940d 2265 #define I2C7 ((I2C_Type *)I2C7_BASE)
Kojto 148:fd96258d940d 2266 /** Array initializer of I2C peripheral base addresses */
Kojto 148:fd96258d940d 2267 #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE }
Kojto 148:fd96258d940d 2268 /** Array initializer of I2C peripheral base pointers */
Kojto 148:fd96258d940d 2269 #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 }
Kojto 148:fd96258d940d 2270 /** Interrupt vectors for the I2C peripheral type */
Kojto 148:fd96258d940d 2271 #define I2C_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn }
Kojto 148:fd96258d940d 2272
Kojto 148:fd96258d940d 2273 /*!
Kojto 148:fd96258d940d 2274 * @}
Kojto 148:fd96258d940d 2275 */ /* end of group I2C_Peripheral_Access_Layer */
Kojto 148:fd96258d940d 2276
Kojto 148:fd96258d940d 2277
Kojto 148:fd96258d940d 2278 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 2279 -- I2S Peripheral Access Layer
Kojto 148:fd96258d940d 2280 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 2281
Kojto 148:fd96258d940d 2282 /*!
Kojto 148:fd96258d940d 2283 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
Kojto 148:fd96258d940d 2284 * @{
Kojto 148:fd96258d940d 2285 */
Kojto 148:fd96258d940d 2286
Kojto 148:fd96258d940d 2287 /** I2S - Register Layout Typedef */
Kojto 148:fd96258d940d 2288 typedef struct {
Kojto 148:fd96258d940d 2289 uint8_t RESERVED_0[3072];
Kojto 148:fd96258d940d 2290 __IO uint32_t CFG1; /**< Configuration register 1 for the primary channel pair., offset: 0xC00 */
Kojto 148:fd96258d940d 2291 __IO uint32_t CFG2; /**< Configuration register 2 for the primary channel pair., offset: 0xC04 */
Kojto 148:fd96258d940d 2292 __IO uint32_t STAT; /**< Status register for the primary channel pair., offset: 0xC08 */
Kojto 148:fd96258d940d 2293 uint8_t RESERVED_1[16];
Kojto 148:fd96258d940d 2294 __IO uint32_t DIV; /**< Clock divider, used by all channel pairs., offset: 0xC1C */
Kojto 148:fd96258d940d 2295 uint8_t RESERVED_2[480];
Kojto 148:fd96258d940d 2296 __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */
Kojto 148:fd96258d940d 2297 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */
Kojto 148:fd96258d940d 2298 __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */
Kojto 148:fd96258d940d 2299 uint8_t RESERVED_3[4];
Kojto 148:fd96258d940d 2300 __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */
Kojto 148:fd96258d940d 2301 __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */
Kojto 148:fd96258d940d 2302 __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */
Kojto 148:fd96258d940d 2303 uint8_t RESERVED_4[4];
Kojto 148:fd96258d940d 2304 __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */
Kojto 148:fd96258d940d 2305 __O uint32_t FIFOWR48H; /**< FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE24 */
Kojto 148:fd96258d940d 2306 uint8_t RESERVED_5[8];
Kojto 148:fd96258d940d 2307 __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */
Kojto 148:fd96258d940d 2308 __I uint32_t FIFORD48H; /**< FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE34 */
Kojto 148:fd96258d940d 2309 uint8_t RESERVED_6[8];
Kojto 148:fd96258d940d 2310 __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */
Kojto 148:fd96258d940d 2311 __I uint32_t FIFORD48HNOPOP; /**< FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE44 */
Kojto 148:fd96258d940d 2312 } I2S_Type;
Kojto 148:fd96258d940d 2313
Kojto 148:fd96258d940d 2314 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 2315 -- I2S Register Masks
Kojto 148:fd96258d940d 2316 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 2317
Kojto 148:fd96258d940d 2318 /*!
Kojto 148:fd96258d940d 2319 * @addtogroup I2S_Register_Masks I2S Register Masks
Kojto 148:fd96258d940d 2320 * @{
Kojto 148:fd96258d940d 2321 */
Kojto 148:fd96258d940d 2322
Kojto 148:fd96258d940d 2323 /*! @name CFG1 - Configuration register 1 for the primary channel pair. */
Kojto 148:fd96258d940d 2324 #define I2S_CFG1_MAINENABLE_MASK (0x1U)
Kojto 148:fd96258d940d 2325 #define I2S_CFG1_MAINENABLE_SHIFT (0U)
Kojto 148:fd96258d940d 2326 #define I2S_CFG1_MAINENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK)
Kojto 148:fd96258d940d 2327 #define I2S_CFG1_DATAPAUSE_MASK (0x2U)
Kojto 148:fd96258d940d 2328 #define I2S_CFG1_DATAPAUSE_SHIFT (1U)
Kojto 148:fd96258d940d 2329 #define I2S_CFG1_DATAPAUSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK)
Kojto 148:fd96258d940d 2330 #define I2S_CFG1_PAIRCOUNT_MASK (0xCU)
Kojto 148:fd96258d940d 2331 #define I2S_CFG1_PAIRCOUNT_SHIFT (2U)
Kojto 148:fd96258d940d 2332 #define I2S_CFG1_PAIRCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK)
Kojto 148:fd96258d940d 2333 #define I2S_CFG1_MSTSLVCFG_MASK (0x30U)
Kojto 148:fd96258d940d 2334 #define I2S_CFG1_MSTSLVCFG_SHIFT (4U)
Kojto 148:fd96258d940d 2335 #define I2S_CFG1_MSTSLVCFG(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK)
Kojto 148:fd96258d940d 2336 #define I2S_CFG1_MODE_MASK (0xC0U)
Kojto 148:fd96258d940d 2337 #define I2S_CFG1_MODE_SHIFT (6U)
Kojto 148:fd96258d940d 2338 #define I2S_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK)
Kojto 148:fd96258d940d 2339 #define I2S_CFG1_RIGHTLOW_MASK (0x100U)
Kojto 148:fd96258d940d 2340 #define I2S_CFG1_RIGHTLOW_SHIFT (8U)
Kojto 148:fd96258d940d 2341 #define I2S_CFG1_RIGHTLOW(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK)
Kojto 148:fd96258d940d 2342 #define I2S_CFG1_LEFTJUST_MASK (0x200U)
Kojto 148:fd96258d940d 2343 #define I2S_CFG1_LEFTJUST_SHIFT (9U)
Kojto 148:fd96258d940d 2344 #define I2S_CFG1_LEFTJUST(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK)
Kojto 148:fd96258d940d 2345 #define I2S_CFG1_ONECHANNEL_MASK (0x400U)
Kojto 148:fd96258d940d 2346 #define I2S_CFG1_ONECHANNEL_SHIFT (10U)
Kojto 148:fd96258d940d 2347 #define I2S_CFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK)
Kojto 148:fd96258d940d 2348 #define I2S_CFG1_PDMDATA_MASK (0x800U)
Kojto 148:fd96258d940d 2349 #define I2S_CFG1_PDMDATA_SHIFT (11U)
Kojto 148:fd96258d940d 2350 #define I2S_CFG1_PDMDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PDMDATA_SHIFT)) & I2S_CFG1_PDMDATA_MASK)
Kojto 148:fd96258d940d 2351 #define I2S_CFG1_SCK_POL_MASK (0x1000U)
Kojto 148:fd96258d940d 2352 #define I2S_CFG1_SCK_POL_SHIFT (12U)
Kojto 148:fd96258d940d 2353 #define I2S_CFG1_SCK_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK)
Kojto 148:fd96258d940d 2354 #define I2S_CFG1_WS_POL_MASK (0x2000U)
Kojto 148:fd96258d940d 2355 #define I2S_CFG1_WS_POL_SHIFT (13U)
Kojto 148:fd96258d940d 2356 #define I2S_CFG1_WS_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK)
Kojto 148:fd96258d940d 2357 #define I2S_CFG1_DATALEN_MASK (0x1F0000U)
Kojto 148:fd96258d940d 2358 #define I2S_CFG1_DATALEN_SHIFT (16U)
Kojto 148:fd96258d940d 2359 #define I2S_CFG1_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK)
Kojto 148:fd96258d940d 2360
Kojto 148:fd96258d940d 2361 /*! @name CFG2 - Configuration register 2 for the primary channel pair. */
Kojto 148:fd96258d940d 2362 #define I2S_CFG2_FRAMELEN_MASK (0x1FFU)
Kojto 148:fd96258d940d 2363 #define I2S_CFG2_FRAMELEN_SHIFT (0U)
Kojto 148:fd96258d940d 2364 #define I2S_CFG2_FRAMELEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK)
Kojto 148:fd96258d940d 2365 #define I2S_CFG2_POSITION_MASK (0x1FF0000U)
Kojto 148:fd96258d940d 2366 #define I2S_CFG2_POSITION_SHIFT (16U)
Kojto 148:fd96258d940d 2367 #define I2S_CFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK)
Kojto 148:fd96258d940d 2368
Kojto 148:fd96258d940d 2369 /*! @name STAT - Status register for the primary channel pair. */
Kojto 148:fd96258d940d 2370 #define I2S_STAT_BUSY_MASK (0x1U)
Kojto 148:fd96258d940d 2371 #define I2S_STAT_BUSY_SHIFT (0U)
Kojto 148:fd96258d940d 2372 #define I2S_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK)
Kojto 148:fd96258d940d 2373 #define I2S_STAT_SLVFRMERR_MASK (0x2U)
Kojto 148:fd96258d940d 2374 #define I2S_STAT_SLVFRMERR_SHIFT (1U)
Kojto 148:fd96258d940d 2375 #define I2S_STAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK)
Kojto 148:fd96258d940d 2376 #define I2S_STAT_LR_MASK (0x4U)
Kojto 148:fd96258d940d 2377 #define I2S_STAT_LR_SHIFT (2U)
Kojto 148:fd96258d940d 2378 #define I2S_STAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK)
Kojto 148:fd96258d940d 2379 #define I2S_STAT_DATAPAUSED_MASK (0x8U)
Kojto 148:fd96258d940d 2380 #define I2S_STAT_DATAPAUSED_SHIFT (3U)
Kojto 148:fd96258d940d 2381 #define I2S_STAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK)
Kojto 148:fd96258d940d 2382
Kojto 148:fd96258d940d 2383 /*! @name DIV - Clock divider, used by all channel pairs. */
Kojto 148:fd96258d940d 2384 #define I2S_DIV_DIV_MASK (0xFFFU)
Kojto 148:fd96258d940d 2385 #define I2S_DIV_DIV_SHIFT (0U)
Kojto 148:fd96258d940d 2386 #define I2S_DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK)
Kojto 148:fd96258d940d 2387
Kojto 148:fd96258d940d 2388 /*! @name FIFOCFG - FIFO configuration and enable register. */
Kojto 148:fd96258d940d 2389 #define I2S_FIFOCFG_ENABLETX_MASK (0x1U)
Kojto 148:fd96258d940d 2390 #define I2S_FIFOCFG_ENABLETX_SHIFT (0U)
Kojto 148:fd96258d940d 2391 #define I2S_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK)
Kojto 148:fd96258d940d 2392 #define I2S_FIFOCFG_ENABLERX_MASK (0x2U)
Kojto 148:fd96258d940d 2393 #define I2S_FIFOCFG_ENABLERX_SHIFT (1U)
Kojto 148:fd96258d940d 2394 #define I2S_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK)
Kojto 148:fd96258d940d 2395 #define I2S_FIFOCFG_TXI2SSE0_MASK (0x4U)
Kojto 148:fd96258d940d 2396 #define I2S_FIFOCFG_TXI2SSE0_SHIFT (2U)
Kojto 148:fd96258d940d 2397 #define I2S_FIFOCFG_TXI2SSE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SSE0_SHIFT)) & I2S_FIFOCFG_TXI2SSE0_MASK)
Kojto 148:fd96258d940d 2398 #define I2S_FIFOCFG_PACK48_MASK (0x8U)
Kojto 148:fd96258d940d 2399 #define I2S_FIFOCFG_PACK48_SHIFT (3U)
Kojto 148:fd96258d940d 2400 #define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK)
Kojto 148:fd96258d940d 2401 #define I2S_FIFOCFG_SIZE_MASK (0x30U)
Kojto 148:fd96258d940d 2402 #define I2S_FIFOCFG_SIZE_SHIFT (4U)
Kojto 148:fd96258d940d 2403 #define I2S_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK)
Kojto 148:fd96258d940d 2404 #define I2S_FIFOCFG_DMATX_MASK (0x1000U)
Kojto 148:fd96258d940d 2405 #define I2S_FIFOCFG_DMATX_SHIFT (12U)
Kojto 148:fd96258d940d 2406 #define I2S_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK)
Kojto 148:fd96258d940d 2407 #define I2S_FIFOCFG_DMARX_MASK (0x2000U)
Kojto 148:fd96258d940d 2408 #define I2S_FIFOCFG_DMARX_SHIFT (13U)
Kojto 148:fd96258d940d 2409 #define I2S_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK)
Kojto 148:fd96258d940d 2410 #define I2S_FIFOCFG_WAKETX_MASK (0x4000U)
Kojto 148:fd96258d940d 2411 #define I2S_FIFOCFG_WAKETX_SHIFT (14U)
Kojto 148:fd96258d940d 2412 #define I2S_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK)
Kojto 148:fd96258d940d 2413 #define I2S_FIFOCFG_WAKERX_MASK (0x8000U)
Kojto 148:fd96258d940d 2414 #define I2S_FIFOCFG_WAKERX_SHIFT (15U)
Kojto 148:fd96258d940d 2415 #define I2S_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK)
Kojto 148:fd96258d940d 2416 #define I2S_FIFOCFG_EMPTYTX_MASK (0x10000U)
Kojto 148:fd96258d940d 2417 #define I2S_FIFOCFG_EMPTYTX_SHIFT (16U)
Kojto 148:fd96258d940d 2418 #define I2S_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK)
Kojto 148:fd96258d940d 2419 #define I2S_FIFOCFG_EMPTYRX_MASK (0x20000U)
Kojto 148:fd96258d940d 2420 #define I2S_FIFOCFG_EMPTYRX_SHIFT (17U)
Kojto 148:fd96258d940d 2421 #define I2S_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK)
Kojto 148:fd96258d940d 2422 #define I2S_FIFOCFG_POPDBG_MASK (0x40000U)
Kojto 148:fd96258d940d 2423 #define I2S_FIFOCFG_POPDBG_SHIFT (18U)
Kojto 148:fd96258d940d 2424 #define I2S_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_POPDBG_SHIFT)) & I2S_FIFOCFG_POPDBG_MASK)
Kojto 148:fd96258d940d 2425
Kojto 148:fd96258d940d 2426 /*! @name FIFOSTAT - FIFO status register. */
Kojto 148:fd96258d940d 2427 #define I2S_FIFOSTAT_TXERR_MASK (0x1U)
Kojto 148:fd96258d940d 2428 #define I2S_FIFOSTAT_TXERR_SHIFT (0U)
Kojto 148:fd96258d940d 2429 #define I2S_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK)
Kojto 148:fd96258d940d 2430 #define I2S_FIFOSTAT_RXERR_MASK (0x2U)
Kojto 148:fd96258d940d 2431 #define I2S_FIFOSTAT_RXERR_SHIFT (1U)
Kojto 148:fd96258d940d 2432 #define I2S_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK)
Kojto 148:fd96258d940d 2433 #define I2S_FIFOSTAT_PERINT_MASK (0x8U)
Kojto 148:fd96258d940d 2434 #define I2S_FIFOSTAT_PERINT_SHIFT (3U)
Kojto 148:fd96258d940d 2435 #define I2S_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK)
Kojto 148:fd96258d940d 2436 #define I2S_FIFOSTAT_TXEMPTY_MASK (0x10U)
Kojto 148:fd96258d940d 2437 #define I2S_FIFOSTAT_TXEMPTY_SHIFT (4U)
Kojto 148:fd96258d940d 2438 #define I2S_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK)
Kojto 148:fd96258d940d 2439 #define I2S_FIFOSTAT_TXNOTFULL_MASK (0x20U)
Kojto 148:fd96258d940d 2440 #define I2S_FIFOSTAT_TXNOTFULL_SHIFT (5U)
Kojto 148:fd96258d940d 2441 #define I2S_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK)
Kojto 148:fd96258d940d 2442 #define I2S_FIFOSTAT_RXNOTEMPTY_MASK (0x40U)
Kojto 148:fd96258d940d 2443 #define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT (6U)
Kojto 148:fd96258d940d 2444 #define I2S_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK)
Kojto 148:fd96258d940d 2445 #define I2S_FIFOSTAT_RXFULL_MASK (0x80U)
Kojto 148:fd96258d940d 2446 #define I2S_FIFOSTAT_RXFULL_SHIFT (7U)
Kojto 148:fd96258d940d 2447 #define I2S_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK)
Kojto 148:fd96258d940d 2448 #define I2S_FIFOSTAT_TXLVL_MASK (0x1F00U)
Kojto 148:fd96258d940d 2449 #define I2S_FIFOSTAT_TXLVL_SHIFT (8U)
Kojto 148:fd96258d940d 2450 #define I2S_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK)
Kojto 148:fd96258d940d 2451 #define I2S_FIFOSTAT_RXLVL_MASK (0x1F0000U)
Kojto 148:fd96258d940d 2452 #define I2S_FIFOSTAT_RXLVL_SHIFT (16U)
Kojto 148:fd96258d940d 2453 #define I2S_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK)
Kojto 148:fd96258d940d 2454
Kojto 148:fd96258d940d 2455 /*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */
Kojto 148:fd96258d940d 2456 #define I2S_FIFOTRIG_TXLVLENA_MASK (0x1U)
Kojto 148:fd96258d940d 2457 #define I2S_FIFOTRIG_TXLVLENA_SHIFT (0U)
Kojto 148:fd96258d940d 2458 #define I2S_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK)
Kojto 148:fd96258d940d 2459 #define I2S_FIFOTRIG_RXLVLENA_MASK (0x2U)
Kojto 148:fd96258d940d 2460 #define I2S_FIFOTRIG_RXLVLENA_SHIFT (1U)
Kojto 148:fd96258d940d 2461 #define I2S_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK)
Kojto 148:fd96258d940d 2462 #define I2S_FIFOTRIG_TXLVL_MASK (0xF00U)
Kojto 148:fd96258d940d 2463 #define I2S_FIFOTRIG_TXLVL_SHIFT (8U)
Kojto 148:fd96258d940d 2464 #define I2S_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK)
Kojto 148:fd96258d940d 2465 #define I2S_FIFOTRIG_RXLVL_MASK (0xF0000U)
Kojto 148:fd96258d940d 2466 #define I2S_FIFOTRIG_RXLVL_SHIFT (16U)
Kojto 148:fd96258d940d 2467 #define I2S_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK)
Kojto 148:fd96258d940d 2468
Kojto 148:fd96258d940d 2469 /*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */
Kojto 148:fd96258d940d 2470 #define I2S_FIFOINTENSET_TXERR_MASK (0x1U)
Kojto 148:fd96258d940d 2471 #define I2S_FIFOINTENSET_TXERR_SHIFT (0U)
Kojto 148:fd96258d940d 2472 #define I2S_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK)
Kojto 148:fd96258d940d 2473 #define I2S_FIFOINTENSET_RXERR_MASK (0x2U)
Kojto 148:fd96258d940d 2474 #define I2S_FIFOINTENSET_RXERR_SHIFT (1U)
Kojto 148:fd96258d940d 2475 #define I2S_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK)
Kojto 148:fd96258d940d 2476 #define I2S_FIFOINTENSET_TXLVL_MASK (0x4U)
Kojto 148:fd96258d940d 2477 #define I2S_FIFOINTENSET_TXLVL_SHIFT (2U)
Kojto 148:fd96258d940d 2478 #define I2S_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK)
Kojto 148:fd96258d940d 2479 #define I2S_FIFOINTENSET_RXLVL_MASK (0x8U)
Kojto 148:fd96258d940d 2480 #define I2S_FIFOINTENSET_RXLVL_SHIFT (3U)
Kojto 148:fd96258d940d 2481 #define I2S_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK)
Kojto 148:fd96258d940d 2482
Kojto 148:fd96258d940d 2483 /*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */
Kojto 148:fd96258d940d 2484 #define I2S_FIFOINTENCLR_TXERR_MASK (0x1U)
Kojto 148:fd96258d940d 2485 #define I2S_FIFOINTENCLR_TXERR_SHIFT (0U)
Kojto 148:fd96258d940d 2486 #define I2S_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK)
Kojto 148:fd96258d940d 2487 #define I2S_FIFOINTENCLR_RXERR_MASK (0x2U)
Kojto 148:fd96258d940d 2488 #define I2S_FIFOINTENCLR_RXERR_SHIFT (1U)
Kojto 148:fd96258d940d 2489 #define I2S_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK)
Kojto 148:fd96258d940d 2490 #define I2S_FIFOINTENCLR_TXLVL_MASK (0x4U)
Kojto 148:fd96258d940d 2491 #define I2S_FIFOINTENCLR_TXLVL_SHIFT (2U)
Kojto 148:fd96258d940d 2492 #define I2S_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK)
Kojto 148:fd96258d940d 2493 #define I2S_FIFOINTENCLR_RXLVL_MASK (0x8U)
Kojto 148:fd96258d940d 2494 #define I2S_FIFOINTENCLR_RXLVL_SHIFT (3U)
Kojto 148:fd96258d940d 2495 #define I2S_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK)
Kojto 148:fd96258d940d 2496
Kojto 148:fd96258d940d 2497 /*! @name FIFOINTSTAT - FIFO interrupt status register. */
Kojto 148:fd96258d940d 2498 #define I2S_FIFOINTSTAT_TXERR_MASK (0x1U)
Kojto 148:fd96258d940d 2499 #define I2S_FIFOINTSTAT_TXERR_SHIFT (0U)
Kojto 148:fd96258d940d 2500 #define I2S_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK)
Kojto 148:fd96258d940d 2501 #define I2S_FIFOINTSTAT_RXERR_MASK (0x2U)
Kojto 148:fd96258d940d 2502 #define I2S_FIFOINTSTAT_RXERR_SHIFT (1U)
Kojto 148:fd96258d940d 2503 #define I2S_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK)
Kojto 148:fd96258d940d 2504 #define I2S_FIFOINTSTAT_TXLVL_MASK (0x4U)
Kojto 148:fd96258d940d 2505 #define I2S_FIFOINTSTAT_TXLVL_SHIFT (2U)
Kojto 148:fd96258d940d 2506 #define I2S_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK)
Kojto 148:fd96258d940d 2507 #define I2S_FIFOINTSTAT_RXLVL_MASK (0x8U)
Kojto 148:fd96258d940d 2508 #define I2S_FIFOINTSTAT_RXLVL_SHIFT (3U)
Kojto 148:fd96258d940d 2509 #define I2S_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK)
Kojto 148:fd96258d940d 2510 #define I2S_FIFOINTSTAT_PERINT_MASK (0x10U)
Kojto 148:fd96258d940d 2511 #define I2S_FIFOINTSTAT_PERINT_SHIFT (4U)
Kojto 148:fd96258d940d 2512 #define I2S_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK)
Kojto 148:fd96258d940d 2513
Kojto 148:fd96258d940d 2514 /*! @name FIFOWR - FIFO write data. */
Kojto 148:fd96258d940d 2515 #define I2S_FIFOWR_TXDATA_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 2516 #define I2S_FIFOWR_TXDATA_SHIFT (0U)
Kojto 148:fd96258d940d 2517 #define I2S_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK)
Kojto 148:fd96258d940d 2518
Kojto 148:fd96258d940d 2519 /*! @name FIFOWR48H - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */
Kojto 148:fd96258d940d 2520 #define I2S_FIFOWR48H_TXDATA_MASK (0xFFFFFFU)
Kojto 148:fd96258d940d 2521 #define I2S_FIFOWR48H_TXDATA_SHIFT (0U)
Kojto 148:fd96258d940d 2522 #define I2S_FIFOWR48H_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK)
Kojto 148:fd96258d940d 2523
Kojto 148:fd96258d940d 2524 /*! @name FIFORD - FIFO read data. */
Kojto 148:fd96258d940d 2525 #define I2S_FIFORD_RXDATA_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 2526 #define I2S_FIFORD_RXDATA_SHIFT (0U)
Kojto 148:fd96258d940d 2527 #define I2S_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK)
Kojto 148:fd96258d940d 2528
Kojto 148:fd96258d940d 2529 /*! @name FIFORD48H - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */
Kojto 148:fd96258d940d 2530 #define I2S_FIFORD48H_RXDATA_MASK (0xFFFFFFU)
Kojto 148:fd96258d940d 2531 #define I2S_FIFORD48H_RXDATA_SHIFT (0U)
Kojto 148:fd96258d940d 2532 #define I2S_FIFORD48H_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK)
Kojto 148:fd96258d940d 2533
Kojto 148:fd96258d940d 2534 /*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */
Kojto 148:fd96258d940d 2535 #define I2S_FIFORDNOPOP_RXDATA_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 2536 #define I2S_FIFORDNOPOP_RXDATA_SHIFT (0U)
Kojto 148:fd96258d940d 2537 #define I2S_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK)
Kojto 148:fd96258d940d 2538
Kojto 148:fd96258d940d 2539 /*! @name FIFORD48HNOPOP - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */
Kojto 148:fd96258d940d 2540 #define I2S_FIFORD48HNOPOP_RXDATA_MASK (0xFFFFFFU)
Kojto 148:fd96258d940d 2541 #define I2S_FIFORD48HNOPOP_RXDATA_SHIFT (0U)
Kojto 148:fd96258d940d 2542 #define I2S_FIFORD48HNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK)
Kojto 148:fd96258d940d 2543
Kojto 148:fd96258d940d 2544
Kojto 148:fd96258d940d 2545 /*!
Kojto 148:fd96258d940d 2546 * @}
Kojto 148:fd96258d940d 2547 */ /* end of group I2S_Register_Masks */
Kojto 148:fd96258d940d 2548
Kojto 148:fd96258d940d 2549
Kojto 148:fd96258d940d 2550 /* I2S - Peripheral instance base addresses */
Kojto 148:fd96258d940d 2551 /** Peripheral I2S0 base address */
Kojto 148:fd96258d940d 2552 #define I2S0_BASE (0x40097000u)
Kojto 148:fd96258d940d 2553 /** Peripheral I2S0 base pointer */
Kojto 148:fd96258d940d 2554 #define I2S0 ((I2S_Type *)I2S0_BASE)
Kojto 148:fd96258d940d 2555 /** Peripheral I2S1 base address */
Kojto 148:fd96258d940d 2556 #define I2S1_BASE (0x40098000u)
Kojto 148:fd96258d940d 2557 /** Peripheral I2S1 base pointer */
Kojto 148:fd96258d940d 2558 #define I2S1 ((I2S_Type *)I2S1_BASE)
Kojto 148:fd96258d940d 2559 /** Array initializer of I2S peripheral base addresses */
Kojto 148:fd96258d940d 2560 #define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE }
Kojto 148:fd96258d940d 2561 /** Array initializer of I2S peripheral base pointers */
Kojto 148:fd96258d940d 2562 #define I2S_BASE_PTRS { I2S0, I2S1 }
Kojto 148:fd96258d940d 2563 /** Interrupt vectors for the I2S peripheral type */
Kojto 148:fd96258d940d 2564 #define I2S_IRQS { FLEXCOMM6_IRQn, FLEXCOMM7_IRQn }
Kojto 148:fd96258d940d 2565
Kojto 148:fd96258d940d 2566 /*!
Kojto 148:fd96258d940d 2567 * @}
Kojto 148:fd96258d940d 2568 */ /* end of group I2S_Peripheral_Access_Layer */
Kojto 148:fd96258d940d 2569
Kojto 148:fd96258d940d 2570
Kojto 148:fd96258d940d 2571 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 2572 -- INPUTMUX Peripheral Access Layer
Kojto 148:fd96258d940d 2573 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 2574
Kojto 148:fd96258d940d 2575 /*!
Kojto 148:fd96258d940d 2576 * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer
Kojto 148:fd96258d940d 2577 * @{
Kojto 148:fd96258d940d 2578 */
Kojto 148:fd96258d940d 2579
Kojto 148:fd96258d940d 2580 /** INPUTMUX - Register Layout Typedef */
Kojto 148:fd96258d940d 2581 typedef struct {
Kojto 148:fd96258d940d 2582 uint8_t RESERVED_0[192];
Kojto 148:fd96258d940d 2583 __IO uint32_t PINTSEL[8]; /**< Pin interrupt select register, array offset: 0xC0, array step: 0x4 */
Kojto 148:fd96258d940d 2584 __IO uint32_t DMA_ITRIG_INMUX[22]; /**< Trigger select register for DMA channel, array offset: 0xE0, array step: 0x4 */
Kojto 148:fd96258d940d 2585 uint8_t RESERVED_1[40];
Kojto 148:fd96258d940d 2586 __IO uint32_t DMA_OTRIG_INMUX[4]; /**< DMA output trigger selection to become DMA trigger, array offset: 0x160, array step: 0x4 */
Kojto 148:fd96258d940d 2587 uint8_t RESERVED_2[16];
Kojto 148:fd96258d940d 2588 __IO uint32_t FREQMEAS_REF; /**< Selection for frequency measurement reference clock, offset: 0x180 */
Kojto 148:fd96258d940d 2589 __IO uint32_t FREQMEAS_TARGET; /**< Selection for frequency measurement target clock, offset: 0x184 */
Kojto 148:fd96258d940d 2590 } INPUTMUX_Type;
Kojto 148:fd96258d940d 2591
Kojto 148:fd96258d940d 2592 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 2593 -- INPUTMUX Register Masks
Kojto 148:fd96258d940d 2594 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 2595
Kojto 148:fd96258d940d 2596 /*!
Kojto 148:fd96258d940d 2597 * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks
Kojto 148:fd96258d940d 2598 * @{
Kojto 148:fd96258d940d 2599 */
Kojto 148:fd96258d940d 2600
Kojto 148:fd96258d940d 2601 /*! @name PINTSEL - Pin interrupt select register */
Kojto 148:fd96258d940d 2602 #define INPUTMUX_PINTSEL_INTPIN_MASK (0xFFU)
Kojto 148:fd96258d940d 2603 #define INPUTMUX_PINTSEL_INTPIN_SHIFT (0U)
Kojto 148:fd96258d940d 2604 #define INPUTMUX_PINTSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK)
Kojto 148:fd96258d940d 2605
Kojto 148:fd96258d940d 2606 /* The count of INPUTMUX_PINTSEL */
Kojto 148:fd96258d940d 2607 #define INPUTMUX_PINTSEL_COUNT (8U)
Kojto 148:fd96258d940d 2608
Kojto 148:fd96258d940d 2609 /*! @name DMA_ITRIG_INMUX - Trigger select register for DMA channel */
Kojto 148:fd96258d940d 2610 #define INPUTMUX_DMA_ITRIG_INMUX_INP_MASK (0x1FU)
Kojto 148:fd96258d940d 2611 #define INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT (0U)
Kojto 148:fd96258d940d 2612 #define INPUTMUX_DMA_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_ITRIG_INMUX_INP_MASK)
Kojto 148:fd96258d940d 2613
Kojto 148:fd96258d940d 2614 /* The count of INPUTMUX_DMA_ITRIG_INMUX */
Kojto 148:fd96258d940d 2615 #define INPUTMUX_DMA_ITRIG_INMUX_COUNT (22U)
Kojto 148:fd96258d940d 2616
Kojto 148:fd96258d940d 2617 /*! @name DMA_OTRIG_INMUX - DMA output trigger selection to become DMA trigger */
Kojto 148:fd96258d940d 2618 #define INPUTMUX_DMA_OTRIG_INMUX_INP_MASK (0x1FU)
Kojto 148:fd96258d940d 2619 #define INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT (0U)
Kojto 148:fd96258d940d 2620 #define INPUTMUX_DMA_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_OTRIG_INMUX_INP_MASK)
Kojto 148:fd96258d940d 2621
Kojto 148:fd96258d940d 2622 /* The count of INPUTMUX_DMA_OTRIG_INMUX */
Kojto 148:fd96258d940d 2623 #define INPUTMUX_DMA_OTRIG_INMUX_COUNT (4U)
Kojto 148:fd96258d940d 2624
Kojto 148:fd96258d940d 2625 /*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */
Kojto 148:fd96258d940d 2626 #define INPUTMUX_FREQMEAS_REF_CLKIN_MASK (0x1FU)
Kojto 148:fd96258d940d 2627 #define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT (0U)
Kojto 148:fd96258d940d 2628 #define INPUTMUX_FREQMEAS_REF_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK)
Kojto 148:fd96258d940d 2629
Kojto 148:fd96258d940d 2630 /*! @name FREQMEAS_TARGET - Selection for frequency measurement target clock */
Kojto 148:fd96258d940d 2631 #define INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK (0x1FU)
Kojto 148:fd96258d940d 2632 #define INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT (0U)
Kojto 148:fd96258d940d 2633 #define INPUTMUX_FREQMEAS_TARGET_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK)
Kojto 148:fd96258d940d 2634
Kojto 148:fd96258d940d 2635
Kojto 148:fd96258d940d 2636 /*!
Kojto 148:fd96258d940d 2637 * @}
Kojto 148:fd96258d940d 2638 */ /* end of group INPUTMUX_Register_Masks */
Kojto 148:fd96258d940d 2639
Kojto 148:fd96258d940d 2640
Kojto 148:fd96258d940d 2641 /* INPUTMUX - Peripheral instance base addresses */
Kojto 148:fd96258d940d 2642 /** Peripheral INPUTMUX base address */
Kojto 148:fd96258d940d 2643 #define INPUTMUX_BASE (0x40005000u)
Kojto 148:fd96258d940d 2644 /** Peripheral INPUTMUX base pointer */
Kojto 148:fd96258d940d 2645 #define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE)
Kojto 148:fd96258d940d 2646 /** Array initializer of INPUTMUX peripheral base addresses */
Kojto 148:fd96258d940d 2647 #define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE }
Kojto 148:fd96258d940d 2648 /** Array initializer of INPUTMUX peripheral base pointers */
Kojto 148:fd96258d940d 2649 #define INPUTMUX_BASE_PTRS { INPUTMUX }
Kojto 148:fd96258d940d 2650
Kojto 148:fd96258d940d 2651 /*!
Kojto 148:fd96258d940d 2652 * @}
Kojto 148:fd96258d940d 2653 */ /* end of group INPUTMUX_Peripheral_Access_Layer */
Kojto 148:fd96258d940d 2654
Kojto 148:fd96258d940d 2655
Kojto 148:fd96258d940d 2656 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 2657 -- IOCON Peripheral Access Layer
Kojto 148:fd96258d940d 2658 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 2659
Kojto 148:fd96258d940d 2660 /*!
Kojto 148:fd96258d940d 2661 * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer
Kojto 148:fd96258d940d 2662 * @{
Kojto 148:fd96258d940d 2663 */
Kojto 148:fd96258d940d 2664
Kojto 148:fd96258d940d 2665 /** IOCON - Register Layout Typedef */
Kojto 148:fd96258d940d 2666 typedef struct {
Kojto 148:fd96258d940d 2667 __IO uint32_t PIO[2][32]; /**< Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31, array offset: 0x0, array step: index*0x80, index2*0x4 */
Kojto 148:fd96258d940d 2668 } IOCON_Type;
Kojto 148:fd96258d940d 2669
Kojto 148:fd96258d940d 2670 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 2671 -- IOCON Register Masks
Kojto 148:fd96258d940d 2672 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 2673
Kojto 148:fd96258d940d 2674 /*!
Kojto 148:fd96258d940d 2675 * @addtogroup IOCON_Register_Masks IOCON Register Masks
Kojto 148:fd96258d940d 2676 * @{
Kojto 148:fd96258d940d 2677 */
Kojto 148:fd96258d940d 2678
Kojto 148:fd96258d940d 2679 /*! @name PIO - Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31 */
Kojto 148:fd96258d940d 2680 #define IOCON_PIO_FUNC_MASK (0x7U)
Kojto 148:fd96258d940d 2681 #define IOCON_PIO_FUNC_SHIFT (0U)
Kojto 148:fd96258d940d 2682 #define IOCON_PIO_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK)
Kojto 148:fd96258d940d 2683 #define IOCON_PIO_MODE_MASK (0x18U)
Kojto 148:fd96258d940d 2684 #define IOCON_PIO_MODE_SHIFT (3U)
Kojto 148:fd96258d940d 2685 #define IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK)
Kojto 148:fd96258d940d 2686 #define IOCON_PIO_I2CSLEW_MASK (0x20U)
Kojto 148:fd96258d940d 2687 #define IOCON_PIO_I2CSLEW_SHIFT (5U)
Kojto 148:fd96258d940d 2688 #define IOCON_PIO_I2CSLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CSLEW_SHIFT)) & IOCON_PIO_I2CSLEW_MASK)
Kojto 148:fd96258d940d 2689 #define IOCON_PIO_INVERT_MASK (0x40U)
Kojto 148:fd96258d940d 2690 #define IOCON_PIO_INVERT_SHIFT (6U)
Kojto 148:fd96258d940d 2691 #define IOCON_PIO_INVERT(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INVERT_SHIFT)) & IOCON_PIO_INVERT_MASK)
Kojto 148:fd96258d940d 2692 #define IOCON_PIO_DIGIMODE_MASK (0x80U)
Kojto 148:fd96258d940d 2693 #define IOCON_PIO_DIGIMODE_SHIFT (7U)
Kojto 148:fd96258d940d 2694 #define IOCON_PIO_DIGIMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK)
Kojto 148:fd96258d940d 2695 #define IOCON_PIO_FILTEROFF_MASK (0x100U)
Kojto 148:fd96258d940d 2696 #define IOCON_PIO_FILTEROFF_SHIFT (8U)
Kojto 148:fd96258d940d 2697 #define IOCON_PIO_FILTEROFF(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK)
Kojto 148:fd96258d940d 2698 #define IOCON_PIO_I2CDRIVE_MASK (0x200U)
Kojto 148:fd96258d940d 2699 #define IOCON_PIO_I2CDRIVE_SHIFT (9U)
Kojto 148:fd96258d940d 2700 #define IOCON_PIO_I2CDRIVE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CDRIVE_SHIFT)) & IOCON_PIO_I2CDRIVE_MASK)
Kojto 148:fd96258d940d 2701 #define IOCON_PIO_SLEW_MASK (0x200U)
Kojto 148:fd96258d940d 2702 #define IOCON_PIO_SLEW_SHIFT (9U)
Kojto 148:fd96258d940d 2703 #define IOCON_PIO_SLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK)
Kojto 148:fd96258d940d 2704 #define IOCON_PIO_OD_MASK (0x400U)
Kojto 148:fd96258d940d 2705 #define IOCON_PIO_OD_SHIFT (10U)
Kojto 148:fd96258d940d 2706 #define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK)
Kojto 148:fd96258d940d 2707 #define IOCON_PIO_I2CFILTER_MASK (0x400U)
Kojto 148:fd96258d940d 2708 #define IOCON_PIO_I2CFILTER_SHIFT (10U)
Kojto 148:fd96258d940d 2709 #define IOCON_PIO_I2CFILTER(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTER_SHIFT)) & IOCON_PIO_I2CFILTER_MASK)
Kojto 148:fd96258d940d 2710
Kojto 148:fd96258d940d 2711 /* The count of IOCON_PIO */
Kojto 148:fd96258d940d 2712 #define IOCON_PIO_COUNT (2U)
Kojto 148:fd96258d940d 2713
Kojto 148:fd96258d940d 2714 /* The count of IOCON_PIO */
Kojto 148:fd96258d940d 2715 #define IOCON_PIO_COUNT2 (32U)
Kojto 148:fd96258d940d 2716
Kojto 148:fd96258d940d 2717
Kojto 148:fd96258d940d 2718 /*!
Kojto 148:fd96258d940d 2719 * @}
Kojto 148:fd96258d940d 2720 */ /* end of group IOCON_Register_Masks */
Kojto 148:fd96258d940d 2721
Kojto 148:fd96258d940d 2722
Kojto 148:fd96258d940d 2723 /* IOCON - Peripheral instance base addresses */
Kojto 148:fd96258d940d 2724 /** Peripheral IOCON base address */
Kojto 148:fd96258d940d 2725 #define IOCON_BASE (0x40001000u)
Kojto 148:fd96258d940d 2726 /** Peripheral IOCON base pointer */
Kojto 148:fd96258d940d 2727 #define IOCON ((IOCON_Type *)IOCON_BASE)
Kojto 148:fd96258d940d 2728 /** Array initializer of IOCON peripheral base addresses */
Kojto 148:fd96258d940d 2729 #define IOCON_BASE_ADDRS { IOCON_BASE }
Kojto 148:fd96258d940d 2730 /** Array initializer of IOCON peripheral base pointers */
Kojto 148:fd96258d940d 2731 #define IOCON_BASE_PTRS { IOCON }
Kojto 148:fd96258d940d 2732
Kojto 148:fd96258d940d 2733 /*!
Kojto 148:fd96258d940d 2734 * @}
Kojto 148:fd96258d940d 2735 */ /* end of group IOCON_Peripheral_Access_Layer */
Kojto 148:fd96258d940d 2736
Kojto 148:fd96258d940d 2737
Kojto 148:fd96258d940d 2738 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 2739 -- MAILBOX Peripheral Access Layer
Kojto 148:fd96258d940d 2740 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 2741
Kojto 148:fd96258d940d 2742 /*!
Kojto 148:fd96258d940d 2743 * @addtogroup MAILBOX_Peripheral_Access_Layer MAILBOX Peripheral Access Layer
Kojto 148:fd96258d940d 2744 * @{
Kojto 148:fd96258d940d 2745 */
Kojto 148:fd96258d940d 2746
Kojto 148:fd96258d940d 2747 /** MAILBOX - Register Layout Typedef */
Kojto 148:fd96258d940d 2748 typedef struct {
Kojto 148:fd96258d940d 2749 struct { /* offset: 0x0, array step: 0x10 */
Kojto 148:fd96258d940d 2750 __IO uint32_t IRQ; /**< Interrupt request register for the Cortex-M0+ CPU., array offset: 0x0, array step: 0x10 */
Kojto 148:fd96258d940d 2751 __O uint32_t IRQSET; /**< Set bits in IRQ0, array offset: 0x4, array step: 0x10 */
Kojto 148:fd96258d940d 2752 __O uint32_t IRQCLR; /**< Clear bits in IRQ0, array offset: 0x8, array step: 0x10 */
Kojto 148:fd96258d940d 2753 uint8_t RESERVED_0[4];
Kojto 148:fd96258d940d 2754 } MBOXIRQ[2];
Kojto 148:fd96258d940d 2755 uint8_t RESERVED_0[216];
Kojto 148:fd96258d940d 2756 __IO uint32_t MUTEX; /**< Mutual exclusion register[1], offset: 0xF8 */
Kojto 148:fd96258d940d 2757 } MAILBOX_Type;
Kojto 148:fd96258d940d 2758
Kojto 148:fd96258d940d 2759 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 2760 -- MAILBOX Register Masks
Kojto 148:fd96258d940d 2761 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 2762
Kojto 148:fd96258d940d 2763 /*!
Kojto 148:fd96258d940d 2764 * @addtogroup MAILBOX_Register_Masks MAILBOX Register Masks
Kojto 148:fd96258d940d 2765 * @{
Kojto 148:fd96258d940d 2766 */
Kojto 148:fd96258d940d 2767
Kojto 148:fd96258d940d 2768 /*! @name MBOXIRQ_IRQ - Interrupt request register for the Cortex-M0+ CPU. */
Kojto 148:fd96258d940d 2769 #define MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 2770 #define MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT (0U)
Kojto 148:fd96258d940d 2771 #define MAILBOX_MBOXIRQ_IRQ_INTREQ(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT)) & MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK)
Kojto 148:fd96258d940d 2772
Kojto 148:fd96258d940d 2773 /* The count of MAILBOX_MBOXIRQ_IRQ */
Kojto 148:fd96258d940d 2774 #define MAILBOX_MBOXIRQ_IRQ_COUNT (2U)
Kojto 148:fd96258d940d 2775
Kojto 148:fd96258d940d 2776 /*! @name MBOXIRQ_IRQSET - Set bits in IRQ0 */
Kojto 148:fd96258d940d 2777 #define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 2778 #define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT (0U)
Kojto 148:fd96258d940d 2779 #define MAILBOX_MBOXIRQ_IRQSET_INTREQSET(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT)) & MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK)
Kojto 148:fd96258d940d 2780
Kojto 148:fd96258d940d 2781 /* The count of MAILBOX_MBOXIRQ_IRQSET */
Kojto 148:fd96258d940d 2782 #define MAILBOX_MBOXIRQ_IRQSET_COUNT (2U)
Kojto 148:fd96258d940d 2783
Kojto 148:fd96258d940d 2784 /*! @name MBOXIRQ_IRQCLR - Clear bits in IRQ0 */
Kojto 148:fd96258d940d 2785 #define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 2786 #define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT (0U)
Kojto 148:fd96258d940d 2787 #define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT)) & MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK)
Kojto 148:fd96258d940d 2788
Kojto 148:fd96258d940d 2789 /* The count of MAILBOX_MBOXIRQ_IRQCLR */
Kojto 148:fd96258d940d 2790 #define MAILBOX_MBOXIRQ_IRQCLR_COUNT (2U)
Kojto 148:fd96258d940d 2791
Kojto 148:fd96258d940d 2792 /*! @name MUTEX - Mutual exclusion register[1] */
Kojto 148:fd96258d940d 2793 #define MAILBOX_MUTEX_EX_MASK (0x1U)
Kojto 148:fd96258d940d 2794 #define MAILBOX_MUTEX_EX_SHIFT (0U)
Kojto 148:fd96258d940d 2795 #define MAILBOX_MUTEX_EX(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MUTEX_EX_SHIFT)) & MAILBOX_MUTEX_EX_MASK)
Kojto 148:fd96258d940d 2796
Kojto 148:fd96258d940d 2797
Kojto 148:fd96258d940d 2798 /*!
Kojto 148:fd96258d940d 2799 * @}
Kojto 148:fd96258d940d 2800 */ /* end of group MAILBOX_Register_Masks */
Kojto 148:fd96258d940d 2801
Kojto 148:fd96258d940d 2802
Kojto 148:fd96258d940d 2803 /* MAILBOX - Peripheral instance base addresses */
Kojto 148:fd96258d940d 2804 /** Peripheral MAILBOX base address */
Kojto 148:fd96258d940d 2805 #define MAILBOX_BASE (0x4008B000u)
Kojto 148:fd96258d940d 2806 /** Peripheral MAILBOX base pointer */
Kojto 148:fd96258d940d 2807 #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE)
Kojto 148:fd96258d940d 2808 /** Array initializer of MAILBOX peripheral base addresses */
Kojto 148:fd96258d940d 2809 #define MAILBOX_BASE_ADDRS { MAILBOX_BASE }
Kojto 148:fd96258d940d 2810 /** Array initializer of MAILBOX peripheral base pointers */
Kojto 148:fd96258d940d 2811 #define MAILBOX_BASE_PTRS { MAILBOX }
Kojto 148:fd96258d940d 2812 /** Interrupt vectors for the MAILBOX peripheral type */
Kojto 148:fd96258d940d 2813 #define MAILBOX_IRQS { MAILBOX_IRQn }
Kojto 148:fd96258d940d 2814
Kojto 148:fd96258d940d 2815 /*!
Kojto 148:fd96258d940d 2816 * @}
Kojto 148:fd96258d940d 2817 */ /* end of group MAILBOX_Peripheral_Access_Layer */
Kojto 148:fd96258d940d 2818
Kojto 148:fd96258d940d 2819
Kojto 148:fd96258d940d 2820 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 2821 -- MRT Peripheral Access Layer
Kojto 148:fd96258d940d 2822 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 2823
Kojto 148:fd96258d940d 2824 /*!
Kojto 148:fd96258d940d 2825 * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer
Kojto 148:fd96258d940d 2826 * @{
Kojto 148:fd96258d940d 2827 */
Kojto 148:fd96258d940d 2828
Kojto 148:fd96258d940d 2829 /** MRT - Register Layout Typedef */
Kojto 148:fd96258d940d 2830 typedef struct {
Kojto 148:fd96258d940d 2831 struct { /* offset: 0x0, array step: 0x10 */
Kojto 148:fd96258d940d 2832 __IO uint32_t INTVAL; /**< MRT Time interval value register. This value is loaded into the TIMER register., array offset: 0x0, array step: 0x10 */
Kojto 148:fd96258d940d 2833 __I uint32_t TIMER; /**< MRT Timer register. This register reads the value of the down-counter., array offset: 0x4, array step: 0x10 */
Kojto 148:fd96258d940d 2834 __IO uint32_t CTRL; /**< MRT Control register. This register controls the MRT modes., array offset: 0x8, array step: 0x10 */
Kojto 148:fd96258d940d 2835 __IO uint32_t STAT; /**< MRT Status register., array offset: 0xC, array step: 0x10 */
Kojto 148:fd96258d940d 2836 } CHANNEL[4];
Kojto 148:fd96258d940d 2837 uint8_t RESERVED_0[176];
Kojto 148:fd96258d940d 2838 __IO uint32_t MODCFG; /**< Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature., offset: 0xF0 */
Kojto 148:fd96258d940d 2839 __I uint32_t IDLE_CH; /**< Idle channel register. This register returns the number of the first idle channel., offset: 0xF4 */
Kojto 148:fd96258d940d 2840 __IO uint32_t IRQ_FLAG; /**< Global interrupt flag register, offset: 0xF8 */
Kojto 148:fd96258d940d 2841 } MRT_Type;
Kojto 148:fd96258d940d 2842
Kojto 148:fd96258d940d 2843 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 2844 -- MRT Register Masks
Kojto 148:fd96258d940d 2845 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 2846
Kojto 148:fd96258d940d 2847 /*!
Kojto 148:fd96258d940d 2848 * @addtogroup MRT_Register_Masks MRT Register Masks
Kojto 148:fd96258d940d 2849 * @{
Kojto 148:fd96258d940d 2850 */
Kojto 148:fd96258d940d 2851
Kojto 148:fd96258d940d 2852 /*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */
Kojto 148:fd96258d940d 2853 #define MRT_CHANNEL_INTVAL_IVALUE_MASK (0xFFFFFFU)
Kojto 148:fd96258d940d 2854 #define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U)
Kojto 148:fd96258d940d 2855 #define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK)
Kojto 148:fd96258d940d 2856 #define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U)
Kojto 148:fd96258d940d 2857 #define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U)
Kojto 148:fd96258d940d 2858 #define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK)
Kojto 148:fd96258d940d 2859
Kojto 148:fd96258d940d 2860 /* The count of MRT_CHANNEL_INTVAL */
Kojto 148:fd96258d940d 2861 #define MRT_CHANNEL_INTVAL_COUNT (4U)
Kojto 148:fd96258d940d 2862
Kojto 148:fd96258d940d 2863 /*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */
Kojto 148:fd96258d940d 2864 #define MRT_CHANNEL_TIMER_VALUE_MASK (0xFFFFFFU)
Kojto 148:fd96258d940d 2865 #define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U)
Kojto 148:fd96258d940d 2866 #define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK)
Kojto 148:fd96258d940d 2867
Kojto 148:fd96258d940d 2868 /* The count of MRT_CHANNEL_TIMER */
Kojto 148:fd96258d940d 2869 #define MRT_CHANNEL_TIMER_COUNT (4U)
Kojto 148:fd96258d940d 2870
Kojto 148:fd96258d940d 2871 /*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */
Kojto 148:fd96258d940d 2872 #define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U)
Kojto 148:fd96258d940d 2873 #define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U)
Kojto 148:fd96258d940d 2874 #define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK)
Kojto 148:fd96258d940d 2875 #define MRT_CHANNEL_CTRL_MODE_MASK (0x6U)
Kojto 148:fd96258d940d 2876 #define MRT_CHANNEL_CTRL_MODE_SHIFT (1U)
Kojto 148:fd96258d940d 2877 #define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK)
Kojto 148:fd96258d940d 2878
Kojto 148:fd96258d940d 2879 /* The count of MRT_CHANNEL_CTRL */
Kojto 148:fd96258d940d 2880 #define MRT_CHANNEL_CTRL_COUNT (4U)
Kojto 148:fd96258d940d 2881
Kojto 148:fd96258d940d 2882 /*! @name CHANNEL_STAT - MRT Status register. */
Kojto 148:fd96258d940d 2883 #define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U)
Kojto 148:fd96258d940d 2884 #define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U)
Kojto 148:fd96258d940d 2885 #define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK)
Kojto 148:fd96258d940d 2886 #define MRT_CHANNEL_STAT_RUN_MASK (0x2U)
Kojto 148:fd96258d940d 2887 #define MRT_CHANNEL_STAT_RUN_SHIFT (1U)
Kojto 148:fd96258d940d 2888 #define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK)
Kojto 148:fd96258d940d 2889 #define MRT_CHANNEL_STAT_INUSE_MASK (0x4U)
Kojto 148:fd96258d940d 2890 #define MRT_CHANNEL_STAT_INUSE_SHIFT (2U)
Kojto 148:fd96258d940d 2891 #define MRT_CHANNEL_STAT_INUSE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK)
Kojto 148:fd96258d940d 2892
Kojto 148:fd96258d940d 2893 /* The count of MRT_CHANNEL_STAT */
Kojto 148:fd96258d940d 2894 #define MRT_CHANNEL_STAT_COUNT (4U)
Kojto 148:fd96258d940d 2895
Kojto 148:fd96258d940d 2896 /*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. */
Kojto 148:fd96258d940d 2897 #define MRT_MODCFG_NOC_MASK (0xFU)
Kojto 148:fd96258d940d 2898 #define MRT_MODCFG_NOC_SHIFT (0U)
Kojto 148:fd96258d940d 2899 #define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK)
Kojto 148:fd96258d940d 2900 #define MRT_MODCFG_NOB_MASK (0x1F0U)
Kojto 148:fd96258d940d 2901 #define MRT_MODCFG_NOB_SHIFT (4U)
Kojto 148:fd96258d940d 2902 #define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK)
Kojto 148:fd96258d940d 2903 #define MRT_MODCFG_MULTITASK_MASK (0x80000000U)
Kojto 148:fd96258d940d 2904 #define MRT_MODCFG_MULTITASK_SHIFT (31U)
Kojto 148:fd96258d940d 2905 #define MRT_MODCFG_MULTITASK(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK)
Kojto 148:fd96258d940d 2906
Kojto 148:fd96258d940d 2907 /*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */
Kojto 148:fd96258d940d 2908 #define MRT_IDLE_CH_CHAN_MASK (0xF0U)
Kojto 148:fd96258d940d 2909 #define MRT_IDLE_CH_CHAN_SHIFT (4U)
Kojto 148:fd96258d940d 2910 #define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK)
Kojto 148:fd96258d940d 2911
Kojto 148:fd96258d940d 2912 /*! @name IRQ_FLAG - Global interrupt flag register */
Kojto 148:fd96258d940d 2913 #define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U)
Kojto 148:fd96258d940d 2914 #define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U)
Kojto 148:fd96258d940d 2915 #define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK)
Kojto 148:fd96258d940d 2916 #define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U)
Kojto 148:fd96258d940d 2917 #define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U)
Kojto 148:fd96258d940d 2918 #define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK)
Kojto 148:fd96258d940d 2919 #define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U)
Kojto 148:fd96258d940d 2920 #define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U)
Kojto 148:fd96258d940d 2921 #define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK)
Kojto 148:fd96258d940d 2922 #define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U)
Kojto 148:fd96258d940d 2923 #define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U)
Kojto 148:fd96258d940d 2924 #define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK)
Kojto 148:fd96258d940d 2925
Kojto 148:fd96258d940d 2926
Kojto 148:fd96258d940d 2927 /*!
Kojto 148:fd96258d940d 2928 * @}
Kojto 148:fd96258d940d 2929 */ /* end of group MRT_Register_Masks */
Kojto 148:fd96258d940d 2930
Kojto 148:fd96258d940d 2931
Kojto 148:fd96258d940d 2932 /* MRT - Peripheral instance base addresses */
Kojto 148:fd96258d940d 2933 /** Peripheral MRT0 base address */
Kojto 148:fd96258d940d 2934 #define MRT0_BASE (0x4000D000u)
Kojto 148:fd96258d940d 2935 /** Peripheral MRT0 base pointer */
Kojto 148:fd96258d940d 2936 #define MRT0 ((MRT_Type *)MRT0_BASE)
Kojto 148:fd96258d940d 2937 /** Array initializer of MRT peripheral base addresses */
Kojto 148:fd96258d940d 2938 #define MRT_BASE_ADDRS { MRT0_BASE }
Kojto 148:fd96258d940d 2939 /** Array initializer of MRT peripheral base pointers */
Kojto 148:fd96258d940d 2940 #define MRT_BASE_PTRS { MRT0 }
Kojto 148:fd96258d940d 2941 /** Interrupt vectors for the MRT peripheral type */
Kojto 148:fd96258d940d 2942 #define MRT_IRQS { MRT0_IRQn }
Kojto 148:fd96258d940d 2943
Kojto 148:fd96258d940d 2944 /*!
Kojto 148:fd96258d940d 2945 * @}
Kojto 148:fd96258d940d 2946 */ /* end of group MRT_Peripheral_Access_Layer */
Kojto 148:fd96258d940d 2947
Kojto 148:fd96258d940d 2948
Kojto 148:fd96258d940d 2949 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 2950 -- PINT Peripheral Access Layer
Kojto 148:fd96258d940d 2951 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 2952
Kojto 148:fd96258d940d 2953 /*!
Kojto 148:fd96258d940d 2954 * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer
Kojto 148:fd96258d940d 2955 * @{
Kojto 148:fd96258d940d 2956 */
Kojto 148:fd96258d940d 2957
Kojto 148:fd96258d940d 2958 /** PINT - Register Layout Typedef */
Kojto 148:fd96258d940d 2959 typedef struct {
Kojto 148:fd96258d940d 2960 __IO uint32_t ISEL; /**< Pin Interrupt Mode register, offset: 0x0 */
Kojto 148:fd96258d940d 2961 __IO uint32_t IENR; /**< Pin interrupt level or rising edge interrupt enable register, offset: 0x4 */
Kojto 148:fd96258d940d 2962 __O uint32_t SIENR; /**< Pin interrupt level or rising edge interrupt set register, offset: 0x8 */
Kojto 148:fd96258d940d 2963 __O uint32_t CIENR; /**< Pin interrupt level (rising edge interrupt) clear register, offset: 0xC */
Kojto 148:fd96258d940d 2964 __IO uint32_t IENF; /**< Pin interrupt active level or falling edge interrupt enable register, offset: 0x10 */
Kojto 148:fd96258d940d 2965 __O uint32_t SIENF; /**< Pin interrupt active level or falling edge interrupt set register, offset: 0x14 */
Kojto 148:fd96258d940d 2966 __O uint32_t CIENF; /**< Pin interrupt active level or falling edge interrupt clear register, offset: 0x18 */
Kojto 148:fd96258d940d 2967 __IO uint32_t RISE; /**< Pin interrupt rising edge register, offset: 0x1C */
Kojto 148:fd96258d940d 2968 __IO uint32_t FALL; /**< Pin interrupt falling edge register, offset: 0x20 */
Kojto 148:fd96258d940d 2969 __IO uint32_t IST; /**< Pin interrupt status register, offset: 0x24 */
Kojto 148:fd96258d940d 2970 __IO uint32_t PMCTRL; /**< Pattern match interrupt control register, offset: 0x28 */
Kojto 148:fd96258d940d 2971 __IO uint32_t PMSRC; /**< Pattern match interrupt bit-slice source register, offset: 0x2C */
Kojto 148:fd96258d940d 2972 __IO uint32_t PMCFG; /**< Pattern match interrupt bit slice configuration register, offset: 0x30 */
Kojto 148:fd96258d940d 2973 } PINT_Type;
Kojto 148:fd96258d940d 2974
Kojto 148:fd96258d940d 2975 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 2976 -- PINT Register Masks
Kojto 148:fd96258d940d 2977 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 2978
Kojto 148:fd96258d940d 2979 /*!
Kojto 148:fd96258d940d 2980 * @addtogroup PINT_Register_Masks PINT Register Masks
Kojto 148:fd96258d940d 2981 * @{
Kojto 148:fd96258d940d 2982 */
Kojto 148:fd96258d940d 2983
Kojto 148:fd96258d940d 2984 /*! @name ISEL - Pin Interrupt Mode register */
Kojto 148:fd96258d940d 2985 #define PINT_ISEL_PMODE_MASK (0xFFU)
Kojto 148:fd96258d940d 2986 #define PINT_ISEL_PMODE_SHIFT (0U)
Kojto 148:fd96258d940d 2987 #define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK)
Kojto 148:fd96258d940d 2988
Kojto 148:fd96258d940d 2989 /*! @name IENR - Pin interrupt level or rising edge interrupt enable register */
Kojto 148:fd96258d940d 2990 #define PINT_IENR_ENRL_MASK (0xFFU)
Kojto 148:fd96258d940d 2991 #define PINT_IENR_ENRL_SHIFT (0U)
Kojto 148:fd96258d940d 2992 #define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK)
Kojto 148:fd96258d940d 2993
Kojto 148:fd96258d940d 2994 /*! @name SIENR - Pin interrupt level or rising edge interrupt set register */
Kojto 148:fd96258d940d 2995 #define PINT_SIENR_SETENRL_MASK (0xFFU)
Kojto 148:fd96258d940d 2996 #define PINT_SIENR_SETENRL_SHIFT (0U)
Kojto 148:fd96258d940d 2997 #define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK)
Kojto 148:fd96258d940d 2998
Kojto 148:fd96258d940d 2999 /*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */
Kojto 148:fd96258d940d 3000 #define PINT_CIENR_CENRL_MASK (0xFFU)
Kojto 148:fd96258d940d 3001 #define PINT_CIENR_CENRL_SHIFT (0U)
Kojto 148:fd96258d940d 3002 #define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK)
Kojto 148:fd96258d940d 3003
Kojto 148:fd96258d940d 3004 /*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */
Kojto 148:fd96258d940d 3005 #define PINT_IENF_ENAF_MASK (0xFFU)
Kojto 148:fd96258d940d 3006 #define PINT_IENF_ENAF_SHIFT (0U)
Kojto 148:fd96258d940d 3007 #define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK)
Kojto 148:fd96258d940d 3008
Kojto 148:fd96258d940d 3009 /*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */
Kojto 148:fd96258d940d 3010 #define PINT_SIENF_SETENAF_MASK (0xFFU)
Kojto 148:fd96258d940d 3011 #define PINT_SIENF_SETENAF_SHIFT (0U)
Kojto 148:fd96258d940d 3012 #define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK)
Kojto 148:fd96258d940d 3013
Kojto 148:fd96258d940d 3014 /*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */
Kojto 148:fd96258d940d 3015 #define PINT_CIENF_CENAF_MASK (0xFFU)
Kojto 148:fd96258d940d 3016 #define PINT_CIENF_CENAF_SHIFT (0U)
Kojto 148:fd96258d940d 3017 #define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK)
Kojto 148:fd96258d940d 3018
Kojto 148:fd96258d940d 3019 /*! @name RISE - Pin interrupt rising edge register */
Kojto 148:fd96258d940d 3020 #define PINT_RISE_RDET_MASK (0xFFU)
Kojto 148:fd96258d940d 3021 #define PINT_RISE_RDET_SHIFT (0U)
Kojto 148:fd96258d940d 3022 #define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK)
Kojto 148:fd96258d940d 3023
Kojto 148:fd96258d940d 3024 /*! @name FALL - Pin interrupt falling edge register */
Kojto 148:fd96258d940d 3025 #define PINT_FALL_FDET_MASK (0xFFU)
Kojto 148:fd96258d940d 3026 #define PINT_FALL_FDET_SHIFT (0U)
Kojto 148:fd96258d940d 3027 #define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK)
Kojto 148:fd96258d940d 3028
Kojto 148:fd96258d940d 3029 /*! @name IST - Pin interrupt status register */
Kojto 148:fd96258d940d 3030 #define PINT_IST_PSTAT_MASK (0xFFU)
Kojto 148:fd96258d940d 3031 #define PINT_IST_PSTAT_SHIFT (0U)
Kojto 148:fd96258d940d 3032 #define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK)
Kojto 148:fd96258d940d 3033
Kojto 148:fd96258d940d 3034 /*! @name PMCTRL - Pattern match interrupt control register */
Kojto 148:fd96258d940d 3035 #define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U)
Kojto 148:fd96258d940d 3036 #define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U)
Kojto 148:fd96258d940d 3037 #define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK)
Kojto 148:fd96258d940d 3038 #define PINT_PMCTRL_ENA_RXEV_MASK (0x2U)
Kojto 148:fd96258d940d 3039 #define PINT_PMCTRL_ENA_RXEV_SHIFT (1U)
Kojto 148:fd96258d940d 3040 #define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK)
Kojto 148:fd96258d940d 3041 #define PINT_PMCTRL_PMAT_MASK (0xFF000000U)
Kojto 148:fd96258d940d 3042 #define PINT_PMCTRL_PMAT_SHIFT (24U)
Kojto 148:fd96258d940d 3043 #define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK)
Kojto 148:fd96258d940d 3044
Kojto 148:fd96258d940d 3045 /*! @name PMSRC - Pattern match interrupt bit-slice source register */
Kojto 148:fd96258d940d 3046 #define PINT_PMSRC_SRC0_MASK (0x700U)
Kojto 148:fd96258d940d 3047 #define PINT_PMSRC_SRC0_SHIFT (8U)
Kojto 148:fd96258d940d 3048 #define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK)
Kojto 148:fd96258d940d 3049 #define PINT_PMSRC_SRC1_MASK (0x3800U)
Kojto 148:fd96258d940d 3050 #define PINT_PMSRC_SRC1_SHIFT (11U)
Kojto 148:fd96258d940d 3051 #define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK)
Kojto 148:fd96258d940d 3052 #define PINT_PMSRC_SRC2_MASK (0x1C000U)
Kojto 148:fd96258d940d 3053 #define PINT_PMSRC_SRC2_SHIFT (14U)
Kojto 148:fd96258d940d 3054 #define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK)
Kojto 148:fd96258d940d 3055 #define PINT_PMSRC_SRC3_MASK (0xE0000U)
Kojto 148:fd96258d940d 3056 #define PINT_PMSRC_SRC3_SHIFT (17U)
Kojto 148:fd96258d940d 3057 #define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK)
Kojto 148:fd96258d940d 3058 #define PINT_PMSRC_SRC4_MASK (0x700000U)
Kojto 148:fd96258d940d 3059 #define PINT_PMSRC_SRC4_SHIFT (20U)
Kojto 148:fd96258d940d 3060 #define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK)
Kojto 148:fd96258d940d 3061 #define PINT_PMSRC_SRC5_MASK (0x3800000U)
Kojto 148:fd96258d940d 3062 #define PINT_PMSRC_SRC5_SHIFT (23U)
Kojto 148:fd96258d940d 3063 #define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK)
Kojto 148:fd96258d940d 3064 #define PINT_PMSRC_SRC6_MASK (0x1C000000U)
Kojto 148:fd96258d940d 3065 #define PINT_PMSRC_SRC6_SHIFT (26U)
Kojto 148:fd96258d940d 3066 #define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK)
Kojto 148:fd96258d940d 3067 #define PINT_PMSRC_SRC7_MASK (0xE0000000U)
Kojto 148:fd96258d940d 3068 #define PINT_PMSRC_SRC7_SHIFT (29U)
Kojto 148:fd96258d940d 3069 #define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK)
Kojto 148:fd96258d940d 3070
Kojto 148:fd96258d940d 3071 /*! @name PMCFG - Pattern match interrupt bit slice configuration register */
Kojto 148:fd96258d940d 3072 #define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U)
Kojto 148:fd96258d940d 3073 #define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U)
Kojto 148:fd96258d940d 3074 #define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK)
Kojto 148:fd96258d940d 3075 #define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U)
Kojto 148:fd96258d940d 3076 #define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U)
Kojto 148:fd96258d940d 3077 #define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK)
Kojto 148:fd96258d940d 3078 #define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U)
Kojto 148:fd96258d940d 3079 #define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U)
Kojto 148:fd96258d940d 3080 #define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK)
Kojto 148:fd96258d940d 3081 #define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U)
Kojto 148:fd96258d940d 3082 #define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U)
Kojto 148:fd96258d940d 3083 #define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK)
Kojto 148:fd96258d940d 3084 #define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U)
Kojto 148:fd96258d940d 3085 #define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U)
Kojto 148:fd96258d940d 3086 #define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK)
Kojto 148:fd96258d940d 3087 #define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U)
Kojto 148:fd96258d940d 3088 #define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U)
Kojto 148:fd96258d940d 3089 #define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK)
Kojto 148:fd96258d940d 3090 #define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U)
Kojto 148:fd96258d940d 3091 #define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U)
Kojto 148:fd96258d940d 3092 #define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK)
Kojto 148:fd96258d940d 3093 #define PINT_PMCFG_CFG0_MASK (0x700U)
Kojto 148:fd96258d940d 3094 #define PINT_PMCFG_CFG0_SHIFT (8U)
Kojto 148:fd96258d940d 3095 #define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK)
Kojto 148:fd96258d940d 3096 #define PINT_PMCFG_CFG1_MASK (0x3800U)
Kojto 148:fd96258d940d 3097 #define PINT_PMCFG_CFG1_SHIFT (11U)
Kojto 148:fd96258d940d 3098 #define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK)
Kojto 148:fd96258d940d 3099 #define PINT_PMCFG_CFG2_MASK (0x1C000U)
Kojto 148:fd96258d940d 3100 #define PINT_PMCFG_CFG2_SHIFT (14U)
Kojto 148:fd96258d940d 3101 #define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK)
Kojto 148:fd96258d940d 3102 #define PINT_PMCFG_CFG3_MASK (0xE0000U)
Kojto 148:fd96258d940d 3103 #define PINT_PMCFG_CFG3_SHIFT (17U)
Kojto 148:fd96258d940d 3104 #define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK)
Kojto 148:fd96258d940d 3105 #define PINT_PMCFG_CFG4_MASK (0x700000U)
Kojto 148:fd96258d940d 3106 #define PINT_PMCFG_CFG4_SHIFT (20U)
Kojto 148:fd96258d940d 3107 #define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK)
Kojto 148:fd96258d940d 3108 #define PINT_PMCFG_CFG5_MASK (0x3800000U)
Kojto 148:fd96258d940d 3109 #define PINT_PMCFG_CFG5_SHIFT (23U)
Kojto 148:fd96258d940d 3110 #define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK)
Kojto 148:fd96258d940d 3111 #define PINT_PMCFG_CFG6_MASK (0x1C000000U)
Kojto 148:fd96258d940d 3112 #define PINT_PMCFG_CFG6_SHIFT (26U)
Kojto 148:fd96258d940d 3113 #define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK)
Kojto 148:fd96258d940d 3114 #define PINT_PMCFG_CFG7_MASK (0xE0000000U)
Kojto 148:fd96258d940d 3115 #define PINT_PMCFG_CFG7_SHIFT (29U)
Kojto 148:fd96258d940d 3116 #define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK)
Kojto 148:fd96258d940d 3117
Kojto 148:fd96258d940d 3118
Kojto 148:fd96258d940d 3119 /*!
Kojto 148:fd96258d940d 3120 * @}
Kojto 148:fd96258d940d 3121 */ /* end of group PINT_Register_Masks */
Kojto 148:fd96258d940d 3122
Kojto 148:fd96258d940d 3123
Kojto 148:fd96258d940d 3124 /* PINT - Peripheral instance base addresses */
Kojto 148:fd96258d940d 3125 /** Peripheral PINT base address */
Kojto 148:fd96258d940d 3126 #define PINT_BASE (0x40004000u)
Kojto 148:fd96258d940d 3127 /** Peripheral PINT base pointer */
Kojto 148:fd96258d940d 3128 #define PINT ((PINT_Type *)PINT_BASE)
Kojto 148:fd96258d940d 3129 /** Array initializer of PINT peripheral base addresses */
Kojto 148:fd96258d940d 3130 #define PINT_BASE_ADDRS { PINT_BASE }
Kojto 148:fd96258d940d 3131 /** Array initializer of PINT peripheral base pointers */
Kojto 148:fd96258d940d 3132 #define PINT_BASE_PTRS { PINT }
Kojto 148:fd96258d940d 3133 /** Interrupt vectors for the PINT peripheral type */
Kojto 148:fd96258d940d 3134 #define PINT_IRQS { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn }
Kojto 148:fd96258d940d 3135
Kojto 148:fd96258d940d 3136 /*!
Kojto 148:fd96258d940d 3137 * @}
Kojto 148:fd96258d940d 3138 */ /* end of group PINT_Peripheral_Access_Layer */
Kojto 148:fd96258d940d 3139
Kojto 148:fd96258d940d 3140
Kojto 148:fd96258d940d 3141 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 3142 -- RTC Peripheral Access Layer
Kojto 148:fd96258d940d 3143 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 3144
Kojto 148:fd96258d940d 3145 /*!
Kojto 148:fd96258d940d 3146 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
Kojto 148:fd96258d940d 3147 * @{
Kojto 148:fd96258d940d 3148 */
Kojto 148:fd96258d940d 3149
Kojto 148:fd96258d940d 3150 /** RTC - Register Layout Typedef */
Kojto 148:fd96258d940d 3151 typedef struct {
Kojto 148:fd96258d940d 3152 __IO uint32_t CTRL; /**< RTC control register, offset: 0x0 */
Kojto 148:fd96258d940d 3153 __IO uint32_t MATCH; /**< RTC match register, offset: 0x4 */
Kojto 148:fd96258d940d 3154 __IO uint32_t COUNT; /**< RTC counter register, offset: 0x8 */
Kojto 148:fd96258d940d 3155 __IO uint32_t WAKE; /**< High-resolution/wake-up timer control register, offset: 0xC */
Kojto 148:fd96258d940d 3156 } RTC_Type;
Kojto 148:fd96258d940d 3157
Kojto 148:fd96258d940d 3158 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 3159 -- RTC Register Masks
Kojto 148:fd96258d940d 3160 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 3161
Kojto 148:fd96258d940d 3162 /*!
Kojto 148:fd96258d940d 3163 * @addtogroup RTC_Register_Masks RTC Register Masks
Kojto 148:fd96258d940d 3164 * @{
Kojto 148:fd96258d940d 3165 */
Kojto 148:fd96258d940d 3166
Kojto 148:fd96258d940d 3167 /*! @name CTRL - RTC control register */
Kojto 148:fd96258d940d 3168 #define RTC_CTRL_SWRESET_MASK (0x1U)
Kojto 148:fd96258d940d 3169 #define RTC_CTRL_SWRESET_SHIFT (0U)
Kojto 148:fd96258d940d 3170 #define RTC_CTRL_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK)
Kojto 148:fd96258d940d 3171 #define RTC_CTRL_ALARM1HZ_MASK (0x4U)
Kojto 148:fd96258d940d 3172 #define RTC_CTRL_ALARM1HZ_SHIFT (2U)
Kojto 148:fd96258d940d 3173 #define RTC_CTRL_ALARM1HZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARM1HZ_SHIFT)) & RTC_CTRL_ALARM1HZ_MASK)
Kojto 148:fd96258d940d 3174 #define RTC_CTRL_WAKE1KHZ_MASK (0x8U)
Kojto 148:fd96258d940d 3175 #define RTC_CTRL_WAKE1KHZ_SHIFT (3U)
Kojto 148:fd96258d940d 3176 #define RTC_CTRL_WAKE1KHZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKE1KHZ_SHIFT)) & RTC_CTRL_WAKE1KHZ_MASK)
Kojto 148:fd96258d940d 3177 #define RTC_CTRL_ALARMDPD_EN_MASK (0x10U)
Kojto 148:fd96258d940d 3178 #define RTC_CTRL_ALARMDPD_EN_SHIFT (4U)
Kojto 148:fd96258d940d 3179 #define RTC_CTRL_ALARMDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARMDPD_EN_SHIFT)) & RTC_CTRL_ALARMDPD_EN_MASK)
Kojto 148:fd96258d940d 3180 #define RTC_CTRL_WAKEDPD_EN_MASK (0x20U)
Kojto 148:fd96258d940d 3181 #define RTC_CTRL_WAKEDPD_EN_SHIFT (5U)
Kojto 148:fd96258d940d 3182 #define RTC_CTRL_WAKEDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKEDPD_EN_SHIFT)) & RTC_CTRL_WAKEDPD_EN_MASK)
Kojto 148:fd96258d940d 3183 #define RTC_CTRL_RTC1KHZ_EN_MASK (0x40U)
Kojto 148:fd96258d940d 3184 #define RTC_CTRL_RTC1KHZ_EN_SHIFT (6U)
Kojto 148:fd96258d940d 3185 #define RTC_CTRL_RTC1KHZ_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC1KHZ_EN_SHIFT)) & RTC_CTRL_RTC1KHZ_EN_MASK)
Kojto 148:fd96258d940d 3186 #define RTC_CTRL_RTC_EN_MASK (0x80U)
Kojto 148:fd96258d940d 3187 #define RTC_CTRL_RTC_EN_SHIFT (7U)
Kojto 148:fd96258d940d 3188 #define RTC_CTRL_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_EN_SHIFT)) & RTC_CTRL_RTC_EN_MASK)
Kojto 148:fd96258d940d 3189 #define RTC_CTRL_RTC_OSC_PD_MASK (0x100U)
Kojto 148:fd96258d940d 3190 #define RTC_CTRL_RTC_OSC_PD_SHIFT (8U)
Kojto 148:fd96258d940d 3191 #define RTC_CTRL_RTC_OSC_PD(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_PD_SHIFT)) & RTC_CTRL_RTC_OSC_PD_MASK)
Kojto 148:fd96258d940d 3192 #define RTC_CTRL_RTC_OSC_BYPASS_MASK (0x200U)
Kojto 148:fd96258d940d 3193 #define RTC_CTRL_RTC_OSC_BYPASS_SHIFT (9U)
Kojto 148:fd96258d940d 3194 #define RTC_CTRL_RTC_OSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_BYPASS_SHIFT)) & RTC_CTRL_RTC_OSC_BYPASS_MASK)
Kojto 148:fd96258d940d 3195
Kojto 148:fd96258d940d 3196 /*! @name MATCH - RTC match register */
Kojto 148:fd96258d940d 3197 #define RTC_MATCH_MATVAL_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 3198 #define RTC_MATCH_MATVAL_SHIFT (0U)
Kojto 148:fd96258d940d 3199 #define RTC_MATCH_MATVAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK)
Kojto 148:fd96258d940d 3200
Kojto 148:fd96258d940d 3201 /*! @name COUNT - RTC counter register */
Kojto 148:fd96258d940d 3202 #define RTC_COUNT_VAL_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 3203 #define RTC_COUNT_VAL_SHIFT (0U)
Kojto 148:fd96258d940d 3204 #define RTC_COUNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK)
Kojto 148:fd96258d940d 3205
Kojto 148:fd96258d940d 3206 /*! @name WAKE - High-resolution/wake-up timer control register */
Kojto 148:fd96258d940d 3207 #define RTC_WAKE_VAL_MASK (0xFFFFU)
Kojto 148:fd96258d940d 3208 #define RTC_WAKE_VAL_SHIFT (0U)
Kojto 148:fd96258d940d 3209 #define RTC_WAKE_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK)
Kojto 148:fd96258d940d 3210
Kojto 148:fd96258d940d 3211
Kojto 148:fd96258d940d 3212 /*!
Kojto 148:fd96258d940d 3213 * @}
Kojto 148:fd96258d940d 3214 */ /* end of group RTC_Register_Masks */
Kojto 148:fd96258d940d 3215
Kojto 148:fd96258d940d 3216
Kojto 148:fd96258d940d 3217 /* RTC - Peripheral instance base addresses */
Kojto 148:fd96258d940d 3218 /** Peripheral RTC base address */
Kojto 148:fd96258d940d 3219 #define RTC_BASE (0x4002C000u)
Kojto 148:fd96258d940d 3220 /** Peripheral RTC base pointer */
Kojto 148:fd96258d940d 3221 #define RTC ((RTC_Type *)RTC_BASE)
Kojto 148:fd96258d940d 3222 /** Array initializer of RTC peripheral base addresses */
Kojto 148:fd96258d940d 3223 #define RTC_BASE_ADDRS { RTC_BASE }
Kojto 148:fd96258d940d 3224 /** Array initializer of RTC peripheral base pointers */
Kojto 148:fd96258d940d 3225 #define RTC_BASE_PTRS { RTC }
Kojto 148:fd96258d940d 3226 /** Interrupt vectors for the RTC peripheral type */
Kojto 148:fd96258d940d 3227 #define RTC_IRQS { RTC_IRQn }
Kojto 148:fd96258d940d 3228
Kojto 148:fd96258d940d 3229 /*!
Kojto 148:fd96258d940d 3230 * @}
Kojto 148:fd96258d940d 3231 */ /* end of group RTC_Peripheral_Access_Layer */
Kojto 148:fd96258d940d 3232
Kojto 148:fd96258d940d 3233
Kojto 148:fd96258d940d 3234 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 3235 -- SCT Peripheral Access Layer
Kojto 148:fd96258d940d 3236 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 3237
Kojto 148:fd96258d940d 3238 /*!
Kojto 148:fd96258d940d 3239 * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer
Kojto 148:fd96258d940d 3240 * @{
Kojto 148:fd96258d940d 3241 */
Kojto 148:fd96258d940d 3242
Kojto 148:fd96258d940d 3243 /** SCT - Register Layout Typedef */
Kojto 148:fd96258d940d 3244 typedef struct {
Kojto 148:fd96258d940d 3245 __IO uint32_t CONFIG; /**< SCT configuration register, offset: 0x0 */
Kojto 148:fd96258d940d 3246 __IO uint32_t CTRL; /**< SCT control register, offset: 0x4 */
Kojto 148:fd96258d940d 3247 __IO uint32_t LIMIT; /**< SCT limit event select register, offset: 0x8 */
Kojto 148:fd96258d940d 3248 __IO uint32_t HALT; /**< SCT halt event select register, offset: 0xC */
Kojto 148:fd96258d940d 3249 __IO uint32_t STOP; /**< SCT stop event select register, offset: 0x10 */
Kojto 148:fd96258d940d 3250 __IO uint32_t START; /**< SCT start event select register, offset: 0x14 */
Kojto 148:fd96258d940d 3251 uint8_t RESERVED_0[40];
Kojto 148:fd96258d940d 3252 __IO uint32_t COUNT; /**< SCT counter register, offset: 0x40 */
Kojto 148:fd96258d940d 3253 __IO uint32_t STATE; /**< SCT state register, offset: 0x44 */
Kojto 148:fd96258d940d 3254 __I uint32_t INPUT; /**< SCT input register, offset: 0x48 */
Kojto 148:fd96258d940d 3255 __IO uint32_t REGMODE; /**< SCT match/capture mode register, offset: 0x4C */
Kojto 148:fd96258d940d 3256 __IO uint32_t OUTPUT; /**< SCT output register, offset: 0x50 */
Kojto 148:fd96258d940d 3257 __IO uint32_t OUTPUTDIRCTRL; /**< SCT output counter direction control register, offset: 0x54 */
Kojto 148:fd96258d940d 3258 __IO uint32_t RES; /**< SCT conflict resolution register, offset: 0x58 */
Kojto 148:fd96258d940d 3259 __IO uint32_t DMA0REQUEST; /**< SCT DMA request 0 register, offset: 0x5C */
Kojto 148:fd96258d940d 3260 __IO uint32_t DMA1REQUEST; /**< SCT DMA request 1 register, offset: 0x60 */
Kojto 148:fd96258d940d 3261 uint8_t RESERVED_1[140];
Kojto 148:fd96258d940d 3262 __IO uint32_t EVEN; /**< SCT event interrupt enable register, offset: 0xF0 */
Kojto 148:fd96258d940d 3263 __IO uint32_t EVFLAG; /**< SCT event flag register, offset: 0xF4 */
Kojto 148:fd96258d940d 3264 __IO uint32_t CONEN; /**< SCT conflict interrupt enable register, offset: 0xF8 */
Kojto 148:fd96258d940d 3265 __IO uint32_t CONFLAG; /**< SCT conflict flag register, offset: 0xFC */
Kojto 148:fd96258d940d 3266 union { /* offset: 0x100 */
Kojto 148:fd96258d940d 3267 __IO uint32_t SCTCAP[10]; /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */
Kojto 148:fd96258d940d 3268 __IO uint32_t SCTMATCH[10]; /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */
Kojto 148:fd96258d940d 3269 };
Kojto 148:fd96258d940d 3270 uint8_t RESERVED_2[216];
Kojto 148:fd96258d940d 3271 union { /* offset: 0x200 */
Kojto 148:fd96258d940d 3272 __IO uint32_t SCTCAPCTRL[10]; /**< SCT capture control register, array offset: 0x200, array step: 0x4 */
Kojto 148:fd96258d940d 3273 __IO uint32_t SCTMATCHREL[10]; /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */
Kojto 148:fd96258d940d 3274 };
Kojto 148:fd96258d940d 3275 uint8_t RESERVED_3[216];
Kojto 148:fd96258d940d 3276 struct { /* offset: 0x300, array step: 0x8 */
Kojto 148:fd96258d940d 3277 __IO uint32_t STATE; /**< SCT event state register 0, array offset: 0x300, array step: 0x8 */
Kojto 148:fd96258d940d 3278 __IO uint32_t CTRL; /**< SCT event control register 0, array offset: 0x304, array step: 0x8 */
Kojto 148:fd96258d940d 3279 } EVENT[10];
Kojto 148:fd96258d940d 3280 uint8_t RESERVED_4[432];
Kojto 148:fd96258d940d 3281 struct { /* offset: 0x500, array step: 0x8 */
Kojto 148:fd96258d940d 3282 __IO uint32_t SET; /**< SCT output 0 set register, array offset: 0x500, array step: 0x8 */
Kojto 148:fd96258d940d 3283 __IO uint32_t CLR; /**< SCT output 0 clear register, array offset: 0x504, array step: 0x8 */
Kojto 148:fd96258d940d 3284 } OUT[8];
Kojto 148:fd96258d940d 3285 uint8_t RESERVED_5[700];
Kojto 148:fd96258d940d 3286 __IO uint32_t MODULECONTENT; /**< Reserved, offset: 0x7FC */
Kojto 148:fd96258d940d 3287 } SCT_Type;
Kojto 148:fd96258d940d 3288
Kojto 148:fd96258d940d 3289 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 3290 -- SCT Register Masks
Kojto 148:fd96258d940d 3291 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 3292
Kojto 148:fd96258d940d 3293 /*!
Kojto 148:fd96258d940d 3294 * @addtogroup SCT_Register_Masks SCT Register Masks
Kojto 148:fd96258d940d 3295 * @{
Kojto 148:fd96258d940d 3296 */
Kojto 148:fd96258d940d 3297
Kojto 148:fd96258d940d 3298 /*! @name CONFIG - SCT configuration register */
Kojto 148:fd96258d940d 3299 #define SCT_CONFIG_UNIFY_MASK (0x1U)
Kojto 148:fd96258d940d 3300 #define SCT_CONFIG_UNIFY_SHIFT (0U)
Kojto 148:fd96258d940d 3301 #define SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK)
Kojto 148:fd96258d940d 3302 #define SCT_CONFIG_CLKMODE_MASK (0x6U)
Kojto 148:fd96258d940d 3303 #define SCT_CONFIG_CLKMODE_SHIFT (1U)
Kojto 148:fd96258d940d 3304 #define SCT_CONFIG_CLKMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK)
Kojto 148:fd96258d940d 3305 #define SCT_CONFIG_CKSEL_MASK (0x78U)
Kojto 148:fd96258d940d 3306 #define SCT_CONFIG_CKSEL_SHIFT (3U)
Kojto 148:fd96258d940d 3307 #define SCT_CONFIG_CKSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK)
Kojto 148:fd96258d940d 3308 #define SCT_CONFIG_NORELAOD_L_MASK (0x80U)
Kojto 148:fd96258d940d 3309 #define SCT_CONFIG_NORELAOD_L_SHIFT (7U)
Kojto 148:fd96258d940d 3310 #define SCT_CONFIG_NORELAOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELAOD_L_SHIFT)) & SCT_CONFIG_NORELAOD_L_MASK)
Kojto 148:fd96258d940d 3311 #define SCT_CONFIG_NORELOAD_H_MASK (0x100U)
Kojto 148:fd96258d940d 3312 #define SCT_CONFIG_NORELOAD_H_SHIFT (8U)
Kojto 148:fd96258d940d 3313 #define SCT_CONFIG_NORELOAD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK)
Kojto 148:fd96258d940d 3314 #define SCT_CONFIG_INSYNC_MASK (0x1E00U)
Kojto 148:fd96258d940d 3315 #define SCT_CONFIG_INSYNC_SHIFT (9U)
Kojto 148:fd96258d940d 3316 #define SCT_CONFIG_INSYNC(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK)
Kojto 148:fd96258d940d 3317 #define SCT_CONFIG_AUTOLIMIT_L_MASK (0x20000U)
Kojto 148:fd96258d940d 3318 #define SCT_CONFIG_AUTOLIMIT_L_SHIFT (17U)
Kojto 148:fd96258d940d 3319 #define SCT_CONFIG_AUTOLIMIT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK)
Kojto 148:fd96258d940d 3320 #define SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U)
Kojto 148:fd96258d940d 3321 #define SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U)
Kojto 148:fd96258d940d 3322 #define SCT_CONFIG_AUTOLIMIT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK)
Kojto 148:fd96258d940d 3323
Kojto 148:fd96258d940d 3324 /*! @name CTRL - SCT control register */
Kojto 148:fd96258d940d 3325 #define SCT_CTRL_DOWN_L_MASK (0x1U)
Kojto 148:fd96258d940d 3326 #define SCT_CTRL_DOWN_L_SHIFT (0U)
Kojto 148:fd96258d940d 3327 #define SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK)
Kojto 148:fd96258d940d 3328 #define SCT_CTRL_STOP_L_MASK (0x2U)
Kojto 148:fd96258d940d 3329 #define SCT_CTRL_STOP_L_SHIFT (1U)
Kojto 148:fd96258d940d 3330 #define SCT_CTRL_STOP_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK)
Kojto 148:fd96258d940d 3331 #define SCT_CTRL_HALT_L_MASK (0x4U)
Kojto 148:fd96258d940d 3332 #define SCT_CTRL_HALT_L_SHIFT (2U)
Kojto 148:fd96258d940d 3333 #define SCT_CTRL_HALT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK)
Kojto 148:fd96258d940d 3334 #define SCT_CTRL_CLRCTR_L_MASK (0x8U)
Kojto 148:fd96258d940d 3335 #define SCT_CTRL_CLRCTR_L_SHIFT (3U)
Kojto 148:fd96258d940d 3336 #define SCT_CTRL_CLRCTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK)
Kojto 148:fd96258d940d 3337 #define SCT_CTRL_BIDIR_L_MASK (0x10U)
Kojto 148:fd96258d940d 3338 #define SCT_CTRL_BIDIR_L_SHIFT (4U)
Kojto 148:fd96258d940d 3339 #define SCT_CTRL_BIDIR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK)
Kojto 148:fd96258d940d 3340 #define SCT_CTRL_PRE_L_MASK (0x1FE0U)
Kojto 148:fd96258d940d 3341 #define SCT_CTRL_PRE_L_SHIFT (5U)
Kojto 148:fd96258d940d 3342 #define SCT_CTRL_PRE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK)
Kojto 148:fd96258d940d 3343 #define SCT_CTRL_DOWN_H_MASK (0x10000U)
Kojto 148:fd96258d940d 3344 #define SCT_CTRL_DOWN_H_SHIFT (16U)
Kojto 148:fd96258d940d 3345 #define SCT_CTRL_DOWN_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK)
Kojto 148:fd96258d940d 3346 #define SCT_CTRL_STOP_H_MASK (0x20000U)
Kojto 148:fd96258d940d 3347 #define SCT_CTRL_STOP_H_SHIFT (17U)
Kojto 148:fd96258d940d 3348 #define SCT_CTRL_STOP_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK)
Kojto 148:fd96258d940d 3349 #define SCT_CTRL_HALT_H_MASK (0x40000U)
Kojto 148:fd96258d940d 3350 #define SCT_CTRL_HALT_H_SHIFT (18U)
Kojto 148:fd96258d940d 3351 #define SCT_CTRL_HALT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK)
Kojto 148:fd96258d940d 3352 #define SCT_CTRL_CLRCTR_H_MASK (0x80000U)
Kojto 148:fd96258d940d 3353 #define SCT_CTRL_CLRCTR_H_SHIFT (19U)
Kojto 148:fd96258d940d 3354 #define SCT_CTRL_CLRCTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK)
Kojto 148:fd96258d940d 3355 #define SCT_CTRL_BIDIR_H_MASK (0x100000U)
Kojto 148:fd96258d940d 3356 #define SCT_CTRL_BIDIR_H_SHIFT (20U)
Kojto 148:fd96258d940d 3357 #define SCT_CTRL_BIDIR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK)
Kojto 148:fd96258d940d 3358 #define SCT_CTRL_PRE_H_MASK (0x1FE00000U)
Kojto 148:fd96258d940d 3359 #define SCT_CTRL_PRE_H_SHIFT (21U)
Kojto 148:fd96258d940d 3360 #define SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK)
Kojto 148:fd96258d940d 3361
Kojto 148:fd96258d940d 3362 /*! @name LIMIT - SCT limit event select register */
Kojto 148:fd96258d940d 3363 #define SCT_LIMIT_LIMMSK_L_MASK (0xFFFFU)
Kojto 148:fd96258d940d 3364 #define SCT_LIMIT_LIMMSK_L_SHIFT (0U)
Kojto 148:fd96258d940d 3365 #define SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK)
Kojto 148:fd96258d940d 3366 #define SCT_LIMIT_LIMMSK_H_MASK (0xFFFF0000U)
Kojto 148:fd96258d940d 3367 #define SCT_LIMIT_LIMMSK_H_SHIFT (16U)
Kojto 148:fd96258d940d 3368 #define SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK)
Kojto 148:fd96258d940d 3369
Kojto 148:fd96258d940d 3370 /*! @name HALT - SCT halt event select register */
Kojto 148:fd96258d940d 3371 #define SCT_HALT_HALTMSK_L_MASK (0xFFFFU)
Kojto 148:fd96258d940d 3372 #define SCT_HALT_HALTMSK_L_SHIFT (0U)
Kojto 148:fd96258d940d 3373 #define SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK)
Kojto 148:fd96258d940d 3374 #define SCT_HALT_HALTMSK_H_MASK (0xFFFF0000U)
Kojto 148:fd96258d940d 3375 #define SCT_HALT_HALTMSK_H_SHIFT (16U)
Kojto 148:fd96258d940d 3376 #define SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK)
Kojto 148:fd96258d940d 3377
Kojto 148:fd96258d940d 3378 /*! @name STOP - SCT stop event select register */
Kojto 148:fd96258d940d 3379 #define SCT_STOP_STOPMSK_L_MASK (0xFFFFU)
Kojto 148:fd96258d940d 3380 #define SCT_STOP_STOPMSK_L_SHIFT (0U)
Kojto 148:fd96258d940d 3381 #define SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK)
Kojto 148:fd96258d940d 3382 #define SCT_STOP_STOPMSK_H_MASK (0xFFFF0000U)
Kojto 148:fd96258d940d 3383 #define SCT_STOP_STOPMSK_H_SHIFT (16U)
Kojto 148:fd96258d940d 3384 #define SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK)
Kojto 148:fd96258d940d 3385
Kojto 148:fd96258d940d 3386 /*! @name START - SCT start event select register */
Kojto 148:fd96258d940d 3387 #define SCT_START_STARTMSK_L_MASK (0xFFFFU)
Kojto 148:fd96258d940d 3388 #define SCT_START_STARTMSK_L_SHIFT (0U)
Kojto 148:fd96258d940d 3389 #define SCT_START_STARTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK)
Kojto 148:fd96258d940d 3390 #define SCT_START_STARTMSK_H_MASK (0xFFFF0000U)
Kojto 148:fd96258d940d 3391 #define SCT_START_STARTMSK_H_SHIFT (16U)
Kojto 148:fd96258d940d 3392 #define SCT_START_STARTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK)
Kojto 148:fd96258d940d 3393
Kojto 148:fd96258d940d 3394 /*! @name COUNT - SCT counter register */
Kojto 148:fd96258d940d 3395 #define SCT_COUNT_CTR_L_MASK (0xFFFFU)
Kojto 148:fd96258d940d 3396 #define SCT_COUNT_CTR_L_SHIFT (0U)
Kojto 148:fd96258d940d 3397 #define SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK)
Kojto 148:fd96258d940d 3398 #define SCT_COUNT_CTR_H_MASK (0xFFFF0000U)
Kojto 148:fd96258d940d 3399 #define SCT_COUNT_CTR_H_SHIFT (16U)
Kojto 148:fd96258d940d 3400 #define SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK)
Kojto 148:fd96258d940d 3401
Kojto 148:fd96258d940d 3402 /*! @name STATE - SCT state register */
Kojto 148:fd96258d940d 3403 #define SCT_STATE_STATE_L_MASK (0x1FU)
Kojto 148:fd96258d940d 3404 #define SCT_STATE_STATE_L_SHIFT (0U)
Kojto 148:fd96258d940d 3405 #define SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK)
Kojto 148:fd96258d940d 3406 #define SCT_STATE_STATE_H_MASK (0x1F0000U)
Kojto 148:fd96258d940d 3407 #define SCT_STATE_STATE_H_SHIFT (16U)
Kojto 148:fd96258d940d 3408 #define SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK)
Kojto 148:fd96258d940d 3409
Kojto 148:fd96258d940d 3410 /*! @name INPUT - SCT input register */
Kojto 148:fd96258d940d 3411 #define SCT_INPUT_AIN0_MASK (0x1U)
Kojto 148:fd96258d940d 3412 #define SCT_INPUT_AIN0_SHIFT (0U)
Kojto 148:fd96258d940d 3413 #define SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK)
Kojto 148:fd96258d940d 3414 #define SCT_INPUT_AIN1_MASK (0x2U)
Kojto 148:fd96258d940d 3415 #define SCT_INPUT_AIN1_SHIFT (1U)
Kojto 148:fd96258d940d 3416 #define SCT_INPUT_AIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK)
Kojto 148:fd96258d940d 3417 #define SCT_INPUT_AIN2_MASK (0x4U)
Kojto 148:fd96258d940d 3418 #define SCT_INPUT_AIN2_SHIFT (2U)
Kojto 148:fd96258d940d 3419 #define SCT_INPUT_AIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK)
Kojto 148:fd96258d940d 3420 #define SCT_INPUT_AIN3_MASK (0x8U)
Kojto 148:fd96258d940d 3421 #define SCT_INPUT_AIN3_SHIFT (3U)
Kojto 148:fd96258d940d 3422 #define SCT_INPUT_AIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK)
Kojto 148:fd96258d940d 3423 #define SCT_INPUT_AIN4_MASK (0x10U)
Kojto 148:fd96258d940d 3424 #define SCT_INPUT_AIN4_SHIFT (4U)
Kojto 148:fd96258d940d 3425 #define SCT_INPUT_AIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK)
Kojto 148:fd96258d940d 3426 #define SCT_INPUT_AIN5_MASK (0x20U)
Kojto 148:fd96258d940d 3427 #define SCT_INPUT_AIN5_SHIFT (5U)
Kojto 148:fd96258d940d 3428 #define SCT_INPUT_AIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK)
Kojto 148:fd96258d940d 3429 #define SCT_INPUT_AIN6_MASK (0x40U)
Kojto 148:fd96258d940d 3430 #define SCT_INPUT_AIN6_SHIFT (6U)
Kojto 148:fd96258d940d 3431 #define SCT_INPUT_AIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK)
Kojto 148:fd96258d940d 3432 #define SCT_INPUT_AIN7_MASK (0x80U)
Kojto 148:fd96258d940d 3433 #define SCT_INPUT_AIN7_SHIFT (7U)
Kojto 148:fd96258d940d 3434 #define SCT_INPUT_AIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK)
Kojto 148:fd96258d940d 3435 #define SCT_INPUT_AIN8_MASK (0x100U)
Kojto 148:fd96258d940d 3436 #define SCT_INPUT_AIN8_SHIFT (8U)
Kojto 148:fd96258d940d 3437 #define SCT_INPUT_AIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK)
Kojto 148:fd96258d940d 3438 #define SCT_INPUT_AIN9_MASK (0x200U)
Kojto 148:fd96258d940d 3439 #define SCT_INPUT_AIN9_SHIFT (9U)
Kojto 148:fd96258d940d 3440 #define SCT_INPUT_AIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK)
Kojto 148:fd96258d940d 3441 #define SCT_INPUT_AIN10_MASK (0x400U)
Kojto 148:fd96258d940d 3442 #define SCT_INPUT_AIN10_SHIFT (10U)
Kojto 148:fd96258d940d 3443 #define SCT_INPUT_AIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK)
Kojto 148:fd96258d940d 3444 #define SCT_INPUT_AIN11_MASK (0x800U)
Kojto 148:fd96258d940d 3445 #define SCT_INPUT_AIN11_SHIFT (11U)
Kojto 148:fd96258d940d 3446 #define SCT_INPUT_AIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK)
Kojto 148:fd96258d940d 3447 #define SCT_INPUT_AIN12_MASK (0x1000U)
Kojto 148:fd96258d940d 3448 #define SCT_INPUT_AIN12_SHIFT (12U)
Kojto 148:fd96258d940d 3449 #define SCT_INPUT_AIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK)
Kojto 148:fd96258d940d 3450 #define SCT_INPUT_AIN13_MASK (0x2000U)
Kojto 148:fd96258d940d 3451 #define SCT_INPUT_AIN13_SHIFT (13U)
Kojto 148:fd96258d940d 3452 #define SCT_INPUT_AIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK)
Kojto 148:fd96258d940d 3453 #define SCT_INPUT_AIN14_MASK (0x4000U)
Kojto 148:fd96258d940d 3454 #define SCT_INPUT_AIN14_SHIFT (14U)
Kojto 148:fd96258d940d 3455 #define SCT_INPUT_AIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK)
Kojto 148:fd96258d940d 3456 #define SCT_INPUT_AIN15_MASK (0x8000U)
Kojto 148:fd96258d940d 3457 #define SCT_INPUT_AIN15_SHIFT (15U)
Kojto 148:fd96258d940d 3458 #define SCT_INPUT_AIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK)
Kojto 148:fd96258d940d 3459 #define SCT_INPUT_SIN0_MASK (0x10000U)
Kojto 148:fd96258d940d 3460 #define SCT_INPUT_SIN0_SHIFT (16U)
Kojto 148:fd96258d940d 3461 #define SCT_INPUT_SIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK)
Kojto 148:fd96258d940d 3462 #define SCT_INPUT_SIN1_MASK (0x20000U)
Kojto 148:fd96258d940d 3463 #define SCT_INPUT_SIN1_SHIFT (17U)
Kojto 148:fd96258d940d 3464 #define SCT_INPUT_SIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK)
Kojto 148:fd96258d940d 3465 #define SCT_INPUT_SIN2_MASK (0x40000U)
Kojto 148:fd96258d940d 3466 #define SCT_INPUT_SIN2_SHIFT (18U)
Kojto 148:fd96258d940d 3467 #define SCT_INPUT_SIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK)
Kojto 148:fd96258d940d 3468 #define SCT_INPUT_SIN3_MASK (0x80000U)
Kojto 148:fd96258d940d 3469 #define SCT_INPUT_SIN3_SHIFT (19U)
Kojto 148:fd96258d940d 3470 #define SCT_INPUT_SIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK)
Kojto 148:fd96258d940d 3471 #define SCT_INPUT_SIN4_MASK (0x100000U)
Kojto 148:fd96258d940d 3472 #define SCT_INPUT_SIN4_SHIFT (20U)
Kojto 148:fd96258d940d 3473 #define SCT_INPUT_SIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK)
Kojto 148:fd96258d940d 3474 #define SCT_INPUT_SIN5_MASK (0x200000U)
Kojto 148:fd96258d940d 3475 #define SCT_INPUT_SIN5_SHIFT (21U)
Kojto 148:fd96258d940d 3476 #define SCT_INPUT_SIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK)
Kojto 148:fd96258d940d 3477 #define SCT_INPUT_SIN6_MASK (0x400000U)
Kojto 148:fd96258d940d 3478 #define SCT_INPUT_SIN6_SHIFT (22U)
Kojto 148:fd96258d940d 3479 #define SCT_INPUT_SIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK)
Kojto 148:fd96258d940d 3480 #define SCT_INPUT_SIN7_MASK (0x800000U)
Kojto 148:fd96258d940d 3481 #define SCT_INPUT_SIN7_SHIFT (23U)
Kojto 148:fd96258d940d 3482 #define SCT_INPUT_SIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK)
Kojto 148:fd96258d940d 3483 #define SCT_INPUT_SIN8_MASK (0x1000000U)
Kojto 148:fd96258d940d 3484 #define SCT_INPUT_SIN8_SHIFT (24U)
Kojto 148:fd96258d940d 3485 #define SCT_INPUT_SIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK)
Kojto 148:fd96258d940d 3486 #define SCT_INPUT_SIN9_MASK (0x2000000U)
Kojto 148:fd96258d940d 3487 #define SCT_INPUT_SIN9_SHIFT (25U)
Kojto 148:fd96258d940d 3488 #define SCT_INPUT_SIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK)
Kojto 148:fd96258d940d 3489 #define SCT_INPUT_SIN10_MASK (0x4000000U)
Kojto 148:fd96258d940d 3490 #define SCT_INPUT_SIN10_SHIFT (26U)
Kojto 148:fd96258d940d 3491 #define SCT_INPUT_SIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK)
Kojto 148:fd96258d940d 3492 #define SCT_INPUT_SIN11_MASK (0x8000000U)
Kojto 148:fd96258d940d 3493 #define SCT_INPUT_SIN11_SHIFT (27U)
Kojto 148:fd96258d940d 3494 #define SCT_INPUT_SIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK)
Kojto 148:fd96258d940d 3495 #define SCT_INPUT_SIN12_MASK (0x10000000U)
Kojto 148:fd96258d940d 3496 #define SCT_INPUT_SIN12_SHIFT (28U)
Kojto 148:fd96258d940d 3497 #define SCT_INPUT_SIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK)
Kojto 148:fd96258d940d 3498 #define SCT_INPUT_SIN13_MASK (0x20000000U)
Kojto 148:fd96258d940d 3499 #define SCT_INPUT_SIN13_SHIFT (29U)
Kojto 148:fd96258d940d 3500 #define SCT_INPUT_SIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK)
Kojto 148:fd96258d940d 3501 #define SCT_INPUT_SIN14_MASK (0x40000000U)
Kojto 148:fd96258d940d 3502 #define SCT_INPUT_SIN14_SHIFT (30U)
Kojto 148:fd96258d940d 3503 #define SCT_INPUT_SIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK)
Kojto 148:fd96258d940d 3504 #define SCT_INPUT_SIN15_MASK (0x80000000U)
Kojto 148:fd96258d940d 3505 #define SCT_INPUT_SIN15_SHIFT (31U)
Kojto 148:fd96258d940d 3506 #define SCT_INPUT_SIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK)
Kojto 148:fd96258d940d 3507
Kojto 148:fd96258d940d 3508 /*! @name REGMODE - SCT match/capture mode register */
Kojto 148:fd96258d940d 3509 #define SCT_REGMODE_REGMOD_L_MASK (0xFFFFU)
Kojto 148:fd96258d940d 3510 #define SCT_REGMODE_REGMOD_L_SHIFT (0U)
Kojto 148:fd96258d940d 3511 #define SCT_REGMODE_REGMOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK)
Kojto 148:fd96258d940d 3512 #define SCT_REGMODE_REGMOD_H_MASK (0xFFFF0000U)
Kojto 148:fd96258d940d 3513 #define SCT_REGMODE_REGMOD_H_SHIFT (16U)
Kojto 148:fd96258d940d 3514 #define SCT_REGMODE_REGMOD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK)
Kojto 148:fd96258d940d 3515
Kojto 148:fd96258d940d 3516 /*! @name OUTPUT - SCT output register */
Kojto 148:fd96258d940d 3517 #define SCT_OUTPUT_OUT_MASK (0xFFFFU)
Kojto 148:fd96258d940d 3518 #define SCT_OUTPUT_OUT_SHIFT (0U)
Kojto 148:fd96258d940d 3519 #define SCT_OUTPUT_OUT(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK)
Kojto 148:fd96258d940d 3520
Kojto 148:fd96258d940d 3521 /*! @name OUTPUTDIRCTRL - SCT output counter direction control register */
Kojto 148:fd96258d940d 3522 #define SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U)
Kojto 148:fd96258d940d 3523 #define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U)
Kojto 148:fd96258d940d 3524 #define SCT_OUTPUTDIRCTRL_SETCLR0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK)
Kojto 148:fd96258d940d 3525 #define SCT_OUTPUTDIRCTRL_SETCLR1_MASK (0xCU)
Kojto 148:fd96258d940d 3526 #define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT (2U)
Kojto 148:fd96258d940d 3527 #define SCT_OUTPUTDIRCTRL_SETCLR1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK)
Kojto 148:fd96258d940d 3528 #define SCT_OUTPUTDIRCTRL_SETCLR2_MASK (0x30U)
Kojto 148:fd96258d940d 3529 #define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT (4U)
Kojto 148:fd96258d940d 3530 #define SCT_OUTPUTDIRCTRL_SETCLR2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK)
Kojto 148:fd96258d940d 3531 #define SCT_OUTPUTDIRCTRL_SETCLR3_MASK (0xC0U)
Kojto 148:fd96258d940d 3532 #define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT (6U)
Kojto 148:fd96258d940d 3533 #define SCT_OUTPUTDIRCTRL_SETCLR3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK)
Kojto 148:fd96258d940d 3534 #define SCT_OUTPUTDIRCTRL_SETCLR4_MASK (0x300U)
Kojto 148:fd96258d940d 3535 #define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT (8U)
Kojto 148:fd96258d940d 3536 #define SCT_OUTPUTDIRCTRL_SETCLR4(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK)
Kojto 148:fd96258d940d 3537 #define SCT_OUTPUTDIRCTRL_SETCLR5_MASK (0xC00U)
Kojto 148:fd96258d940d 3538 #define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT (10U)
Kojto 148:fd96258d940d 3539 #define SCT_OUTPUTDIRCTRL_SETCLR5(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK)
Kojto 148:fd96258d940d 3540 #define SCT_OUTPUTDIRCTRL_SETCLR6_MASK (0x3000U)
Kojto 148:fd96258d940d 3541 #define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT (12U)
Kojto 148:fd96258d940d 3542 #define SCT_OUTPUTDIRCTRL_SETCLR6(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK)
Kojto 148:fd96258d940d 3543 #define SCT_OUTPUTDIRCTRL_SETCLR7_MASK (0xC000U)
Kojto 148:fd96258d940d 3544 #define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT (14U)
Kojto 148:fd96258d940d 3545 #define SCT_OUTPUTDIRCTRL_SETCLR7(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK)
Kojto 148:fd96258d940d 3546 #define SCT_OUTPUTDIRCTRL_SETCLR8_MASK (0x30000U)
Kojto 148:fd96258d940d 3547 #define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT (16U)
Kojto 148:fd96258d940d 3548 #define SCT_OUTPUTDIRCTRL_SETCLR8(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK)
Kojto 148:fd96258d940d 3549 #define SCT_OUTPUTDIRCTRL_SETCLR9_MASK (0xC0000U)
Kojto 148:fd96258d940d 3550 #define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT (18U)
Kojto 148:fd96258d940d 3551 #define SCT_OUTPUTDIRCTRL_SETCLR9(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK)
Kojto 148:fd96258d940d 3552 #define SCT_OUTPUTDIRCTRL_SETCLR10_MASK (0x300000U)
Kojto 148:fd96258d940d 3553 #define SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT (20U)
Kojto 148:fd96258d940d 3554 #define SCT_OUTPUTDIRCTRL_SETCLR10(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR10_MASK)
Kojto 148:fd96258d940d 3555 #define SCT_OUTPUTDIRCTRL_SETCLR11_MASK (0xC00000U)
Kojto 148:fd96258d940d 3556 #define SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT (22U)
Kojto 148:fd96258d940d 3557 #define SCT_OUTPUTDIRCTRL_SETCLR11(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR11_MASK)
Kojto 148:fd96258d940d 3558 #define SCT_OUTPUTDIRCTRL_SETCLR12_MASK (0x3000000U)
Kojto 148:fd96258d940d 3559 #define SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT (24U)
Kojto 148:fd96258d940d 3560 #define SCT_OUTPUTDIRCTRL_SETCLR12(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR12_MASK)
Kojto 148:fd96258d940d 3561 #define SCT_OUTPUTDIRCTRL_SETCLR13_MASK (0xC000000U)
Kojto 148:fd96258d940d 3562 #define SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT (26U)
Kojto 148:fd96258d940d 3563 #define SCT_OUTPUTDIRCTRL_SETCLR13(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR13_MASK)
Kojto 148:fd96258d940d 3564 #define SCT_OUTPUTDIRCTRL_SETCLR14_MASK (0x30000000U)
Kojto 148:fd96258d940d 3565 #define SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT (28U)
Kojto 148:fd96258d940d 3566 #define SCT_OUTPUTDIRCTRL_SETCLR14(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR14_MASK)
Kojto 148:fd96258d940d 3567 #define SCT_OUTPUTDIRCTRL_SETCLR15_MASK (0xC0000000U)
Kojto 148:fd96258d940d 3568 #define SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT (30U)
Kojto 148:fd96258d940d 3569 #define SCT_OUTPUTDIRCTRL_SETCLR15(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR15_MASK)
Kojto 148:fd96258d940d 3570
Kojto 148:fd96258d940d 3571 /*! @name RES - SCT conflict resolution register */
Kojto 148:fd96258d940d 3572 #define SCT_RES_O0RES_MASK (0x3U)
Kojto 148:fd96258d940d 3573 #define SCT_RES_O0RES_SHIFT (0U)
Kojto 148:fd96258d940d 3574 #define SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK)
Kojto 148:fd96258d940d 3575 #define SCT_RES_O1RES_MASK (0xCU)
Kojto 148:fd96258d940d 3576 #define SCT_RES_O1RES_SHIFT (2U)
Kojto 148:fd96258d940d 3577 #define SCT_RES_O1RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK)
Kojto 148:fd96258d940d 3578 #define SCT_RES_O2RES_MASK (0x30U)
Kojto 148:fd96258d940d 3579 #define SCT_RES_O2RES_SHIFT (4U)
Kojto 148:fd96258d940d 3580 #define SCT_RES_O2RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK)
Kojto 148:fd96258d940d 3581 #define SCT_RES_O3RES_MASK (0xC0U)
Kojto 148:fd96258d940d 3582 #define SCT_RES_O3RES_SHIFT (6U)
Kojto 148:fd96258d940d 3583 #define SCT_RES_O3RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK)
Kojto 148:fd96258d940d 3584 #define SCT_RES_O4RES_MASK (0x300U)
Kojto 148:fd96258d940d 3585 #define SCT_RES_O4RES_SHIFT (8U)
Kojto 148:fd96258d940d 3586 #define SCT_RES_O4RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK)
Kojto 148:fd96258d940d 3587 #define SCT_RES_O5RES_MASK (0xC00U)
Kojto 148:fd96258d940d 3588 #define SCT_RES_O5RES_SHIFT (10U)
Kojto 148:fd96258d940d 3589 #define SCT_RES_O5RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK)
Kojto 148:fd96258d940d 3590 #define SCT_RES_O6RES_MASK (0x3000U)
Kojto 148:fd96258d940d 3591 #define SCT_RES_O6RES_SHIFT (12U)
Kojto 148:fd96258d940d 3592 #define SCT_RES_O6RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK)
Kojto 148:fd96258d940d 3593 #define SCT_RES_O7RES_MASK (0xC000U)
Kojto 148:fd96258d940d 3594 #define SCT_RES_O7RES_SHIFT (14U)
Kojto 148:fd96258d940d 3595 #define SCT_RES_O7RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK)
Kojto 148:fd96258d940d 3596 #define SCT_RES_O8RES_MASK (0x30000U)
Kojto 148:fd96258d940d 3597 #define SCT_RES_O8RES_SHIFT (16U)
Kojto 148:fd96258d940d 3598 #define SCT_RES_O8RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK)
Kojto 148:fd96258d940d 3599 #define SCT_RES_O9RES_MASK (0xC0000U)
Kojto 148:fd96258d940d 3600 #define SCT_RES_O9RES_SHIFT (18U)
Kojto 148:fd96258d940d 3601 #define SCT_RES_O9RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK)
Kojto 148:fd96258d940d 3602 #define SCT_RES_O10RES_MASK (0x300000U)
Kojto 148:fd96258d940d 3603 #define SCT_RES_O10RES_SHIFT (20U)
Kojto 148:fd96258d940d 3604 #define SCT_RES_O10RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O10RES_SHIFT)) & SCT_RES_O10RES_MASK)
Kojto 148:fd96258d940d 3605 #define SCT_RES_O11RES_MASK (0xC00000U)
Kojto 148:fd96258d940d 3606 #define SCT_RES_O11RES_SHIFT (22U)
Kojto 148:fd96258d940d 3607 #define SCT_RES_O11RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O11RES_SHIFT)) & SCT_RES_O11RES_MASK)
Kojto 148:fd96258d940d 3608 #define SCT_RES_O12RES_MASK (0x3000000U)
Kojto 148:fd96258d940d 3609 #define SCT_RES_O12RES_SHIFT (24U)
Kojto 148:fd96258d940d 3610 #define SCT_RES_O12RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O12RES_SHIFT)) & SCT_RES_O12RES_MASK)
Kojto 148:fd96258d940d 3611 #define SCT_RES_O13RES_MASK (0xC000000U)
Kojto 148:fd96258d940d 3612 #define SCT_RES_O13RES_SHIFT (26U)
Kojto 148:fd96258d940d 3613 #define SCT_RES_O13RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O13RES_SHIFT)) & SCT_RES_O13RES_MASK)
Kojto 148:fd96258d940d 3614 #define SCT_RES_O14RES_MASK (0x30000000U)
Kojto 148:fd96258d940d 3615 #define SCT_RES_O14RES_SHIFT (28U)
Kojto 148:fd96258d940d 3616 #define SCT_RES_O14RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O14RES_SHIFT)) & SCT_RES_O14RES_MASK)
Kojto 148:fd96258d940d 3617 #define SCT_RES_O15RES_MASK (0xC0000000U)
Kojto 148:fd96258d940d 3618 #define SCT_RES_O15RES_SHIFT (30U)
Kojto 148:fd96258d940d 3619 #define SCT_RES_O15RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O15RES_SHIFT)) & SCT_RES_O15RES_MASK)
Kojto 148:fd96258d940d 3620
Kojto 148:fd96258d940d 3621 /*! @name DMA0REQUEST - SCT DMA request 0 register */
Kojto 148:fd96258d940d 3622 #define SCT_DMA0REQUEST_DEV_0_MASK (0xFFFFU)
Kojto 148:fd96258d940d 3623 #define SCT_DMA0REQUEST_DEV_0_SHIFT (0U)
Kojto 148:fd96258d940d 3624 #define SCT_DMA0REQUEST_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DEV_0_SHIFT)) & SCT_DMA0REQUEST_DEV_0_MASK)
Kojto 148:fd96258d940d 3625 #define SCT_DMA0REQUEST_DRL0_MASK (0x40000000U)
Kojto 148:fd96258d940d 3626 #define SCT_DMA0REQUEST_DRL0_SHIFT (30U)
Kojto 148:fd96258d940d 3627 #define SCT_DMA0REQUEST_DRL0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRL0_SHIFT)) & SCT_DMA0REQUEST_DRL0_MASK)
Kojto 148:fd96258d940d 3628 #define SCT_DMA0REQUEST_DRQ0_MASK (0x80000000U)
Kojto 148:fd96258d940d 3629 #define SCT_DMA0REQUEST_DRQ0_SHIFT (31U)
Kojto 148:fd96258d940d 3630 #define SCT_DMA0REQUEST_DRQ0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRQ0_SHIFT)) & SCT_DMA0REQUEST_DRQ0_MASK)
Kojto 148:fd96258d940d 3631
Kojto 148:fd96258d940d 3632 /*! @name DMA1REQUEST - SCT DMA request 1 register */
Kojto 148:fd96258d940d 3633 #define SCT_DMA1REQUEST_DEV_1_MASK (0xFFFFU)
Kojto 148:fd96258d940d 3634 #define SCT_DMA1REQUEST_DEV_1_SHIFT (0U)
Kojto 148:fd96258d940d 3635 #define SCT_DMA1REQUEST_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DEV_1_SHIFT)) & SCT_DMA1REQUEST_DEV_1_MASK)
Kojto 148:fd96258d940d 3636 #define SCT_DMA1REQUEST_DRL1_MASK (0x40000000U)
Kojto 148:fd96258d940d 3637 #define SCT_DMA1REQUEST_DRL1_SHIFT (30U)
Kojto 148:fd96258d940d 3638 #define SCT_DMA1REQUEST_DRL1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRL1_SHIFT)) & SCT_DMA1REQUEST_DRL1_MASK)
Kojto 148:fd96258d940d 3639 #define SCT_DMA1REQUEST_DRQ1_MASK (0x80000000U)
Kojto 148:fd96258d940d 3640 #define SCT_DMA1REQUEST_DRQ1_SHIFT (31U)
Kojto 148:fd96258d940d 3641 #define SCT_DMA1REQUEST_DRQ1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRQ1_SHIFT)) & SCT_DMA1REQUEST_DRQ1_MASK)
Kojto 148:fd96258d940d 3642
Kojto 148:fd96258d940d 3643 /*! @name EVEN - SCT event interrupt enable register */
Kojto 148:fd96258d940d 3644 #define SCT_EVEN_IEN_MASK (0xFFFFU)
Kojto 148:fd96258d940d 3645 #define SCT_EVEN_IEN_SHIFT (0U)
Kojto 148:fd96258d940d 3646 #define SCT_EVEN_IEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK)
Kojto 148:fd96258d940d 3647
Kojto 148:fd96258d940d 3648 /*! @name EVFLAG - SCT event flag register */
Kojto 148:fd96258d940d 3649 #define SCT_EVFLAG_FLAG_MASK (0xFFFFU)
Kojto 148:fd96258d940d 3650 #define SCT_EVFLAG_FLAG_SHIFT (0U)
Kojto 148:fd96258d940d 3651 #define SCT_EVFLAG_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK)
Kojto 148:fd96258d940d 3652
Kojto 148:fd96258d940d 3653 /*! @name CONEN - SCT conflict interrupt enable register */
Kojto 148:fd96258d940d 3654 #define SCT_CONEN_NCEN_MASK (0xFFFFU)
Kojto 148:fd96258d940d 3655 #define SCT_CONEN_NCEN_SHIFT (0U)
Kojto 148:fd96258d940d 3656 #define SCT_CONEN_NCEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK)
Kojto 148:fd96258d940d 3657
Kojto 148:fd96258d940d 3658 /*! @name CONFLAG - SCT conflict flag register */
Kojto 148:fd96258d940d 3659 #define SCT_CONFLAG_NCFLAG_MASK (0xFFFFU)
Kojto 148:fd96258d940d 3660 #define SCT_CONFLAG_NCFLAG_SHIFT (0U)
Kojto 148:fd96258d940d 3661 #define SCT_CONFLAG_NCFLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK)
Kojto 148:fd96258d940d 3662 #define SCT_CONFLAG_BUSERRL_MASK (0x40000000U)
Kojto 148:fd96258d940d 3663 #define SCT_CONFLAG_BUSERRL_SHIFT (30U)
Kojto 148:fd96258d940d 3664 #define SCT_CONFLAG_BUSERRL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK)
Kojto 148:fd96258d940d 3665 #define SCT_CONFLAG_BUSERRH_MASK (0x80000000U)
Kojto 148:fd96258d940d 3666 #define SCT_CONFLAG_BUSERRH_SHIFT (31U)
Kojto 148:fd96258d940d 3667 #define SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK)
Kojto 148:fd96258d940d 3668
Kojto 148:fd96258d940d 3669 /*! @name SCTCAP - SCT capture register of capture channel */
Kojto 148:fd96258d940d 3670 #define SCT_SCTCAP_CAPn_L_MASK (0xFFFFU)
Kojto 148:fd96258d940d 3671 #define SCT_SCTCAP_CAPn_L_SHIFT (0U)
Kojto 148:fd96258d940d 3672 #define SCT_SCTCAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_L_SHIFT)) & SCT_SCTCAP_CAPn_L_MASK)
Kojto 148:fd96258d940d 3673 #define SCT_SCTCAP_CAPn_H_MASK (0xFFFF0000U)
Kojto 148:fd96258d940d 3674 #define SCT_SCTCAP_CAPn_H_SHIFT (16U)
Kojto 148:fd96258d940d 3675 #define SCT_SCTCAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_H_SHIFT)) & SCT_SCTCAP_CAPn_H_MASK)
Kojto 148:fd96258d940d 3676
Kojto 148:fd96258d940d 3677 /* The count of SCT_SCTCAP */
Kojto 148:fd96258d940d 3678 #define SCT_SCTCAP_COUNT (10U)
Kojto 148:fd96258d940d 3679
Kojto 148:fd96258d940d 3680 /*! @name SCTMATCH - SCT match value register of match channels */
Kojto 148:fd96258d940d 3681 #define SCT_SCTMATCH_MATCHn_L_MASK (0xFFFFU)
Kojto 148:fd96258d940d 3682 #define SCT_SCTMATCH_MATCHn_L_SHIFT (0U)
Kojto 148:fd96258d940d 3683 #define SCT_SCTMATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_L_SHIFT)) & SCT_SCTMATCH_MATCHn_L_MASK)
Kojto 148:fd96258d940d 3684 #define SCT_SCTMATCH_MATCHn_H_MASK (0xFFFF0000U)
Kojto 148:fd96258d940d 3685 #define SCT_SCTMATCH_MATCHn_H_SHIFT (16U)
Kojto 148:fd96258d940d 3686 #define SCT_SCTMATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_H_SHIFT)) & SCT_SCTMATCH_MATCHn_H_MASK)
Kojto 148:fd96258d940d 3687
Kojto 148:fd96258d940d 3688 /* The count of SCT_SCTMATCH */
Kojto 148:fd96258d940d 3689 #define SCT_SCTMATCH_COUNT (10U)
Kojto 148:fd96258d940d 3690
Kojto 148:fd96258d940d 3691 /*! @name SCTCAPCTRL - SCT capture control register */
Kojto 148:fd96258d940d 3692 #define SCT_SCTCAPCTRL_CAPCONn_L_MASK (0xFFFFU)
Kojto 148:fd96258d940d 3693 #define SCT_SCTCAPCTRL_CAPCONn_L_SHIFT (0U)
Kojto 148:fd96258d940d 3694 #define SCT_SCTCAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_L_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_L_MASK)
Kojto 148:fd96258d940d 3695 #define SCT_SCTCAPCTRL_CAPCONn_H_MASK (0xFFFF0000U)
Kojto 148:fd96258d940d 3696 #define SCT_SCTCAPCTRL_CAPCONn_H_SHIFT (16U)
Kojto 148:fd96258d940d 3697 #define SCT_SCTCAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_H_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_H_MASK)
Kojto 148:fd96258d940d 3698
Kojto 148:fd96258d940d 3699 /* The count of SCT_SCTCAPCTRL */
Kojto 148:fd96258d940d 3700 #define SCT_SCTCAPCTRL_COUNT (10U)
Kojto 148:fd96258d940d 3701
Kojto 148:fd96258d940d 3702 /*! @name SCTMATCHREL - SCT match reload value register */
Kojto 148:fd96258d940d 3703 #define SCT_SCTMATCHREL_RELOADn_L_MASK (0xFFFFU)
Kojto 148:fd96258d940d 3704 #define SCT_SCTMATCHREL_RELOADn_L_SHIFT (0U)
Kojto 148:fd96258d940d 3705 #define SCT_SCTMATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_L_SHIFT)) & SCT_SCTMATCHREL_RELOADn_L_MASK)
Kojto 148:fd96258d940d 3706 #define SCT_SCTMATCHREL_RELOADn_H_MASK (0xFFFF0000U)
Kojto 148:fd96258d940d 3707 #define SCT_SCTMATCHREL_RELOADn_H_SHIFT (16U)
Kojto 148:fd96258d940d 3708 #define SCT_SCTMATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_H_SHIFT)) & SCT_SCTMATCHREL_RELOADn_H_MASK)
Kojto 148:fd96258d940d 3709
Kojto 148:fd96258d940d 3710 /* The count of SCT_SCTMATCHREL */
Kojto 148:fd96258d940d 3711 #define SCT_SCTMATCHREL_COUNT (10U)
Kojto 148:fd96258d940d 3712
Kojto 148:fd96258d940d 3713 /*! @name EVENT_STATE - SCT event state register 0 */
Kojto 148:fd96258d940d 3714 #define SCT_EVENT_STATE_STATEMSKn_MASK (0xFFFFU)
Kojto 148:fd96258d940d 3715 #define SCT_EVENT_STATE_STATEMSKn_SHIFT (0U)
Kojto 148:fd96258d940d 3716 #define SCT_EVENT_STATE_STATEMSKn(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_STATE_STATEMSKn_SHIFT)) & SCT_EVENT_STATE_STATEMSKn_MASK)
Kojto 148:fd96258d940d 3717
Kojto 148:fd96258d940d 3718 /* The count of SCT_EVENT_STATE */
Kojto 148:fd96258d940d 3719 #define SCT_EVENT_STATE_COUNT (10U)
Kojto 148:fd96258d940d 3720
Kojto 148:fd96258d940d 3721 /*! @name EVENT_CTRL - SCT event control register 0 */
Kojto 148:fd96258d940d 3722 #define SCT_EVENT_CTRL_MATCHSEL_MASK (0xFU)
Kojto 148:fd96258d940d 3723 #define SCT_EVENT_CTRL_MATCHSEL_SHIFT (0U)
Kojto 148:fd96258d940d 3724 #define SCT_EVENT_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHSEL_SHIFT)) & SCT_EVENT_CTRL_MATCHSEL_MASK)
Kojto 148:fd96258d940d 3725 #define SCT_EVENT_CTRL_HEVENT_MASK (0x10U)
Kojto 148:fd96258d940d 3726 #define SCT_EVENT_CTRL_HEVENT_SHIFT (4U)
Kojto 148:fd96258d940d 3727 #define SCT_EVENT_CTRL_HEVENT(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_HEVENT_SHIFT)) & SCT_EVENT_CTRL_HEVENT_MASK)
Kojto 148:fd96258d940d 3728 #define SCT_EVENT_CTRL_OUTSEL_MASK (0x20U)
Kojto 148:fd96258d940d 3729 #define SCT_EVENT_CTRL_OUTSEL_SHIFT (5U)
Kojto 148:fd96258d940d 3730 #define SCT_EVENT_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_OUTSEL_SHIFT)) & SCT_EVENT_CTRL_OUTSEL_MASK)
Kojto 148:fd96258d940d 3731 #define SCT_EVENT_CTRL_IOSEL_MASK (0x3C0U)
Kojto 148:fd96258d940d 3732 #define SCT_EVENT_CTRL_IOSEL_SHIFT (6U)
Kojto 148:fd96258d940d 3733 #define SCT_EVENT_CTRL_IOSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOSEL_SHIFT)) & SCT_EVENT_CTRL_IOSEL_MASK)
Kojto 148:fd96258d940d 3734 #define SCT_EVENT_CTRL_IOCOND_MASK (0xC00U)
Kojto 148:fd96258d940d 3735 #define SCT_EVENT_CTRL_IOCOND_SHIFT (10U)
Kojto 148:fd96258d940d 3736 #define SCT_EVENT_CTRL_IOCOND(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOCOND_SHIFT)) & SCT_EVENT_CTRL_IOCOND_MASK)
Kojto 148:fd96258d940d 3737 #define SCT_EVENT_CTRL_COMBMODE_MASK (0x3000U)
Kojto 148:fd96258d940d 3738 #define SCT_EVENT_CTRL_COMBMODE_SHIFT (12U)
Kojto 148:fd96258d940d 3739 #define SCT_EVENT_CTRL_COMBMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_COMBMODE_SHIFT)) & SCT_EVENT_CTRL_COMBMODE_MASK)
Kojto 148:fd96258d940d 3740 #define SCT_EVENT_CTRL_STATELD_MASK (0x4000U)
Kojto 148:fd96258d940d 3741 #define SCT_EVENT_CTRL_STATELD_SHIFT (14U)
Kojto 148:fd96258d940d 3742 #define SCT_EVENT_CTRL_STATELD(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATELD_SHIFT)) & SCT_EVENT_CTRL_STATELD_MASK)
Kojto 148:fd96258d940d 3743 #define SCT_EVENT_CTRL_STATEV_MASK (0xF8000U)
Kojto 148:fd96258d940d 3744 #define SCT_EVENT_CTRL_STATEV_SHIFT (15U)
Kojto 148:fd96258d940d 3745 #define SCT_EVENT_CTRL_STATEV(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATEV_SHIFT)) & SCT_EVENT_CTRL_STATEV_MASK)
Kojto 148:fd96258d940d 3746 #define SCT_EVENT_CTRL_MATCHMEM_MASK (0x100000U)
Kojto 148:fd96258d940d 3747 #define SCT_EVENT_CTRL_MATCHMEM_SHIFT (20U)
Kojto 148:fd96258d940d 3748 #define SCT_EVENT_CTRL_MATCHMEM(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHMEM_SHIFT)) & SCT_EVENT_CTRL_MATCHMEM_MASK)
Kojto 148:fd96258d940d 3749 #define SCT_EVENT_CTRL_DIRECTION_MASK (0x600000U)
Kojto 148:fd96258d940d 3750 #define SCT_EVENT_CTRL_DIRECTION_SHIFT (21U)
Kojto 148:fd96258d940d 3751 #define SCT_EVENT_CTRL_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_DIRECTION_SHIFT)) & SCT_EVENT_CTRL_DIRECTION_MASK)
Kojto 148:fd96258d940d 3752
Kojto 148:fd96258d940d 3753 /* The count of SCT_EVENT_CTRL */
Kojto 148:fd96258d940d 3754 #define SCT_EVENT_CTRL_COUNT (10U)
Kojto 148:fd96258d940d 3755
Kojto 148:fd96258d940d 3756 /*! @name OUT_SET - SCT output 0 set register */
Kojto 148:fd96258d940d 3757 #define SCT_OUT_SET_SET_MASK (0xFFFFU)
Kojto 148:fd96258d940d 3758 #define SCT_OUT_SET_SET_SHIFT (0U)
Kojto 148:fd96258d940d 3759 #define SCT_OUT_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK)
Kojto 148:fd96258d940d 3760
Kojto 148:fd96258d940d 3761 /* The count of SCT_OUT_SET */
Kojto 148:fd96258d940d 3762 #define SCT_OUT_SET_COUNT (8U)
Kojto 148:fd96258d940d 3763
Kojto 148:fd96258d940d 3764 /*! @name OUT_CLR - SCT output 0 clear register */
Kojto 148:fd96258d940d 3765 #define SCT_OUT_CLR_CLR_MASK (0xFFFFU)
Kojto 148:fd96258d940d 3766 #define SCT_OUT_CLR_CLR_SHIFT (0U)
Kojto 148:fd96258d940d 3767 #define SCT_OUT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK)
Kojto 148:fd96258d940d 3768
Kojto 148:fd96258d940d 3769 /* The count of SCT_OUT_CLR */
Kojto 148:fd96258d940d 3770 #define SCT_OUT_CLR_COUNT (8U)
Kojto 148:fd96258d940d 3771
Kojto 148:fd96258d940d 3772
Kojto 148:fd96258d940d 3773 /*!
Kojto 148:fd96258d940d 3774 * @}
Kojto 148:fd96258d940d 3775 */ /* end of group SCT_Register_Masks */
Kojto 148:fd96258d940d 3776
Kojto 148:fd96258d940d 3777
Kojto 148:fd96258d940d 3778 /* SCT - Peripheral instance base addresses */
Kojto 148:fd96258d940d 3779 /** Peripheral SCT0 base address */
Kojto 148:fd96258d940d 3780 #define SCT0_BASE (0x40085000u)
Kojto 148:fd96258d940d 3781 /** Peripheral SCT0 base pointer */
Kojto 148:fd96258d940d 3782 #define SCT0 ((SCT_Type *)SCT0_BASE)
Kojto 148:fd96258d940d 3783 /** Array initializer of SCT peripheral base addresses */
Kojto 148:fd96258d940d 3784 #define SCT_BASE_ADDRS { SCT0_BASE }
Kojto 148:fd96258d940d 3785 /** Array initializer of SCT peripheral base pointers */
Kojto 148:fd96258d940d 3786 #define SCT_BASE_PTRS { SCT0 }
Kojto 148:fd96258d940d 3787 /** Interrupt vectors for the SCT peripheral type */
Kojto 148:fd96258d940d 3788 #define SCT_IRQS { SCT0_IRQn }
Kojto 148:fd96258d940d 3789
Kojto 148:fd96258d940d 3790 /*!
Kojto 148:fd96258d940d 3791 * @}
Kojto 148:fd96258d940d 3792 */ /* end of group SCT_Peripheral_Access_Layer */
Kojto 148:fd96258d940d 3793
Kojto 148:fd96258d940d 3794
Kojto 148:fd96258d940d 3795 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 3796 -- SPI Peripheral Access Layer
Kojto 148:fd96258d940d 3797 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 3798
Kojto 148:fd96258d940d 3799 /*!
Kojto 148:fd96258d940d 3800 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
Kojto 148:fd96258d940d 3801 * @{
Kojto 148:fd96258d940d 3802 */
Kojto 148:fd96258d940d 3803
Kojto 148:fd96258d940d 3804 /** SPI - Register Layout Typedef */
Kojto 148:fd96258d940d 3805 typedef struct {
Kojto 148:fd96258d940d 3806 uint8_t RESERVED_0[1024];
Kojto 148:fd96258d940d 3807 __IO uint32_t CFG; /**< SPI Configuration register, offset: 0x400 */
Kojto 148:fd96258d940d 3808 __IO uint32_t DLY; /**< SPI Delay register, offset: 0x404 */
Kojto 148:fd96258d940d 3809 __IO uint32_t STAT; /**< SPI Status. Some status flags can be cleared by writing a 1 to that bit position., offset: 0x408 */
Kojto 148:fd96258d940d 3810 __IO uint32_t INTENSET; /**< SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0x40C */
Kojto 148:fd96258d940d 3811 __O uint32_t INTENCLR; /**< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared., offset: 0x410 */
Kojto 148:fd96258d940d 3812 uint8_t RESERVED_1[16];
Kojto 148:fd96258d940d 3813 __IO uint32_t DIV; /**< SPI clock Divider, offset: 0x424 */
Kojto 148:fd96258d940d 3814 __I uint32_t INTSTAT; /**< SPI Interrupt Status, offset: 0x428 */
Kojto 148:fd96258d940d 3815 uint8_t RESERVED_2[2516];
Kojto 148:fd96258d940d 3816 __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */
Kojto 148:fd96258d940d 3817 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */
Kojto 148:fd96258d940d 3818 __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */
Kojto 148:fd96258d940d 3819 uint8_t RESERVED_3[4];
Kojto 148:fd96258d940d 3820 __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */
Kojto 148:fd96258d940d 3821 __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */
Kojto 148:fd96258d940d 3822 __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */
Kojto 148:fd96258d940d 3823 uint8_t RESERVED_4[4];
Kojto 148:fd96258d940d 3824 __IO uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */
Kojto 148:fd96258d940d 3825 uint8_t RESERVED_5[12];
Kojto 148:fd96258d940d 3826 __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */
Kojto 148:fd96258d940d 3827 uint8_t RESERVED_6[12];
Kojto 148:fd96258d940d 3828 __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */
Kojto 148:fd96258d940d 3829 } SPI_Type;
Kojto 148:fd96258d940d 3830
Kojto 148:fd96258d940d 3831 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 3832 -- SPI Register Masks
Kojto 148:fd96258d940d 3833 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 3834
Kojto 148:fd96258d940d 3835 /*!
Kojto 148:fd96258d940d 3836 * @addtogroup SPI_Register_Masks SPI Register Masks
Kojto 148:fd96258d940d 3837 * @{
Kojto 148:fd96258d940d 3838 */
Kojto 148:fd96258d940d 3839
Kojto 148:fd96258d940d 3840 /*! @name CFG - SPI Configuration register */
Kojto 148:fd96258d940d 3841 #define SPI_CFG_ENABLE_MASK (0x1U)
Kojto 148:fd96258d940d 3842 #define SPI_CFG_ENABLE_SHIFT (0U)
Kojto 148:fd96258d940d 3843 #define SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK)
Kojto 148:fd96258d940d 3844 #define SPI_CFG_MASTER_MASK (0x4U)
Kojto 148:fd96258d940d 3845 #define SPI_CFG_MASTER_SHIFT (2U)
Kojto 148:fd96258d940d 3846 #define SPI_CFG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK)
Kojto 148:fd96258d940d 3847 #define SPI_CFG_LSBF_MASK (0x8U)
Kojto 148:fd96258d940d 3848 #define SPI_CFG_LSBF_SHIFT (3U)
Kojto 148:fd96258d940d 3849 #define SPI_CFG_LSBF(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK)
Kojto 148:fd96258d940d 3850 #define SPI_CFG_CPHA_MASK (0x10U)
Kojto 148:fd96258d940d 3851 #define SPI_CFG_CPHA_SHIFT (4U)
Kojto 148:fd96258d940d 3852 #define SPI_CFG_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK)
Kojto 148:fd96258d940d 3853 #define SPI_CFG_CPOL_MASK (0x20U)
Kojto 148:fd96258d940d 3854 #define SPI_CFG_CPOL_SHIFT (5U)
Kojto 148:fd96258d940d 3855 #define SPI_CFG_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK)
Kojto 148:fd96258d940d 3856 #define SPI_CFG_LOOP_MASK (0x80U)
Kojto 148:fd96258d940d 3857 #define SPI_CFG_LOOP_SHIFT (7U)
Kojto 148:fd96258d940d 3858 #define SPI_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK)
Kojto 148:fd96258d940d 3859 #define SPI_CFG_SPOL0_MASK (0x100U)
Kojto 148:fd96258d940d 3860 #define SPI_CFG_SPOL0_SHIFT (8U)
Kojto 148:fd96258d940d 3861 #define SPI_CFG_SPOL0(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK)
Kojto 148:fd96258d940d 3862 #define SPI_CFG_SPOL1_MASK (0x200U)
Kojto 148:fd96258d940d 3863 #define SPI_CFG_SPOL1_SHIFT (9U)
Kojto 148:fd96258d940d 3864 #define SPI_CFG_SPOL1(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK)
Kojto 148:fd96258d940d 3865 #define SPI_CFG_SPOL2_MASK (0x400U)
Kojto 148:fd96258d940d 3866 #define SPI_CFG_SPOL2_SHIFT (10U)
Kojto 148:fd96258d940d 3867 #define SPI_CFG_SPOL2(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK)
Kojto 148:fd96258d940d 3868 #define SPI_CFG_SPOL3_MASK (0x800U)
Kojto 148:fd96258d940d 3869 #define SPI_CFG_SPOL3_SHIFT (11U)
Kojto 148:fd96258d940d 3870 #define SPI_CFG_SPOL3(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK)
Kojto 148:fd96258d940d 3871
Kojto 148:fd96258d940d 3872 /*! @name DLY - SPI Delay register */
Kojto 148:fd96258d940d 3873 #define SPI_DLY_PRE_DELAY_MASK (0xFU)
Kojto 148:fd96258d940d 3874 #define SPI_DLY_PRE_DELAY_SHIFT (0U)
Kojto 148:fd96258d940d 3875 #define SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK)
Kojto 148:fd96258d940d 3876 #define SPI_DLY_POST_DELAY_MASK (0xF0U)
Kojto 148:fd96258d940d 3877 #define SPI_DLY_POST_DELAY_SHIFT (4U)
Kojto 148:fd96258d940d 3878 #define SPI_DLY_POST_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK)
Kojto 148:fd96258d940d 3879 #define SPI_DLY_FRAME_DELAY_MASK (0xF00U)
Kojto 148:fd96258d940d 3880 #define SPI_DLY_FRAME_DELAY_SHIFT (8U)
Kojto 148:fd96258d940d 3881 #define SPI_DLY_FRAME_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK)
Kojto 148:fd96258d940d 3882 #define SPI_DLY_TRANSFER_DELAY_MASK (0xF000U)
Kojto 148:fd96258d940d 3883 #define SPI_DLY_TRANSFER_DELAY_SHIFT (12U)
Kojto 148:fd96258d940d 3884 #define SPI_DLY_TRANSFER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK)
Kojto 148:fd96258d940d 3885
Kojto 148:fd96258d940d 3886 /*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position. */
Kojto 148:fd96258d940d 3887 #define SPI_STAT_SSA_MASK (0x10U)
Kojto 148:fd96258d940d 3888 #define SPI_STAT_SSA_SHIFT (4U)
Kojto 148:fd96258d940d 3889 #define SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK)
Kojto 148:fd96258d940d 3890 #define SPI_STAT_SSD_MASK (0x20U)
Kojto 148:fd96258d940d 3891 #define SPI_STAT_SSD_SHIFT (5U)
Kojto 148:fd96258d940d 3892 #define SPI_STAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK)
Kojto 148:fd96258d940d 3893 #define SPI_STAT_STALLED_MASK (0x40U)
Kojto 148:fd96258d940d 3894 #define SPI_STAT_STALLED_SHIFT (6U)
Kojto 148:fd96258d940d 3895 #define SPI_STAT_STALLED(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK)
Kojto 148:fd96258d940d 3896 #define SPI_STAT_ENDTRANSFER_MASK (0x80U)
Kojto 148:fd96258d940d 3897 #define SPI_STAT_ENDTRANSFER_SHIFT (7U)
Kojto 148:fd96258d940d 3898 #define SPI_STAT_ENDTRANSFER(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK)
Kojto 148:fd96258d940d 3899 #define SPI_STAT_MSTIDLE_MASK (0x100U)
Kojto 148:fd96258d940d 3900 #define SPI_STAT_MSTIDLE_SHIFT (8U)
Kojto 148:fd96258d940d 3901 #define SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK)
Kojto 148:fd96258d940d 3902
Kojto 148:fd96258d940d 3903 /*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */
Kojto 148:fd96258d940d 3904 #define SPI_INTENSET_SSAEN_MASK (0x10U)
Kojto 148:fd96258d940d 3905 #define SPI_INTENSET_SSAEN_SHIFT (4U)
Kojto 148:fd96258d940d 3906 #define SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK)
Kojto 148:fd96258d940d 3907 #define SPI_INTENSET_SSDEN_MASK (0x20U)
Kojto 148:fd96258d940d 3908 #define SPI_INTENSET_SSDEN_SHIFT (5U)
Kojto 148:fd96258d940d 3909 #define SPI_INTENSET_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK)
Kojto 148:fd96258d940d 3910 #define SPI_INTENSET_MSTIDLEEN_MASK (0x100U)
Kojto 148:fd96258d940d 3911 #define SPI_INTENSET_MSTIDLEEN_SHIFT (8U)
Kojto 148:fd96258d940d 3912 #define SPI_INTENSET_MSTIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK)
Kojto 148:fd96258d940d 3913
Kojto 148:fd96258d940d 3914 /*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */
Kojto 148:fd96258d940d 3915 #define SPI_INTENCLR_SSAEN_MASK (0x10U)
Kojto 148:fd96258d940d 3916 #define SPI_INTENCLR_SSAEN_SHIFT (4U)
Kojto 148:fd96258d940d 3917 #define SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK)
Kojto 148:fd96258d940d 3918 #define SPI_INTENCLR_SSDEN_MASK (0x20U)
Kojto 148:fd96258d940d 3919 #define SPI_INTENCLR_SSDEN_SHIFT (5U)
Kojto 148:fd96258d940d 3920 #define SPI_INTENCLR_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK)
Kojto 148:fd96258d940d 3921 #define SPI_INTENCLR_MSTIDLE_MASK (0x100U)
Kojto 148:fd96258d940d 3922 #define SPI_INTENCLR_MSTIDLE_SHIFT (8U)
Kojto 148:fd96258d940d 3923 #define SPI_INTENCLR_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK)
Kojto 148:fd96258d940d 3924
Kojto 148:fd96258d940d 3925 /*! @name DIV - SPI clock Divider */
Kojto 148:fd96258d940d 3926 #define SPI_DIV_DIVVAL_MASK (0xFFFFU)
Kojto 148:fd96258d940d 3927 #define SPI_DIV_DIVVAL_SHIFT (0U)
Kojto 148:fd96258d940d 3928 #define SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK)
Kojto 148:fd96258d940d 3929
Kojto 148:fd96258d940d 3930 /*! @name INTSTAT - SPI Interrupt Status */
Kojto 148:fd96258d940d 3931 #define SPI_INTSTAT_SSA_MASK (0x10U)
Kojto 148:fd96258d940d 3932 #define SPI_INTSTAT_SSA_SHIFT (4U)
Kojto 148:fd96258d940d 3933 #define SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK)
Kojto 148:fd96258d940d 3934 #define SPI_INTSTAT_SSD_MASK (0x20U)
Kojto 148:fd96258d940d 3935 #define SPI_INTSTAT_SSD_SHIFT (5U)
Kojto 148:fd96258d940d 3936 #define SPI_INTSTAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK)
Kojto 148:fd96258d940d 3937 #define SPI_INTSTAT_MSTIDLE_MASK (0x100U)
Kojto 148:fd96258d940d 3938 #define SPI_INTSTAT_MSTIDLE_SHIFT (8U)
Kojto 148:fd96258d940d 3939 #define SPI_INTSTAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK)
Kojto 148:fd96258d940d 3940
Kojto 148:fd96258d940d 3941 /*! @name FIFOCFG - FIFO configuration and enable register. */
Kojto 148:fd96258d940d 3942 #define SPI_FIFOCFG_ENABLETX_MASK (0x1U)
Kojto 148:fd96258d940d 3943 #define SPI_FIFOCFG_ENABLETX_SHIFT (0U)
Kojto 148:fd96258d940d 3944 #define SPI_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK)
Kojto 148:fd96258d940d 3945 #define SPI_FIFOCFG_ENABLERX_MASK (0x2U)
Kojto 148:fd96258d940d 3946 #define SPI_FIFOCFG_ENABLERX_SHIFT (1U)
Kojto 148:fd96258d940d 3947 #define SPI_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK)
Kojto 148:fd96258d940d 3948 #define SPI_FIFOCFG_SIZE_MASK (0x30U)
Kojto 148:fd96258d940d 3949 #define SPI_FIFOCFG_SIZE_SHIFT (4U)
Kojto 148:fd96258d940d 3950 #define SPI_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK)
Kojto 148:fd96258d940d 3951 #define SPI_FIFOCFG_DMATX_MASK (0x1000U)
Kojto 148:fd96258d940d 3952 #define SPI_FIFOCFG_DMATX_SHIFT (12U)
Kojto 148:fd96258d940d 3953 #define SPI_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK)
Kojto 148:fd96258d940d 3954 #define SPI_FIFOCFG_DMARX_MASK (0x2000U)
Kojto 148:fd96258d940d 3955 #define SPI_FIFOCFG_DMARX_SHIFT (13U)
Kojto 148:fd96258d940d 3956 #define SPI_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK)
Kojto 148:fd96258d940d 3957 #define SPI_FIFOCFG_WAKETX_MASK (0x4000U)
Kojto 148:fd96258d940d 3958 #define SPI_FIFOCFG_WAKETX_SHIFT (14U)
Kojto 148:fd96258d940d 3959 #define SPI_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK)
Kojto 148:fd96258d940d 3960 #define SPI_FIFOCFG_WAKERX_MASK (0x8000U)
Kojto 148:fd96258d940d 3961 #define SPI_FIFOCFG_WAKERX_SHIFT (15U)
Kojto 148:fd96258d940d 3962 #define SPI_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK)
Kojto 148:fd96258d940d 3963 #define SPI_FIFOCFG_EMPTYTX_MASK (0x10000U)
Kojto 148:fd96258d940d 3964 #define SPI_FIFOCFG_EMPTYTX_SHIFT (16U)
Kojto 148:fd96258d940d 3965 #define SPI_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK)
Kojto 148:fd96258d940d 3966 #define SPI_FIFOCFG_EMPTYRX_MASK (0x20000U)
Kojto 148:fd96258d940d 3967 #define SPI_FIFOCFG_EMPTYRX_SHIFT (17U)
Kojto 148:fd96258d940d 3968 #define SPI_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK)
Kojto 148:fd96258d940d 3969
Kojto 148:fd96258d940d 3970 /*! @name FIFOSTAT - FIFO status register. */
Kojto 148:fd96258d940d 3971 #define SPI_FIFOSTAT_TXERR_MASK (0x1U)
Kojto 148:fd96258d940d 3972 #define SPI_FIFOSTAT_TXERR_SHIFT (0U)
Kojto 148:fd96258d940d 3973 #define SPI_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK)
Kojto 148:fd96258d940d 3974 #define SPI_FIFOSTAT_RXERR_MASK (0x2U)
Kojto 148:fd96258d940d 3975 #define SPI_FIFOSTAT_RXERR_SHIFT (1U)
Kojto 148:fd96258d940d 3976 #define SPI_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK)
Kojto 148:fd96258d940d 3977 #define SPI_FIFOSTAT_PERINT_MASK (0x8U)
Kojto 148:fd96258d940d 3978 #define SPI_FIFOSTAT_PERINT_SHIFT (3U)
Kojto 148:fd96258d940d 3979 #define SPI_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK)
Kojto 148:fd96258d940d 3980 #define SPI_FIFOSTAT_TXEMPTY_MASK (0x10U)
Kojto 148:fd96258d940d 3981 #define SPI_FIFOSTAT_TXEMPTY_SHIFT (4U)
Kojto 148:fd96258d940d 3982 #define SPI_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK)
Kojto 148:fd96258d940d 3983 #define SPI_FIFOSTAT_TXNOTFULL_MASK (0x20U)
Kojto 148:fd96258d940d 3984 #define SPI_FIFOSTAT_TXNOTFULL_SHIFT (5U)
Kojto 148:fd96258d940d 3985 #define SPI_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK)
Kojto 148:fd96258d940d 3986 #define SPI_FIFOSTAT_RXNOTEMPTY_MASK (0x40U)
Kojto 148:fd96258d940d 3987 #define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT (6U)
Kojto 148:fd96258d940d 3988 #define SPI_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK)
Kojto 148:fd96258d940d 3989 #define SPI_FIFOSTAT_RXFULL_MASK (0x80U)
Kojto 148:fd96258d940d 3990 #define SPI_FIFOSTAT_RXFULL_SHIFT (7U)
Kojto 148:fd96258d940d 3991 #define SPI_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK)
Kojto 148:fd96258d940d 3992 #define SPI_FIFOSTAT_TXLVL_MASK (0x1F00U)
Kojto 148:fd96258d940d 3993 #define SPI_FIFOSTAT_TXLVL_SHIFT (8U)
Kojto 148:fd96258d940d 3994 #define SPI_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK)
Kojto 148:fd96258d940d 3995 #define SPI_FIFOSTAT_RXLVL_MASK (0x1F0000U)
Kojto 148:fd96258d940d 3996 #define SPI_FIFOSTAT_RXLVL_SHIFT (16U)
Kojto 148:fd96258d940d 3997 #define SPI_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK)
Kojto 148:fd96258d940d 3998
Kojto 148:fd96258d940d 3999 /*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */
Kojto 148:fd96258d940d 4000 #define SPI_FIFOTRIG_TXLVLENA_MASK (0x1U)
Kojto 148:fd96258d940d 4001 #define SPI_FIFOTRIG_TXLVLENA_SHIFT (0U)
Kojto 148:fd96258d940d 4002 #define SPI_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK)
Kojto 148:fd96258d940d 4003 #define SPI_FIFOTRIG_RXLVLENA_MASK (0x2U)
Kojto 148:fd96258d940d 4004 #define SPI_FIFOTRIG_RXLVLENA_SHIFT (1U)
Kojto 148:fd96258d940d 4005 #define SPI_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK)
Kojto 148:fd96258d940d 4006 #define SPI_FIFOTRIG_TXLVL_MASK (0xF00U)
Kojto 148:fd96258d940d 4007 #define SPI_FIFOTRIG_TXLVL_SHIFT (8U)
Kojto 148:fd96258d940d 4008 #define SPI_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK)
Kojto 148:fd96258d940d 4009 #define SPI_FIFOTRIG_RXLVL_MASK (0xF0000U)
Kojto 148:fd96258d940d 4010 #define SPI_FIFOTRIG_RXLVL_SHIFT (16U)
Kojto 148:fd96258d940d 4011 #define SPI_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK)
Kojto 148:fd96258d940d 4012
Kojto 148:fd96258d940d 4013 /*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */
Kojto 148:fd96258d940d 4014 #define SPI_FIFOINTENSET_TXERR_MASK (0x1U)
Kojto 148:fd96258d940d 4015 #define SPI_FIFOINTENSET_TXERR_SHIFT (0U)
Kojto 148:fd96258d940d 4016 #define SPI_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK)
Kojto 148:fd96258d940d 4017 #define SPI_FIFOINTENSET_RXERR_MASK (0x2U)
Kojto 148:fd96258d940d 4018 #define SPI_FIFOINTENSET_RXERR_SHIFT (1U)
Kojto 148:fd96258d940d 4019 #define SPI_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK)
Kojto 148:fd96258d940d 4020 #define SPI_FIFOINTENSET_TXLVL_MASK (0x4U)
Kojto 148:fd96258d940d 4021 #define SPI_FIFOINTENSET_TXLVL_SHIFT (2U)
Kojto 148:fd96258d940d 4022 #define SPI_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK)
Kojto 148:fd96258d940d 4023 #define SPI_FIFOINTENSET_RXLVL_MASK (0x8U)
Kojto 148:fd96258d940d 4024 #define SPI_FIFOINTENSET_RXLVL_SHIFT (3U)
Kojto 148:fd96258d940d 4025 #define SPI_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK)
Kojto 148:fd96258d940d 4026
Kojto 148:fd96258d940d 4027 /*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */
Kojto 148:fd96258d940d 4028 #define SPI_FIFOINTENCLR_TXERR_MASK (0x1U)
Kojto 148:fd96258d940d 4029 #define SPI_FIFOINTENCLR_TXERR_SHIFT (0U)
Kojto 148:fd96258d940d 4030 #define SPI_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK)
Kojto 148:fd96258d940d 4031 #define SPI_FIFOINTENCLR_RXERR_MASK (0x2U)
Kojto 148:fd96258d940d 4032 #define SPI_FIFOINTENCLR_RXERR_SHIFT (1U)
Kojto 148:fd96258d940d 4033 #define SPI_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK)
Kojto 148:fd96258d940d 4034 #define SPI_FIFOINTENCLR_TXLVL_MASK (0x4U)
Kojto 148:fd96258d940d 4035 #define SPI_FIFOINTENCLR_TXLVL_SHIFT (2U)
Kojto 148:fd96258d940d 4036 #define SPI_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK)
Kojto 148:fd96258d940d 4037 #define SPI_FIFOINTENCLR_RXLVL_MASK (0x8U)
Kojto 148:fd96258d940d 4038 #define SPI_FIFOINTENCLR_RXLVL_SHIFT (3U)
Kojto 148:fd96258d940d 4039 #define SPI_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK)
Kojto 148:fd96258d940d 4040
Kojto 148:fd96258d940d 4041 /*! @name FIFOINTSTAT - FIFO interrupt status register. */
Kojto 148:fd96258d940d 4042 #define SPI_FIFOINTSTAT_TXERR_MASK (0x1U)
Kojto 148:fd96258d940d 4043 #define SPI_FIFOINTSTAT_TXERR_SHIFT (0U)
Kojto 148:fd96258d940d 4044 #define SPI_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK)
Kojto 148:fd96258d940d 4045 #define SPI_FIFOINTSTAT_RXERR_MASK (0x2U)
Kojto 148:fd96258d940d 4046 #define SPI_FIFOINTSTAT_RXERR_SHIFT (1U)
Kojto 148:fd96258d940d 4047 #define SPI_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK)
Kojto 148:fd96258d940d 4048 #define SPI_FIFOINTSTAT_TXLVL_MASK (0x4U)
Kojto 148:fd96258d940d 4049 #define SPI_FIFOINTSTAT_TXLVL_SHIFT (2U)
Kojto 148:fd96258d940d 4050 #define SPI_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK)
Kojto 148:fd96258d940d 4051 #define SPI_FIFOINTSTAT_RXLVL_MASK (0x8U)
Kojto 148:fd96258d940d 4052 #define SPI_FIFOINTSTAT_RXLVL_SHIFT (3U)
Kojto 148:fd96258d940d 4053 #define SPI_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK)
Kojto 148:fd96258d940d 4054 #define SPI_FIFOINTSTAT_PERINT_MASK (0x10U)
Kojto 148:fd96258d940d 4055 #define SPI_FIFOINTSTAT_PERINT_SHIFT (4U)
Kojto 148:fd96258d940d 4056 #define SPI_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK)
Kojto 148:fd96258d940d 4057
Kojto 148:fd96258d940d 4058 /*! @name FIFOWR - FIFO write data. */
Kojto 148:fd96258d940d 4059 #define SPI_FIFOWR_TXDATA_MASK (0xFFFFU)
Kojto 148:fd96258d940d 4060 #define SPI_FIFOWR_TXDATA_SHIFT (0U)
Kojto 148:fd96258d940d 4061 #define SPI_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK)
Kojto 148:fd96258d940d 4062 #define SPI_FIFOWR_TXSSEL0_N_MASK (0x10000U)
Kojto 148:fd96258d940d 4063 #define SPI_FIFOWR_TXSSEL0_N_SHIFT (16U)
Kojto 148:fd96258d940d 4064 #define SPI_FIFOWR_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK)
Kojto 148:fd96258d940d 4065 #define SPI_FIFOWR_TXSSEL1_N_MASK (0x20000U)
Kojto 148:fd96258d940d 4066 #define SPI_FIFOWR_TXSSEL1_N_SHIFT (17U)
Kojto 148:fd96258d940d 4067 #define SPI_FIFOWR_TXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK)
Kojto 148:fd96258d940d 4068 #define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U)
Kojto 148:fd96258d940d 4069 #define SPI_FIFOWR_TXSSEL2_N_SHIFT (18U)
Kojto 148:fd96258d940d 4070 #define SPI_FIFOWR_TXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK)
Kojto 148:fd96258d940d 4071 #define SPI_FIFOWR_TXSSEL3_N_MASK (0x80000U)
Kojto 148:fd96258d940d 4072 #define SPI_FIFOWR_TXSSEL3_N_SHIFT (19U)
Kojto 148:fd96258d940d 4073 #define SPI_FIFOWR_TXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK)
Kojto 148:fd96258d940d 4074 #define SPI_FIFOWR_EOT_MASK (0x100000U)
Kojto 148:fd96258d940d 4075 #define SPI_FIFOWR_EOT_SHIFT (20U)
Kojto 148:fd96258d940d 4076 #define SPI_FIFOWR_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK)
Kojto 148:fd96258d940d 4077 #define SPI_FIFOWR_EOF_MASK (0x200000U)
Kojto 148:fd96258d940d 4078 #define SPI_FIFOWR_EOF_SHIFT (21U)
Kojto 148:fd96258d940d 4079 #define SPI_FIFOWR_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK)
Kojto 148:fd96258d940d 4080 #define SPI_FIFOWR_RXIGNORE_MASK (0x400000U)
Kojto 148:fd96258d940d 4081 #define SPI_FIFOWR_RXIGNORE_SHIFT (22U)
Kojto 148:fd96258d940d 4082 #define SPI_FIFOWR_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK)
Kojto 148:fd96258d940d 4083 #define SPI_FIFOWR_LEN_MASK (0xF000000U)
Kojto 148:fd96258d940d 4084 #define SPI_FIFOWR_LEN_SHIFT (24U)
Kojto 148:fd96258d940d 4085 #define SPI_FIFOWR_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK)
Kojto 148:fd96258d940d 4086
Kojto 148:fd96258d940d 4087 /*! @name FIFORD - FIFO read data. */
Kojto 148:fd96258d940d 4088 #define SPI_FIFORD_RXDATA_MASK (0xFFFFU)
Kojto 148:fd96258d940d 4089 #define SPI_FIFORD_RXDATA_SHIFT (0U)
Kojto 148:fd96258d940d 4090 #define SPI_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK)
Kojto 148:fd96258d940d 4091 #define SPI_FIFORD_RXSSEL0_N_MASK (0x10000U)
Kojto 148:fd96258d940d 4092 #define SPI_FIFORD_RXSSEL0_N_SHIFT (16U)
Kojto 148:fd96258d940d 4093 #define SPI_FIFORD_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK)
Kojto 148:fd96258d940d 4094 #define SPI_FIFORD_RXSSEL1_N_MASK (0x20000U)
Kojto 148:fd96258d940d 4095 #define SPI_FIFORD_RXSSEL1_N_SHIFT (17U)
Kojto 148:fd96258d940d 4096 #define SPI_FIFORD_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK)
Kojto 148:fd96258d940d 4097 #define SPI_FIFORD_RXSSEL2_N_MASK (0x40000U)
Kojto 148:fd96258d940d 4098 #define SPI_FIFORD_RXSSEL2_N_SHIFT (18U)
Kojto 148:fd96258d940d 4099 #define SPI_FIFORD_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK)
Kojto 148:fd96258d940d 4100 #define SPI_FIFORD_RXSSEL3_N_MASK (0x80000U)
Kojto 148:fd96258d940d 4101 #define SPI_FIFORD_RXSSEL3_N_SHIFT (19U)
Kojto 148:fd96258d940d 4102 #define SPI_FIFORD_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK)
Kojto 148:fd96258d940d 4103 #define SPI_FIFORD_SOT_MASK (0x100000U)
Kojto 148:fd96258d940d 4104 #define SPI_FIFORD_SOT_SHIFT (20U)
Kojto 148:fd96258d940d 4105 #define SPI_FIFORD_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK)
Kojto 148:fd96258d940d 4106
Kojto 148:fd96258d940d 4107 /*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */
Kojto 148:fd96258d940d 4108 #define SPI_FIFORDNOPOP_RXDATA_MASK (0xFFFFU)
Kojto 148:fd96258d940d 4109 #define SPI_FIFORDNOPOP_RXDATA_SHIFT (0U)
Kojto 148:fd96258d940d 4110 #define SPI_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK)
Kojto 148:fd96258d940d 4111 #define SPI_FIFORDNOPOP_RXSSEL0_N_MASK (0x10000U)
Kojto 148:fd96258d940d 4112 #define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT (16U)
Kojto 148:fd96258d940d 4113 #define SPI_FIFORDNOPOP_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK)
Kojto 148:fd96258d940d 4114 #define SPI_FIFORDNOPOP_RXSSEL1_N_MASK (0x20000U)
Kojto 148:fd96258d940d 4115 #define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT (17U)
Kojto 148:fd96258d940d 4116 #define SPI_FIFORDNOPOP_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK)
Kojto 148:fd96258d940d 4117 #define SPI_FIFORDNOPOP_RXSSEL2_N_MASK (0x40000U)
Kojto 148:fd96258d940d 4118 #define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT (18U)
Kojto 148:fd96258d940d 4119 #define SPI_FIFORDNOPOP_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK)
Kojto 148:fd96258d940d 4120 #define SPI_FIFORDNOPOP_RXSSEL3_N_MASK (0x80000U)
Kojto 148:fd96258d940d 4121 #define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT (19U)
Kojto 148:fd96258d940d 4122 #define SPI_FIFORDNOPOP_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK)
Kojto 148:fd96258d940d 4123 #define SPI_FIFORDNOPOP_SOT_MASK (0x100000U)
Kojto 148:fd96258d940d 4124 #define SPI_FIFORDNOPOP_SOT_SHIFT (20U)
Kojto 148:fd96258d940d 4125 #define SPI_FIFORDNOPOP_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK)
Kojto 148:fd96258d940d 4126
Kojto 148:fd96258d940d 4127
Kojto 148:fd96258d940d 4128 /*!
Kojto 148:fd96258d940d 4129 * @}
Kojto 148:fd96258d940d 4130 */ /* end of group SPI_Register_Masks */
Kojto 148:fd96258d940d 4131
Kojto 148:fd96258d940d 4132
Kojto 148:fd96258d940d 4133 /* SPI - Peripheral instance base addresses */
Kojto 148:fd96258d940d 4134 /** Peripheral SPI0 base address */
Kojto 148:fd96258d940d 4135 #define SPI0_BASE (0x40086000u)
Kojto 148:fd96258d940d 4136 /** Peripheral SPI0 base pointer */
Kojto 148:fd96258d940d 4137 #define SPI0 ((SPI_Type *)SPI0_BASE)
Kojto 148:fd96258d940d 4138 /** Peripheral SPI1 base address */
Kojto 148:fd96258d940d 4139 #define SPI1_BASE (0x40087000u)
Kojto 148:fd96258d940d 4140 /** Peripheral SPI1 base pointer */
Kojto 148:fd96258d940d 4141 #define SPI1 ((SPI_Type *)SPI1_BASE)
Kojto 148:fd96258d940d 4142 /** Peripheral SPI2 base address */
Kojto 148:fd96258d940d 4143 #define SPI2_BASE (0x40088000u)
Kojto 148:fd96258d940d 4144 /** Peripheral SPI2 base pointer */
Kojto 148:fd96258d940d 4145 #define SPI2 ((SPI_Type *)SPI2_BASE)
Kojto 148:fd96258d940d 4146 /** Peripheral SPI3 base address */
Kojto 148:fd96258d940d 4147 #define SPI3_BASE (0x40089000u)
Kojto 148:fd96258d940d 4148 /** Peripheral SPI3 base pointer */
Kojto 148:fd96258d940d 4149 #define SPI3 ((SPI_Type *)SPI3_BASE)
Kojto 148:fd96258d940d 4150 /** Peripheral SPI4 base address */
Kojto 148:fd96258d940d 4151 #define SPI4_BASE (0x4008A000u)
Kojto 148:fd96258d940d 4152 /** Peripheral SPI4 base pointer */
Kojto 148:fd96258d940d 4153 #define SPI4 ((SPI_Type *)SPI4_BASE)
Kojto 148:fd96258d940d 4154 /** Peripheral SPI5 base address */
Kojto 148:fd96258d940d 4155 #define SPI5_BASE (0x40096000u)
Kojto 148:fd96258d940d 4156 /** Peripheral SPI5 base pointer */
Kojto 148:fd96258d940d 4157 #define SPI5 ((SPI_Type *)SPI5_BASE)
Kojto 148:fd96258d940d 4158 /** Peripheral SPI6 base address */
Kojto 148:fd96258d940d 4159 #define SPI6_BASE (0x40097000u)
Kojto 148:fd96258d940d 4160 /** Peripheral SPI6 base pointer */
Kojto 148:fd96258d940d 4161 #define SPI6 ((SPI_Type *)SPI6_BASE)
Kojto 148:fd96258d940d 4162 /** Peripheral SPI7 base address */
Kojto 148:fd96258d940d 4163 #define SPI7_BASE (0x40098000u)
Kojto 148:fd96258d940d 4164 /** Peripheral SPI7 base pointer */
Kojto 148:fd96258d940d 4165 #define SPI7 ((SPI_Type *)SPI7_BASE)
Kojto 148:fd96258d940d 4166 /** Array initializer of SPI peripheral base addresses */
Kojto 148:fd96258d940d 4167 #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE }
Kojto 148:fd96258d940d 4168 /** Array initializer of SPI peripheral base pointers */
Kojto 148:fd96258d940d 4169 #define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7 }
Kojto 148:fd96258d940d 4170 /** Interrupt vectors for the SPI peripheral type */
Kojto 148:fd96258d940d 4171 #define SPI_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn }
Kojto 148:fd96258d940d 4172
Kojto 148:fd96258d940d 4173 /*!
Kojto 148:fd96258d940d 4174 * @}
Kojto 148:fd96258d940d 4175 */ /* end of group SPI_Peripheral_Access_Layer */
Kojto 148:fd96258d940d 4176
Kojto 148:fd96258d940d 4177
Kojto 148:fd96258d940d 4178 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 4179 -- SPIFI Peripheral Access Layer
Kojto 148:fd96258d940d 4180 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 4181
Kojto 148:fd96258d940d 4182 /*!
Kojto 148:fd96258d940d 4183 * @addtogroup SPIFI_Peripheral_Access_Layer SPIFI Peripheral Access Layer
Kojto 148:fd96258d940d 4184 * @{
Kojto 148:fd96258d940d 4185 */
Kojto 148:fd96258d940d 4186
Kojto 148:fd96258d940d 4187 /** SPIFI - Register Layout Typedef */
Kojto 148:fd96258d940d 4188 typedef struct {
Kojto 148:fd96258d940d 4189 __IO uint32_t CTRL; /**< SPIFI control register, offset: 0x0 */
Kojto 148:fd96258d940d 4190 __IO uint32_t CMD; /**< SPIFI command register, offset: 0x4 */
Kojto 148:fd96258d940d 4191 __IO uint32_t ADDR; /**< SPIFI address register, offset: 0x8 */
Kojto 148:fd96258d940d 4192 __IO uint32_t IDATA; /**< SPIFI intermediate data register, offset: 0xC */
Kojto 148:fd96258d940d 4193 __IO uint32_t CLIMIT; /**< SPIFI limit register, offset: 0x10 */
Kojto 148:fd96258d940d 4194 __IO uint32_t DATA; /**< SPIFI data register, offset: 0x14 */
Kojto 148:fd96258d940d 4195 __IO uint32_t MCMD; /**< SPIFI memory command register, offset: 0x18 */
Kojto 148:fd96258d940d 4196 __IO uint32_t STAT; /**< SPIFI status register, offset: 0x1C */
Kojto 148:fd96258d940d 4197 } SPIFI_Type;
Kojto 148:fd96258d940d 4198
Kojto 148:fd96258d940d 4199 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 4200 -- SPIFI Register Masks
Kojto 148:fd96258d940d 4201 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 4202
Kojto 148:fd96258d940d 4203 /*!
Kojto 148:fd96258d940d 4204 * @addtogroup SPIFI_Register_Masks SPIFI Register Masks
Kojto 148:fd96258d940d 4205 * @{
Kojto 148:fd96258d940d 4206 */
Kojto 148:fd96258d940d 4207
Kojto 148:fd96258d940d 4208 /*! @name CTRL - SPIFI control register */
Kojto 148:fd96258d940d 4209 #define SPIFI_CTRL_TIMEOUT_MASK (0xFFFFU)
Kojto 148:fd96258d940d 4210 #define SPIFI_CTRL_TIMEOUT_SHIFT (0U)
Kojto 148:fd96258d940d 4211 #define SPIFI_CTRL_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_TIMEOUT_SHIFT)) & SPIFI_CTRL_TIMEOUT_MASK)
Kojto 148:fd96258d940d 4212 #define SPIFI_CTRL_CSHIGH_MASK (0xF0000U)
Kojto 148:fd96258d940d 4213 #define SPIFI_CTRL_CSHIGH_SHIFT (16U)
Kojto 148:fd96258d940d 4214 #define SPIFI_CTRL_CSHIGH(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_CSHIGH_SHIFT)) & SPIFI_CTRL_CSHIGH_MASK)
Kojto 148:fd96258d940d 4215 #define SPIFI_CTRL_D_PRFTCH_DIS_MASK (0x200000U)
Kojto 148:fd96258d940d 4216 #define SPIFI_CTRL_D_PRFTCH_DIS_SHIFT (21U)
Kojto 148:fd96258d940d 4217 #define SPIFI_CTRL_D_PRFTCH_DIS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_D_PRFTCH_DIS_SHIFT)) & SPIFI_CTRL_D_PRFTCH_DIS_MASK)
Kojto 148:fd96258d940d 4218 #define SPIFI_CTRL_INTEN_MASK (0x400000U)
Kojto 148:fd96258d940d 4219 #define SPIFI_CTRL_INTEN_SHIFT (22U)
Kojto 148:fd96258d940d 4220 #define SPIFI_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_INTEN_SHIFT)) & SPIFI_CTRL_INTEN_MASK)
Kojto 148:fd96258d940d 4221 #define SPIFI_CTRL_MODE3_MASK (0x800000U)
Kojto 148:fd96258d940d 4222 #define SPIFI_CTRL_MODE3_SHIFT (23U)
Kojto 148:fd96258d940d 4223 #define SPIFI_CTRL_MODE3(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_MODE3_SHIFT)) & SPIFI_CTRL_MODE3_MASK)
Kojto 148:fd96258d940d 4224 #define SPIFI_CTRL_PRFTCH_DIS_MASK (0x8000000U)
Kojto 148:fd96258d940d 4225 #define SPIFI_CTRL_PRFTCH_DIS_SHIFT (27U)
Kojto 148:fd96258d940d 4226 #define SPIFI_CTRL_PRFTCH_DIS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_PRFTCH_DIS_SHIFT)) & SPIFI_CTRL_PRFTCH_DIS_MASK)
Kojto 148:fd96258d940d 4227 #define SPIFI_CTRL_DUAL_MASK (0x10000000U)
Kojto 148:fd96258d940d 4228 #define SPIFI_CTRL_DUAL_SHIFT (28U)
Kojto 148:fd96258d940d 4229 #define SPIFI_CTRL_DUAL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_DUAL_SHIFT)) & SPIFI_CTRL_DUAL_MASK)
Kojto 148:fd96258d940d 4230 #define SPIFI_CTRL_RFCLK_MASK (0x20000000U)
Kojto 148:fd96258d940d 4231 #define SPIFI_CTRL_RFCLK_SHIFT (29U)
Kojto 148:fd96258d940d 4232 #define SPIFI_CTRL_RFCLK(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_RFCLK_SHIFT)) & SPIFI_CTRL_RFCLK_MASK)
Kojto 148:fd96258d940d 4233 #define SPIFI_CTRL_FBCLK_MASK (0x40000000U)
Kojto 148:fd96258d940d 4234 #define SPIFI_CTRL_FBCLK_SHIFT (30U)
Kojto 148:fd96258d940d 4235 #define SPIFI_CTRL_FBCLK(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_FBCLK_SHIFT)) & SPIFI_CTRL_FBCLK_MASK)
Kojto 148:fd96258d940d 4236 #define SPIFI_CTRL_DMAEN_MASK (0x80000000U)
Kojto 148:fd96258d940d 4237 #define SPIFI_CTRL_DMAEN_SHIFT (31U)
Kojto 148:fd96258d940d 4238 #define SPIFI_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_DMAEN_SHIFT)) & SPIFI_CTRL_DMAEN_MASK)
Kojto 148:fd96258d940d 4239
Kojto 148:fd96258d940d 4240 /*! @name CMD - SPIFI command register */
Kojto 148:fd96258d940d 4241 #define SPIFI_CMD_DATALEN_MASK (0x3FFFU)
Kojto 148:fd96258d940d 4242 #define SPIFI_CMD_DATALEN_SHIFT (0U)
Kojto 148:fd96258d940d 4243 #define SPIFI_CMD_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_DATALEN_SHIFT)) & SPIFI_CMD_DATALEN_MASK)
Kojto 148:fd96258d940d 4244 #define SPIFI_CMD_POLL_MASK (0x4000U)
Kojto 148:fd96258d940d 4245 #define SPIFI_CMD_POLL_SHIFT (14U)
Kojto 148:fd96258d940d 4246 #define SPIFI_CMD_POLL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_POLL_SHIFT)) & SPIFI_CMD_POLL_MASK)
Kojto 148:fd96258d940d 4247 #define SPIFI_CMD_DOUT_MASK (0x8000U)
Kojto 148:fd96258d940d 4248 #define SPIFI_CMD_DOUT_SHIFT (15U)
Kojto 148:fd96258d940d 4249 #define SPIFI_CMD_DOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_DOUT_SHIFT)) & SPIFI_CMD_DOUT_MASK)
Kojto 148:fd96258d940d 4250 #define SPIFI_CMD_INTLEN_MASK (0x70000U)
Kojto 148:fd96258d940d 4251 #define SPIFI_CMD_INTLEN_SHIFT (16U)
Kojto 148:fd96258d940d 4252 #define SPIFI_CMD_INTLEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_INTLEN_SHIFT)) & SPIFI_CMD_INTLEN_MASK)
Kojto 148:fd96258d940d 4253 #define SPIFI_CMD_FIELDFORM_MASK (0x180000U)
Kojto 148:fd96258d940d 4254 #define SPIFI_CMD_FIELDFORM_SHIFT (19U)
Kojto 148:fd96258d940d 4255 #define SPIFI_CMD_FIELDFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_FIELDFORM_SHIFT)) & SPIFI_CMD_FIELDFORM_MASK)
Kojto 148:fd96258d940d 4256 #define SPIFI_CMD_FRAMEFORM_MASK (0xE00000U)
Kojto 148:fd96258d940d 4257 #define SPIFI_CMD_FRAMEFORM_SHIFT (21U)
Kojto 148:fd96258d940d 4258 #define SPIFI_CMD_FRAMEFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_FRAMEFORM_SHIFT)) & SPIFI_CMD_FRAMEFORM_MASK)
Kojto 148:fd96258d940d 4259 #define SPIFI_CMD_OPCODE_MASK (0xFF000000U)
Kojto 148:fd96258d940d 4260 #define SPIFI_CMD_OPCODE_SHIFT (24U)
Kojto 148:fd96258d940d 4261 #define SPIFI_CMD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_OPCODE_SHIFT)) & SPIFI_CMD_OPCODE_MASK)
Kojto 148:fd96258d940d 4262
Kojto 148:fd96258d940d 4263 /*! @name ADDR - SPIFI address register */
Kojto 148:fd96258d940d 4264 #define SPIFI_ADDR_ADDRESS_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 4265 #define SPIFI_ADDR_ADDRESS_SHIFT (0U)
Kojto 148:fd96258d940d 4266 #define SPIFI_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_ADDR_ADDRESS_SHIFT)) & SPIFI_ADDR_ADDRESS_MASK)
Kojto 148:fd96258d940d 4267
Kojto 148:fd96258d940d 4268 /*! @name IDATA - SPIFI intermediate data register */
Kojto 148:fd96258d940d 4269 #define SPIFI_IDATA_IDATA_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 4270 #define SPIFI_IDATA_IDATA_SHIFT (0U)
Kojto 148:fd96258d940d 4271 #define SPIFI_IDATA_IDATA(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_IDATA_IDATA_SHIFT)) & SPIFI_IDATA_IDATA_MASK)
Kojto 148:fd96258d940d 4272
Kojto 148:fd96258d940d 4273 /*! @name CLIMIT - SPIFI limit register */
Kojto 148:fd96258d940d 4274 #define SPIFI_CLIMIT_CLIMIT_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 4275 #define SPIFI_CLIMIT_CLIMIT_SHIFT (0U)
Kojto 148:fd96258d940d 4276 #define SPIFI_CLIMIT_CLIMIT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CLIMIT_CLIMIT_SHIFT)) & SPIFI_CLIMIT_CLIMIT_MASK)
Kojto 148:fd96258d940d 4277
Kojto 148:fd96258d940d 4278 /*! @name DATA - SPIFI data register */
Kojto 148:fd96258d940d 4279 #define SPIFI_DATA_DATA_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 4280 #define SPIFI_DATA_DATA_SHIFT (0U)
Kojto 148:fd96258d940d 4281 #define SPIFI_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_DATA_DATA_SHIFT)) & SPIFI_DATA_DATA_MASK)
Kojto 148:fd96258d940d 4282
Kojto 148:fd96258d940d 4283 /*! @name MCMD - SPIFI memory command register */
Kojto 148:fd96258d940d 4284 #define SPIFI_MCMD_POLL_MASK (0x4000U)
Kojto 148:fd96258d940d 4285 #define SPIFI_MCMD_POLL_SHIFT (14U)
Kojto 148:fd96258d940d 4286 #define SPIFI_MCMD_POLL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_POLL_SHIFT)) & SPIFI_MCMD_POLL_MASK)
Kojto 148:fd96258d940d 4287 #define SPIFI_MCMD_DOUT_MASK (0x8000U)
Kojto 148:fd96258d940d 4288 #define SPIFI_MCMD_DOUT_SHIFT (15U)
Kojto 148:fd96258d940d 4289 #define SPIFI_MCMD_DOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_DOUT_SHIFT)) & SPIFI_MCMD_DOUT_MASK)
Kojto 148:fd96258d940d 4290 #define SPIFI_MCMD_INTLEN_MASK (0x70000U)
Kojto 148:fd96258d940d 4291 #define SPIFI_MCMD_INTLEN_SHIFT (16U)
Kojto 148:fd96258d940d 4292 #define SPIFI_MCMD_INTLEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_INTLEN_SHIFT)) & SPIFI_MCMD_INTLEN_MASK)
Kojto 148:fd96258d940d 4293 #define SPIFI_MCMD_FIELDFORM_MASK (0x180000U)
Kojto 148:fd96258d940d 4294 #define SPIFI_MCMD_FIELDFORM_SHIFT (19U)
Kojto 148:fd96258d940d 4295 #define SPIFI_MCMD_FIELDFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_FIELDFORM_SHIFT)) & SPIFI_MCMD_FIELDFORM_MASK)
Kojto 148:fd96258d940d 4296 #define SPIFI_MCMD_FRAMEFORM_MASK (0xE00000U)
Kojto 148:fd96258d940d 4297 #define SPIFI_MCMD_FRAMEFORM_SHIFT (21U)
Kojto 148:fd96258d940d 4298 #define SPIFI_MCMD_FRAMEFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_FRAMEFORM_SHIFT)) & SPIFI_MCMD_FRAMEFORM_MASK)
Kojto 148:fd96258d940d 4299 #define SPIFI_MCMD_OPCODE_MASK (0xFF000000U)
Kojto 148:fd96258d940d 4300 #define SPIFI_MCMD_OPCODE_SHIFT (24U)
Kojto 148:fd96258d940d 4301 #define SPIFI_MCMD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_OPCODE_SHIFT)) & SPIFI_MCMD_OPCODE_MASK)
Kojto 148:fd96258d940d 4302
Kojto 148:fd96258d940d 4303 /*! @name STAT - SPIFI status register */
Kojto 148:fd96258d940d 4304 #define SPIFI_STAT_MCINIT_MASK (0x1U)
Kojto 148:fd96258d940d 4305 #define SPIFI_STAT_MCINIT_SHIFT (0U)
Kojto 148:fd96258d940d 4306 #define SPIFI_STAT_MCINIT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_MCINIT_SHIFT)) & SPIFI_STAT_MCINIT_MASK)
Kojto 148:fd96258d940d 4307 #define SPIFI_STAT_CMD_MASK (0x2U)
Kojto 148:fd96258d940d 4308 #define SPIFI_STAT_CMD_SHIFT (1U)
Kojto 148:fd96258d940d 4309 #define SPIFI_STAT_CMD(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_CMD_SHIFT)) & SPIFI_STAT_CMD_MASK)
Kojto 148:fd96258d940d 4310 #define SPIFI_STAT_RESET_MASK (0x10U)
Kojto 148:fd96258d940d 4311 #define SPIFI_STAT_RESET_SHIFT (4U)
Kojto 148:fd96258d940d 4312 #define SPIFI_STAT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_RESET_SHIFT)) & SPIFI_STAT_RESET_MASK)
Kojto 148:fd96258d940d 4313 #define SPIFI_STAT_INTRQ_MASK (0x20U)
Kojto 148:fd96258d940d 4314 #define SPIFI_STAT_INTRQ_SHIFT (5U)
Kojto 148:fd96258d940d 4315 #define SPIFI_STAT_INTRQ(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_INTRQ_SHIFT)) & SPIFI_STAT_INTRQ_MASK)
Kojto 148:fd96258d940d 4316 #define SPIFI_STAT_VERSION_MASK (0xFF000000U)
Kojto 148:fd96258d940d 4317 #define SPIFI_STAT_VERSION_SHIFT (24U)
Kojto 148:fd96258d940d 4318 #define SPIFI_STAT_VERSION(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_VERSION_SHIFT)) & SPIFI_STAT_VERSION_MASK)
Kojto 148:fd96258d940d 4319
Kojto 148:fd96258d940d 4320
Kojto 148:fd96258d940d 4321 /*!
Kojto 148:fd96258d940d 4322 * @}
Kojto 148:fd96258d940d 4323 */ /* end of group SPIFI_Register_Masks */
Kojto 148:fd96258d940d 4324
Kojto 148:fd96258d940d 4325
Kojto 148:fd96258d940d 4326 /* SPIFI - Peripheral instance base addresses */
Kojto 148:fd96258d940d 4327 /** Peripheral SPIFI0 base address */
Kojto 148:fd96258d940d 4328 #define SPIFI0_BASE (0x40080000u)
Kojto 148:fd96258d940d 4329 /** Peripheral SPIFI0 base pointer */
Kojto 148:fd96258d940d 4330 #define SPIFI0 ((SPIFI_Type *)SPIFI0_BASE)
Kojto 148:fd96258d940d 4331 /** Array initializer of SPIFI peripheral base addresses */
Kojto 148:fd96258d940d 4332 #define SPIFI_BASE_ADDRS { SPIFI0_BASE }
Kojto 148:fd96258d940d 4333 /** Array initializer of SPIFI peripheral base pointers */
Kojto 148:fd96258d940d 4334 #define SPIFI_BASE_PTRS { SPIFI0 }
Kojto 148:fd96258d940d 4335 /** Interrupt vectors for the SPIFI peripheral type */
Kojto 148:fd96258d940d 4336 #define SPIFI_IRQS { SPIFI0_IRQn }
Kojto 148:fd96258d940d 4337
Kojto 148:fd96258d940d 4338 /*!
Kojto 148:fd96258d940d 4339 * @}
Kojto 148:fd96258d940d 4340 */ /* end of group SPIFI_Peripheral_Access_Layer */
Kojto 148:fd96258d940d 4341
Kojto 148:fd96258d940d 4342
Kojto 148:fd96258d940d 4343 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 4344 -- SYSCON Peripheral Access Layer
Kojto 148:fd96258d940d 4345 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 4346
Kojto 148:fd96258d940d 4347 /*!
Kojto 148:fd96258d940d 4348 * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer
Kojto 148:fd96258d940d 4349 * @{
Kojto 148:fd96258d940d 4350 */
Kojto 148:fd96258d940d 4351
Kojto 148:fd96258d940d 4352 /** SYSCON - Register Layout Typedef */
Kojto 148:fd96258d940d 4353 typedef struct {
Kojto 148:fd96258d940d 4354 __IO uint32_t SYSMEMREMAP; /**< System Remap register, offset: 0x0 */
Kojto 148:fd96258d940d 4355 uint8_t RESERVED_0[12];
Kojto 148:fd96258d940d 4356 __IO uint32_t AHBMATPRIO; /**< AHB multilayer matrix priority control, offset: 0x10 */
Kojto 148:fd96258d940d 4357 uint8_t RESERVED_1[44];
Kojto 148:fd96258d940d 4358 __IO uint32_t SYSTCKCAL; /**< System tick counter calibration, offset: 0x40 */
Kojto 148:fd96258d940d 4359 uint8_t RESERVED_2[4];
Kojto 148:fd96258d940d 4360 __IO uint32_t NMISRC; /**< NMI Source Select, offset: 0x48 */
Kojto 148:fd96258d940d 4361 __IO uint32_t ASYNCAPBCTRL; /**< Asynchronous APB Control, offset: 0x4C */
Kojto 148:fd96258d940d 4362 uint8_t RESERVED_3[112];
Kojto 148:fd96258d940d 4363 __I uint32_t PIOPORCAP[2]; /**< POR captured value of port n, array offset: 0xC0, array step: 0x4 */
Kojto 148:fd96258d940d 4364 uint8_t RESERVED_4[8];
Kojto 148:fd96258d940d 4365 __I uint32_t PIORESCAP[2]; /**< Reset captured value of port n, array offset: 0xD0, array step: 0x4 */
Kojto 148:fd96258d940d 4366 uint8_t RESERVED_5[40];
Kojto 148:fd96258d940d 4367 __IO uint32_t PRESETCTRL[2]; /**< Peripheral reset control n, array offset: 0x100, array step: 0x4 */
Kojto 148:fd96258d940d 4368 uint8_t RESERVED_6[24];
Kojto 148:fd96258d940d 4369 __O uint32_t PRESETCTRLSET[2]; /**< Set bits in PRESETCTRLn, array offset: 0x120, array step: 0x4 */
Kojto 148:fd96258d940d 4370 uint8_t RESERVED_7[24];
Kojto 148:fd96258d940d 4371 __O uint32_t PRESETCTRLCLR[2]; /**< Clear bits in PRESETCTRLn, array offset: 0x140, array step: 0x4 */
Kojto 148:fd96258d940d 4372 uint8_t RESERVED_8[168];
Kojto 148:fd96258d940d 4373 __IO uint32_t SYSRSTSTAT; /**< System reset status register, offset: 0x1F0 */
Kojto 148:fd96258d940d 4374 uint8_t RESERVED_9[12];
Kojto 148:fd96258d940d 4375 __IO uint32_t AHBCLKCTRL[2]; /**< AHB Clock control n, array offset: 0x200, array step: 0x4 */
Kojto 148:fd96258d940d 4376 uint8_t RESERVED_10[24];
Kojto 148:fd96258d940d 4377 __O uint32_t AHBCLKCTRLSET[2]; /**< Set bits in AHBCLKCTRLn, array offset: 0x220, array step: 0x4 */
Kojto 148:fd96258d940d 4378 uint8_t RESERVED_11[24];
Kojto 148:fd96258d940d 4379 __O uint32_t AHBCLKCTRLCLR[2]; /**< Clear bits in AHBCLKCTRLn, array offset: 0x240, array step: 0x4 */
Kojto 148:fd96258d940d 4380 uint8_t RESERVED_12[56];
Kojto 148:fd96258d940d 4381 __IO uint32_t MAINCLKSELA; /**< Main clock source select A, offset: 0x280 */
Kojto 148:fd96258d940d 4382 __IO uint32_t MAINCLKSELB; /**< Main clock source select B, offset: 0x284 */
Kojto 148:fd96258d940d 4383 __IO uint32_t CLKOUTSELA; /**< CLKOUT clock source select A, offset: 0x288 */
Kojto 148:fd96258d940d 4384 uint8_t RESERVED_13[4];
Kojto 148:fd96258d940d 4385 __IO uint32_t SYSPLLCLKSEL; /**< PLL clock source select, offset: 0x290 */
Kojto 148:fd96258d940d 4386 uint8_t RESERVED_14[12];
Kojto 148:fd96258d940d 4387 __IO uint32_t SPIFICLKSEL; /**< SPIFI clock source select, offset: 0x2A0 */
Kojto 148:fd96258d940d 4388 __IO uint32_t ADCCLKSEL; /**< ADC clock source select, offset: 0x2A4 */
Kojto 148:fd96258d940d 4389 __IO uint32_t USBCLKSEL; /**< USB clock source select, offset: 0x2A8 */
Kojto 148:fd96258d940d 4390 uint8_t RESERVED_15[4];
Kojto 148:fd96258d940d 4391 __IO uint32_t FXCOMCLKSEL[8]; /**< Flexcomm 0 clock source select, array offset: 0x2B0, array step: 0x4 */
Kojto 148:fd96258d940d 4392 uint8_t RESERVED_16[16];
Kojto 148:fd96258d940d 4393 __IO uint32_t MCLKCLKSEL; /**< MCLK clock source select, offset: 0x2E0 */
Kojto 148:fd96258d940d 4394 uint8_t RESERVED_17[4];
Kojto 148:fd96258d940d 4395 __IO uint32_t FRGCLKSEL; /**< Fractional Rate Generator clock source select, offset: 0x2E8 */
Kojto 148:fd96258d940d 4396 __IO uint32_t DMICCLKSEL; /**< Digital microphone (D-Mic) subsystem clock select, offset: 0x2EC */
Kojto 148:fd96258d940d 4397 uint8_t RESERVED_18[16];
Kojto 148:fd96258d940d 4398 __IO uint32_t SYSTICKCLKDIV; /**< SYSTICK clock divider, offset: 0x300 */
Kojto 148:fd96258d940d 4399 __IO uint32_t TRACECLKDIV; /**< Trace clock divider, offset: 0x304 */
Kojto 148:fd96258d940d 4400 uint8_t RESERVED_19[120];
Kojto 148:fd96258d940d 4401 __IO uint32_t AHBCLKDIV; /**< AHB clock divider, offset: 0x380 */
Kojto 148:fd96258d940d 4402 __IO uint32_t CLKOUTDIV; /**< CLKOUT clock divider, offset: 0x384 */
Kojto 148:fd96258d940d 4403 uint8_t RESERVED_20[8];
Kojto 148:fd96258d940d 4404 __IO uint32_t SPIFICLKDIV; /**< SPIFI clock divider, offset: 0x390 */
Kojto 148:fd96258d940d 4405 __IO uint32_t ADCCLKDIV; /**< ADC clock divider, offset: 0x394 */
Kojto 148:fd96258d940d 4406 __IO uint32_t USBCLKDIV; /**< USB clock divider, offset: 0x398 */
Kojto 148:fd96258d940d 4407 uint8_t RESERVED_21[4];
Kojto 148:fd96258d940d 4408 __IO uint32_t FRGCTRL; /**< Fractional rate divider, offset: 0x3A0 */
Kojto 148:fd96258d940d 4409 uint8_t RESERVED_22[4];
Kojto 148:fd96258d940d 4410 __IO uint32_t DMICCLKDIV; /**< DMIC clock divider, offset: 0x3A8 */
Kojto 148:fd96258d940d 4411 __IO uint32_t MCLKDIV; /**< I2S MCLK clock divider, offset: 0x3AC */
Kojto 148:fd96258d940d 4412 uint8_t RESERVED_23[80];
Kojto 148:fd96258d940d 4413 __IO uint32_t FLASHCFG; /**< Flash wait states configuration, offset: 0x400 */
Kojto 148:fd96258d940d 4414 uint8_t RESERVED_24[8];
Kojto 148:fd96258d940d 4415 __IO uint32_t USBCLKCTRL; /**< USB clock control, offset: 0x40C */
Kojto 148:fd96258d940d 4416 __IO uint32_t USBCLKSTAT; /**< USB clock status, offset: 0x410 */
Kojto 148:fd96258d940d 4417 uint8_t RESERVED_25[4];
Kojto 148:fd96258d940d 4418 __IO uint32_t FREQMECTRL; /**< Frequency measure register, offset: 0x418 */
Kojto 148:fd96258d940d 4419 uint8_t RESERVED_26[4];
Kojto 148:fd96258d940d 4420 __IO uint32_t MCLKIO; /**< MCLK input/output control, offset: 0x420 */
Kojto 148:fd96258d940d 4421 uint8_t RESERVED_27[220];
Kojto 148:fd96258d940d 4422 __IO uint32_t FROCTRL; /**< FRO oscillator control, offset: 0x500 */
Kojto 148:fd96258d940d 4423 uint8_t RESERVED_28[4];
Kojto 148:fd96258d940d 4424 __IO uint32_t WDTOSCCTRL; /**< Watchdog oscillator control, offset: 0x508 */
Kojto 148:fd96258d940d 4425 __IO uint32_t RTCOSCCTRL; /**< RTC oscillator 32 kHz output control, offset: 0x50C */
Kojto 148:fd96258d940d 4426 uint8_t RESERVED_29[112];
Kojto 148:fd96258d940d 4427 __IO uint32_t SYSPLLCTRL; /**< PLL control, offset: 0x580 */
Kojto 148:fd96258d940d 4428 __I uint32_t SYSPLLSTAT; /**< PLL status, offset: 0x584 */
Kojto 148:fd96258d940d 4429 __IO uint32_t SYSPLLNDEC; /**< PLL N decoder, offset: 0x588 */
Kojto 148:fd96258d940d 4430 __IO uint32_t SYSPLLPDEC; /**< PLL P decoder, offset: 0x58C */
Kojto 148:fd96258d940d 4431 __IO uint32_t SYSPLLSSCTRL0; /**< PLL spread spectrum control 0, offset: 0x590 */
Kojto 148:fd96258d940d 4432 __IO uint32_t SYSPLLSSCTRL1; /**< PLL spread spectrum control 1, offset: 0x594 */
Kojto 148:fd96258d940d 4433 uint8_t RESERVED_30[104];
Kojto 148:fd96258d940d 4434 __IO uint32_t PDSLEEPCFG[2]; /**< Sleep configuration register n, array offset: 0x600, array step: 0x4 */
Kojto 148:fd96258d940d 4435 uint8_t RESERVED_31[8];
Kojto 148:fd96258d940d 4436 __IO uint32_t PDRUNCFG[2]; /**< Power configuration register n, array offset: 0x610, array step: 0x4 */
Kojto 148:fd96258d940d 4437 uint8_t RESERVED_32[8];
Kojto 148:fd96258d940d 4438 __O uint32_t PDRUNCFGSET[2]; /**< Set bits in PDRUNCFGn, array offset: 0x620, array step: 0x4 */
Kojto 148:fd96258d940d 4439 uint8_t RESERVED_33[8];
Kojto 148:fd96258d940d 4440 __O uint32_t PDRUNCFGCLR[2]; /**< Clear bits in PDRUNCFGn, array offset: 0x630, array step: 0x4 */
Kojto 148:fd96258d940d 4441 uint8_t RESERVED_34[72];
Kojto 148:fd96258d940d 4442 __IO uint32_t STARTERP[2]; /**< Start logic n wake-up enable register, array offset: 0x680, array step: 0x4 */
Kojto 148:fd96258d940d 4443 uint8_t RESERVED_35[24];
Kojto 148:fd96258d940d 4444 __O uint32_t STARTERSET[2]; /**< Set bits in STARTERn, array offset: 0x6A0, array step: 0x4 */
Kojto 148:fd96258d940d 4445 uint8_t RESERVED_36[24];
Kojto 148:fd96258d940d 4446 __O uint32_t STARTERCLR[2]; /**< Clear bits in STARTERn, array offset: 0x6C0, array step: 0x4 */
Kojto 148:fd96258d940d 4447 uint8_t RESERVED_37[184];
Kojto 148:fd96258d940d 4448 __IO uint32_t HWWAKE; /**< Configures special cases of hardware wake-up, offset: 0x780 */
Kojto 148:fd96258d940d 4449 uint8_t RESERVED_38[124];
Kojto 148:fd96258d940d 4450 __IO uint32_t CPCTRL; /**< CPU Control for multiple processors, offset: 0x800 */
Kojto 148:fd96258d940d 4451 __IO uint32_t CPBOOT; /**< Coprocessor Boot Address, offset: 0x804 */
Kojto 148:fd96258d940d 4452 __IO uint32_t CPSTACK; /**< Coprocessor Stack Address, offset: 0x808 */
Kojto 148:fd96258d940d 4453 __I uint32_t CPSTAT; /**< Coprocessor Status, offset: 0x80C */
Kojto 148:fd96258d940d 4454 uint8_t RESERVED_39[1524];
Kojto 148:fd96258d940d 4455 __IO uint32_t AUTOCGOR; /**< Auto Clock-Gate Override Register, offset: 0xE04 */
Kojto 148:fd96258d940d 4456 uint8_t RESERVED_40[492];
Kojto 148:fd96258d940d 4457 __I uint32_t JTAGIDCODE; /**< JTAG ID code register, offset: 0xFF4 */
Kojto 148:fd96258d940d 4458 __I uint32_t DEVICE_ID0; /**< Part ID register, offset: 0xFF8 */
Kojto 148:fd96258d940d 4459 __I uint32_t DEVICE_ID1; /**< Boot ROM and die revision register, offset: 0xFFC */
Kojto 148:fd96258d940d 4460 uint8_t RESERVED_41[127044];
Kojto 148:fd96258d940d 4461 __IO uint32_t BODCTRL; /**< Brown-Out Detect control, offset: 0x20044 */
Kojto 148:fd96258d940d 4462 } SYSCON_Type;
Kojto 148:fd96258d940d 4463
Kojto 148:fd96258d940d 4464 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 4465 -- SYSCON Register Masks
Kojto 148:fd96258d940d 4466 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 4467
Kojto 148:fd96258d940d 4468 /*!
Kojto 148:fd96258d940d 4469 * @addtogroup SYSCON_Register_Masks SYSCON Register Masks
Kojto 148:fd96258d940d 4470 * @{
Kojto 148:fd96258d940d 4471 */
Kojto 148:fd96258d940d 4472
Kojto 148:fd96258d940d 4473 /*! @name AHBMATPRIO - AHB multilayer matrix priority control */
Kojto 148:fd96258d940d 4474 #define SYSCON_AHBMATPRIO_PRI_ICODE_MASK (0x3U)
Kojto 148:fd96258d940d 4475 #define SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT (0U)
Kojto 148:fd96258d940d 4476 #define SYSCON_AHBMATPRIO_PRI_ICODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT)) & SYSCON_AHBMATPRIO_PRI_ICODE_MASK)
Kojto 148:fd96258d940d 4477 #define SYSCON_AHBMATPRIO_PRI_DCODE_MASK (0xCU)
Kojto 148:fd96258d940d 4478 #define SYSCON_AHBMATPRIO_PRI_DCODE_SHIFT (2U)
Kojto 148:fd96258d940d 4479 #define SYSCON_AHBMATPRIO_PRI_DCODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_DCODE_SHIFT)) & SYSCON_AHBMATPRIO_PRI_DCODE_MASK)
Kojto 148:fd96258d940d 4480 #define SYSCON_AHBMATPRIO_PRI_SYS_MASK (0x30U)
Kojto 148:fd96258d940d 4481 #define SYSCON_AHBMATPRIO_PRI_SYS_SHIFT (4U)
Kojto 148:fd96258d940d 4482 #define SYSCON_AHBMATPRIO_PRI_SYS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SYS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SYS_MASK)
Kojto 148:fd96258d940d 4483 #define SYSCON_AHBMATPRIO_PRI_M0_MASK (0xC0U)
Kojto 148:fd96258d940d 4484 #define SYSCON_AHBMATPRIO_PRI_M0_SHIFT (6U)
Kojto 148:fd96258d940d 4485 #define SYSCON_AHBMATPRIO_PRI_M0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_M0_SHIFT)) & SYSCON_AHBMATPRIO_PRI_M0_MASK)
Kojto 148:fd96258d940d 4486 #define SYSCON_AHBMATPRIO_PRI_USB_MASK (0x300U)
Kojto 148:fd96258d940d 4487 #define SYSCON_AHBMATPRIO_PRI_USB_SHIFT (8U)
Kojto 148:fd96258d940d 4488 #define SYSCON_AHBMATPRIO_PRI_USB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_MASK)
Kojto 148:fd96258d940d 4489 #define SYSCON_AHBMATPRIO_PRI_DMA_MASK (0xC00U)
Kojto 148:fd96258d940d 4490 #define SYSCON_AHBMATPRIO_PRI_DMA_SHIFT (10U)
Kojto 148:fd96258d940d 4491 #define SYSCON_AHBMATPRIO_PRI_DMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_DMA_SHIFT)) & SYSCON_AHBMATPRIO_PRI_DMA_MASK)
Kojto 148:fd96258d940d 4492
Kojto 148:fd96258d940d 4493 /*! @name SYSTCKCAL - System tick counter calibration */
Kojto 148:fd96258d940d 4494 #define SYSCON_SYSTCKCAL_CAL_MASK (0xFFFFFFU)
Kojto 148:fd96258d940d 4495 #define SYSCON_SYSTCKCAL_CAL_SHIFT (0U)
Kojto 148:fd96258d940d 4496 #define SYSCON_SYSTCKCAL_CAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_CAL_SHIFT)) & SYSCON_SYSTCKCAL_CAL_MASK)
Kojto 148:fd96258d940d 4497 #define SYSCON_SYSTCKCAL_SKEW_MASK (0x1000000U)
Kojto 148:fd96258d940d 4498 #define SYSCON_SYSTCKCAL_SKEW_SHIFT (24U)
Kojto 148:fd96258d940d 4499 #define SYSCON_SYSTCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_SKEW_SHIFT)) & SYSCON_SYSTCKCAL_SKEW_MASK)
Kojto 148:fd96258d940d 4500 #define SYSCON_SYSTCKCAL_NOREF_MASK (0x2000000U)
Kojto 148:fd96258d940d 4501 #define SYSCON_SYSTCKCAL_NOREF_SHIFT (25U)
Kojto 148:fd96258d940d 4502 #define SYSCON_SYSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_NOREF_SHIFT)) & SYSCON_SYSTCKCAL_NOREF_MASK)
Kojto 148:fd96258d940d 4503
Kojto 148:fd96258d940d 4504 /*! @name NMISRC - NMI Source Select */
Kojto 148:fd96258d940d 4505 #define SYSCON_NMISRC_IRQM4_MASK (0x3FU)
Kojto 148:fd96258d940d 4506 #define SYSCON_NMISRC_IRQM4_SHIFT (0U)
Kojto 148:fd96258d940d 4507 #define SYSCON_NMISRC_IRQM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQM4_SHIFT)) & SYSCON_NMISRC_IRQM4_MASK)
Kojto 148:fd96258d940d 4508 #define SYSCON_NMISRC_IRQM0_MASK (0x3F00U)
Kojto 148:fd96258d940d 4509 #define SYSCON_NMISRC_IRQM0_SHIFT (8U)
Kojto 148:fd96258d940d 4510 #define SYSCON_NMISRC_IRQM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQM0_SHIFT)) & SYSCON_NMISRC_IRQM0_MASK)
Kojto 148:fd96258d940d 4511 #define SYSCON_NMISRC_NMIENM0_MASK (0x40000000U)
Kojto 148:fd96258d940d 4512 #define SYSCON_NMISRC_NMIENM0_SHIFT (30U)
Kojto 148:fd96258d940d 4513 #define SYSCON_NMISRC_NMIENM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENM0_SHIFT)) & SYSCON_NMISRC_NMIENM0_MASK)
Kojto 148:fd96258d940d 4514 #define SYSCON_NMISRC_NMIENM4_MASK (0x80000000U)
Kojto 148:fd96258d940d 4515 #define SYSCON_NMISRC_NMIENM4_SHIFT (31U)
Kojto 148:fd96258d940d 4516 #define SYSCON_NMISRC_NMIENM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENM4_SHIFT)) & SYSCON_NMISRC_NMIENM4_MASK)
Kojto 148:fd96258d940d 4517
Kojto 148:fd96258d940d 4518 /*! @name ASYNCAPBCTRL - Asynchronous APB Control */
Kojto 148:fd96258d940d 4519 #define SYSCON_ASYNCAPBCTRL_ENABLE_MASK (0x1U)
Kojto 148:fd96258d940d 4520 #define SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT (0U)
Kojto 148:fd96258d940d 4521 #define SYSCON_ASYNCAPBCTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT)) & SYSCON_ASYNCAPBCTRL_ENABLE_MASK)
Kojto 148:fd96258d940d 4522
Kojto 148:fd96258d940d 4523 /*! @name PIOPORCAP - POR captured value of port n */
Kojto 148:fd96258d940d 4524 #define SYSCON_PIOPORCAP_PIOPORCAP_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 4525 #define SYSCON_PIOPORCAP_PIOPORCAP_SHIFT (0U)
Kojto 148:fd96258d940d 4526 #define SYSCON_PIOPORCAP_PIOPORCAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PIOPORCAP_PIOPORCAP_SHIFT)) & SYSCON_PIOPORCAP_PIOPORCAP_MASK)
Kojto 148:fd96258d940d 4527
Kojto 148:fd96258d940d 4528 /* The count of SYSCON_PIOPORCAP */
Kojto 148:fd96258d940d 4529 #define SYSCON_PIOPORCAP_COUNT (2U)
Kojto 148:fd96258d940d 4530
Kojto 148:fd96258d940d 4531 /*! @name PIORESCAP - Reset captured value of port n */
Kojto 148:fd96258d940d 4532 #define SYSCON_PIORESCAP_PIORESCAP_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 4533 #define SYSCON_PIORESCAP_PIORESCAP_SHIFT (0U)
Kojto 148:fd96258d940d 4534 #define SYSCON_PIORESCAP_PIORESCAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PIORESCAP_PIORESCAP_SHIFT)) & SYSCON_PIORESCAP_PIORESCAP_MASK)
Kojto 148:fd96258d940d 4535
Kojto 148:fd96258d940d 4536 /* The count of SYSCON_PIORESCAP */
Kojto 148:fd96258d940d 4537 #define SYSCON_PIORESCAP_COUNT (2U)
Kojto 148:fd96258d940d 4538
Kojto 148:fd96258d940d 4539 /*! @name PRESETCTRL - Peripheral reset control n */
Kojto 148:fd96258d940d 4540 #define SYSCON_PRESETCTRL_MRT0_RST_MASK (0x1U)
Kojto 148:fd96258d940d 4541 #define SYSCON_PRESETCTRL_MRT0_RST_SHIFT (0U)
Kojto 148:fd96258d940d 4542 #define SYSCON_PRESETCTRL_MRT0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MRT0_RST_SHIFT)) & SYSCON_PRESETCTRL_MRT0_RST_MASK)
Kojto 148:fd96258d940d 4543 #define SYSCON_PRESETCTRL_SCT0_RST_MASK (0x4U)
Kojto 148:fd96258d940d 4544 #define SYSCON_PRESETCTRL_SCT0_RST_SHIFT (2U)
Kojto 148:fd96258d940d 4545 #define SYSCON_PRESETCTRL_SCT0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SCT0_RST_SHIFT)) & SYSCON_PRESETCTRL_SCT0_RST_MASK)
Kojto 148:fd96258d940d 4546 #define SYSCON_PRESETCTRL_FLASH_RST_MASK (0x80U)
Kojto 148:fd96258d940d 4547 #define SYSCON_PRESETCTRL_FLASH_RST_SHIFT (7U)
Kojto 148:fd96258d940d 4548 #define SYSCON_PRESETCTRL_FLASH_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FLASH_RST_SHIFT)) & SYSCON_PRESETCTRL_FLASH_RST_MASK)
Kojto 148:fd96258d940d 4549 #define SYSCON_PRESETCTRL_FMC_RST_MASK (0x100U)
Kojto 148:fd96258d940d 4550 #define SYSCON_PRESETCTRL_FMC_RST_SHIFT (8U)
Kojto 148:fd96258d940d 4551 #define SYSCON_PRESETCTRL_FMC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FMC_RST_SHIFT)) & SYSCON_PRESETCTRL_FMC_RST_MASK)
Kojto 148:fd96258d940d 4552 #define SYSCON_PRESETCTRL_UTICK0_RST_MASK (0x400U)
Kojto 148:fd96258d940d 4553 #define SYSCON_PRESETCTRL_UTICK0_RST_SHIFT (10U)
Kojto 148:fd96258d940d 4554 #define SYSCON_PRESETCTRL_UTICK0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_UTICK0_RST_SHIFT)) & SYSCON_PRESETCTRL_UTICK0_RST_MASK)
Kojto 148:fd96258d940d 4555 #define SYSCON_PRESETCTRL_MUX_RST_MASK (0x800U)
Kojto 148:fd96258d940d 4556 #define SYSCON_PRESETCTRL_MUX_RST_SHIFT (11U)
Kojto 148:fd96258d940d 4557 #define SYSCON_PRESETCTRL_MUX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL_MUX_RST_MASK)
Kojto 148:fd96258d940d 4558 #define SYSCON_PRESETCTRL_FC0_RST_MASK (0x800U)
Kojto 148:fd96258d940d 4559 #define SYSCON_PRESETCTRL_FC0_RST_SHIFT (11U)
Kojto 148:fd96258d940d 4560 #define SYSCON_PRESETCTRL_FC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL_FC0_RST_MASK)
Kojto 148:fd96258d940d 4561 #define SYSCON_PRESETCTRL_FC1_RST_MASK (0x1000U)
Kojto 148:fd96258d940d 4562 #define SYSCON_PRESETCTRL_FC1_RST_SHIFT (12U)
Kojto 148:fd96258d940d 4563 #define SYSCON_PRESETCTRL_FC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL_FC1_RST_MASK)
Kojto 148:fd96258d940d 4564 #define SYSCON_PRESETCTRL_FC2_RST_MASK (0x2000U)
Kojto 148:fd96258d940d 4565 #define SYSCON_PRESETCTRL_FC2_RST_SHIFT (13U)
Kojto 148:fd96258d940d 4566 #define SYSCON_PRESETCTRL_FC2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL_FC2_RST_MASK)
Kojto 148:fd96258d940d 4567 #define SYSCON_PRESETCTRL_IOCON_RST_MASK (0x2000U)
Kojto 148:fd96258d940d 4568 #define SYSCON_PRESETCTRL_IOCON_RST_SHIFT (13U)
Kojto 148:fd96258d940d 4569 #define SYSCON_PRESETCTRL_IOCON_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_IOCON_RST_SHIFT)) & SYSCON_PRESETCTRL_IOCON_RST_MASK)
Kojto 148:fd96258d940d 4570 #define SYSCON_PRESETCTRL_FC3_RST_MASK (0x4000U)
Kojto 148:fd96258d940d 4571 #define SYSCON_PRESETCTRL_FC3_RST_SHIFT (14U)
Kojto 148:fd96258d940d 4572 #define SYSCON_PRESETCTRL_FC3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL_FC3_RST_MASK)
Kojto 148:fd96258d940d 4573 #define SYSCON_PRESETCTRL_GPIO0_RST_MASK (0x4000U)
Kojto 148:fd96258d940d 4574 #define SYSCON_PRESETCTRL_GPIO0_RST_SHIFT (14U)
Kojto 148:fd96258d940d 4575 #define SYSCON_PRESETCTRL_GPIO0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO0_RST_MASK)
Kojto 148:fd96258d940d 4576 #define SYSCON_PRESETCTRL_FC4_RST_MASK (0x8000U)
Kojto 148:fd96258d940d 4577 #define SYSCON_PRESETCTRL_FC4_RST_SHIFT (15U)
Kojto 148:fd96258d940d 4578 #define SYSCON_PRESETCTRL_FC4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL_FC4_RST_MASK)
Kojto 148:fd96258d940d 4579 #define SYSCON_PRESETCTRL_GPIO1_RST_MASK (0x8000U)
Kojto 148:fd96258d940d 4580 #define SYSCON_PRESETCTRL_GPIO1_RST_SHIFT (15U)
Kojto 148:fd96258d940d 4581 #define SYSCON_PRESETCTRL_GPIO1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO1_RST_MASK)
Kojto 148:fd96258d940d 4582 #define SYSCON_PRESETCTRL_FC5_RST_MASK (0x10000U)
Kojto 148:fd96258d940d 4583 #define SYSCON_PRESETCTRL_FC5_RST_SHIFT (16U)
Kojto 148:fd96258d940d 4584 #define SYSCON_PRESETCTRL_FC5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL_FC5_RST_MASK)
Kojto 148:fd96258d940d 4585 #define SYSCON_PRESETCTRL_FC6_RST_MASK (0x20000U)
Kojto 148:fd96258d940d 4586 #define SYSCON_PRESETCTRL_FC6_RST_SHIFT (17U)
Kojto 148:fd96258d940d 4587 #define SYSCON_PRESETCTRL_FC6_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL_FC6_RST_MASK)
Kojto 148:fd96258d940d 4588 #define SYSCON_PRESETCTRL_FC7_RST_MASK (0x40000U)
Kojto 148:fd96258d940d 4589 #define SYSCON_PRESETCTRL_FC7_RST_SHIFT (18U)
Kojto 148:fd96258d940d 4590 #define SYSCON_PRESETCTRL_FC7_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL_FC7_RST_MASK)
Kojto 148:fd96258d940d 4591 #define SYSCON_PRESETCTRL_PINT_RST_MASK (0x40000U)
Kojto 148:fd96258d940d 4592 #define SYSCON_PRESETCTRL_PINT_RST_SHIFT (18U)
Kojto 148:fd96258d940d 4593 #define SYSCON_PRESETCTRL_PINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL_PINT_RST_MASK)
Kojto 148:fd96258d940d 4594 #define SYSCON_PRESETCTRL_GINT_RST_MASK (0x80000U)
Kojto 148:fd96258d940d 4595 #define SYSCON_PRESETCTRL_GINT_RST_SHIFT (19U)
Kojto 148:fd96258d940d 4596 #define SYSCON_PRESETCTRL_GINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL_GINT_RST_MASK)
Kojto 148:fd96258d940d 4597 #define SYSCON_PRESETCTRL_DMIC0_RST_MASK (0x80000U)
Kojto 148:fd96258d940d 4598 #define SYSCON_PRESETCTRL_DMIC0_RST_SHIFT (19U)
Kojto 148:fd96258d940d 4599 #define SYSCON_PRESETCTRL_DMIC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMIC0_RST_SHIFT)) & SYSCON_PRESETCTRL_DMIC0_RST_MASK)
Kojto 148:fd96258d940d 4600 #define SYSCON_PRESETCTRL_DMA0_RST_MASK (0x100000U)
Kojto 148:fd96258d940d 4601 #define SYSCON_PRESETCTRL_DMA0_RST_SHIFT (20U)
Kojto 148:fd96258d940d 4602 #define SYSCON_PRESETCTRL_DMA0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL_DMA0_RST_MASK)
Kojto 148:fd96258d940d 4603 #define SYSCON_PRESETCTRL_CRC_RST_MASK (0x200000U)
Kojto 148:fd96258d940d 4604 #define SYSCON_PRESETCTRL_CRC_RST_SHIFT (21U)
Kojto 148:fd96258d940d 4605 #define SYSCON_PRESETCTRL_CRC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CRC_RST_SHIFT)) & SYSCON_PRESETCTRL_CRC_RST_MASK)
Kojto 148:fd96258d940d 4606 #define SYSCON_PRESETCTRL_CTIMER2_RST_MASK (0x400000U)
Kojto 148:fd96258d940d 4607 #define SYSCON_PRESETCTRL_CTIMER2_RST_SHIFT (22U)
Kojto 148:fd96258d940d 4608 #define SYSCON_PRESETCTRL_CTIMER2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER2_RST_MASK)
Kojto 148:fd96258d940d 4609 #define SYSCON_PRESETCTRL_WWDT_RST_MASK (0x400000U)
Kojto 148:fd96258d940d 4610 #define SYSCON_PRESETCTRL_WWDT_RST_SHIFT (22U)
Kojto 148:fd96258d940d 4611 #define SYSCON_PRESETCTRL_WWDT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_WWDT_RST_SHIFT)) & SYSCON_PRESETCTRL_WWDT_RST_MASK)
Kojto 148:fd96258d940d 4612 #define SYSCON_PRESETCTRL_USB0_RST_MASK (0x2000000U)
Kojto 148:fd96258d940d 4613 #define SYSCON_PRESETCTRL_USB0_RST_SHIFT (25U)
Kojto 148:fd96258d940d 4614 #define SYSCON_PRESETCTRL_USB0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0_RST_MASK)
Kojto 148:fd96258d940d 4615 #define SYSCON_PRESETCTRL_CTIMER0_RST_MASK (0x4000000U)
Kojto 148:fd96258d940d 4616 #define SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT (26U)
Kojto 148:fd96258d940d 4617 #define SYSCON_PRESETCTRL_CTIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER0_RST_MASK)
Kojto 148:fd96258d940d 4618 #define SYSCON_PRESETCTRL_CTIMER1_RST_MASK (0x8000000U)
Kojto 148:fd96258d940d 4619 #define SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT (27U)
Kojto 148:fd96258d940d 4620 #define SYSCON_PRESETCTRL_CTIMER1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER1_RST_MASK)
Kojto 148:fd96258d940d 4621 #define SYSCON_PRESETCTRL_ADC0_RST_MASK (0x8000000U)
Kojto 148:fd96258d940d 4622 #define SYSCON_PRESETCTRL_ADC0_RST_SHIFT (27U)
Kojto 148:fd96258d940d 4623 #define SYSCON_PRESETCTRL_ADC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_ADC0_RST_SHIFT)) & SYSCON_PRESETCTRL_ADC0_RST_MASK)
Kojto 148:fd96258d940d 4624
Kojto 148:fd96258d940d 4625 /* The count of SYSCON_PRESETCTRL */
Kojto 148:fd96258d940d 4626 #define SYSCON_PRESETCTRL_COUNT (2U)
Kojto 148:fd96258d940d 4627
Kojto 148:fd96258d940d 4628 /*! @name PRESETCTRLSET - Set bits in PRESETCTRLn */
Kojto 148:fd96258d940d 4629 #define SYSCON_PRESETCTRLSET_RST_SET_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 4630 #define SYSCON_PRESETCTRLSET_RST_SET_SHIFT (0U)
Kojto 148:fd96258d940d 4631 #define SYSCON_PRESETCTRLSET_RST_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_RST_SET_SHIFT)) & SYSCON_PRESETCTRLSET_RST_SET_MASK)
Kojto 148:fd96258d940d 4632
Kojto 148:fd96258d940d 4633 /* The count of SYSCON_PRESETCTRLSET */
Kojto 148:fd96258d940d 4634 #define SYSCON_PRESETCTRLSET_COUNT (2U)
Kojto 148:fd96258d940d 4635
Kojto 148:fd96258d940d 4636 /*! @name PRESETCTRLCLR - Clear bits in PRESETCTRLn */
Kojto 148:fd96258d940d 4637 #define SYSCON_PRESETCTRLCLR_RST_CLR_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 4638 #define SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT (0U)
Kojto 148:fd96258d940d 4639 #define SYSCON_PRESETCTRLCLR_RST_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT)) & SYSCON_PRESETCTRLCLR_RST_CLR_MASK)
Kojto 148:fd96258d940d 4640
Kojto 148:fd96258d940d 4641 /* The count of SYSCON_PRESETCTRLCLR */
Kojto 148:fd96258d940d 4642 #define SYSCON_PRESETCTRLCLR_COUNT (2U)
Kojto 148:fd96258d940d 4643
Kojto 148:fd96258d940d 4644 /*! @name SYSRSTSTAT - System reset status register */
Kojto 148:fd96258d940d 4645 #define SYSCON_SYSRSTSTAT_POR_MASK (0x1U)
Kojto 148:fd96258d940d 4646 #define SYSCON_SYSRSTSTAT_POR_SHIFT (0U)
Kojto 148:fd96258d940d 4647 #define SYSCON_SYSRSTSTAT_POR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_POR_SHIFT)) & SYSCON_SYSRSTSTAT_POR_MASK)
Kojto 148:fd96258d940d 4648 #define SYSCON_SYSRSTSTAT_EXTRST_MASK (0x2U)
Kojto 148:fd96258d940d 4649 #define SYSCON_SYSRSTSTAT_EXTRST_SHIFT (1U)
Kojto 148:fd96258d940d 4650 #define SYSCON_SYSRSTSTAT_EXTRST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_EXTRST_SHIFT)) & SYSCON_SYSRSTSTAT_EXTRST_MASK)
Kojto 148:fd96258d940d 4651 #define SYSCON_SYSRSTSTAT_WDT_MASK (0x4U)
Kojto 148:fd96258d940d 4652 #define SYSCON_SYSRSTSTAT_WDT_SHIFT (2U)
Kojto 148:fd96258d940d 4653 #define SYSCON_SYSRSTSTAT_WDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_WDT_SHIFT)) & SYSCON_SYSRSTSTAT_WDT_MASK)
Kojto 148:fd96258d940d 4654 #define SYSCON_SYSRSTSTAT_BOD_MASK (0x8U)
Kojto 148:fd96258d940d 4655 #define SYSCON_SYSRSTSTAT_BOD_SHIFT (3U)
Kojto 148:fd96258d940d 4656 #define SYSCON_SYSRSTSTAT_BOD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_BOD_SHIFT)) & SYSCON_SYSRSTSTAT_BOD_MASK)
Kojto 148:fd96258d940d 4657 #define SYSCON_SYSRSTSTAT_SYSRST_MASK (0x10U)
Kojto 148:fd96258d940d 4658 #define SYSCON_SYSRSTSTAT_SYSRST_SHIFT (4U)
Kojto 148:fd96258d940d 4659 #define SYSCON_SYSRSTSTAT_SYSRST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_SYSRST_SHIFT)) & SYSCON_SYSRSTSTAT_SYSRST_MASK)
Kojto 148:fd96258d940d 4660
Kojto 148:fd96258d940d 4661 /*! @name AHBCLKCTRL - AHB Clock control n */
Kojto 148:fd96258d940d 4662 #define SYSCON_AHBCLKCTRL_MRT0_MASK (0x1U)
Kojto 148:fd96258d940d 4663 #define SYSCON_AHBCLKCTRL_MRT0_SHIFT (0U)
Kojto 148:fd96258d940d 4664 #define SYSCON_AHBCLKCTRL_MRT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MRT0_SHIFT)) & SYSCON_AHBCLKCTRL_MRT0_MASK)
Kojto 148:fd96258d940d 4665 #define SYSCON_AHBCLKCTRL_ROM_MASK (0x2U)
Kojto 148:fd96258d940d 4666 #define SYSCON_AHBCLKCTRL_ROM_SHIFT (1U)
Kojto 148:fd96258d940d 4667 #define SYSCON_AHBCLKCTRL_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ROM_SHIFT)) & SYSCON_AHBCLKCTRL_ROM_MASK)
Kojto 148:fd96258d940d 4668 #define SYSCON_AHBCLKCTRL_SCT0_MASK (0x4U)
Kojto 148:fd96258d940d 4669 #define SYSCON_AHBCLKCTRL_SCT0_SHIFT (2U)
Kojto 148:fd96258d940d 4670 #define SYSCON_AHBCLKCTRL_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SCT0_SHIFT)) & SYSCON_AHBCLKCTRL_SCT0_MASK)
Kojto 148:fd96258d940d 4671 #define SYSCON_AHBCLKCTRL_SRAM1_MASK (0x8U)
Kojto 148:fd96258d940d 4672 #define SYSCON_AHBCLKCTRL_SRAM1_SHIFT (3U)
Kojto 148:fd96258d940d 4673 #define SYSCON_AHBCLKCTRL_SRAM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM1_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM1_MASK)
Kojto 148:fd96258d940d 4674 #define SYSCON_AHBCLKCTRL_SRAM2_MASK (0x10U)
Kojto 148:fd96258d940d 4675 #define SYSCON_AHBCLKCTRL_SRAM2_SHIFT (4U)
Kojto 148:fd96258d940d 4676 #define SYSCON_AHBCLKCTRL_SRAM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM2_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM2_MASK)
Kojto 148:fd96258d940d 4677 #define SYSCON_AHBCLKCTRL_FLASH_MASK (0x80U)
Kojto 148:fd96258d940d 4678 #define SYSCON_AHBCLKCTRL_FLASH_SHIFT (7U)
Kojto 148:fd96258d940d 4679 #define SYSCON_AHBCLKCTRL_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLASH_SHIFT)) & SYSCON_AHBCLKCTRL_FLASH_MASK)
Kojto 148:fd96258d940d 4680 #define SYSCON_AHBCLKCTRL_FMC_MASK (0x100U)
Kojto 148:fd96258d940d 4681 #define SYSCON_AHBCLKCTRL_FMC_SHIFT (8U)
Kojto 148:fd96258d940d 4682 #define SYSCON_AHBCLKCTRL_FMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FMC_SHIFT)) & SYSCON_AHBCLKCTRL_FMC_MASK)
Kojto 148:fd96258d940d 4683 #define SYSCON_AHBCLKCTRL_UTICK0_MASK (0x400U)
Kojto 148:fd96258d940d 4684 #define SYSCON_AHBCLKCTRL_UTICK0_SHIFT (10U)
Kojto 148:fd96258d940d 4685 #define SYSCON_AHBCLKCTRL_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_UTICK0_SHIFT)) & SYSCON_AHBCLKCTRL_UTICK0_MASK)
Kojto 148:fd96258d940d 4686 #define SYSCON_AHBCLKCTRL_FLEXCOMM0_MASK (0x800U)
Kojto 148:fd96258d940d 4687 #define SYSCON_AHBCLKCTRL_FLEXCOMM0_SHIFT (11U)
Kojto 148:fd96258d940d 4688 #define SYSCON_AHBCLKCTRL_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM0_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM0_MASK)
Kojto 148:fd96258d940d 4689 #define SYSCON_AHBCLKCTRL_INPUTMUX_MASK (0x800U)
Kojto 148:fd96258d940d 4690 #define SYSCON_AHBCLKCTRL_INPUTMUX_SHIFT (11U)
Kojto 148:fd96258d940d 4691 #define SYSCON_AHBCLKCTRL_INPUTMUX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_INPUTMUX_SHIFT)) & SYSCON_AHBCLKCTRL_INPUTMUX_MASK)
Kojto 148:fd96258d940d 4692 #define SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK (0x1000U)
Kojto 148:fd96258d940d 4693 #define SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT (12U)
Kojto 148:fd96258d940d 4694 #define SYSCON_AHBCLKCTRL_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK)
Kojto 148:fd96258d940d 4695 #define SYSCON_AHBCLKCTRL_IOCON_MASK (0x2000U)
Kojto 148:fd96258d940d 4696 #define SYSCON_AHBCLKCTRL_IOCON_SHIFT (13U)
Kojto 148:fd96258d940d 4697 #define SYSCON_AHBCLKCTRL_IOCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL_IOCON_MASK)
Kojto 148:fd96258d940d 4698 #define SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK (0x2000U)
Kojto 148:fd96258d940d 4699 #define SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT (13U)
Kojto 148:fd96258d940d 4700 #define SYSCON_AHBCLKCTRL_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK)
Kojto 148:fd96258d940d 4701 #define SYSCON_AHBCLKCTRL_GPIO0_MASK (0x4000U)
Kojto 148:fd96258d940d 4702 #define SYSCON_AHBCLKCTRL_GPIO0_SHIFT (14U)
Kojto 148:fd96258d940d 4703 #define SYSCON_AHBCLKCTRL_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO0_MASK)
Kojto 148:fd96258d940d 4704 #define SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK (0x4000U)
Kojto 148:fd96258d940d 4705 #define SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT (14U)
Kojto 148:fd96258d940d 4706 #define SYSCON_AHBCLKCTRL_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK)
Kojto 148:fd96258d940d 4707 #define SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK (0x8000U)
Kojto 148:fd96258d940d 4708 #define SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT (15U)
Kojto 148:fd96258d940d 4709 #define SYSCON_AHBCLKCTRL_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK)
Kojto 148:fd96258d940d 4710 #define SYSCON_AHBCLKCTRL_GPIO1_MASK (0x8000U)
Kojto 148:fd96258d940d 4711 #define SYSCON_AHBCLKCTRL_GPIO1_SHIFT (15U)
Kojto 148:fd96258d940d 4712 #define SYSCON_AHBCLKCTRL_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO1_MASK)
Kojto 148:fd96258d940d 4713 #define SYSCON_AHBCLKCTRL_FLEXCOMM5_MASK (0x10000U)
Kojto 148:fd96258d940d 4714 #define SYSCON_AHBCLKCTRL_FLEXCOMM5_SHIFT (16U)
Kojto 148:fd96258d940d 4715 #define SYSCON_AHBCLKCTRL_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM5_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM5_MASK)
Kojto 148:fd96258d940d 4716 #define SYSCON_AHBCLKCTRL_FLEXCOMM6_MASK (0x20000U)
Kojto 148:fd96258d940d 4717 #define SYSCON_AHBCLKCTRL_FLEXCOMM6_SHIFT (17U)
Kojto 148:fd96258d940d 4718 #define SYSCON_AHBCLKCTRL_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM6_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM6_MASK)
Kojto 148:fd96258d940d 4719 #define SYSCON_AHBCLKCTRL_FLEXCOMM7_MASK (0x40000U)
Kojto 148:fd96258d940d 4720 #define SYSCON_AHBCLKCTRL_FLEXCOMM7_SHIFT (18U)
Kojto 148:fd96258d940d 4721 #define SYSCON_AHBCLKCTRL_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM7_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM7_MASK)
Kojto 148:fd96258d940d 4722 #define SYSCON_AHBCLKCTRL_PINT_MASK (0x40000U)
Kojto 148:fd96258d940d 4723 #define SYSCON_AHBCLKCTRL_PINT_SHIFT (18U)
Kojto 148:fd96258d940d 4724 #define SYSCON_AHBCLKCTRL_PINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_PINT_SHIFT)) & SYSCON_AHBCLKCTRL_PINT_MASK)
Kojto 148:fd96258d940d 4725 #define SYSCON_AHBCLKCTRL_GINT_MASK (0x80000U)
Kojto 148:fd96258d940d 4726 #define SYSCON_AHBCLKCTRL_GINT_SHIFT (19U)
Kojto 148:fd96258d940d 4727 #define SYSCON_AHBCLKCTRL_GINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GINT_SHIFT)) & SYSCON_AHBCLKCTRL_GINT_MASK)
Kojto 148:fd96258d940d 4728 #define SYSCON_AHBCLKCTRL_DMIC0_MASK (0x80000U)
Kojto 148:fd96258d940d 4729 #define SYSCON_AHBCLKCTRL_DMIC0_SHIFT (19U)
Kojto 148:fd96258d940d 4730 #define SYSCON_AHBCLKCTRL_DMIC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_DMIC0_SHIFT)) & SYSCON_AHBCLKCTRL_DMIC0_MASK)
Kojto 148:fd96258d940d 4731 #define SYSCON_AHBCLKCTRL_DMA0_MASK (0x100000U)
Kojto 148:fd96258d940d 4732 #define SYSCON_AHBCLKCTRL_DMA0_SHIFT (20U)
Kojto 148:fd96258d940d 4733 #define SYSCON_AHBCLKCTRL_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_DMA0_SHIFT)) & SYSCON_AHBCLKCTRL_DMA0_MASK)
Kojto 148:fd96258d940d 4734 #define SYSCON_AHBCLKCTRL_CRC_MASK (0x200000U)
Kojto 148:fd96258d940d 4735 #define SYSCON_AHBCLKCTRL_CRC_SHIFT (21U)
Kojto 148:fd96258d940d 4736 #define SYSCON_AHBCLKCTRL_CRC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CRC_SHIFT)) & SYSCON_AHBCLKCTRL_CRC_MASK)
Kojto 148:fd96258d940d 4737 #define SYSCON_AHBCLKCTRL_CTIMER2_MASK (0x400000U)
Kojto 148:fd96258d940d 4738 #define SYSCON_AHBCLKCTRL_CTIMER2_SHIFT (22U)
Kojto 148:fd96258d940d 4739 #define SYSCON_AHBCLKCTRL_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER2_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER2_MASK)
Kojto 148:fd96258d940d 4740 #define SYSCON_AHBCLKCTRL_WWDT_MASK (0x400000U)
Kojto 148:fd96258d940d 4741 #define SYSCON_AHBCLKCTRL_WWDT_SHIFT (22U)
Kojto 148:fd96258d940d 4742 #define SYSCON_AHBCLKCTRL_WWDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_WWDT_SHIFT)) & SYSCON_AHBCLKCTRL_WWDT_MASK)
Kojto 148:fd96258d940d 4743 #define SYSCON_AHBCLKCTRL_RTC_MASK (0x800000U)
Kojto 148:fd96258d940d 4744 #define SYSCON_AHBCLKCTRL_RTC_SHIFT (23U)
Kojto 148:fd96258d940d 4745 #define SYSCON_AHBCLKCTRL_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RTC_SHIFT)) & SYSCON_AHBCLKCTRL_RTC_MASK)
Kojto 148:fd96258d940d 4746 #define SYSCON_AHBCLKCTRL_USB0_MASK (0x2000000U)
Kojto 148:fd96258d940d 4747 #define SYSCON_AHBCLKCTRL_USB0_SHIFT (25U)
Kojto 148:fd96258d940d 4748 #define SYSCON_AHBCLKCTRL_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0_SHIFT)) & SYSCON_AHBCLKCTRL_USB0_MASK)
Kojto 148:fd96258d940d 4749 #define SYSCON_AHBCLKCTRL_CTIMER0_MASK (0x4000000U)
Kojto 148:fd96258d940d 4750 #define SYSCON_AHBCLKCTRL_CTIMER0_SHIFT (26U)
Kojto 148:fd96258d940d 4751 #define SYSCON_AHBCLKCTRL_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER0_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER0_MASK)
Kojto 148:fd96258d940d 4752 #define SYSCON_AHBCLKCTRL_MAILBOX_MASK (0x4000000U)
Kojto 148:fd96258d940d 4753 #define SYSCON_AHBCLKCTRL_MAILBOX_SHIFT (26U)
Kojto 148:fd96258d940d 4754 #define SYSCON_AHBCLKCTRL_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MAILBOX_SHIFT)) & SYSCON_AHBCLKCTRL_MAILBOX_MASK)
Kojto 148:fd96258d940d 4755 #define SYSCON_AHBCLKCTRL_CTIMER1_MASK (0x8000000U)
Kojto 148:fd96258d940d 4756 #define SYSCON_AHBCLKCTRL_CTIMER1_SHIFT (27U)
Kojto 148:fd96258d940d 4757 #define SYSCON_AHBCLKCTRL_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER1_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER1_MASK)
Kojto 148:fd96258d940d 4758 #define SYSCON_AHBCLKCTRL_ADC0_MASK (0x8000000U)
Kojto 148:fd96258d940d 4759 #define SYSCON_AHBCLKCTRL_ADC0_SHIFT (27U)
Kojto 148:fd96258d940d 4760 #define SYSCON_AHBCLKCTRL_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ADC0_SHIFT)) & SYSCON_AHBCLKCTRL_ADC0_MASK)
Kojto 148:fd96258d940d 4761
Kojto 148:fd96258d940d 4762 /* The count of SYSCON_AHBCLKCTRL */
Kojto 148:fd96258d940d 4763 #define SYSCON_AHBCLKCTRL_COUNT (2U)
Kojto 148:fd96258d940d 4764
Kojto 148:fd96258d940d 4765 /*! @name AHBCLKCTRLSET - Set bits in AHBCLKCTRLn */
Kojto 148:fd96258d940d 4766 #define SYSCON_AHBCLKCTRLSET_CLK_SET_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 4767 #define SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT (0U)
Kojto 148:fd96258d940d 4768 #define SYSCON_AHBCLKCTRLSET_CLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT)) & SYSCON_AHBCLKCTRLSET_CLK_SET_MASK)
Kojto 148:fd96258d940d 4769
Kojto 148:fd96258d940d 4770 /* The count of SYSCON_AHBCLKCTRLSET */
Kojto 148:fd96258d940d 4771 #define SYSCON_AHBCLKCTRLSET_COUNT (2U)
Kojto 148:fd96258d940d 4772
Kojto 148:fd96258d940d 4773 /*! @name AHBCLKCTRLCLR - Clear bits in AHBCLKCTRLn */
Kojto 148:fd96258d940d 4774 #define SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 4775 #define SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT (0U)
Kojto 148:fd96258d940d 4776 #define SYSCON_AHBCLKCTRLCLR_CLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT)) & SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK)
Kojto 148:fd96258d940d 4777
Kojto 148:fd96258d940d 4778 /* The count of SYSCON_AHBCLKCTRLCLR */
Kojto 148:fd96258d940d 4779 #define SYSCON_AHBCLKCTRLCLR_COUNT (2U)
Kojto 148:fd96258d940d 4780
Kojto 148:fd96258d940d 4781 /*! @name MAINCLKSELA - Main clock source select A */
Kojto 148:fd96258d940d 4782 #define SYSCON_MAINCLKSELA_SEL_MASK (0x3U)
Kojto 148:fd96258d940d 4783 #define SYSCON_MAINCLKSELA_SEL_SHIFT (0U)
Kojto 148:fd96258d940d 4784 #define SYSCON_MAINCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK)
Kojto 148:fd96258d940d 4785
Kojto 148:fd96258d940d 4786 /*! @name MAINCLKSELB - Main clock source select B */
Kojto 148:fd96258d940d 4787 #define SYSCON_MAINCLKSELB_SEL_MASK (0x3U)
Kojto 148:fd96258d940d 4788 #define SYSCON_MAINCLKSELB_SEL_SHIFT (0U)
Kojto 148:fd96258d940d 4789 #define SYSCON_MAINCLKSELB_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK)
Kojto 148:fd96258d940d 4790
Kojto 148:fd96258d940d 4791 /*! @name CLKOUTSELA - CLKOUT clock source select A */
Kojto 148:fd96258d940d 4792 #define SYSCON_CLKOUTSELA_SEL_MASK (0x7U)
Kojto 148:fd96258d940d 4793 #define SYSCON_CLKOUTSELA_SEL_SHIFT (0U)
Kojto 148:fd96258d940d 4794 #define SYSCON_CLKOUTSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSELA_SEL_SHIFT)) & SYSCON_CLKOUTSELA_SEL_MASK)
Kojto 148:fd96258d940d 4795
Kojto 148:fd96258d940d 4796 /*! @name SYSPLLCLKSEL - PLL clock source select */
Kojto 148:fd96258d940d 4797 #define SYSCON_SYSPLLCLKSEL_SEL_MASK (0x7U)
Kojto 148:fd96258d940d 4798 #define SYSCON_SYSPLLCLKSEL_SEL_SHIFT (0U)
Kojto 148:fd96258d940d 4799 #define SYSCON_SYSPLLCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCLKSEL_SEL_SHIFT)) & SYSCON_SYSPLLCLKSEL_SEL_MASK)
Kojto 148:fd96258d940d 4800
Kojto 148:fd96258d940d 4801 /*! @name SPIFICLKSEL - SPIFI clock source select */
Kojto 148:fd96258d940d 4802 #define SYSCON_SPIFICLKSEL_SEL_MASK (0x7U)
Kojto 148:fd96258d940d 4803 #define SYSCON_SPIFICLKSEL_SEL_SHIFT (0U)
Kojto 148:fd96258d940d 4804 #define SYSCON_SPIFICLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKSEL_SEL_SHIFT)) & SYSCON_SPIFICLKSEL_SEL_MASK)
Kojto 148:fd96258d940d 4805
Kojto 148:fd96258d940d 4806 /*! @name ADCCLKSEL - ADC clock source select */
Kojto 148:fd96258d940d 4807 #define SYSCON_ADCCLKSEL_SEL_MASK (0x7U)
Kojto 148:fd96258d940d 4808 #define SYSCON_ADCCLKSEL_SEL_SHIFT (0U)
Kojto 148:fd96258d940d 4809 #define SYSCON_ADCCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKSEL_SEL_SHIFT)) & SYSCON_ADCCLKSEL_SEL_MASK)
Kojto 148:fd96258d940d 4810
Kojto 148:fd96258d940d 4811 /*! @name USBCLKSEL - USB clock source select */
Kojto 148:fd96258d940d 4812 #define SYSCON_USBCLKSEL_SEL_MASK (0x7U)
Kojto 148:fd96258d940d 4813 #define SYSCON_USBCLKSEL_SEL_SHIFT (0U)
Kojto 148:fd96258d940d 4814 #define SYSCON_USBCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKSEL_SEL_SHIFT)) & SYSCON_USBCLKSEL_SEL_MASK)
Kojto 148:fd96258d940d 4815
Kojto 148:fd96258d940d 4816 /*! @name FXCOMCLKSEL - Flexcomm 0 clock source select */
Kojto 148:fd96258d940d 4817 #define SYSCON_FXCOMCLKSEL_SEL_MASK (0x7U)
Kojto 148:fd96258d940d 4818 #define SYSCON_FXCOMCLKSEL_SEL_SHIFT (0U)
Kojto 148:fd96258d940d 4819 #define SYSCON_FXCOMCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FXCOMCLKSEL_SEL_SHIFT)) & SYSCON_FXCOMCLKSEL_SEL_MASK)
Kojto 148:fd96258d940d 4820
Kojto 148:fd96258d940d 4821 /* The count of SYSCON_FXCOMCLKSEL */
Kojto 148:fd96258d940d 4822 #define SYSCON_FXCOMCLKSEL_COUNT (8U)
Kojto 148:fd96258d940d 4823
Kojto 148:fd96258d940d 4824 /*! @name MCLKCLKSEL - MCLK clock source select */
Kojto 148:fd96258d940d 4825 #define SYSCON_MCLKCLKSEL_SEL_MASK (0x7U)
Kojto 148:fd96258d940d 4826 #define SYSCON_MCLKCLKSEL_SEL_SHIFT (0U)
Kojto 148:fd96258d940d 4827 #define SYSCON_MCLKCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKCLKSEL_SEL_SHIFT)) & SYSCON_MCLKCLKSEL_SEL_MASK)
Kojto 148:fd96258d940d 4828
Kojto 148:fd96258d940d 4829 /*! @name FRGCLKSEL - Fractional Rate Generator clock source select */
Kojto 148:fd96258d940d 4830 #define SYSCON_FRGCLKSEL_SEL_MASK (0x7U)
Kojto 148:fd96258d940d 4831 #define SYSCON_FRGCLKSEL_SEL_SHIFT (0U)
Kojto 148:fd96258d940d 4832 #define SYSCON_FRGCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCLKSEL_SEL_SHIFT)) & SYSCON_FRGCLKSEL_SEL_MASK)
Kojto 148:fd96258d940d 4833
Kojto 148:fd96258d940d 4834 /*! @name DMICCLKSEL - Digital microphone (D-Mic) subsystem clock select */
Kojto 148:fd96258d940d 4835 #define SYSCON_DMICCLKSEL_SEL_MASK (0x7U)
Kojto 148:fd96258d940d 4836 #define SYSCON_DMICCLKSEL_SEL_SHIFT (0U)
Kojto 148:fd96258d940d 4837 #define SYSCON_DMICCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKSEL_SEL_SHIFT)) & SYSCON_DMICCLKSEL_SEL_MASK)
Kojto 148:fd96258d940d 4838
Kojto 148:fd96258d940d 4839 /*! @name SYSTICKCLKDIV - SYSTICK clock divider */
Kojto 148:fd96258d940d 4840 #define SYSCON_SYSTICKCLKDIV_DIV_MASK (0xFFU)
Kojto 148:fd96258d940d 4841 #define SYSCON_SYSTICKCLKDIV_DIV_SHIFT (0U)
Kojto 148:fd96258d940d 4842 #define SYSCON_SYSTICKCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV_DIV_MASK)
Kojto 148:fd96258d940d 4843 #define SYSCON_SYSTICKCLKDIV_RESET_MASK (0x20000000U)
Kojto 148:fd96258d940d 4844 #define SYSCON_SYSTICKCLKDIV_RESET_SHIFT (29U)
Kojto 148:fd96258d940d 4845 #define SYSCON_SYSTICKCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV_RESET_MASK)
Kojto 148:fd96258d940d 4846 #define SYSCON_SYSTICKCLKDIV_HALT_MASK (0x40000000U)
Kojto 148:fd96258d940d 4847 #define SYSCON_SYSTICKCLKDIV_HALT_SHIFT (30U)
Kojto 148:fd96258d940d 4848 #define SYSCON_SYSTICKCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV_HALT_MASK)
Kojto 148:fd96258d940d 4849
Kojto 148:fd96258d940d 4850 /*! @name TRACECLKDIV - Trace clock divider */
Kojto 148:fd96258d940d 4851 #define SYSCON_TRACECLKDIV_DIV_MASK (0xFFU)
Kojto 148:fd96258d940d 4852 #define SYSCON_TRACECLKDIV_DIV_SHIFT (0U)
Kojto 148:fd96258d940d 4853 #define SYSCON_TRACECLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_DIV_SHIFT)) & SYSCON_TRACECLKDIV_DIV_MASK)
Kojto 148:fd96258d940d 4854 #define SYSCON_TRACECLKDIV_RESET_MASK (0x20000000U)
Kojto 148:fd96258d940d 4855 #define SYSCON_TRACECLKDIV_RESET_SHIFT (29U)
Kojto 148:fd96258d940d 4856 #define SYSCON_TRACECLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_RESET_SHIFT)) & SYSCON_TRACECLKDIV_RESET_MASK)
Kojto 148:fd96258d940d 4857 #define SYSCON_TRACECLKDIV_HALT_MASK (0x40000000U)
Kojto 148:fd96258d940d 4858 #define SYSCON_TRACECLKDIV_HALT_SHIFT (30U)
Kojto 148:fd96258d940d 4859 #define SYSCON_TRACECLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_HALT_SHIFT)) & SYSCON_TRACECLKDIV_HALT_MASK)
Kojto 148:fd96258d940d 4860
Kojto 148:fd96258d940d 4861 /*! @name AHBCLKDIV - AHB clock divider */
Kojto 148:fd96258d940d 4862 #define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU)
Kojto 148:fd96258d940d 4863 #define SYSCON_AHBCLKDIV_DIV_SHIFT (0U)
Kojto 148:fd96258d940d 4864 #define SYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK)
Kojto 148:fd96258d940d 4865 #define SYSCON_AHBCLKDIV_RESET_MASK (0x20000000U)
Kojto 148:fd96258d940d 4866 #define SYSCON_AHBCLKDIV_RESET_SHIFT (29U)
Kojto 148:fd96258d940d 4867 #define SYSCON_AHBCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_RESET_SHIFT)) & SYSCON_AHBCLKDIV_RESET_MASK)
Kojto 148:fd96258d940d 4868 #define SYSCON_AHBCLKDIV_HALT_MASK (0x40000000U)
Kojto 148:fd96258d940d 4869 #define SYSCON_AHBCLKDIV_HALT_SHIFT (30U)
Kojto 148:fd96258d940d 4870 #define SYSCON_AHBCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_HALT_SHIFT)) & SYSCON_AHBCLKDIV_HALT_MASK)
Kojto 148:fd96258d940d 4871
Kojto 148:fd96258d940d 4872 /*! @name CLKOUTDIV - CLKOUT clock divider */
Kojto 148:fd96258d940d 4873 #define SYSCON_CLKOUTDIV_DIV_MASK (0xFFU)
Kojto 148:fd96258d940d 4874 #define SYSCON_CLKOUTDIV_DIV_SHIFT (0U)
Kojto 148:fd96258d940d 4875 #define SYSCON_CLKOUTDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK)
Kojto 148:fd96258d940d 4876 #define SYSCON_CLKOUTDIV_RESET_MASK (0x20000000U)
Kojto 148:fd96258d940d 4877 #define SYSCON_CLKOUTDIV_RESET_SHIFT (29U)
Kojto 148:fd96258d940d 4878 #define SYSCON_CLKOUTDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK)
Kojto 148:fd96258d940d 4879 #define SYSCON_CLKOUTDIV_HALT_MASK (0x40000000U)
Kojto 148:fd96258d940d 4880 #define SYSCON_CLKOUTDIV_HALT_SHIFT (30U)
Kojto 148:fd96258d940d 4881 #define SYSCON_CLKOUTDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK)
Kojto 148:fd96258d940d 4882
Kojto 148:fd96258d940d 4883 /*! @name SPIFICLKDIV - SPIFI clock divider */
Kojto 148:fd96258d940d 4884 #define SYSCON_SPIFICLKDIV_DIV_MASK (0xFFU)
Kojto 148:fd96258d940d 4885 #define SYSCON_SPIFICLKDIV_DIV_SHIFT (0U)
Kojto 148:fd96258d940d 4886 #define SYSCON_SPIFICLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_DIV_SHIFT)) & SYSCON_SPIFICLKDIV_DIV_MASK)
Kojto 148:fd96258d940d 4887 #define SYSCON_SPIFICLKDIV_RESET_MASK (0x20000000U)
Kojto 148:fd96258d940d 4888 #define SYSCON_SPIFICLKDIV_RESET_SHIFT (29U)
Kojto 148:fd96258d940d 4889 #define SYSCON_SPIFICLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_RESET_SHIFT)) & SYSCON_SPIFICLKDIV_RESET_MASK)
Kojto 148:fd96258d940d 4890 #define SYSCON_SPIFICLKDIV_HALT_MASK (0x40000000U)
Kojto 148:fd96258d940d 4891 #define SYSCON_SPIFICLKDIV_HALT_SHIFT (30U)
Kojto 148:fd96258d940d 4892 #define SYSCON_SPIFICLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_HALT_SHIFT)) & SYSCON_SPIFICLKDIV_HALT_MASK)
Kojto 148:fd96258d940d 4893
Kojto 148:fd96258d940d 4894 /*! @name ADCCLKDIV - ADC clock divider */
Kojto 148:fd96258d940d 4895 #define SYSCON_ADCCLKDIV_DIV_MASK (0xFFU)
Kojto 148:fd96258d940d 4896 #define SYSCON_ADCCLKDIV_DIV_SHIFT (0U)
Kojto 148:fd96258d940d 4897 #define SYSCON_ADCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK)
Kojto 148:fd96258d940d 4898 #define SYSCON_ADCCLKDIV_RESET_MASK (0x20000000U)
Kojto 148:fd96258d940d 4899 #define SYSCON_ADCCLKDIV_RESET_SHIFT (29U)
Kojto 148:fd96258d940d 4900 #define SYSCON_ADCCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_RESET_SHIFT)) & SYSCON_ADCCLKDIV_RESET_MASK)
Kojto 148:fd96258d940d 4901 #define SYSCON_ADCCLKDIV_HALT_MASK (0x40000000U)
Kojto 148:fd96258d940d 4902 #define SYSCON_ADCCLKDIV_HALT_SHIFT (30U)
Kojto 148:fd96258d940d 4903 #define SYSCON_ADCCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_HALT_SHIFT)) & SYSCON_ADCCLKDIV_HALT_MASK)
Kojto 148:fd96258d940d 4904
Kojto 148:fd96258d940d 4905 /*! @name USBCLKDIV - USB clock divider */
Kojto 148:fd96258d940d 4906 #define SYSCON_USBCLKDIV_DIV_MASK (0xFFU)
Kojto 148:fd96258d940d 4907 #define SYSCON_USBCLKDIV_DIV_SHIFT (0U)
Kojto 148:fd96258d940d 4908 #define SYSCON_USBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKDIV_DIV_SHIFT)) & SYSCON_USBCLKDIV_DIV_MASK)
Kojto 148:fd96258d940d 4909 #define SYSCON_USBCLKDIV_RESET_MASK (0x20000000U)
Kojto 148:fd96258d940d 4910 #define SYSCON_USBCLKDIV_RESET_SHIFT (29U)
Kojto 148:fd96258d940d 4911 #define SYSCON_USBCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKDIV_RESET_SHIFT)) & SYSCON_USBCLKDIV_RESET_MASK)
Kojto 148:fd96258d940d 4912 #define SYSCON_USBCLKDIV_HALT_MASK (0x40000000U)
Kojto 148:fd96258d940d 4913 #define SYSCON_USBCLKDIV_HALT_SHIFT (30U)
Kojto 148:fd96258d940d 4914 #define SYSCON_USBCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKDIV_HALT_SHIFT)) & SYSCON_USBCLKDIV_HALT_MASK)
Kojto 148:fd96258d940d 4915
Kojto 148:fd96258d940d 4916 /*! @name FRGCTRL - Fractional rate divider */
Kojto 148:fd96258d940d 4917 #define SYSCON_FRGCTRL_DIV_MASK (0xFFU)
Kojto 148:fd96258d940d 4918 #define SYSCON_FRGCTRL_DIV_SHIFT (0U)
Kojto 148:fd96258d940d 4919 #define SYSCON_FRGCTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_DIV_SHIFT)) & SYSCON_FRGCTRL_DIV_MASK)
Kojto 148:fd96258d940d 4920 #define SYSCON_FRGCTRL_MULT_MASK (0xFF00U)
Kojto 148:fd96258d940d 4921 #define SYSCON_FRGCTRL_MULT_SHIFT (8U)
Kojto 148:fd96258d940d 4922 #define SYSCON_FRGCTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_MULT_SHIFT)) & SYSCON_FRGCTRL_MULT_MASK)
Kojto 148:fd96258d940d 4923
Kojto 148:fd96258d940d 4924 /*! @name DMICCLKDIV - DMIC clock divider */
Kojto 148:fd96258d940d 4925 #define SYSCON_DMICCLKDIV_DIV_MASK (0xFFU)
Kojto 148:fd96258d940d 4926 #define SYSCON_DMICCLKDIV_DIV_SHIFT (0U)
Kojto 148:fd96258d940d 4927 #define SYSCON_DMICCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_DIV_SHIFT)) & SYSCON_DMICCLKDIV_DIV_MASK)
Kojto 148:fd96258d940d 4928 #define SYSCON_DMICCLKDIV_RESET_MASK (0x20000000U)
Kojto 148:fd96258d940d 4929 #define SYSCON_DMICCLKDIV_RESET_SHIFT (29U)
Kojto 148:fd96258d940d 4930 #define SYSCON_DMICCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_RESET_SHIFT)) & SYSCON_DMICCLKDIV_RESET_MASK)
Kojto 148:fd96258d940d 4931 #define SYSCON_DMICCLKDIV_HALT_MASK (0x40000000U)
Kojto 148:fd96258d940d 4932 #define SYSCON_DMICCLKDIV_HALT_SHIFT (30U)
Kojto 148:fd96258d940d 4933 #define SYSCON_DMICCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_HALT_SHIFT)) & SYSCON_DMICCLKDIV_HALT_MASK)
Kojto 148:fd96258d940d 4934
Kojto 148:fd96258d940d 4935 /*! @name MCLKDIV - I2S MCLK clock divider */
Kojto 148:fd96258d940d 4936 #define SYSCON_MCLKDIV_DIV_MASK (0xFFU)
Kojto 148:fd96258d940d 4937 #define SYSCON_MCLKDIV_DIV_SHIFT (0U)
Kojto 148:fd96258d940d 4938 #define SYSCON_MCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK)
Kojto 148:fd96258d940d 4939 #define SYSCON_MCLKDIV_RESET_MASK (0x20000000U)
Kojto 148:fd96258d940d 4940 #define SYSCON_MCLKDIV_RESET_SHIFT (29U)
Kojto 148:fd96258d940d 4941 #define SYSCON_MCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_RESET_SHIFT)) & SYSCON_MCLKDIV_RESET_MASK)
Kojto 148:fd96258d940d 4942 #define SYSCON_MCLKDIV_HALT_MASK (0x40000000U)
Kojto 148:fd96258d940d 4943 #define SYSCON_MCLKDIV_HALT_SHIFT (30U)
Kojto 148:fd96258d940d 4944 #define SYSCON_MCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_HALT_SHIFT)) & SYSCON_MCLKDIV_HALT_MASK)
Kojto 148:fd96258d940d 4945
Kojto 148:fd96258d940d 4946 /*! @name FLASHCFG - Flash wait states configuration */
Kojto 148:fd96258d940d 4947 #define SYSCON_FLASHCFG_FETCHCFG_MASK (0x3U)
Kojto 148:fd96258d940d 4948 #define SYSCON_FLASHCFG_FETCHCFG_SHIFT (0U)
Kojto 148:fd96258d940d 4949 #define SYSCON_FLASHCFG_FETCHCFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_FETCHCFG_SHIFT)) & SYSCON_FLASHCFG_FETCHCFG_MASK)
Kojto 148:fd96258d940d 4950 #define SYSCON_FLASHCFG_DATACFG_MASK (0xCU)
Kojto 148:fd96258d940d 4951 #define SYSCON_FLASHCFG_DATACFG_SHIFT (2U)
Kojto 148:fd96258d940d 4952 #define SYSCON_FLASHCFG_DATACFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_DATACFG_SHIFT)) & SYSCON_FLASHCFG_DATACFG_MASK)
Kojto 148:fd96258d940d 4953 #define SYSCON_FLASHCFG_ACCEL_MASK (0x10U)
Kojto 148:fd96258d940d 4954 #define SYSCON_FLASHCFG_ACCEL_SHIFT (4U)
Kojto 148:fd96258d940d 4955 #define SYSCON_FLASHCFG_ACCEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_ACCEL_SHIFT)) & SYSCON_FLASHCFG_ACCEL_MASK)
Kojto 148:fd96258d940d 4956 #define SYSCON_FLASHCFG_PREFEN_MASK (0x20U)
Kojto 148:fd96258d940d 4957 #define SYSCON_FLASHCFG_PREFEN_SHIFT (5U)
Kojto 148:fd96258d940d 4958 #define SYSCON_FLASHCFG_PREFEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_PREFEN_SHIFT)) & SYSCON_FLASHCFG_PREFEN_MASK)
Kojto 148:fd96258d940d 4959 #define SYSCON_FLASHCFG_PREFOVR_MASK (0x40U)
Kojto 148:fd96258d940d 4960 #define SYSCON_FLASHCFG_PREFOVR_SHIFT (6U)
Kojto 148:fd96258d940d 4961 #define SYSCON_FLASHCFG_PREFOVR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_PREFOVR_SHIFT)) & SYSCON_FLASHCFG_PREFOVR_MASK)
Kojto 148:fd96258d940d 4962 #define SYSCON_FLASHCFG_FLASHTIM_MASK (0xF000U)
Kojto 148:fd96258d940d 4963 #define SYSCON_FLASHCFG_FLASHTIM_SHIFT (12U)
Kojto 148:fd96258d940d 4964 #define SYSCON_FLASHCFG_FLASHTIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_FLASHTIM_SHIFT)) & SYSCON_FLASHCFG_FLASHTIM_MASK)
Kojto 148:fd96258d940d 4965
Kojto 148:fd96258d940d 4966 /*! @name USBCLKCTRL - USB clock control */
Kojto 148:fd96258d940d 4967 #define SYSCON_USBCLKCTRL_POL_CLK_MASK (0x2U)
Kojto 148:fd96258d940d 4968 #define SYSCON_USBCLKCTRL_POL_CLK_SHIFT (1U)
Kojto 148:fd96258d940d 4969 #define SYSCON_USBCLKCTRL_POL_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKCTRL_POL_CLK_SHIFT)) & SYSCON_USBCLKCTRL_POL_CLK_MASK)
Kojto 148:fd96258d940d 4970
Kojto 148:fd96258d940d 4971 /*! @name USBCLKSTAT - USB clock status */
Kojto 148:fd96258d940d 4972 #define SYSCON_USBCLKSTAT_NEED_CLKST_MASK (0x1U)
Kojto 148:fd96258d940d 4973 #define SYSCON_USBCLKSTAT_NEED_CLKST_SHIFT (0U)
Kojto 148:fd96258d940d 4974 #define SYSCON_USBCLKSTAT_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKSTAT_NEED_CLKST_SHIFT)) & SYSCON_USBCLKSTAT_NEED_CLKST_MASK)
Kojto 148:fd96258d940d 4975
Kojto 148:fd96258d940d 4976 /*! @name FREQMECTRL - Frequency measure register */
Kojto 148:fd96258d940d 4977 #define SYSCON_FREQMECTRL_CAPVAL_MASK (0x3FFFU)
Kojto 148:fd96258d940d 4978 #define SYSCON_FREQMECTRL_CAPVAL_SHIFT (0U)
Kojto 148:fd96258d940d 4979 #define SYSCON_FREQMECTRL_CAPVAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_CAPVAL_SHIFT)) & SYSCON_FREQMECTRL_CAPVAL_MASK)
Kojto 148:fd96258d940d 4980 #define SYSCON_FREQMECTRL_PROG_MASK (0x80000000U)
Kojto 148:fd96258d940d 4981 #define SYSCON_FREQMECTRL_PROG_SHIFT (31U)
Kojto 148:fd96258d940d 4982 #define SYSCON_FREQMECTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_PROG_SHIFT)) & SYSCON_FREQMECTRL_PROG_MASK)
Kojto 148:fd96258d940d 4983
Kojto 148:fd96258d940d 4984 /*! @name MCLKIO - MCLK input/output control */
Kojto 148:fd96258d940d 4985 #define SYSCON_MCLKIO_DIR_MASK (0x1U)
Kojto 148:fd96258d940d 4986 #define SYSCON_MCLKIO_DIR_SHIFT (0U)
Kojto 148:fd96258d940d 4987 #define SYSCON_MCLKIO_DIR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_DIR_SHIFT)) & SYSCON_MCLKIO_DIR_MASK)
Kojto 148:fd96258d940d 4988
Kojto 148:fd96258d940d 4989 /*! @name FROCTRL - FRO oscillator control */
Kojto 148:fd96258d940d 4990 #define SYSCON_FROCTRL_TRIM_MASK (0x3FFFU)
Kojto 148:fd96258d940d 4991 #define SYSCON_FROCTRL_TRIM_SHIFT (0U)
Kojto 148:fd96258d940d 4992 #define SYSCON_FROCTRL_TRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_TRIM_SHIFT)) & SYSCON_FROCTRL_TRIM_MASK)
Kojto 148:fd96258d940d 4993 #define SYSCON_FROCTRL_SEL_MASK (0x4000U)
Kojto 148:fd96258d940d 4994 #define SYSCON_FROCTRL_SEL_SHIFT (14U)
Kojto 148:fd96258d940d 4995 #define SYSCON_FROCTRL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_SEL_SHIFT)) & SYSCON_FROCTRL_SEL_MASK)
Kojto 148:fd96258d940d 4996 #define SYSCON_FROCTRL_FREQTRIM_MASK (0xFF0000U)
Kojto 148:fd96258d940d 4997 #define SYSCON_FROCTRL_FREQTRIM_SHIFT (16U)
Kojto 148:fd96258d940d 4998 #define SYSCON_FROCTRL_FREQTRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_FREQTRIM_SHIFT)) & SYSCON_FROCTRL_FREQTRIM_MASK)
Kojto 148:fd96258d940d 4999 #define SYSCON_FROCTRL_USBCLKADJ_MASK (0x1000000U)
Kojto 148:fd96258d940d 5000 #define SYSCON_FROCTRL_USBCLKADJ_SHIFT (24U)
Kojto 148:fd96258d940d 5001 #define SYSCON_FROCTRL_USBCLKADJ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_USBCLKADJ_SHIFT)) & SYSCON_FROCTRL_USBCLKADJ_MASK)
Kojto 148:fd96258d940d 5002 #define SYSCON_FROCTRL_USBMODCHG_MASK (0x2000000U)
Kojto 148:fd96258d940d 5003 #define SYSCON_FROCTRL_USBMODCHG_SHIFT (25U)
Kojto 148:fd96258d940d 5004 #define SYSCON_FROCTRL_USBMODCHG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_USBMODCHG_SHIFT)) & SYSCON_FROCTRL_USBMODCHG_MASK)
Kojto 148:fd96258d940d 5005 #define SYSCON_FROCTRL_HSPDCLK_MASK (0x40000000U)
Kojto 148:fd96258d940d 5006 #define SYSCON_FROCTRL_HSPDCLK_SHIFT (30U)
Kojto 148:fd96258d940d 5007 #define SYSCON_FROCTRL_HSPDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_HSPDCLK_SHIFT)) & SYSCON_FROCTRL_HSPDCLK_MASK)
Kojto 148:fd96258d940d 5008 #define SYSCON_FROCTRL_WRTRIM_MASK (0x80000000U)
Kojto 148:fd96258d940d 5009 #define SYSCON_FROCTRL_WRTRIM_SHIFT (31U)
Kojto 148:fd96258d940d 5010 #define SYSCON_FROCTRL_WRTRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_WRTRIM_SHIFT)) & SYSCON_FROCTRL_WRTRIM_MASK)
Kojto 148:fd96258d940d 5011
Kojto 148:fd96258d940d 5012 /*! @name WDTOSCCTRL - Watchdog oscillator control */
Kojto 148:fd96258d940d 5013 #define SYSCON_WDTOSCCTRL_DIVSEL_MASK (0x1FU)
Kojto 148:fd96258d940d 5014 #define SYSCON_WDTOSCCTRL_DIVSEL_SHIFT (0U)
Kojto 148:fd96258d940d 5015 #define SYSCON_WDTOSCCTRL_DIVSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_DIVSEL_SHIFT)) & SYSCON_WDTOSCCTRL_DIVSEL_MASK)
Kojto 148:fd96258d940d 5016 #define SYSCON_WDTOSCCTRL_FREQSEL_MASK (0x3E0U)
Kojto 148:fd96258d940d 5017 #define SYSCON_WDTOSCCTRL_FREQSEL_SHIFT (5U)
Kojto 148:fd96258d940d 5018 #define SYSCON_WDTOSCCTRL_FREQSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)) & SYSCON_WDTOSCCTRL_FREQSEL_MASK)
Kojto 148:fd96258d940d 5019
Kojto 148:fd96258d940d 5020 /*! @name RTCOSCCTRL - RTC oscillator 32 kHz output control */
Kojto 148:fd96258d940d 5021 #define SYSCON_RTCOSCCTRL_EN_MASK (0x1U)
Kojto 148:fd96258d940d 5022 #define SYSCON_RTCOSCCTRL_EN_SHIFT (0U)
Kojto 148:fd96258d940d 5023 #define SYSCON_RTCOSCCTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_RTCOSCCTRL_EN_SHIFT)) & SYSCON_RTCOSCCTRL_EN_MASK)
Kojto 148:fd96258d940d 5024
Kojto 148:fd96258d940d 5025 /*! @name SYSPLLCTRL - PLL control */
Kojto 148:fd96258d940d 5026 #define SYSCON_SYSPLLCTRL_SELR_MASK (0xFU)
Kojto 148:fd96258d940d 5027 #define SYSCON_SYSPLLCTRL_SELR_SHIFT (0U)
Kojto 148:fd96258d940d 5028 #define SYSCON_SYSPLLCTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELR_SHIFT)) & SYSCON_SYSPLLCTRL_SELR_MASK)
Kojto 148:fd96258d940d 5029 #define SYSCON_SYSPLLCTRL_SELI_MASK (0x3F0U)
Kojto 148:fd96258d940d 5030 #define SYSCON_SYSPLLCTRL_SELI_SHIFT (4U)
Kojto 148:fd96258d940d 5031 #define SYSCON_SYSPLLCTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELI_SHIFT)) & SYSCON_SYSPLLCTRL_SELI_MASK)
Kojto 148:fd96258d940d 5032 #define SYSCON_SYSPLLCTRL_SELP_MASK (0x7C00U)
Kojto 148:fd96258d940d 5033 #define SYSCON_SYSPLLCTRL_SELP_SHIFT (10U)
Kojto 148:fd96258d940d 5034 #define SYSCON_SYSPLLCTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELP_SHIFT)) & SYSCON_SYSPLLCTRL_SELP_MASK)
Kojto 148:fd96258d940d 5035 #define SYSCON_SYSPLLCTRL_BYPASS_MASK (0x8000U)
Kojto 148:fd96258d940d 5036 #define SYSCON_SYSPLLCTRL_BYPASS_SHIFT (15U)
Kojto 148:fd96258d940d 5037 #define SYSCON_SYSPLLCTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_BYPASS_SHIFT)) & SYSCON_SYSPLLCTRL_BYPASS_MASK)
Kojto 148:fd96258d940d 5038 #define SYSCON_SYSPLLCTRL_BYPASSCCODIV2_MASK (0x10000U)
Kojto 148:fd96258d940d 5039 #define SYSCON_SYSPLLCTRL_BYPASSCCODIV2_SHIFT (16U)
Kojto 148:fd96258d940d 5040 #define SYSCON_SYSPLLCTRL_BYPASSCCODIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_BYPASSCCODIV2_SHIFT)) & SYSCON_SYSPLLCTRL_BYPASSCCODIV2_MASK)
Kojto 148:fd96258d940d 5041 #define SYSCON_SYSPLLCTRL_UPLIMOFF_MASK (0x20000U)
Kojto 148:fd96258d940d 5042 #define SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT (17U)
Kojto 148:fd96258d940d 5043 #define SYSCON_SYSPLLCTRL_UPLIMOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT)) & SYSCON_SYSPLLCTRL_UPLIMOFF_MASK)
Kojto 148:fd96258d940d 5044 #define SYSCON_SYSPLLCTRL_BANDSEL_MASK (0x40000U)
Kojto 148:fd96258d940d 5045 #define SYSCON_SYSPLLCTRL_BANDSEL_SHIFT (18U)
Kojto 148:fd96258d940d 5046 #define SYSCON_SYSPLLCTRL_BANDSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_BANDSEL_SHIFT)) & SYSCON_SYSPLLCTRL_BANDSEL_MASK)
Kojto 148:fd96258d940d 5047 #define SYSCON_SYSPLLCTRL_DIRECTI_MASK (0x80000U)
Kojto 148:fd96258d940d 5048 #define SYSCON_SYSPLLCTRL_DIRECTI_SHIFT (19U)
Kojto 148:fd96258d940d 5049 #define SYSCON_SYSPLLCTRL_DIRECTI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT)) & SYSCON_SYSPLLCTRL_DIRECTI_MASK)
Kojto 148:fd96258d940d 5050 #define SYSCON_SYSPLLCTRL_DIRECTO_MASK (0x100000U)
Kojto 148:fd96258d940d 5051 #define SYSCON_SYSPLLCTRL_DIRECTO_SHIFT (20U)
Kojto 148:fd96258d940d 5052 #define SYSCON_SYSPLLCTRL_DIRECTO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_DIRECTO_SHIFT)) & SYSCON_SYSPLLCTRL_DIRECTO_MASK)
Kojto 148:fd96258d940d 5053
Kojto 148:fd96258d940d 5054 /*! @name SYSPLLSTAT - PLL status */
Kojto 148:fd96258d940d 5055 #define SYSCON_SYSPLLSTAT_LOCK_MASK (0x1U)
Kojto 148:fd96258d940d 5056 #define SYSCON_SYSPLLSTAT_LOCK_SHIFT (0U)
Kojto 148:fd96258d940d 5057 #define SYSCON_SYSPLLSTAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSTAT_LOCK_SHIFT)) & SYSCON_SYSPLLSTAT_LOCK_MASK)
Kojto 148:fd96258d940d 5058
Kojto 148:fd96258d940d 5059 /*! @name SYSPLLNDEC - PLL N decoder */
Kojto 148:fd96258d940d 5060 #define SYSCON_SYSPLLNDEC_NDEC_MASK (0x3FFU)
Kojto 148:fd96258d940d 5061 #define SYSCON_SYSPLLNDEC_NDEC_SHIFT (0U)
Kojto 148:fd96258d940d 5062 #define SYSCON_SYSPLLNDEC_NDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NDEC_SHIFT)) & SYSCON_SYSPLLNDEC_NDEC_MASK)
Kojto 148:fd96258d940d 5063 #define SYSCON_SYSPLLNDEC_NREQ_MASK (0x400U)
Kojto 148:fd96258d940d 5064 #define SYSCON_SYSPLLNDEC_NREQ_SHIFT (10U)
Kojto 148:fd96258d940d 5065 #define SYSCON_SYSPLLNDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NREQ_SHIFT)) & SYSCON_SYSPLLNDEC_NREQ_MASK)
Kojto 148:fd96258d940d 5066
Kojto 148:fd96258d940d 5067 /*! @name SYSPLLPDEC - PLL P decoder */
Kojto 148:fd96258d940d 5068 #define SYSCON_SYSPLLPDEC_PDEC_MASK (0x7FU)
Kojto 148:fd96258d940d 5069 #define SYSCON_SYSPLLPDEC_PDEC_SHIFT (0U)
Kojto 148:fd96258d940d 5070 #define SYSCON_SYSPLLPDEC_PDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PDEC_SHIFT)) & SYSCON_SYSPLLPDEC_PDEC_MASK)
Kojto 148:fd96258d940d 5071 #define SYSCON_SYSPLLPDEC_PREQ_MASK (0x80U)
Kojto 148:fd96258d940d 5072 #define SYSCON_SYSPLLPDEC_PREQ_SHIFT (7U)
Kojto 148:fd96258d940d 5073 #define SYSCON_SYSPLLPDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PREQ_SHIFT)) & SYSCON_SYSPLLPDEC_PREQ_MASK)
Kojto 148:fd96258d940d 5074
Kojto 148:fd96258d940d 5075 /*! @name SYSPLLSSCTRL0 - PLL spread spectrum control 0 */
Kojto 148:fd96258d940d 5076 #define SYSCON_SYSPLLSSCTRL0_MDEC_MASK (0x1FFFFU)
Kojto 148:fd96258d940d 5077 #define SYSCON_SYSPLLSSCTRL0_MDEC_SHIFT (0U)
Kojto 148:fd96258d940d 5078 #define SYSCON_SYSPLLSSCTRL0_MDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL0_MDEC_SHIFT)) & SYSCON_SYSPLLSSCTRL0_MDEC_MASK)
Kojto 148:fd96258d940d 5079 #define SYSCON_SYSPLLSSCTRL0_MREQ_MASK (0x20000U)
Kojto 148:fd96258d940d 5080 #define SYSCON_SYSPLLSSCTRL0_MREQ_SHIFT (17U)
Kojto 148:fd96258d940d 5081 #define SYSCON_SYSPLLSSCTRL0_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL0_MREQ_SHIFT)) & SYSCON_SYSPLLSSCTRL0_MREQ_MASK)
Kojto 148:fd96258d940d 5082 #define SYSCON_SYSPLLSSCTRL0_SEL_EXT_MASK (0x40000U)
Kojto 148:fd96258d940d 5083 #define SYSCON_SYSPLLSSCTRL0_SEL_EXT_SHIFT (18U)
Kojto 148:fd96258d940d 5084 #define SYSCON_SYSPLLSSCTRL0_SEL_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL0_SEL_EXT_SHIFT)) & SYSCON_SYSPLLSSCTRL0_SEL_EXT_MASK)
Kojto 148:fd96258d940d 5085
Kojto 148:fd96258d940d 5086 /*! @name SYSPLLSSCTRL1 - PLL spread spectrum control 1 */
Kojto 148:fd96258d940d 5087 #define SYSCON_SYSPLLSSCTRL1_MD_MASK (0x7FFFFU)
Kojto 148:fd96258d940d 5088 #define SYSCON_SYSPLLSSCTRL1_MD_SHIFT (0U)
Kojto 148:fd96258d940d 5089 #define SYSCON_SYSPLLSSCTRL1_MD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MD_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MD_MASK)
Kojto 148:fd96258d940d 5090 #define SYSCON_SYSPLLSSCTRL1_MDREQ_MASK (0x80000U)
Kojto 148:fd96258d940d 5091 #define SYSCON_SYSPLLSSCTRL1_MDREQ_SHIFT (19U)
Kojto 148:fd96258d940d 5092 #define SYSCON_SYSPLLSSCTRL1_MDREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MDREQ_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MDREQ_MASK)
Kojto 148:fd96258d940d 5093 #define SYSCON_SYSPLLSSCTRL1_MF_MASK (0x700000U)
Kojto 148:fd96258d940d 5094 #define SYSCON_SYSPLLSSCTRL1_MF_SHIFT (20U)
Kojto 148:fd96258d940d 5095 #define SYSCON_SYSPLLSSCTRL1_MF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MF_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MF_MASK)
Kojto 148:fd96258d940d 5096 #define SYSCON_SYSPLLSSCTRL1_MR_MASK (0x3800000U)
Kojto 148:fd96258d940d 5097 #define SYSCON_SYSPLLSSCTRL1_MR_SHIFT (23U)
Kojto 148:fd96258d940d 5098 #define SYSCON_SYSPLLSSCTRL1_MR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MR_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MR_MASK)
Kojto 148:fd96258d940d 5099 #define SYSCON_SYSPLLSSCTRL1_MC_MASK (0xC000000U)
Kojto 148:fd96258d940d 5100 #define SYSCON_SYSPLLSSCTRL1_MC_SHIFT (26U)
Kojto 148:fd96258d940d 5101 #define SYSCON_SYSPLLSSCTRL1_MC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MC_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MC_MASK)
Kojto 148:fd96258d940d 5102 #define SYSCON_SYSPLLSSCTRL1_PD_MASK (0x10000000U)
Kojto 148:fd96258d940d 5103 #define SYSCON_SYSPLLSSCTRL1_PD_SHIFT (28U)
Kojto 148:fd96258d940d 5104 #define SYSCON_SYSPLLSSCTRL1_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_PD_SHIFT)) & SYSCON_SYSPLLSSCTRL1_PD_MASK)
Kojto 148:fd96258d940d 5105 #define SYSCON_SYSPLLSSCTRL1_DITHER_MASK (0x20000000U)
Kojto 148:fd96258d940d 5106 #define SYSCON_SYSPLLSSCTRL1_DITHER_SHIFT (29U)
Kojto 148:fd96258d940d 5107 #define SYSCON_SYSPLLSSCTRL1_DITHER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_DITHER_SHIFT)) & SYSCON_SYSPLLSSCTRL1_DITHER_MASK)
Kojto 148:fd96258d940d 5108
Kojto 148:fd96258d940d 5109 /*! @name PDSLEEPCFG - Sleep configuration register n */
Kojto 148:fd96258d940d 5110 #define SYSCON_PDSLEEPCFG_PD_SLEEP_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 5111 #define SYSCON_PDSLEEPCFG_PD_SLEEP_SHIFT (0U)
Kojto 148:fd96258d940d 5112 #define SYSCON_PDSLEEPCFG_PD_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PD_SLEEP_SHIFT)) & SYSCON_PDSLEEPCFG_PD_SLEEP_MASK)
Kojto 148:fd96258d940d 5113
Kojto 148:fd96258d940d 5114 /* The count of SYSCON_PDSLEEPCFG */
Kojto 148:fd96258d940d 5115 #define SYSCON_PDSLEEPCFG_COUNT (2U)
Kojto 148:fd96258d940d 5116
Kojto 148:fd96258d940d 5117 /*! @name PDRUNCFG - Power configuration register n */
Kojto 148:fd96258d940d 5118 #define SYSCON_PDRUNCFG_PDEN_FRO_MASK (0x10U)
Kojto 148:fd96258d940d 5119 #define SYSCON_PDRUNCFG_PDEN_FRO_SHIFT (4U)
Kojto 148:fd96258d940d 5120 #define SYSCON_PDRUNCFG_PDEN_FRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFG_PDEN_FRO_MASK)
Kojto 148:fd96258d940d 5121 #define SYSCON_PDRUNCFG_PD_FLASH_MASK (0x20U)
Kojto 148:fd96258d940d 5122 #define SYSCON_PDRUNCFG_PD_FLASH_SHIFT (5U)
Kojto 148:fd96258d940d 5123 #define SYSCON_PDRUNCFG_PD_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PD_FLASH_SHIFT)) & SYSCON_PDRUNCFG_PD_FLASH_MASK)
Kojto 148:fd96258d940d 5124 #define SYSCON_PDRUNCFG_PDEN_TS_MASK (0x40U)
Kojto 148:fd96258d940d 5125 #define SYSCON_PDRUNCFG_PDEN_TS_SHIFT (6U)
Kojto 148:fd96258d940d 5126 #define SYSCON_PDRUNCFG_PDEN_TS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFG_PDEN_TS_MASK)
Kojto 148:fd96258d940d 5127 #define SYSCON_PDRUNCFG_PDEN_BOD_RST_MASK (0x80U)
Kojto 148:fd96258d940d 5128 #define SYSCON_PDRUNCFG_PDEN_BOD_RST_SHIFT (7U)
Kojto 148:fd96258d940d 5129 #define SYSCON_PDRUNCFG_PDEN_BOD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFG_PDEN_BOD_RST_MASK)
Kojto 148:fd96258d940d 5130 #define SYSCON_PDRUNCFG_PDEN_BOD_INTR_MASK (0x100U)
Kojto 148:fd96258d940d 5131 #define SYSCON_PDRUNCFG_PDEN_BOD_INTR_SHIFT (8U)
Kojto 148:fd96258d940d 5132 #define SYSCON_PDRUNCFG_PDEN_BOD_INTR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFG_PDEN_BOD_INTR_MASK)
Kojto 148:fd96258d940d 5133 #define SYSCON_PDRUNCFG_PDEN_ADC0_MASK (0x400U)
Kojto 148:fd96258d940d 5134 #define SYSCON_PDRUNCFG_PDEN_ADC0_SHIFT (10U)
Kojto 148:fd96258d940d 5135 #define SYSCON_PDRUNCFG_PDEN_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFG_PDEN_ADC0_MASK)
Kojto 148:fd96258d940d 5136 #define SYSCON_PDRUNCFG_PD_VDDFLASH_MASK (0x800U)
Kojto 148:fd96258d940d 5137 #define SYSCON_PDRUNCFG_PD_VDDFLASH_SHIFT (11U)
Kojto 148:fd96258d940d 5138 #define SYSCON_PDRUNCFG_PD_VDDFLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PD_VDDFLASH_SHIFT)) & SYSCON_PDRUNCFG_PD_VDDFLASH_MASK)
Kojto 148:fd96258d940d 5139 #define SYSCON_PDRUNCFG_LP_VDDFLASH_MASK (0x1000U)
Kojto 148:fd96258d940d 5140 #define SYSCON_PDRUNCFG_LP_VDDFLASH_SHIFT (12U)
Kojto 148:fd96258d940d 5141 #define SYSCON_PDRUNCFG_LP_VDDFLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_LP_VDDFLASH_SHIFT)) & SYSCON_PDRUNCFG_LP_VDDFLASH_MASK)
Kojto 148:fd96258d940d 5142 #define SYSCON_PDRUNCFG_PDEN_SRAM0_MASK (0x2000U)
Kojto 148:fd96258d940d 5143 #define SYSCON_PDRUNCFG_PDEN_SRAM0_SHIFT (13U)
Kojto 148:fd96258d940d 5144 #define SYSCON_PDRUNCFG_PDEN_SRAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM0_MASK)
Kojto 148:fd96258d940d 5145 #define SYSCON_PDRUNCFG_PDEN_SRAM1_MASK (0x4000U)
Kojto 148:fd96258d940d 5146 #define SYSCON_PDRUNCFG_PDEN_SRAM1_SHIFT (14U)
Kojto 148:fd96258d940d 5147 #define SYSCON_PDRUNCFG_PDEN_SRAM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM1_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM1_MASK)
Kojto 148:fd96258d940d 5148 #define SYSCON_PDRUNCFG_PDEN_SRAM2_MASK (0x8000U)
Kojto 148:fd96258d940d 5149 #define SYSCON_PDRUNCFG_PDEN_SRAM2_SHIFT (15U)
Kojto 148:fd96258d940d 5150 #define SYSCON_PDRUNCFG_PDEN_SRAM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM2_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM2_MASK)
Kojto 148:fd96258d940d 5151 #define SYSCON_PDRUNCFG_PDEN_SRAMX_MASK (0x10000U)
Kojto 148:fd96258d940d 5152 #define SYSCON_PDRUNCFG_PDEN_SRAMX_SHIFT (16U)
Kojto 148:fd96258d940d 5153 #define SYSCON_PDRUNCFG_PDEN_SRAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAMX_MASK)
Kojto 148:fd96258d940d 5154 #define SYSCON_PDRUNCFG_PDEN_ROM_MASK (0x20000U)
Kojto 148:fd96258d940d 5155 #define SYSCON_PDRUNCFG_PDEN_ROM_SHIFT (17U)
Kojto 148:fd96258d940d 5156 #define SYSCON_PDRUNCFG_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFG_PDEN_ROM_MASK)
Kojto 148:fd96258d940d 5157 #define SYSCON_PDRUNCFG_PD_VDDHV_ENA_MASK (0x40000U)
Kojto 148:fd96258d940d 5158 #define SYSCON_PDRUNCFG_PD_VDDHV_ENA_SHIFT (18U)
Kojto 148:fd96258d940d 5159 #define SYSCON_PDRUNCFG_PD_VDDHV_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PD_VDDHV_ENA_SHIFT)) & SYSCON_PDRUNCFG_PD_VDDHV_ENA_MASK)
Kojto 148:fd96258d940d 5160 #define SYSCON_PDRUNCFG_PDEN_VDDA_MASK (0x80000U)
Kojto 148:fd96258d940d 5161 #define SYSCON_PDRUNCFG_PDEN_VDDA_SHIFT (19U)
Kojto 148:fd96258d940d 5162 #define SYSCON_PDRUNCFG_PDEN_VDDA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VDDA_MASK)
Kojto 148:fd96258d940d 5163 #define SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK (0x100000U)
Kojto 148:fd96258d940d 5164 #define SYSCON_PDRUNCFG_PDEN_WDT_OSC_SHIFT (20U)
Kojto 148:fd96258d940d 5165 #define SYSCON_PDRUNCFG_PDEN_WDT_OSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK)
Kojto 148:fd96258d940d 5166 #define SYSCON_PDRUNCFG_PDEN_USB_PHY_MASK (0x200000U)
Kojto 148:fd96258d940d 5167 #define SYSCON_PDRUNCFG_PDEN_USB_PHY_SHIFT (21U)
Kojto 148:fd96258d940d 5168 #define SYSCON_PDRUNCFG_PDEN_USB_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB_PHY_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB_PHY_MASK)
Kojto 148:fd96258d940d 5169 #define SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK (0x400000U)
Kojto 148:fd96258d940d 5170 #define SYSCON_PDRUNCFG_PDEN_SYS_PLL_SHIFT (22U)
Kojto 148:fd96258d940d 5171 #define SYSCON_PDRUNCFG_PDEN_SYS_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK)
Kojto 148:fd96258d940d 5172 #define SYSCON_PDRUNCFG_PDEN_VREFP_MASK (0x800000U)
Kojto 148:fd96258d940d 5173 #define SYSCON_PDRUNCFG_PDEN_VREFP_SHIFT (23U)
Kojto 148:fd96258d940d 5174 #define SYSCON_PDRUNCFG_PDEN_VREFP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VREFP_MASK)
Kojto 148:fd96258d940d 5175 #define SYSCON_PDRUNCFG_PD_FLASH_BG_MASK (0x2000000U)
Kojto 148:fd96258d940d 5176 #define SYSCON_PDRUNCFG_PD_FLASH_BG_SHIFT (25U)
Kojto 148:fd96258d940d 5177 #define SYSCON_PDRUNCFG_PD_FLASH_BG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PD_FLASH_BG_SHIFT)) & SYSCON_PDRUNCFG_PD_FLASH_BG_MASK)
Kojto 148:fd96258d940d 5178 #define SYSCON_PDRUNCFG_PD_ALT_FLASH_IBG_MASK (0x10000000U)
Kojto 148:fd96258d940d 5179 #define SYSCON_PDRUNCFG_PD_ALT_FLASH_IBG_SHIFT (28U)
Kojto 148:fd96258d940d 5180 #define SYSCON_PDRUNCFG_PD_ALT_FLASH_IBG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PD_ALT_FLASH_IBG_SHIFT)) & SYSCON_PDRUNCFG_PD_ALT_FLASH_IBG_MASK)
Kojto 148:fd96258d940d 5181 #define SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG_MASK (0x20000000U)
Kojto 148:fd96258d940d 5182 #define SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG_SHIFT (29U)
Kojto 148:fd96258d940d 5183 #define SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG_SHIFT)) & SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG_MASK)
Kojto 148:fd96258d940d 5184
Kojto 148:fd96258d940d 5185 /* The count of SYSCON_PDRUNCFG */
Kojto 148:fd96258d940d 5186 #define SYSCON_PDRUNCFG_COUNT (2U)
Kojto 148:fd96258d940d 5187
Kojto 148:fd96258d940d 5188 /*! @name PDRUNCFGSET - Set bits in PDRUNCFGn */
Kojto 148:fd96258d940d 5189 #define SYSCON_PDRUNCFGSET_PD_SET_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 5190 #define SYSCON_PDRUNCFGSET_PD_SET_SHIFT (0U)
Kojto 148:fd96258d940d 5191 #define SYSCON_PDRUNCFGSET_PD_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PD_SET_SHIFT)) & SYSCON_PDRUNCFGSET_PD_SET_MASK)
Kojto 148:fd96258d940d 5192
Kojto 148:fd96258d940d 5193 /* The count of SYSCON_PDRUNCFGSET */
Kojto 148:fd96258d940d 5194 #define SYSCON_PDRUNCFGSET_COUNT (2U)
Kojto 148:fd96258d940d 5195
Kojto 148:fd96258d940d 5196 /*! @name PDRUNCFGCLR - Clear bits in PDRUNCFGn */
Kojto 148:fd96258d940d 5197 #define SYSCON_PDRUNCFGCLR_PD_CLR_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 5198 #define SYSCON_PDRUNCFGCLR_PD_CLR_SHIFT (0U)
Kojto 148:fd96258d940d 5199 #define SYSCON_PDRUNCFGCLR_PD_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PD_CLR_SHIFT)) & SYSCON_PDRUNCFGCLR_PD_CLR_MASK)
Kojto 148:fd96258d940d 5200
Kojto 148:fd96258d940d 5201 /* The count of SYSCON_PDRUNCFGCLR */
Kojto 148:fd96258d940d 5202 #define SYSCON_PDRUNCFGCLR_COUNT (2U)
Kojto 148:fd96258d940d 5203
Kojto 148:fd96258d940d 5204 /*! @name STARTERP - Start logic n wake-up enable register */
Kojto 148:fd96258d940d 5205 #define SYSCON_STARTERP_WDT_BOD_MASK (0x1U)
Kojto 148:fd96258d940d 5206 #define SYSCON_STARTERP_WDT_BOD_SHIFT (0U)
Kojto 148:fd96258d940d 5207 #define SYSCON_STARTERP_WDT_BOD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_WDT_BOD_SHIFT)) & SYSCON_STARTERP_WDT_BOD_MASK)
Kojto 148:fd96258d940d 5208 #define SYSCON_STARTERP_PINT4_MASK (0x1U)
Kojto 148:fd96258d940d 5209 #define SYSCON_STARTERP_PINT4_SHIFT (0U)
Kojto 148:fd96258d940d 5210 #define SYSCON_STARTERP_PINT4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PINT4_SHIFT)) & SYSCON_STARTERP_PINT4_MASK)
Kojto 148:fd96258d940d 5211 #define SYSCON_STARTERP_PINT5_MASK (0x2U)
Kojto 148:fd96258d940d 5212 #define SYSCON_STARTERP_PINT5_SHIFT (1U)
Kojto 148:fd96258d940d 5213 #define SYSCON_STARTERP_PINT5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PINT5_SHIFT)) & SYSCON_STARTERP_PINT5_MASK)
Kojto 148:fd96258d940d 5214 #define SYSCON_STARTERP_DMA0_MASK (0x2U)
Kojto 148:fd96258d940d 5215 #define SYSCON_STARTERP_DMA0_SHIFT (1U)
Kojto 148:fd96258d940d 5216 #define SYSCON_STARTERP_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_DMA0_SHIFT)) & SYSCON_STARTERP_DMA0_MASK)
Kojto 148:fd96258d940d 5217 #define SYSCON_STARTERP_GINT0_MASK (0x4U)
Kojto 148:fd96258d940d 5218 #define SYSCON_STARTERP_GINT0_SHIFT (2U)
Kojto 148:fd96258d940d 5219 #define SYSCON_STARTERP_GINT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_GINT0_SHIFT)) & SYSCON_STARTERP_GINT0_MASK)
Kojto 148:fd96258d940d 5220 #define SYSCON_STARTERP_PINT6_MASK (0x4U)
Kojto 148:fd96258d940d 5221 #define SYSCON_STARTERP_PINT6_SHIFT (2U)
Kojto 148:fd96258d940d 5222 #define SYSCON_STARTERP_PINT6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PINT6_SHIFT)) & SYSCON_STARTERP_PINT6_MASK)
Kojto 148:fd96258d940d 5223 #define SYSCON_STARTERP_GINT1_MASK (0x8U)
Kojto 148:fd96258d940d 5224 #define SYSCON_STARTERP_GINT1_SHIFT (3U)
Kojto 148:fd96258d940d 5225 #define SYSCON_STARTERP_GINT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_GINT1_SHIFT)) & SYSCON_STARTERP_GINT1_MASK)
Kojto 148:fd96258d940d 5226 #define SYSCON_STARTERP_PINT7_MASK (0x8U)
Kojto 148:fd96258d940d 5227 #define SYSCON_STARTERP_PINT7_SHIFT (3U)
Kojto 148:fd96258d940d 5228 #define SYSCON_STARTERP_PINT7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PINT7_SHIFT)) & SYSCON_STARTERP_PINT7_MASK)
Kojto 148:fd96258d940d 5229 #define SYSCON_STARTERP_CTIMER2_MASK (0x10U)
Kojto 148:fd96258d940d 5230 #define SYSCON_STARTERP_CTIMER2_SHIFT (4U)
Kojto 148:fd96258d940d 5231 #define SYSCON_STARTERP_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_CTIMER2_SHIFT)) & SYSCON_STARTERP_CTIMER2_MASK)
Kojto 148:fd96258d940d 5232 #define SYSCON_STARTERP_PIN_INT0_MASK (0x10U)
Kojto 148:fd96258d940d 5233 #define SYSCON_STARTERP_PIN_INT0_SHIFT (4U)
Kojto 148:fd96258d940d 5234 #define SYSCON_STARTERP_PIN_INT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PIN_INT0_SHIFT)) & SYSCON_STARTERP_PIN_INT0_MASK)
Kojto 148:fd96258d940d 5235 #define SYSCON_STARTERP_PIN_INT1_MASK (0x20U)
Kojto 148:fd96258d940d 5236 #define SYSCON_STARTERP_PIN_INT1_SHIFT (5U)
Kojto 148:fd96258d940d 5237 #define SYSCON_STARTERP_PIN_INT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PIN_INT1_SHIFT)) & SYSCON_STARTERP_PIN_INT1_MASK)
Kojto 148:fd96258d940d 5238 #define SYSCON_STARTERP_CTIMER4_MASK (0x20U)
Kojto 148:fd96258d940d 5239 #define SYSCON_STARTERP_CTIMER4_SHIFT (5U)
Kojto 148:fd96258d940d 5240 #define SYSCON_STARTERP_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_CTIMER4_SHIFT)) & SYSCON_STARTERP_CTIMER4_MASK)
Kojto 148:fd96258d940d 5241 #define SYSCON_STARTERP_PIN_INT2_MASK (0x40U)
Kojto 148:fd96258d940d 5242 #define SYSCON_STARTERP_PIN_INT2_SHIFT (6U)
Kojto 148:fd96258d940d 5243 #define SYSCON_STARTERP_PIN_INT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PIN_INT2_SHIFT)) & SYSCON_STARTERP_PIN_INT2_MASK)
Kojto 148:fd96258d940d 5244 #define SYSCON_STARTERP_PIN_INT3_MASK (0x80U)
Kojto 148:fd96258d940d 5245 #define SYSCON_STARTERP_PIN_INT3_SHIFT (7U)
Kojto 148:fd96258d940d 5246 #define SYSCON_STARTERP_PIN_INT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PIN_INT3_SHIFT)) & SYSCON_STARTERP_PIN_INT3_MASK)
Kojto 148:fd96258d940d 5247 #define SYSCON_STARTERP_UTICK0_MASK (0x100U)
Kojto 148:fd96258d940d 5248 #define SYSCON_STARTERP_UTICK0_SHIFT (8U)
Kojto 148:fd96258d940d 5249 #define SYSCON_STARTERP_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_UTICK0_SHIFT)) & SYSCON_STARTERP_UTICK0_MASK)
Kojto 148:fd96258d940d 5250 #define SYSCON_STARTERP_MRT0_MASK (0x200U)
Kojto 148:fd96258d940d 5251 #define SYSCON_STARTERP_MRT0_SHIFT (9U)
Kojto 148:fd96258d940d 5252 #define SYSCON_STARTERP_MRT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_MRT0_SHIFT)) & SYSCON_STARTERP_MRT0_MASK)
Kojto 148:fd96258d940d 5253 #define SYSCON_STARTERP_CTIMER0_MASK (0x400U)
Kojto 148:fd96258d940d 5254 #define SYSCON_STARTERP_CTIMER0_SHIFT (10U)
Kojto 148:fd96258d940d 5255 #define SYSCON_STARTERP_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_CTIMER0_SHIFT)) & SYSCON_STARTERP_CTIMER0_MASK)
Kojto 148:fd96258d940d 5256 #define SYSCON_STARTERP_CTIMER1_MASK (0x800U)
Kojto 148:fd96258d940d 5257 #define SYSCON_STARTERP_CTIMER1_SHIFT (11U)
Kojto 148:fd96258d940d 5258 #define SYSCON_STARTERP_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_CTIMER1_SHIFT)) & SYSCON_STARTERP_CTIMER1_MASK)
Kojto 148:fd96258d940d 5259 #define SYSCON_STARTERP_SCT0_MASK (0x1000U)
Kojto 148:fd96258d940d 5260 #define SYSCON_STARTERP_SCT0_SHIFT (12U)
Kojto 148:fd96258d940d 5261 #define SYSCON_STARTERP_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_SCT0_SHIFT)) & SYSCON_STARTERP_SCT0_MASK)
Kojto 148:fd96258d940d 5262 #define SYSCON_STARTERP_CTIMER3_MASK (0x2000U)
Kojto 148:fd96258d940d 5263 #define SYSCON_STARTERP_CTIMER3_SHIFT (13U)
Kojto 148:fd96258d940d 5264 #define SYSCON_STARTERP_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_CTIMER3_SHIFT)) & SYSCON_STARTERP_CTIMER3_MASK)
Kojto 148:fd96258d940d 5265 #define SYSCON_STARTERP_FLEXCOMM0_MASK (0x4000U)
Kojto 148:fd96258d940d 5266 #define SYSCON_STARTERP_FLEXCOMM0_SHIFT (14U)
Kojto 148:fd96258d940d 5267 #define SYSCON_STARTERP_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM0_SHIFT)) & SYSCON_STARTERP_FLEXCOMM0_MASK)
Kojto 148:fd96258d940d 5268 #define SYSCON_STARTERP_FLEXCOMM1_MASK (0x8000U)
Kojto 148:fd96258d940d 5269 #define SYSCON_STARTERP_FLEXCOMM1_SHIFT (15U)
Kojto 148:fd96258d940d 5270 #define SYSCON_STARTERP_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM1_SHIFT)) & SYSCON_STARTERP_FLEXCOMM1_MASK)
Kojto 148:fd96258d940d 5271 #define SYSCON_STARTERP_FLEXCOMM2_MASK (0x10000U)
Kojto 148:fd96258d940d 5272 #define SYSCON_STARTERP_FLEXCOMM2_SHIFT (16U)
Kojto 148:fd96258d940d 5273 #define SYSCON_STARTERP_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM2_SHIFT)) & SYSCON_STARTERP_FLEXCOMM2_MASK)
Kojto 148:fd96258d940d 5274 #define SYSCON_STARTERP_FLEXCOMM3_MASK (0x20000U)
Kojto 148:fd96258d940d 5275 #define SYSCON_STARTERP_FLEXCOMM3_SHIFT (17U)
Kojto 148:fd96258d940d 5276 #define SYSCON_STARTERP_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM3_SHIFT)) & SYSCON_STARTERP_FLEXCOMM3_MASK)
Kojto 148:fd96258d940d 5277 #define SYSCON_STARTERP_FLEXCOMM4_MASK (0x40000U)
Kojto 148:fd96258d940d 5278 #define SYSCON_STARTERP_FLEXCOMM4_SHIFT (18U)
Kojto 148:fd96258d940d 5279 #define SYSCON_STARTERP_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM4_SHIFT)) & SYSCON_STARTERP_FLEXCOMM4_MASK)
Kojto 148:fd96258d940d 5280 #define SYSCON_STARTERP_FLEXCOMM5_MASK (0x80000U)
Kojto 148:fd96258d940d 5281 #define SYSCON_STARTERP_FLEXCOMM5_SHIFT (19U)
Kojto 148:fd96258d940d 5282 #define SYSCON_STARTERP_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM5_SHIFT)) & SYSCON_STARTERP_FLEXCOMM5_MASK)
Kojto 148:fd96258d940d 5283 #define SYSCON_STARTERP_FLEXCOMM6_MASK (0x100000U)
Kojto 148:fd96258d940d 5284 #define SYSCON_STARTERP_FLEXCOMM6_SHIFT (20U)
Kojto 148:fd96258d940d 5285 #define SYSCON_STARTERP_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM6_SHIFT)) & SYSCON_STARTERP_FLEXCOMM6_MASK)
Kojto 148:fd96258d940d 5286 #define SYSCON_STARTERP_FLEXCOMM7_MASK (0x200000U)
Kojto 148:fd96258d940d 5287 #define SYSCON_STARTERP_FLEXCOMM7_SHIFT (21U)
Kojto 148:fd96258d940d 5288 #define SYSCON_STARTERP_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM7_SHIFT)) & SYSCON_STARTERP_FLEXCOMM7_MASK)
Kojto 148:fd96258d940d 5289 #define SYSCON_STARTERP_ADC0_SEQA_MASK (0x400000U)
Kojto 148:fd96258d940d 5290 #define SYSCON_STARTERP_ADC0_SEQA_SHIFT (22U)
Kojto 148:fd96258d940d 5291 #define SYSCON_STARTERP_ADC0_SEQA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_ADC0_SEQA_SHIFT)) & SYSCON_STARTERP_ADC0_SEQA_MASK)
Kojto 148:fd96258d940d 5292 #define SYSCON_STARTERP_ADC0_SEQB_MASK (0x800000U)
Kojto 148:fd96258d940d 5293 #define SYSCON_STARTERP_ADC0_SEQB_SHIFT (23U)
Kojto 148:fd96258d940d 5294 #define SYSCON_STARTERP_ADC0_SEQB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_ADC0_SEQB_SHIFT)) & SYSCON_STARTERP_ADC0_SEQB_MASK)
Kojto 148:fd96258d940d 5295 #define SYSCON_STARTERP_ADC0_THCMP_MASK (0x1000000U)
Kojto 148:fd96258d940d 5296 #define SYSCON_STARTERP_ADC0_THCMP_SHIFT (24U)
Kojto 148:fd96258d940d 5297 #define SYSCON_STARTERP_ADC0_THCMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_ADC0_THCMP_SHIFT)) & SYSCON_STARTERP_ADC0_THCMP_MASK)
Kojto 148:fd96258d940d 5298 #define SYSCON_STARTERP_DMIC0_MASK (0x2000000U)
Kojto 148:fd96258d940d 5299 #define SYSCON_STARTERP_DMIC0_SHIFT (25U)
Kojto 148:fd96258d940d 5300 #define SYSCON_STARTERP_DMIC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_DMIC0_SHIFT)) & SYSCON_STARTERP_DMIC0_MASK)
Kojto 148:fd96258d940d 5301 #define SYSCON_STARTERP_USB0_NEEDCLK_MASK (0x8000000U)
Kojto 148:fd96258d940d 5302 #define SYSCON_STARTERP_USB0_NEEDCLK_SHIFT (27U)
Kojto 148:fd96258d940d 5303 #define SYSCON_STARTERP_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_USB0_NEEDCLK_SHIFT)) & SYSCON_STARTERP_USB0_NEEDCLK_MASK)
Kojto 148:fd96258d940d 5304 #define SYSCON_STARTERP_USB0_MASK (0x10000000U)
Kojto 148:fd96258d940d 5305 #define SYSCON_STARTERP_USB0_SHIFT (28U)
Kojto 148:fd96258d940d 5306 #define SYSCON_STARTERP_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_USB0_SHIFT)) & SYSCON_STARTERP_USB0_MASK)
Kojto 148:fd96258d940d 5307 #define SYSCON_STARTERP_RTC_MASK (0x20000000U)
Kojto 148:fd96258d940d 5308 #define SYSCON_STARTERP_RTC_SHIFT (29U)
Kojto 148:fd96258d940d 5309 #define SYSCON_STARTERP_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_RTC_SHIFT)) & SYSCON_STARTERP_RTC_MASK)
Kojto 148:fd96258d940d 5310 #define SYSCON_STARTERP_MAILBOX_MASK (0x80000000U)
Kojto 148:fd96258d940d 5311 #define SYSCON_STARTERP_MAILBOX_SHIFT (31U)
Kojto 148:fd96258d940d 5312 #define SYSCON_STARTERP_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_MAILBOX_SHIFT)) & SYSCON_STARTERP_MAILBOX_MASK)
Kojto 148:fd96258d940d 5313
Kojto 148:fd96258d940d 5314 /* The count of SYSCON_STARTERP */
Kojto 148:fd96258d940d 5315 #define SYSCON_STARTERP_COUNT (2U)
Kojto 148:fd96258d940d 5316
Kojto 148:fd96258d940d 5317 /*! @name STARTERSET - Set bits in STARTERn */
Kojto 148:fd96258d940d 5318 #define SYSCON_STARTERSET_START_SET_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 5319 #define SYSCON_STARTERSET_START_SET_SHIFT (0U)
Kojto 148:fd96258d940d 5320 #define SYSCON_STARTERSET_START_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_START_SET_SHIFT)) & SYSCON_STARTERSET_START_SET_MASK)
Kojto 148:fd96258d940d 5321
Kojto 148:fd96258d940d 5322 /* The count of SYSCON_STARTERSET */
Kojto 148:fd96258d940d 5323 #define SYSCON_STARTERSET_COUNT (2U)
Kojto 148:fd96258d940d 5324
Kojto 148:fd96258d940d 5325 /*! @name STARTERCLR - Clear bits in STARTERn */
Kojto 148:fd96258d940d 5326 #define SYSCON_STARTERCLR_START_CLR_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 5327 #define SYSCON_STARTERCLR_START_CLR_SHIFT (0U)
Kojto 148:fd96258d940d 5328 #define SYSCON_STARTERCLR_START_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_START_CLR_SHIFT)) & SYSCON_STARTERCLR_START_CLR_MASK)
Kojto 148:fd96258d940d 5329
Kojto 148:fd96258d940d 5330 /* The count of SYSCON_STARTERCLR */
Kojto 148:fd96258d940d 5331 #define SYSCON_STARTERCLR_COUNT (2U)
Kojto 148:fd96258d940d 5332
Kojto 148:fd96258d940d 5333 /*! @name HWWAKE - Configures special cases of hardware wake-up */
Kojto 148:fd96258d940d 5334 #define SYSCON_HWWAKE_FORCEWAKE_MASK (0x1U)
Kojto 148:fd96258d940d 5335 #define SYSCON_HWWAKE_FORCEWAKE_SHIFT (0U)
Kojto 148:fd96258d940d 5336 #define SYSCON_HWWAKE_FORCEWAKE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_FORCEWAKE_SHIFT)) & SYSCON_HWWAKE_FORCEWAKE_MASK)
Kojto 148:fd96258d940d 5337 #define SYSCON_HWWAKE_FCWAKE_MASK (0x2U)
Kojto 148:fd96258d940d 5338 #define SYSCON_HWWAKE_FCWAKE_SHIFT (1U)
Kojto 148:fd96258d940d 5339 #define SYSCON_HWWAKE_FCWAKE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_FCWAKE_SHIFT)) & SYSCON_HWWAKE_FCWAKE_MASK)
Kojto 148:fd96258d940d 5340 #define SYSCON_HWWAKE_WAKEDMIC_MASK (0x4U)
Kojto 148:fd96258d940d 5341 #define SYSCON_HWWAKE_WAKEDMIC_SHIFT (2U)
Kojto 148:fd96258d940d 5342 #define SYSCON_HWWAKE_WAKEDMIC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_WAKEDMIC_SHIFT)) & SYSCON_HWWAKE_WAKEDMIC_MASK)
Kojto 148:fd96258d940d 5343 #define SYSCON_HWWAKE_WAKEDMA_MASK (0x8U)
Kojto 148:fd96258d940d 5344 #define SYSCON_HWWAKE_WAKEDMA_SHIFT (3U)
Kojto 148:fd96258d940d 5345 #define SYSCON_HWWAKE_WAKEDMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_WAKEDMA_SHIFT)) & SYSCON_HWWAKE_WAKEDMA_MASK)
Kojto 148:fd96258d940d 5346
Kojto 148:fd96258d940d 5347 /*! @name CPCTRL - CPU Control for multiple processors */
Kojto 148:fd96258d940d 5348 #define SYSCON_CPCTRL_MASTERCPU_MASK (0x1U)
Kojto 148:fd96258d940d 5349 #define SYSCON_CPCTRL_MASTERCPU_SHIFT (0U)
Kojto 148:fd96258d940d 5350 #define SYSCON_CPCTRL_MASTERCPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPCTRL_MASTERCPU_SHIFT)) & SYSCON_CPCTRL_MASTERCPU_MASK)
Kojto 148:fd96258d940d 5351 #define SYSCON_CPCTRL_CM4CLKEN_MASK (0x4U)
Kojto 148:fd96258d940d 5352 #define SYSCON_CPCTRL_CM4CLKEN_SHIFT (2U)
Kojto 148:fd96258d940d 5353 #define SYSCON_CPCTRL_CM4CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPCTRL_CM4CLKEN_SHIFT)) & SYSCON_CPCTRL_CM4CLKEN_MASK)
Kojto 148:fd96258d940d 5354 #define SYSCON_CPCTRL_CM0CLKEN_MASK (0x8U)
Kojto 148:fd96258d940d 5355 #define SYSCON_CPCTRL_CM0CLKEN_SHIFT (3U)
Kojto 148:fd96258d940d 5356 #define SYSCON_CPCTRL_CM0CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPCTRL_CM0CLKEN_SHIFT)) & SYSCON_CPCTRL_CM0CLKEN_MASK)
Kojto 148:fd96258d940d 5357 #define SYSCON_CPCTRL_CM4RSTEN_MASK (0x10U)
Kojto 148:fd96258d940d 5358 #define SYSCON_CPCTRL_CM4RSTEN_SHIFT (4U)
Kojto 148:fd96258d940d 5359 #define SYSCON_CPCTRL_CM4RSTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPCTRL_CM4RSTEN_SHIFT)) & SYSCON_CPCTRL_CM4RSTEN_MASK)
Kojto 148:fd96258d940d 5360 #define SYSCON_CPCTRL_CM0RSTEN_MASK (0x20U)
Kojto 148:fd96258d940d 5361 #define SYSCON_CPCTRL_CM0RSTEN_SHIFT (5U)
Kojto 148:fd96258d940d 5362 #define SYSCON_CPCTRL_CM0RSTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPCTRL_CM0RSTEN_SHIFT)) & SYSCON_CPCTRL_CM0RSTEN_MASK)
Kojto 148:fd96258d940d 5363 #define SYSCON_CPCTRL_POWERCPU_MASK (0x40U)
Kojto 148:fd96258d940d 5364 #define SYSCON_CPCTRL_POWERCPU_SHIFT (6U)
Kojto 148:fd96258d940d 5365 #define SYSCON_CPCTRL_POWERCPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPCTRL_POWERCPU_SHIFT)) & SYSCON_CPCTRL_POWERCPU_MASK)
Kojto 148:fd96258d940d 5366
Kojto 148:fd96258d940d 5367 /*! @name CPBOOT - Coprocessor Boot Address */
Kojto 148:fd96258d940d 5368 #define SYSCON_CPBOOT_BOOTADDR_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 5369 #define SYSCON_CPBOOT_BOOTADDR_SHIFT (0U)
Kojto 148:fd96258d940d 5370 #define SYSCON_CPBOOT_BOOTADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPBOOT_BOOTADDR_SHIFT)) & SYSCON_CPBOOT_BOOTADDR_MASK)
Kojto 148:fd96258d940d 5371
Kojto 148:fd96258d940d 5372 /*! @name CPSTACK - Coprocessor Stack Address */
Kojto 148:fd96258d940d 5373 #define SYSCON_CPSTACK_STACKADDR_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 5374 #define SYSCON_CPSTACK_STACKADDR_SHIFT (0U)
Kojto 148:fd96258d940d 5375 #define SYSCON_CPSTACK_STACKADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTACK_STACKADDR_SHIFT)) & SYSCON_CPSTACK_STACKADDR_MASK)
Kojto 148:fd96258d940d 5376
Kojto 148:fd96258d940d 5377 /*! @name CPSTAT - Coprocessor Status */
Kojto 148:fd96258d940d 5378 #define SYSCON_CPSTAT_CM4SLEEPING_MASK (0x1U)
Kojto 148:fd96258d940d 5379 #define SYSCON_CPSTAT_CM4SLEEPING_SHIFT (0U)
Kojto 148:fd96258d940d 5380 #define SYSCON_CPSTAT_CM4SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CM4SLEEPING_SHIFT)) & SYSCON_CPSTAT_CM4SLEEPING_MASK)
Kojto 148:fd96258d940d 5381 #define SYSCON_CPSTAT_CM0SLEEPING_MASK (0x2U)
Kojto 148:fd96258d940d 5382 #define SYSCON_CPSTAT_CM0SLEEPING_SHIFT (1U)
Kojto 148:fd96258d940d 5383 #define SYSCON_CPSTAT_CM0SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CM0SLEEPING_SHIFT)) & SYSCON_CPSTAT_CM0SLEEPING_MASK)
Kojto 148:fd96258d940d 5384 #define SYSCON_CPSTAT_CM4LOCKUP_MASK (0x4U)
Kojto 148:fd96258d940d 5385 #define SYSCON_CPSTAT_CM4LOCKUP_SHIFT (2U)
Kojto 148:fd96258d940d 5386 #define SYSCON_CPSTAT_CM4LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CM4LOCKUP_SHIFT)) & SYSCON_CPSTAT_CM4LOCKUP_MASK)
Kojto 148:fd96258d940d 5387 #define SYSCON_CPSTAT_CM0LOCKUP_MASK (0x8U)
Kojto 148:fd96258d940d 5388 #define SYSCON_CPSTAT_CM0LOCKUP_SHIFT (3U)
Kojto 148:fd96258d940d 5389 #define SYSCON_CPSTAT_CM0LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CM0LOCKUP_SHIFT)) & SYSCON_CPSTAT_CM0LOCKUP_MASK)
Kojto 148:fd96258d940d 5390
Kojto 148:fd96258d940d 5391 /*! @name AUTOCGOR - Auto Clock-Gate Override Register */
Kojto 148:fd96258d940d 5392 #define SYSCON_AUTOCGOR_RAM0X_MASK (0x2U)
Kojto 148:fd96258d940d 5393 #define SYSCON_AUTOCGOR_RAM0X_SHIFT (1U)
Kojto 148:fd96258d940d 5394 #define SYSCON_AUTOCGOR_RAM0X(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM0X_SHIFT)) & SYSCON_AUTOCGOR_RAM0X_MASK)
Kojto 148:fd96258d940d 5395 #define SYSCON_AUTOCGOR_RAM1_MASK (0x4U)
Kojto 148:fd96258d940d 5396 #define SYSCON_AUTOCGOR_RAM1_SHIFT (2U)
Kojto 148:fd96258d940d 5397 #define SYSCON_AUTOCGOR_RAM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM1_SHIFT)) & SYSCON_AUTOCGOR_RAM1_MASK)
Kojto 148:fd96258d940d 5398 #define SYSCON_AUTOCGOR_RAM2_MASK (0x8U)
Kojto 148:fd96258d940d 5399 #define SYSCON_AUTOCGOR_RAM2_SHIFT (3U)
Kojto 148:fd96258d940d 5400 #define SYSCON_AUTOCGOR_RAM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM2_SHIFT)) & SYSCON_AUTOCGOR_RAM2_MASK)
Kojto 148:fd96258d940d 5401
Kojto 148:fd96258d940d 5402 /*! @name JTAGIDCODE - JTAG ID code register */
Kojto 148:fd96258d940d 5403 #define SYSCON_JTAGIDCODE_JTAGID_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 5404 #define SYSCON_JTAGIDCODE_JTAGID_SHIFT (0U)
Kojto 148:fd96258d940d 5405 #define SYSCON_JTAGIDCODE_JTAGID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_JTAGIDCODE_JTAGID_SHIFT)) & SYSCON_JTAGIDCODE_JTAGID_MASK)
Kojto 148:fd96258d940d 5406
Kojto 148:fd96258d940d 5407 /*! @name DEVICE_ID0 - Part ID register */
Kojto 148:fd96258d940d 5408 #define SYSCON_DEVICE_ID0_PARTID_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 5409 #define SYSCON_DEVICE_ID0_PARTID_SHIFT (0U)
Kojto 148:fd96258d940d 5410 #define SYSCON_DEVICE_ID0_PARTID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_PARTID_SHIFT)) & SYSCON_DEVICE_ID0_PARTID_MASK)
Kojto 148:fd96258d940d 5411
Kojto 148:fd96258d940d 5412 /*! @name DEVICE_ID1 - Boot ROM and die revision register */
Kojto 148:fd96258d940d 5413 #define SYSCON_DEVICE_ID1_REVID_MASK (0xFFFFFFFFU)
Kojto 148:fd96258d940d 5414 #define SYSCON_DEVICE_ID1_REVID_SHIFT (0U)
Kojto 148:fd96258d940d 5415 #define SYSCON_DEVICE_ID1_REVID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID1_REVID_SHIFT)) & SYSCON_DEVICE_ID1_REVID_MASK)
Kojto 148:fd96258d940d 5416
Kojto 148:fd96258d940d 5417 /*! @name BODCTRL - Brown-Out Detect control */
Kojto 148:fd96258d940d 5418 #define SYSCON_BODCTRL_BODRSTLEV_MASK (0x3U)
Kojto 148:fd96258d940d 5419 #define SYSCON_BODCTRL_BODRSTLEV_SHIFT (0U)
Kojto 148:fd96258d940d 5420 #define SYSCON_BODCTRL_BODRSTLEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTLEV_SHIFT)) & SYSCON_BODCTRL_BODRSTLEV_MASK)
Kojto 148:fd96258d940d 5421 #define SYSCON_BODCTRL_BODRSTENA_MASK (0x4U)
Kojto 148:fd96258d940d 5422 #define SYSCON_BODCTRL_BODRSTENA_SHIFT (2U)
Kojto 148:fd96258d940d 5423 #define SYSCON_BODCTRL_BODRSTENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTENA_SHIFT)) & SYSCON_BODCTRL_BODRSTENA_MASK)
Kojto 148:fd96258d940d 5424 #define SYSCON_BODCTRL_BODINTLEV_MASK (0x18U)
Kojto 148:fd96258d940d 5425 #define SYSCON_BODCTRL_BODINTLEV_SHIFT (3U)
Kojto 148:fd96258d940d 5426 #define SYSCON_BODCTRL_BODINTLEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTLEV_SHIFT)) & SYSCON_BODCTRL_BODINTLEV_MASK)
Kojto 148:fd96258d940d 5427 #define SYSCON_BODCTRL_BODINTENA_MASK (0x20U)
Kojto 148:fd96258d940d 5428 #define SYSCON_BODCTRL_BODINTENA_SHIFT (5U)
Kojto 148:fd96258d940d 5429 #define SYSCON_BODCTRL_BODINTENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTENA_SHIFT)) & SYSCON_BODCTRL_BODINTENA_MASK)
Kojto 148:fd96258d940d 5430 #define SYSCON_BODCTRL_BODRSTSTAT_MASK (0x40U)
Kojto 148:fd96258d940d 5431 #define SYSCON_BODCTRL_BODRSTSTAT_SHIFT (6U)
Kojto 148:fd96258d940d 5432 #define SYSCON_BODCTRL_BODRSTSTAT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTSTAT_SHIFT)) & SYSCON_BODCTRL_BODRSTSTAT_MASK)
Kojto 148:fd96258d940d 5433 #define SYSCON_BODCTRL_BODINTSTAT_MASK (0x80U)
Kojto 148:fd96258d940d 5434 #define SYSCON_BODCTRL_BODINTSTAT_SHIFT (7U)
Kojto 148:fd96258d940d 5435 #define SYSCON_BODCTRL_BODINTSTAT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTSTAT_SHIFT)) & SYSCON_BODCTRL_BODINTSTAT_MASK)
Kojto 148:fd96258d940d 5436
Kojto 148:fd96258d940d 5437
Kojto 148:fd96258d940d 5438 /*!
Kojto 148:fd96258d940d 5439 * @}
Kojto 148:fd96258d940d 5440 */ /* end of group SYSCON_Register_Masks */
Kojto 148:fd96258d940d 5441
Kojto 148:fd96258d940d 5442
Kojto 148:fd96258d940d 5443 /* SYSCON - Peripheral instance base addresses */
Kojto 148:fd96258d940d 5444 /** Peripheral SYSCON base address */
Kojto 148:fd96258d940d 5445 #define SYSCON_BASE (0x40000000u)
Kojto 148:fd96258d940d 5446 /** Peripheral SYSCON base pointer */
Kojto 148:fd96258d940d 5447 #define SYSCON ((SYSCON_Type *)SYSCON_BASE)
Kojto 148:fd96258d940d 5448 /** Array initializer of SYSCON peripheral base addresses */
Kojto 148:fd96258d940d 5449 #define SYSCON_BASE_ADDRS { SYSCON_BASE }
Kojto 148:fd96258d940d 5450 /** Array initializer of SYSCON peripheral base pointers */
Kojto 148:fd96258d940d 5451 #define SYSCON_BASE_PTRS { SYSCON }
Kojto 148:fd96258d940d 5452
Kojto 148:fd96258d940d 5453 /*!
Kojto 148:fd96258d940d 5454 * @}
Kojto 148:fd96258d940d 5455 */ /* end of group SYSCON_Peripheral_Access_Layer */
Kojto 148:fd96258d940d 5456
Kojto 148:fd96258d940d 5457
Kojto 148:fd96258d940d 5458 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 5459 -- USART Peripheral Access Layer
Kojto 148:fd96258d940d 5460 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 5461
Kojto 148:fd96258d940d 5462 /*!
Kojto 148:fd96258d940d 5463 * @addtogroup USART_Peripheral_Access_Layer USART Peripheral Access Layer
Kojto 148:fd96258d940d 5464 * @{
Kojto 148:fd96258d940d 5465 */
Kojto 148:fd96258d940d 5466
Kojto 148:fd96258d940d 5467 /** USART - Register Layout Typedef */
Kojto 148:fd96258d940d 5468 typedef struct {
Kojto 148:fd96258d940d 5469 __IO uint32_t CFG; /**< USART Configuration register. Basic USART configuration settings that typically are not changed during operation., offset: 0x0 */
Kojto 148:fd96258d940d 5470 __IO uint32_t CTL; /**< USART Control register. USART control settings that are more likely to change during operation., offset: 0x4 */
Kojto 148:fd96258d940d 5471 __IO uint32_t STAT; /**< USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them., offset: 0x8 */
Kojto 148:fd96258d940d 5472 __IO uint32_t INTENSET; /**< Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0xC */
Kojto 148:fd96258d940d 5473 __O uint32_t INTENCLR; /**< Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared., offset: 0x10 */
Kojto 148:fd96258d940d 5474 uint8_t RESERVED_0[12];
Kojto 148:fd96258d940d 5475 __IO uint32_t BRG; /**< Baud Rate Generator register. 16-bit integer baud rate divisor value., offset: 0x20 */
Kojto 148:fd96258d940d 5476 __I uint32_t INTSTAT; /**< Interrupt status register. Reflects interrupts that are currently enabled., offset: 0x24 */
Kojto 148:fd96258d940d 5477 __IO uint32_t OSR; /**< Oversample selection register for asynchronous communication., offset: 0x28 */
Kojto 148:fd96258d940d 5478 __IO uint32_t ADDR; /**< Address register for automatic address matching., offset: 0x2C */
Kojto 148:fd96258d940d 5479 uint8_t RESERVED_1[3536];
Kojto 148:fd96258d940d 5480 __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */
Kojto 148:fd96258d940d 5481 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */
Kojto 148:fd96258d940d 5482 __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */
Kojto 148:fd96258d940d 5483 uint8_t RESERVED_2[4];
Kojto 148:fd96258d940d 5484 __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */
Kojto 148:fd96258d940d 5485 __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */
Kojto 148:fd96258d940d 5486 __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */
Kojto 148:fd96258d940d 5487 uint8_t RESERVED_3[4];
Kojto 148:fd96258d940d 5488 __IO uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */
Kojto 148:fd96258d940d 5489 uint8_t RESERVED_4[12];
Kojto 148:fd96258d940d 5490 __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */
Kojto 148:fd96258d940d 5491 uint8_t RESERVED_5[12];
Kojto 148:fd96258d940d 5492 __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */
Kojto 148:fd96258d940d 5493 } USART_Type;
Kojto 148:fd96258d940d 5494
Kojto 148:fd96258d940d 5495 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 5496 -- USART Register Masks
Kojto 148:fd96258d940d 5497 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 5498
Kojto 148:fd96258d940d 5499 /*!
Kojto 148:fd96258d940d 5500 * @addtogroup USART_Register_Masks USART Register Masks
Kojto 148:fd96258d940d 5501 * @{
Kojto 148:fd96258d940d 5502 */
Kojto 148:fd96258d940d 5503
Kojto 148:fd96258d940d 5504 /*! @name CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. */
Kojto 148:fd96258d940d 5505 #define USART_CFG_ENABLE_MASK (0x1U)
Kojto 148:fd96258d940d 5506 #define USART_CFG_ENABLE_SHIFT (0U)
Kojto 148:fd96258d940d 5507 #define USART_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK)
Kojto 148:fd96258d940d 5508 #define USART_CFG_DATALEN_MASK (0xCU)
Kojto 148:fd96258d940d 5509 #define USART_CFG_DATALEN_SHIFT (2U)
Kojto 148:fd96258d940d 5510 #define USART_CFG_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK)
Kojto 148:fd96258d940d 5511 #define USART_CFG_PARITYSEL_MASK (0x30U)
Kojto 148:fd96258d940d 5512 #define USART_CFG_PARITYSEL_SHIFT (4U)
Kojto 148:fd96258d940d 5513 #define USART_CFG_PARITYSEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK)
Kojto 148:fd96258d940d 5514 #define USART_CFG_STOPLEN_MASK (0x40U)
Kojto 148:fd96258d940d 5515 #define USART_CFG_STOPLEN_SHIFT (6U)
Kojto 148:fd96258d940d 5516 #define USART_CFG_STOPLEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK)
Kojto 148:fd96258d940d 5517 #define USART_CFG_MODE32K_MASK (0x80U)
Kojto 148:fd96258d940d 5518 #define USART_CFG_MODE32K_SHIFT (7U)
Kojto 148:fd96258d940d 5519 #define USART_CFG_MODE32K(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK)
Kojto 148:fd96258d940d 5520 #define USART_CFG_LINMODE_MASK (0x100U)
Kojto 148:fd96258d940d 5521 #define USART_CFG_LINMODE_SHIFT (8U)
Kojto 148:fd96258d940d 5522 #define USART_CFG_LINMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK)
Kojto 148:fd96258d940d 5523 #define USART_CFG_CTSEN_MASK (0x200U)
Kojto 148:fd96258d940d 5524 #define USART_CFG_CTSEN_SHIFT (9U)
Kojto 148:fd96258d940d 5525 #define USART_CFG_CTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK)
Kojto 148:fd96258d940d 5526 #define USART_CFG_SYNCEN_MASK (0x800U)
Kojto 148:fd96258d940d 5527 #define USART_CFG_SYNCEN_SHIFT (11U)
Kojto 148:fd96258d940d 5528 #define USART_CFG_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK)
Kojto 148:fd96258d940d 5529 #define USART_CFG_CLKPOL_MASK (0x1000U)
Kojto 148:fd96258d940d 5530 #define USART_CFG_CLKPOL_SHIFT (12U)
Kojto 148:fd96258d940d 5531 #define USART_CFG_CLKPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK)
Kojto 148:fd96258d940d 5532 #define USART_CFG_SYNCMST_MASK (0x4000U)
Kojto 148:fd96258d940d 5533 #define USART_CFG_SYNCMST_SHIFT (14U)
Kojto 148:fd96258d940d 5534 #define USART_CFG_SYNCMST(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK)
Kojto 148:fd96258d940d 5535 #define USART_CFG_LOOP_MASK (0x8000U)
Kojto 148:fd96258d940d 5536 #define USART_CFG_LOOP_SHIFT (15U)
Kojto 148:fd96258d940d 5537 #define USART_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK)
Kojto 148:fd96258d940d 5538 #define USART_CFG_IOMODE_MASK (0x10000U)
Kojto 148:fd96258d940d 5539 #define USART_CFG_IOMODE_SHIFT (16U)
Kojto 148:fd96258d940d 5540 #define USART_CFG_IOMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_IOMODE_SHIFT)) & USART_CFG_IOMODE_MASK)
Kojto 148:fd96258d940d 5541 #define USART_CFG_OETA_MASK (0x40000U)
Kojto 148:fd96258d940d 5542 #define USART_CFG_OETA_SHIFT (18U)
Kojto 148:fd96258d940d 5543 #define USART_CFG_OETA(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK)
Kojto 148:fd96258d940d 5544 #define USART_CFG_AUTOADDR_MASK (0x80000U)
Kojto 148:fd96258d940d 5545 #define USART_CFG_AUTOADDR_SHIFT (19U)
Kojto 148:fd96258d940d 5546 #define USART_CFG_AUTOADDR(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK)
Kojto 148:fd96258d940d 5547 #define USART_CFG_OESEL_MASK (0x100000U)
Kojto 148:fd96258d940d 5548 #define USART_CFG_OESEL_SHIFT (20U)
Kojto 148:fd96258d940d 5549 #define USART_CFG_OESEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK)
Kojto 148:fd96258d940d 5550 #define USART_CFG_OEPOL_MASK (0x200000U)
Kojto 148:fd96258d940d 5551 #define USART_CFG_OEPOL_SHIFT (21U)
Kojto 148:fd96258d940d 5552 #define USART_CFG_OEPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK)
Kojto 148:fd96258d940d 5553 #define USART_CFG_RXPOL_MASK (0x400000U)
Kojto 148:fd96258d940d 5554 #define USART_CFG_RXPOL_SHIFT (22U)
Kojto 148:fd96258d940d 5555 #define USART_CFG_RXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK)
Kojto 148:fd96258d940d 5556 #define USART_CFG_TXPOL_MASK (0x800000U)
Kojto 148:fd96258d940d 5557 #define USART_CFG_TXPOL_SHIFT (23U)
Kojto 148:fd96258d940d 5558 #define USART_CFG_TXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK)
Kojto 148:fd96258d940d 5559
Kojto 148:fd96258d940d 5560 /*! @name CTL - USART Control register. USART control settings that are more likely to change during operation. */
Kojto 148:fd96258d940d 5561 #define USART_CTL_TXBRKEN_MASK (0x2U)
Kojto 148:fd96258d940d 5562 #define USART_CTL_TXBRKEN_SHIFT (1U)
Kojto 148:fd96258d940d 5563 #define USART_CTL_TXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK)
Kojto 148:fd96258d940d 5564 #define USART_CTL_ADDRDET_MASK (0x4U)
Kojto 148:fd96258d940d 5565 #define USART_CTL_ADDRDET_SHIFT (2U)
Kojto 148:fd96258d940d 5566 #define USART_CTL_ADDRDET(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK)
Kojto 148:fd96258d940d 5567 #define USART_CTL_TXDIS_MASK (0x40U)
Kojto 148:fd96258d940d 5568 #define USART_CTL_TXDIS_SHIFT (6U)
Kojto 148:fd96258d940d 5569 #define USART_CTL_TXDIS(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK)
Kojto 148:fd96258d940d 5570 #define USART_CTL_CC_MASK (0x100U)
Kojto 148:fd96258d940d 5571 #define USART_CTL_CC_SHIFT (8U)
Kojto 148:fd96258d940d 5572 #define USART_CTL_CC(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK)
Kojto 148:fd96258d940d 5573 #define USART_CTL_CLRCCONRX_MASK (0x200U)
Kojto 148:fd96258d940d 5574 #define USART_CTL_CLRCCONRX_SHIFT (9U)
Kojto 148:fd96258d940d 5575 #define USART_CTL_CLRCCONRX(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK)
Kojto 148:fd96258d940d 5576 #define USART_CTL_AUTOBAUD_MASK (0x10000U)
Kojto 148:fd96258d940d 5577 #define USART_CTL_AUTOBAUD_SHIFT (16U)
Kojto 148:fd96258d940d 5578 #define USART_CTL_AUTOBAUD(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK)
Kojto 148:fd96258d940d 5579
Kojto 148:fd96258d940d 5580 /*! @name STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. */
Kojto 148:fd96258d940d 5581 #define USART_STAT_RXIDLE_MASK (0x2U)
Kojto 148:fd96258d940d 5582 #define USART_STAT_RXIDLE_SHIFT (1U)
Kojto 148:fd96258d940d 5583 #define USART_STAT_RXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK)
Kojto 148:fd96258d940d 5584 #define USART_STAT_TXIDLE_MASK (0x8U)
Kojto 148:fd96258d940d 5585 #define USART_STAT_TXIDLE_SHIFT (3U)
Kojto 148:fd96258d940d 5586 #define USART_STAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK)
Kojto 148:fd96258d940d 5587 #define USART_STAT_CTS_MASK (0x10U)
Kojto 148:fd96258d940d 5588 #define USART_STAT_CTS_SHIFT (4U)
Kojto 148:fd96258d940d 5589 #define USART_STAT_CTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK)
Kojto 148:fd96258d940d 5590 #define USART_STAT_DELTACTS_MASK (0x20U)
Kojto 148:fd96258d940d 5591 #define USART_STAT_DELTACTS_SHIFT (5U)
Kojto 148:fd96258d940d 5592 #define USART_STAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK)
Kojto 148:fd96258d940d 5593 #define USART_STAT_TXDISSTAT_MASK (0x40U)
Kojto 148:fd96258d940d 5594 #define USART_STAT_TXDISSTAT_SHIFT (6U)
Kojto 148:fd96258d940d 5595 #define USART_STAT_TXDISSTAT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK)
Kojto 148:fd96258d940d 5596 #define USART_STAT_RXBRK_MASK (0x400U)
Kojto 148:fd96258d940d 5597 #define USART_STAT_RXBRK_SHIFT (10U)
Kojto 148:fd96258d940d 5598 #define USART_STAT_RXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK)
Kojto 148:fd96258d940d 5599 #define USART_STAT_DELTARXBRK_MASK (0x800U)
Kojto 148:fd96258d940d 5600 #define USART_STAT_DELTARXBRK_SHIFT (11U)
Kojto 148:fd96258d940d 5601 #define USART_STAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK)
Kojto 148:fd96258d940d 5602 #define USART_STAT_START_MASK (0x1000U)
Kojto 148:fd96258d940d 5603 #define USART_STAT_START_SHIFT (12U)
Kojto 148:fd96258d940d 5604 #define USART_STAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK)
Kojto 148:fd96258d940d 5605 #define USART_STAT_FRAMERRINT_MASK (0x2000U)
Kojto 148:fd96258d940d 5606 #define USART_STAT_FRAMERRINT_SHIFT (13U)
Kojto 148:fd96258d940d 5607 #define USART_STAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK)
Kojto 148:fd96258d940d 5608 #define USART_STAT_PARITYERRINT_MASK (0x4000U)
Kojto 148:fd96258d940d 5609 #define USART_STAT_PARITYERRINT_SHIFT (14U)
Kojto 148:fd96258d940d 5610 #define USART_STAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK)
Kojto 148:fd96258d940d 5611 #define USART_STAT_RXNOISEINT_MASK (0x8000U)
Kojto 148:fd96258d940d 5612 #define USART_STAT_RXNOISEINT_SHIFT (15U)
Kojto 148:fd96258d940d 5613 #define USART_STAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK)
Kojto 148:fd96258d940d 5614 #define USART_STAT_ABERR_MASK (0x10000U)
Kojto 148:fd96258d940d 5615 #define USART_STAT_ABERR_SHIFT (16U)
Kojto 148:fd96258d940d 5616 #define USART_STAT_ABERR(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK)
Kojto 148:fd96258d940d 5617
Kojto 148:fd96258d940d 5618 /*! @name INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */
Kojto 148:fd96258d940d 5619 #define USART_INTENSET_TXIDLEEN_MASK (0x8U)
Kojto 148:fd96258d940d 5620 #define USART_INTENSET_TXIDLEEN_SHIFT (3U)
Kojto 148:fd96258d940d 5621 #define USART_INTENSET_TXIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK)
Kojto 148:fd96258d940d 5622 #define USART_INTENSET_DELTACTSEN_MASK (0x20U)
Kojto 148:fd96258d940d 5623 #define USART_INTENSET_DELTACTSEN_SHIFT (5U)
Kojto 148:fd96258d940d 5624 #define USART_INTENSET_DELTACTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK)
Kojto 148:fd96258d940d 5625 #define USART_INTENSET_TXDISEN_MASK (0x40U)
Kojto 148:fd96258d940d 5626 #define USART_INTENSET_TXDISEN_SHIFT (6U)
Kojto 148:fd96258d940d 5627 #define USART_INTENSET_TXDISEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK)
Kojto 148:fd96258d940d 5628 #define USART_INTENSET_DELTARXBRKEN_MASK (0x800U)
Kojto 148:fd96258d940d 5629 #define USART_INTENSET_DELTARXBRKEN_SHIFT (11U)
Kojto 148:fd96258d940d 5630 #define USART_INTENSET_DELTARXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK)
Kojto 148:fd96258d940d 5631 #define USART_INTENSET_STARTEN_MASK (0x1000U)
Kojto 148:fd96258d940d 5632 #define USART_INTENSET_STARTEN_SHIFT (12U)
Kojto 148:fd96258d940d 5633 #define USART_INTENSET_STARTEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK)
Kojto 148:fd96258d940d 5634 #define USART_INTENSET_FRAMERREN_MASK (0x2000U)
Kojto 148:fd96258d940d 5635 #define USART_INTENSET_FRAMERREN_SHIFT (13U)
Kojto 148:fd96258d940d 5636 #define USART_INTENSET_FRAMERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK)
Kojto 148:fd96258d940d 5637 #define USART_INTENSET_PARITYERREN_MASK (0x4000U)
Kojto 148:fd96258d940d 5638 #define USART_INTENSET_PARITYERREN_SHIFT (14U)
Kojto 148:fd96258d940d 5639 #define USART_INTENSET_PARITYERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK)
Kojto 148:fd96258d940d 5640 #define USART_INTENSET_RXNOISEEN_MASK (0x8000U)
Kojto 148:fd96258d940d 5641 #define USART_INTENSET_RXNOISEEN_SHIFT (15U)
Kojto 148:fd96258d940d 5642 #define USART_INTENSET_RXNOISEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK)
Kojto 148:fd96258d940d 5643 #define USART_INTENSET_ABERREN_MASK (0x10000U)
Kojto 148:fd96258d940d 5644 #define USART_INTENSET_ABERREN_SHIFT (16U)
Kojto 148:fd96258d940d 5645 #define USART_INTENSET_ABERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK)
Kojto 148:fd96258d940d 5646
Kojto 148:fd96258d940d 5647 /*! @name INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. */
Kojto 148:fd96258d940d 5648 #define USART_INTENCLR_TXIDLECLR_MASK (0x8U)
Kojto 148:fd96258d940d 5649 #define USART_INTENCLR_TXIDLECLR_SHIFT (3U)
Kojto 148:fd96258d940d 5650 #define USART_INTENCLR_TXIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK)
Kojto 148:fd96258d940d 5651 #define USART_INTENCLR_DELTACTSCLR_MASK (0x20U)
Kojto 148:fd96258d940d 5652 #define USART_INTENCLR_DELTACTSCLR_SHIFT (5U)
Kojto 148:fd96258d940d 5653 #define USART_INTENCLR_DELTACTSCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK)
Kojto 148:fd96258d940d 5654 #define USART_INTENCLR_TXDISCLR_MASK (0x40U)
Kojto 148:fd96258d940d 5655 #define USART_INTENCLR_TXDISCLR_SHIFT (6U)
Kojto 148:fd96258d940d 5656 #define USART_INTENCLR_TXDISCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK)
Kojto 148:fd96258d940d 5657 #define USART_INTENCLR_DELTARXBRKCLR_MASK (0x800U)
Kojto 148:fd96258d940d 5658 #define USART_INTENCLR_DELTARXBRKCLR_SHIFT (11U)
Kojto 148:fd96258d940d 5659 #define USART_INTENCLR_DELTARXBRKCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK)
Kojto 148:fd96258d940d 5660 #define USART_INTENCLR_STARTCLR_MASK (0x1000U)
Kojto 148:fd96258d940d 5661 #define USART_INTENCLR_STARTCLR_SHIFT (12U)
Kojto 148:fd96258d940d 5662 #define USART_INTENCLR_STARTCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK)
Kojto 148:fd96258d940d 5663 #define USART_INTENCLR_FRAMERRCLR_MASK (0x2000U)
Kojto 148:fd96258d940d 5664 #define USART_INTENCLR_FRAMERRCLR_SHIFT (13U)
Kojto 148:fd96258d940d 5665 #define USART_INTENCLR_FRAMERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK)
Kojto 148:fd96258d940d 5666 #define USART_INTENCLR_PARITYERRCLR_MASK (0x4000U)
Kojto 148:fd96258d940d 5667 #define USART_INTENCLR_PARITYERRCLR_SHIFT (14U)
Kojto 148:fd96258d940d 5668 #define USART_INTENCLR_PARITYERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK)
Kojto 148:fd96258d940d 5669 #define USART_INTENCLR_RXNOISECLR_MASK (0x8000U)
Kojto 148:fd96258d940d 5670 #define USART_INTENCLR_RXNOISECLR_SHIFT (15U)
Kojto 148:fd96258d940d 5671 #define USART_INTENCLR_RXNOISECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK)
Kojto 148:fd96258d940d 5672 #define USART_INTENCLR_ABERRCLR_MASK (0x10000U)
Kojto 148:fd96258d940d 5673 #define USART_INTENCLR_ABERRCLR_SHIFT (16U)
Kojto 148:fd96258d940d 5674 #define USART_INTENCLR_ABERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK)
Kojto 148:fd96258d940d 5675
Kojto 148:fd96258d940d 5676 /*! @name BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. */
Kojto 148:fd96258d940d 5677 #define USART_BRG_BRGVAL_MASK (0xFFFFU)
Kojto 148:fd96258d940d 5678 #define USART_BRG_BRGVAL_SHIFT (0U)
Kojto 148:fd96258d940d 5679 #define USART_BRG_BRGVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK)
Kojto 148:fd96258d940d 5680
Kojto 148:fd96258d940d 5681 /*! @name INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. */
Kojto 148:fd96258d940d 5682 #define USART_INTSTAT_TXIDLE_MASK (0x8U)
Kojto 148:fd96258d940d 5683 #define USART_INTSTAT_TXIDLE_SHIFT (3U)
Kojto 148:fd96258d940d 5684 #define USART_INTSTAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK)
Kojto 148:fd96258d940d 5685 #define USART_INTSTAT_DELTACTS_MASK (0x20U)
Kojto 148:fd96258d940d 5686 #define USART_INTSTAT_DELTACTS_SHIFT (5U)
Kojto 148:fd96258d940d 5687 #define USART_INTSTAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK)
Kojto 148:fd96258d940d 5688 #define USART_INTSTAT_TXDISINT_MASK (0x40U)
Kojto 148:fd96258d940d 5689 #define USART_INTSTAT_TXDISINT_SHIFT (6U)
Kojto 148:fd96258d940d 5690 #define USART_INTSTAT_TXDISINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK)
Kojto 148:fd96258d940d 5691 #define USART_INTSTAT_DELTARXBRK_MASK (0x800U)
Kojto 148:fd96258d940d 5692 #define USART_INTSTAT_DELTARXBRK_SHIFT (11U)
Kojto 148:fd96258d940d 5693 #define USART_INTSTAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK)
Kojto 148:fd96258d940d 5694 #define USART_INTSTAT_START_MASK (0x1000U)
Kojto 148:fd96258d940d 5695 #define USART_INTSTAT_START_SHIFT (12U)
Kojto 148:fd96258d940d 5696 #define USART_INTSTAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK)
Kojto 148:fd96258d940d 5697 #define USART_INTSTAT_FRAMERRINT_MASK (0x2000U)
Kojto 148:fd96258d940d 5698 #define USART_INTSTAT_FRAMERRINT_SHIFT (13U)
Kojto 148:fd96258d940d 5699 #define USART_INTSTAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK)
Kojto 148:fd96258d940d 5700 #define USART_INTSTAT_PARITYERRINT_MASK (0x4000U)
Kojto 148:fd96258d940d 5701 #define USART_INTSTAT_PARITYERRINT_SHIFT (14U)
Kojto 148:fd96258d940d 5702 #define USART_INTSTAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK)
Kojto 148:fd96258d940d 5703 #define USART_INTSTAT_RXNOISEINT_MASK (0x8000U)
Kojto 148:fd96258d940d 5704 #define USART_INTSTAT_RXNOISEINT_SHIFT (15U)
Kojto 148:fd96258d940d 5705 #define USART_INTSTAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK)
Kojto 148:fd96258d940d 5706 #define USART_INTSTAT_ABERRINT_MASK (0x10000U)
Kojto 148:fd96258d940d 5707 #define USART_INTSTAT_ABERRINT_SHIFT (16U)
Kojto 148:fd96258d940d 5708 #define USART_INTSTAT_ABERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK)
Kojto 148:fd96258d940d 5709
Kojto 148:fd96258d940d 5710 /*! @name OSR - Oversample selection register for asynchronous communication. */
Kojto 148:fd96258d940d 5711 #define USART_OSR_OSRVAL_MASK (0xFU)
Kojto 148:fd96258d940d 5712 #define USART_OSR_OSRVAL_SHIFT (0U)
Kojto 148:fd96258d940d 5713 #define USART_OSR_OSRVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK)
Kojto 148:fd96258d940d 5714
Kojto 148:fd96258d940d 5715 /*! @name ADDR - Address register for automatic address matching. */
Kojto 148:fd96258d940d 5716 #define USART_ADDR_ADDRESS_MASK (0xFFU)
Kojto 148:fd96258d940d 5717 #define USART_ADDR_ADDRESS_SHIFT (0U)
Kojto 148:fd96258d940d 5718 #define USART_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK)
Kojto 148:fd96258d940d 5719
Kojto 148:fd96258d940d 5720 /*! @name FIFOCFG - FIFO configuration and enable register. */
Kojto 148:fd96258d940d 5721 #define USART_FIFOCFG_ENABLETX_MASK (0x1U)
Kojto 148:fd96258d940d 5722 #define USART_FIFOCFG_ENABLETX_SHIFT (0U)
Kojto 148:fd96258d940d 5723 #define USART_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK)
Kojto 148:fd96258d940d 5724 #define USART_FIFOCFG_ENABLERX_MASK (0x2U)
Kojto 148:fd96258d940d 5725 #define USART_FIFOCFG_ENABLERX_SHIFT (1U)
Kojto 148:fd96258d940d 5726 #define USART_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK)
Kojto 148:fd96258d940d 5727 #define USART_FIFOCFG_SIZE_MASK (0x30U)
Kojto 148:fd96258d940d 5728 #define USART_FIFOCFG_SIZE_SHIFT (4U)
Kojto 148:fd96258d940d 5729 #define USART_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK)
Kojto 148:fd96258d940d 5730 #define USART_FIFOCFG_DMATX_MASK (0x1000U)
Kojto 148:fd96258d940d 5731 #define USART_FIFOCFG_DMATX_SHIFT (12U)
Kojto 148:fd96258d940d 5732 #define USART_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK)
Kojto 148:fd96258d940d 5733 #define USART_FIFOCFG_DMARX_MASK (0x2000U)
Kojto 148:fd96258d940d 5734 #define USART_FIFOCFG_DMARX_SHIFT (13U)
Kojto 148:fd96258d940d 5735 #define USART_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK)
Kojto 148:fd96258d940d 5736 #define USART_FIFOCFG_WAKETX_MASK (0x4000U)
Kojto 148:fd96258d940d 5737 #define USART_FIFOCFG_WAKETX_SHIFT (14U)
Kojto 148:fd96258d940d 5738 #define USART_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK)
Kojto 148:fd96258d940d 5739 #define USART_FIFOCFG_WAKERX_MASK (0x8000U)
Kojto 148:fd96258d940d 5740 #define USART_FIFOCFG_WAKERX_SHIFT (15U)
Kojto 148:fd96258d940d 5741 #define USART_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK)
Kojto 148:fd96258d940d 5742 #define USART_FIFOCFG_EMPTYTX_MASK (0x10000U)
Kojto 148:fd96258d940d 5743 #define USART_FIFOCFG_EMPTYTX_SHIFT (16U)
Kojto 148:fd96258d940d 5744 #define USART_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK)
Kojto 148:fd96258d940d 5745 #define USART_FIFOCFG_EMPTYRX_MASK (0x20000U)
Kojto 148:fd96258d940d 5746 #define USART_FIFOCFG_EMPTYRX_SHIFT (17U)
Kojto 148:fd96258d940d 5747 #define USART_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK)
Kojto 148:fd96258d940d 5748
Kojto 148:fd96258d940d 5749 /*! @name FIFOSTAT - FIFO status register. */
Kojto 148:fd96258d940d 5750 #define USART_FIFOSTAT_TXERR_MASK (0x1U)
Kojto 148:fd96258d940d 5751 #define USART_FIFOSTAT_TXERR_SHIFT (0U)
Kojto 148:fd96258d940d 5752 #define USART_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK)
Kojto 148:fd96258d940d 5753 #define USART_FIFOSTAT_RXERR_MASK (0x2U)
Kojto 148:fd96258d940d 5754 #define USART_FIFOSTAT_RXERR_SHIFT (1U)
Kojto 148:fd96258d940d 5755 #define USART_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK)
Kojto 148:fd96258d940d 5756 #define USART_FIFOSTAT_PERINT_MASK (0x8U)
Kojto 148:fd96258d940d 5757 #define USART_FIFOSTAT_PERINT_SHIFT (3U)
Kojto 148:fd96258d940d 5758 #define USART_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK)
Kojto 148:fd96258d940d 5759 #define USART_FIFOSTAT_TXEMPTY_MASK (0x10U)
Kojto 148:fd96258d940d 5760 #define USART_FIFOSTAT_TXEMPTY_SHIFT (4U)
Kojto 148:fd96258d940d 5761 #define USART_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK)
Kojto 148:fd96258d940d 5762 #define USART_FIFOSTAT_TXNOTFULL_MASK (0x20U)
Kojto 148:fd96258d940d 5763 #define USART_FIFOSTAT_TXNOTFULL_SHIFT (5U)
Kojto 148:fd96258d940d 5764 #define USART_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK)
Kojto 148:fd96258d940d 5765 #define USART_FIFOSTAT_RXNOTEMPTY_MASK (0x40U)
Kojto 148:fd96258d940d 5766 #define USART_FIFOSTAT_RXNOTEMPTY_SHIFT (6U)
Kojto 148:fd96258d940d 5767 #define USART_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK)
Kojto 148:fd96258d940d 5768 #define USART_FIFOSTAT_RXFULL_MASK (0x80U)
Kojto 148:fd96258d940d 5769 #define USART_FIFOSTAT_RXFULL_SHIFT (7U)
Kojto 148:fd96258d940d 5770 #define USART_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK)
Kojto 148:fd96258d940d 5771 #define USART_FIFOSTAT_TXLVL_MASK (0x1F00U)
Kojto 148:fd96258d940d 5772 #define USART_FIFOSTAT_TXLVL_SHIFT (8U)
Kojto 148:fd96258d940d 5773 #define USART_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK)
Kojto 148:fd96258d940d 5774 #define USART_FIFOSTAT_RXLVL_MASK (0x1F0000U)
Kojto 148:fd96258d940d 5775 #define USART_FIFOSTAT_RXLVL_SHIFT (16U)
Kojto 148:fd96258d940d 5776 #define USART_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK)
Kojto 148:fd96258d940d 5777
Kojto 148:fd96258d940d 5778 /*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */
Kojto 148:fd96258d940d 5779 #define USART_FIFOTRIG_TXLVLENA_MASK (0x1U)
Kojto 148:fd96258d940d 5780 #define USART_FIFOTRIG_TXLVLENA_SHIFT (0U)
Kojto 148:fd96258d940d 5781 #define USART_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK)
Kojto 148:fd96258d940d 5782 #define USART_FIFOTRIG_RXLVLENA_MASK (0x2U)
Kojto 148:fd96258d940d 5783 #define USART_FIFOTRIG_RXLVLENA_SHIFT (1U)
Kojto 148:fd96258d940d 5784 #define USART_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK)
Kojto 148:fd96258d940d 5785 #define USART_FIFOTRIG_TXLVL_MASK (0xF00U)
Kojto 148:fd96258d940d 5786 #define USART_FIFOTRIG_TXLVL_SHIFT (8U)
Kojto 148:fd96258d940d 5787 #define USART_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK)
Kojto 148:fd96258d940d 5788 #define USART_FIFOTRIG_RXLVL_MASK (0xF0000U)
Kojto 148:fd96258d940d 5789 #define USART_FIFOTRIG_RXLVL_SHIFT (16U)
Kojto 148:fd96258d940d 5790 #define USART_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK)
Kojto 148:fd96258d940d 5791
Kojto 148:fd96258d940d 5792 /*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */
Kojto 148:fd96258d940d 5793 #define USART_FIFOINTENSET_TXERR_MASK (0x1U)
Kojto 148:fd96258d940d 5794 #define USART_FIFOINTENSET_TXERR_SHIFT (0U)
Kojto 148:fd96258d940d 5795 #define USART_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK)
Kojto 148:fd96258d940d 5796 #define USART_FIFOINTENSET_RXERR_MASK (0x2U)
Kojto 148:fd96258d940d 5797 #define USART_FIFOINTENSET_RXERR_SHIFT (1U)
Kojto 148:fd96258d940d 5798 #define USART_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK)
Kojto 148:fd96258d940d 5799 #define USART_FIFOINTENSET_TXLVL_MASK (0x4U)
Kojto 148:fd96258d940d 5800 #define USART_FIFOINTENSET_TXLVL_SHIFT (2U)
Kojto 148:fd96258d940d 5801 #define USART_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK)
Kojto 148:fd96258d940d 5802 #define USART_FIFOINTENSET_RXLVL_MASK (0x8U)
Kojto 148:fd96258d940d 5803 #define USART_FIFOINTENSET_RXLVL_SHIFT (3U)
Kojto 148:fd96258d940d 5804 #define USART_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK)
Kojto 148:fd96258d940d 5805
Kojto 148:fd96258d940d 5806 /*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */
Kojto 148:fd96258d940d 5807 #define USART_FIFOINTENCLR_TXERR_MASK (0x1U)
Kojto 148:fd96258d940d 5808 #define USART_FIFOINTENCLR_TXERR_SHIFT (0U)
Kojto 148:fd96258d940d 5809 #define USART_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK)
Kojto 148:fd96258d940d 5810 #define USART_FIFOINTENCLR_RXERR_MASK (0x2U)
Kojto 148:fd96258d940d 5811 #define USART_FIFOINTENCLR_RXERR_SHIFT (1U)
Kojto 148:fd96258d940d 5812 #define USART_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK)
Kojto 148:fd96258d940d 5813 #define USART_FIFOINTENCLR_TXLVL_MASK (0x4U)
Kojto 148:fd96258d940d 5814 #define USART_FIFOINTENCLR_TXLVL_SHIFT (2U)
Kojto 148:fd96258d940d 5815 #define USART_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK)
Kojto 148:fd96258d940d 5816 #define USART_FIFOINTENCLR_RXLVL_MASK (0x8U)
Kojto 148:fd96258d940d 5817 #define USART_FIFOINTENCLR_RXLVL_SHIFT (3U)
Kojto 148:fd96258d940d 5818 #define USART_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK)
Kojto 148:fd96258d940d 5819
Kojto 148:fd96258d940d 5820 /*! @name FIFOINTSTAT - FIFO interrupt status register. */
Kojto 148:fd96258d940d 5821 #define USART_FIFOINTSTAT_TXERR_MASK (0x1U)
Kojto 148:fd96258d940d 5822 #define USART_FIFOINTSTAT_TXERR_SHIFT (0U)
Kojto 148:fd96258d940d 5823 #define USART_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK)
Kojto 148:fd96258d940d 5824 #define USART_FIFOINTSTAT_RXERR_MASK (0x2U)
Kojto 148:fd96258d940d 5825 #define USART_FIFOINTSTAT_RXERR_SHIFT (1U)
Kojto 148:fd96258d940d 5826 #define USART_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK)
Kojto 148:fd96258d940d 5827 #define USART_FIFOINTSTAT_TXLVL_MASK (0x4U)
Kojto 148:fd96258d940d 5828 #define USART_FIFOINTSTAT_TXLVL_SHIFT (2U)
Kojto 148:fd96258d940d 5829 #define USART_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK)
Kojto 148:fd96258d940d 5830 #define USART_FIFOINTSTAT_RXLVL_MASK (0x8U)
Kojto 148:fd96258d940d 5831 #define USART_FIFOINTSTAT_RXLVL_SHIFT (3U)
Kojto 148:fd96258d940d 5832 #define USART_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK)
Kojto 148:fd96258d940d 5833 #define USART_FIFOINTSTAT_PERINT_MASK (0x10U)
Kojto 148:fd96258d940d 5834 #define USART_FIFOINTSTAT_PERINT_SHIFT (4U)
Kojto 148:fd96258d940d 5835 #define USART_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK)
Kojto 148:fd96258d940d 5836
Kojto 148:fd96258d940d 5837 /*! @name FIFOWR - FIFO write data. */
Kojto 148:fd96258d940d 5838 #define USART_FIFOWR_TXDATA_MASK (0x1FFU)
Kojto 148:fd96258d940d 5839 #define USART_FIFOWR_TXDATA_SHIFT (0U)
Kojto 148:fd96258d940d 5840 #define USART_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK)
Kojto 148:fd96258d940d 5841
Kojto 148:fd96258d940d 5842 /*! @name FIFORD - FIFO read data. */
Kojto 148:fd96258d940d 5843 #define USART_FIFORD_RXDATA_MASK (0x1FFU)
Kojto 148:fd96258d940d 5844 #define USART_FIFORD_RXDATA_SHIFT (0U)
Kojto 148:fd96258d940d 5845 #define USART_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK)
Kojto 148:fd96258d940d 5846 #define USART_FIFORD_FRAMERR_MASK (0x2000U)
Kojto 148:fd96258d940d 5847 #define USART_FIFORD_FRAMERR_SHIFT (13U)
Kojto 148:fd96258d940d 5848 #define USART_FIFORD_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK)
Kojto 148:fd96258d940d 5849 #define USART_FIFORD_PARITYERR_MASK (0x4000U)
Kojto 148:fd96258d940d 5850 #define USART_FIFORD_PARITYERR_SHIFT (14U)
Kojto 148:fd96258d940d 5851 #define USART_FIFORD_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK)
Kojto 148:fd96258d940d 5852 #define USART_FIFORD_RXNOISE_MASK (0x8000U)
Kojto 148:fd96258d940d 5853 #define USART_FIFORD_RXNOISE_SHIFT (15U)
Kojto 148:fd96258d940d 5854 #define USART_FIFORD_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK)
Kojto 148:fd96258d940d 5855
Kojto 148:fd96258d940d 5856 /*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */
Kojto 148:fd96258d940d 5857 #define USART_FIFORDNOPOP_RXDATA_MASK (0x1FFU)
Kojto 148:fd96258d940d 5858 #define USART_FIFORDNOPOP_RXDATA_SHIFT (0U)
Kojto 148:fd96258d940d 5859 #define USART_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK)
Kojto 148:fd96258d940d 5860 #define USART_FIFORDNOPOP_FRAMERR_MASK (0x2000U)
Kojto 148:fd96258d940d 5861 #define USART_FIFORDNOPOP_FRAMERR_SHIFT (13U)
Kojto 148:fd96258d940d 5862 #define USART_FIFORDNOPOP_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK)
Kojto 148:fd96258d940d 5863 #define USART_FIFORDNOPOP_PARITYERR_MASK (0x4000U)
Kojto 148:fd96258d940d 5864 #define USART_FIFORDNOPOP_PARITYERR_SHIFT (14U)
Kojto 148:fd96258d940d 5865 #define USART_FIFORDNOPOP_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK)
Kojto 148:fd96258d940d 5866 #define USART_FIFORDNOPOP_RXNOISE_MASK (0x8000U)
Kojto 148:fd96258d940d 5867 #define USART_FIFORDNOPOP_RXNOISE_SHIFT (15U)
Kojto 148:fd96258d940d 5868 #define USART_FIFORDNOPOP_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK)
Kojto 148:fd96258d940d 5869
Kojto 148:fd96258d940d 5870
Kojto 148:fd96258d940d 5871 /*!
Kojto 148:fd96258d940d 5872 * @}
Kojto 148:fd96258d940d 5873 */ /* end of group USART_Register_Masks */
Kojto 148:fd96258d940d 5874
Kojto 148:fd96258d940d 5875
Kojto 148:fd96258d940d 5876 /* USART - Peripheral instance base addresses */
Kojto 148:fd96258d940d 5877 /** Peripheral USART0 base address */
Kojto 148:fd96258d940d 5878 #define USART0_BASE (0x40086000u)
Kojto 148:fd96258d940d 5879 /** Peripheral USART0 base pointer */
Kojto 148:fd96258d940d 5880 #define USART0 ((USART_Type *)USART0_BASE)
Kojto 148:fd96258d940d 5881 /** Peripheral USART1 base address */
Kojto 148:fd96258d940d 5882 #define USART1_BASE (0x40087000u)
Kojto 148:fd96258d940d 5883 /** Peripheral USART1 base pointer */
Kojto 148:fd96258d940d 5884 #define USART1 ((USART_Type *)USART1_BASE)
Kojto 148:fd96258d940d 5885 /** Peripheral USART2 base address */
Kojto 148:fd96258d940d 5886 #define USART2_BASE (0x40088000u)
Kojto 148:fd96258d940d 5887 /** Peripheral USART2 base pointer */
Kojto 148:fd96258d940d 5888 #define USART2 ((USART_Type *)USART2_BASE)
Kojto 148:fd96258d940d 5889 /** Peripheral USART3 base address */
Kojto 148:fd96258d940d 5890 #define USART3_BASE (0x40089000u)
Kojto 148:fd96258d940d 5891 /** Peripheral USART3 base pointer */
Kojto 148:fd96258d940d 5892 #define USART3 ((USART_Type *)USART3_BASE)
Kojto 148:fd96258d940d 5893 /** Peripheral USART4 base address */
Kojto 148:fd96258d940d 5894 #define USART4_BASE (0x4008A000u)
Kojto 148:fd96258d940d 5895 /** Peripheral USART4 base pointer */
Kojto 148:fd96258d940d 5896 #define USART4 ((USART_Type *)USART4_BASE)
Kojto 148:fd96258d940d 5897 /** Peripheral USART5 base address */
Kojto 148:fd96258d940d 5898 #define USART5_BASE (0x40096000u)
Kojto 148:fd96258d940d 5899 /** Peripheral USART5 base pointer */
Kojto 148:fd96258d940d 5900 #define USART5 ((USART_Type *)USART5_BASE)
Kojto 148:fd96258d940d 5901 /** Peripheral USART6 base address */
Kojto 148:fd96258d940d 5902 #define USART6_BASE (0x40097000u)
Kojto 148:fd96258d940d 5903 /** Peripheral USART6 base pointer */
Kojto 148:fd96258d940d 5904 #define USART6 ((USART_Type *)USART6_BASE)
Kojto 148:fd96258d940d 5905 /** Peripheral USART7 base address */
Kojto 148:fd96258d940d 5906 #define USART7_BASE (0x40098000u)
Kojto 148:fd96258d940d 5907 /** Peripheral USART7 base pointer */
Kojto 148:fd96258d940d 5908 #define USART7 ((USART_Type *)USART7_BASE)
Kojto 148:fd96258d940d 5909 /** Array initializer of USART peripheral base addresses */
Kojto 148:fd96258d940d 5910 #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE }
Kojto 148:fd96258d940d 5911 /** Array initializer of USART peripheral base pointers */
Kojto 148:fd96258d940d 5912 #define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 }
Kojto 148:fd96258d940d 5913 /** Interrupt vectors for the USART peripheral type */
Kojto 148:fd96258d940d 5914 #define USART_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn }
Kojto 148:fd96258d940d 5915
Kojto 148:fd96258d940d 5916 /*!
Kojto 148:fd96258d940d 5917 * @}
Kojto 148:fd96258d940d 5918 */ /* end of group USART_Peripheral_Access_Layer */
Kojto 148:fd96258d940d 5919
Kojto 148:fd96258d940d 5920
Kojto 148:fd96258d940d 5921 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 5922 -- USB Peripheral Access Layer
Kojto 148:fd96258d940d 5923 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 5924
Kojto 148:fd96258d940d 5925 /*!
Kojto 148:fd96258d940d 5926 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
Kojto 148:fd96258d940d 5927 * @{
Kojto 148:fd96258d940d 5928 */
Kojto 148:fd96258d940d 5929
Kojto 148:fd96258d940d 5930 /** USB - Register Layout Typedef */
Kojto 148:fd96258d940d 5931 typedef struct {
Kojto 148:fd96258d940d 5932 __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */
Kojto 148:fd96258d940d 5933 __IO uint32_t INFO; /**< USB Info register, offset: 0x4 */
Kojto 148:fd96258d940d 5934 __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */
Kojto 148:fd96258d940d 5935 __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */
Kojto 148:fd96258d940d 5936 __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */
Kojto 148:fd96258d940d 5937 __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */
Kojto 148:fd96258d940d 5938 __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */
Kojto 148:fd96258d940d 5939 __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */
Kojto 148:fd96258d940d 5940 __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */
Kojto 148:fd96258d940d 5941 __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */
Kojto 148:fd96258d940d 5942 __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */
Kojto 148:fd96258d940d 5943 uint8_t RESERVED_0[8];
Kojto 148:fd96258d940d 5944 __I uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */
Kojto 148:fd96258d940d 5945 } USB_Type;
Kojto 148:fd96258d940d 5946
Kojto 148:fd96258d940d 5947 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 5948 -- USB Register Masks
Kojto 148:fd96258d940d 5949 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 5950
Kojto 148:fd96258d940d 5951 /*!
Kojto 148:fd96258d940d 5952 * @addtogroup USB_Register_Masks USB Register Masks
Kojto 148:fd96258d940d 5953 * @{
Kojto 148:fd96258d940d 5954 */
Kojto 148:fd96258d940d 5955
Kojto 148:fd96258d940d 5956 /*! @name DEVCMDSTAT - USB Device Command/Status register */
Kojto 148:fd96258d940d 5957 #define USB_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU)
Kojto 148:fd96258d940d 5958 #define USB_DEVCMDSTAT_DEV_ADDR_SHIFT (0U)
Kojto 148:fd96258d940d 5959 #define USB_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK)
Kojto 148:fd96258d940d 5960 #define USB_DEVCMDSTAT_DEV_EN_MASK (0x80U)
Kojto 148:fd96258d940d 5961 #define USB_DEVCMDSTAT_DEV_EN_SHIFT (7U)
Kojto 148:fd96258d940d 5962 #define USB_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_EN_SHIFT)) & USB_DEVCMDSTAT_DEV_EN_MASK)
Kojto 148:fd96258d940d 5963 #define USB_DEVCMDSTAT_SETUP_MASK (0x100U)
Kojto 148:fd96258d940d 5964 #define USB_DEVCMDSTAT_SETUP_SHIFT (8U)
Kojto 148:fd96258d940d 5965 #define USB_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_SETUP_SHIFT)) & USB_DEVCMDSTAT_SETUP_MASK)
Kojto 148:fd96258d940d 5966 #define USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U)
Kojto 148:fd96258d940d 5967 #define USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U)
Kojto 148:fd96258d940d 5968 #define USB_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK)
Kojto 148:fd96258d940d 5969 #define USB_DEVCMDSTAT_LPM_SUP_MASK (0x800U)
Kojto 148:fd96258d940d 5970 #define USB_DEVCMDSTAT_LPM_SUP_SHIFT (11U)
Kojto 148:fd96258d940d 5971 #define USB_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUP_SHIFT)) & USB_DEVCMDSTAT_LPM_SUP_MASK)
Kojto 148:fd96258d940d 5972 #define USB_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U)
Kojto 148:fd96258d940d 5973 #define USB_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U)
Kojto 148:fd96258d940d 5974 #define USB_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AO_MASK)
Kojto 148:fd96258d940d 5975 #define USB_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U)
Kojto 148:fd96258d940d 5976 #define USB_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U)
Kojto 148:fd96258d940d 5977 #define USB_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AI_MASK)
Kojto 148:fd96258d940d 5978 #define USB_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U)
Kojto 148:fd96258d940d 5979 #define USB_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U)
Kojto 148:fd96258d940d 5980 #define USB_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CO_MASK)
Kojto 148:fd96258d940d 5981 #define USB_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U)
Kojto 148:fd96258d940d 5982 #define USB_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U)
Kojto 148:fd96258d940d 5983 #define USB_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CI_MASK)
Kojto 148:fd96258d940d 5984 #define USB_DEVCMDSTAT_DCON_MASK (0x10000U)
Kojto 148:fd96258d940d 5985 #define USB_DEVCMDSTAT_DCON_SHIFT (16U)
Kojto 148:fd96258d940d 5986 #define USB_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_SHIFT)) & USB_DEVCMDSTAT_DCON_MASK)
Kojto 148:fd96258d940d 5987 #define USB_DEVCMDSTAT_DSUS_MASK (0x20000U)
Kojto 148:fd96258d940d 5988 #define USB_DEVCMDSTAT_DSUS_SHIFT (17U)
Kojto 148:fd96258d940d 5989 #define USB_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_SHIFT)) & USB_DEVCMDSTAT_DSUS_MASK)
Kojto 148:fd96258d940d 5990 #define USB_DEVCMDSTAT_LPM_SUS_MASK (0x80000U)
Kojto 148:fd96258d940d 5991 #define USB_DEVCMDSTAT_LPM_SUS_SHIFT (19U)
Kojto 148:fd96258d940d 5992 #define USB_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUS_SHIFT)) & USB_DEVCMDSTAT_LPM_SUS_MASK)
Kojto 148:fd96258d940d 5993 #define USB_DEVCMDSTAT_LPM_REWP_MASK (0x100000U)
Kojto 148:fd96258d940d 5994 #define USB_DEVCMDSTAT_LPM_REWP_SHIFT (20U)
Kojto 148:fd96258d940d 5995 #define USB_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_REWP_SHIFT)) & USB_DEVCMDSTAT_LPM_REWP_MASK)
Kojto 148:fd96258d940d 5996 #define USB_DEVCMDSTAT_DCON_C_MASK (0x1000000U)
Kojto 148:fd96258d940d 5997 #define USB_DEVCMDSTAT_DCON_C_SHIFT (24U)
Kojto 148:fd96258d940d 5998 #define USB_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_C_SHIFT)) & USB_DEVCMDSTAT_DCON_C_MASK)
Kojto 148:fd96258d940d 5999 #define USB_DEVCMDSTAT_DSUS_C_MASK (0x2000000U)
Kojto 148:fd96258d940d 6000 #define USB_DEVCMDSTAT_DSUS_C_SHIFT (25U)
Kojto 148:fd96258d940d 6001 #define USB_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_C_SHIFT)) & USB_DEVCMDSTAT_DSUS_C_MASK)
Kojto 148:fd96258d940d 6002 #define USB_DEVCMDSTAT_DRES_C_MASK (0x4000000U)
Kojto 148:fd96258d940d 6003 #define USB_DEVCMDSTAT_DRES_C_SHIFT (26U)
Kojto 148:fd96258d940d 6004 #define USB_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DRES_C_SHIFT)) & USB_DEVCMDSTAT_DRES_C_MASK)
Kojto 148:fd96258d940d 6005 #define USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK (0x10000000U)
Kojto 148:fd96258d940d 6006 #define USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT (28U)
Kojto 148:fd96258d940d 6007 #define USB_DEVCMDSTAT_VBUSDEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK)
Kojto 148:fd96258d940d 6008
Kojto 148:fd96258d940d 6009 /*! @name INFO - USB Info register */
Kojto 148:fd96258d940d 6010 #define USB_INFO_FRAME_NR_MASK (0x7FFU)
Kojto 148:fd96258d940d 6011 #define USB_INFO_FRAME_NR_SHIFT (0U)
Kojto 148:fd96258d940d 6012 #define USB_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK)
Kojto 148:fd96258d940d 6013 #define USB_INFO_ERR_CODE_MASK (0x7800U)
Kojto 148:fd96258d940d 6014 #define USB_INFO_ERR_CODE_SHIFT (11U)
Kojto 148:fd96258d940d 6015 #define USB_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK)
Kojto 148:fd96258d940d 6016
Kojto 148:fd96258d940d 6017 /*! @name EPLISTSTART - USB EP Command/Status List start address */
Kojto 148:fd96258d940d 6018 #define USB_EPLISTSTART_EP_LIST_MASK (0xFFFFFF00U)
Kojto 148:fd96258d940d 6019 #define USB_EPLISTSTART_EP_LIST_SHIFT (8U)
Kojto 148:fd96258d940d 6020 #define USB_EPLISTSTART_EP_LIST(x) (((uint32_t)(((uint32_t)(x)) << USB_EPLISTSTART_EP_LIST_SHIFT)) & USB_EPLISTSTART_EP_LIST_MASK)
Kojto 148:fd96258d940d 6021
Kojto 148:fd96258d940d 6022 /*! @name DATABUFSTART - USB Data buffer start address */
Kojto 148:fd96258d940d 6023 #define USB_DATABUFSTART_DA_BUF_MASK (0xFFC00000U)
Kojto 148:fd96258d940d 6024 #define USB_DATABUFSTART_DA_BUF_SHIFT (22U)
Kojto 148:fd96258d940d 6025 #define USB_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_DATABUFSTART_DA_BUF_SHIFT)) & USB_DATABUFSTART_DA_BUF_MASK)
Kojto 148:fd96258d940d 6026
Kojto 148:fd96258d940d 6027 /*! @name LPM - USB Link Power Management register */
Kojto 148:fd96258d940d 6028 #define USB_LPM_HIRD_HW_MASK (0xFU)
Kojto 148:fd96258d940d 6029 #define USB_LPM_HIRD_HW_SHIFT (0U)
Kojto 148:fd96258d940d 6030 #define USB_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_HW_SHIFT)) & USB_LPM_HIRD_HW_MASK)
Kojto 148:fd96258d940d 6031 #define USB_LPM_HIRD_SW_MASK (0xF0U)
Kojto 148:fd96258d940d 6032 #define USB_LPM_HIRD_SW_SHIFT (4U)
Kojto 148:fd96258d940d 6033 #define USB_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_SW_SHIFT)) & USB_LPM_HIRD_SW_MASK)
Kojto 148:fd96258d940d 6034 #define USB_LPM_DATA_PENDING_MASK (0x100U)
Kojto 148:fd96258d940d 6035 #define USB_LPM_DATA_PENDING_SHIFT (8U)
Kojto 148:fd96258d940d 6036 #define USB_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_DATA_PENDING_SHIFT)) & USB_LPM_DATA_PENDING_MASK)
Kojto 148:fd96258d940d 6037
Kojto 148:fd96258d940d 6038 /*! @name EPSKIP - USB Endpoint skip */
Kojto 148:fd96258d940d 6039 #define USB_EPSKIP_SKIP_MASK (0x3FFFFFFFU)
Kojto 148:fd96258d940d 6040 #define USB_EPSKIP_SKIP_SHIFT (0U)
Kojto 148:fd96258d940d 6041 #define USB_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USB_EPSKIP_SKIP_SHIFT)) & USB_EPSKIP_SKIP_MASK)
Kojto 148:fd96258d940d 6042
Kojto 148:fd96258d940d 6043 /*! @name EPINUSE - USB Endpoint Buffer in use */
Kojto 148:fd96258d940d 6044 #define USB_EPINUSE_BUF_MASK (0x3FCU)
Kojto 148:fd96258d940d 6045 #define USB_EPINUSE_BUF_SHIFT (2U)
Kojto 148:fd96258d940d 6046 #define USB_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_EPINUSE_BUF_SHIFT)) & USB_EPINUSE_BUF_MASK)
Kojto 148:fd96258d940d 6047
Kojto 148:fd96258d940d 6048 /*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */
Kojto 148:fd96258d940d 6049 #define USB_EPBUFCFG_BUF_SB_MASK (0x3FCU)
Kojto 148:fd96258d940d 6050 #define USB_EPBUFCFG_BUF_SB_SHIFT (2U)
Kojto 148:fd96258d940d 6051 #define USB_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USB_EPBUFCFG_BUF_SB_SHIFT)) & USB_EPBUFCFG_BUF_SB_MASK)
Kojto 148:fd96258d940d 6052
Kojto 148:fd96258d940d 6053 /*! @name INTSTAT - USB interrupt status register */
Kojto 148:fd96258d940d 6054 #define USB_INTSTAT_EP0OUT_MASK (0x1U)
Kojto 148:fd96258d940d 6055 #define USB_INTSTAT_EP0OUT_SHIFT (0U)
Kojto 148:fd96258d940d 6056 #define USB_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0OUT_SHIFT)) & USB_INTSTAT_EP0OUT_MASK)
Kojto 148:fd96258d940d 6057 #define USB_INTSTAT_EP0IN_MASK (0x2U)
Kojto 148:fd96258d940d 6058 #define USB_INTSTAT_EP0IN_SHIFT (1U)
Kojto 148:fd96258d940d 6059 #define USB_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0IN_SHIFT)) & USB_INTSTAT_EP0IN_MASK)
Kojto 148:fd96258d940d 6060 #define USB_INTSTAT_EP1OUT_MASK (0x4U)
Kojto 148:fd96258d940d 6061 #define USB_INTSTAT_EP1OUT_SHIFT (2U)
Kojto 148:fd96258d940d 6062 #define USB_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1OUT_SHIFT)) & USB_INTSTAT_EP1OUT_MASK)
Kojto 148:fd96258d940d 6063 #define USB_INTSTAT_EP1IN_MASK (0x8U)
Kojto 148:fd96258d940d 6064 #define USB_INTSTAT_EP1IN_SHIFT (3U)
Kojto 148:fd96258d940d 6065 #define USB_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1IN_SHIFT)) & USB_INTSTAT_EP1IN_MASK)
Kojto 148:fd96258d940d 6066 #define USB_INTSTAT_EP2OUT_MASK (0x10U)
Kojto 148:fd96258d940d 6067 #define USB_INTSTAT_EP2OUT_SHIFT (4U)
Kojto 148:fd96258d940d 6068 #define USB_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2OUT_SHIFT)) & USB_INTSTAT_EP2OUT_MASK)
Kojto 148:fd96258d940d 6069 #define USB_INTSTAT_EP2IN_MASK (0x20U)
Kojto 148:fd96258d940d 6070 #define USB_INTSTAT_EP2IN_SHIFT (5U)
Kojto 148:fd96258d940d 6071 #define USB_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2IN_SHIFT)) & USB_INTSTAT_EP2IN_MASK)
Kojto 148:fd96258d940d 6072 #define USB_INTSTAT_EP3OUT_MASK (0x40U)
Kojto 148:fd96258d940d 6073 #define USB_INTSTAT_EP3OUT_SHIFT (6U)
Kojto 148:fd96258d940d 6074 #define USB_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3OUT_SHIFT)) & USB_INTSTAT_EP3OUT_MASK)
Kojto 148:fd96258d940d 6075 #define USB_INTSTAT_EP3IN_MASK (0x80U)
Kojto 148:fd96258d940d 6076 #define USB_INTSTAT_EP3IN_SHIFT (7U)
Kojto 148:fd96258d940d 6077 #define USB_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3IN_SHIFT)) & USB_INTSTAT_EP3IN_MASK)
Kojto 148:fd96258d940d 6078 #define USB_INTSTAT_EP4OUT_MASK (0x100U)
Kojto 148:fd96258d940d 6079 #define USB_INTSTAT_EP4OUT_SHIFT (8U)
Kojto 148:fd96258d940d 6080 #define USB_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4OUT_SHIFT)) & USB_INTSTAT_EP4OUT_MASK)
Kojto 148:fd96258d940d 6081 #define USB_INTSTAT_EP4IN_MASK (0x200U)
Kojto 148:fd96258d940d 6082 #define USB_INTSTAT_EP4IN_SHIFT (9U)
Kojto 148:fd96258d940d 6083 #define USB_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4IN_SHIFT)) & USB_INTSTAT_EP4IN_MASK)
Kojto 148:fd96258d940d 6084 #define USB_INTSTAT_FRAME_INT_MASK (0x40000000U)
Kojto 148:fd96258d940d 6085 #define USB_INTSTAT_FRAME_INT_SHIFT (30U)
Kojto 148:fd96258d940d 6086 #define USB_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_FRAME_INT_SHIFT)) & USB_INTSTAT_FRAME_INT_MASK)
Kojto 148:fd96258d940d 6087 #define USB_INTSTAT_DEV_INT_MASK (0x80000000U)
Kojto 148:fd96258d940d 6088 #define USB_INTSTAT_DEV_INT_SHIFT (31U)
Kojto 148:fd96258d940d 6089 #define USB_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_DEV_INT_SHIFT)) & USB_INTSTAT_DEV_INT_MASK)
Kojto 148:fd96258d940d 6090
Kojto 148:fd96258d940d 6091 /*! @name INTEN - USB interrupt enable register */
Kojto 148:fd96258d940d 6092 #define USB_INTEN_EP_INT_EN_MASK (0x3FFU)
Kojto 148:fd96258d940d 6093 #define USB_INTEN_EP_INT_EN_SHIFT (0U)
Kojto 148:fd96258d940d 6094 #define USB_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_EP_INT_EN_SHIFT)) & USB_INTEN_EP_INT_EN_MASK)
Kojto 148:fd96258d940d 6095 #define USB_INTEN_FRAME_INT_EN_MASK (0x40000000U)
Kojto 148:fd96258d940d 6096 #define USB_INTEN_FRAME_INT_EN_SHIFT (30U)
Kojto 148:fd96258d940d 6097 #define USB_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_FRAME_INT_EN_SHIFT)) & USB_INTEN_FRAME_INT_EN_MASK)
Kojto 148:fd96258d940d 6098 #define USB_INTEN_DEV_INT_EN_MASK (0x80000000U)
Kojto 148:fd96258d940d 6099 #define USB_INTEN_DEV_INT_EN_SHIFT (31U)
Kojto 148:fd96258d940d 6100 #define USB_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_DEV_INT_EN_SHIFT)) & USB_INTEN_DEV_INT_EN_MASK)
Kojto 148:fd96258d940d 6101
Kojto 148:fd96258d940d 6102 /*! @name INTSETSTAT - USB set interrupt status register */
Kojto 148:fd96258d940d 6103 #define USB_INTSETSTAT_EP_SET_INT_MASK (0x3FFU)
Kojto 148:fd96258d940d 6104 #define USB_INTSETSTAT_EP_SET_INT_SHIFT (0U)
Kojto 148:fd96258d940d 6105 #define USB_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_EP_SET_INT_SHIFT)) & USB_INTSETSTAT_EP_SET_INT_MASK)
Kojto 148:fd96258d940d 6106 #define USB_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U)
Kojto 148:fd96258d940d 6107 #define USB_INTSETSTAT_FRAME_SET_INT_SHIFT (30U)
Kojto 148:fd96258d940d 6108 #define USB_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USB_INTSETSTAT_FRAME_SET_INT_MASK)
Kojto 148:fd96258d940d 6109 #define USB_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U)
Kojto 148:fd96258d940d 6110 #define USB_INTSETSTAT_DEV_SET_INT_SHIFT (31U)
Kojto 148:fd96258d940d 6111 #define USB_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_DEV_SET_INT_SHIFT)) & USB_INTSETSTAT_DEV_SET_INT_MASK)
Kojto 148:fd96258d940d 6112
Kojto 148:fd96258d940d 6113 /*! @name EPTOGGLE - USB Endpoint toggle register */
Kojto 148:fd96258d940d 6114 #define USB_EPTOGGLE_TOGGLE_MASK (0x3FFU)
Kojto 148:fd96258d940d 6115 #define USB_EPTOGGLE_TOGGLE_SHIFT (0U)
Kojto 148:fd96258d940d 6116 #define USB_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USB_EPTOGGLE_TOGGLE_SHIFT)) & USB_EPTOGGLE_TOGGLE_MASK)
Kojto 148:fd96258d940d 6117
Kojto 148:fd96258d940d 6118
Kojto 148:fd96258d940d 6119 /*!
Kojto 148:fd96258d940d 6120 * @}
Kojto 148:fd96258d940d 6121 */ /* end of group USB_Register_Masks */
Kojto 148:fd96258d940d 6122
Kojto 148:fd96258d940d 6123
Kojto 148:fd96258d940d 6124 /* USB - Peripheral instance base addresses */
Kojto 148:fd96258d940d 6125 /** Peripheral USB0 base address */
Kojto 148:fd96258d940d 6126 #define USB0_BASE (0x40084000u)
Kojto 148:fd96258d940d 6127 /** Peripheral USB0 base pointer */
Kojto 148:fd96258d940d 6128 #define USB0 ((USB_Type *)USB0_BASE)
Kojto 148:fd96258d940d 6129 /** Array initializer of USB peripheral base addresses */
Kojto 148:fd96258d940d 6130 #define USB_BASE_ADDRS { USB0_BASE }
Kojto 148:fd96258d940d 6131 /** Array initializer of USB peripheral base pointers */
Kojto 148:fd96258d940d 6132 #define USB_BASE_PTRS { USB0 }
Kojto 148:fd96258d940d 6133 /** Interrupt vectors for the USB peripheral type */
Kojto 148:fd96258d940d 6134 #define USB_IRQS { USB0_IRQn }
Kojto 148:fd96258d940d 6135 #define USB_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn }
Kojto 148:fd96258d940d 6136
Kojto 148:fd96258d940d 6137 /*!
Kojto 148:fd96258d940d 6138 * @}
Kojto 148:fd96258d940d 6139 */ /* end of group USB_Peripheral_Access_Layer */
Kojto 148:fd96258d940d 6140
Kojto 148:fd96258d940d 6141
Kojto 148:fd96258d940d 6142 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 6143 -- UTICK Peripheral Access Layer
Kojto 148:fd96258d940d 6144 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 6145
Kojto 148:fd96258d940d 6146 /*!
Kojto 148:fd96258d940d 6147 * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer
Kojto 148:fd96258d940d 6148 * @{
Kojto 148:fd96258d940d 6149 */
Kojto 148:fd96258d940d 6150
Kojto 148:fd96258d940d 6151 /** UTICK - Register Layout Typedef */
Kojto 148:fd96258d940d 6152 typedef struct {
Kojto 148:fd96258d940d 6153 __IO uint32_t CTRL; /**< Control register., offset: 0x0 */
Kojto 148:fd96258d940d 6154 __IO uint32_t STAT; /**< Status register., offset: 0x4 */
Kojto 148:fd96258d940d 6155 __IO uint32_t CFG; /**< Capture configuration register., offset: 0x8 */
Kojto 148:fd96258d940d 6156 __O uint32_t CAPCLR; /**< Capture clear register., offset: 0xC */
Kojto 148:fd96258d940d 6157 __I uint32_t CAP[4]; /**< Capture register ., array offset: 0x10, array step: 0x4 */
Kojto 148:fd96258d940d 6158 } UTICK_Type;
Kojto 148:fd96258d940d 6159
Kojto 148:fd96258d940d 6160 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 6161 -- UTICK Register Masks
Kojto 148:fd96258d940d 6162 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 6163
Kojto 148:fd96258d940d 6164 /*!
Kojto 148:fd96258d940d 6165 * @addtogroup UTICK_Register_Masks UTICK Register Masks
Kojto 148:fd96258d940d 6166 * @{
Kojto 148:fd96258d940d 6167 */
Kojto 148:fd96258d940d 6168
Kojto 148:fd96258d940d 6169 /*! @name CTRL - Control register. */
Kojto 148:fd96258d940d 6170 #define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU)
Kojto 148:fd96258d940d 6171 #define UTICK_CTRL_DELAYVAL_SHIFT (0U)
Kojto 148:fd96258d940d 6172 #define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK)
Kojto 148:fd96258d940d 6173 #define UTICK_CTRL_REPEAT_MASK (0x80000000U)
Kojto 148:fd96258d940d 6174 #define UTICK_CTRL_REPEAT_SHIFT (31U)
Kojto 148:fd96258d940d 6175 #define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK)
Kojto 148:fd96258d940d 6176
Kojto 148:fd96258d940d 6177 /*! @name STAT - Status register. */
Kojto 148:fd96258d940d 6178 #define UTICK_STAT_INTR_MASK (0x1U)
Kojto 148:fd96258d940d 6179 #define UTICK_STAT_INTR_SHIFT (0U)
Kojto 148:fd96258d940d 6180 #define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK)
Kojto 148:fd96258d940d 6181 #define UTICK_STAT_ACTIVE_MASK (0x2U)
Kojto 148:fd96258d940d 6182 #define UTICK_STAT_ACTIVE_SHIFT (1U)
Kojto 148:fd96258d940d 6183 #define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK)
Kojto 148:fd96258d940d 6184
Kojto 148:fd96258d940d 6185 /*! @name CFG - Capture configuration register. */
Kojto 148:fd96258d940d 6186 #define UTICK_CFG_CAPEN0_MASK (0x1U)
Kojto 148:fd96258d940d 6187 #define UTICK_CFG_CAPEN0_SHIFT (0U)
Kojto 148:fd96258d940d 6188 #define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK)
Kojto 148:fd96258d940d 6189 #define UTICK_CFG_CAPEN1_MASK (0x2U)
Kojto 148:fd96258d940d 6190 #define UTICK_CFG_CAPEN1_SHIFT (1U)
Kojto 148:fd96258d940d 6191 #define UTICK_CFG_CAPEN1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK)
Kojto 148:fd96258d940d 6192 #define UTICK_CFG_CAPEN2_MASK (0x4U)
Kojto 148:fd96258d940d 6193 #define UTICK_CFG_CAPEN2_SHIFT (2U)
Kojto 148:fd96258d940d 6194 #define UTICK_CFG_CAPEN2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK)
Kojto 148:fd96258d940d 6195 #define UTICK_CFG_CAPEN3_MASK (0x8U)
Kojto 148:fd96258d940d 6196 #define UTICK_CFG_CAPEN3_SHIFT (3U)
Kojto 148:fd96258d940d 6197 #define UTICK_CFG_CAPEN3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK)
Kojto 148:fd96258d940d 6198 #define UTICK_CFG_CAPPOL0_MASK (0x100U)
Kojto 148:fd96258d940d 6199 #define UTICK_CFG_CAPPOL0_SHIFT (8U)
Kojto 148:fd96258d940d 6200 #define UTICK_CFG_CAPPOL0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK)
Kojto 148:fd96258d940d 6201 #define UTICK_CFG_CAPPOL1_MASK (0x200U)
Kojto 148:fd96258d940d 6202 #define UTICK_CFG_CAPPOL1_SHIFT (9U)
Kojto 148:fd96258d940d 6203 #define UTICK_CFG_CAPPOL1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK)
Kojto 148:fd96258d940d 6204 #define UTICK_CFG_CAPPOL2_MASK (0x400U)
Kojto 148:fd96258d940d 6205 #define UTICK_CFG_CAPPOL2_SHIFT (10U)
Kojto 148:fd96258d940d 6206 #define UTICK_CFG_CAPPOL2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK)
Kojto 148:fd96258d940d 6207 #define UTICK_CFG_CAPPOL3_MASK (0x800U)
Kojto 148:fd96258d940d 6208 #define UTICK_CFG_CAPPOL3_SHIFT (11U)
Kojto 148:fd96258d940d 6209 #define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK)
Kojto 148:fd96258d940d 6210
Kojto 148:fd96258d940d 6211 /*! @name CAPCLR - Capture clear register. */
Kojto 148:fd96258d940d 6212 #define UTICK_CAPCLR_CAPCLR0_MASK (0x1U)
Kojto 148:fd96258d940d 6213 #define UTICK_CAPCLR_CAPCLR0_SHIFT (0U)
Kojto 148:fd96258d940d 6214 #define UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK)
Kojto 148:fd96258d940d 6215 #define UTICK_CAPCLR_CAPCLR1_MASK (0x2U)
Kojto 148:fd96258d940d 6216 #define UTICK_CAPCLR_CAPCLR1_SHIFT (1U)
Kojto 148:fd96258d940d 6217 #define UTICK_CAPCLR_CAPCLR1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK)
Kojto 148:fd96258d940d 6218 #define UTICK_CAPCLR_CAPCLR2_MASK (0x4U)
Kojto 148:fd96258d940d 6219 #define UTICK_CAPCLR_CAPCLR2_SHIFT (2U)
Kojto 148:fd96258d940d 6220 #define UTICK_CAPCLR_CAPCLR2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK)
Kojto 148:fd96258d940d 6221 #define UTICK_CAPCLR_CAPCLR3_MASK (0x8U)
Kojto 148:fd96258d940d 6222 #define UTICK_CAPCLR_CAPCLR3_SHIFT (3U)
Kojto 148:fd96258d940d 6223 #define UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK)
Kojto 148:fd96258d940d 6224
Kojto 148:fd96258d940d 6225 /*! @name CAP - Capture register . */
Kojto 148:fd96258d940d 6226 #define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU)
Kojto 148:fd96258d940d 6227 #define UTICK_CAP_CAP_VALUE_SHIFT (0U)
Kojto 148:fd96258d940d 6228 #define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK)
Kojto 148:fd96258d940d 6229 #define UTICK_CAP_VALID_MASK (0x80000000U)
Kojto 148:fd96258d940d 6230 #define UTICK_CAP_VALID_SHIFT (31U)
Kojto 148:fd96258d940d 6231 #define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK)
Kojto 148:fd96258d940d 6232
Kojto 148:fd96258d940d 6233 /* The count of UTICK_CAP */
Kojto 148:fd96258d940d 6234 #define UTICK_CAP_COUNT (4U)
Kojto 148:fd96258d940d 6235
Kojto 148:fd96258d940d 6236
Kojto 148:fd96258d940d 6237 /*!
Kojto 148:fd96258d940d 6238 * @}
Kojto 148:fd96258d940d 6239 */ /* end of group UTICK_Register_Masks */
Kojto 148:fd96258d940d 6240
Kojto 148:fd96258d940d 6241
Kojto 148:fd96258d940d 6242 /* UTICK - Peripheral instance base addresses */
Kojto 148:fd96258d940d 6243 /** Peripheral UTICK0 base address */
Kojto 148:fd96258d940d 6244 #define UTICK0_BASE (0x4000E000u)
Kojto 148:fd96258d940d 6245 /** Peripheral UTICK0 base pointer */
Kojto 148:fd96258d940d 6246 #define UTICK0 ((UTICK_Type *)UTICK0_BASE)
Kojto 148:fd96258d940d 6247 /** Array initializer of UTICK peripheral base addresses */
Kojto 148:fd96258d940d 6248 #define UTICK_BASE_ADDRS { UTICK0_BASE }
Kojto 148:fd96258d940d 6249 /** Array initializer of UTICK peripheral base pointers */
Kojto 148:fd96258d940d 6250 #define UTICK_BASE_PTRS { UTICK0 }
Kojto 148:fd96258d940d 6251 /** Interrupt vectors for the UTICK peripheral type */
Kojto 148:fd96258d940d 6252 #define UTICK_IRQS { UTICK0_IRQn }
Kojto 148:fd96258d940d 6253
Kojto 148:fd96258d940d 6254 /*!
Kojto 148:fd96258d940d 6255 * @}
Kojto 148:fd96258d940d 6256 */ /* end of group UTICK_Peripheral_Access_Layer */
Kojto 148:fd96258d940d 6257
Kojto 148:fd96258d940d 6258
Kojto 148:fd96258d940d 6259 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 6260 -- WWDT Peripheral Access Layer
Kojto 148:fd96258d940d 6261 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 6262
Kojto 148:fd96258d940d 6263 /*!
Kojto 148:fd96258d940d 6264 * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer
Kojto 148:fd96258d940d 6265 * @{
Kojto 148:fd96258d940d 6266 */
Kojto 148:fd96258d940d 6267
Kojto 148:fd96258d940d 6268 /** WWDT - Register Layout Typedef */
Kojto 148:fd96258d940d 6269 typedef struct {
Kojto 148:fd96258d940d 6270 __IO uint32_t MOD; /**< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer., offset: 0x0 */
Kojto 148:fd96258d940d 6271 __IO uint32_t TC; /**< Watchdog timer constant register. This 24-bit register determines the time-out value., offset: 0x4 */
Kojto 148:fd96258d940d 6272 __O uint32_t FEED; /**< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC., offset: 0x8 */
Kojto 148:fd96258d940d 6273 __I uint32_t TV; /**< Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer., offset: 0xC */
Kojto 148:fd96258d940d 6274 uint8_t RESERVED_0[4];
Kojto 148:fd96258d940d 6275 __IO uint32_t WARNINT; /**< Watchdog Warning Interrupt compare value., offset: 0x14 */
Kojto 148:fd96258d940d 6276 __IO uint32_t WINDOW; /**< Watchdog Window compare value., offset: 0x18 */
Kojto 148:fd96258d940d 6277 } WWDT_Type;
Kojto 148:fd96258d940d 6278
Kojto 148:fd96258d940d 6279 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 6280 -- WWDT Register Masks
Kojto 148:fd96258d940d 6281 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 6282
Kojto 148:fd96258d940d 6283 /*!
Kojto 148:fd96258d940d 6284 * @addtogroup WWDT_Register_Masks WWDT Register Masks
Kojto 148:fd96258d940d 6285 * @{
Kojto 148:fd96258d940d 6286 */
Kojto 148:fd96258d940d 6287
Kojto 148:fd96258d940d 6288 /*! @name MOD - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
Kojto 148:fd96258d940d 6289 #define WWDT_MOD_WDEN_MASK (0x1U)
Kojto 148:fd96258d940d 6290 #define WWDT_MOD_WDEN_SHIFT (0U)
Kojto 148:fd96258d940d 6291 #define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK)
Kojto 148:fd96258d940d 6292 #define WWDT_MOD_WDRESET_MASK (0x2U)
Kojto 148:fd96258d940d 6293 #define WWDT_MOD_WDRESET_SHIFT (1U)
Kojto 148:fd96258d940d 6294 #define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK)
Kojto 148:fd96258d940d 6295 #define WWDT_MOD_WDTOF_MASK (0x4U)
Kojto 148:fd96258d940d 6296 #define WWDT_MOD_WDTOF_SHIFT (2U)
Kojto 148:fd96258d940d 6297 #define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK)
Kojto 148:fd96258d940d 6298 #define WWDT_MOD_WDINT_MASK (0x8U)
Kojto 148:fd96258d940d 6299 #define WWDT_MOD_WDINT_SHIFT (3U)
Kojto 148:fd96258d940d 6300 #define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK)
Kojto 148:fd96258d940d 6301 #define WWDT_MOD_WDPROTECT_MASK (0x10U)
Kojto 148:fd96258d940d 6302 #define WWDT_MOD_WDPROTECT_SHIFT (4U)
Kojto 148:fd96258d940d 6303 #define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK)
Kojto 148:fd96258d940d 6304 #define WWDT_MOD_LOCK_MASK (0x20U)
Kojto 148:fd96258d940d 6305 #define WWDT_MOD_LOCK_SHIFT (5U)
Kojto 148:fd96258d940d 6306 #define WWDT_MOD_LOCK(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_LOCK_SHIFT)) & WWDT_MOD_LOCK_MASK)
Kojto 148:fd96258d940d 6307
Kojto 148:fd96258d940d 6308 /*! @name TC - Watchdog timer constant register. This 24-bit register determines the time-out value. */
Kojto 148:fd96258d940d 6309 #define WWDT_TC_COUNT_MASK (0xFFFFFFU)
Kojto 148:fd96258d940d 6310 #define WWDT_TC_COUNT_SHIFT (0U)
Kojto 148:fd96258d940d 6311 #define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK)
Kojto 148:fd96258d940d 6312
Kojto 148:fd96258d940d 6313 /*! @name FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. */
Kojto 148:fd96258d940d 6314 #define WWDT_FEED_FEED_MASK (0xFFU)
Kojto 148:fd96258d940d 6315 #define WWDT_FEED_FEED_SHIFT (0U)
Kojto 148:fd96258d940d 6316 #define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK)
Kojto 148:fd96258d940d 6317
Kojto 148:fd96258d940d 6318 /*! @name TV - Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */
Kojto 148:fd96258d940d 6319 #define WWDT_TV_COUNT_MASK (0xFFFFFFU)
Kojto 148:fd96258d940d 6320 #define WWDT_TV_COUNT_SHIFT (0U)
Kojto 148:fd96258d940d 6321 #define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK)
Kojto 148:fd96258d940d 6322
Kojto 148:fd96258d940d 6323 /*! @name WARNINT - Watchdog Warning Interrupt compare value. */
Kojto 148:fd96258d940d 6324 #define WWDT_WARNINT_WARNINT_MASK (0x3FFU)
Kojto 148:fd96258d940d 6325 #define WWDT_WARNINT_WARNINT_SHIFT (0U)
Kojto 148:fd96258d940d 6326 #define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK)
Kojto 148:fd96258d940d 6327
Kojto 148:fd96258d940d 6328 /*! @name WINDOW - Watchdog Window compare value. */
Kojto 148:fd96258d940d 6329 #define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU)
Kojto 148:fd96258d940d 6330 #define WWDT_WINDOW_WINDOW_SHIFT (0U)
Kojto 148:fd96258d940d 6331 #define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK)
Kojto 148:fd96258d940d 6332
Kojto 148:fd96258d940d 6333
Kojto 148:fd96258d940d 6334 /*!
Kojto 148:fd96258d940d 6335 * @}
Kojto 148:fd96258d940d 6336 */ /* end of group WWDT_Register_Masks */
Kojto 148:fd96258d940d 6337
Kojto 148:fd96258d940d 6338
Kojto 148:fd96258d940d 6339 /* WWDT - Peripheral instance base addresses */
Kojto 148:fd96258d940d 6340 /** Peripheral WWDT base address */
Kojto 148:fd96258d940d 6341 #define WWDT_BASE (0x4000C000u)
Kojto 148:fd96258d940d 6342 /** Peripheral WWDT base pointer */
Kojto 148:fd96258d940d 6343 #define WWDT ((WWDT_Type *)WWDT_BASE)
Kojto 148:fd96258d940d 6344 /** Array initializer of WWDT peripheral base addresses */
Kojto 148:fd96258d940d 6345 #define WWDT_BASE_ADDRS { WWDT_BASE }
Kojto 148:fd96258d940d 6346 /** Array initializer of WWDT peripheral base pointers */
Kojto 148:fd96258d940d 6347 #define WWDT_BASE_PTRS { WWDT }
Kojto 148:fd96258d940d 6348 /** Interrupt vectors for the WWDT peripheral type */
Kojto 148:fd96258d940d 6349 #define WWDT_IRQS { WDT_BOD_IRQn }
Kojto 148:fd96258d940d 6350
Kojto 148:fd96258d940d 6351 /*!
Kojto 148:fd96258d940d 6352 * @}
Kojto 148:fd96258d940d 6353 */ /* end of group WWDT_Peripheral_Access_Layer */
Kojto 148:fd96258d940d 6354
Kojto 148:fd96258d940d 6355
Kojto 148:fd96258d940d 6356 /*
Kojto 148:fd96258d940d 6357 ** End of section using anonymous unions
Kojto 148:fd96258d940d 6358 */
Kojto 148:fd96258d940d 6359
Kojto 148:fd96258d940d 6360 #if defined(__ARMCC_VERSION)
Kojto 148:fd96258d940d 6361 #pragma pop
Kojto 148:fd96258d940d 6362 #elif defined(__GNUC__)
Kojto 148:fd96258d940d 6363 /* leave anonymous unions enabled */
Kojto 148:fd96258d940d 6364 #elif defined(__IAR_SYSTEMS_ICC__)
Kojto 148:fd96258d940d 6365 #pragma language=default
Kojto 148:fd96258d940d 6366 #else
Kojto 148:fd96258d940d 6367 #error Not supported compiler type
Kojto 148:fd96258d940d 6368 #endif
Kojto 148:fd96258d940d 6369
Kojto 148:fd96258d940d 6370 /*!
Kojto 148:fd96258d940d 6371 * @}
Kojto 148:fd96258d940d 6372 */ /* end of group Peripheral_access_layer */
Kojto 148:fd96258d940d 6373
Kojto 148:fd96258d940d 6374
Kojto 148:fd96258d940d 6375 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 6376 -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
Kojto 148:fd96258d940d 6377 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 6378
Kojto 148:fd96258d940d 6379 /*!
Kojto 148:fd96258d940d 6380 * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
Kojto 148:fd96258d940d 6381 * @{
Kojto 148:fd96258d940d 6382 */
Kojto 148:fd96258d940d 6383
Kojto 148:fd96258d940d 6384 #if defined(__ARMCC_VERSION)
Kojto 148:fd96258d940d 6385 #if (__ARMCC_VERSION >= 6010050)
Kojto 148:fd96258d940d 6386 #pragma clang system_header
Kojto 148:fd96258d940d 6387 #endif
Kojto 148:fd96258d940d 6388 #elif defined(__IAR_SYSTEMS_ICC__)
Kojto 148:fd96258d940d 6389 #pragma system_include
Kojto 148:fd96258d940d 6390 #endif
Kojto 148:fd96258d940d 6391
Kojto 148:fd96258d940d 6392 /**
Kojto 148:fd96258d940d 6393 * @brief Mask and left-shift a bit field value for use in a register bit range.
Kojto 148:fd96258d940d 6394 * @param field Name of the register bit field.
Kojto 148:fd96258d940d 6395 * @param value Value of the bit field.
Kojto 148:fd96258d940d 6396 * @return Masked and shifted value.
Kojto 148:fd96258d940d 6397 */
Kojto 148:fd96258d940d 6398 #define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK))
Kojto 148:fd96258d940d 6399 /**
Kojto 148:fd96258d940d 6400 * @brief Mask and right-shift a register value to extract a bit field value.
Kojto 148:fd96258d940d 6401 * @param field Name of the register bit field.
Kojto 148:fd96258d940d 6402 * @param value Value of the register.
Kojto 148:fd96258d940d 6403 * @return Masked and shifted bit field value.
Kojto 148:fd96258d940d 6404 */
Kojto 148:fd96258d940d 6405 #define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT))
Kojto 148:fd96258d940d 6406
Kojto 148:fd96258d940d 6407 /*!
Kojto 148:fd96258d940d 6408 * @}
Kojto 148:fd96258d940d 6409 */ /* end of group Bit_Field_Generic_Macros */
Kojto 148:fd96258d940d 6410
Kojto 148:fd96258d940d 6411
Kojto 148:fd96258d940d 6412 /* ----------------------------------------------------------------------------
Kojto 148:fd96258d940d 6413 -- SDK Compatibility
Kojto 148:fd96258d940d 6414 ---------------------------------------------------------------------------- */
Kojto 148:fd96258d940d 6415
Kojto 148:fd96258d940d 6416 /*!
Kojto 148:fd96258d940d 6417 * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
Kojto 148:fd96258d940d 6418 * @{
Kojto 148:fd96258d940d 6419 */
Kojto 148:fd96258d940d 6420
Kojto 148:fd96258d940d 6421 /* No SDK compatibility issues. */
Kojto 148:fd96258d940d 6422
Kojto 148:fd96258d940d 6423 /*!
Kojto 148:fd96258d940d 6424 * @}
Kojto 148:fd96258d940d 6425 */ /* end of group SDK_Compatibility_Symbols */
Kojto 148:fd96258d940d 6426
Kojto 148:fd96258d940d 6427
Kojto 148:fd96258d940d 6428 #endif /* _LPC54114_CM4_H_ */
Kojto 148:fd96258d940d 6429