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Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more
TARGET_MAX32620HSP/pwrseq_regs.h@125:2e9cc70d1897, 2016-08-31 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Aug 31 18:09:46 2016 +0100
- Revision:
- 125:2e9cc70d1897
Release 125 of the mbed library
Changes:
New target - KL27Z_IAR
New target - MAX32620HSP_ARM_STD
New target - MAX32620HSP_GCC_ARM
New target - MAX32620HSP_IAR
New target - NCS36510_ARM_STD
New target - NCS36510_GCC_ARM
New target - NCS36510_IAR
Added support for NSAPI_REUSEADDR to the lwip interface.
STM32F3 family : Add and enable asynchronous serial, plus tests.
STM32L4 family : Add and enable asynchronous serial, plus tests.
Fixing issue where GCC fails to report compile errors when non-verbose.
Add ethernet and IPV4 support for: NUCLEO_F207ZG, NUCLEO_F429ZI, NUCLEO_F767ZI, DISCO_F746NG.
RZ_A1H - Enable SPI1 on pins P6_4 to P6_7.
KL27Z : SPI driver bug fixes and Improvements, ARM linker file update.
STM32F4, STM32F7 families : Add entropy functions, documentation, code improvements, fix build issues.
HEXIWEAR: Update I2C pin mapping, Add support to create KDS projects.
LWIP - fix recv blocking send on accepted sockets.
SingletonPtr bugfixes.
Beetle: Implement sleep API.
uVisor: Update to v0.20.1-alpha, minor documentation update.
STM32F3 : fix RTOS IAR test, RTOS GCC_ARM test.
nrf5x : Introduce uart hardware flow control configuration.
K64F/K22F: Implement HAL lp_timer API.
Ticker: Move ticker initialisation to object creation time.
STM32F4 : remove printf from pwmout
NXP : Fix multiple definition errors in GCC_CR build, fix linker errors.
Add TOOLCHAIN_GCC_CR support.
STM32L1 family : Add and enable asynchronous serial, plus tests.
mbed-client : Fix Bootstrap and Connector functionality.
NUC472 : Fix Ethernet wrong INT status in RX_Action.
RTX_CM_lib.h : fix compiler warning.
NUCLEO : Use GCC small build for 64K flash STM32.
STM32F2 family : Add and enable asynchronous serial, plus tests.
uvisor : Move page heap after uVisor private data, update page allocator.
K64F: Revert to hardcoded stack pointer in RTX .
dns-query : Internal API change , documentation, Added support for multiple results and ipv6.
Add support for implementation-provided DNS servers.
Adopted netconn_gethostbyname in the lwip interface.
Restructured nsapi_dns.h to have clear separation between C/C++ .
Tool fixes.
Tests : New ones added and some updates to existing.
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 125:2e9cc70d1897 | 1 | /******************************************************************************* |
| AnnaBridge | 125:2e9cc70d1897 | 2 | * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. |
| AnnaBridge | 125:2e9cc70d1897 | 3 | * |
| AnnaBridge | 125:2e9cc70d1897 | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| AnnaBridge | 125:2e9cc70d1897 | 5 | * copy of this software and associated documentation files (the "Software"), |
| AnnaBridge | 125:2e9cc70d1897 | 6 | * to deal in the Software without restriction, including without limitation |
| AnnaBridge | 125:2e9cc70d1897 | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| AnnaBridge | 125:2e9cc70d1897 | 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| AnnaBridge | 125:2e9cc70d1897 | 9 | * Software is furnished to do so, subject to the following conditions: |
| AnnaBridge | 125:2e9cc70d1897 | 10 | * |
| AnnaBridge | 125:2e9cc70d1897 | 11 | * The above copyright notice and this permission notice shall be included |
| AnnaBridge | 125:2e9cc70d1897 | 12 | * in all copies or substantial portions of the Software. |
| AnnaBridge | 125:2e9cc70d1897 | 13 | * |
| AnnaBridge | 125:2e9cc70d1897 | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| AnnaBridge | 125:2e9cc70d1897 | 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| AnnaBridge | 125:2e9cc70d1897 | 16 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| AnnaBridge | 125:2e9cc70d1897 | 17 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
| AnnaBridge | 125:2e9cc70d1897 | 18 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| AnnaBridge | 125:2e9cc70d1897 | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| AnnaBridge | 125:2e9cc70d1897 | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| AnnaBridge | 125:2e9cc70d1897 | 21 | * |
| AnnaBridge | 125:2e9cc70d1897 | 22 | * Except as contained in this notice, the name of Maxim Integrated |
| AnnaBridge | 125:2e9cc70d1897 | 23 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
| AnnaBridge | 125:2e9cc70d1897 | 24 | * Products, Inc. Branding Policy. |
| AnnaBridge | 125:2e9cc70d1897 | 25 | * |
| AnnaBridge | 125:2e9cc70d1897 | 26 | * The mere transfer of this software does not imply any licenses |
| AnnaBridge | 125:2e9cc70d1897 | 27 | * of trade secrets, proprietary technology, copyrights, patents, |
| AnnaBridge | 125:2e9cc70d1897 | 28 | * trademarks, maskwork rights, or any other form of intellectual |
| AnnaBridge | 125:2e9cc70d1897 | 29 | * property whatsoever. Maxim Integrated Products, Inc. retains all |
| AnnaBridge | 125:2e9cc70d1897 | 30 | * ownership rights. |
| AnnaBridge | 125:2e9cc70d1897 | 31 | ******************************************************************************* |
| AnnaBridge | 125:2e9cc70d1897 | 32 | */ |
| AnnaBridge | 125:2e9cc70d1897 | 33 | |
| AnnaBridge | 125:2e9cc70d1897 | 34 | #ifndef _MXC_PWRSEQ_REGS_H_ |
| AnnaBridge | 125:2e9cc70d1897 | 35 | #define _MXC_PWRSEQ_REGS_H_ |
| AnnaBridge | 125:2e9cc70d1897 | 36 | |
| AnnaBridge | 125:2e9cc70d1897 | 37 | #ifdef __cplusplus |
| AnnaBridge | 125:2e9cc70d1897 | 38 | extern "C" { |
| AnnaBridge | 125:2e9cc70d1897 | 39 | #endif |
| AnnaBridge | 125:2e9cc70d1897 | 40 | |
| AnnaBridge | 125:2e9cc70d1897 | 41 | #include <stdint.h> |
| AnnaBridge | 125:2e9cc70d1897 | 42 | |
| AnnaBridge | 125:2e9cc70d1897 | 43 | /* |
| AnnaBridge | 125:2e9cc70d1897 | 44 | If types are not defined elsewhere (CMSIS) define them here |
| AnnaBridge | 125:2e9cc70d1897 | 45 | */ |
| AnnaBridge | 125:2e9cc70d1897 | 46 | #ifndef __IO |
| AnnaBridge | 125:2e9cc70d1897 | 47 | #define __IO volatile |
| AnnaBridge | 125:2e9cc70d1897 | 48 | #endif |
| AnnaBridge | 125:2e9cc70d1897 | 49 | #ifndef __I |
| AnnaBridge | 125:2e9cc70d1897 | 50 | #define __I volatile const |
| AnnaBridge | 125:2e9cc70d1897 | 51 | #endif |
| AnnaBridge | 125:2e9cc70d1897 | 52 | #ifndef __O |
| AnnaBridge | 125:2e9cc70d1897 | 53 | #define __O volatile |
| AnnaBridge | 125:2e9cc70d1897 | 54 | #endif |
| AnnaBridge | 125:2e9cc70d1897 | 55 | |
| AnnaBridge | 125:2e9cc70d1897 | 56 | |
| AnnaBridge | 125:2e9cc70d1897 | 57 | /* |
| AnnaBridge | 125:2e9cc70d1897 | 58 | Typedefed structure(s) for module registers (per instance or section) with direct 32-bit |
| AnnaBridge | 125:2e9cc70d1897 | 59 | access to each register in module. |
| AnnaBridge | 125:2e9cc70d1897 | 60 | */ |
| AnnaBridge | 125:2e9cc70d1897 | 61 | |
| AnnaBridge | 125:2e9cc70d1897 | 62 | /* Offset Register Description |
| AnnaBridge | 125:2e9cc70d1897 | 63 | ============= ============================================================================ */ |
| AnnaBridge | 125:2e9cc70d1897 | 64 | typedef struct { |
| AnnaBridge | 125:2e9cc70d1897 | 65 | __IO uint32_t reg0; /* 0x0000 Power Sequencer Control Register 0 */ |
| AnnaBridge | 125:2e9cc70d1897 | 66 | __IO uint32_t reg1; /* 0x0004 Power Sequencer Control Register 1 */ |
| AnnaBridge | 125:2e9cc70d1897 | 67 | __IO uint32_t reg2; /* 0x0008 Power Sequencer Control Register 2 */ |
| AnnaBridge | 125:2e9cc70d1897 | 68 | __IO uint32_t reg3; /* 0x000C Power Sequencer Control Register 3 */ |
| AnnaBridge | 125:2e9cc70d1897 | 69 | __IO uint32_t reg4; /* 0x0010 Power Sequencer Control Register 4 (Internal Test Only) */ |
| AnnaBridge | 125:2e9cc70d1897 | 70 | __IO uint32_t reg5; /* 0x0014 Power Sequencer Control Register 5 (Trim 0) */ |
| AnnaBridge | 125:2e9cc70d1897 | 71 | __IO uint32_t reg6; /* 0x0018 Power Sequencer Control Register 6 (Trim 1) */ |
| AnnaBridge | 125:2e9cc70d1897 | 72 | __IO uint32_t reg7; /* 0x001C Power Sequencer Control Register 7 (Trim 2) */ |
| AnnaBridge | 125:2e9cc70d1897 | 73 | __IO uint32_t flags; /* 0x0020 Power Sequencer Flags */ |
| AnnaBridge | 125:2e9cc70d1897 | 74 | __IO uint32_t msk_flags; /* 0x0024 Power Sequencer Flags Mask Register */ |
| AnnaBridge | 125:2e9cc70d1897 | 75 | __I uint32_t rsv028[2]; /* 0x0028-0x002C */ |
| AnnaBridge | 125:2e9cc70d1897 | 76 | __IO uint32_t retn_ctrl0; /* 0x0030 Retention Control Register 0 */ |
| AnnaBridge | 125:2e9cc70d1897 | 77 | __IO uint32_t retn_ctrl1; /* 0x0034 Retention Control Register 1 */ |
| AnnaBridge | 125:2e9cc70d1897 | 78 | } mxc_pwrseq_regs_t; |
| AnnaBridge | 125:2e9cc70d1897 | 79 | |
| AnnaBridge | 125:2e9cc70d1897 | 80 | |
| AnnaBridge | 125:2e9cc70d1897 | 81 | /* |
| AnnaBridge | 125:2e9cc70d1897 | 82 | Register offsets for module PWRSEQ. |
| AnnaBridge | 125:2e9cc70d1897 | 83 | */ |
| AnnaBridge | 125:2e9cc70d1897 | 84 | |
| AnnaBridge | 125:2e9cc70d1897 | 85 | #define MXC_R_PWRSEQ_OFFS_REG0 ((uint32_t)0x00000000UL) |
| AnnaBridge | 125:2e9cc70d1897 | 86 | #define MXC_R_PWRSEQ_OFFS_REG1 ((uint32_t)0x00000004UL) |
| AnnaBridge | 125:2e9cc70d1897 | 87 | #define MXC_R_PWRSEQ_OFFS_REG2 ((uint32_t)0x00000008UL) |
| AnnaBridge | 125:2e9cc70d1897 | 88 | #define MXC_R_PWRSEQ_OFFS_REG3 ((uint32_t)0x0000000CUL) |
| AnnaBridge | 125:2e9cc70d1897 | 89 | #define MXC_R_PWRSEQ_OFFS_REG4 ((uint32_t)0x00000010UL) |
| AnnaBridge | 125:2e9cc70d1897 | 90 | #define MXC_R_PWRSEQ_OFFS_REG5 ((uint32_t)0x00000014UL) |
| AnnaBridge | 125:2e9cc70d1897 | 91 | #define MXC_R_PWRSEQ_OFFS_REG6 ((uint32_t)0x00000018UL) |
| AnnaBridge | 125:2e9cc70d1897 | 92 | #define MXC_R_PWRSEQ_OFFS_REG7 ((uint32_t)0x0000001CUL) |
| AnnaBridge | 125:2e9cc70d1897 | 93 | #define MXC_R_PWRSEQ_OFFS_FLAGS ((uint32_t)0x00000020UL) |
| AnnaBridge | 125:2e9cc70d1897 | 94 | #define MXC_R_PWRSEQ_OFFS_MSK_FLAGS ((uint32_t)0x00000024UL) |
| AnnaBridge | 125:2e9cc70d1897 | 95 | #define MXC_R_PWRSEQ_OFFS_RETN_CTRL0 ((uint32_t)0x00000030UL) |
| AnnaBridge | 125:2e9cc70d1897 | 96 | #define MXC_R_PWRSEQ_OFFS_RETN_CTRL1 ((uint32_t)0x00000034UL) |
| AnnaBridge | 125:2e9cc70d1897 | 97 | |
| AnnaBridge | 125:2e9cc70d1897 | 98 | |
| AnnaBridge | 125:2e9cc70d1897 | 99 | /* |
| AnnaBridge | 125:2e9cc70d1897 | 100 | Field positions and masks for module PWRSEQ. |
| AnnaBridge | 125:2e9cc70d1897 | 101 | */ |
| AnnaBridge | 125:2e9cc70d1897 | 102 | |
| AnnaBridge | 125:2e9cc70d1897 | 103 | #define MXC_F_PWRSEQ_REG0_PWR_LP1_POS 0 |
| AnnaBridge | 125:2e9cc70d1897 | 104 | #define MXC_F_PWRSEQ_REG0_PWR_LP1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LP1_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 105 | #define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS 1 |
| AnnaBridge | 125:2e9cc70d1897 | 106 | #define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 107 | #define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS 2 |
| AnnaBridge | 125:2e9cc70d1897 | 108 | #define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 109 | #define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_RUN_POS 3 |
| AnnaBridge | 125:2e9cc70d1897 | 110 | #define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FLASHEN_RUN_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 111 | #define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_SLP_POS 4 |
| AnnaBridge | 125:2e9cc70d1897 | 112 | #define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FLASHEN_SLP_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 113 | #define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN_POS 5 |
| AnnaBridge | 125:2e9cc70d1897 | 114 | #define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 115 | #define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP_POS 6 |
| AnnaBridge | 125:2e9cc70d1897 | 116 | #define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 117 | #define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS 7 |
| AnnaBridge | 125:2e9cc70d1897 | 118 | #define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 119 | #define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS 8 |
| AnnaBridge | 125:2e9cc70d1897 | 120 | #define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 121 | #define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS 9 |
| AnnaBridge | 125:2e9cc70d1897 | 122 | #define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 123 | #define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS 10 |
| AnnaBridge | 125:2e9cc70d1897 | 124 | #define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 125 | #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS 11 |
| AnnaBridge | 125:2e9cc70d1897 | 126 | #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 127 | #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS 12 |
| AnnaBridge | 125:2e9cc70d1897 | 128 | #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 129 | #define MXC_F_PWRSEQ_REG0_PWR_SVM12EN_RUN_POS 13 |
| AnnaBridge | 125:2e9cc70d1897 | 130 | #define MXC_F_PWRSEQ_REG0_PWR_SVM12EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM12EN_RUN_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 131 | #define MXC_F_PWRSEQ_REG0_PWR_SVM18EN_RUN_POS 15 |
| AnnaBridge | 125:2e9cc70d1897 | 132 | #define MXC_F_PWRSEQ_REG0_PWR_SVM18EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM18EN_RUN_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 133 | #define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS 17 |
| AnnaBridge | 125:2e9cc70d1897 | 134 | #define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 135 | #define MXC_F_PWRSEQ_REG0_PWR_SVM_VDDB_RUN_POS 19 |
| AnnaBridge | 125:2e9cc70d1897 | 136 | #define MXC_F_PWRSEQ_REG0_PWR_SVM_VDDB_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM_VDDB_RUN_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 137 | #define MXC_F_PWRSEQ_REG0_PWR_SVMTVDD12EN_RUN_POS 21 |
| AnnaBridge | 125:2e9cc70d1897 | 138 | #define MXC_F_PWRSEQ_REG0_PWR_SVMTVDD12EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMTVDD12EN_RUN_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 139 | #define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_RUN_POS 23 |
| AnnaBridge | 125:2e9cc70d1897 | 140 | #define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_RUN_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 141 | #define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_SLP_POS 24 |
| AnnaBridge | 125:2e9cc70d1897 | 142 | #define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_SLP_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 143 | #define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_RUN_POS 25 |
| AnnaBridge | 125:2e9cc70d1897 | 144 | #define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_RUN_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 145 | #define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_SLP_POS 26 |
| AnnaBridge | 125:2e9cc70d1897 | 146 | #define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_SLP_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 147 | #define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_RUN_POS 27 |
| AnnaBridge | 125:2e9cc70d1897 | 148 | #define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_RUN_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 149 | #define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_SLP_POS 28 |
| AnnaBridge | 125:2e9cc70d1897 | 150 | #define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_SLP_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 151 | |
| AnnaBridge | 125:2e9cc70d1897 | 152 | #define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH_POS 0 |
| AnnaBridge | 125:2e9cc70d1897 | 153 | #define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 154 | #define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH_POS 1 |
| AnnaBridge | 125:2e9cc70d1897 | 155 | #define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 156 | #define MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE_POS 2 |
| AnnaBridge | 125:2e9cc70d1897 | 157 | #define MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 158 | #define MXC_F_PWRSEQ_REG1_PWR_DISCHARGE_EN_POS 3 |
| AnnaBridge | 125:2e9cc70d1897 | 159 | #define MXC_F_PWRSEQ_REG1_PWR_DISCHARGE_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_DISCHARGE_EN_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 160 | #define MXC_F_PWRSEQ_REG1_PWR_TVDD12_WELL_POS 4 |
| AnnaBridge | 125:2e9cc70d1897 | 161 | #define MXC_F_PWRSEQ_REG1_PWR_TVDD12_WELL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_TVDD12_WELL_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 162 | |
| AnnaBridge | 125:2e9cc70d1897 | 163 | #define MXC_F_PWRSEQ_REG2_PWR_VDD12_HYST_POS 0 |
| AnnaBridge | 125:2e9cc70d1897 | 164 | #define MXC_F_PWRSEQ_REG2_PWR_VDD12_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDD12_HYST_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 165 | #define MXC_F_PWRSEQ_REG2_PWR_VDD18_HYST_POS 2 |
| AnnaBridge | 125:2e9cc70d1897 | 166 | #define MXC_F_PWRSEQ_REG2_PWR_VDD18_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDD18_HYST_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 167 | #define MXC_F_PWRSEQ_REG2_PWR_VRTC_HYST_POS 4 |
| AnnaBridge | 125:2e9cc70d1897 | 168 | #define MXC_F_PWRSEQ_REG2_PWR_VRTC_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VRTC_HYST_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 169 | #define MXC_F_PWRSEQ_REG2_PWR_VDDB_HYST_POS 6 |
| AnnaBridge | 125:2e9cc70d1897 | 170 | #define MXC_F_PWRSEQ_REG2_PWR_VDDB_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDDB_HYST_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 171 | #define MXC_F_PWRSEQ_REG2_PWR_TVDD12_HYST_POS 8 |
| AnnaBridge | 125:2e9cc70d1897 | 172 | #define MXC_F_PWRSEQ_REG2_PWR_TVDD12_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_TVDD12_HYST_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 173 | |
| AnnaBridge | 125:2e9cc70d1897 | 174 | #define MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS 0 |
| AnnaBridge | 125:2e9cc70d1897 | 175 | #define MXC_F_PWRSEQ_REG3_PWR_ROSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 176 | #define MXC_F_PWRSEQ_REG3_PWR_FLTRROSEL_POS 3 |
| AnnaBridge | 125:2e9cc70d1897 | 177 | #define MXC_F_PWRSEQ_REG3_PWR_FLTRROSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_FLTRROSEL_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 178 | #define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS 6 |
| AnnaBridge | 125:2e9cc70d1897 | 179 | #define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 180 | #define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS 8 |
| AnnaBridge | 125:2e9cc70d1897 | 181 | #define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 182 | #define MXC_F_PWRSEQ_REG3_PWR_FAILSEL_POS 10 |
| AnnaBridge | 125:2e9cc70d1897 | 183 | #define MXC_F_PWRSEQ_REG3_PWR_FAILSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_FAILSEL_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 184 | |
| AnnaBridge | 125:2e9cc70d1897 | 185 | #define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS 0 |
| AnnaBridge | 125:2e9cc70d1897 | 186 | #define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 187 | #define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS 1 |
| AnnaBridge | 125:2e9cc70d1897 | 188 | #define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 189 | #define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS 3 |
| AnnaBridge | 125:2e9cc70d1897 | 190 | #define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 191 | #define MXC_F_PWRSEQ_REG4_PWR_RO_TSTCLK_EN_POS 4 |
| AnnaBridge | 125:2e9cc70d1897 | 192 | #define MXC_F_PWRSEQ_REG4_PWR_RO_TSTCLK_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_RO_TSTCLK_EN_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 193 | #define MXC_F_PWRSEQ_REG4_PWR_NR_CLK_GATE_EN_POS 5 |
| AnnaBridge | 125:2e9cc70d1897 | 194 | #define MXC_F_PWRSEQ_REG4_PWR_NR_CLK_GATE_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_NR_CLK_GATE_EN_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 195 | #define MXC_F_PWRSEQ_REG4_PWR_EXT_CLK_IN_EN_POS 6 |
| AnnaBridge | 125:2e9cc70d1897 | 196 | #define MXC_F_PWRSEQ_REG4_PWR_EXT_CLK_IN_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_EXT_CLK_IN_EN_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 197 | #define MXC_F_PWRSEQ_REG4_PWR_PSEQ_32K_EN_POS 7 |
| AnnaBridge | 125:2e9cc70d1897 | 198 | #define MXC_F_PWRSEQ_REG4_PWR_PSEQ_32K_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_PSEQ_32K_EN_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 199 | |
| AnnaBridge | 125:2e9cc70d1897 | 200 | #define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS 0 |
| AnnaBridge | 125:2e9cc70d1897 | 201 | #define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG ((uint32_t)(0x000001FFUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 202 | #define MXC_F_PWRSEQ_REG5_PWR_TRIM_BIAS_POS 9 |
| AnnaBridge | 125:2e9cc70d1897 | 203 | #define MXC_F_PWRSEQ_REG5_PWR_TRIM_BIAS ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_BIAS_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 204 | #define MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_POS 15 |
| AnnaBridge | 125:2e9cc70d1897 | 205 | #define MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 206 | #define MXC_F_PWRSEQ_REG5_PWR_RTC_TRIM_POS 21 |
| AnnaBridge | 125:2e9cc70d1897 | 207 | #define MXC_F_PWRSEQ_REG5_PWR_RTC_TRIM ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG5_PWR_RTC_TRIM_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 208 | |
| AnnaBridge | 125:2e9cc70d1897 | 209 | #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS 0 |
| AnnaBridge | 125:2e9cc70d1897 | 210 | #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 211 | #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS 3 |
| AnnaBridge | 125:2e9cc70d1897 | 212 | #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 213 | #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS 7 |
| AnnaBridge | 125:2e9cc70d1897 | 214 | #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 215 | #define MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS 11 |
| AnnaBridge | 125:2e9cc70d1897 | 216 | #define MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF ((uint32_t)(0x000001FFUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 217 | #define MXC_F_PWRSEQ_REG6_PWR_TRIM_CRYPTO_OSC_POS 20 |
| AnnaBridge | 125:2e9cc70d1897 | 218 | #define MXC_F_PWRSEQ_REG6_PWR_TRIM_CRYPTO_OSC ((uint32_t)(0x000001FFUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_CRYPTO_OSC_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 219 | |
| AnnaBridge | 125:2e9cc70d1897 | 220 | #define MXC_F_PWRSEQ_REG7_PWR_FLASH_PD_LOOKAHEAD_POS 0 |
| AnnaBridge | 125:2e9cc70d1897 | 221 | #define MXC_F_PWRSEQ_REG7_PWR_FLASH_PD_LOOKAHEAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG7_PWR_FLASH_PD_LOOKAHEAD_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 222 | |
| AnnaBridge | 125:2e9cc70d1897 | 223 | #define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS 0 |
| AnnaBridge | 125:2e9cc70d1897 | 224 | #define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 225 | #define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS 1 |
| AnnaBridge | 125:2e9cc70d1897 | 226 | #define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 227 | #define MXC_F_PWRSEQ_FLAGS_PWR_POWER_FAIL_POS 2 |
| AnnaBridge | 125:2e9cc70d1897 | 228 | #define MXC_F_PWRSEQ_FLAGS_PWR_POWER_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_POWER_FAIL_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 229 | #define MXC_F_PWRSEQ_FLAGS_PWR_BOOT_FAIL_POS 3 |
| AnnaBridge | 125:2e9cc70d1897 | 230 | #define MXC_F_PWRSEQ_FLAGS_PWR_BOOT_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_BOOT_FAIL_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 231 | #define MXC_F_PWRSEQ_FLAGS_PWR_FLASH_DISCHARGE_POS 4 |
| AnnaBridge | 125:2e9cc70d1897 | 232 | #define MXC_F_PWRSEQ_FLAGS_PWR_FLASH_DISCHARGE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_FLASH_DISCHARGE_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 233 | #define MXC_F_PWRSEQ_FLAGS_PWR_IOWAKEUP_POS 5 |
| AnnaBridge | 125:2e9cc70d1897 | 234 | #define MXC_F_PWRSEQ_FLAGS_PWR_IOWAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_IOWAKEUP_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 235 | #define MXC_F_PWRSEQ_FLAGS_PWR_VDD12_RST_BAD_POS 6 |
| AnnaBridge | 125:2e9cc70d1897 | 236 | #define MXC_F_PWRSEQ_FLAGS_PWR_VDD12_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD12_RST_BAD_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 237 | #define MXC_F_PWRSEQ_FLAGS_PWR_VDD18_RST_BAD_POS 7 |
| AnnaBridge | 125:2e9cc70d1897 | 238 | #define MXC_F_PWRSEQ_FLAGS_PWR_VDD18_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD18_RST_BAD_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 239 | #define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_RST_BAD_POS 8 |
| AnnaBridge | 125:2e9cc70d1897 | 240 | #define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VRTC_RST_BAD_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 241 | #define MXC_F_PWRSEQ_FLAGS_PWR_VDDB_RST_BAD_POS 9 |
| AnnaBridge | 125:2e9cc70d1897 | 242 | #define MXC_F_PWRSEQ_FLAGS_PWR_VDDB_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDDB_RST_BAD_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 243 | #define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_RST_BAD_POS 10 |
| AnnaBridge | 125:2e9cc70d1897 | 244 | #define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_RST_BAD_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 245 | #define MXC_F_PWRSEQ_FLAGS_PWR_POR18Z_FAIL_LATCH_POS 11 |
| AnnaBridge | 125:2e9cc70d1897 | 246 | #define MXC_F_PWRSEQ_FLAGS_PWR_POR18Z_FAIL_LATCH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_POR18Z_FAIL_LATCH_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 247 | #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS 12 |
| AnnaBridge | 125:2e9cc70d1897 | 248 | #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 249 | #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS 13 |
| AnnaBridge | 125:2e9cc70d1897 | 250 | #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 251 | #define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS 14 |
| AnnaBridge | 125:2e9cc70d1897 | 252 | #define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 253 | #define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS 15 |
| AnnaBridge | 125:2e9cc70d1897 | 254 | #define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 255 | #define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS 16 |
| AnnaBridge | 125:2e9cc70d1897 | 256 | #define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 257 | #define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS 17 |
| AnnaBridge | 125:2e9cc70d1897 | 258 | #define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 259 | #define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_BAD_POS 18 |
| AnnaBridge | 125:2e9cc70d1897 | 260 | #define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_BAD_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 261 | |
| AnnaBridge | 125:2e9cc70d1897 | 262 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS 1 |
| AnnaBridge | 125:2e9cc70d1897 | 263 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 264 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POWER_FAIL_POS 2 |
| AnnaBridge | 125:2e9cc70d1897 | 265 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POWER_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_POWER_FAIL_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 266 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BOOT_FAIL_POS 3 |
| AnnaBridge | 125:2e9cc70d1897 | 267 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BOOT_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_BOOT_FAIL_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 268 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_FLASH_DISCHARGE_POS 4 |
| AnnaBridge | 125:2e9cc70d1897 | 269 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_FLASH_DISCHARGE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_FLASH_DISCHARGE_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 270 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP_POS 5 |
| AnnaBridge | 125:2e9cc70d1897 | 271 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 272 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD12_RST_BAD_POS 6 |
| AnnaBridge | 125:2e9cc70d1897 | 273 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD12_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD12_RST_BAD_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 274 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD18_RST_BAD_POS 7 |
| AnnaBridge | 125:2e9cc70d1897 | 275 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD18_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD18_RST_BAD_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 276 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_RST_BAD_POS 8 |
| AnnaBridge | 125:2e9cc70d1897 | 277 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_RST_BAD_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 278 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDB_RST_BAD_POS 9 |
| AnnaBridge | 125:2e9cc70d1897 | 279 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDB_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDB_RST_BAD_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 280 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_RST_BAD_POS 10 |
| AnnaBridge | 125:2e9cc70d1897 | 281 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_RST_BAD_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 282 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR18Z_FAIL_LATCH_POS 11 |
| AnnaBridge | 125:2e9cc70d1897 | 283 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR18Z_FAIL_LATCH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR18Z_FAIL_LATCH_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 284 | #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS 12 |
| AnnaBridge | 125:2e9cc70d1897 | 285 | #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 286 | #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS 13 |
| AnnaBridge | 125:2e9cc70d1897 | 287 | #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 288 | #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS 14 |
| AnnaBridge | 125:2e9cc70d1897 | 289 | #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 290 | #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS 15 |
| AnnaBridge | 125:2e9cc70d1897 | 291 | #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 292 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS 16 |
| AnnaBridge | 125:2e9cc70d1897 | 293 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 294 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS 17 |
| AnnaBridge | 125:2e9cc70d1897 | 295 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 296 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_BAD_POS 18 |
| AnnaBridge | 125:2e9cc70d1897 | 297 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_BAD_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 298 | |
| AnnaBridge | 125:2e9cc70d1897 | 299 | #define MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN_POS 0 |
| AnnaBridge | 125:2e9cc70d1897 | 300 | #define MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 301 | #define MXC_F_PWRSEQ_RETN_CTRL0_RC_REL_CCG_EARLY_POS 1 |
| AnnaBridge | 125:2e9cc70d1897 | 302 | #define MXC_F_PWRSEQ_RETN_CTRL0_RC_REL_CCG_EARLY ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RC_REL_CCG_EARLY_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 303 | #define MXC_F_PWRSEQ_RETN_CTRL0_RC_USE_FLC_TWK_POS 2 |
| AnnaBridge | 125:2e9cc70d1897 | 304 | #define MXC_F_PWRSEQ_RETN_CTRL0_RC_USE_FLC_TWK ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RC_USE_FLC_TWK_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 305 | #define MXC_F_PWRSEQ_RETN_CTRL0_RC_POLL_FLASH_POS 3 |
| AnnaBridge | 125:2e9cc70d1897 | 306 | #define MXC_F_PWRSEQ_RETN_CTRL0_RC_POLL_FLASH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RC_POLL_FLASH_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 307 | #define MXC_F_PWRSEQ_RETN_CTRL0_RESTORE_OVERRIDE_POS 4 |
| AnnaBridge | 125:2e9cc70d1897 | 308 | #define MXC_F_PWRSEQ_RETN_CTRL0_RESTORE_OVERRIDE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RESTORE_OVERRIDE_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 309 | |
| AnnaBridge | 125:2e9cc70d1897 | 310 | #define MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK_POS 0 |
| AnnaBridge | 125:2e9cc70d1897 | 311 | #define MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 312 | #define MXC_F_PWRSEQ_RETN_CTRL1_SRAM_FMS_POS 4 |
| AnnaBridge | 125:2e9cc70d1897 | 313 | #define MXC_F_PWRSEQ_RETN_CTRL1_SRAM_FMS ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_RETN_CTRL1_SRAM_FMS_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 314 | |
| AnnaBridge | 125:2e9cc70d1897 | 315 | |
| AnnaBridge | 125:2e9cc70d1897 | 316 | |
| AnnaBridge | 125:2e9cc70d1897 | 317 | #ifdef __cplusplus |
| AnnaBridge | 125:2e9cc70d1897 | 318 | } |
| AnnaBridge | 125:2e9cc70d1897 | 319 | #endif |
| AnnaBridge | 125:2e9cc70d1897 | 320 | |
| AnnaBridge | 125:2e9cc70d1897 | 321 | #endif /* _MXC_PWRSEQ_REGS_H_ */ |
| AnnaBridge | 125:2e9cc70d1897 | 322 |
