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Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

TARGET_SAMR21G18A/ins_port.h@114:252557024ec3, 2016-02-16 (annotated)

Committer:
Kojto
Date:
Tue Feb 16 14:28:01 2016 +0000
Revision:
114:252557024ec3
Parent:
111:4336505e4b1c 
Release 114 of the mbed library



Changes:

- Atmel SAM - warnings fixes

- B96B F446VE - hw control flow addition

- Remove of GCC CW which was not active

- Remove GCC CS, not released anymore - deprecated

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 111:4336505e4b1c 1 /**
Kojto 111:4336505e4b1c 2 * \file
Kojto 111:4336505e4b1c 3 *
Kojto 111:4336505e4b1c 4 * \brief Instance description for PORT
Kojto 111:4336505e4b1c 5 *
Kojto 111:4336505e4b1c 6 * Copyright (c) 2015 Atmel Corporation. All rights reserved.
Kojto 111:4336505e4b1c 7 *
Kojto 111:4336505e4b1c 8 * \asf_license_start
Kojto 111:4336505e4b1c 9 *
Kojto 111:4336505e4b1c 10 * \page License
Kojto 111:4336505e4b1c 11 *
Kojto 111:4336505e4b1c 12 * Redistribution and use in source and binary forms, with or without
Kojto 111:4336505e4b1c 13 * modification, are permitted provided that the following conditions are met:
Kojto 111:4336505e4b1c 14 *
Kojto 111:4336505e4b1c 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 111:4336505e4b1c 16 * this list of conditions and the following disclaimer.
Kojto 111:4336505e4b1c 17 *
Kojto 111:4336505e4b1c 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 111:4336505e4b1c 19 * this list of conditions and the following disclaimer in the documentation
Kojto 111:4336505e4b1c 20 * and/or other materials provided with the distribution.
Kojto 111:4336505e4b1c 21 *
Kojto 111:4336505e4b1c 22 * 3. The name of Atmel may not be used to endorse or promote products derived
Kojto 111:4336505e4b1c 23 * from this software without specific prior written permission.
Kojto 111:4336505e4b1c 24 *
Kojto 111:4336505e4b1c 25 * 4. This software may only be redistributed and used in connection with an
Kojto 111:4336505e4b1c 26 * Atmel microcontroller product.
Kojto 111:4336505e4b1c 27 *
Kojto 111:4336505e4b1c 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
Kojto 111:4336505e4b1c 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
Kojto 111:4336505e4b1c 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
Kojto 111:4336505e4b1c 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
Kojto 111:4336505e4b1c 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 111:4336505e4b1c 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
Kojto 111:4336505e4b1c 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
Kojto 111:4336505e4b1c 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
Kojto 111:4336505e4b1c 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
Kojto 111:4336505e4b1c 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 111:4336505e4b1c 38 * POSSIBILITY OF SUCH DAMAGE.
Kojto 111:4336505e4b1c 39 *
Kojto 111:4336505e4b1c 40 * \asf_license_stop
Kojto 111:4336505e4b1c 41 *
Kojto 111:4336505e4b1c 42 */
Kojto 111:4336505e4b1c 43
Kojto 111:4336505e4b1c 44 #ifndef _SAMR21_PORT_INSTANCE_
Kojto 111:4336505e4b1c 45 #define _SAMR21_PORT_INSTANCE_
Kojto 111:4336505e4b1c 46
Kojto 111:4336505e4b1c 47 /* ========== Register definition for PORT peripheral ========== */
Kojto 111:4336505e4b1c 48 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 49 #define REG_PORT_DIR0 (0x41004400U) /**< \brief (PORT) Data Direction 0 */
Kojto 111:4336505e4b1c 50 #define REG_PORT_DIRCLR0 (0x41004404U) /**< \brief (PORT) Data Direction Clear 0 */
Kojto 111:4336505e4b1c 51 #define REG_PORT_DIRSET0 (0x41004408U) /**< \brief (PORT) Data Direction Set 0 */
Kojto 111:4336505e4b1c 52 #define REG_PORT_DIRTGL0 (0x4100440CU) /**< \brief (PORT) Data Direction Toggle 0 */
Kojto 111:4336505e4b1c 53 #define REG_PORT_OUT0 (0x41004410U) /**< \brief (PORT) Data Output Value 0 */
Kojto 111:4336505e4b1c 54 #define REG_PORT_OUTCLR0 (0x41004414U) /**< \brief (PORT) Data Output Value Clear 0 */
Kojto 111:4336505e4b1c 55 #define REG_PORT_OUTSET0 (0x41004418U) /**< \brief (PORT) Data Output Value Set 0 */
Kojto 111:4336505e4b1c 56 #define REG_PORT_OUTTGL0 (0x4100441CU) /**< \brief (PORT) Data Output Value Toggle 0 */
Kojto 111:4336505e4b1c 57 #define REG_PORT_IN0 (0x41004420U) /**< \brief (PORT) Data Input Value 0 */
Kojto 111:4336505e4b1c 58 #define REG_PORT_CTRL0 (0x41004424U) /**< \brief (PORT) Control 0 */
Kojto 111:4336505e4b1c 59 #define REG_PORT_WRCONFIG0 (0x41004428U) /**< \brief (PORT) Write Configuration 0 */
Kojto 111:4336505e4b1c 60 #define REG_PORT_PMUX0 (0x41004430U) /**< \brief (PORT) Peripheral Multiplexing 0 */
Kojto 111:4336505e4b1c 61 #define REG_PORT_PINCFG0 (0x41004440U) /**< \brief (PORT) Pin Configuration 0 */
Kojto 111:4336505e4b1c 62 #define REG_PORT_DIR1 (0x41004480U) /**< \brief (PORT) Data Direction 1 */
Kojto 111:4336505e4b1c 63 #define REG_PORT_DIRCLR1 (0x41004484U) /**< \brief (PORT) Data Direction Clear 1 */
Kojto 111:4336505e4b1c 64 #define REG_PORT_DIRSET1 (0x41004488U) /**< \brief (PORT) Data Direction Set 1 */
Kojto 111:4336505e4b1c 65 #define REG_PORT_DIRTGL1 (0x4100448CU) /**< \brief (PORT) Data Direction Toggle 1 */
Kojto 111:4336505e4b1c 66 #define REG_PORT_OUT1 (0x41004490U) /**< \brief (PORT) Data Output Value 1 */
Kojto 111:4336505e4b1c 67 #define REG_PORT_OUTCLR1 (0x41004494U) /**< \brief (PORT) Data Output Value Clear 1 */
Kojto 111:4336505e4b1c 68 #define REG_PORT_OUTSET1 (0x41004498U) /**< \brief (PORT) Data Output Value Set 1 */
Kojto 111:4336505e4b1c 69 #define REG_PORT_OUTTGL1 (0x4100449CU) /**< \brief (PORT) Data Output Value Toggle 1 */
Kojto 111:4336505e4b1c 70 #define REG_PORT_IN1 (0x410044A0U) /**< \brief (PORT) Data Input Value 1 */
Kojto 111:4336505e4b1c 71 #define REG_PORT_CTRL1 (0x410044A4U) /**< \brief (PORT) Control 1 */
Kojto 111:4336505e4b1c 72 #define REG_PORT_WRCONFIG1 (0x410044A8U) /**< \brief (PORT) Write Configuration 1 */
Kojto 111:4336505e4b1c 73 #define REG_PORT_PMUX1 (0x410044B0U) /**< \brief (PORT) Peripheral Multiplexing 1 */
Kojto 111:4336505e4b1c 74 #define REG_PORT_PINCFG1 (0x410044C0U) /**< \brief (PORT) Pin Configuration 1 */
Kojto 111:4336505e4b1c 75 #define REG_PORT_DIR2 (0x41004500U) /**< \brief (PORT) Data Direction 2 */
Kojto 111:4336505e4b1c 76 #define REG_PORT_DIRCLR2 (0x41004504U) /**< \brief (PORT) Data Direction Clear 2 */
Kojto 111:4336505e4b1c 77 #define REG_PORT_DIRSET2 (0x41004508U) /**< \brief (PORT) Data Direction Set 2 */
Kojto 111:4336505e4b1c 78 #define REG_PORT_DIRTGL2 (0x4100450CU) /**< \brief (PORT) Data Direction Toggle 2 */
Kojto 111:4336505e4b1c 79 #define REG_PORT_OUT2 (0x41004510U) /**< \brief (PORT) Data Output Value 2 */
Kojto 111:4336505e4b1c 80 #define REG_PORT_OUTCLR2 (0x41004514U) /**< \brief (PORT) Data Output Value Clear 2 */
Kojto 111:4336505e4b1c 81 #define REG_PORT_OUTSET2 (0x41004518U) /**< \brief (PORT) Data Output Value Set 2 */
Kojto 111:4336505e4b1c 82 #define REG_PORT_OUTTGL2 (0x4100451CU) /**< \brief (PORT) Data Output Value Toggle 2 */
Kojto 111:4336505e4b1c 83 #define REG_PORT_IN2 (0x41004520U) /**< \brief (PORT) Data Input Value 2 */
Kojto 111:4336505e4b1c 84 #define REG_PORT_CTRL2 (0x41004524U) /**< \brief (PORT) Control 2 */
Kojto 111:4336505e4b1c 85 #define REG_PORT_WRCONFIG2 (0x41004528U) /**< \brief (PORT) Write Configuration 2 */
Kojto 111:4336505e4b1c 86 #define REG_PORT_PMUX2 (0x41004530U) /**< \brief (PORT) Peripheral Multiplexing 2 */
Kojto 111:4336505e4b1c 87 #define REG_PORT_PINCFG2 (0x41004540U) /**< \brief (PORT) Pin Configuration 2 */
Kojto 111:4336505e4b1c 88 #else
Kojto 111:4336505e4b1c 89 #define REG_PORT_DIR0 (*(RwReg *)0x41004400U) /**< \brief (PORT) Data Direction 0 */
Kojto 111:4336505e4b1c 90 #define REG_PORT_DIRCLR0 (*(RwReg *)0x41004404U) /**< \brief (PORT) Data Direction Clear 0 */
Kojto 111:4336505e4b1c 91 #define REG_PORT_DIRSET0 (*(RwReg *)0x41004408U) /**< \brief (PORT) Data Direction Set 0 */
Kojto 111:4336505e4b1c 92 #define REG_PORT_DIRTGL0 (*(RwReg *)0x4100440CU) /**< \brief (PORT) Data Direction Toggle 0 */
Kojto 111:4336505e4b1c 93 #define REG_PORT_OUT0 (*(RwReg *)0x41004410U) /**< \brief (PORT) Data Output Value 0 */
Kojto 111:4336505e4b1c 94 #define REG_PORT_OUTCLR0 (*(RwReg *)0x41004414U) /**< \brief (PORT) Data Output Value Clear 0 */
Kojto 111:4336505e4b1c 95 #define REG_PORT_OUTSET0 (*(RwReg *)0x41004418U) /**< \brief (PORT) Data Output Value Set 0 */
Kojto 111:4336505e4b1c 96 #define REG_PORT_OUTTGL0 (*(RwReg *)0x4100441CU) /**< \brief (PORT) Data Output Value Toggle 0 */
Kojto 111:4336505e4b1c 97 #define REG_PORT_IN0 (*(RoReg *)0x41004420U) /**< \brief (PORT) Data Input Value 0 */
Kojto 111:4336505e4b1c 98 #define REG_PORT_CTRL0 (*(RwReg *)0x41004424U) /**< \brief (PORT) Control 0 */
Kojto 111:4336505e4b1c 99 #define REG_PORT_WRCONFIG0 (*(WoReg *)0x41004428U) /**< \brief (PORT) Write Configuration 0 */
Kojto 111:4336505e4b1c 100 #define REG_PORT_PMUX0 (*(RwReg *)0x41004430U) /**< \brief (PORT) Peripheral Multiplexing 0 */
Kojto 111:4336505e4b1c 101 #define REG_PORT_PINCFG0 (*(RwReg *)0x41004440U) /**< \brief (PORT) Pin Configuration 0 */
Kojto 111:4336505e4b1c 102 #define REG_PORT_DIR1 (*(RwReg *)0x41004480U) /**< \brief (PORT) Data Direction 1 */
Kojto 111:4336505e4b1c 103 #define REG_PORT_DIRCLR1 (*(RwReg *)0x41004484U) /**< \brief (PORT) Data Direction Clear 1 */
Kojto 111:4336505e4b1c 104 #define REG_PORT_DIRSET1 (*(RwReg *)0x41004488U) /**< \brief (PORT) Data Direction Set 1 */
Kojto 111:4336505e4b1c 105 #define REG_PORT_DIRTGL1 (*(RwReg *)0x4100448CU) /**< \brief (PORT) Data Direction Toggle 1 */
Kojto 111:4336505e4b1c 106 #define REG_PORT_OUT1 (*(RwReg *)0x41004490U) /**< \brief (PORT) Data Output Value 1 */
Kojto 111:4336505e4b1c 107 #define REG_PORT_OUTCLR1 (*(RwReg *)0x41004494U) /**< \brief (PORT) Data Output Value Clear 1 */
Kojto 111:4336505e4b1c 108 #define REG_PORT_OUTSET1 (*(RwReg *)0x41004498U) /**< \brief (PORT) Data Output Value Set 1 */
Kojto 111:4336505e4b1c 109 #define REG_PORT_OUTTGL1 (*(RwReg *)0x4100449CU) /**< \brief (PORT) Data Output Value Toggle 1 */
Kojto 111:4336505e4b1c 110 #define REG_PORT_IN1 (*(RoReg *)0x410044A0U) /**< \brief (PORT) Data Input Value 1 */
Kojto 111:4336505e4b1c 111 #define REG_PORT_CTRL1 (*(RwReg *)0x410044A4U) /**< \brief (PORT) Control 1 */
Kojto 111:4336505e4b1c 112 #define REG_PORT_WRCONFIG1 (*(WoReg *)0x410044A8U) /**< \brief (PORT) Write Configuration 1 */
Kojto 111:4336505e4b1c 113 #define REG_PORT_PMUX1 (*(RwReg *)0x410044B0U) /**< \brief (PORT) Peripheral Multiplexing 1 */
Kojto 111:4336505e4b1c 114 #define REG_PORT_PINCFG1 (*(RwReg *)0x410044C0U) /**< \brief (PORT) Pin Configuration 1 */
Kojto 111:4336505e4b1c 115 #define REG_PORT_DIR2 (*(RwReg *)0x41004500U) /**< \brief (PORT) Data Direction 2 */
Kojto 111:4336505e4b1c 116 #define REG_PORT_DIRCLR2 (*(RwReg *)0x41004504U) /**< \brief (PORT) Data Direction Clear 2 */
Kojto 111:4336505e4b1c 117 #define REG_PORT_DIRSET2 (*(RwReg *)0x41004508U) /**< \brief (PORT) Data Direction Set 2 */
Kojto 111:4336505e4b1c 118 #define REG_PORT_DIRTGL2 (*(RwReg *)0x4100450CU) /**< \brief (PORT) Data Direction Toggle 2 */
Kojto 111:4336505e4b1c 119 #define REG_PORT_OUT2 (*(RwReg *)0x41004510U) /**< \brief (PORT) Data Output Value 2 */
Kojto 111:4336505e4b1c 120 #define REG_PORT_OUTCLR2 (*(RwReg *)0x41004514U) /**< \brief (PORT) Data Output Value Clear 2 */
Kojto 111:4336505e4b1c 121 #define REG_PORT_OUTSET2 (*(RwReg *)0x41004518U) /**< \brief (PORT) Data Output Value Set 2 */
Kojto 111:4336505e4b1c 122 #define REG_PORT_OUTTGL2 (*(RwReg *)0x4100451CU) /**< \brief (PORT) Data Output Value Toggle 2 */
Kojto 111:4336505e4b1c 123 #define REG_PORT_IN2 (*(RoReg *)0x41004520U) /**< \brief (PORT) Data Input Value 2 */
Kojto 111:4336505e4b1c 124 #define REG_PORT_CTRL2 (*(RwReg *)0x41004524U) /**< \brief (PORT) Control 2 */
Kojto 111:4336505e4b1c 125 #define REG_PORT_WRCONFIG2 (*(WoReg *)0x41004528U) /**< \brief (PORT) Write Configuration 2 */
Kojto 111:4336505e4b1c 126 #define REG_PORT_PMUX2 (*(RwReg *)0x41004530U) /**< \brief (PORT) Peripheral Multiplexing 2 */
Kojto 111:4336505e4b1c 127 #define REG_PORT_PINCFG2 (*(RwReg *)0x41004540U) /**< \brief (PORT) Pin Configuration 2 */
Kojto 111:4336505e4b1c 128 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 129
Kojto 111:4336505e4b1c 130 /* ========== Instance parameters for PORT peripheral ========== */
Kojto 111:4336505e4b1c 131 #define PORT_BITS 84 // Number of PORT pins
Kojto 111:4336505e4b1c 132 #define PORT_DIR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for DIR of all pins
Kojto 111:4336505e4b1c 133 #define PORT_DIR_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for DIR of all pins
Kojto 111:4336505e4b1c 134 #define PORT_DRVSTR 1 // DRVSTR supported
Kojto 111:4336505e4b1c 135 #define PORT_DRVSTR_DEFAULT_VAL { 0xD8FFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Default value for DRVSTR of all pins
Kojto 111:4336505e4b1c 136 #define PORT_DRVSTR_IMPLEMENTED { 0xD8FFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for DRVSTR of all pins
Kojto 111:4336505e4b1c 137 #define PORT_EVENT_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 }
Kojto 111:4336505e4b1c 138 #define PORT_INEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for INEN of all pins
Kojto 111:4336505e4b1c 139 #define PORT_INEN_IMPLEMENTED { 0xD8FFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for INEN of all pins
Kojto 111:4336505e4b1c 140 #define PORT_ODRAIN 0 // ODRAIN supported
Kojto 111:4336505e4b1c 141 #define PORT_ODRAIN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for ODRAIN of all pins
Kojto 111:4336505e4b1c 142 #define PORT_ODRAIN_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 } // Implementation mask for ODRAIN of all pins
Kojto 111:4336505e4b1c 143 #define PORT_OUT_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for OUT of all pins
Kojto 111:4336505e4b1c 144 #define PORT_OUT_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for OUT of all pins
Kojto 111:4336505e4b1c 145 #define PORT_PIN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for all PORT pins
Kojto 111:4336505e4b1c 146 #define PORT_PMUXBIT0_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for PMUX[0] of all pins
Kojto 111:4336505e4b1c 147 #define PORT_PMUXBIT0_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000D0000 } // Implementation mask for PMUX[0] of all pins
Kojto 111:4336505e4b1c 148 #define PORT_PMUXBIT1_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000 } // Default value for PMUX[1] of all pins
Kojto 111:4336505e4b1c 149 #define PORT_PMUXBIT1_IMPLEMENTED { 0xDBFFFFF3, 0xC0C3FF0F, 0x00000000 } // Implementation mask for PMUX[1] of all pins
Kojto 111:4336505e4b1c 150 #define PORT_PMUXBIT2_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000 } // Default value for PMUX[2] of all pins
Kojto 111:4336505e4b1c 151 #define PORT_PMUXBIT2_IMPLEMENTED { 0xDBFFFFF3, 0xC0C3FF0F, 0x000D0000 } // Implementation mask for PMUX[2] of all pins
Kojto 111:4336505e4b1c 152 #define PORT_PMUXBIT3_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for PMUX[3] of all pins
Kojto 111:4336505e4b1c 153 #define PORT_PMUXBIT3_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 } // Implementation mask for PMUX[3] of all pins
Kojto 111:4336505e4b1c 154 #define PORT_PMUXEN_DEFAULT_VAL { 0x64000000, 0x3F3C0000, 0x00000000 } // Default value for PMUXEN of all pins
Kojto 111:4336505e4b1c 155 #define PORT_PMUXEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000F7FFE } // Implementation mask for PMUXEN of all pins
Kojto 111:4336505e4b1c 156 #define PORT_PULLEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for PULLEN of all pins
Kojto 111:4336505e4b1c 157 #define PORT_PULLEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for PULLEN of all pins
Kojto 111:4336505e4b1c 158 #define PORT_SLEWLIM 0 // SLEWLIM supported
Kojto 111:4336505e4b1c 159 #define PORT_SLEWLIM_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for SLEWLIM of all pins
Kojto 111:4336505e4b1c 160 #define PORT_SLEWLIM_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 } // Implementation mask for SLEWLIM of all pins
Kojto 111:4336505e4b1c 161
Kojto 111:4336505e4b1c 162 #endif /* _SAMR21_PORT_INSTANCE_ */