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TARGET_MTS_MDOT_F405RG/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_conf.h@146:22da6e220af6, 2017-07-06 (annotated)

Committer:
AnnaBridge
Date:
Thu Jul 06 15:30:22 2017 +0100
Revision:
146:22da6e220af6
Parent:
145:64910690c574 
Release 146 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 133:99b5ccf27215 1 /**
<> 133:99b5ccf27215 2 ******************************************************************************
<> 133:99b5ccf27215 3 * @file stm32f4xx_hal_conf.h
<> 133:99b5ccf27215 4 * @author MCD Application Team
AnnaBridge 145:64910690c574 5 * @version V1.7.1
AnnaBridge 145:64910690c574 6 * @date 14-April-2017
<> 133:99b5ccf27215 7 * @brief HAL configuration file.
<> 133:99b5ccf27215 8 ******************************************************************************
<> 133:99b5ccf27215 9 * @attention
<> 133:99b5ccf27215 10 *
AnnaBridge 145:64910690c574 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 133:99b5ccf27215 12 *
<> 133:99b5ccf27215 13 * Redistribution and use in source and binary forms, with or without modification,
<> 133:99b5ccf27215 14 * are permitted provided that the following conditions are met:
<> 133:99b5ccf27215 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 133:99b5ccf27215 16 * this list of conditions and the following disclaimer.
<> 133:99b5ccf27215 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 133:99b5ccf27215 18 * this list of conditions and the following disclaimer in the documentation
<> 133:99b5ccf27215 19 * and/or other materials provided with the distribution.
<> 133:99b5ccf27215 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 133:99b5ccf27215 21 * may be used to endorse or promote products derived from this software
<> 133:99b5ccf27215 22 * without specific prior written permission.
<> 133:99b5ccf27215 23 *
<> 133:99b5ccf27215 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 133:99b5ccf27215 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 133:99b5ccf27215 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 133:99b5ccf27215 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 133:99b5ccf27215 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 133:99b5ccf27215 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 133:99b5ccf27215 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 133:99b5ccf27215 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 133:99b5ccf27215 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 133:99b5ccf27215 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 133:99b5ccf27215 34 *
<> 133:99b5ccf27215 35 ******************************************************************************
<> 133:99b5ccf27215 36 */
<> 133:99b5ccf27215 37
<> 133:99b5ccf27215 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 133:99b5ccf27215 39 #ifndef __STM32F4xx_HAL_CONF_H
<> 133:99b5ccf27215 40 #define __STM32F4xx_HAL_CONF_H
<> 133:99b5ccf27215 41
<> 133:99b5ccf27215 42 #ifdef __cplusplus
<> 133:99b5ccf27215 43 extern "C" {
<> 133:99b5ccf27215 44 #endif
<> 133:99b5ccf27215 45
<> 133:99b5ccf27215 46 /* Exported types ------------------------------------------------------------*/
<> 133:99b5ccf27215 47 /* Exported constants --------------------------------------------------------*/
<> 133:99b5ccf27215 48
<> 133:99b5ccf27215 49 /* ########################## Module Selection ############################## */
<> 133:99b5ccf27215 50 /**
<> 133:99b5ccf27215 51 * @brief This is the list of modules to be used in the HAL driver
<> 133:99b5ccf27215 52 */
<> 133:99b5ccf27215 53 #define HAL_MODULE_ENABLED
<> 133:99b5ccf27215 54 #define HAL_ADC_MODULE_ENABLED
<> 133:99b5ccf27215 55 #define HAL_CAN_MODULE_ENABLED
<> 133:99b5ccf27215 56 #define HAL_CRC_MODULE_ENABLED
<> 133:99b5ccf27215 57 #define HAL_CEC_MODULE_ENABLED
<> 133:99b5ccf27215 58 #define HAL_CRYP_MODULE_ENABLED
<> 133:99b5ccf27215 59 #define HAL_DAC_MODULE_ENABLED
<> 133:99b5ccf27215 60 #define HAL_DCMI_MODULE_ENABLED
<> 133:99b5ccf27215 61 #define HAL_DMA_MODULE_ENABLED
<> 133:99b5ccf27215 62 #define HAL_DMA2D_MODULE_ENABLED
<> 133:99b5ccf27215 63 #define HAL_ETH_MODULE_ENABLED
<> 133:99b5ccf27215 64 #define HAL_FLASH_MODULE_ENABLED
<> 133:99b5ccf27215 65 #define HAL_NAND_MODULE_ENABLED
<> 133:99b5ccf27215 66 #define HAL_NOR_MODULE_ENABLED
<> 133:99b5ccf27215 67 #define HAL_PCCARD_MODULE_ENABLED
<> 133:99b5ccf27215 68 #define HAL_SRAM_MODULE_ENABLED
<> 133:99b5ccf27215 69 #define HAL_SDRAM_MODULE_ENABLED
<> 133:99b5ccf27215 70 #define HAL_HASH_MODULE_ENABLED
<> 133:99b5ccf27215 71 #define HAL_GPIO_MODULE_ENABLED
<> 133:99b5ccf27215 72 #define HAL_I2C_MODULE_ENABLED
<> 133:99b5ccf27215 73 #define HAL_I2S_MODULE_ENABLED
<> 133:99b5ccf27215 74 #define HAL_IWDG_MODULE_ENABLED
<> 133:99b5ccf27215 75 #define HAL_LTDC_MODULE_ENABLED
<> 133:99b5ccf27215 76 #define HAL_DSI_MODULE_ENABLED
<> 133:99b5ccf27215 77 #define HAL_PWR_MODULE_ENABLED
<> 133:99b5ccf27215 78 #define HAL_QSPI_MODULE_ENABLED
<> 133:99b5ccf27215 79 #define HAL_RCC_MODULE_ENABLED
<> 133:99b5ccf27215 80 #define HAL_RNG_MODULE_ENABLED
<> 133:99b5ccf27215 81 #define HAL_RTC_MODULE_ENABLED
<> 133:99b5ccf27215 82 #define HAL_SAI_MODULE_ENABLED
<> 133:99b5ccf27215 83 #define HAL_SD_MODULE_ENABLED
<> 133:99b5ccf27215 84 #define HAL_SPI_MODULE_ENABLED
<> 133:99b5ccf27215 85 #define HAL_TIM_MODULE_ENABLED
<> 133:99b5ccf27215 86 #define HAL_UART_MODULE_ENABLED
<> 133:99b5ccf27215 87 #define HAL_USART_MODULE_ENABLED
<> 133:99b5ccf27215 88 #define HAL_IRDA_MODULE_ENABLED
<> 133:99b5ccf27215 89 #define HAL_SMARTCARD_MODULE_ENABLED
<> 133:99b5ccf27215 90 #define HAL_WWDG_MODULE_ENABLED
<> 133:99b5ccf27215 91 #define HAL_CORTEX_MODULE_ENABLED
<> 133:99b5ccf27215 92 #define HAL_PCD_MODULE_ENABLED
<> 133:99b5ccf27215 93 #define HAL_HCD_MODULE_ENABLED
<> 133:99b5ccf27215 94 #define HAL_FMPI2C_MODULE_ENABLED
<> 133:99b5ccf27215 95 #define HAL_SPDIFRX_MODULE_ENABLED
<> 133:99b5ccf27215 96 #define HAL_DFSDM_MODULE_ENABLED
<> 133:99b5ccf27215 97 #define HAL_LPTIM_MODULE_ENABLED
AnnaBridge 145:64910690c574 98 #define HAL_MMC_MODULE_ENABLED
<> 133:99b5ccf27215 99
<> 133:99b5ccf27215 100 /* ########################## HSE/HSI Values adaptation ##################### */
<> 133:99b5ccf27215 101 /**
<> 133:99b5ccf27215 102 * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
<> 133:99b5ccf27215 103 * This value is used by the RCC HAL module to compute the system frequency
<> 133:99b5ccf27215 104 * (when HSE is used as system clock source, directly or through the PLL).
<> 133:99b5ccf27215 105 */
<> 133:99b5ccf27215 106 #if !defined (HSE_VALUE)
<> 133:99b5ccf27215 107 #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
<> 133:99b5ccf27215 108 #endif /* HSE_VALUE */
<> 133:99b5ccf27215 109
<> 133:99b5ccf27215 110 #if !defined (HSE_STARTUP_TIMEOUT)
AnnaBridge 146:22da6e220af6 111 #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */
<> 133:99b5ccf27215 112 #endif /* HSE_STARTUP_TIMEOUT */
<> 133:99b5ccf27215 113
<> 133:99b5ccf27215 114 /**
<> 133:99b5ccf27215 115 * @brief Internal High Speed oscillator (HSI) value.
<> 133:99b5ccf27215 116 * This value is used by the RCC HAL module to compute the system frequency
<> 133:99b5ccf27215 117 * (when HSI is used as system clock source, directly or through the PLL).
<> 133:99b5ccf27215 118 */
<> 133:99b5ccf27215 119 #if !defined (HSI_VALUE)
AnnaBridge 145:64910690c574 120 #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz */
<> 133:99b5ccf27215 121 #endif /* HSI_VALUE */
<> 133:99b5ccf27215 122
<> 133:99b5ccf27215 123 /**
<> 133:99b5ccf27215 124 * @brief Internal Low Speed oscillator (LSI) value.
<> 133:99b5ccf27215 125 */
<> 133:99b5ccf27215 126 #if !defined (LSI_VALUE)
AnnaBridge 145:64910690c574 127 #define LSI_VALUE 32000U /*!< LSI Typical Value in Hz */
AnnaBridge 145:64910690c574 128 #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
AnnaBridge 145:64910690c574 129 The real value may vary depending on the variations
AnnaBridge 145:64910690c574 130 in voltage and temperature. */
<> 133:99b5ccf27215 131 /**
<> 133:99b5ccf27215 132 * @brief External Low Speed oscillator (LSE) value.
<> 133:99b5ccf27215 133 */
<> 133:99b5ccf27215 134 #if !defined (LSE_VALUE)
AnnaBridge 145:64910690c574 135 #define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */
<> 133:99b5ccf27215 136 #endif /* LSE_VALUE */
<> 133:99b5ccf27215 137
<> 133:99b5ccf27215 138 #if !defined (LSE_STARTUP_TIMEOUT)
AnnaBridge 145:64910690c574 139 #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */
<> 133:99b5ccf27215 140 #endif /* LSE_STARTUP_TIMEOUT */
<> 133:99b5ccf27215 141
<> 133:99b5ccf27215 142 /**
<> 133:99b5ccf27215 143 * @brief External clock source for I2S peripheral
<> 133:99b5ccf27215 144 * This value is used by the I2S HAL module to compute the I2S clock source
<> 133:99b5ccf27215 145 * frequency, this source is inserted directly through I2S_CKIN pad.
<> 133:99b5ccf27215 146 */
<> 133:99b5ccf27215 147 #if !defined (EXTERNAL_CLOCK_VALUE)
AnnaBridge 145:64910690c574 148 #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External oscillator in Hz*/
<> 133:99b5ccf27215 149 #endif /* EXTERNAL_CLOCK_VALUE */
<> 133:99b5ccf27215 150
<> 133:99b5ccf27215 151 /* Tip: To avoid modifying this file each time you need to use different HSE,
<> 133:99b5ccf27215 152 === you can define the HSE value in your toolchain compiler preprocessor. */
<> 133:99b5ccf27215 153
<> 133:99b5ccf27215 154 /* ########################### System Configuration ######################### */
<> 133:99b5ccf27215 155 /**
<> 133:99b5ccf27215 156 * @brief This is the HAL system configuration section
<> 133:99b5ccf27215 157 */
AnnaBridge 145:64910690c574 158 #define VDD_VALUE 3300U /*!< Value of VDD in mv */
AnnaBridge 145:64910690c574 159 #define TICK_INT_PRIORITY 0x0FU /*!< tick interrupt priority */
<> 133:99b5ccf27215 160 #define USE_RTOS 0U
<> 133:99b5ccf27215 161 #define PREFETCH_ENABLE 1U
<> 133:99b5ccf27215 162 #define INSTRUCTION_CACHE_ENABLE 1U
<> 133:99b5ccf27215 163 #define DATA_CACHE_ENABLE 1U
<> 133:99b5ccf27215 164
<> 133:99b5ccf27215 165 /* ########################## Assert Selection ############################## */
<> 133:99b5ccf27215 166 /**
<> 133:99b5ccf27215 167 * @brief Uncomment the line below to expanse the "assert_param" macro in the
<> 133:99b5ccf27215 168 * HAL drivers code
<> 133:99b5ccf27215 169 */
<> 133:99b5ccf27215 170 /* #define USE_FULL_ASSERT 1U */
<> 133:99b5ccf27215 171
<> 133:99b5ccf27215 172 /* ################## Ethernet peripheral configuration ##################### */
<> 133:99b5ccf27215 173
<> 133:99b5ccf27215 174 /* Section 1 : Ethernet peripheral configuration */
<> 133:99b5ccf27215 175
<> 133:99b5ccf27215 176 /* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
<> 133:99b5ccf27215 177 #define MAC_ADDR0 2U
<> 133:99b5ccf27215 178 #define MAC_ADDR1 0U
<> 133:99b5ccf27215 179 #define MAC_ADDR2 0U
<> 133:99b5ccf27215 180 #define MAC_ADDR3 0U
<> 133:99b5ccf27215 181 #define MAC_ADDR4 0U
<> 133:99b5ccf27215 182 #define MAC_ADDR5 0U
<> 133:99b5ccf27215 183
<> 133:99b5ccf27215 184 /* Definition of the Ethernet driver buffers size and count */
<> 133:99b5ccf27215 185 #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
<> 133:99b5ccf27215 186 #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
AnnaBridge 145:64910690c574 187 #define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
AnnaBridge 145:64910690c574 188 #define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
<> 133:99b5ccf27215 189
<> 133:99b5ccf27215 190 /* Section 2: PHY configuration section */
<> 133:99b5ccf27215 191
<> 133:99b5ccf27215 192 /* DP83848 PHY Address*/
<> 133:99b5ccf27215 193 #define DP83848_PHY_ADDRESS 0x01U
<> 133:99b5ccf27215 194 /* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
AnnaBridge 145:64910690c574 195 #define PHY_RESET_DELAY 0x000000FFU
<> 133:99b5ccf27215 196 /* PHY Configuration delay */
AnnaBridge 145:64910690c574 197 #define PHY_CONFIG_DELAY 0x00000FFFU
<> 133:99b5ccf27215 198
AnnaBridge 145:64910690c574 199 #define PHY_READ_TO 0x0000FFFFU
AnnaBridge 145:64910690c574 200 #define PHY_WRITE_TO 0x0000FFFFU
<> 133:99b5ccf27215 201
<> 133:99b5ccf27215 202 /* Section 3: Common PHY Registers */
<> 133:99b5ccf27215 203
AnnaBridge 145:64910690c574 204 #define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */
AnnaBridge 145:64910690c574 205 #define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */
<> 133:99b5ccf27215 206
AnnaBridge 145:64910690c574 207 #define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
AnnaBridge 145:64910690c574 208 #define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
AnnaBridge 145:64910690c574 209 #define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
AnnaBridge 145:64910690c574 210 #define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
AnnaBridge 145:64910690c574 211 #define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
AnnaBridge 145:64910690c574 212 #define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
AnnaBridge 145:64910690c574 213 #define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
AnnaBridge 145:64910690c574 214 #define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
AnnaBridge 145:64910690c574 215 #define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
AnnaBridge 145:64910690c574 216 #define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
<> 133:99b5ccf27215 217
AnnaBridge 145:64910690c574 218 #define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
AnnaBridge 145:64910690c574 219 #define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
AnnaBridge 145:64910690c574 220 #define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
<> 133:99b5ccf27215 221
<> 133:99b5ccf27215 222 /* Section 4: Extended PHY Registers */
<> 133:99b5ccf27215 223
AnnaBridge 145:64910690c574 224 #define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */
AnnaBridge 145:64910690c574 225 #define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */
AnnaBridge 145:64910690c574 226 #define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */
<> 133:99b5ccf27215 227
AnnaBridge 145:64910690c574 228 #define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
AnnaBridge 145:64910690c574 229 #define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
AnnaBridge 145:64910690c574 230 #define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
<> 133:99b5ccf27215 231
AnnaBridge 145:64910690c574 232 #define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
AnnaBridge 145:64910690c574 233 #define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
<> 133:99b5ccf27215 234
AnnaBridge 145:64910690c574 235 #define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
AnnaBridge 145:64910690c574 236 #define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
<> 133:99b5ccf27215 237
<> 133:99b5ccf27215 238 /* ################## SPI peripheral configuration ########################## */
<> 133:99b5ccf27215 239
<> 133:99b5ccf27215 240 /* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
<> 133:99b5ccf27215 241 * Activated: CRC code is present inside driver
<> 133:99b5ccf27215 242 * Deactivated: CRC code cleaned from driver
<> 133:99b5ccf27215 243 */
<> 133:99b5ccf27215 244
<> 133:99b5ccf27215 245 #define USE_SPI_CRC 1U
<> 133:99b5ccf27215 246
<> 133:99b5ccf27215 247 /* Includes ------------------------------------------------------------------*/
<> 133:99b5ccf27215 248 /**
<> 133:99b5ccf27215 249 * @brief Include module's header file
<> 133:99b5ccf27215 250 */
<> 133:99b5ccf27215 251
<> 133:99b5ccf27215 252 #ifdef HAL_RCC_MODULE_ENABLED
<> 133:99b5ccf27215 253 #include "stm32f4xx_hal_rcc.h"
<> 133:99b5ccf27215 254 #endif /* HAL_RCC_MODULE_ENABLED */
<> 133:99b5ccf27215 255
<> 133:99b5ccf27215 256 #ifdef HAL_GPIO_MODULE_ENABLED
<> 133:99b5ccf27215 257 #include "stm32f4xx_hal_gpio.h"
<> 133:99b5ccf27215 258 #endif /* HAL_GPIO_MODULE_ENABLED */
<> 133:99b5ccf27215 259
<> 133:99b5ccf27215 260 #ifdef HAL_DMA_MODULE_ENABLED
<> 133:99b5ccf27215 261 #include "stm32f4xx_hal_dma.h"
<> 133:99b5ccf27215 262 #endif /* HAL_DMA_MODULE_ENABLED */
<> 133:99b5ccf27215 263
<> 133:99b5ccf27215 264 #ifdef HAL_CORTEX_MODULE_ENABLED
<> 133:99b5ccf27215 265 #include "stm32f4xx_hal_cortex.h"
<> 133:99b5ccf27215 266 #endif /* HAL_CORTEX_MODULE_ENABLED */
<> 133:99b5ccf27215 267
<> 133:99b5ccf27215 268 #ifdef HAL_ADC_MODULE_ENABLED
<> 133:99b5ccf27215 269 #include "stm32f4xx_hal_adc.h"
<> 133:99b5ccf27215 270 #endif /* HAL_ADC_MODULE_ENABLED */
<> 133:99b5ccf27215 271
<> 133:99b5ccf27215 272 #ifdef HAL_CAN_MODULE_ENABLED
<> 133:99b5ccf27215 273 #include "stm32f4xx_hal_can.h"
<> 133:99b5ccf27215 274 #endif /* HAL_CAN_MODULE_ENABLED */
<> 133:99b5ccf27215 275
<> 133:99b5ccf27215 276 #ifdef HAL_CRC_MODULE_ENABLED
<> 133:99b5ccf27215 277 #include "stm32f4xx_hal_crc.h"
<> 133:99b5ccf27215 278 #endif /* HAL_CRC_MODULE_ENABLED */
<> 133:99b5ccf27215 279
<> 133:99b5ccf27215 280 #ifdef HAL_CRYP_MODULE_ENABLED
<> 133:99b5ccf27215 281 #include "stm32f4xx_hal_cryp.h"
<> 133:99b5ccf27215 282 #endif /* HAL_CRYP_MODULE_ENABLED */
<> 133:99b5ccf27215 283
<> 133:99b5ccf27215 284 #ifdef HAL_DMA2D_MODULE_ENABLED
<> 133:99b5ccf27215 285 #include "stm32f4xx_hal_dma2d.h"
<> 133:99b5ccf27215 286 #endif /* HAL_DMA2D_MODULE_ENABLED */
<> 133:99b5ccf27215 287
<> 133:99b5ccf27215 288 #ifdef HAL_DAC_MODULE_ENABLED
<> 133:99b5ccf27215 289 #include "stm32f4xx_hal_dac.h"
<> 133:99b5ccf27215 290 #endif /* HAL_DAC_MODULE_ENABLED */
<> 133:99b5ccf27215 291
<> 133:99b5ccf27215 292 #ifdef HAL_DCMI_MODULE_ENABLED
<> 133:99b5ccf27215 293 #include "stm32f4xx_hal_dcmi.h"
<> 133:99b5ccf27215 294 #endif /* HAL_DCMI_MODULE_ENABLED */
<> 133:99b5ccf27215 295
<> 133:99b5ccf27215 296 #ifdef HAL_ETH_MODULE_ENABLED
<> 133:99b5ccf27215 297 #include "stm32f4xx_hal_eth.h"
<> 133:99b5ccf27215 298 #endif /* HAL_ETH_MODULE_ENABLED */
<> 133:99b5ccf27215 299
<> 133:99b5ccf27215 300 #ifdef HAL_FLASH_MODULE_ENABLED
<> 133:99b5ccf27215 301 #include "stm32f4xx_hal_flash.h"
<> 133:99b5ccf27215 302 #endif /* HAL_FLASH_MODULE_ENABLED */
<> 133:99b5ccf27215 303
<> 133:99b5ccf27215 304 #ifdef HAL_SRAM_MODULE_ENABLED
<> 133:99b5ccf27215 305 #include "stm32f4xx_hal_sram.h"
<> 133:99b5ccf27215 306 #endif /* HAL_SRAM_MODULE_ENABLED */
<> 133:99b5ccf27215 307
<> 133:99b5ccf27215 308 #ifdef HAL_NOR_MODULE_ENABLED
<> 133:99b5ccf27215 309 #include "stm32f4xx_hal_nor.h"
<> 133:99b5ccf27215 310 #endif /* HAL_NOR_MODULE_ENABLED */
<> 133:99b5ccf27215 311
<> 133:99b5ccf27215 312 #ifdef HAL_NAND_MODULE_ENABLED
<> 133:99b5ccf27215 313 #include "stm32f4xx_hal_nand.h"
<> 133:99b5ccf27215 314 #endif /* HAL_NAND_MODULE_ENABLED */
<> 133:99b5ccf27215 315
<> 133:99b5ccf27215 316 #ifdef HAL_PCCARD_MODULE_ENABLED
<> 133:99b5ccf27215 317 #include "stm32f4xx_hal_pccard.h"
<> 133:99b5ccf27215 318 #endif /* HAL_PCCARD_MODULE_ENABLED */
<> 133:99b5ccf27215 319
<> 133:99b5ccf27215 320 #ifdef HAL_SDRAM_MODULE_ENABLED
<> 133:99b5ccf27215 321 #include "stm32f4xx_hal_sdram.h"
<> 133:99b5ccf27215 322 #endif /* HAL_SDRAM_MODULE_ENABLED */
<> 133:99b5ccf27215 323
<> 133:99b5ccf27215 324 #ifdef HAL_HASH_MODULE_ENABLED
<> 133:99b5ccf27215 325 #include "stm32f4xx_hal_hash.h"
<> 133:99b5ccf27215 326 #endif /* HAL_HASH_MODULE_ENABLED */
<> 133:99b5ccf27215 327
<> 133:99b5ccf27215 328 #ifdef HAL_I2C_MODULE_ENABLED
<> 133:99b5ccf27215 329 #include "stm32f4xx_hal_i2c.h"
<> 133:99b5ccf27215 330 #endif /* HAL_I2C_MODULE_ENABLED */
<> 133:99b5ccf27215 331
<> 133:99b5ccf27215 332 #ifdef HAL_I2S_MODULE_ENABLED
<> 133:99b5ccf27215 333 #include "stm32f4xx_hal_i2s.h"
<> 133:99b5ccf27215 334 #endif /* HAL_I2S_MODULE_ENABLED */
<> 133:99b5ccf27215 335
<> 133:99b5ccf27215 336 #ifdef HAL_IWDG_MODULE_ENABLED
<> 133:99b5ccf27215 337 #include "stm32f4xx_hal_iwdg.h"
<> 133:99b5ccf27215 338 #endif /* HAL_IWDG_MODULE_ENABLED */
<> 133:99b5ccf27215 339
<> 133:99b5ccf27215 340 #ifdef HAL_LTDC_MODULE_ENABLED
<> 133:99b5ccf27215 341 #include "stm32f4xx_hal_ltdc.h"
<> 133:99b5ccf27215 342 #endif /* HAL_LTDC_MODULE_ENABLED */
<> 133:99b5ccf27215 343
<> 133:99b5ccf27215 344 #ifdef HAL_PWR_MODULE_ENABLED
<> 133:99b5ccf27215 345 #include "stm32f4xx_hal_pwr.h"
<> 133:99b5ccf27215 346 #endif /* HAL_PWR_MODULE_ENABLED */
<> 133:99b5ccf27215 347
<> 133:99b5ccf27215 348 #ifdef HAL_RNG_MODULE_ENABLED
<> 133:99b5ccf27215 349 #include "stm32f4xx_hal_rng.h"
<> 133:99b5ccf27215 350 #endif /* HAL_RNG_MODULE_ENABLED */
<> 133:99b5ccf27215 351
<> 133:99b5ccf27215 352 #ifdef HAL_RTC_MODULE_ENABLED
<> 133:99b5ccf27215 353 #include "stm32f4xx_hal_rtc.h"
<> 133:99b5ccf27215 354 #endif /* HAL_RTC_MODULE_ENABLED */
<> 133:99b5ccf27215 355
<> 133:99b5ccf27215 356 #ifdef HAL_SAI_MODULE_ENABLED
<> 133:99b5ccf27215 357 #include "stm32f4xx_hal_sai.h"
<> 133:99b5ccf27215 358 #endif /* HAL_SAI_MODULE_ENABLED */
<> 133:99b5ccf27215 359
<> 133:99b5ccf27215 360 #ifdef HAL_SD_MODULE_ENABLED
<> 133:99b5ccf27215 361 #include "stm32f4xx_hal_sd.h"
<> 133:99b5ccf27215 362 #endif /* HAL_SD_MODULE_ENABLED */
<> 133:99b5ccf27215 363
<> 133:99b5ccf27215 364 #ifdef HAL_SPI_MODULE_ENABLED
<> 133:99b5ccf27215 365 #include "stm32f4xx_hal_spi.h"
<> 133:99b5ccf27215 366 #endif /* HAL_SPI_MODULE_ENABLED */
<> 133:99b5ccf27215 367
<> 133:99b5ccf27215 368 #ifdef HAL_TIM_MODULE_ENABLED
<> 133:99b5ccf27215 369 #include "stm32f4xx_hal_tim.h"
<> 133:99b5ccf27215 370 #endif /* HAL_TIM_MODULE_ENABLED */
<> 133:99b5ccf27215 371
<> 133:99b5ccf27215 372 #ifdef HAL_UART_MODULE_ENABLED
<> 133:99b5ccf27215 373 #include "stm32f4xx_hal_uart.h"
<> 133:99b5ccf27215 374 #endif /* HAL_UART_MODULE_ENABLED */
<> 133:99b5ccf27215 375
<> 133:99b5ccf27215 376 #ifdef HAL_USART_MODULE_ENABLED
<> 133:99b5ccf27215 377 #include "stm32f4xx_hal_usart.h"
<> 133:99b5ccf27215 378 #endif /* HAL_USART_MODULE_ENABLED */
<> 133:99b5ccf27215 379
<> 133:99b5ccf27215 380 #ifdef HAL_IRDA_MODULE_ENABLED
<> 133:99b5ccf27215 381 #include "stm32f4xx_hal_irda.h"
<> 133:99b5ccf27215 382 #endif /* HAL_IRDA_MODULE_ENABLED */
<> 133:99b5ccf27215 383
<> 133:99b5ccf27215 384 #ifdef HAL_SMARTCARD_MODULE_ENABLED
<> 133:99b5ccf27215 385 #include "stm32f4xx_hal_smartcard.h"
<> 133:99b5ccf27215 386 #endif /* HAL_SMARTCARD_MODULE_ENABLED */
<> 133:99b5ccf27215 387
<> 133:99b5ccf27215 388 #ifdef HAL_WWDG_MODULE_ENABLED
<> 133:99b5ccf27215 389 #include "stm32f4xx_hal_wwdg.h"
<> 133:99b5ccf27215 390 #endif /* HAL_WWDG_MODULE_ENABLED */
<> 133:99b5ccf27215 391
<> 133:99b5ccf27215 392 #ifdef HAL_PCD_MODULE_ENABLED
<> 133:99b5ccf27215 393 #include "stm32f4xx_hal_pcd.h"
<> 133:99b5ccf27215 394 #endif /* HAL_PCD_MODULE_ENABLED */
<> 133:99b5ccf27215 395
<> 133:99b5ccf27215 396 #ifdef HAL_HCD_MODULE_ENABLED
<> 133:99b5ccf27215 397 #include "stm32f4xx_hal_hcd.h"
<> 133:99b5ccf27215 398 #endif /* HAL_HCD_MODULE_ENABLED */
<> 133:99b5ccf27215 399
<> 133:99b5ccf27215 400 #ifdef HAL_DSI_MODULE_ENABLED
<> 133:99b5ccf27215 401 #include "stm32f4xx_hal_dsi.h"
<> 133:99b5ccf27215 402 #endif /* HAL_DSI_MODULE_ENABLED */
<> 133:99b5ccf27215 403
<> 133:99b5ccf27215 404 #ifdef HAL_QSPI_MODULE_ENABLED
<> 133:99b5ccf27215 405 #include "stm32f4xx_hal_qspi.h"
<> 133:99b5ccf27215 406 #endif /* HAL_QSPI_MODULE_ENABLED */
<> 133:99b5ccf27215 407
<> 133:99b5ccf27215 408 #ifdef HAL_CEC_MODULE_ENABLED
<> 133:99b5ccf27215 409 #include "stm32f4xx_hal_cec.h"
<> 133:99b5ccf27215 410 #endif /* HAL_CEC_MODULE_ENABLED */
<> 133:99b5ccf27215 411
<> 133:99b5ccf27215 412 #ifdef HAL_FMPI2C_MODULE_ENABLED
<> 133:99b5ccf27215 413 #include "stm32f4xx_hal_fmpi2c.h"
<> 133:99b5ccf27215 414 #endif /* HAL_FMPI2C_MODULE_ENABLED */
<> 133:99b5ccf27215 415
<> 133:99b5ccf27215 416 #ifdef HAL_SPDIFRX_MODULE_ENABLED
<> 133:99b5ccf27215 417 #include "stm32f4xx_hal_spdifrx.h"
<> 133:99b5ccf27215 418 #endif /* HAL_SPDIFRX_MODULE_ENABLED */
<> 133:99b5ccf27215 419
<> 133:99b5ccf27215 420 #ifdef HAL_DFSDM_MODULE_ENABLED
<> 133:99b5ccf27215 421 #include "stm32f4xx_hal_dfsdm.h"
<> 133:99b5ccf27215 422 #endif /* HAL_DFSDM_MODULE_ENABLED */
<> 133:99b5ccf27215 423
<> 133:99b5ccf27215 424 #ifdef HAL_LPTIM_MODULE_ENABLED
<> 133:99b5ccf27215 425 #include "stm32f4xx_hal_lptim.h"
<> 133:99b5ccf27215 426 #endif /* HAL_LPTIM_MODULE_ENABLED */
<> 133:99b5ccf27215 427
AnnaBridge 145:64910690c574 428 #ifdef HAL_MMC_MODULE_ENABLED
AnnaBridge 145:64910690c574 429 #include "stm32f4xx_hal_mmc.h"
AnnaBridge 145:64910690c574 430 #endif /* HAL_MMC_MODULE_ENABLED */
AnnaBridge 145:64910690c574 431
<> 133:99b5ccf27215 432 /* Exported macro ------------------------------------------------------------*/
<> 133:99b5ccf27215 433 #ifdef USE_FULL_ASSERT
AnnaBridge 145:64910690c574 434 /* ALL MBED targets use same stm32_assert.h */
AnnaBridge 145:64910690c574 435 #include "stm32_assert.h"
<> 133:99b5ccf27215 436 #else
AnnaBridge 145:64910690c574 437 #define assert_param(expr) ((void)0U)
<> 133:99b5ccf27215 438 #endif /* USE_FULL_ASSERT */
<> 133:99b5ccf27215 439
<> 133:99b5ccf27215 440
<> 133:99b5ccf27215 441 #ifdef __cplusplus
<> 133:99b5ccf27215 442 }
<> 133:99b5ccf27215 443 #endif
<> 133:99b5ccf27215 444
<> 133:99b5ccf27215 445 #endif /* __STM32F4xx_HAL_CONF_H */
<> 133:99b5ccf27215 446
<> 133:99b5ccf27215 447
<> 133:99b5ccf27215 448 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/