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TARGET_DISCO_F413ZH/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_sdmmc.h@146:22da6e220af6, 2017-07-06 (annotated)

Committer:: AnnaBridge
Date:: Thu Jul 06 15:30:22 2017 +0100
Revision:: 146:22da6e220af6
Child:: 163:e59c8e839560

Release 146 of the mbed library.

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	146:22da6e220af6	1	/**
AnnaBridge	146:22da6e220af6	2	******************************************************************************
AnnaBridge	146:22da6e220af6	3	* @file stm32f4xx_ll_sdmmc.h
AnnaBridge	146:22da6e220af6	4	* @author MCD Application Team
AnnaBridge	146:22da6e220af6	5	* @version V1.7.1
AnnaBridge	146:22da6e220af6	6	* @date 14-April-2017
AnnaBridge	146:22da6e220af6	7	* @brief Header file of SDMMC HAL module.
AnnaBridge	146:22da6e220af6	8	******************************************************************************
AnnaBridge	146:22da6e220af6	9	* @attention
AnnaBridge	146:22da6e220af6	10	*
AnnaBridge	146:22da6e220af6	11	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	146:22da6e220af6	12	*
AnnaBridge	146:22da6e220af6	13	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	146:22da6e220af6	14	* are permitted provided that the following conditions are met:
AnnaBridge	146:22da6e220af6	15	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	146:22da6e220af6	16	* this list of conditions and the following disclaimer.
AnnaBridge	146:22da6e220af6	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	146:22da6e220af6	18	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	146:22da6e220af6	19	* and/or other materials provided with the distribution.
AnnaBridge	146:22da6e220af6	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	146:22da6e220af6	21	* may be used to endorse or promote products derived from this software
AnnaBridge	146:22da6e220af6	22	* without specific prior written permission.
AnnaBridge	146:22da6e220af6	23	*
AnnaBridge	146:22da6e220af6	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	146:22da6e220af6	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	146:22da6e220af6	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	146:22da6e220af6	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	146:22da6e220af6	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	146:22da6e220af6	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	146:22da6e220af6	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	146:22da6e220af6	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	146:22da6e220af6	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	146:22da6e220af6	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	146:22da6e220af6	34	*
AnnaBridge	146:22da6e220af6	35	******************************************************************************
AnnaBridge	146:22da6e220af6	36	*/
AnnaBridge	146:22da6e220af6	37
AnnaBridge	146:22da6e220af6	38	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	146:22da6e220af6	39	#ifndef __STM32F4xx_LL_SDMMC_H
AnnaBridge	146:22da6e220af6	40	#define __STM32F4xx_LL_SDMMC_H
AnnaBridge	146:22da6e220af6	41
AnnaBridge	146:22da6e220af6	42	#ifdef __cplusplus
AnnaBridge	146:22da6e220af6	43	extern "C" {
AnnaBridge	146:22da6e220af6	44	#endif
AnnaBridge	146:22da6e220af6	45
AnnaBridge	146:22da6e220af6	46	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
AnnaBridge	146:22da6e220af6	47	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
AnnaBridge	146:22da6e220af6	48	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
AnnaBridge	146:22da6e220af6	49	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
AnnaBridge	146:22da6e220af6	50	defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	146:22da6e220af6	51
AnnaBridge	146:22da6e220af6	52	/* Includes ------------------------------------------------------------------*/
AnnaBridge	146:22da6e220af6	53	#include "stm32f4xx_hal_def.h"
AnnaBridge	146:22da6e220af6	54
AnnaBridge	146:22da6e220af6	55	/** @addtogroup STM32F4xx_Driver
AnnaBridge	146:22da6e220af6	56	* @{
AnnaBridge	146:22da6e220af6	57	*/
AnnaBridge	146:22da6e220af6	58
AnnaBridge	146:22da6e220af6	59	/** @addtogroup SDMMC_LL
AnnaBridge	146:22da6e220af6	60	* @{
AnnaBridge	146:22da6e220af6	61	*/
AnnaBridge	146:22da6e220af6	62
AnnaBridge	146:22da6e220af6	63	/* Exported types ------------------------------------------------------------*/
AnnaBridge	146:22da6e220af6	64	/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
AnnaBridge	146:22da6e220af6	65	* @{
AnnaBridge	146:22da6e220af6	66	*/
AnnaBridge	146:22da6e220af6	67
AnnaBridge	146:22da6e220af6	68	/**
AnnaBridge	146:22da6e220af6	69	* @brief SDMMC Configuration Structure definition
AnnaBridge	146:22da6e220af6	70	*/
AnnaBridge	146:22da6e220af6	71	typedef struct
AnnaBridge	146:22da6e220af6	72	{
AnnaBridge	146:22da6e220af6	73	uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
AnnaBridge	146:22da6e220af6	74	This parameter can be a value of @ref SDMMC_LL_Clock_Edge */
AnnaBridge	146:22da6e220af6	75
AnnaBridge	146:22da6e220af6	76	uint32_t ClockBypass; /*!< Specifies whether the SDMMC Clock divider bypass is
AnnaBridge	146:22da6e220af6	77	enabled or disabled.
AnnaBridge	146:22da6e220af6	78	This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */
AnnaBridge	146:22da6e220af6	79
AnnaBridge	146:22da6e220af6	80	uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or
AnnaBridge	146:22da6e220af6	81	disabled when the bus is idle.
AnnaBridge	146:22da6e220af6	82	This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */
AnnaBridge	146:22da6e220af6	83
AnnaBridge	146:22da6e220af6	84	uint32_t BusWide; /*!< Specifies the SDMMC bus width.
AnnaBridge	146:22da6e220af6	85	This parameter can be a value of @ref SDMMC_LL_Bus_Wide */
AnnaBridge	146:22da6e220af6	86
AnnaBridge	146:22da6e220af6	87	uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled.
AnnaBridge	146:22da6e220af6	88	This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */
AnnaBridge	146:22da6e220af6	89
AnnaBridge	146:22da6e220af6	90	uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller.
AnnaBridge	146:22da6e220af6	91	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	146:22da6e220af6	92
AnnaBridge	146:22da6e220af6	93	}SDIO_InitTypeDef;
AnnaBridge	146:22da6e220af6	94
AnnaBridge	146:22da6e220af6	95
AnnaBridge	146:22da6e220af6	96	/**
AnnaBridge	146:22da6e220af6	97	* @brief SDMMC Command Control structure
AnnaBridge	146:22da6e220af6	98	*/
AnnaBridge	146:22da6e220af6	99	typedef struct
AnnaBridge	146:22da6e220af6	100	{
AnnaBridge	146:22da6e220af6	101	uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent
AnnaBridge	146:22da6e220af6	102	to a card as part of a command message. If a command
AnnaBridge	146:22da6e220af6	103	contains an argument, it must be loaded into this register
AnnaBridge	146:22da6e220af6	104	before writing the command to the command register. */
AnnaBridge	146:22da6e220af6	105
AnnaBridge	146:22da6e220af6	106	uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and
AnnaBridge	146:22da6e220af6	107	Max_Data = 64 */
AnnaBridge	146:22da6e220af6	108
AnnaBridge	146:22da6e220af6	109	uint32_t Response; /*!< Specifies the SDMMC response type.
AnnaBridge	146:22da6e220af6	110	This parameter can be a value of @ref SDMMC_LL_Response_Type */
AnnaBridge	146:22da6e220af6	111
AnnaBridge	146:22da6e220af6	112	uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is
AnnaBridge	146:22da6e220af6	113	enabled or disabled.
AnnaBridge	146:22da6e220af6	114	This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */
AnnaBridge	146:22da6e220af6	115
AnnaBridge	146:22da6e220af6	116	uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM)
AnnaBridge	146:22da6e220af6	117	is enabled or disabled.
AnnaBridge	146:22da6e220af6	118	This parameter can be a value of @ref SDMMC_LL_CPSM_State */
AnnaBridge	146:22da6e220af6	119	}SDIO_CmdInitTypeDef;
AnnaBridge	146:22da6e220af6	120
AnnaBridge	146:22da6e220af6	121
AnnaBridge	146:22da6e220af6	122	/**
AnnaBridge	146:22da6e220af6	123	* @brief SDMMC Data Control structure
AnnaBridge	146:22da6e220af6	124	*/
AnnaBridge	146:22da6e220af6	125	typedef struct
AnnaBridge	146:22da6e220af6	126	{
AnnaBridge	146:22da6e220af6	127	uint32_t DataTimeOut; /!< Specifies the data timeout period in card bus clock periods. /
AnnaBridge	146:22da6e220af6	128
AnnaBridge	146:22da6e220af6	129	uint32_t DataLength; /!< Specifies the number of data bytes to be transferred. /
AnnaBridge	146:22da6e220af6	130
AnnaBridge	146:22da6e220af6	131	uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
AnnaBridge	146:22da6e220af6	132	This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */
AnnaBridge	146:22da6e220af6	133
AnnaBridge	146:22da6e220af6	134	uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
AnnaBridge	146:22da6e220af6	135	is a read or write.
AnnaBridge	146:22da6e220af6	136	This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
AnnaBridge	146:22da6e220af6	137
AnnaBridge	146:22da6e220af6	138	uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
AnnaBridge	146:22da6e220af6	139	This parameter can be a value of @ref SDMMC_LL_Transfer_Type */
AnnaBridge	146:22da6e220af6	140
AnnaBridge	146:22da6e220af6	141	uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM)
AnnaBridge	146:22da6e220af6	142	is enabled or disabled.
AnnaBridge	146:22da6e220af6	143	This parameter can be a value of @ref SDMMC_LL_DPSM_State */
AnnaBridge	146:22da6e220af6	144	}SDIO_DataInitTypeDef;
AnnaBridge	146:22da6e220af6	145
AnnaBridge	146:22da6e220af6	146	/**
AnnaBridge	146:22da6e220af6	147	* @}
AnnaBridge	146:22da6e220af6	148	*/
AnnaBridge	146:22da6e220af6	149
AnnaBridge	146:22da6e220af6	150	/* Exported constants --------------------------------------------------------*/
AnnaBridge	146:22da6e220af6	151	/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
AnnaBridge	146:22da6e220af6	152	* @{
AnnaBridge	146:22da6e220af6	153	*/
AnnaBridge	146:22da6e220af6	154	#define SDMMC_ERROR_NONE 0x00000000U /!< No error /
AnnaBridge	146:22da6e220af6	155	#define SDMMC_ERROR_CMD_CRC_FAIL 0x00000001U /!< Command response received (but CRC check failed) /
AnnaBridge	146:22da6e220af6	156	#define SDMMC_ERROR_DATA_CRC_FAIL 0x00000002U /!< Data block sent/received (CRC check failed) /
AnnaBridge	146:22da6e220af6	157	#define SDMMC_ERROR_CMD_RSP_TIMEOUT 0x00000004U /!< Command response timeout /
AnnaBridge	146:22da6e220af6	158	#define SDMMC_ERROR_DATA_TIMEOUT 0x00000008U /!< Data timeout /
AnnaBridge	146:22da6e220af6	159	#define SDMMC_ERROR_TX_UNDERRUN 0x00000010U /!< Transmit FIFO underrun /
AnnaBridge	146:22da6e220af6	160	#define SDMMC_ERROR_RX_OVERRUN 0x00000020U /!< Receive FIFO overrun /
AnnaBridge	146:22da6e220af6	161	#define SDMMC_ERROR_ADDR_MISALIGNED 0x00000040U /!< Misaligned address /
AnnaBridge	146:22da6e220af6	162	#define SDMMC_ERROR_BLOCK_LEN_ERR 0x00000080U /*!< Transferred block length is not allowed for the card or the
AnnaBridge	146:22da6e220af6	163	number of transferred bytes does not match the block length */
AnnaBridge	146:22da6e220af6	164	#define SDMMC_ERROR_ERASE_SEQ_ERR 0x00000100U /!< An error in the sequence of erase command occurs /
AnnaBridge	146:22da6e220af6	165	#define SDMMC_ERROR_BAD_ERASE_PARAM 0x00000200U /!< An invalid selection for erase groups /
AnnaBridge	146:22da6e220af6	166	#define SDMMC_ERROR_WRITE_PROT_VIOLATION 0x00000400U /!< Attempt to program a write protect block /
AnnaBridge	146:22da6e220af6	167	#define SDMMC_ERROR_LOCK_UNLOCK_FAILED 0x00000800U /*!< Sequence or password error has been detected in unlock
AnnaBridge	146:22da6e220af6	168	command or if there was an attempt to access a locked card */
AnnaBridge	146:22da6e220af6	169	#define SDMMC_ERROR_COM_CRC_FAILED 0x00001000U /!< CRC check of the previous command failed /
AnnaBridge	146:22da6e220af6	170	#define SDMMC_ERROR_ILLEGAL_CMD 0x00002000U /!< Command is not legal for the card state /
AnnaBridge	146:22da6e220af6	171	#define SDMMC_ERROR_CARD_ECC_FAILED 0x00004000U /!< Card internal ECC was applied but failed to correct the data /
AnnaBridge	146:22da6e220af6	172	#define SDMMC_ERROR_CC_ERR 0x00008000U /!< Internal card controller error /
AnnaBridge	146:22da6e220af6	173	#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR 0x00010000U /!< General or unknown error /
AnnaBridge	146:22da6e220af6	174	#define SDMMC_ERROR_STREAM_READ_UNDERRUN 0x00020000U /!< The card could not sustain data reading in stream rmode /
AnnaBridge	146:22da6e220af6	175	#define SDMMC_ERROR_STREAM_WRITE_OVERRUN 0x00040000U /!< The card could not sustain data programming in stream mode /
AnnaBridge	146:22da6e220af6	176	#define SDMMC_ERROR_CID_CSD_OVERWRITE 0x00080000U /!< CID/CSD overwrite error /
AnnaBridge	146:22da6e220af6	177	#define SDMMC_ERROR_WP_ERASE_SKIP 0x00100000U /!< Only partial address space was erased /
AnnaBridge	146:22da6e220af6	178	#define SDMMC_ERROR_CARD_ECC_DISABLED 0x00200000U /!< Command has been executed without using internal ECC /
AnnaBridge	146:22da6e220af6	179	#define SDMMC_ERROR_ERASE_RESET 0x00400000U /*!< Erase sequence was cleared before executing because an out
AnnaBridge	146:22da6e220af6	180	of erase sequence command was received */
AnnaBridge	146:22da6e220af6	181	#define SDMMC_ERROR_AKE_SEQ_ERR 0x00800000U /!< Error in sequence of authentication /
AnnaBridge	146:22da6e220af6	182	#define SDMMC_ERROR_INVALID_VOLTRANGE 0x01000000U /!< Error in case of invalid voltage range /
AnnaBridge	146:22da6e220af6	183	#define SDMMC_ERROR_ADDR_OUT_OF_RANGE 0x02000000U /!< Error when addressed block is out of range /
AnnaBridge	146:22da6e220af6	184	#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE 0x04000000U /!< Error when command request is not applicable /
AnnaBridge	146:22da6e220af6	185	#define SDMMC_ERROR_INVALID_PARAMETER 0x08000000U /!< the used parameter is not valid /
AnnaBridge	146:22da6e220af6	186	#define SDMMC_ERROR_UNSUPPORTED_FEATURE 0x10000000U /!< Error when feature is not insupported /
AnnaBridge	146:22da6e220af6	187	#define SDMMC_ERROR_BUSY 0x20000000U /!< Error when transfer process is busy /
AnnaBridge	146:22da6e220af6	188	#define SDMMC_ERROR_DMA 0x40000000U /!< Error while DMA transfer /
AnnaBridge	146:22da6e220af6	189	#define SDMMC_ERROR_TIMEOUT 0x80000000U /!< Timeout error /
AnnaBridge	146:22da6e220af6	190
AnnaBridge	146:22da6e220af6	191	/**
AnnaBridge	146:22da6e220af6	192	* @brief SDMMC Commands Index
AnnaBridge	146:22da6e220af6	193	*/
AnnaBridge	146:22da6e220af6	194	#define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0) /!< Resets the SD memory card. /
AnnaBridge	146:22da6e220af6	195	#define SDMMC_CMD_SEND_OP_COND ((uint8_t)1) /!< Sends host capacity support information and activates the card's initialization process. /
AnnaBridge	146:22da6e220af6	196	#define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2) /!< Asks any card connected to the host to send the CID numbers on the CMD line. /
AnnaBridge	146:22da6e220af6	197	#define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3) /!< Asks the card to publish a new relative address (RCA). /
AnnaBridge	146:22da6e220af6	198	#define SDMMC_CMD_SET_DSR ((uint8_t)4) /!< Programs the DSR of all cards. /
AnnaBridge	146:22da6e220af6	199	#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
AnnaBridge	146:22da6e220af6	200	operating condition register (OCR) content in the response on the CMD line. */
AnnaBridge	146:22da6e220af6	201	#define SDMMC_CMD_HS_SWITCH ((uint8_t)6) /!< Checks switchable function (mode 0) and switch card function (mode 1). /
AnnaBridge	146:22da6e220af6	202	#define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7) /!< Selects the card by its own relative address and gets deselected by any other address /
AnnaBridge	146:22da6e220af6	203	#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
AnnaBridge	146:22da6e220af6	204	and asks the card whether card supports voltage. */
AnnaBridge	146:22da6e220af6	205	#define SDMMC_CMD_SEND_CSD ((uint8_t)9) /!< Addressed card sends its card specific data (CSD) on the CMD line. /
AnnaBridge	146:22da6e220af6	206	#define SDMMC_CMD_SEND_CID ((uint8_t)10) /!< Addressed card sends its card identification (CID) on the CMD line. /
AnnaBridge	146:22da6e220af6	207	#define SDMMC_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11) /!< SD card doesn't support it. /
AnnaBridge	146:22da6e220af6	208	#define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12) /!< Forces the card to stop transmission. /
AnnaBridge	146:22da6e220af6	209	#define SDMMC_CMD_SEND_STATUS ((uint8_t)13) /!< Addressed card sends its status register. /
AnnaBridge	146:22da6e220af6	210	#define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14) /!< Reserved /
AnnaBridge	146:22da6e220af6	211	#define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15) /!< Sends an addressed card into the inactive state. /
AnnaBridge	146:22da6e220af6	212	#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16) /*!< Sets the block length (in bytes for SDSC) for all following block commands
AnnaBridge	146:22da6e220af6	213	(read, write, lock). Default block length is fixed to 512 Bytes. Not effective
AnnaBridge	146:22da6e220af6	214	for SDHS and SDXC. */
AnnaBridge	146:22da6e220af6	215	#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
AnnaBridge	146:22da6e220af6	216	fixed 512 bytes in case of SDHC and SDXC. */
AnnaBridge	146:22da6e220af6	217	#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18) /*!< Continuously transfers data blocks from card to host until interrupted by
AnnaBridge	146:22da6e220af6	218	STOP_TRANSMISSION command. */
AnnaBridge	146:22da6e220af6	219	#define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19) /!< 64 bytes tuning pattern is sent for SDR50 and SDR104. /
AnnaBridge	146:22da6e220af6	220	#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20) /!< Speed class control command. /
AnnaBridge	146:22da6e220af6	221	#define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23) /!< Specify block count for CMD18 and CMD25. /
AnnaBridge	146:22da6e220af6	222	#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
AnnaBridge	146:22da6e220af6	223	fixed 512 bytes in case of SDHC and SDXC. */
AnnaBridge	146:22da6e220af6	224	#define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25) /!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. /
AnnaBridge	146:22da6e220af6	225	#define SDMMC_CMD_PROG_CID ((uint8_t)26) /!< Reserved for manufacturers. /
AnnaBridge	146:22da6e220af6	226	#define SDMMC_CMD_PROG_CSD ((uint8_t)27) /!< Programming of the programmable bits of the CSD. /
AnnaBridge	146:22da6e220af6	227	#define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28) /!< Sets the write protection bit of the addressed group. /
AnnaBridge	146:22da6e220af6	228	#define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29) /!< Clears the write protection bit of the addressed group. /
AnnaBridge	146:22da6e220af6	229	#define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30) /!< Asks the card to send the status of the write protection bits. /
AnnaBridge	146:22da6e220af6	230	#define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32) /!< Sets the address of the first write block to be erased. (For SD card only). /
AnnaBridge	146:22da6e220af6	231	#define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33) /!< Sets the address of the last write block of the continuous range to be erased. /
AnnaBridge	146:22da6e220af6	232	#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35) /*!< Sets the address of the first write block to be erased. Reserved for each command
AnnaBridge	146:22da6e220af6	233	system set by switch function command (CMD6). */
AnnaBridge	146:22da6e220af6	234	#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36) /*!< Sets the address of the last write block of the continuous range to be erased.
AnnaBridge	146:22da6e220af6	235	Reserved for each command system set by switch function command (CMD6). */
AnnaBridge	146:22da6e220af6	236	#define SDMMC_CMD_ERASE ((uint8_t)38) /!< Reserved for SD security applications. /
AnnaBridge	146:22da6e220af6	237	#define SDMMC_CMD_FAST_IO ((uint8_t)39) /!< SD card doesn't support it (Reserved). /
AnnaBridge	146:22da6e220af6	238	#define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40) /!< SD card doesn't support it (Reserved). /
AnnaBridge	146:22da6e220af6	239	#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
AnnaBridge	146:22da6e220af6	240	the SET_BLOCK_LEN command. */
AnnaBridge	146:22da6e220af6	241	#define SDMMC_CMD_APP_CMD ((uint8_t)55) /*!< Indicates to the card that the next command is an application specific command rather
AnnaBridge	146:22da6e220af6	242	than a standard command. */
AnnaBridge	146:22da6e220af6	243	#define SDMMC_CMD_GEN_CMD ((uint8_t)56) /*!< Used either to transfer a data block to the card or to get a data block from the card
AnnaBridge	146:22da6e220af6	244	for general purpose/application specific commands. */
AnnaBridge	146:22da6e220af6	245	#define SDMMC_CMD_NO_CMD ((uint8_t)64) /!< No command /
AnnaBridge	146:22da6e220af6	246
AnnaBridge	146:22da6e220af6	247	/**
AnnaBridge	146:22da6e220af6	248	* @brief Following commands are SD Card Specific commands.
AnnaBridge	146:22da6e220af6	249	* SDMMC_APP_CMD should be sent before sending these commands.
AnnaBridge	146:22da6e220af6	250	*/
AnnaBridge	146:22da6e220af6	251	#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
AnnaBridge	146:22da6e220af6	252	widths are given in SCR register. */
AnnaBridge	146:22da6e220af6	253	#define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13) /!< (ACMD13) Sends the SD status. /
AnnaBridge	146:22da6e220af6	254	#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
AnnaBridge	146:22da6e220af6	255	32bit+CRC data block. */
AnnaBridge	146:22da6e220af6	256	#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
AnnaBridge	146:22da6e220af6	257	send its operating condition register (OCR) content in the response on the CMD line. */
AnnaBridge	146:22da6e220af6	258	#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42) /!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card /
AnnaBridge	146:22da6e220af6	259	#define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51) /!< Reads the SD Configuration Register (SCR). /
AnnaBridge	146:22da6e220af6	260	#define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52) /!< For SD I/O card only, reserved for security specification. /
AnnaBridge	146:22da6e220af6	261	#define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53) /!< For SD I/O card only, reserved for security specification. /
AnnaBridge	146:22da6e220af6	262
AnnaBridge	146:22da6e220af6	263	/**
AnnaBridge	146:22da6e220af6	264	* @brief Following commands are SD Card Specific security commands.
AnnaBridge	146:22da6e220af6	265	* SDMMC_CMD_APP_CMD should be sent before sending these commands.
AnnaBridge	146:22da6e220af6	266	*/
AnnaBridge	146:22da6e220af6	267	#define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43)
AnnaBridge	146:22da6e220af6	268	#define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44)
AnnaBridge	146:22da6e220af6	269	#define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45)
AnnaBridge	146:22da6e220af6	270	#define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46)
AnnaBridge	146:22da6e220af6	271	#define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47)
AnnaBridge	146:22da6e220af6	272	#define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48)
AnnaBridge	146:22da6e220af6	273	#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18)
AnnaBridge	146:22da6e220af6	274	#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25)
AnnaBridge	146:22da6e220af6	275	#define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38)
AnnaBridge	146:22da6e220af6	276	#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49)
AnnaBridge	146:22da6e220af6	277	#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48)
AnnaBridge	146:22da6e220af6	278
AnnaBridge	146:22da6e220af6	279	/**
AnnaBridge	146:22da6e220af6	280	* @brief Masks for errors Card Status R1 (OCR Register)
AnnaBridge	146:22da6e220af6	281	*/
AnnaBridge	146:22da6e220af6	282	#define SDMMC_OCR_ADDR_OUT_OF_RANGE 0x80000000U
AnnaBridge	146:22da6e220af6	283	#define SDMMC_OCR_ADDR_MISALIGNED 0x40000000U
AnnaBridge	146:22da6e220af6	284	#define SDMMC_OCR_BLOCK_LEN_ERR 0x20000000U
AnnaBridge	146:22da6e220af6	285	#define SDMMC_OCR_ERASE_SEQ_ERR 0x10000000U
AnnaBridge	146:22da6e220af6	286	#define SDMMC_OCR_BAD_ERASE_PARAM 0x08000000U
AnnaBridge	146:22da6e220af6	287	#define SDMMC_OCR_WRITE_PROT_VIOLATION 0x04000000U
AnnaBridge	146:22da6e220af6	288	#define SDMMC_OCR_LOCK_UNLOCK_FAILED 0x01000000U
AnnaBridge	146:22da6e220af6	289	#define SDMMC_OCR_COM_CRC_FAILED 0x00800000U
AnnaBridge	146:22da6e220af6	290	#define SDMMC_OCR_ILLEGAL_CMD 0x00400000U
AnnaBridge	146:22da6e220af6	291	#define SDMMC_OCR_CARD_ECC_FAILED 0x00200000U
AnnaBridge	146:22da6e220af6	292	#define SDMMC_OCR_CC_ERROR 0x00100000U
AnnaBridge	146:22da6e220af6	293	#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR 0x00080000U
AnnaBridge	146:22da6e220af6	294	#define SDMMC_OCR_STREAM_READ_UNDERRUN 0x00040000U
AnnaBridge	146:22da6e220af6	295	#define SDMMC_OCR_STREAM_WRITE_OVERRUN 0x00020000U
AnnaBridge	146:22da6e220af6	296	#define SDMMC_OCR_CID_CSD_OVERWRITE 0x00010000U
AnnaBridge	146:22da6e220af6	297	#define SDMMC_OCR_WP_ERASE_SKIP 0x00008000U
AnnaBridge	146:22da6e220af6	298	#define SDMMC_OCR_CARD_ECC_DISABLED 0x00004000U
AnnaBridge	146:22da6e220af6	299	#define SDMMC_OCR_ERASE_RESET 0x00002000U
AnnaBridge	146:22da6e220af6	300	#define SDMMC_OCR_AKE_SEQ_ERROR 0x00000008U
AnnaBridge	146:22da6e220af6	301	#define SDMMC_OCR_ERRORBITS 0xFDFFE008U
AnnaBridge	146:22da6e220af6	302
AnnaBridge	146:22da6e220af6	303	/**
AnnaBridge	146:22da6e220af6	304	* @brief Masks for R6 Response
AnnaBridge	146:22da6e220af6	305	*/
AnnaBridge	146:22da6e220af6	306	#define SDMMC_R6_GENERAL_UNKNOWN_ERROR 0x00002000U
AnnaBridge	146:22da6e220af6	307	#define SDMMC_R6_ILLEGAL_CMD 0x00004000U
AnnaBridge	146:22da6e220af6	308	#define SDMMC_R6_COM_CRC_FAILED 0x00008000U
AnnaBridge	146:22da6e220af6	309
AnnaBridge	146:22da6e220af6	310	#define SDMMC_VOLTAGE_WINDOW_SD 0x80100000U
AnnaBridge	146:22da6e220af6	311	#define SDMMC_HIGH_CAPACITY 0x40000000U
AnnaBridge	146:22da6e220af6	312	#define SDMMC_STD_CAPACITY 0x00000000U
AnnaBridge	146:22da6e220af6	313	#define SDMMC_CHECK_PATTERN 0x000001AAU
AnnaBridge	146:22da6e220af6	314
AnnaBridge	146:22da6e220af6	315	#define SDMMC_MAX_VOLT_TRIAL 0x0000FFFFU
AnnaBridge	146:22da6e220af6	316
AnnaBridge	146:22da6e220af6	317	#define SDMMC_MAX_TRIAL 0x0000FFFFU
AnnaBridge	146:22da6e220af6	318
AnnaBridge	146:22da6e220af6	319	#define SDMMC_ALLZERO 0x00000000U
AnnaBridge	146:22da6e220af6	320
AnnaBridge	146:22da6e220af6	321	#define SDMMC_WIDE_BUS_SUPPORT 0x00040000U
AnnaBridge	146:22da6e220af6	322	#define SDMMC_SINGLE_BUS_SUPPORT 0x00010000U
AnnaBridge	146:22da6e220af6	323	#define SDMMC_CARD_LOCKED 0x02000000U
AnnaBridge	146:22da6e220af6	324
AnnaBridge	146:22da6e220af6	325	#define SDMMC_DATATIMEOUT 0xFFFFFFFFU
AnnaBridge	146:22da6e220af6	326
AnnaBridge	146:22da6e220af6	327	#define SDMMC_0TO7BITS 0x000000FFU
AnnaBridge	146:22da6e220af6	328	#define SDMMC_8TO15BITS 0x0000FF00U
AnnaBridge	146:22da6e220af6	329	#define SDMMC_16TO23BITS 0x00FF0000U
AnnaBridge	146:22da6e220af6	330	#define SDMMC_24TO31BITS 0xFF000000U
AnnaBridge	146:22da6e220af6	331	#define SDMMC_MAX_DATA_LENGTH 0x01FFFFFFU
AnnaBridge	146:22da6e220af6	332
AnnaBridge	146:22da6e220af6	333	#define SDMMC_HALFFIFO 0x00000008U
AnnaBridge	146:22da6e220af6	334	#define SDMMC_HALFFIFOBYTES 0x00000020U
AnnaBridge	146:22da6e220af6	335
AnnaBridge	146:22da6e220af6	336	/**
AnnaBridge	146:22da6e220af6	337	* @brief Command Class supported
AnnaBridge	146:22da6e220af6	338	*/
AnnaBridge	146:22da6e220af6	339	#define SDIO_CCCC_ERASE 0x00000020U
AnnaBridge	146:22da6e220af6	340
AnnaBridge	146:22da6e220af6	341	#define SDIO_CMDTIMEOUT 5000U /* Command send and response timeout */
AnnaBridge	146:22da6e220af6	342	#define SDIO_MAXERASETIMEOUT 63000U /* Max erase Timeout 63 s */
AnnaBridge	146:22da6e220af6	343
AnnaBridge	146:22da6e220af6	344
AnnaBridge	146:22da6e220af6	345	/** @defgroup SDIO_LL_Clock_Edge Clock Edge
AnnaBridge	146:22da6e220af6	346	* @{
AnnaBridge	146:22da6e220af6	347	*/
AnnaBridge	146:22da6e220af6	348	#define SDIO_CLOCK_EDGE_RISING 0x00000000U
AnnaBridge	146:22da6e220af6	349	#define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE
AnnaBridge	146:22da6e220af6	350
AnnaBridge	146:22da6e220af6	351	#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) \|\| \
AnnaBridge	146:22da6e220af6	352	((EDGE) == SDIO_CLOCK_EDGE_FALLING))
AnnaBridge	146:22da6e220af6	353	/**
AnnaBridge	146:22da6e220af6	354	* @}
AnnaBridge	146:22da6e220af6	355	*/
AnnaBridge	146:22da6e220af6	356
AnnaBridge	146:22da6e220af6	357	/** @defgroup SDIO_LL_Clock_Bypass Clock Bypass
AnnaBridge	146:22da6e220af6	358	* @{
AnnaBridge	146:22da6e220af6	359	*/
AnnaBridge	146:22da6e220af6	360	#define SDIO_CLOCK_BYPASS_DISABLE 0x00000000U
AnnaBridge	146:22da6e220af6	361	#define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS
AnnaBridge	146:22da6e220af6	362
AnnaBridge	146:22da6e220af6	363	#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) \|\| \
AnnaBridge	146:22da6e220af6	364	((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
AnnaBridge	146:22da6e220af6	365	/**
AnnaBridge	146:22da6e220af6	366	* @}
AnnaBridge	146:22da6e220af6	367	*/
AnnaBridge	146:22da6e220af6	368
AnnaBridge	146:22da6e220af6	369	/** @defgroup SDIO_LL_Clock_Power_Save Clock Power Saving
AnnaBridge	146:22da6e220af6	370	* @{
AnnaBridge	146:22da6e220af6	371	*/
AnnaBridge	146:22da6e220af6	372	#define SDIO_CLOCK_POWER_SAVE_DISABLE 0x00000000U
AnnaBridge	146:22da6e220af6	373	#define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV
AnnaBridge	146:22da6e220af6	374
AnnaBridge	146:22da6e220af6	375	#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) \|\| \
AnnaBridge	146:22da6e220af6	376	((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
AnnaBridge	146:22da6e220af6	377	/**
AnnaBridge	146:22da6e220af6	378	* @}
AnnaBridge	146:22da6e220af6	379	*/
AnnaBridge	146:22da6e220af6	380
AnnaBridge	146:22da6e220af6	381	/** @defgroup SDIO_LL_Bus_Wide Bus Width
AnnaBridge	146:22da6e220af6	382	* @{
AnnaBridge	146:22da6e220af6	383	*/
AnnaBridge	146:22da6e220af6	384	#define SDIO_BUS_WIDE_1B 0x00000000U
AnnaBridge	146:22da6e220af6	385	#define SDIO_BUS_WIDE_4B SDIO_CLKCR_WIDBUS_0
AnnaBridge	146:22da6e220af6	386	#define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1
AnnaBridge	146:22da6e220af6	387
AnnaBridge	146:22da6e220af6	388	#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) \|\| \
AnnaBridge	146:22da6e220af6	389	((WIDE) == SDIO_BUS_WIDE_4B) \|\| \
AnnaBridge	146:22da6e220af6	390	((WIDE) == SDIO_BUS_WIDE_8B))
AnnaBridge	146:22da6e220af6	391	/**
AnnaBridge	146:22da6e220af6	392	* @}
AnnaBridge	146:22da6e220af6	393	*/
AnnaBridge	146:22da6e220af6	394
AnnaBridge	146:22da6e220af6	395	/** @defgroup SDIO_LL_Hardware_Flow_Control Hardware Flow Control
AnnaBridge	146:22da6e220af6	396	* @{
AnnaBridge	146:22da6e220af6	397	*/
AnnaBridge	146:22da6e220af6	398	#define SDIO_HARDWARE_FLOW_CONTROL_DISABLE 0x00000000U
AnnaBridge	146:22da6e220af6	399	#define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN
AnnaBridge	146:22da6e220af6	400
AnnaBridge	146:22da6e220af6	401	#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) \|\| \
AnnaBridge	146:22da6e220af6	402	((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
AnnaBridge	146:22da6e220af6	403	/**
AnnaBridge	146:22da6e220af6	404	* @}
AnnaBridge	146:22da6e220af6	405	*/
AnnaBridge	146:22da6e220af6	406
AnnaBridge	146:22da6e220af6	407	/** @defgroup SDIO_LL_Clock_Division Clock Division
AnnaBridge	146:22da6e220af6	408	* @{
AnnaBridge	146:22da6e220af6	409	*/
AnnaBridge	146:22da6e220af6	410	#define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFFU)
AnnaBridge	146:22da6e220af6	411	/**
AnnaBridge	146:22da6e220af6	412	* @}
AnnaBridge	146:22da6e220af6	413	*/
AnnaBridge	146:22da6e220af6	414
AnnaBridge	146:22da6e220af6	415	/** @defgroup SDIO_LL_Command_Index Command Index
AnnaBridge	146:22da6e220af6	416	* @{
AnnaBridge	146:22da6e220af6	417	*/
AnnaBridge	146:22da6e220af6	418	#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40U)
AnnaBridge	146:22da6e220af6	419	/**
AnnaBridge	146:22da6e220af6	420	* @}
AnnaBridge	146:22da6e220af6	421	*/
AnnaBridge	146:22da6e220af6	422
AnnaBridge	146:22da6e220af6	423	/** @defgroup SDIO_LL_Response_Type Response Type
AnnaBridge	146:22da6e220af6	424	* @{
AnnaBridge	146:22da6e220af6	425	*/
AnnaBridge	146:22da6e220af6	426	#define SDIO_RESPONSE_NO 0x00000000U
AnnaBridge	146:22da6e220af6	427	#define SDIO_RESPONSE_SHORT SDIO_CMD_WAITRESP_0
AnnaBridge	146:22da6e220af6	428	#define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP
AnnaBridge	146:22da6e220af6	429
AnnaBridge	146:22da6e220af6	430	#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) \|\| \
AnnaBridge	146:22da6e220af6	431	((RESPONSE) == SDIO_RESPONSE_SHORT) \|\| \
AnnaBridge	146:22da6e220af6	432	((RESPONSE) == SDIO_RESPONSE_LONG))
AnnaBridge	146:22da6e220af6	433	/**
AnnaBridge	146:22da6e220af6	434	* @}
AnnaBridge	146:22da6e220af6	435	*/
AnnaBridge	146:22da6e220af6	436
AnnaBridge	146:22da6e220af6	437	/** @defgroup SDIO_LL_Wait_Interrupt_State Wait Interrupt
AnnaBridge	146:22da6e220af6	438	* @{
AnnaBridge	146:22da6e220af6	439	*/
AnnaBridge	146:22da6e220af6	440	#define SDIO_WAIT_NO 0x00000000U
AnnaBridge	146:22da6e220af6	441	#define SDIO_WAIT_IT SDIO_CMD_WAITINT
AnnaBridge	146:22da6e220af6	442	#define SDIO_WAIT_PEND SDIO_CMD_WAITPEND
AnnaBridge	146:22da6e220af6	443
AnnaBridge	146:22da6e220af6	444	#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) \|\| \
AnnaBridge	146:22da6e220af6	445	((WAIT) == SDIO_WAIT_IT) \|\| \
AnnaBridge	146:22da6e220af6	446	((WAIT) == SDIO_WAIT_PEND))
AnnaBridge	146:22da6e220af6	447	/**
AnnaBridge	146:22da6e220af6	448	* @}
AnnaBridge	146:22da6e220af6	449	*/
AnnaBridge	146:22da6e220af6	450
AnnaBridge	146:22da6e220af6	451	/** @defgroup SDIO_LL_CPSM_State CPSM State
AnnaBridge	146:22da6e220af6	452	* @{
AnnaBridge	146:22da6e220af6	453	*/
AnnaBridge	146:22da6e220af6	454	#define SDIO_CPSM_DISABLE 0x00000000U
AnnaBridge	146:22da6e220af6	455	#define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN
AnnaBridge	146:22da6e220af6	456
AnnaBridge	146:22da6e220af6	457	#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) \|\| \
AnnaBridge	146:22da6e220af6	458	((CPSM) == SDIO_CPSM_ENABLE))
AnnaBridge	146:22da6e220af6	459	/**
AnnaBridge	146:22da6e220af6	460	* @}
AnnaBridge	146:22da6e220af6	461	*/
AnnaBridge	146:22da6e220af6	462
AnnaBridge	146:22da6e220af6	463	/** @defgroup SDIO_LL_Response_Registers Response Register
AnnaBridge	146:22da6e220af6	464	* @{
AnnaBridge	146:22da6e220af6	465	*/
AnnaBridge	146:22da6e220af6	466	#define SDIO_RESP1 0x00000000U
AnnaBridge	146:22da6e220af6	467	#define SDIO_RESP2 0x00000004U
AnnaBridge	146:22da6e220af6	468	#define SDIO_RESP3 0x00000008U
AnnaBridge	146:22da6e220af6	469	#define SDIO_RESP4 0x0000000CU
AnnaBridge	146:22da6e220af6	470
AnnaBridge	146:22da6e220af6	471	#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) \|\| \
AnnaBridge	146:22da6e220af6	472	((RESP) == SDIO_RESP2) \|\| \
AnnaBridge	146:22da6e220af6	473	((RESP) == SDIO_RESP3) \|\| \
AnnaBridge	146:22da6e220af6	474	((RESP) == SDIO_RESP4))
AnnaBridge	146:22da6e220af6	475	/**
AnnaBridge	146:22da6e220af6	476	* @}
AnnaBridge	146:22da6e220af6	477	*/
AnnaBridge	146:22da6e220af6	478
AnnaBridge	146:22da6e220af6	479	/** @defgroup SDIO_LL_Data_Length Data Lenght
AnnaBridge	146:22da6e220af6	480	* @{
AnnaBridge	146:22da6e220af6	481	*/
AnnaBridge	146:22da6e220af6	482	#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU)
AnnaBridge	146:22da6e220af6	483	/**
AnnaBridge	146:22da6e220af6	484	* @}
AnnaBridge	146:22da6e220af6	485	*/
AnnaBridge	146:22da6e220af6	486
AnnaBridge	146:22da6e220af6	487	/** @defgroup SDIO_LL_Data_Block_Size Data Block Size
AnnaBridge	146:22da6e220af6	488	* @{
AnnaBridge	146:22da6e220af6	489	*/
AnnaBridge	146:22da6e220af6	490	#define SDIO_DATABLOCK_SIZE_1B 0x00000000U
AnnaBridge	146:22da6e220af6	491	#define SDIO_DATABLOCK_SIZE_2B SDIO_DCTRL_DBLOCKSIZE_0
AnnaBridge	146:22da6e220af6	492	#define SDIO_DATABLOCK_SIZE_4B SDIO_DCTRL_DBLOCKSIZE_1
AnnaBridge	146:22da6e220af6	493	#define SDIO_DATABLOCK_SIZE_8B (SDIO_DCTRL_DBLOCKSIZE_0\|SDIO_DCTRL_DBLOCKSIZE_1)
AnnaBridge	146:22da6e220af6	494	#define SDIO_DATABLOCK_SIZE_16B SDIO_DCTRL_DBLOCKSIZE_2
AnnaBridge	146:22da6e220af6	495	#define SDIO_DATABLOCK_SIZE_32B (SDIO_DCTRL_DBLOCKSIZE_0\|SDIO_DCTRL_DBLOCKSIZE_2)
AnnaBridge	146:22da6e220af6	496	#define SDIO_DATABLOCK_SIZE_64B (SDIO_DCTRL_DBLOCKSIZE_1\|SDIO_DCTRL_DBLOCKSIZE_2)
AnnaBridge	146:22da6e220af6	497	#define SDIO_DATABLOCK_SIZE_128B (SDIO_DCTRL_DBLOCKSIZE_0\|SDIO_DCTRL_DBLOCKSIZE_1\|SDIO_DCTRL_DBLOCKSIZE_2)
AnnaBridge	146:22da6e220af6	498	#define SDIO_DATABLOCK_SIZE_256B SDIO_DCTRL_DBLOCKSIZE_3
AnnaBridge	146:22da6e220af6	499	#define SDIO_DATABLOCK_SIZE_512B (SDIO_DCTRL_DBLOCKSIZE_0\|SDIO_DCTRL_DBLOCKSIZE_3)
AnnaBridge	146:22da6e220af6	500	#define SDIO_DATABLOCK_SIZE_1024B (SDIO_DCTRL_DBLOCKSIZE_1\|SDIO_DCTRL_DBLOCKSIZE_3)
AnnaBridge	146:22da6e220af6	501	#define SDIO_DATABLOCK_SIZE_2048B (SDIO_DCTRL_DBLOCKSIZE_0\|SDIO_DCTRL_DBLOCKSIZE_1\|SDIO_DCTRL_DBLOCKSIZE_3)
AnnaBridge	146:22da6e220af6	502	#define SDIO_DATABLOCK_SIZE_4096B (SDIO_DCTRL_DBLOCKSIZE_2\|SDIO_DCTRL_DBLOCKSIZE_3)
AnnaBridge	146:22da6e220af6	503	#define SDIO_DATABLOCK_SIZE_8192B (SDIO_DCTRL_DBLOCKSIZE_0\|SDIO_DCTRL_DBLOCKSIZE_2\|SDIO_DCTRL_DBLOCKSIZE_3)
AnnaBridge	146:22da6e220af6	504	#define SDIO_DATABLOCK_SIZE_16384B (SDIO_DCTRL_DBLOCKSIZE_1\|SDIO_DCTRL_DBLOCKSIZE_2\|SDIO_DCTRL_DBLOCKSIZE_3)
AnnaBridge	146:22da6e220af6	505
AnnaBridge	146:22da6e220af6	506	#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) \|\| \
AnnaBridge	146:22da6e220af6	507	((SIZE) == SDIO_DATABLOCK_SIZE_2B) \|\| \
AnnaBridge	146:22da6e220af6	508	((SIZE) == SDIO_DATABLOCK_SIZE_4B) \|\| \
AnnaBridge	146:22da6e220af6	509	((SIZE) == SDIO_DATABLOCK_SIZE_8B) \|\| \
AnnaBridge	146:22da6e220af6	510	((SIZE) == SDIO_DATABLOCK_SIZE_16B) \|\| \
AnnaBridge	146:22da6e220af6	511	((SIZE) == SDIO_DATABLOCK_SIZE_32B) \|\| \
AnnaBridge	146:22da6e220af6	512	((SIZE) == SDIO_DATABLOCK_SIZE_64B) \|\| \
AnnaBridge	146:22da6e220af6	513	((SIZE) == SDIO_DATABLOCK_SIZE_128B) \|\| \
AnnaBridge	146:22da6e220af6	514	((SIZE) == SDIO_DATABLOCK_SIZE_256B) \|\| \
AnnaBridge	146:22da6e220af6	515	((SIZE) == SDIO_DATABLOCK_SIZE_512B) \|\| \
AnnaBridge	146:22da6e220af6	516	((SIZE) == SDIO_DATABLOCK_SIZE_1024B) \|\| \
AnnaBridge	146:22da6e220af6	517	((SIZE) == SDIO_DATABLOCK_SIZE_2048B) \|\| \
AnnaBridge	146:22da6e220af6	518	((SIZE) == SDIO_DATABLOCK_SIZE_4096B) \|\| \
AnnaBridge	146:22da6e220af6	519	((SIZE) == SDIO_DATABLOCK_SIZE_8192B) \|\| \
AnnaBridge	146:22da6e220af6	520	((SIZE) == SDIO_DATABLOCK_SIZE_16384B))
AnnaBridge	146:22da6e220af6	521	/**
AnnaBridge	146:22da6e220af6	522	* @}
AnnaBridge	146:22da6e220af6	523	*/
AnnaBridge	146:22da6e220af6	524
AnnaBridge	146:22da6e220af6	525	/** @defgroup SDIO_LL_Transfer_Direction Transfer Direction
AnnaBridge	146:22da6e220af6	526	* @{
AnnaBridge	146:22da6e220af6	527	*/
AnnaBridge	146:22da6e220af6	528	#define SDIO_TRANSFER_DIR_TO_CARD 0x00000000U
AnnaBridge	146:22da6e220af6	529	#define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR
AnnaBridge	146:22da6e220af6	530
AnnaBridge	146:22da6e220af6	531	#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) \|\| \
AnnaBridge	146:22da6e220af6	532	((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
AnnaBridge	146:22da6e220af6	533	/**
AnnaBridge	146:22da6e220af6	534	* @}
AnnaBridge	146:22da6e220af6	535	*/
AnnaBridge	146:22da6e220af6	536
AnnaBridge	146:22da6e220af6	537	/** @defgroup SDIO_LL_Transfer_Type Transfer Type
AnnaBridge	146:22da6e220af6	538	* @{
AnnaBridge	146:22da6e220af6	539	*/
AnnaBridge	146:22da6e220af6	540	#define SDIO_TRANSFER_MODE_BLOCK 0x00000000U
AnnaBridge	146:22da6e220af6	541	#define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE
AnnaBridge	146:22da6e220af6	542
AnnaBridge	146:22da6e220af6	543	#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) \|\| \
AnnaBridge	146:22da6e220af6	544	((MODE) == SDIO_TRANSFER_MODE_STREAM))
AnnaBridge	146:22da6e220af6	545	/**
AnnaBridge	146:22da6e220af6	546	* @}
AnnaBridge	146:22da6e220af6	547	*/
AnnaBridge	146:22da6e220af6	548
AnnaBridge	146:22da6e220af6	549	/** @defgroup SDIO_LL_DPSM_State DPSM State
AnnaBridge	146:22da6e220af6	550	* @{
AnnaBridge	146:22da6e220af6	551	*/
AnnaBridge	146:22da6e220af6	552	#define SDIO_DPSM_DISABLE 0x00000000U
AnnaBridge	146:22da6e220af6	553	#define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN
AnnaBridge	146:22da6e220af6	554
AnnaBridge	146:22da6e220af6	555	#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) \|\|\
AnnaBridge	146:22da6e220af6	556	((DPSM) == SDIO_DPSM_ENABLE))
AnnaBridge	146:22da6e220af6	557	/**
AnnaBridge	146:22da6e220af6	558	* @}
AnnaBridge	146:22da6e220af6	559	*/
AnnaBridge	146:22da6e220af6	560
AnnaBridge	146:22da6e220af6	561	/** @defgroup SDIO_LL_Read_Wait_Mode Read Wait Mode
AnnaBridge	146:22da6e220af6	562	* @{
AnnaBridge	146:22da6e220af6	563	*/
AnnaBridge	146:22da6e220af6	564	#define SDIO_READ_WAIT_MODE_DATA2 0x00000000U
AnnaBridge	146:22da6e220af6	565	#define SDIO_READ_WAIT_MODE_CLK (SDIO_DCTRL_RWMOD)
AnnaBridge	146:22da6e220af6	566
AnnaBridge	146:22da6e220af6	567	#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) \|\| \
AnnaBridge	146:22da6e220af6	568	((MODE) == SDIO_READ_WAIT_MODE_DATA2))
AnnaBridge	146:22da6e220af6	569	/**
AnnaBridge	146:22da6e220af6	570	* @}
AnnaBridge	146:22da6e220af6	571	*/
AnnaBridge	146:22da6e220af6	572
AnnaBridge	146:22da6e220af6	573	/** @defgroup SDIO_LL_Interrupt_sources Interrupt Sources
AnnaBridge	146:22da6e220af6	574	* @{
AnnaBridge	146:22da6e220af6	575	*/
AnnaBridge	146:22da6e220af6	576	#define SDIO_IT_CCRCFAIL SDIO_STA_CCRCFAIL
AnnaBridge	146:22da6e220af6	577	#define SDIO_IT_DCRCFAIL SDIO_STA_DCRCFAIL
AnnaBridge	146:22da6e220af6	578	#define SDIO_IT_CTIMEOUT SDIO_STA_CTIMEOUT
AnnaBridge	146:22da6e220af6	579	#define SDIO_IT_DTIMEOUT SDIO_STA_DTIMEOUT
AnnaBridge	146:22da6e220af6	580	#define SDIO_IT_TXUNDERR SDIO_STA_TXUNDERR
AnnaBridge	146:22da6e220af6	581	#define SDIO_IT_RXOVERR SDIO_STA_RXOVERR
AnnaBridge	146:22da6e220af6	582	#define SDIO_IT_CMDREND SDIO_STA_CMDREND
AnnaBridge	146:22da6e220af6	583	#define SDIO_IT_CMDSENT SDIO_STA_CMDSENT
AnnaBridge	146:22da6e220af6	584	#define SDIO_IT_DATAEND SDIO_STA_DATAEND
AnnaBridge	146:22da6e220af6	585	#define SDIO_IT_STBITERR SDIO_STA_STBITERR
AnnaBridge	146:22da6e220af6	586	#define SDIO_IT_DBCKEND SDIO_STA_DBCKEND
AnnaBridge	146:22da6e220af6	587	#define SDIO_IT_CMDACT SDIO_STA_CMDACT
AnnaBridge	146:22da6e220af6	588	#define SDIO_IT_TXACT SDIO_STA_TXACT
AnnaBridge	146:22da6e220af6	589	#define SDIO_IT_RXACT SDIO_STA_RXACT
AnnaBridge	146:22da6e220af6	590	#define SDIO_IT_TXFIFOHE SDIO_STA_TXFIFOHE
AnnaBridge	146:22da6e220af6	591	#define SDIO_IT_RXFIFOHF SDIO_STA_RXFIFOHF
AnnaBridge	146:22da6e220af6	592	#define SDIO_IT_TXFIFOF SDIO_STA_TXFIFOF
AnnaBridge	146:22da6e220af6	593	#define SDIO_IT_RXFIFOF SDIO_STA_RXFIFOF
AnnaBridge	146:22da6e220af6	594	#define SDIO_IT_TXFIFOE SDIO_STA_TXFIFOE
AnnaBridge	146:22da6e220af6	595	#define SDIO_IT_RXFIFOE SDIO_STA_RXFIFOE
AnnaBridge	146:22da6e220af6	596	#define SDIO_IT_TXDAVL SDIO_STA_TXDAVL
AnnaBridge	146:22da6e220af6	597	#define SDIO_IT_RXDAVL SDIO_STA_RXDAVL
AnnaBridge	146:22da6e220af6	598	#define SDIO_IT_SDIOIT SDIO_STA_SDIOIT
AnnaBridge	146:22da6e220af6	599	#define SDIO_IT_CEATAEND SDIO_STA_CEATAEND
AnnaBridge	146:22da6e220af6	600	/**
AnnaBridge	146:22da6e220af6	601	* @}
AnnaBridge	146:22da6e220af6	602	*/
AnnaBridge	146:22da6e220af6	603
AnnaBridge	146:22da6e220af6	604	/** @defgroup SDIO_LL_Flags Flags
AnnaBridge	146:22da6e220af6	605	* @{
AnnaBridge	146:22da6e220af6	606	*/
AnnaBridge	146:22da6e220af6	607	#define SDIO_FLAG_CCRCFAIL SDIO_STA_CCRCFAIL
AnnaBridge	146:22da6e220af6	608	#define SDIO_FLAG_DCRCFAIL SDIO_STA_DCRCFAIL
AnnaBridge	146:22da6e220af6	609	#define SDIO_FLAG_CTIMEOUT SDIO_STA_CTIMEOUT
AnnaBridge	146:22da6e220af6	610	#define SDIO_FLAG_DTIMEOUT SDIO_STA_DTIMEOUT
AnnaBridge	146:22da6e220af6	611	#define SDIO_FLAG_TXUNDERR SDIO_STA_TXUNDERR
AnnaBridge	146:22da6e220af6	612	#define SDIO_FLAG_RXOVERR SDIO_STA_RXOVERR
AnnaBridge	146:22da6e220af6	613	#define SDIO_FLAG_CMDREND SDIO_STA_CMDREND
AnnaBridge	146:22da6e220af6	614	#define SDIO_FLAG_CMDSENT SDIO_STA_CMDSENT
AnnaBridge	146:22da6e220af6	615	#define SDIO_FLAG_DATAEND SDIO_STA_DATAEND
AnnaBridge	146:22da6e220af6	616	#define SDIO_FLAG_STBITERR SDIO_STA_STBITERR
AnnaBridge	146:22da6e220af6	617	#define SDIO_FLAG_DBCKEND SDIO_STA_DBCKEND
AnnaBridge	146:22da6e220af6	618	#define SDIO_FLAG_CMDACT SDIO_STA_CMDACT
AnnaBridge	146:22da6e220af6	619	#define SDIO_FLAG_TXACT SDIO_STA_TXACT
AnnaBridge	146:22da6e220af6	620	#define SDIO_FLAG_RXACT SDIO_STA_RXACT
AnnaBridge	146:22da6e220af6	621	#define SDIO_FLAG_TXFIFOHE SDIO_STA_TXFIFOHE
AnnaBridge	146:22da6e220af6	622	#define SDIO_FLAG_RXFIFOHF SDIO_STA_RXFIFOHF
AnnaBridge	146:22da6e220af6	623	#define SDIO_FLAG_TXFIFOF SDIO_STA_TXFIFOF
AnnaBridge	146:22da6e220af6	624	#define SDIO_FLAG_RXFIFOF SDIO_STA_RXFIFOF
AnnaBridge	146:22da6e220af6	625	#define SDIO_FLAG_TXFIFOE SDIO_STA_TXFIFOE
AnnaBridge	146:22da6e220af6	626	#define SDIO_FLAG_RXFIFOE SDIO_STA_RXFIFOE
AnnaBridge	146:22da6e220af6	627	#define SDIO_FLAG_TXDAVL SDIO_STA_TXDAVL
AnnaBridge	146:22da6e220af6	628	#define SDIO_FLAG_RXDAVL SDIO_STA_RXDAVL
AnnaBridge	146:22da6e220af6	629	#define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT
AnnaBridge	146:22da6e220af6	630	#define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND
AnnaBridge	146:22da6e220af6	631	#define SDIO_STATIC_FLAGS ((uint32_t)(SDIO_FLAG_CCRCFAIL \| SDIO_FLAG_DCRCFAIL \| SDIO_FLAG_CTIMEOUT \|\
AnnaBridge	146:22da6e220af6	632	SDIO_FLAG_DTIMEOUT \| SDIO_FLAG_TXUNDERR \| SDIO_FLAG_RXOVERR \|\
AnnaBridge	146:22da6e220af6	633	SDIO_FLAG_CMDREND \| SDIO_FLAG_CMDSENT \| SDIO_FLAG_DATAEND \|\
AnnaBridge	146:22da6e220af6	634	SDIO_FLAG_DBCKEND))
AnnaBridge	146:22da6e220af6	635	/**
AnnaBridge	146:22da6e220af6	636	* @}
AnnaBridge	146:22da6e220af6	637	*/
AnnaBridge	146:22da6e220af6	638
AnnaBridge	146:22da6e220af6	639	/**
AnnaBridge	146:22da6e220af6	640	* @}
AnnaBridge	146:22da6e220af6	641	*/
AnnaBridge	146:22da6e220af6	642
AnnaBridge	146:22da6e220af6	643	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	146:22da6e220af6	644	/** @defgroup SDIO_LL_Exported_macros SDIO_LL Exported Macros
AnnaBridge	146:22da6e220af6	645	* @{
AnnaBridge	146:22da6e220af6	646	*/
AnnaBridge	146:22da6e220af6	647
AnnaBridge	146:22da6e220af6	648	/** @defgroup SDMMC_LL_Alias_Region Bit Address in the alias region
AnnaBridge	146:22da6e220af6	649	* @{
AnnaBridge	146:22da6e220af6	650	*/
AnnaBridge	146:22da6e220af6	651	/* ------------ SDIO registers bit address in the alias region -------------- */
AnnaBridge	146:22da6e220af6	652	#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
AnnaBridge	146:22da6e220af6	653
AnnaBridge	146:22da6e220af6	654	/* --- CLKCR Register ---*/
AnnaBridge	146:22da6e220af6	655	/* Alias word address of CLKEN bit */
AnnaBridge	146:22da6e220af6	656	#define CLKCR_OFFSET (SDIO_OFFSET + 0x04U)
AnnaBridge	146:22da6e220af6	657	#define CLKEN_BITNUMBER 0x08U
AnnaBridge	146:22da6e220af6	658	#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32U) + (CLKEN_BITNUMBER * 4U))
AnnaBridge	146:22da6e220af6	659
AnnaBridge	146:22da6e220af6	660	/* --- CMD Register ---*/
AnnaBridge	146:22da6e220af6	661	/* Alias word address of SDIOSUSPEND bit */
AnnaBridge	146:22da6e220af6	662	#define CMD_OFFSET (SDIO_OFFSET + 0x0CU)
AnnaBridge	146:22da6e220af6	663	#define SDIOSUSPEND_BITNUMBER 0x0BU
AnnaBridge	146:22da6e220af6	664	#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (SDIOSUSPEND_BITNUMBER * 4U))
AnnaBridge	146:22da6e220af6	665
AnnaBridge	146:22da6e220af6	666	/* Alias word address of ENCMDCOMPL bit */
AnnaBridge	146:22da6e220af6	667	#define ENCMDCOMPL_BITNUMBER 0x0CU
AnnaBridge	146:22da6e220af6	668	#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ENCMDCOMPL_BITNUMBER * 4U))
AnnaBridge	146:22da6e220af6	669
AnnaBridge	146:22da6e220af6	670	/* Alias word address of NIEN bit */
AnnaBridge	146:22da6e220af6	671	#define NIEN_BITNUMBER 0x0DU
AnnaBridge	146:22da6e220af6	672	#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (NIEN_BITNUMBER * 4U))
AnnaBridge	146:22da6e220af6	673
AnnaBridge	146:22da6e220af6	674	/* Alias word address of ATACMD bit */
AnnaBridge	146:22da6e220af6	675	#define ATACMD_BITNUMBER 0x0EU
AnnaBridge	146:22da6e220af6	676	#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ATACMD_BITNUMBER * 4U))
AnnaBridge	146:22da6e220af6	677
AnnaBridge	146:22da6e220af6	678	/* --- DCTRL Register ---*/
AnnaBridge	146:22da6e220af6	679	/* Alias word address of DMAEN bit */
AnnaBridge	146:22da6e220af6	680	#define DCTRL_OFFSET (SDIO_OFFSET + 0x2CU)
AnnaBridge	146:22da6e220af6	681	#define DMAEN_BITNUMBER 0x03U
AnnaBridge	146:22da6e220af6	682	#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (DMAEN_BITNUMBER * 4U))
AnnaBridge	146:22da6e220af6	683
AnnaBridge	146:22da6e220af6	684	/* Alias word address of RWSTART bit */
AnnaBridge	146:22da6e220af6	685	#define RWSTART_BITNUMBER 0x08U
AnnaBridge	146:22da6e220af6	686	#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTART_BITNUMBER * 4U))
AnnaBridge	146:22da6e220af6	687
AnnaBridge	146:22da6e220af6	688	/* Alias word address of RWSTOP bit */
AnnaBridge	146:22da6e220af6	689	#define RWSTOP_BITNUMBER 0x09U
AnnaBridge	146:22da6e220af6	690	#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTOP_BITNUMBER * 4U))
AnnaBridge	146:22da6e220af6	691
AnnaBridge	146:22da6e220af6	692	/* Alias word address of RWMOD bit */
AnnaBridge	146:22da6e220af6	693	#define RWMOD_BITNUMBER 0x0AU
AnnaBridge	146:22da6e220af6	694	#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWMOD_BITNUMBER * 4U))
AnnaBridge	146:22da6e220af6	695
AnnaBridge	146:22da6e220af6	696	/* Alias word address of SDIOEN bit */
AnnaBridge	146:22da6e220af6	697	#define SDIOEN_BITNUMBER 0x0BU
AnnaBridge	146:22da6e220af6	698	#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (SDIOEN_BITNUMBER * 4U))
AnnaBridge	146:22da6e220af6	699	/**
AnnaBridge	146:22da6e220af6	700	* @}
AnnaBridge	146:22da6e220af6	701	*/
AnnaBridge	146:22da6e220af6	702
AnnaBridge	146:22da6e220af6	703	/** @defgroup SDIO_LL_Register Bits And Addresses Definitions
AnnaBridge	146:22da6e220af6	704	* @brief SDIO_LL registers bit address in the alias region
AnnaBridge	146:22da6e220af6	705	* @{
AnnaBridge	146:22da6e220af6	706	*/
AnnaBridge	146:22da6e220af6	707	/* ---------------------- SDIO registers bit mask --------------------------- */
AnnaBridge	146:22da6e220af6	708	/* --- CLKCR Register ---*/
AnnaBridge	146:22da6e220af6	709	/* CLKCR register clear mask */
AnnaBridge	146:22da6e220af6	710	#define CLKCR_CLEAR_MASK ((uint32_t)(SDIO_CLKCR_CLKDIV \| SDIO_CLKCR_PWRSAV \|\
AnnaBridge	146:22da6e220af6	711	SDIO_CLKCR_BYPASS \| SDIO_CLKCR_WIDBUS \|\
AnnaBridge	146:22da6e220af6	712	SDIO_CLKCR_NEGEDGE \| SDIO_CLKCR_HWFC_EN))
AnnaBridge	146:22da6e220af6	713
AnnaBridge	146:22da6e220af6	714	/* --- DCTRL Register ---*/
AnnaBridge	146:22da6e220af6	715	/* SDIO DCTRL Clear Mask */
AnnaBridge	146:22da6e220af6	716	#define DCTRL_CLEAR_MASK ((uint32_t)(SDIO_DCTRL_DTEN \| SDIO_DCTRL_DTDIR \|\
AnnaBridge	146:22da6e220af6	717	SDIO_DCTRL_DTMODE \| SDIO_DCTRL_DBLOCKSIZE))
AnnaBridge	146:22da6e220af6	718
AnnaBridge	146:22da6e220af6	719	/* --- CMD Register ---*/
AnnaBridge	146:22da6e220af6	720	/* CMD Register clear mask */
AnnaBridge	146:22da6e220af6	721	#define CMD_CLEAR_MASK ((uint32_t)(SDIO_CMD_CMDINDEX \| SDIO_CMD_WAITRESP \|\
AnnaBridge	146:22da6e220af6	722	SDIO_CMD_WAITINT \| SDIO_CMD_WAITPEND \|\
AnnaBridge	146:22da6e220af6	723	SDIO_CMD_CPSMEN \| SDIO_CMD_SDIOSUSPEND))
AnnaBridge	146:22da6e220af6	724
AnnaBridge	146:22da6e220af6	725	/* SDIO Initialization Frequency (400KHz max) */
AnnaBridge	146:22da6e220af6	726	#define SDIO_INIT_CLK_DIV ((uint8_t)0x76)
AnnaBridge	146:22da6e220af6	727
AnnaBridge	146:22da6e220af6	728	/* SDIO Data Transfer Frequency (25MHz max) */
AnnaBridge	146:22da6e220af6	729	#define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x0)
AnnaBridge	146:22da6e220af6	730
AnnaBridge	146:22da6e220af6	731	/**
AnnaBridge	146:22da6e220af6	732	* @}
AnnaBridge	146:22da6e220af6	733	*/
AnnaBridge	146:22da6e220af6	734
AnnaBridge	146:22da6e220af6	735	/** @defgroup SDIO_LL_Interrupt_Clock Interrupt And Clock Configuration
AnnaBridge	146:22da6e220af6	736	* @brief macros to handle interrupts and specific clock configurations
AnnaBridge	146:22da6e220af6	737	* @{
AnnaBridge	146:22da6e220af6	738	*/
AnnaBridge	146:22da6e220af6	739
AnnaBridge	146:22da6e220af6	740	/**
AnnaBridge	146:22da6e220af6	741	* @brief Enable the SDIO device.
AnnaBridge	146:22da6e220af6	742	* @param __INSTANCE__: SDIO Instance
AnnaBridge	146:22da6e220af6	743	* @retval None
AnnaBridge	146:22da6e220af6	744	*/
AnnaBridge	146:22da6e220af6	745	#define __SDIO_ENABLE(__INSTANCE__) ((__IO uint32_t )CLKCR_CLKEN_BB = ENABLE)
AnnaBridge	146:22da6e220af6	746
AnnaBridge	146:22da6e220af6	747	/**
AnnaBridge	146:22da6e220af6	748	* @brief Disable the SDIO device.
AnnaBridge	146:22da6e220af6	749	* @param __INSTANCE__: SDIO Instance
AnnaBridge	146:22da6e220af6	750	* @retval None
AnnaBridge	146:22da6e220af6	751	*/
AnnaBridge	146:22da6e220af6	752	#define __SDIO_DISABLE(__INSTANCE__) ((__IO uint32_t )CLKCR_CLKEN_BB = DISABLE)
AnnaBridge	146:22da6e220af6	753
AnnaBridge	146:22da6e220af6	754	/**
AnnaBridge	146:22da6e220af6	755	* @brief Enable the SDIO DMA transfer.
AnnaBridge	146:22da6e220af6	756	* @param __INSTANCE__: SDIO Instance
AnnaBridge	146:22da6e220af6	757	* @retval None
AnnaBridge	146:22da6e220af6	758	*/
AnnaBridge	146:22da6e220af6	759	#define __SDIO_DMA_ENABLE(__INSTANCE__) ((__IO uint32_t )DCTRL_DMAEN_BB = ENABLE)
AnnaBridge	146:22da6e220af6	760	/**
AnnaBridge	146:22da6e220af6	761	* @brief Disable the SDIO DMA transfer.
AnnaBridge	146:22da6e220af6	762	* @param __INSTANCE__: SDIO Instance
AnnaBridge	146:22da6e220af6	763	* @retval None
AnnaBridge	146:22da6e220af6	764	*/
AnnaBridge	146:22da6e220af6	765	#define __SDIO_DMA_DISABLE(__INSTANCE__) ((__IO uint32_t )DCTRL_DMAEN_BB = DISABLE)
AnnaBridge	146:22da6e220af6	766
AnnaBridge	146:22da6e220af6	767	/**
AnnaBridge	146:22da6e220af6	768	* @brief Enable the SDIO device interrupt.
AnnaBridge	146:22da6e220af6	769	* @param __INSTANCE__ : Pointer to SDIO register base
AnnaBridge	146:22da6e220af6	770	* @param __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled.
AnnaBridge	146:22da6e220af6	771	* This parameter can be one or a combination of the following values:
AnnaBridge	146:22da6e220af6	772	* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
AnnaBridge	146:22da6e220af6	773	* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
AnnaBridge	146:22da6e220af6	774	* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
AnnaBridge	146:22da6e220af6	775	* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
AnnaBridge	146:22da6e220af6	776	* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
AnnaBridge	146:22da6e220af6	777	* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
AnnaBridge	146:22da6e220af6	778	* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
AnnaBridge	146:22da6e220af6	779	* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
AnnaBridge	146:22da6e220af6	780	* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
AnnaBridge	146:22da6e220af6	781	* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
AnnaBridge	146:22da6e220af6	782	* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
AnnaBridge	146:22da6e220af6	783	* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
AnnaBridge	146:22da6e220af6	784	* @arg SDIO_IT_RXACT: Data receive in progress interrupt
AnnaBridge	146:22da6e220af6	785	* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
AnnaBridge	146:22da6e220af6	786	* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
AnnaBridge	146:22da6e220af6	787	* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
AnnaBridge	146:22da6e220af6	788	* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
AnnaBridge	146:22da6e220af6	789	* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
AnnaBridge	146:22da6e220af6	790	* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
AnnaBridge	146:22da6e220af6	791	* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
AnnaBridge	146:22da6e220af6	792	* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
AnnaBridge	146:22da6e220af6	793	* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
AnnaBridge	146:22da6e220af6	794	* @retval None
AnnaBridge	146:22da6e220af6	795	*/
AnnaBridge	146:22da6e220af6	796	#define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK \|= (__INTERRUPT__))
AnnaBridge	146:22da6e220af6	797
AnnaBridge	146:22da6e220af6	798	/**
AnnaBridge	146:22da6e220af6	799	* @brief Disable the SDIO device interrupt.
AnnaBridge	146:22da6e220af6	800	* @param __INSTANCE__ : Pointer to SDIO register base
AnnaBridge	146:22da6e220af6	801	* @param __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled.
AnnaBridge	146:22da6e220af6	802	* This parameter can be one or a combination of the following values:
AnnaBridge	146:22da6e220af6	803	* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
AnnaBridge	146:22da6e220af6	804	* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
AnnaBridge	146:22da6e220af6	805	* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
AnnaBridge	146:22da6e220af6	806	* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
AnnaBridge	146:22da6e220af6	807	* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
AnnaBridge	146:22da6e220af6	808	* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
AnnaBridge	146:22da6e220af6	809	* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
AnnaBridge	146:22da6e220af6	810	* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
AnnaBridge	146:22da6e220af6	811	* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
AnnaBridge	146:22da6e220af6	812	* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
AnnaBridge	146:22da6e220af6	813	* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
AnnaBridge	146:22da6e220af6	814	* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
AnnaBridge	146:22da6e220af6	815	* @arg SDIO_IT_RXACT: Data receive in progress interrupt
AnnaBridge	146:22da6e220af6	816	* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
AnnaBridge	146:22da6e220af6	817	* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
AnnaBridge	146:22da6e220af6	818	* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
AnnaBridge	146:22da6e220af6	819	* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
AnnaBridge	146:22da6e220af6	820	* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
AnnaBridge	146:22da6e220af6	821	* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
AnnaBridge	146:22da6e220af6	822	* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
AnnaBridge	146:22da6e220af6	823	* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
AnnaBridge	146:22da6e220af6	824	* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
AnnaBridge	146:22da6e220af6	825	* @retval None
AnnaBridge	146:22da6e220af6	826	*/
AnnaBridge	146:22da6e220af6	827	#define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
AnnaBridge	146:22da6e220af6	828
AnnaBridge	146:22da6e220af6	829	/**
AnnaBridge	146:22da6e220af6	830	* @brief Checks whether the specified SDIO flag is set or not.
AnnaBridge	146:22da6e220af6	831	* @param __INSTANCE__ : Pointer to SDIO register base
AnnaBridge	146:22da6e220af6	832	* @param __FLAG__: specifies the flag to check.
AnnaBridge	146:22da6e220af6	833	* This parameter can be one of the following values:
AnnaBridge	146:22da6e220af6	834	* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
AnnaBridge	146:22da6e220af6	835	* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
AnnaBridge	146:22da6e220af6	836	* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
AnnaBridge	146:22da6e220af6	837	* @arg SDIO_FLAG_DTIMEOUT: Data timeout
AnnaBridge	146:22da6e220af6	838	* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
AnnaBridge	146:22da6e220af6	839	* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
AnnaBridge	146:22da6e220af6	840	* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
AnnaBridge	146:22da6e220af6	841	* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
AnnaBridge	146:22da6e220af6	842	* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
AnnaBridge	146:22da6e220af6	843	* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
AnnaBridge	146:22da6e220af6	844	* @arg SDIO_FLAG_CMDACT: Command transfer in progress
AnnaBridge	146:22da6e220af6	845	* @arg SDIO_FLAG_TXACT: Data transmit in progress
AnnaBridge	146:22da6e220af6	846	* @arg SDIO_FLAG_RXACT: Data receive in progress
AnnaBridge	146:22da6e220af6	847	* @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
AnnaBridge	146:22da6e220af6	848	* @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
AnnaBridge	146:22da6e220af6	849	* @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
AnnaBridge	146:22da6e220af6	850	* @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
AnnaBridge	146:22da6e220af6	851	* @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
AnnaBridge	146:22da6e220af6	852	* @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
AnnaBridge	146:22da6e220af6	853	* @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
AnnaBridge	146:22da6e220af6	854	* @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
AnnaBridge	146:22da6e220af6	855	* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
AnnaBridge	146:22da6e220af6	856	* @retval The new state of SDIO_FLAG (SET or RESET).
AnnaBridge	146:22da6e220af6	857	*/
AnnaBridge	146:22da6e220af6	858	#define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
AnnaBridge	146:22da6e220af6	859
AnnaBridge	146:22da6e220af6	860
AnnaBridge	146:22da6e220af6	861	/**
AnnaBridge	146:22da6e220af6	862	* @brief Clears the SDIO pending flags.
AnnaBridge	146:22da6e220af6	863	* @param __INSTANCE__ : Pointer to SDIO register base
AnnaBridge	146:22da6e220af6	864	* @param __FLAG__: specifies the flag to clear.
AnnaBridge	146:22da6e220af6	865	* This parameter can be one or a combination of the following values:
AnnaBridge	146:22da6e220af6	866	* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
AnnaBridge	146:22da6e220af6	867	* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
AnnaBridge	146:22da6e220af6	868	* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
AnnaBridge	146:22da6e220af6	869	* @arg SDIO_FLAG_DTIMEOUT: Data timeout
AnnaBridge	146:22da6e220af6	870	* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
AnnaBridge	146:22da6e220af6	871	* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
AnnaBridge	146:22da6e220af6	872	* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
AnnaBridge	146:22da6e220af6	873	* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
AnnaBridge	146:22da6e220af6	874	* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
AnnaBridge	146:22da6e220af6	875	* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
AnnaBridge	146:22da6e220af6	876	* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
AnnaBridge	146:22da6e220af6	877	* @retval None
AnnaBridge	146:22da6e220af6	878	*/
AnnaBridge	146:22da6e220af6	879	#define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
AnnaBridge	146:22da6e220af6	880
AnnaBridge	146:22da6e220af6	881	/**
AnnaBridge	146:22da6e220af6	882	* @brief Checks whether the specified SDIO interrupt has occurred or not.
AnnaBridge	146:22da6e220af6	883	* @param __INSTANCE__ : Pointer to SDIO register base
AnnaBridge	146:22da6e220af6	884	* @param __INTERRUPT__: specifies the SDIO interrupt source to check.
AnnaBridge	146:22da6e220af6	885	* This parameter can be one of the following values:
AnnaBridge	146:22da6e220af6	886	* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
AnnaBridge	146:22da6e220af6	887	* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
AnnaBridge	146:22da6e220af6	888	* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
AnnaBridge	146:22da6e220af6	889	* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
AnnaBridge	146:22da6e220af6	890	* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
AnnaBridge	146:22da6e220af6	891	* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
AnnaBridge	146:22da6e220af6	892	* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
AnnaBridge	146:22da6e220af6	893	* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
AnnaBridge	146:22da6e220af6	894	* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
AnnaBridge	146:22da6e220af6	895	* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
AnnaBridge	146:22da6e220af6	896	* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
AnnaBridge	146:22da6e220af6	897	* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
AnnaBridge	146:22da6e220af6	898	* @arg SDIO_IT_RXACT: Data receive in progress interrupt
AnnaBridge	146:22da6e220af6	899	* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
AnnaBridge	146:22da6e220af6	900	* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
AnnaBridge	146:22da6e220af6	901	* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
AnnaBridge	146:22da6e220af6	902	* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
AnnaBridge	146:22da6e220af6	903	* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
AnnaBridge	146:22da6e220af6	904	* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
AnnaBridge	146:22da6e220af6	905	* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
AnnaBridge	146:22da6e220af6	906	* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
AnnaBridge	146:22da6e220af6	907	* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
AnnaBridge	146:22da6e220af6	908	* @retval The new state of SDIO_IT (SET or RESET).
AnnaBridge	146:22da6e220af6	909	*/
AnnaBridge	146:22da6e220af6	910	#define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
AnnaBridge	146:22da6e220af6	911
AnnaBridge	146:22da6e220af6	912	/**
AnnaBridge	146:22da6e220af6	913	* @brief Clears the SDIO's interrupt pending bits.
AnnaBridge	146:22da6e220af6	914	* @param __INSTANCE__ : Pointer to SDIO register base
AnnaBridge	146:22da6e220af6	915	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
AnnaBridge	146:22da6e220af6	916	* This parameter can be one or a combination of the following values:
AnnaBridge	146:22da6e220af6	917	* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
AnnaBridge	146:22da6e220af6	918	* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
AnnaBridge	146:22da6e220af6	919	* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
AnnaBridge	146:22da6e220af6	920	* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
AnnaBridge	146:22da6e220af6	921	* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
AnnaBridge	146:22da6e220af6	922	* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
AnnaBridge	146:22da6e220af6	923	* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
AnnaBridge	146:22da6e220af6	924	* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
AnnaBridge	146:22da6e220af6	925	* @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt
AnnaBridge	146:22da6e220af6	926	* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
AnnaBridge	146:22da6e220af6	927	* @retval None
AnnaBridge	146:22da6e220af6	928	*/
AnnaBridge	146:22da6e220af6	929	#define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
AnnaBridge	146:22da6e220af6	930
AnnaBridge	146:22da6e220af6	931	/**
AnnaBridge	146:22da6e220af6	932	* @brief Enable Start the SD I/O Read Wait operation.
AnnaBridge	146:22da6e220af6	933	* @param __INSTANCE__ : Pointer to SDIO register base
AnnaBridge	146:22da6e220af6	934	* @retval None
AnnaBridge	146:22da6e220af6	935	*/
AnnaBridge	146:22da6e220af6	936	#define __SDIO_START_READWAIT_ENABLE(__INSTANCE__) ((__IO uint32_t ) DCTRL_RWSTART_BB = ENABLE)
AnnaBridge	146:22da6e220af6	937
AnnaBridge	146:22da6e220af6	938	/**
AnnaBridge	146:22da6e220af6	939	* @brief Disable Start the SD I/O Read Wait operations.
AnnaBridge	146:22da6e220af6	940	* @param __INSTANCE__ : Pointer to SDIO register base
AnnaBridge	146:22da6e220af6	941	* @retval None
AnnaBridge	146:22da6e220af6	942	*/
AnnaBridge	146:22da6e220af6	943	#define __SDIO_START_READWAIT_DISABLE(__INSTANCE__) ((__IO uint32_t ) DCTRL_RWSTART_BB = DISABLE)
AnnaBridge	146:22da6e220af6	944
AnnaBridge	146:22da6e220af6	945	/**
AnnaBridge	146:22da6e220af6	946	* @brief Enable Start the SD I/O Read Wait operation.
AnnaBridge	146:22da6e220af6	947	* @param __INSTANCE__ : Pointer to SDIO register base
AnnaBridge	146:22da6e220af6	948	* @retval None
AnnaBridge	146:22da6e220af6	949	*/
AnnaBridge	146:22da6e220af6	950	#define __SDIO_STOP_READWAIT_ENABLE(__INSTANCE__) ((__IO uint32_t ) DCTRL_RWSTOP_BB = ENABLE)
AnnaBridge	146:22da6e220af6	951
AnnaBridge	146:22da6e220af6	952	/**
AnnaBridge	146:22da6e220af6	953	* @brief Disable Stop the SD I/O Read Wait operations.
AnnaBridge	146:22da6e220af6	954	* @param __INSTANCE__ : Pointer to SDIO register base
AnnaBridge	146:22da6e220af6	955	* @retval None
AnnaBridge	146:22da6e220af6	956	*/
AnnaBridge	146:22da6e220af6	957	#define __SDIO_STOP_READWAIT_DISABLE(__INSTANCE__) ((__IO uint32_t ) DCTRL_RWSTOP_BB = DISABLE)
AnnaBridge	146:22da6e220af6	958
AnnaBridge	146:22da6e220af6	959	/**
AnnaBridge	146:22da6e220af6	960	* @brief Enable the SD I/O Mode Operation.
AnnaBridge	146:22da6e220af6	961	* @param __INSTANCE__ : Pointer to SDIO register base
AnnaBridge	146:22da6e220af6	962	* @retval None
AnnaBridge	146:22da6e220af6	963	*/
AnnaBridge	146:22da6e220af6	964	#define __SDIO_OPERATION_ENABLE(__INSTANCE__) ((__IO uint32_t ) DCTRL_SDIOEN_BB = ENABLE)
AnnaBridge	146:22da6e220af6	965
AnnaBridge	146:22da6e220af6	966	/**
AnnaBridge	146:22da6e220af6	967	* @brief Disable the SD I/O Mode Operation.
AnnaBridge	146:22da6e220af6	968	* @param __INSTANCE__ : Pointer to SDIO register base
AnnaBridge	146:22da6e220af6	969	* @retval None
AnnaBridge	146:22da6e220af6	970	*/
AnnaBridge	146:22da6e220af6	971	#define __SDIO_OPERATION_DISABLE(__INSTANCE__) ((__IO uint32_t ) DCTRL_SDIOEN_BB = DISABLE)
AnnaBridge	146:22da6e220af6	972
AnnaBridge	146:22da6e220af6	973	/**
AnnaBridge	146:22da6e220af6	974	* @brief Enable the SD I/O Suspend command sending.
AnnaBridge	146:22da6e220af6	975	* @param __INSTANCE__ : Pointer to SDIO register base
AnnaBridge	146:22da6e220af6	976	* @retval None
AnnaBridge	146:22da6e220af6	977	*/
AnnaBridge	146:22da6e220af6	978	#define __SDIO_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__IO uint32_t ) CMD_SDIOSUSPEND_BB = ENABLE)
AnnaBridge	146:22da6e220af6	979
AnnaBridge	146:22da6e220af6	980	/**
AnnaBridge	146:22da6e220af6	981	* @brief Disable the SD I/O Suspend command sending.
AnnaBridge	146:22da6e220af6	982	* @param __INSTANCE__ : Pointer to SDIO register base
AnnaBridge	146:22da6e220af6	983	* @retval None
AnnaBridge	146:22da6e220af6	984	*/
AnnaBridge	146:22da6e220af6	985	#define __SDIO_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__IO uint32_t ) CMD_SDIOSUSPEND_BB = DISABLE)
AnnaBridge	146:22da6e220af6	986
AnnaBridge	146:22da6e220af6	987	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\|\
AnnaBridge	146:22da6e220af6	988	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
AnnaBridge	146:22da6e220af6	989	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
AnnaBridge	146:22da6e220af6	990	/**
AnnaBridge	146:22da6e220af6	991	* @brief Enable the command completion signal.
AnnaBridge	146:22da6e220af6	992	* @retval None
AnnaBridge	146:22da6e220af6	993	*/
AnnaBridge	146:22da6e220af6	994	#define __SDIO_CEATA_CMD_COMPLETION_ENABLE() ((__IO uint32_t ) CMD_ENCMDCOMPL_BB = ENABLE)
AnnaBridge	146:22da6e220af6	995
AnnaBridge	146:22da6e220af6	996	/**
AnnaBridge	146:22da6e220af6	997	* @brief Disable the command completion signal.
AnnaBridge	146:22da6e220af6	998	* @retval None
AnnaBridge	146:22da6e220af6	999	*/
AnnaBridge	146:22da6e220af6	1000	#define __SDIO_CEATA_CMD_COMPLETION_DISABLE() ((__IO uint32_t ) CMD_ENCMDCOMPL_BB = DISABLE)
AnnaBridge	146:22da6e220af6	1001
AnnaBridge	146:22da6e220af6	1002	/**
AnnaBridge	146:22da6e220af6	1003	* @brief Enable the CE-ATA interrupt.
AnnaBridge	146:22da6e220af6	1004	* @retval None
AnnaBridge	146:22da6e220af6	1005	*/
AnnaBridge	146:22da6e220af6	1006	#define __SDIO_CEATA_ENABLE_IT() ((__IO uint32_t ) CMD_NIEN_BB = (uint32_t)0U)
AnnaBridge	146:22da6e220af6	1007
AnnaBridge	146:22da6e220af6	1008	/**
AnnaBridge	146:22da6e220af6	1009	* @brief Disable the CE-ATA interrupt.
AnnaBridge	146:22da6e220af6	1010	* @retval None
AnnaBridge	146:22da6e220af6	1011	*/
AnnaBridge	146:22da6e220af6	1012	#define __SDIO_CEATA_DISABLE_IT() ((__IO uint32_t ) CMD_NIEN_BB = (uint32_t)1U)
AnnaBridge	146:22da6e220af6	1013
AnnaBridge	146:22da6e220af6	1014	/**
AnnaBridge	146:22da6e220af6	1015	* @brief Enable send CE-ATA command (CMD61).
AnnaBridge	146:22da6e220af6	1016	* @retval None
AnnaBridge	146:22da6e220af6	1017	*/
AnnaBridge	146:22da6e220af6	1018	#define __SDIO_CEATA_SENDCMD_ENABLE() ((__IO uint32_t ) CMD_ATACMD_BB = ENABLE)
AnnaBridge	146:22da6e220af6	1019
AnnaBridge	146:22da6e220af6	1020	/**
AnnaBridge	146:22da6e220af6	1021	* @brief Disable send CE-ATA command (CMD61).
AnnaBridge	146:22da6e220af6	1022	* @retval None
AnnaBridge	146:22da6e220af6	1023	*/
AnnaBridge	146:22da6e220af6	1024	#define __SDIO_CEATA_SENDCMD_DISABLE() ((__IO uint32_t ) CMD_ATACMD_BB = DISABLE)
AnnaBridge	146:22da6e220af6	1025	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\|\
AnnaBridge	146:22da6e220af6	1026	STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
AnnaBridge	146:22da6e220af6	1027
AnnaBridge	146:22da6e220af6	1028	/**
AnnaBridge	146:22da6e220af6	1029	* @}
AnnaBridge	146:22da6e220af6	1030	*/
AnnaBridge	146:22da6e220af6	1031
AnnaBridge	146:22da6e220af6	1032	/**
AnnaBridge	146:22da6e220af6	1033	* @}
AnnaBridge	146:22da6e220af6	1034	*/
AnnaBridge	146:22da6e220af6	1035
AnnaBridge	146:22da6e220af6	1036	/* Exported functions --------------------------------------------------------*/
AnnaBridge	146:22da6e220af6	1037	/** @addtogroup SDMMC_LL_Exported_Functions
AnnaBridge	146:22da6e220af6	1038	* @{
AnnaBridge	146:22da6e220af6	1039	*/
AnnaBridge	146:22da6e220af6	1040
AnnaBridge	146:22da6e220af6	1041	/* Initialization/de-initialization functions **********************************/
AnnaBridge	146:22da6e220af6	1042	/** @addtogroup HAL_SDMMC_LL_Group1
AnnaBridge	146:22da6e220af6	1043	* @{
AnnaBridge	146:22da6e220af6	1044	*/
AnnaBridge	146:22da6e220af6	1045	HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
AnnaBridge	146:22da6e220af6	1046	/**
AnnaBridge	146:22da6e220af6	1047	* @}
AnnaBridge	146:22da6e220af6	1048	*/
AnnaBridge	146:22da6e220af6	1049
AnnaBridge	146:22da6e220af6	1050	/* I/O operation functions *****************************************************/
AnnaBridge	146:22da6e220af6	1051	/** @addtogroup HAL_SDMMC_LL_Group2
AnnaBridge	146:22da6e220af6	1052	* @{
AnnaBridge	146:22da6e220af6	1053	*/
AnnaBridge	146:22da6e220af6	1054	uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx);
AnnaBridge	146:22da6e220af6	1055	HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef SDIOx, uint32_t pWriteData);
AnnaBridge	146:22da6e220af6	1056	/**
AnnaBridge	146:22da6e220af6	1057	* @}
AnnaBridge	146:22da6e220af6	1058	*/
AnnaBridge	146:22da6e220af6	1059
AnnaBridge	146:22da6e220af6	1060	/* Peripheral Control functions ************************************************/
AnnaBridge	146:22da6e220af6	1061	/** @addtogroup HAL_SDMMC_LL_Group3
AnnaBridge	146:22da6e220af6	1062	* @{
AnnaBridge	146:22da6e220af6	1063	*/
AnnaBridge	146:22da6e220af6	1064	HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);
AnnaBridge	146:22da6e220af6	1065	HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx);
AnnaBridge	146:22da6e220af6	1066	uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx);
AnnaBridge	146:22da6e220af6	1067
AnnaBridge	146:22da6e220af6	1068	/* Command path state machine (CPSM) management functions */
AnnaBridge	146:22da6e220af6	1069	HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef SDIOx, SDIO_CmdInitTypeDef Command);
AnnaBridge	146:22da6e220af6	1070	uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx);
AnnaBridge	146:22da6e220af6	1071	uint32_t SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response);
AnnaBridge	146:22da6e220af6	1072
AnnaBridge	146:22da6e220af6	1073	/* Data path state machine (DPSM) management functions */
AnnaBridge	146:22da6e220af6	1074	HAL_StatusTypeDef SDIO_ConfigData(SDIO_TypeDef SDIOx, SDIO_DataInitTypeDef Data);
AnnaBridge	146:22da6e220af6	1075	uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx);
AnnaBridge	146:22da6e220af6	1076	uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx);
AnnaBridge	146:22da6e220af6	1077
AnnaBridge	146:22da6e220af6	1078	/* SDMMC Cards mode management functions */
AnnaBridge	146:22da6e220af6	1079	HAL_StatusTypeDef SDIO_SetSDMMCReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode);
AnnaBridge	146:22da6e220af6	1080
AnnaBridge	146:22da6e220af6	1081	/* SDMMC Commands management functions */
AnnaBridge	146:22da6e220af6	1082	uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize);
AnnaBridge	146:22da6e220af6	1083	uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
AnnaBridge	146:22da6e220af6	1084	uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
AnnaBridge	146:22da6e220af6	1085	uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
AnnaBridge	146:22da6e220af6	1086	uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
AnnaBridge	146:22da6e220af6	1087	uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
AnnaBridge	146:22da6e220af6	1088	uint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
AnnaBridge	146:22da6e220af6	1089	uint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx);
AnnaBridge	146:22da6e220af6	1090	uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx);
AnnaBridge	146:22da6e220af6	1091	uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr);
AnnaBridge	146:22da6e220af6	1092	uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx);
AnnaBridge	146:22da6e220af6	1093	uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx);
AnnaBridge	146:22da6e220af6	1094	uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument);
AnnaBridge	146:22da6e220af6	1095	uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t SdType);
AnnaBridge	146:22da6e220af6	1096	uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth);
AnnaBridge	146:22da6e220af6	1097	uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx);
AnnaBridge	146:22da6e220af6	1098	uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx);
AnnaBridge	146:22da6e220af6	1099	uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument);
AnnaBridge	146:22da6e220af6	1100	uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef SDIOx, uint16_t pRCA);
AnnaBridge	146:22da6e220af6	1101	uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument);
AnnaBridge	146:22da6e220af6	1102	uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx);
AnnaBridge	146:22da6e220af6	1103
AnnaBridge	146:22da6e220af6	1104	uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument);
AnnaBridge	146:22da6e220af6	1105	uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument);
AnnaBridge	146:22da6e220af6	1106	uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
AnnaBridge	146:22da6e220af6	1107	uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
AnnaBridge	146:22da6e220af6	1108
AnnaBridge	146:22da6e220af6	1109	/**
AnnaBridge	146:22da6e220af6	1110	* @}
AnnaBridge	146:22da6e220af6	1111	*/
AnnaBridge	146:22da6e220af6	1112
AnnaBridge	146:22da6e220af6	1113	/**
AnnaBridge	146:22da6e220af6	1114	* @}
AnnaBridge	146:22da6e220af6	1115	*/
AnnaBridge	146:22da6e220af6	1116
AnnaBridge	146:22da6e220af6	1117	/**
AnnaBridge	146:22da6e220af6	1118	* @}
AnnaBridge	146:22da6e220af6	1119	*/
AnnaBridge	146:22da6e220af6	1120
AnnaBridge	146:22da6e220af6	1121	/**
AnnaBridge	146:22da6e220af6	1122	* @}
AnnaBridge	146:22da6e220af6	1123	*/
AnnaBridge	146:22da6e220af6	1124
AnnaBridge	146:22da6e220af6	1125	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
AnnaBridge	146:22da6e220af6	1126	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\|
AnnaBridge	146:22da6e220af6	1127	STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	146:22da6e220af6	1128
AnnaBridge	146:22da6e220af6	1129	#ifdef __cplusplus
AnnaBridge	146:22da6e220af6	1130	}
AnnaBridge	146:22da6e220af6	1131	#endif
AnnaBridge	146:22da6e220af6	1132
AnnaBridge	146:22da6e220af6	1133	#endif /* __STM32F4xx_LL_SDMMC_H */
AnnaBridge	146:22da6e220af6	1134
AnnaBridge	146:22da6e220af6	1135	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/