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TARGET_NUCLEO_L496ZG_P/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h@158:1c57384330a6, 2017-11-23 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 23 11:44:04 2017 +0000
Revision:
158:1c57384330a6
Child:
161:aa5281ff4a02
mbed library. Release version 156

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 158:1c57384330a6 1 /**
AnnaBridge 158:1c57384330a6 2 ******************************************************************************
AnnaBridge 158:1c57384330a6 3 * @file stm32l4xx_hal_rcc.h
AnnaBridge 158:1c57384330a6 4 * @author MCD Application Team
AnnaBridge 158:1c57384330a6 5 * @version V1.7.1
AnnaBridge 158:1c57384330a6 6 * @date 21-April-2017
AnnaBridge 158:1c57384330a6 7 * @brief Header file of RCC HAL module.
AnnaBridge 158:1c57384330a6 8 ******************************************************************************
AnnaBridge 158:1c57384330a6 9 * @attention
AnnaBridge 158:1c57384330a6 10 *
AnnaBridge 158:1c57384330a6 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 158:1c57384330a6 12 *
AnnaBridge 158:1c57384330a6 13 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 158:1c57384330a6 14 * are permitted provided that the following conditions are met:
AnnaBridge 158:1c57384330a6 15 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 158:1c57384330a6 16 * this list of conditions and the following disclaimer.
AnnaBridge 158:1c57384330a6 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 158:1c57384330a6 18 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 158:1c57384330a6 19 * and/or other materials provided with the distribution.
AnnaBridge 158:1c57384330a6 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 158:1c57384330a6 21 * may be used to endorse or promote products derived from this software
AnnaBridge 158:1c57384330a6 22 * without specific prior written permission.
AnnaBridge 158:1c57384330a6 23 *
AnnaBridge 158:1c57384330a6 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 158:1c57384330a6 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 158:1c57384330a6 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 158:1c57384330a6 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 158:1c57384330a6 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 158:1c57384330a6 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 158:1c57384330a6 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 158:1c57384330a6 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 158:1c57384330a6 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 158:1c57384330a6 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 158:1c57384330a6 34 *
AnnaBridge 158:1c57384330a6 35 ******************************************************************************
AnnaBridge 158:1c57384330a6 36 */
AnnaBridge 158:1c57384330a6 37
AnnaBridge 158:1c57384330a6 38 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 158:1c57384330a6 39 #ifndef __STM32L4xx_HAL_RCC_H
AnnaBridge 158:1c57384330a6 40 #define __STM32L4xx_HAL_RCC_H
AnnaBridge 158:1c57384330a6 41
AnnaBridge 158:1c57384330a6 42 #ifdef __cplusplus
AnnaBridge 158:1c57384330a6 43 extern "C" {
AnnaBridge 158:1c57384330a6 44 #endif
AnnaBridge 158:1c57384330a6 45
AnnaBridge 158:1c57384330a6 46 /* Includes ------------------------------------------------------------------*/
AnnaBridge 158:1c57384330a6 47 #include "stm32l4xx_hal_def.h"
AnnaBridge 158:1c57384330a6 48
AnnaBridge 158:1c57384330a6 49 /** @addtogroup STM32L4xx_HAL_Driver
AnnaBridge 158:1c57384330a6 50 * @{
AnnaBridge 158:1c57384330a6 51 */
AnnaBridge 158:1c57384330a6 52
AnnaBridge 158:1c57384330a6 53 /** @addtogroup RCC
AnnaBridge 158:1c57384330a6 54 * @{
AnnaBridge 158:1c57384330a6 55 */
AnnaBridge 158:1c57384330a6 56
AnnaBridge 158:1c57384330a6 57 /* Exported types ------------------------------------------------------------*/
AnnaBridge 158:1c57384330a6 58 /** @defgroup RCC_Exported_Types RCC Exported Types
AnnaBridge 158:1c57384330a6 59 * @{
AnnaBridge 158:1c57384330a6 60 */
AnnaBridge 158:1c57384330a6 61
AnnaBridge 158:1c57384330a6 62 /**
AnnaBridge 158:1c57384330a6 63 * @brief RCC PLL configuration structure definition
AnnaBridge 158:1c57384330a6 64 */
AnnaBridge 158:1c57384330a6 65 typedef struct
AnnaBridge 158:1c57384330a6 66 {
AnnaBridge 158:1c57384330a6 67 uint32_t PLLState; /*!< The new state of the PLL.
AnnaBridge 158:1c57384330a6 68 This parameter can be a value of @ref RCC_PLL_Config */
AnnaBridge 158:1c57384330a6 69
AnnaBridge 158:1c57384330a6 70 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
AnnaBridge 158:1c57384330a6 71 This parameter must be a value of @ref RCC_PLL_Clock_Source */
AnnaBridge 158:1c57384330a6 72
AnnaBridge 158:1c57384330a6 73 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
AnnaBridge 158:1c57384330a6 74 This parameter must be a number between Min_Data = 1 and Max_Data = 8 */
AnnaBridge 158:1c57384330a6 75
AnnaBridge 158:1c57384330a6 76 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
AnnaBridge 158:1c57384330a6 77 This parameter must be a number between Min_Data = 8 and Max_Data = 86 */
AnnaBridge 158:1c57384330a6 78
AnnaBridge 158:1c57384330a6 79 uint32_t PLLP; /*!< PLLP: Division factor for SAI clock.
AnnaBridge 158:1c57384330a6 80 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
AnnaBridge 158:1c57384330a6 81
AnnaBridge 158:1c57384330a6 82 uint32_t PLLQ; /*!< PLLQ: Division factor for SDMMC1, RNG and USB clocks.
AnnaBridge 158:1c57384330a6 83 This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */
AnnaBridge 158:1c57384330a6 84
AnnaBridge 158:1c57384330a6 85 uint32_t PLLR; /*!< PLLR: Division for the main system clock.
AnnaBridge 158:1c57384330a6 86 User have to set the PLLR parameter correctly to not exceed max frequency 80MHZ.
AnnaBridge 158:1c57384330a6 87 This parameter must be a value of @ref RCC_PLLR_Clock_Divider */
AnnaBridge 158:1c57384330a6 88
AnnaBridge 158:1c57384330a6 89 }RCC_PLLInitTypeDef;
AnnaBridge 158:1c57384330a6 90
AnnaBridge 158:1c57384330a6 91 /**
AnnaBridge 158:1c57384330a6 92 * @brief RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) configuration structure definition
AnnaBridge 158:1c57384330a6 93 */
AnnaBridge 158:1c57384330a6 94 typedef struct
AnnaBridge 158:1c57384330a6 95 {
AnnaBridge 158:1c57384330a6 96 uint32_t OscillatorType; /*!< The oscillators to be configured.
AnnaBridge 158:1c57384330a6 97 This parameter can be a value of @ref RCC_Oscillator_Type */
AnnaBridge 158:1c57384330a6 98
AnnaBridge 158:1c57384330a6 99 uint32_t HSEState; /*!< The new state of the HSE.
AnnaBridge 158:1c57384330a6 100 This parameter can be a value of @ref RCC_HSE_Config */
AnnaBridge 158:1c57384330a6 101
AnnaBridge 158:1c57384330a6 102 uint32_t LSEState; /*!< The new state of the LSE.
AnnaBridge 158:1c57384330a6 103 This parameter can be a value of @ref RCC_LSE_Config */
AnnaBridge 158:1c57384330a6 104
AnnaBridge 158:1c57384330a6 105 uint32_t HSIState; /*!< The new state of the HSI.
AnnaBridge 158:1c57384330a6 106 This parameter can be a value of @ref RCC_HSI_Config */
AnnaBridge 158:1c57384330a6 107
AnnaBridge 158:1c57384330a6 108 uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
AnnaBridge 158:1c57384330a6 109 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F on STM32L43x/STM32L44x/STM32L47x/STM32L48x devices.
AnnaBridge 158:1c57384330a6 110 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F on the other devices */
AnnaBridge 158:1c57384330a6 111
AnnaBridge 158:1c57384330a6 112 uint32_t LSIState; /*!< The new state of the LSI.
AnnaBridge 158:1c57384330a6 113 This parameter can be a value of @ref RCC_LSI_Config */
AnnaBridge 158:1c57384330a6 114
AnnaBridge 158:1c57384330a6 115 uint32_t MSIState; /*!< The new state of the MSI.
AnnaBridge 158:1c57384330a6 116 This parameter can be a value of @ref RCC_MSI_Config */
AnnaBridge 158:1c57384330a6 117
AnnaBridge 158:1c57384330a6 118 uint32_t MSICalibrationValue; /*!< The calibration trimming value (default is RCC_MSICALIBRATION_DEFAULT).
AnnaBridge 158:1c57384330a6 119 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
AnnaBridge 158:1c57384330a6 120
AnnaBridge 158:1c57384330a6 121 uint32_t MSIClockRange; /*!< The MSI frequency range.
AnnaBridge 158:1c57384330a6 122 This parameter can be a value of @ref RCC_MSI_Clock_Range */
AnnaBridge 158:1c57384330a6 123
AnnaBridge 158:1c57384330a6 124 uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32L43x/STM32L44x/STM32L45x/STM32L46x/STM32L49x/STM32L4Ax devices).
AnnaBridge 158:1c57384330a6 125 This parameter can be a value of @ref RCC_HSI48_Config */
AnnaBridge 158:1c57384330a6 126
AnnaBridge 158:1c57384330a6 127 RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */
AnnaBridge 158:1c57384330a6 128
AnnaBridge 158:1c57384330a6 129 }RCC_OscInitTypeDef;
AnnaBridge 158:1c57384330a6 130
AnnaBridge 158:1c57384330a6 131 /**
AnnaBridge 158:1c57384330a6 132 * @brief RCC System, AHB and APB busses clock configuration structure definition
AnnaBridge 158:1c57384330a6 133 */
AnnaBridge 158:1c57384330a6 134 typedef struct
AnnaBridge 158:1c57384330a6 135 {
AnnaBridge 158:1c57384330a6 136 uint32_t ClockType; /*!< The clock to be configured.
AnnaBridge 158:1c57384330a6 137 This parameter can be a value of @ref RCC_System_Clock_Type */
AnnaBridge 158:1c57384330a6 138
AnnaBridge 158:1c57384330a6 139 uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK).
AnnaBridge 158:1c57384330a6 140 This parameter can be a value of @ref RCC_System_Clock_Source */
AnnaBridge 158:1c57384330a6 141
AnnaBridge 158:1c57384330a6 142 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
AnnaBridge 158:1c57384330a6 143 This parameter can be a value of @ref RCC_AHB_Clock_Source */
AnnaBridge 158:1c57384330a6 144
AnnaBridge 158:1c57384330a6 145 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
AnnaBridge 158:1c57384330a6 146 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
AnnaBridge 158:1c57384330a6 147
AnnaBridge 158:1c57384330a6 148 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
AnnaBridge 158:1c57384330a6 149 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
AnnaBridge 158:1c57384330a6 150
AnnaBridge 158:1c57384330a6 151 }RCC_ClkInitTypeDef;
AnnaBridge 158:1c57384330a6 152
AnnaBridge 158:1c57384330a6 153 /**
AnnaBridge 158:1c57384330a6 154 * @}
AnnaBridge 158:1c57384330a6 155 */
AnnaBridge 158:1c57384330a6 156
AnnaBridge 158:1c57384330a6 157 /* Exported constants --------------------------------------------------------*/
AnnaBridge 158:1c57384330a6 158 /** @defgroup RCC_Exported_Constants RCC Exported Constants
AnnaBridge 158:1c57384330a6 159 * @{
AnnaBridge 158:1c57384330a6 160 */
AnnaBridge 158:1c57384330a6 161
AnnaBridge 158:1c57384330a6 162 /** @defgroup RCC_Timeout_Value Timeout Values
AnnaBridge 158:1c57384330a6 163 * @{
AnnaBridge 158:1c57384330a6 164 */
AnnaBridge 158:1c57384330a6 165 #define RCC_DBP_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
AnnaBridge 158:1c57384330a6 166 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
AnnaBridge 158:1c57384330a6 167 /**
AnnaBridge 158:1c57384330a6 168 * @}
AnnaBridge 158:1c57384330a6 169 */
AnnaBridge 158:1c57384330a6 170
AnnaBridge 158:1c57384330a6 171 /** @defgroup RCC_Oscillator_Type Oscillator Type
AnnaBridge 158:1c57384330a6 172 * @{
AnnaBridge 158:1c57384330a6 173 */
AnnaBridge 158:1c57384330a6 174 #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U) /*!< Oscillator configuration unchanged */
AnnaBridge 158:1c57384330a6 175 #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U) /*!< HSE to configure */
AnnaBridge 158:1c57384330a6 176 #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U) /*!< HSI to configure */
AnnaBridge 158:1c57384330a6 177 #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U) /*!< LSE to configure */
AnnaBridge 158:1c57384330a6 178 #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U) /*!< LSI to configure */
AnnaBridge 158:1c57384330a6 179 #define RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010U) /*!< MSI to configure */
AnnaBridge 158:1c57384330a6 180 #if defined(RCC_HSI48_SUPPORT)
AnnaBridge 158:1c57384330a6 181 #define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020U) /*!< HSI48 to configure */
AnnaBridge 158:1c57384330a6 182 #endif /* RCC_HSI48_SUPPORT */
AnnaBridge 158:1c57384330a6 183 /**
AnnaBridge 158:1c57384330a6 184 * @}
AnnaBridge 158:1c57384330a6 185 */
AnnaBridge 158:1c57384330a6 186
AnnaBridge 158:1c57384330a6 187 /** @defgroup RCC_HSE_Config HSE Config
AnnaBridge 158:1c57384330a6 188 * @{
AnnaBridge 158:1c57384330a6 189 */
AnnaBridge 158:1c57384330a6 190 #define RCC_HSE_OFF ((uint32_t)0x00000000U) /*!< HSE clock deactivation */
AnnaBridge 158:1c57384330a6 191 #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */
AnnaBridge 158:1c57384330a6 192 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */
AnnaBridge 158:1c57384330a6 193 /**
AnnaBridge 158:1c57384330a6 194 * @}
AnnaBridge 158:1c57384330a6 195 */
AnnaBridge 158:1c57384330a6 196
AnnaBridge 158:1c57384330a6 197 /** @defgroup RCC_LSE_Config LSE Config
AnnaBridge 158:1c57384330a6 198 * @{
AnnaBridge 158:1c57384330a6 199 */
AnnaBridge 158:1c57384330a6 200 #define RCC_LSE_OFF ((uint32_t)0x00000000U) /*!< LSE clock deactivation */
AnnaBridge 158:1c57384330a6 201 #define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */
AnnaBridge 158:1c57384330a6 202 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */
AnnaBridge 158:1c57384330a6 203 /**
AnnaBridge 158:1c57384330a6 204 * @}
AnnaBridge 158:1c57384330a6 205 */
AnnaBridge 158:1c57384330a6 206
AnnaBridge 158:1c57384330a6 207 /** @defgroup RCC_HSI_Config HSI Config
AnnaBridge 158:1c57384330a6 208 * @{
AnnaBridge 158:1c57384330a6 209 */
AnnaBridge 158:1c57384330a6 210 #define RCC_HSI_OFF ((uint32_t)0x00000000U) /*!< HSI clock deactivation */
AnnaBridge 158:1c57384330a6 211 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */
AnnaBridge 158:1c57384330a6 212
AnnaBridge 158:1c57384330a6 213 #if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \
AnnaBridge 158:1c57384330a6 214 defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
AnnaBridge 158:1c57384330a6 215 #define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10U) /* Default HSI calibration trimming value */
AnnaBridge 158:1c57384330a6 216 #else
AnnaBridge 158:1c57384330a6 217 #define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x40U) /* Default HSI calibration trimming value */
AnnaBridge 158:1c57384330a6 218 #endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */
AnnaBridge 158:1c57384330a6 219 /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
AnnaBridge 158:1c57384330a6 220 /**
AnnaBridge 158:1c57384330a6 221 * @}
AnnaBridge 158:1c57384330a6 222 */
AnnaBridge 158:1c57384330a6 223
AnnaBridge 158:1c57384330a6 224 /** @defgroup RCC_LSI_Config LSI Config
AnnaBridge 158:1c57384330a6 225 * @{
AnnaBridge 158:1c57384330a6 226 */
AnnaBridge 158:1c57384330a6 227 #define RCC_LSI_OFF ((uint32_t)0x00000000U) /*!< LSI clock deactivation */
AnnaBridge 158:1c57384330a6 228 #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */
AnnaBridge 158:1c57384330a6 229 /**
AnnaBridge 158:1c57384330a6 230 * @}
AnnaBridge 158:1c57384330a6 231 */
AnnaBridge 158:1c57384330a6 232
AnnaBridge 158:1c57384330a6 233 /** @defgroup RCC_MSI_Config MSI Config
AnnaBridge 158:1c57384330a6 234 * @{
AnnaBridge 158:1c57384330a6 235 */
AnnaBridge 158:1c57384330a6 236 #define RCC_MSI_OFF ((uint32_t)0x00000000U) /*!< MSI clock deactivation */
AnnaBridge 158:1c57384330a6 237 #define RCC_MSI_ON RCC_CR_MSION /*!< MSI clock activation */
AnnaBridge 158:1c57384330a6 238
AnnaBridge 158:1c57384330a6 239 #define RCC_MSICALIBRATION_DEFAULT ((uint32_t)0) /*!< Default MSI calibration trimming value */
AnnaBridge 158:1c57384330a6 240 /**
AnnaBridge 158:1c57384330a6 241 * @}
AnnaBridge 158:1c57384330a6 242 */
AnnaBridge 158:1c57384330a6 243
AnnaBridge 158:1c57384330a6 244 #if defined(RCC_HSI48_SUPPORT)
AnnaBridge 158:1c57384330a6 245 /** @defgroup RCC_HSI48_Config HSI48 Config
AnnaBridge 158:1c57384330a6 246 * @{
AnnaBridge 158:1c57384330a6 247 */
AnnaBridge 158:1c57384330a6 248 #define RCC_HSI48_OFF ((uint32_t)0x00000000U) /*!< HSI48 clock deactivation */
AnnaBridge 158:1c57384330a6 249 #define RCC_HSI48_ON RCC_CRRCR_HSI48ON /*!< HSI48 clock activation */
AnnaBridge 158:1c57384330a6 250 /**
AnnaBridge 158:1c57384330a6 251 * @}
AnnaBridge 158:1c57384330a6 252 */
AnnaBridge 158:1c57384330a6 253 #else
AnnaBridge 158:1c57384330a6 254 /** @defgroup RCC_HSI48_Config HSI48 Config
AnnaBridge 158:1c57384330a6 255 * @{
AnnaBridge 158:1c57384330a6 256 */
AnnaBridge 158:1c57384330a6 257 #define RCC_HSI48_OFF ((uint32_t)0x00000000U) /*!< HSI48 clock deactivation */
AnnaBridge 158:1c57384330a6 258 /**
AnnaBridge 158:1c57384330a6 259 * @}
AnnaBridge 158:1c57384330a6 260 */
AnnaBridge 158:1c57384330a6 261 #endif /* RCC_HSI48_SUPPORT */
AnnaBridge 158:1c57384330a6 262
AnnaBridge 158:1c57384330a6 263 /** @defgroup RCC_PLL_Config PLL Config
AnnaBridge 158:1c57384330a6 264 * @{
AnnaBridge 158:1c57384330a6 265 */
AnnaBridge 158:1c57384330a6 266 #define RCC_PLL_NONE ((uint32_t)0x00000000U) /*!< PLL configuration unchanged */
AnnaBridge 158:1c57384330a6 267 #define RCC_PLL_OFF ((uint32_t)0x00000001U) /*!< PLL deactivation */
AnnaBridge 158:1c57384330a6 268 #define RCC_PLL_ON ((uint32_t)0x00000002U) /*!< PLL activation */
AnnaBridge 158:1c57384330a6 269 /**
AnnaBridge 158:1c57384330a6 270 * @}
AnnaBridge 158:1c57384330a6 271 */
AnnaBridge 158:1c57384330a6 272
AnnaBridge 158:1c57384330a6 273 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
AnnaBridge 158:1c57384330a6 274 * @{
AnnaBridge 158:1c57384330a6 275 */
AnnaBridge 158:1c57384330a6 276 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
AnnaBridge 158:1c57384330a6 277 #define RCC_PLLP_DIV2 ((uint32_t)0x00000002U) /*!< PLLP division factor = 2 */
AnnaBridge 158:1c57384330a6 278 #define RCC_PLLP_DIV3 ((uint32_t)0x00000003U) /*!< PLLP division factor = 3 */
AnnaBridge 158:1c57384330a6 279 #define RCC_PLLP_DIV4 ((uint32_t)0x00000004U) /*!< PLLP division factor = 4 */
AnnaBridge 158:1c57384330a6 280 #define RCC_PLLP_DIV5 ((uint32_t)0x00000005U) /*!< PLLP division factor = 5 */
AnnaBridge 158:1c57384330a6 281 #define RCC_PLLP_DIV6 ((uint32_t)0x00000006U) /*!< PLLP division factor = 6 */
AnnaBridge 158:1c57384330a6 282 #define RCC_PLLP_DIV7 ((uint32_t)0x00000007U) /*!< PLLP division factor = 7 */
AnnaBridge 158:1c57384330a6 283 #define RCC_PLLP_DIV8 ((uint32_t)0x00000008U) /*!< PLLP division factor = 8 */
AnnaBridge 158:1c57384330a6 284 #define RCC_PLLP_DIV9 ((uint32_t)0x00000009U) /*!< PLLP division factor = 9 */
AnnaBridge 158:1c57384330a6 285 #define RCC_PLLP_DIV10 ((uint32_t)0x0000000AU) /*!< PLLP division factor = 10 */
AnnaBridge 158:1c57384330a6 286 #define RCC_PLLP_DIV11 ((uint32_t)0x0000000BU) /*!< PLLP division factor = 11 */
AnnaBridge 158:1c57384330a6 287 #define RCC_PLLP_DIV12 ((uint32_t)0x0000000CU) /*!< PLLP division factor = 12 */
AnnaBridge 158:1c57384330a6 288 #define RCC_PLLP_DIV13 ((uint32_t)0x0000000DU) /*!< PLLP division factor = 13 */
AnnaBridge 158:1c57384330a6 289 #define RCC_PLLP_DIV14 ((uint32_t)0x0000000EU) /*!< PLLP division factor = 14 */
AnnaBridge 158:1c57384330a6 290 #define RCC_PLLP_DIV15 ((uint32_t)0x0000000FU) /*!< PLLP division factor = 15 */
AnnaBridge 158:1c57384330a6 291 #define RCC_PLLP_DIV16 ((uint32_t)0x00000010U) /*!< PLLP division factor = 16 */
AnnaBridge 158:1c57384330a6 292 #define RCC_PLLP_DIV17 ((uint32_t)0x00000011U) /*!< PLLP division factor = 17 */
AnnaBridge 158:1c57384330a6 293 #define RCC_PLLP_DIV18 ((uint32_t)0x00000012U) /*!< PLLP division factor = 18 */
AnnaBridge 158:1c57384330a6 294 #define RCC_PLLP_DIV19 ((uint32_t)0x00000013U) /*!< PLLP division factor = 19 */
AnnaBridge 158:1c57384330a6 295 #define RCC_PLLP_DIV20 ((uint32_t)0x00000014U) /*!< PLLP division factor = 20 */
AnnaBridge 158:1c57384330a6 296 #define RCC_PLLP_DIV21 ((uint32_t)0x00000015U) /*!< PLLP division factor = 21 */
AnnaBridge 158:1c57384330a6 297 #define RCC_PLLP_DIV22 ((uint32_t)0x00000016U) /*!< PLLP division factor = 22 */
AnnaBridge 158:1c57384330a6 298 #define RCC_PLLP_DIV23 ((uint32_t)0x00000017U) /*!< PLLP division factor = 23 */
AnnaBridge 158:1c57384330a6 299 #define RCC_PLLP_DIV24 ((uint32_t)0x00000018U) /*!< PLLP division factor = 24 */
AnnaBridge 158:1c57384330a6 300 #define RCC_PLLP_DIV25 ((uint32_t)0x00000019U) /*!< PLLP division factor = 25 */
AnnaBridge 158:1c57384330a6 301 #define RCC_PLLP_DIV26 ((uint32_t)0x0000001AU) /*!< PLLP division factor = 26 */
AnnaBridge 158:1c57384330a6 302 #define RCC_PLLP_DIV27 ((uint32_t)0x0000001BU) /*!< PLLP division factor = 27 */
AnnaBridge 158:1c57384330a6 303 #define RCC_PLLP_DIV28 ((uint32_t)0x0000001CU) /*!< PLLP division factor = 28 */
AnnaBridge 158:1c57384330a6 304 #define RCC_PLLP_DIV29 ((uint32_t)0x0000001DU) /*!< PLLP division factor = 29 */
AnnaBridge 158:1c57384330a6 305 #define RCC_PLLP_DIV30 ((uint32_t)0x0000001EU) /*!< PLLP division factor = 30 */
AnnaBridge 158:1c57384330a6 306 #define RCC_PLLP_DIV31 ((uint32_t)0x0000001FU) /*!< PLLP division factor = 31 */
AnnaBridge 158:1c57384330a6 307 #else
AnnaBridge 158:1c57384330a6 308 #define RCC_PLLP_DIV7 ((uint32_t)0x00000007U) /*!< PLLP division factor = 7 */
AnnaBridge 158:1c57384330a6 309 #define RCC_PLLP_DIV17 ((uint32_t)0x00000011U) /*!< PLLP division factor = 17 */
AnnaBridge 158:1c57384330a6 310 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */
AnnaBridge 158:1c57384330a6 311 /**
AnnaBridge 158:1c57384330a6 312 * @}
AnnaBridge 158:1c57384330a6 313 */
AnnaBridge 158:1c57384330a6 314
AnnaBridge 158:1c57384330a6 315 /** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider
AnnaBridge 158:1c57384330a6 316 * @{
AnnaBridge 158:1c57384330a6 317 */
AnnaBridge 158:1c57384330a6 318 #define RCC_PLLQ_DIV2 ((uint32_t)0x00000002U) /*!< PLLQ division factor = 2 */
AnnaBridge 158:1c57384330a6 319 #define RCC_PLLQ_DIV4 ((uint32_t)0x00000004U) /*!< PLLQ division factor = 4 */
AnnaBridge 158:1c57384330a6 320 #define RCC_PLLQ_DIV6 ((uint32_t)0x00000006U) /*!< PLLQ division factor = 6 */
AnnaBridge 158:1c57384330a6 321 #define RCC_PLLQ_DIV8 ((uint32_t)0x00000008U) /*!< PLLQ division factor = 8 */
AnnaBridge 158:1c57384330a6 322 /**
AnnaBridge 158:1c57384330a6 323 * @}
AnnaBridge 158:1c57384330a6 324 */
AnnaBridge 158:1c57384330a6 325
AnnaBridge 158:1c57384330a6 326 /** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider
AnnaBridge 158:1c57384330a6 327 * @{
AnnaBridge 158:1c57384330a6 328 */
AnnaBridge 158:1c57384330a6 329 #define RCC_PLLR_DIV2 ((uint32_t)0x00000002U) /*!< PLLR division factor = 2 */
AnnaBridge 158:1c57384330a6 330 #define RCC_PLLR_DIV4 ((uint32_t)0x00000004U) /*!< PLLR division factor = 4 */
AnnaBridge 158:1c57384330a6 331 #define RCC_PLLR_DIV6 ((uint32_t)0x00000006U) /*!< PLLR division factor = 6 */
AnnaBridge 158:1c57384330a6 332 #define RCC_PLLR_DIV8 ((uint32_t)0x00000008U) /*!< PLLR division factor = 8 */
AnnaBridge 158:1c57384330a6 333 /**
AnnaBridge 158:1c57384330a6 334 * @}
AnnaBridge 158:1c57384330a6 335 */
AnnaBridge 158:1c57384330a6 336
AnnaBridge 158:1c57384330a6 337 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
AnnaBridge 158:1c57384330a6 338 * @{
AnnaBridge 158:1c57384330a6 339 */
AnnaBridge 158:1c57384330a6 340 #define RCC_PLLSOURCE_NONE ((uint32_t)0x00000000U) /*!< No clock selected as PLL entry clock source */
AnnaBridge 158:1c57384330a6 341 #define RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI /*!< MSI clock selected as PLL entry clock source */
AnnaBridge 158:1c57384330a6 342 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */
AnnaBridge 158:1c57384330a6 343 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */
AnnaBridge 158:1c57384330a6 344 /**
AnnaBridge 158:1c57384330a6 345 * @}
AnnaBridge 158:1c57384330a6 346 */
AnnaBridge 158:1c57384330a6 347
AnnaBridge 158:1c57384330a6 348 /** @defgroup RCC_PLL_Clock_Output PLL Clock Output
AnnaBridge 158:1c57384330a6 349 * @{
AnnaBridge 158:1c57384330a6 350 */
AnnaBridge 158:1c57384330a6 351 #if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge 158:1c57384330a6 352 #define RCC_PLL_SAI3CLK RCC_PLLCFGR_PLLPEN /*!< PLLSAI3CLK selection from main PLL (for devices with PLLSAI2) */
AnnaBridge 158:1c57384330a6 353 #else
AnnaBridge 158:1c57384330a6 354 #define RCC_PLL_SAI2CLK RCC_PLLCFGR_PLLPEN /*!< PLLSAI2CLK selection from main PLL (for devices without PLLSAI2) */
AnnaBridge 158:1c57384330a6 355 #endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge 158:1c57384330a6 356 #define RCC_PLL_48M1CLK RCC_PLLCFGR_PLLQEN /*!< PLL48M1CLK selection from main PLL */
AnnaBridge 158:1c57384330a6 357 #define RCC_PLL_SYSCLK RCC_PLLCFGR_PLLREN /*!< PLLCLK selection from main PLL */
AnnaBridge 158:1c57384330a6 358 /**
AnnaBridge 158:1c57384330a6 359 * @}
AnnaBridge 158:1c57384330a6 360 */
AnnaBridge 158:1c57384330a6 361
AnnaBridge 158:1c57384330a6 362 /** @defgroup RCC_PLLSAI1_Clock_Output PLLSAI1 Clock Output
AnnaBridge 158:1c57384330a6 363 * @{
AnnaBridge 158:1c57384330a6 364 */
AnnaBridge 158:1c57384330a6 365 #define RCC_PLLSAI1_SAI1CLK RCC_PLLSAI1CFGR_PLLSAI1PEN /*!< PLLSAI1CLK selection from PLLSAI1 */
AnnaBridge 158:1c57384330a6 366 #define RCC_PLLSAI1_48M2CLK RCC_PLLSAI1CFGR_PLLSAI1QEN /*!< PLL48M2CLK selection from PLLSAI1 */
AnnaBridge 158:1c57384330a6 367 #define RCC_PLLSAI1_ADC1CLK RCC_PLLSAI1CFGR_PLLSAI1REN /*!< PLLADC1CLK selection from PLLSAI1 */
AnnaBridge 158:1c57384330a6 368 /**
AnnaBridge 158:1c57384330a6 369 * @}
AnnaBridge 158:1c57384330a6 370 */
AnnaBridge 158:1c57384330a6 371
AnnaBridge 158:1c57384330a6 372 #if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge 158:1c57384330a6 373
AnnaBridge 158:1c57384330a6 374 /** @defgroup RCC_PLLSAI2_Clock_Output PLLSAI2 Clock Output
AnnaBridge 158:1c57384330a6 375 * @{
AnnaBridge 158:1c57384330a6 376 */
AnnaBridge 158:1c57384330a6 377 #define RCC_PLLSAI2_SAI2CLK RCC_PLLSAI2CFGR_PLLSAI2PEN /*!< PLLSAI2CLK selection from PLLSAI2 */
AnnaBridge 158:1c57384330a6 378 #define RCC_PLLSAI2_ADC2CLK RCC_PLLSAI2CFGR_PLLSAI2REN /*!< PLLADC2CLK selection from PLLSAI2 */
AnnaBridge 158:1c57384330a6 379 /**
AnnaBridge 158:1c57384330a6 380 * @}
AnnaBridge 158:1c57384330a6 381 */
AnnaBridge 158:1c57384330a6 382
AnnaBridge 158:1c57384330a6 383 #endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge 158:1c57384330a6 384
AnnaBridge 158:1c57384330a6 385 /** @defgroup RCC_MSI_Clock_Range MSI Clock Range
AnnaBridge 158:1c57384330a6 386 * @{
AnnaBridge 158:1c57384330a6 387 */
AnnaBridge 158:1c57384330a6 388 #define RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0 /*!< MSI = 100 KHz */
AnnaBridge 158:1c57384330a6 389 #define RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1 /*!< MSI = 200 KHz */
AnnaBridge 158:1c57384330a6 390 #define RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2 /*!< MSI = 400 KHz */
AnnaBridge 158:1c57384330a6 391 #define RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3 /*!< MSI = 800 KHz */
AnnaBridge 158:1c57384330a6 392 #define RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4 /*!< MSI = 1 MHz */
AnnaBridge 158:1c57384330a6 393 #define RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5 /*!< MSI = 2 MHz */
AnnaBridge 158:1c57384330a6 394 #define RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6 /*!< MSI = 4 MHz */
AnnaBridge 158:1c57384330a6 395 #define RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7 /*!< MSI = 8 MHz */
AnnaBridge 158:1c57384330a6 396 #define RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8 /*!< MSI = 16 MHz */
AnnaBridge 158:1c57384330a6 397 #define RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9 /*!< MSI = 24 MHz */
AnnaBridge 158:1c57384330a6 398 #define RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10 /*!< MSI = 32 MHz */
AnnaBridge 158:1c57384330a6 399 #define RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11 /*!< MSI = 48 MHz */
AnnaBridge 158:1c57384330a6 400 /**
AnnaBridge 158:1c57384330a6 401 * @}
AnnaBridge 158:1c57384330a6 402 */
AnnaBridge 158:1c57384330a6 403
AnnaBridge 158:1c57384330a6 404 /** @defgroup RCC_System_Clock_Type System Clock Type
AnnaBridge 158:1c57384330a6 405 * @{
AnnaBridge 158:1c57384330a6 406 */
AnnaBridge 158:1c57384330a6 407 #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U) /*!< SYSCLK to configure */
AnnaBridge 158:1c57384330a6 408 #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U) /*!< HCLK to configure */
AnnaBridge 158:1c57384330a6 409 #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U) /*!< PCLK1 to configure */
AnnaBridge 158:1c57384330a6 410 #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U) /*!< PCLK2 to configure */
AnnaBridge 158:1c57384330a6 411 /**
AnnaBridge 158:1c57384330a6 412 * @}
AnnaBridge 158:1c57384330a6 413 */
AnnaBridge 158:1c57384330a6 414
AnnaBridge 158:1c57384330a6 415 /** @defgroup RCC_System_Clock_Source System Clock Source
AnnaBridge 158:1c57384330a6 416 * @{
AnnaBridge 158:1c57384330a6 417 */
AnnaBridge 158:1c57384330a6 418 #define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI /*!< MSI selection as system clock */
AnnaBridge 158:1c57384330a6 419 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
AnnaBridge 158:1c57384330a6 420 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
AnnaBridge 158:1c57384330a6 421 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
AnnaBridge 158:1c57384330a6 422 /**
AnnaBridge 158:1c57384330a6 423 * @}
AnnaBridge 158:1c57384330a6 424 */
AnnaBridge 158:1c57384330a6 425
AnnaBridge 158:1c57384330a6 426 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
AnnaBridge 158:1c57384330a6 427 * @{
AnnaBridge 158:1c57384330a6 428 */
AnnaBridge 158:1c57384330a6 429 #define RCC_SYSCLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /*!< MSI used as system clock */
AnnaBridge 158:1c57384330a6 430 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
AnnaBridge 158:1c57384330a6 431 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
AnnaBridge 158:1c57384330a6 432 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
AnnaBridge 158:1c57384330a6 433 /**
AnnaBridge 158:1c57384330a6 434 * @}
AnnaBridge 158:1c57384330a6 435 */
AnnaBridge 158:1c57384330a6 436
AnnaBridge 158:1c57384330a6 437 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source
AnnaBridge 158:1c57384330a6 438 * @{
AnnaBridge 158:1c57384330a6 439 */
AnnaBridge 158:1c57384330a6 440 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
AnnaBridge 158:1c57384330a6 441 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
AnnaBridge 158:1c57384330a6 442 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
AnnaBridge 158:1c57384330a6 443 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
AnnaBridge 158:1c57384330a6 444 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
AnnaBridge 158:1c57384330a6 445 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
AnnaBridge 158:1c57384330a6 446 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
AnnaBridge 158:1c57384330a6 447 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
AnnaBridge 158:1c57384330a6 448 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
AnnaBridge 158:1c57384330a6 449 /**
AnnaBridge 158:1c57384330a6 450 * @}
AnnaBridge 158:1c57384330a6 451 */
AnnaBridge 158:1c57384330a6 452
AnnaBridge 158:1c57384330a6 453 /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
AnnaBridge 158:1c57384330a6 454 * @{
AnnaBridge 158:1c57384330a6 455 */
AnnaBridge 158:1c57384330a6 456 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
AnnaBridge 158:1c57384330a6 457 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
AnnaBridge 158:1c57384330a6 458 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
AnnaBridge 158:1c57384330a6 459 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
AnnaBridge 158:1c57384330a6 460 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
AnnaBridge 158:1c57384330a6 461 /**
AnnaBridge 158:1c57384330a6 462 * @}
AnnaBridge 158:1c57384330a6 463 */
AnnaBridge 158:1c57384330a6 464
AnnaBridge 158:1c57384330a6 465 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source
AnnaBridge 158:1c57384330a6 466 * @{
AnnaBridge 158:1c57384330a6 467 */
AnnaBridge 158:1c57384330a6 468 #define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000U) /*!< No clock used as RTC clock */
AnnaBridge 158:1c57384330a6 469 #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
AnnaBridge 158:1c57384330a6 470 #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
AnnaBridge 158:1c57384330a6 471 #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */
AnnaBridge 158:1c57384330a6 472 /**
AnnaBridge 158:1c57384330a6 473 * @}
AnnaBridge 158:1c57384330a6 474 */
AnnaBridge 158:1c57384330a6 475
AnnaBridge 158:1c57384330a6 476 /** @defgroup RCC_MCO_Index MCO Index
AnnaBridge 158:1c57384330a6 477 * @{
AnnaBridge 158:1c57384330a6 478 */
AnnaBridge 158:1c57384330a6 479 #define RCC_MCO1 ((uint32_t)0x00000000U)
AnnaBridge 158:1c57384330a6 480 #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/
AnnaBridge 158:1c57384330a6 481 /**
AnnaBridge 158:1c57384330a6 482 * @}
AnnaBridge 158:1c57384330a6 483 */
AnnaBridge 158:1c57384330a6 484
AnnaBridge 158:1c57384330a6 485 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
AnnaBridge 158:1c57384330a6 486 * @{
AnnaBridge 158:1c57384330a6 487 */
AnnaBridge 158:1c57384330a6 488 #define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)0x00000000U) /*!< MCO1 output disabled, no clock on MCO1 */
AnnaBridge 158:1c57384330a6 489 #define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */
AnnaBridge 158:1c57384330a6 490 #define RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /*!< MSI selection as MCO1 source */
AnnaBridge 158:1c57384330a6 491 #define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */
AnnaBridge 158:1c57384330a6 492 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */
AnnaBridge 158:1c57384330a6 493 #define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< PLLCLK selection as MCO1 source */
AnnaBridge 158:1c57384330a6 494 #define RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */
AnnaBridge 158:1c57384330a6 495 #define RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */
AnnaBridge 158:1c57384330a6 496 #if defined(RCC_HSI48_SUPPORT)
AnnaBridge 158:1c57384330a6 497 #define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3 /*!< HSI48 selection as MCO1 source (STM32L43x/STM32L44x devices) */
AnnaBridge 158:1c57384330a6 498 #endif /* RCC_HSI48_SUPPORT */
AnnaBridge 158:1c57384330a6 499 /**
AnnaBridge 158:1c57384330a6 500 * @}
AnnaBridge 158:1c57384330a6 501 */
AnnaBridge 158:1c57384330a6 502
AnnaBridge 158:1c57384330a6 503 /** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler
AnnaBridge 158:1c57384330a6 504 * @{
AnnaBridge 158:1c57384330a6 505 */
AnnaBridge 158:1c57384330a6 506 #define RCC_MCODIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO not divided */
AnnaBridge 158:1c57384330a6 507 #define RCC_MCODIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO divided by 2 */
AnnaBridge 158:1c57384330a6 508 #define RCC_MCODIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO divided by 4 */
AnnaBridge 158:1c57384330a6 509 #define RCC_MCODIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO divided by 8 */
AnnaBridge 158:1c57384330a6 510 #define RCC_MCODIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO divided by 16 */
AnnaBridge 158:1c57384330a6 511 /**
AnnaBridge 158:1c57384330a6 512 * @}
AnnaBridge 158:1c57384330a6 513 */
AnnaBridge 158:1c57384330a6 514
AnnaBridge 158:1c57384330a6 515 /** @defgroup RCC_Interrupt Interrupts
AnnaBridge 158:1c57384330a6 516 * @{
AnnaBridge 158:1c57384330a6 517 */
AnnaBridge 158:1c57384330a6 518 #define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */
AnnaBridge 158:1c57384330a6 519 #define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */
AnnaBridge 158:1c57384330a6 520 #define RCC_IT_MSIRDY RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */
AnnaBridge 158:1c57384330a6 521 #define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI16 Ready Interrupt flag */
AnnaBridge 158:1c57384330a6 522 #define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */
AnnaBridge 158:1c57384330a6 523 #define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */
AnnaBridge 158:1c57384330a6 524 #define RCC_IT_PLLSAI1RDY RCC_CIFR_PLLSAI1RDYF /*!< PLLSAI1 Ready Interrupt flag */
AnnaBridge 158:1c57384330a6 525 #if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge 158:1c57384330a6 526 #define RCC_IT_PLLSAI2RDY RCC_CIFR_PLLSAI2RDYF /*!< PLLSAI2 Ready Interrupt flag */
AnnaBridge 158:1c57384330a6 527 #endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge 158:1c57384330a6 528 #define RCC_IT_CSS RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */
AnnaBridge 158:1c57384330a6 529 #define RCC_IT_LSECSS RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */
AnnaBridge 158:1c57384330a6 530 #if defined(RCC_HSI48_SUPPORT)
AnnaBridge 158:1c57384330a6 531 #define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */
AnnaBridge 158:1c57384330a6 532 #endif /* RCC_HSI48_SUPPORT */
AnnaBridge 158:1c57384330a6 533 /**
AnnaBridge 158:1c57384330a6 534 * @}
AnnaBridge 158:1c57384330a6 535 */
AnnaBridge 158:1c57384330a6 536
AnnaBridge 158:1c57384330a6 537 /** @defgroup RCC_Flag Flags
AnnaBridge 158:1c57384330a6 538 * Elements values convention: XXXYYYYYb
AnnaBridge 158:1c57384330a6 539 * - YYYYY : Flag position in the register
AnnaBridge 158:1c57384330a6 540 * - XXX : Register index
AnnaBridge 158:1c57384330a6 541 * - 001: CR register
AnnaBridge 158:1c57384330a6 542 * - 010: BDCR register
AnnaBridge 158:1c57384330a6 543 * - 011: CSR register
AnnaBridge 158:1c57384330a6 544 * - 100: CRRCR register
AnnaBridge 158:1c57384330a6 545 * @{
AnnaBridge 158:1c57384330a6 546 */
AnnaBridge 158:1c57384330a6 547 /* Flags in the CR register */
AnnaBridge 158:1c57384330a6 548 #define RCC_FLAG_MSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_MSIRDY))) /*!< MSI Ready flag */
AnnaBridge 158:1c57384330a6 549 #define RCC_FLAG_HSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSIRDY))) /*!< HSI Ready flag */
AnnaBridge 158:1c57384330a6 550 #define RCC_FLAG_HSERDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSERDY))) /*!< HSE Ready flag */
AnnaBridge 158:1c57384330a6 551 #define RCC_FLAG_PLLRDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLRDY))) /*!< PLL Ready flag */
AnnaBridge 158:1c57384330a6 552 #define RCC_FLAG_PLLSAI1RDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLSAI1RDY))) /*!< PLLSAI1 Ready flag */
AnnaBridge 158:1c57384330a6 553 #if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge 158:1c57384330a6 554 #define RCC_FLAG_PLLSAI2RDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLSAI2RDY))) /*!< PLLSAI2 Ready flag */
AnnaBridge 158:1c57384330a6 555 #endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge 158:1c57384330a6 556
AnnaBridge 158:1c57384330a6 557 /* Flags in the BDCR register */
AnnaBridge 158:1c57384330a6 558 #define RCC_FLAG_LSERDY ((uint32_t)((BDCR_REG_INDEX << 5U) | POSITION_VAL(RCC_BDCR_LSERDY))) /*!< LSE Ready flag */
AnnaBridge 158:1c57384330a6 559 #define RCC_FLAG_LSECSSD ((uint32_t)((BDCR_REG_INDEX << 5U) | POSITION_VAL(RCC_BDCR_LSECSSD))) /*!< LSE Clock Security System Interrupt flag */
AnnaBridge 158:1c57384330a6 560
AnnaBridge 158:1c57384330a6 561 /* Flags in the CSR register */
AnnaBridge 158:1c57384330a6 562 #define RCC_FLAG_LSIRDY ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LSIRDY))) /*!< LSI Ready flag */
AnnaBridge 158:1c57384330a6 563 #define RCC_FLAG_RMVF ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_RMVF))) /*!< Remove reset flag */
AnnaBridge 158:1c57384330a6 564 #define RCC_FLAG_FWRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_FWRSTF))) /*!< Firewall reset flag */
AnnaBridge 158:1c57384330a6 565 #define RCC_FLAG_OBLRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_OBLRSTF))) /*!< Option Byte Loader reset flag */
AnnaBridge 158:1c57384330a6 566 #define RCC_FLAG_PINRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PINRSTF))) /*!< PIN reset flag */
AnnaBridge 158:1c57384330a6 567 #define RCC_FLAG_BORRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_BORRSTF))) /*!< BOR reset flag */
AnnaBridge 158:1c57384330a6 568 #define RCC_FLAG_SFTRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_SFTRSTF))) /*!< Software Reset flag */
AnnaBridge 158:1c57384330a6 569 #define RCC_FLAG_IWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_IWDGRSTF))) /*!< Independent Watchdog reset flag */
AnnaBridge 158:1c57384330a6 570 #define RCC_FLAG_WWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_WWDGRSTF))) /*!< Window watchdog reset flag */
AnnaBridge 158:1c57384330a6 571 #define RCC_FLAG_LPWRRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LPWRRSTF))) /*!< Low-Power reset flag */
AnnaBridge 158:1c57384330a6 572
AnnaBridge 158:1c57384330a6 573 #if defined(RCC_HSI48_SUPPORT)
AnnaBridge 158:1c57384330a6 574 /* Flags in the CRRCR register */
AnnaBridge 158:1c57384330a6 575 #define RCC_FLAG_HSI48RDY ((uint32_t)((CRRCR_REG_INDEX << 5U) | POSITION_VAL(RCC_CRRCR_HSI48RDY))) /*!< HSI48 Ready flag */
AnnaBridge 158:1c57384330a6 576 #endif /* RCC_HSI48_SUPPORT */
AnnaBridge 158:1c57384330a6 577 /**
AnnaBridge 158:1c57384330a6 578 * @}
AnnaBridge 158:1c57384330a6 579 */
AnnaBridge 158:1c57384330a6 580
AnnaBridge 158:1c57384330a6 581 /** @defgroup RCC_LSEDrive_Config LSE Drive Config
AnnaBridge 158:1c57384330a6 582 * @{
AnnaBridge 158:1c57384330a6 583 */
AnnaBridge 158:1c57384330a6 584 #define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) /*!< LSE low drive capability */
AnnaBridge 158:1c57384330a6 585 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */
AnnaBridge 158:1c57384330a6 586 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */
AnnaBridge 158:1c57384330a6 587 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */
AnnaBridge 158:1c57384330a6 588 /**
AnnaBridge 158:1c57384330a6 589 * @}
AnnaBridge 158:1c57384330a6 590 */
AnnaBridge 158:1c57384330a6 591
AnnaBridge 158:1c57384330a6 592 /** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock
AnnaBridge 158:1c57384330a6 593 * @{
AnnaBridge 158:1c57384330a6 594 */
AnnaBridge 158:1c57384330a6 595 #define RCC_STOP_WAKEUPCLOCK_MSI ((uint32_t)0x00000000U) /*!< MSI selection after wake-up from STOP */
AnnaBridge 158:1c57384330a6 596 #define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /*!< HSI selection after wake-up from STOP */
AnnaBridge 158:1c57384330a6 597 /**
AnnaBridge 158:1c57384330a6 598 * @}
AnnaBridge 158:1c57384330a6 599 */
AnnaBridge 158:1c57384330a6 600
AnnaBridge 158:1c57384330a6 601 /**
AnnaBridge 158:1c57384330a6 602 * @}
AnnaBridge 158:1c57384330a6 603 */
AnnaBridge 158:1c57384330a6 604
AnnaBridge 158:1c57384330a6 605 /* Exported macros -----------------------------------------------------------*/
AnnaBridge 158:1c57384330a6 606
AnnaBridge 158:1c57384330a6 607 /** @defgroup RCC_Exported_Macros RCC Exported Macros
AnnaBridge 158:1c57384330a6 608 * @{
AnnaBridge 158:1c57384330a6 609 */
AnnaBridge 158:1c57384330a6 610
AnnaBridge 158:1c57384330a6 611 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
AnnaBridge 158:1c57384330a6 612 * @brief Enable or disable the AHB1 peripheral clock.
AnnaBridge 158:1c57384330a6 613 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 158:1c57384330a6 614 * is disabled and the application software has to enable this clock before
AnnaBridge 158:1c57384330a6 615 * using it.
AnnaBridge 158:1c57384330a6 616 * @{
AnnaBridge 158:1c57384330a6 617 */
AnnaBridge 158:1c57384330a6 618
AnnaBridge 158:1c57384330a6 619 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 620 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 621 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
AnnaBridge 158:1c57384330a6 622 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 623 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
AnnaBridge 158:1c57384330a6 624 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 625 } while(0)
AnnaBridge 158:1c57384330a6 626
AnnaBridge 158:1c57384330a6 627 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 628 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 629 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
AnnaBridge 158:1c57384330a6 630 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 631 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
AnnaBridge 158:1c57384330a6 632 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 633 } while(0)
AnnaBridge 158:1c57384330a6 634
AnnaBridge 158:1c57384330a6 635 #define __HAL_RCC_FLASH_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 636 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 637 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
AnnaBridge 158:1c57384330a6 638 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 639 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
AnnaBridge 158:1c57384330a6 640 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 641 } while(0)
AnnaBridge 158:1c57384330a6 642
AnnaBridge 158:1c57384330a6 643 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 644 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 645 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
AnnaBridge 158:1c57384330a6 646 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 647 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
AnnaBridge 158:1c57384330a6 648 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 649 } while(0)
AnnaBridge 158:1c57384330a6 650
AnnaBridge 158:1c57384330a6 651 #define __HAL_RCC_TSC_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 652 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 653 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
AnnaBridge 158:1c57384330a6 654 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 655 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
AnnaBridge 158:1c57384330a6 656 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 657 } while(0)
AnnaBridge 158:1c57384330a6 658
AnnaBridge 158:1c57384330a6 659 #if defined(DMA2D)
AnnaBridge 158:1c57384330a6 660 #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 661 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 662 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \
AnnaBridge 158:1c57384330a6 663 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 664 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \
AnnaBridge 158:1c57384330a6 665 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 666 } while(0)
AnnaBridge 158:1c57384330a6 667 #endif /* DMA2D */
AnnaBridge 158:1c57384330a6 668
AnnaBridge 158:1c57384330a6 669
AnnaBridge 158:1c57384330a6 670 #define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN)
AnnaBridge 158:1c57384330a6 671
AnnaBridge 158:1c57384330a6 672 #define __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN)
AnnaBridge 158:1c57384330a6 673
AnnaBridge 158:1c57384330a6 674 #define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN)
AnnaBridge 158:1c57384330a6 675
AnnaBridge 158:1c57384330a6 676 #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN)
AnnaBridge 158:1c57384330a6 677
AnnaBridge 158:1c57384330a6 678 #define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN)
AnnaBridge 158:1c57384330a6 679
AnnaBridge 158:1c57384330a6 680 #if defined(DMA2D)
AnnaBridge 158:1c57384330a6 681 #define __HAL_RCC_DMA2D_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN)
AnnaBridge 158:1c57384330a6 682 #endif /* DMA2D */
AnnaBridge 158:1c57384330a6 683
AnnaBridge 158:1c57384330a6 684 /**
AnnaBridge 158:1c57384330a6 685 * @}
AnnaBridge 158:1c57384330a6 686 */
AnnaBridge 158:1c57384330a6 687
AnnaBridge 158:1c57384330a6 688 /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
AnnaBridge 158:1c57384330a6 689 * @brief Enable or disable the AHB2 peripheral clock.
AnnaBridge 158:1c57384330a6 690 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 158:1c57384330a6 691 * is disabled and the application software has to enable this clock before
AnnaBridge 158:1c57384330a6 692 * using it.
AnnaBridge 158:1c57384330a6 693 * @{
AnnaBridge 158:1c57384330a6 694 */
AnnaBridge 158:1c57384330a6 695
AnnaBridge 158:1c57384330a6 696 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 697 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 698 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
AnnaBridge 158:1c57384330a6 699 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 700 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
AnnaBridge 158:1c57384330a6 701 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 702 } while(0)
AnnaBridge 158:1c57384330a6 703
AnnaBridge 158:1c57384330a6 704 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 705 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 706 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
AnnaBridge 158:1c57384330a6 707 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 708 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
AnnaBridge 158:1c57384330a6 709 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 710 } while(0)
AnnaBridge 158:1c57384330a6 711
AnnaBridge 158:1c57384330a6 712 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 713 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 714 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
AnnaBridge 158:1c57384330a6 715 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 716 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
AnnaBridge 158:1c57384330a6 717 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 718 } while(0)
AnnaBridge 158:1c57384330a6 719
AnnaBridge 158:1c57384330a6 720 #if defined(GPIOD)
AnnaBridge 158:1c57384330a6 721 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 722 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 723 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
AnnaBridge 158:1c57384330a6 724 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 725 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
AnnaBridge 158:1c57384330a6 726 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 727 } while(0)
AnnaBridge 158:1c57384330a6 728 #endif /* GPIOD */
AnnaBridge 158:1c57384330a6 729
AnnaBridge 158:1c57384330a6 730 #if defined(GPIOE)
AnnaBridge 158:1c57384330a6 731 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 732 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 733 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
AnnaBridge 158:1c57384330a6 734 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 735 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
AnnaBridge 158:1c57384330a6 736 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 737 } while(0)
AnnaBridge 158:1c57384330a6 738 #endif /* GPIOE */
AnnaBridge 158:1c57384330a6 739
AnnaBridge 158:1c57384330a6 740 #if defined(GPIOF)
AnnaBridge 158:1c57384330a6 741 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 742 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 743 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
AnnaBridge 158:1c57384330a6 744 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 745 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
AnnaBridge 158:1c57384330a6 746 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 747 } while(0)
AnnaBridge 158:1c57384330a6 748 #endif /* GPIOF */
AnnaBridge 158:1c57384330a6 749
AnnaBridge 158:1c57384330a6 750 #if defined(GPIOG)
AnnaBridge 158:1c57384330a6 751 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 752 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 753 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
AnnaBridge 158:1c57384330a6 754 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 755 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
AnnaBridge 158:1c57384330a6 756 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 757 } while(0)
AnnaBridge 158:1c57384330a6 758 #endif /* GPIOG */
AnnaBridge 158:1c57384330a6 759
AnnaBridge 158:1c57384330a6 760 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 761 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 762 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \
AnnaBridge 158:1c57384330a6 763 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 764 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \
AnnaBridge 158:1c57384330a6 765 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 766 } while(0)
AnnaBridge 158:1c57384330a6 767
AnnaBridge 158:1c57384330a6 768 #if defined(GPIOI)
AnnaBridge 158:1c57384330a6 769 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 770 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 771 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN); \
AnnaBridge 158:1c57384330a6 772 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 773 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN); \
AnnaBridge 158:1c57384330a6 774 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 775 } while(0)
AnnaBridge 158:1c57384330a6 776 #endif /* GPIOI */
AnnaBridge 158:1c57384330a6 777
AnnaBridge 158:1c57384330a6 778 #if defined(USB_OTG_FS)
AnnaBridge 158:1c57384330a6 779 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 780 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 781 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \
AnnaBridge 158:1c57384330a6 782 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 783 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \
AnnaBridge 158:1c57384330a6 784 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 785 } while(0)
AnnaBridge 158:1c57384330a6 786 #endif /* USB_OTG_FS */
AnnaBridge 158:1c57384330a6 787
AnnaBridge 158:1c57384330a6 788 #define __HAL_RCC_ADC_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 789 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 790 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \
AnnaBridge 158:1c57384330a6 791 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 792 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \
AnnaBridge 158:1c57384330a6 793 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 794 } while(0)
AnnaBridge 158:1c57384330a6 795
AnnaBridge 158:1c57384330a6 796 #if defined(DCMI)
AnnaBridge 158:1c57384330a6 797 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 798 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 799 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN); \
AnnaBridge 158:1c57384330a6 800 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 801 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN); \
AnnaBridge 158:1c57384330a6 802 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 803 } while(0)
AnnaBridge 158:1c57384330a6 804 #endif /* DCMI */
AnnaBridge 158:1c57384330a6 805
AnnaBridge 158:1c57384330a6 806 #if defined(AES)
AnnaBridge 158:1c57384330a6 807 #define __HAL_RCC_AES_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 808 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 809 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
AnnaBridge 158:1c57384330a6 810 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 811 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
AnnaBridge 158:1c57384330a6 812 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 813 } while(0)
AnnaBridge 158:1c57384330a6 814 #endif /* AES */
AnnaBridge 158:1c57384330a6 815
AnnaBridge 158:1c57384330a6 816 #if defined(HASH)
AnnaBridge 158:1c57384330a6 817 #define __HAL_RCC_HASH_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 818 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 819 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \
AnnaBridge 158:1c57384330a6 820 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 821 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \
AnnaBridge 158:1c57384330a6 822 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 823 } while(0)
AnnaBridge 158:1c57384330a6 824 #endif /* HASH */
AnnaBridge 158:1c57384330a6 825
AnnaBridge 158:1c57384330a6 826 #define __HAL_RCC_RNG_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 827 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 828 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
AnnaBridge 158:1c57384330a6 829 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 830 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
AnnaBridge 158:1c57384330a6 831 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 832 } while(0)
AnnaBridge 158:1c57384330a6 833
AnnaBridge 158:1c57384330a6 834
AnnaBridge 158:1c57384330a6 835 #define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN)
AnnaBridge 158:1c57384330a6 836
AnnaBridge 158:1c57384330a6 837 #define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN)
AnnaBridge 158:1c57384330a6 838
AnnaBridge 158:1c57384330a6 839 #define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN)
AnnaBridge 158:1c57384330a6 840
AnnaBridge 158:1c57384330a6 841 #if defined(GPIOD)
AnnaBridge 158:1c57384330a6 842 #define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN)
AnnaBridge 158:1c57384330a6 843 #endif /* GPIOD */
AnnaBridge 158:1c57384330a6 844
AnnaBridge 158:1c57384330a6 845 #if defined(GPIOE)
AnnaBridge 158:1c57384330a6 846 #define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN)
AnnaBridge 158:1c57384330a6 847 #endif /* GPIOE */
AnnaBridge 158:1c57384330a6 848
AnnaBridge 158:1c57384330a6 849 #if defined(GPIOF)
AnnaBridge 158:1c57384330a6 850 #define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN)
AnnaBridge 158:1c57384330a6 851 #endif /* GPIOF */
AnnaBridge 158:1c57384330a6 852
AnnaBridge 158:1c57384330a6 853 #if defined(GPIOG)
AnnaBridge 158:1c57384330a6 854 #define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN)
AnnaBridge 158:1c57384330a6 855 #endif /* GPIOG */
AnnaBridge 158:1c57384330a6 856
AnnaBridge 158:1c57384330a6 857 #define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN)
AnnaBridge 158:1c57384330a6 858
AnnaBridge 158:1c57384330a6 859 #if defined(GPIOI)
AnnaBridge 158:1c57384330a6 860 #define __HAL_RCC_GPIOI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN)
AnnaBridge 158:1c57384330a6 861 #endif /* GPIOI */
AnnaBridge 158:1c57384330a6 862
AnnaBridge 158:1c57384330a6 863 #if defined(USB_OTG_FS)
AnnaBridge 158:1c57384330a6 864 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);
AnnaBridge 158:1c57384330a6 865 #endif /* USB_OTG_FS */
AnnaBridge 158:1c57384330a6 866
AnnaBridge 158:1c57384330a6 867 #define __HAL_RCC_ADC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN)
AnnaBridge 158:1c57384330a6 868
AnnaBridge 158:1c57384330a6 869 #if defined(DCMI)
AnnaBridge 158:1c57384330a6 870 #define __HAL_RCC_DCMI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN)
AnnaBridge 158:1c57384330a6 871 #endif /* DCMI */
AnnaBridge 158:1c57384330a6 872
AnnaBridge 158:1c57384330a6 873 #if defined(AES)
AnnaBridge 158:1c57384330a6 874 #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);
AnnaBridge 158:1c57384330a6 875 #endif /* AES */
AnnaBridge 158:1c57384330a6 876
AnnaBridge 158:1c57384330a6 877 #if defined(HASH)
AnnaBridge 158:1c57384330a6 878 #define __HAL_RCC_HASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN)
AnnaBridge 158:1c57384330a6 879 #endif /* HASH */
AnnaBridge 158:1c57384330a6 880
AnnaBridge 158:1c57384330a6 881 #define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN)
AnnaBridge 158:1c57384330a6 882
AnnaBridge 158:1c57384330a6 883 /**
AnnaBridge 158:1c57384330a6 884 * @}
AnnaBridge 158:1c57384330a6 885 */
AnnaBridge 158:1c57384330a6 886
AnnaBridge 158:1c57384330a6 887 /** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
AnnaBridge 158:1c57384330a6 888 * @brief Enable or disable the AHB3 peripheral clock.
AnnaBridge 158:1c57384330a6 889 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 158:1c57384330a6 890 * is disabled and the application software has to enable this clock before
AnnaBridge 158:1c57384330a6 891 * using it.
AnnaBridge 158:1c57384330a6 892 * @{
AnnaBridge 158:1c57384330a6 893 */
AnnaBridge 158:1c57384330a6 894
AnnaBridge 158:1c57384330a6 895 #if defined(FMC_BANK1)
AnnaBridge 158:1c57384330a6 896 #define __HAL_RCC_FMC_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 897 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 898 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
AnnaBridge 158:1c57384330a6 899 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 900 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
AnnaBridge 158:1c57384330a6 901 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 902 } while(0)
AnnaBridge 158:1c57384330a6 903 #endif /* FMC_BANK1 */
AnnaBridge 158:1c57384330a6 904
AnnaBridge 158:1c57384330a6 905 #if defined(QUADSPI)
AnnaBridge 158:1c57384330a6 906 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 907 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 908 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
AnnaBridge 158:1c57384330a6 909 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 910 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
AnnaBridge 158:1c57384330a6 911 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 912 } while(0)
AnnaBridge 158:1c57384330a6 913 #endif /* QUADSPI */
AnnaBridge 158:1c57384330a6 914
AnnaBridge 158:1c57384330a6 915 #if defined(FMC_BANK1)
AnnaBridge 158:1c57384330a6 916 #define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN)
AnnaBridge 158:1c57384330a6 917 #endif /* FMC_BANK1 */
AnnaBridge 158:1c57384330a6 918
AnnaBridge 158:1c57384330a6 919 #if defined(QUADSPI)
AnnaBridge 158:1c57384330a6 920 #define __HAL_RCC_QSPI_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN)
AnnaBridge 158:1c57384330a6 921 #endif /* QUADSPI */
AnnaBridge 158:1c57384330a6 922
AnnaBridge 158:1c57384330a6 923 /**
AnnaBridge 158:1c57384330a6 924 * @}
AnnaBridge 158:1c57384330a6 925 */
AnnaBridge 158:1c57384330a6 926
AnnaBridge 158:1c57384330a6 927 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
AnnaBridge 158:1c57384330a6 928 * @brief Enable or disable the APB1 peripheral clock.
AnnaBridge 158:1c57384330a6 929 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 158:1c57384330a6 930 * is disabled and the application software has to enable this clock before
AnnaBridge 158:1c57384330a6 931 * using it.
AnnaBridge 158:1c57384330a6 932 * @{
AnnaBridge 158:1c57384330a6 933 */
AnnaBridge 158:1c57384330a6 934
AnnaBridge 158:1c57384330a6 935 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 936 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 937 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
AnnaBridge 158:1c57384330a6 938 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 939 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
AnnaBridge 158:1c57384330a6 940 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 941 } while(0)
AnnaBridge 158:1c57384330a6 942
AnnaBridge 158:1c57384330a6 943 #if defined(TIM3)
AnnaBridge 158:1c57384330a6 944 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 945 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 946 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
AnnaBridge 158:1c57384330a6 947 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 948 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
AnnaBridge 158:1c57384330a6 949 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 950 } while(0)
AnnaBridge 158:1c57384330a6 951 #endif /* TIM3 */
AnnaBridge 158:1c57384330a6 952
AnnaBridge 158:1c57384330a6 953 #if defined(TIM4)
AnnaBridge 158:1c57384330a6 954 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 955 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 956 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
AnnaBridge 158:1c57384330a6 957 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 958 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
AnnaBridge 158:1c57384330a6 959 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 960 } while(0)
AnnaBridge 158:1c57384330a6 961 #endif /* TIM4 */
AnnaBridge 158:1c57384330a6 962
AnnaBridge 158:1c57384330a6 963 #if defined(TIM5)
AnnaBridge 158:1c57384330a6 964 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 965 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 966 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
AnnaBridge 158:1c57384330a6 967 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 968 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
AnnaBridge 158:1c57384330a6 969 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 970 } while(0)
AnnaBridge 158:1c57384330a6 971 #endif /* TIM5 */
AnnaBridge 158:1c57384330a6 972
AnnaBridge 158:1c57384330a6 973 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 974 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 975 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
AnnaBridge 158:1c57384330a6 976 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 977 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
AnnaBridge 158:1c57384330a6 978 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 979 } while(0)
AnnaBridge 158:1c57384330a6 980
AnnaBridge 158:1c57384330a6 981 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 982 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 983 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
AnnaBridge 158:1c57384330a6 984 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 985 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
AnnaBridge 158:1c57384330a6 986 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 987 } while(0)
AnnaBridge 158:1c57384330a6 988
AnnaBridge 158:1c57384330a6 989 #if defined(LCD)
AnnaBridge 158:1c57384330a6 990 #define __HAL_RCC_LCD_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 991 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 992 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \
AnnaBridge 158:1c57384330a6 993 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 994 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \
AnnaBridge 158:1c57384330a6 995 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 996 } while(0)
AnnaBridge 158:1c57384330a6 997 #endif /* LCD */
AnnaBridge 158:1c57384330a6 998
AnnaBridge 158:1c57384330a6 999 #if defined(RCC_APB1ENR1_RTCAPBEN)
AnnaBridge 158:1c57384330a6 1000 #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 1001 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 1002 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \
AnnaBridge 158:1c57384330a6 1003 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 1004 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \
AnnaBridge 158:1c57384330a6 1005 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 1006 } while(0)
AnnaBridge 158:1c57384330a6 1007 #endif /* RCC_APB1ENR1_RTCAPBEN */
AnnaBridge 158:1c57384330a6 1008
AnnaBridge 158:1c57384330a6 1009 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 1010 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 1011 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
AnnaBridge 158:1c57384330a6 1012 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 1013 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
AnnaBridge 158:1c57384330a6 1014 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 1015 } while(0)
AnnaBridge 158:1c57384330a6 1016
AnnaBridge 158:1c57384330a6 1017 #if defined(SPI2)
AnnaBridge 158:1c57384330a6 1018 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 1019 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 1020 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
AnnaBridge 158:1c57384330a6 1021 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 1022 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
AnnaBridge 158:1c57384330a6 1023 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 1024 } while(0)
AnnaBridge 158:1c57384330a6 1025 #endif /* SPI2 */
AnnaBridge 158:1c57384330a6 1026
AnnaBridge 158:1c57384330a6 1027 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 1028 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 1029 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
AnnaBridge 158:1c57384330a6 1030 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 1031 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
AnnaBridge 158:1c57384330a6 1032 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 1033 } while(0)
AnnaBridge 158:1c57384330a6 1034
AnnaBridge 158:1c57384330a6 1035 #define __HAL_RCC_USART2_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 1036 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 1037 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
AnnaBridge 158:1c57384330a6 1038 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 1039 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
AnnaBridge 158:1c57384330a6 1040 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 1041 } while(0)
AnnaBridge 158:1c57384330a6 1042
AnnaBridge 158:1c57384330a6 1043 #if defined(USART3)
AnnaBridge 158:1c57384330a6 1044 #define __HAL_RCC_USART3_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 1045 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 1046 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
AnnaBridge 158:1c57384330a6 1047 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 1048 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
AnnaBridge 158:1c57384330a6 1049 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 1050 } while(0)
AnnaBridge 158:1c57384330a6 1051 #endif /* USART3 */
AnnaBridge 158:1c57384330a6 1052
AnnaBridge 158:1c57384330a6 1053 #if defined(UART4)
AnnaBridge 158:1c57384330a6 1054 #define __HAL_RCC_UART4_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 1055 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 1056 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
AnnaBridge 158:1c57384330a6 1057 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 1058 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
AnnaBridge 158:1c57384330a6 1059 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 1060 } while(0)
AnnaBridge 158:1c57384330a6 1061 #endif /* UART4 */
AnnaBridge 158:1c57384330a6 1062
AnnaBridge 158:1c57384330a6 1063 #if defined(UART5)
AnnaBridge 158:1c57384330a6 1064 #define __HAL_RCC_UART5_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 1065 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 1066 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
AnnaBridge 158:1c57384330a6 1067 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 1068 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
AnnaBridge 158:1c57384330a6 1069 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 1070 } while(0)
AnnaBridge 158:1c57384330a6 1071 #endif /* UART5 */
AnnaBridge 158:1c57384330a6 1072
AnnaBridge 158:1c57384330a6 1073 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 1074 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 1075 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
AnnaBridge 158:1c57384330a6 1076 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 1077 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
AnnaBridge 158:1c57384330a6 1078 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 1079 } while(0)
AnnaBridge 158:1c57384330a6 1080
AnnaBridge 158:1c57384330a6 1081 #if defined(I2C2)
AnnaBridge 158:1c57384330a6 1082 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 1083 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 1084 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
AnnaBridge 158:1c57384330a6 1085 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 1086 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
AnnaBridge 158:1c57384330a6 1087 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 1088 } while(0)
AnnaBridge 158:1c57384330a6 1089 #endif /* I2C2 */
AnnaBridge 158:1c57384330a6 1090
AnnaBridge 158:1c57384330a6 1091 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 1092 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 1093 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
AnnaBridge 158:1c57384330a6 1094 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 1095 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
AnnaBridge 158:1c57384330a6 1096 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 1097 } while(0)
AnnaBridge 158:1c57384330a6 1098
AnnaBridge 158:1c57384330a6 1099 #if defined(I2C4)
AnnaBridge 158:1c57384330a6 1100 #define __HAL_RCC_I2C4_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 1101 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 1102 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \
AnnaBridge 158:1c57384330a6 1103 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 1104 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \
AnnaBridge 158:1c57384330a6 1105 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 1106 } while(0)
AnnaBridge 158:1c57384330a6 1107 #endif /* I2C4 */
AnnaBridge 158:1c57384330a6 1108
AnnaBridge 158:1c57384330a6 1109 #if defined(CRS)
AnnaBridge 158:1c57384330a6 1110 #define __HAL_RCC_CRS_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 1111 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 1112 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \
AnnaBridge 158:1c57384330a6 1113 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 1114 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \
AnnaBridge 158:1c57384330a6 1115 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 1116 } while(0)
AnnaBridge 158:1c57384330a6 1117 #endif /* CRS */
AnnaBridge 158:1c57384330a6 1118
AnnaBridge 158:1c57384330a6 1119 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 1120 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 1121 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \
AnnaBridge 158:1c57384330a6 1122 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 1123 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \
AnnaBridge 158:1c57384330a6 1124 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 1125 } while(0)
AnnaBridge 158:1c57384330a6 1126
AnnaBridge 158:1c57384330a6 1127 #if defined(CAN2)
AnnaBridge 158:1c57384330a6 1128 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 1129 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 1130 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN); \
AnnaBridge 158:1c57384330a6 1131 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 1132 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN); \
AnnaBridge 158:1c57384330a6 1133 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 1134 } while(0)
AnnaBridge 158:1c57384330a6 1135 #endif /* CAN2 */
AnnaBridge 158:1c57384330a6 1136
AnnaBridge 158:1c57384330a6 1137 #if defined(USB)
AnnaBridge 158:1c57384330a6 1138 #define __HAL_RCC_USB_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 1139 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 1140 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); \
AnnaBridge 158:1c57384330a6 1141 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 1142 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); \
AnnaBridge 158:1c57384330a6 1143 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 1144 } while(0)
AnnaBridge 158:1c57384330a6 1145 #endif /* USB */
AnnaBridge 158:1c57384330a6 1146
AnnaBridge 158:1c57384330a6 1147 #define __HAL_RCC_PWR_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 1148 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 1149 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
AnnaBridge 158:1c57384330a6 1150 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 1151 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
AnnaBridge 158:1c57384330a6 1152 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 1153 } while(0)
AnnaBridge 158:1c57384330a6 1154
AnnaBridge 158:1c57384330a6 1155 #define __HAL_RCC_DAC1_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 1156 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 1157 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \
AnnaBridge 158:1c57384330a6 1158 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 1159 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \
AnnaBridge 158:1c57384330a6 1160 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 1161 } while(0)
AnnaBridge 158:1c57384330a6 1162
AnnaBridge 158:1c57384330a6 1163 #define __HAL_RCC_OPAMP_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 1164 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 1165 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \
AnnaBridge 158:1c57384330a6 1166 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 1167 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \
AnnaBridge 158:1c57384330a6 1168 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 1169 } while(0)
AnnaBridge 158:1c57384330a6 1170
AnnaBridge 158:1c57384330a6 1171 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 1172 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 1173 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
AnnaBridge 158:1c57384330a6 1174 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 1175 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
AnnaBridge 158:1c57384330a6 1176 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 1177 } while(0)
AnnaBridge 158:1c57384330a6 1178
AnnaBridge 158:1c57384330a6 1179 #define __HAL_RCC_LPUART1_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 1180 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 1181 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
AnnaBridge 158:1c57384330a6 1182 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 1183 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
AnnaBridge 158:1c57384330a6 1184 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 1185 } while(0)
AnnaBridge 158:1c57384330a6 1186
AnnaBridge 158:1c57384330a6 1187 #if defined(SWPMI1)
AnnaBridge 158:1c57384330a6 1188 #define __HAL_RCC_SWPMI1_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 1189 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 1190 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \
AnnaBridge 158:1c57384330a6 1191 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 1192 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \
AnnaBridge 158:1c57384330a6 1193 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 1194 } while(0)
AnnaBridge 158:1c57384330a6 1195 #endif /* SWPMI1 */
AnnaBridge 158:1c57384330a6 1196
AnnaBridge 158:1c57384330a6 1197 #define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 1198 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 1199 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
AnnaBridge 158:1c57384330a6 1200 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 1201 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
AnnaBridge 158:1c57384330a6 1202 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 1203 } while(0)
AnnaBridge 158:1c57384330a6 1204
AnnaBridge 158:1c57384330a6 1205
AnnaBridge 158:1c57384330a6 1206 #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN)
AnnaBridge 158:1c57384330a6 1207
AnnaBridge 158:1c57384330a6 1208 #if defined(TIM3)
AnnaBridge 158:1c57384330a6 1209 #define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN)
AnnaBridge 158:1c57384330a6 1210 #endif /* TIM3 */
AnnaBridge 158:1c57384330a6 1211
AnnaBridge 158:1c57384330a6 1212 #if defined(TIM4)
AnnaBridge 158:1c57384330a6 1213 #define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN)
AnnaBridge 158:1c57384330a6 1214 #endif /* TIM4 */
AnnaBridge 158:1c57384330a6 1215
AnnaBridge 158:1c57384330a6 1216 #if defined(TIM5)
AnnaBridge 158:1c57384330a6 1217 #define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN)
AnnaBridge 158:1c57384330a6 1218 #endif /* TIM5 */
AnnaBridge 158:1c57384330a6 1219
AnnaBridge 158:1c57384330a6 1220 #define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN)
AnnaBridge 158:1c57384330a6 1221
AnnaBridge 158:1c57384330a6 1222 #define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN)
AnnaBridge 158:1c57384330a6 1223
AnnaBridge 158:1c57384330a6 1224 #if defined(LCD)
AnnaBridge 158:1c57384330a6 1225 #define __HAL_RCC_LCD_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN);
AnnaBridge 158:1c57384330a6 1226 #endif /* LCD */
AnnaBridge 158:1c57384330a6 1227
AnnaBridge 158:1c57384330a6 1228 #if defined(RCC_APB1ENR1_RTCAPBEN)
AnnaBridge 158:1c57384330a6 1229 #define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN);
AnnaBridge 158:1c57384330a6 1230 #endif /* RCC_APB1ENR1_RTCAPBEN */
AnnaBridge 158:1c57384330a6 1231
AnnaBridge 158:1c57384330a6 1232 #if defined(SPI2)
AnnaBridge 158:1c57384330a6 1233 #define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN)
AnnaBridge 158:1c57384330a6 1234 #endif /* SPI2 */
AnnaBridge 158:1c57384330a6 1235
AnnaBridge 158:1c57384330a6 1236 #define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN)
AnnaBridge 158:1c57384330a6 1237
AnnaBridge 158:1c57384330a6 1238 #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN)
AnnaBridge 158:1c57384330a6 1239
AnnaBridge 158:1c57384330a6 1240 #if defined(USART3)
AnnaBridge 158:1c57384330a6 1241 #define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN)
AnnaBridge 158:1c57384330a6 1242 #endif /* USART3 */
AnnaBridge 158:1c57384330a6 1243
AnnaBridge 158:1c57384330a6 1244 #if defined(UART4)
AnnaBridge 158:1c57384330a6 1245 #define __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN)
AnnaBridge 158:1c57384330a6 1246 #endif /* UART4 */
AnnaBridge 158:1c57384330a6 1247
AnnaBridge 158:1c57384330a6 1248 #if defined(UART5)
AnnaBridge 158:1c57384330a6 1249 #define __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN)
AnnaBridge 158:1c57384330a6 1250 #endif /* UART5 */
AnnaBridge 158:1c57384330a6 1251
AnnaBridge 158:1c57384330a6 1252 #define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN)
AnnaBridge 158:1c57384330a6 1253
AnnaBridge 158:1c57384330a6 1254 #if defined(I2C2)
AnnaBridge 158:1c57384330a6 1255 #define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN)
AnnaBridge 158:1c57384330a6 1256 #endif /* I2C2 */
AnnaBridge 158:1c57384330a6 1257
AnnaBridge 158:1c57384330a6 1258 #define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN)
AnnaBridge 158:1c57384330a6 1259
AnnaBridge 158:1c57384330a6 1260 #if defined(I2C4)
AnnaBridge 158:1c57384330a6 1261 #define __HAL_RCC_I2C4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN)
AnnaBridge 158:1c57384330a6 1262 #endif /* I2C4 */
AnnaBridge 158:1c57384330a6 1263
AnnaBridge 158:1c57384330a6 1264 #if defined(CRS)
AnnaBridge 158:1c57384330a6 1265 #define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN);
AnnaBridge 158:1c57384330a6 1266 #endif /* CRS */
AnnaBridge 158:1c57384330a6 1267
AnnaBridge 158:1c57384330a6 1268 #define __HAL_RCC_CAN1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN)
AnnaBridge 158:1c57384330a6 1269
AnnaBridge 158:1c57384330a6 1270 #if defined(CAN2)
AnnaBridge 158:1c57384330a6 1271 #define __HAL_RCC_CAN2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN)
AnnaBridge 158:1c57384330a6 1272 #endif /* CAN2 */
AnnaBridge 158:1c57384330a6 1273
AnnaBridge 158:1c57384330a6 1274 #if defined(USB)
AnnaBridge 158:1c57384330a6 1275 #define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN);
AnnaBridge 158:1c57384330a6 1276 #endif /* USB */
AnnaBridge 158:1c57384330a6 1277
AnnaBridge 158:1c57384330a6 1278 #define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN)
AnnaBridge 158:1c57384330a6 1279
AnnaBridge 158:1c57384330a6 1280 #define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN)
AnnaBridge 158:1c57384330a6 1281
AnnaBridge 158:1c57384330a6 1282 #define __HAL_RCC_OPAMP_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN)
AnnaBridge 158:1c57384330a6 1283
AnnaBridge 158:1c57384330a6 1284 #define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN)
AnnaBridge 158:1c57384330a6 1285
AnnaBridge 158:1c57384330a6 1286 #define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN)
AnnaBridge 158:1c57384330a6 1287
AnnaBridge 158:1c57384330a6 1288 #if defined(SWPMI1)
AnnaBridge 158:1c57384330a6 1289 #define __HAL_RCC_SWPMI1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN)
AnnaBridge 158:1c57384330a6 1290 #endif /* SWPMI1 */
AnnaBridge 158:1c57384330a6 1291
AnnaBridge 158:1c57384330a6 1292 #define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN)
AnnaBridge 158:1c57384330a6 1293
AnnaBridge 158:1c57384330a6 1294 /**
AnnaBridge 158:1c57384330a6 1295 * @}
AnnaBridge 158:1c57384330a6 1296 */
AnnaBridge 158:1c57384330a6 1297
AnnaBridge 158:1c57384330a6 1298 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
AnnaBridge 158:1c57384330a6 1299 * @brief Enable or disable the APB2 peripheral clock.
AnnaBridge 158:1c57384330a6 1300 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 158:1c57384330a6 1301 * is disabled and the application software has to enable this clock before
AnnaBridge 158:1c57384330a6 1302 * using it.
AnnaBridge 158:1c57384330a6 1303 * @{
AnnaBridge 158:1c57384330a6 1304 */
AnnaBridge 158:1c57384330a6 1305
AnnaBridge 158:1c57384330a6 1306 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 1307 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 1308 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
AnnaBridge 158:1c57384330a6 1309 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 1310 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
AnnaBridge 158:1c57384330a6 1311 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 1312 } while(0)
AnnaBridge 158:1c57384330a6 1313
AnnaBridge 158:1c57384330a6 1314 #define __HAL_RCC_FIREWALL_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 1315 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 1316 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \
AnnaBridge 158:1c57384330a6 1317 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 1318 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \
AnnaBridge 158:1c57384330a6 1319 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 1320 } while(0)
AnnaBridge 158:1c57384330a6 1321
AnnaBridge 158:1c57384330a6 1322 #if defined(SDMMC1)
AnnaBridge 158:1c57384330a6 1323 #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 1324 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 1325 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \
AnnaBridge 158:1c57384330a6 1326 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 1327 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \
AnnaBridge 158:1c57384330a6 1328 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 1329 } while(0)
AnnaBridge 158:1c57384330a6 1330 #endif /* SDMMC1 */
AnnaBridge 158:1c57384330a6 1331
AnnaBridge 158:1c57384330a6 1332 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 1333 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 1334 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
AnnaBridge 158:1c57384330a6 1335 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 1336 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
AnnaBridge 158:1c57384330a6 1337 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 1338 } while(0)
AnnaBridge 158:1c57384330a6 1339
AnnaBridge 158:1c57384330a6 1340 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 1341 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 1342 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
AnnaBridge 158:1c57384330a6 1343 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 1344 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
AnnaBridge 158:1c57384330a6 1345 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 1346 } while(0)
AnnaBridge 158:1c57384330a6 1347
AnnaBridge 158:1c57384330a6 1348 #if defined(TIM8)
AnnaBridge 158:1c57384330a6 1349 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 1350 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 1351 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
AnnaBridge 158:1c57384330a6 1352 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 1353 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
AnnaBridge 158:1c57384330a6 1354 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 1355 } while(0)
AnnaBridge 158:1c57384330a6 1356 #endif /* TIM8 */
AnnaBridge 158:1c57384330a6 1357
AnnaBridge 158:1c57384330a6 1358 #define __HAL_RCC_USART1_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 1359 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 1360 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
AnnaBridge 158:1c57384330a6 1361 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 1362 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
AnnaBridge 158:1c57384330a6 1363 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 1364 } while(0)
AnnaBridge 158:1c57384330a6 1365
AnnaBridge 158:1c57384330a6 1366
AnnaBridge 158:1c57384330a6 1367 #define __HAL_RCC_TIM15_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 1368 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 1369 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
AnnaBridge 158:1c57384330a6 1370 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 1371 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
AnnaBridge 158:1c57384330a6 1372 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 1373 } while(0)
AnnaBridge 158:1c57384330a6 1374
AnnaBridge 158:1c57384330a6 1375 #define __HAL_RCC_TIM16_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 1376 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 1377 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
AnnaBridge 158:1c57384330a6 1378 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 1379 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
AnnaBridge 158:1c57384330a6 1380 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 1381 } while(0)
AnnaBridge 158:1c57384330a6 1382
AnnaBridge 158:1c57384330a6 1383 #if defined(TIM17)
AnnaBridge 158:1c57384330a6 1384 #define __HAL_RCC_TIM17_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 1385 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 1386 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
AnnaBridge 158:1c57384330a6 1387 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 1388 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
AnnaBridge 158:1c57384330a6 1389 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 1390 } while(0)
AnnaBridge 158:1c57384330a6 1391 #endif /* TIM17 */
AnnaBridge 158:1c57384330a6 1392
AnnaBridge 158:1c57384330a6 1393 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 1394 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 1395 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
AnnaBridge 158:1c57384330a6 1396 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 1397 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
AnnaBridge 158:1c57384330a6 1398 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 1399 } while(0)
AnnaBridge 158:1c57384330a6 1400
AnnaBridge 158:1c57384330a6 1401 #if defined(SAI2)
AnnaBridge 158:1c57384330a6 1402 #define __HAL_RCC_SAI2_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 1403 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 1404 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \
AnnaBridge 158:1c57384330a6 1405 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 1406 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \
AnnaBridge 158:1c57384330a6 1407 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 1408 } while(0)
AnnaBridge 158:1c57384330a6 1409 #endif /* SAI2 */
AnnaBridge 158:1c57384330a6 1410
AnnaBridge 158:1c57384330a6 1411 #if defined(DFSDM1_Filter0)
AnnaBridge 158:1c57384330a6 1412 #define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \
AnnaBridge 158:1c57384330a6 1413 __IO uint32_t tmpreg; \
AnnaBridge 158:1c57384330a6 1414 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \
AnnaBridge 158:1c57384330a6 1415 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 158:1c57384330a6 1416 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \
AnnaBridge 158:1c57384330a6 1417 UNUSED(tmpreg); \
AnnaBridge 158:1c57384330a6 1418 } while(0)
AnnaBridge 158:1c57384330a6 1419 #endif /* DFSDM1_Filter0 */
AnnaBridge 158:1c57384330a6 1420
AnnaBridge 158:1c57384330a6 1421
AnnaBridge 158:1c57384330a6 1422 #define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN)
AnnaBridge 158:1c57384330a6 1423
AnnaBridge 158:1c57384330a6 1424 #if defined(SDMMC1)
AnnaBridge 158:1c57384330a6 1425 #define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN)
AnnaBridge 158:1c57384330a6 1426 #endif /* SDMMC1 */
AnnaBridge 158:1c57384330a6 1427
AnnaBridge 158:1c57384330a6 1428 #define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN)
AnnaBridge 158:1c57384330a6 1429
AnnaBridge 158:1c57384330a6 1430 #define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN)
AnnaBridge 158:1c57384330a6 1431
AnnaBridge 158:1c57384330a6 1432 #if defined(TIM8)
AnnaBridge 158:1c57384330a6 1433 #define __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN)
AnnaBridge 158:1c57384330a6 1434 #endif /* TIM8 */
AnnaBridge 158:1c57384330a6 1435
AnnaBridge 158:1c57384330a6 1436 #define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN)
AnnaBridge 158:1c57384330a6 1437
AnnaBridge 158:1c57384330a6 1438 #define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN)
AnnaBridge 158:1c57384330a6 1439
AnnaBridge 158:1c57384330a6 1440 #define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN)
AnnaBridge 158:1c57384330a6 1441
AnnaBridge 158:1c57384330a6 1442 #if defined(TIM17)
AnnaBridge 158:1c57384330a6 1443 #define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN)
AnnaBridge 158:1c57384330a6 1444 #endif /* TIM17 */
AnnaBridge 158:1c57384330a6 1445
AnnaBridge 158:1c57384330a6 1446 #define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN)
AnnaBridge 158:1c57384330a6 1447
AnnaBridge 158:1c57384330a6 1448 #if defined(SAI2)
AnnaBridge 158:1c57384330a6 1449 #define __HAL_RCC_SAI2_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN)
AnnaBridge 158:1c57384330a6 1450 #endif /* SAI2 */
AnnaBridge 158:1c57384330a6 1451
AnnaBridge 158:1c57384330a6 1452 #if defined(DFSDM1_Filter0)
AnnaBridge 158:1c57384330a6 1453 #define __HAL_RCC_DFSDM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN)
AnnaBridge 158:1c57384330a6 1454 #endif /* DFSDM1_Filter0 */
AnnaBridge 158:1c57384330a6 1455
AnnaBridge 158:1c57384330a6 1456 /**
AnnaBridge 158:1c57384330a6 1457 * @}
AnnaBridge 158:1c57384330a6 1458 */
AnnaBridge 158:1c57384330a6 1459
AnnaBridge 158:1c57384330a6 1460 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status
AnnaBridge 158:1c57384330a6 1461 * @brief Check whether the AHB1 peripheral clock is enabled or not.
AnnaBridge 158:1c57384330a6 1462 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 158:1c57384330a6 1463 * is disabled and the application software has to enable this clock before
AnnaBridge 158:1c57384330a6 1464 * using it.
AnnaBridge 158:1c57384330a6 1465 * @{
AnnaBridge 158:1c57384330a6 1466 */
AnnaBridge 158:1c57384330a6 1467
AnnaBridge 158:1c57384330a6 1468 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != RESET)
AnnaBridge 158:1c57384330a6 1469
AnnaBridge 158:1c57384330a6 1470 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != RESET)
AnnaBridge 158:1c57384330a6 1471
AnnaBridge 158:1c57384330a6 1472 #define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != RESET)
AnnaBridge 158:1c57384330a6 1473
AnnaBridge 158:1c57384330a6 1474 #define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != RESET)
AnnaBridge 158:1c57384330a6 1475
AnnaBridge 158:1c57384330a6 1476 #define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != RESET)
AnnaBridge 158:1c57384330a6 1477
AnnaBridge 158:1c57384330a6 1478 #if defined(DMA2D)
AnnaBridge 158:1c57384330a6 1479 #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) != RESET)
AnnaBridge 158:1c57384330a6 1480 #endif /* DMA2D */
AnnaBridge 158:1c57384330a6 1481
AnnaBridge 158:1c57384330a6 1482
AnnaBridge 158:1c57384330a6 1483 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == RESET)
AnnaBridge 158:1c57384330a6 1484
AnnaBridge 158:1c57384330a6 1485 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == RESET)
AnnaBridge 158:1c57384330a6 1486
AnnaBridge 158:1c57384330a6 1487 #define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == RESET)
AnnaBridge 158:1c57384330a6 1488
AnnaBridge 158:1c57384330a6 1489 #define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == RESET)
AnnaBridge 158:1c57384330a6 1490
AnnaBridge 158:1c57384330a6 1491 #define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) == RESET)
AnnaBridge 158:1c57384330a6 1492
AnnaBridge 158:1c57384330a6 1493 #if defined(DMA2D)
AnnaBridge 158:1c57384330a6 1494 #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) == RESET)
AnnaBridge 158:1c57384330a6 1495 #endif /* DMA2D */
AnnaBridge 158:1c57384330a6 1496
AnnaBridge 158:1c57384330a6 1497 /**
AnnaBridge 158:1c57384330a6 1498 * @}
AnnaBridge 158:1c57384330a6 1499 */
AnnaBridge 158:1c57384330a6 1500
AnnaBridge 158:1c57384330a6 1501 /** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status
AnnaBridge 158:1c57384330a6 1502 * @brief Check whether the AHB2 peripheral clock is enabled or not.
AnnaBridge 158:1c57384330a6 1503 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 158:1c57384330a6 1504 * is disabled and the application software has to enable this clock before
AnnaBridge 158:1c57384330a6 1505 * using it.
AnnaBridge 158:1c57384330a6 1506 * @{
AnnaBridge 158:1c57384330a6 1507 */
AnnaBridge 158:1c57384330a6 1508
AnnaBridge 158:1c57384330a6 1509 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != RESET)
AnnaBridge 158:1c57384330a6 1510
AnnaBridge 158:1c57384330a6 1511 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET)
AnnaBridge 158:1c57384330a6 1512
AnnaBridge 158:1c57384330a6 1513 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET)
AnnaBridge 158:1c57384330a6 1514
AnnaBridge 158:1c57384330a6 1515 #if defined(GPIOD)
AnnaBridge 158:1c57384330a6 1516 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != RESET)
AnnaBridge 158:1c57384330a6 1517 #endif /* GPIOD */
AnnaBridge 158:1c57384330a6 1518
AnnaBridge 158:1c57384330a6 1519 #if defined(GPIOE)
AnnaBridge 158:1c57384330a6 1520 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != RESET)
AnnaBridge 158:1c57384330a6 1521 #endif /* GPIOE */
AnnaBridge 158:1c57384330a6 1522
AnnaBridge 158:1c57384330a6 1523 #if defined(GPIOF)
AnnaBridge 158:1c57384330a6 1524 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != RESET)
AnnaBridge 158:1c57384330a6 1525 #endif /* GPIOF */
AnnaBridge 158:1c57384330a6 1526
AnnaBridge 158:1c57384330a6 1527 #if defined(GPIOG)
AnnaBridge 158:1c57384330a6 1528 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != RESET)
AnnaBridge 158:1c57384330a6 1529 #endif /* GPIOG */
AnnaBridge 158:1c57384330a6 1530
AnnaBridge 158:1c57384330a6 1531 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) != RESET)
AnnaBridge 158:1c57384330a6 1532
AnnaBridge 158:1c57384330a6 1533 #if defined(GPIOI)
AnnaBridge 158:1c57384330a6 1534 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) != RESET)
AnnaBridge 158:1c57384330a6 1535 #endif /* GPIOI */
AnnaBridge 158:1c57384330a6 1536
AnnaBridge 158:1c57384330a6 1537 #if defined(USB_OTG_FS)
AnnaBridge 158:1c57384330a6 1538 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) != RESET)
AnnaBridge 158:1c57384330a6 1539 #endif /* USB_OTG_FS */
AnnaBridge 158:1c57384330a6 1540
AnnaBridge 158:1c57384330a6 1541 #define __HAL_RCC_ADC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != RESET)
AnnaBridge 158:1c57384330a6 1542
AnnaBridge 158:1c57384330a6 1543 #if defined(DCMI)
AnnaBridge 158:1c57384330a6 1544 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) != RESET)
AnnaBridge 158:1c57384330a6 1545 #endif /* DCMI */
AnnaBridge 158:1c57384330a6 1546
AnnaBridge 158:1c57384330a6 1547 #if defined(AES)
AnnaBridge 158:1c57384330a6 1548 #define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != RESET)
AnnaBridge 158:1c57384330a6 1549 #endif /* AES */
AnnaBridge 158:1c57384330a6 1550
AnnaBridge 158:1c57384330a6 1551 #if defined(HASH)
AnnaBridge 158:1c57384330a6 1552 #define __HAL_RCC_HASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) != RESET)
AnnaBridge 158:1c57384330a6 1553 #endif /* HASH */
AnnaBridge 158:1c57384330a6 1554
AnnaBridge 158:1c57384330a6 1555 #define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != RESET)
AnnaBridge 158:1c57384330a6 1556
AnnaBridge 158:1c57384330a6 1557
AnnaBridge 158:1c57384330a6 1558 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == RESET)
AnnaBridge 158:1c57384330a6 1559
AnnaBridge 158:1c57384330a6 1560 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == RESET)
AnnaBridge 158:1c57384330a6 1561
AnnaBridge 158:1c57384330a6 1562 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == RESET)
AnnaBridge 158:1c57384330a6 1563
AnnaBridge 158:1c57384330a6 1564 #if defined(GPIOD)
AnnaBridge 158:1c57384330a6 1565 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == RESET)
AnnaBridge 158:1c57384330a6 1566 #endif /* GPIOD */
AnnaBridge 158:1c57384330a6 1567
AnnaBridge 158:1c57384330a6 1568 #if defined(GPIOE)
AnnaBridge 158:1c57384330a6 1569 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == RESET)
AnnaBridge 158:1c57384330a6 1570 #endif /* GPIOE */
AnnaBridge 158:1c57384330a6 1571
AnnaBridge 158:1c57384330a6 1572 #if defined(GPIOF)
AnnaBridge 158:1c57384330a6 1573 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == RESET)
AnnaBridge 158:1c57384330a6 1574 #endif /* GPIOF */
AnnaBridge 158:1c57384330a6 1575
AnnaBridge 158:1c57384330a6 1576 #if defined(GPIOG)
AnnaBridge 158:1c57384330a6 1577 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == RESET)
AnnaBridge 158:1c57384330a6 1578 #endif /* GPIOG */
AnnaBridge 158:1c57384330a6 1579
AnnaBridge 158:1c57384330a6 1580 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) == RESET)
AnnaBridge 158:1c57384330a6 1581
AnnaBridge 158:1c57384330a6 1582 #if defined(GPIOI)
AnnaBridge 158:1c57384330a6 1583 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) == RESET)
AnnaBridge 158:1c57384330a6 1584 #endif /* GPIOI */
AnnaBridge 158:1c57384330a6 1585
AnnaBridge 158:1c57384330a6 1586 #if defined(USB_OTG_FS)
AnnaBridge 158:1c57384330a6 1587 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) == RESET)
AnnaBridge 158:1c57384330a6 1588 #endif /* USB_OTG_FS */
AnnaBridge 158:1c57384330a6 1589
AnnaBridge 158:1c57384330a6 1590 #define __HAL_RCC_ADC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) == RESET)
AnnaBridge 158:1c57384330a6 1591
AnnaBridge 158:1c57384330a6 1592 #if defined(DCMI)
AnnaBridge 158:1c57384330a6 1593 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) == RESET)
AnnaBridge 158:1c57384330a6 1594 #endif /* DCMI */
AnnaBridge 158:1c57384330a6 1595
AnnaBridge 158:1c57384330a6 1596 #if defined(AES)
AnnaBridge 158:1c57384330a6 1597 #define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == RESET)
AnnaBridge 158:1c57384330a6 1598 #endif /* AES */
AnnaBridge 158:1c57384330a6 1599
AnnaBridge 158:1c57384330a6 1600 #if defined(HASH)
AnnaBridge 158:1c57384330a6 1601 #define __HAL_RCC_HASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) == RESET)
AnnaBridge 158:1c57384330a6 1602 #endif /* HASH */
AnnaBridge 158:1c57384330a6 1603
AnnaBridge 158:1c57384330a6 1604 #define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == RESET)
AnnaBridge 158:1c57384330a6 1605
AnnaBridge 158:1c57384330a6 1606 /**
AnnaBridge 158:1c57384330a6 1607 * @}
AnnaBridge 158:1c57384330a6 1608 */
AnnaBridge 158:1c57384330a6 1609
AnnaBridge 158:1c57384330a6 1610 /** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status
AnnaBridge 158:1c57384330a6 1611 * @brief Check whether the AHB3 peripheral clock is enabled or not.
AnnaBridge 158:1c57384330a6 1612 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 158:1c57384330a6 1613 * is disabled and the application software has to enable this clock before
AnnaBridge 158:1c57384330a6 1614 * using it.
AnnaBridge 158:1c57384330a6 1615 * @{
AnnaBridge 158:1c57384330a6 1616 */
AnnaBridge 158:1c57384330a6 1617
AnnaBridge 158:1c57384330a6 1618 #if defined(FMC_BANK1)
AnnaBridge 158:1c57384330a6 1619 #define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != RESET)
AnnaBridge 158:1c57384330a6 1620 #endif /* FMC_BANK1 */
AnnaBridge 158:1c57384330a6 1621
AnnaBridge 158:1c57384330a6 1622 #if defined(QUADSPI)
AnnaBridge 158:1c57384330a6 1623 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != RESET)
AnnaBridge 158:1c57384330a6 1624 #endif /* QUADSPI */
AnnaBridge 158:1c57384330a6 1625
AnnaBridge 158:1c57384330a6 1626 #if defined(FMC_BANK1)
AnnaBridge 158:1c57384330a6 1627 #define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == RESET)
AnnaBridge 158:1c57384330a6 1628 #endif /* FMC_BANK1 */
AnnaBridge 158:1c57384330a6 1629
AnnaBridge 158:1c57384330a6 1630 #if defined(QUADSPI)
AnnaBridge 158:1c57384330a6 1631 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == RESET)
AnnaBridge 158:1c57384330a6 1632 #endif /* QUADSPI */
AnnaBridge 158:1c57384330a6 1633
AnnaBridge 158:1c57384330a6 1634 /**
AnnaBridge 158:1c57384330a6 1635 * @}
AnnaBridge 158:1c57384330a6 1636 */
AnnaBridge 158:1c57384330a6 1637
AnnaBridge 158:1c57384330a6 1638 /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status
AnnaBridge 158:1c57384330a6 1639 * @brief Check whether the APB1 peripheral clock is enabled or not.
AnnaBridge 158:1c57384330a6 1640 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 158:1c57384330a6 1641 * is disabled and the application software has to enable this clock before
AnnaBridge 158:1c57384330a6 1642 * using it.
AnnaBridge 158:1c57384330a6 1643 * @{
AnnaBridge 158:1c57384330a6 1644 */
AnnaBridge 158:1c57384330a6 1645
AnnaBridge 158:1c57384330a6 1646 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != RESET)
AnnaBridge 158:1c57384330a6 1647
AnnaBridge 158:1c57384330a6 1648 #if defined(TIM3)
AnnaBridge 158:1c57384330a6 1649 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != RESET)
AnnaBridge 158:1c57384330a6 1650 #endif /* TIM3 */
AnnaBridge 158:1c57384330a6 1651
AnnaBridge 158:1c57384330a6 1652 #if defined(TIM4)
AnnaBridge 158:1c57384330a6 1653 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != RESET)
AnnaBridge 158:1c57384330a6 1654 #endif /* TIM4 */
AnnaBridge 158:1c57384330a6 1655
AnnaBridge 158:1c57384330a6 1656 #if defined(TIM5)
AnnaBridge 158:1c57384330a6 1657 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != RESET)
AnnaBridge 158:1c57384330a6 1658 #endif /* TIM5 */
AnnaBridge 158:1c57384330a6 1659
AnnaBridge 158:1c57384330a6 1660 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != RESET)
AnnaBridge 158:1c57384330a6 1661
AnnaBridge 158:1c57384330a6 1662 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != RESET)
AnnaBridge 158:1c57384330a6 1663
AnnaBridge 158:1c57384330a6 1664 #if defined(LCD)
AnnaBridge 158:1c57384330a6 1665 #define __HAL_RCC_LCD_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) != RESET)
AnnaBridge 158:1c57384330a6 1666 #endif /* LCD */
AnnaBridge 158:1c57384330a6 1667
AnnaBridge 158:1c57384330a6 1668 #if defined(RCC_APB1ENR1_RTCAPBEN)
AnnaBridge 158:1c57384330a6 1669 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) != RESET)
AnnaBridge 158:1c57384330a6 1670 #endif /* RCC_APB1ENR1_RTCAPBEN */
AnnaBridge 158:1c57384330a6 1671
AnnaBridge 158:1c57384330a6 1672 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != RESET)
AnnaBridge 158:1c57384330a6 1673
AnnaBridge 158:1c57384330a6 1674 #if defined(SPI2)
AnnaBridge 158:1c57384330a6 1675 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != RESET)
AnnaBridge 158:1c57384330a6 1676 #endif /* SPI2 */
AnnaBridge 158:1c57384330a6 1677
AnnaBridge 158:1c57384330a6 1678 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != RESET)
AnnaBridge 158:1c57384330a6 1679
AnnaBridge 158:1c57384330a6 1680 #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != RESET)
AnnaBridge 158:1c57384330a6 1681
AnnaBridge 158:1c57384330a6 1682 #if defined(USART3)
AnnaBridge 158:1c57384330a6 1683 #define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != RESET)
AnnaBridge 158:1c57384330a6 1684 #endif /* USART3 */
AnnaBridge 158:1c57384330a6 1685
AnnaBridge 158:1c57384330a6 1686 #if defined(UART4)
AnnaBridge 158:1c57384330a6 1687 #define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != RESET)
AnnaBridge 158:1c57384330a6 1688 #endif /* UART4 */
AnnaBridge 158:1c57384330a6 1689
AnnaBridge 158:1c57384330a6 1690 #if defined(UART5)
AnnaBridge 158:1c57384330a6 1691 #define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != RESET)
AnnaBridge 158:1c57384330a6 1692 #endif /* UART5 */
AnnaBridge 158:1c57384330a6 1693
AnnaBridge 158:1c57384330a6 1694 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != RESET)
AnnaBridge 158:1c57384330a6 1695
AnnaBridge 158:1c57384330a6 1696 #if defined(I2C2)
AnnaBridge 158:1c57384330a6 1697 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != RESET)
AnnaBridge 158:1c57384330a6 1698 #endif /* I2C2 */
AnnaBridge 158:1c57384330a6 1699
AnnaBridge 158:1c57384330a6 1700 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != RESET)
AnnaBridge 158:1c57384330a6 1701
AnnaBridge 158:1c57384330a6 1702 #if defined(I2C4)
AnnaBridge 158:1c57384330a6 1703 #define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != RESET)
AnnaBridge 158:1c57384330a6 1704 #endif /* I2C4 */
AnnaBridge 158:1c57384330a6 1705
AnnaBridge 158:1c57384330a6 1706 #if defined(CRS)
AnnaBridge 158:1c57384330a6 1707 #define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != RESET)
AnnaBridge 158:1c57384330a6 1708 #endif /* CRS */
AnnaBridge 158:1c57384330a6 1709
AnnaBridge 158:1c57384330a6 1710 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) != RESET)
AnnaBridge 158:1c57384330a6 1711
AnnaBridge 158:1c57384330a6 1712 #if defined(CAN2)
AnnaBridge 158:1c57384330a6 1713 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) != RESET)
AnnaBridge 158:1c57384330a6 1714 #endif /* CAN2 */
AnnaBridge 158:1c57384330a6 1715
AnnaBridge 158:1c57384330a6 1716 #if defined(USB)
AnnaBridge 158:1c57384330a6 1717 #define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) != RESET)
AnnaBridge 158:1c57384330a6 1718 #endif /* USB */
AnnaBridge 158:1c57384330a6 1719
AnnaBridge 158:1c57384330a6 1720 #define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != RESET)
AnnaBridge 158:1c57384330a6 1721
AnnaBridge 158:1c57384330a6 1722 #define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) != RESET)
AnnaBridge 158:1c57384330a6 1723
AnnaBridge 158:1c57384330a6 1724 #define __HAL_RCC_OPAMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) != RESET)
AnnaBridge 158:1c57384330a6 1725
AnnaBridge 158:1c57384330a6 1726 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != RESET)
AnnaBridge 158:1c57384330a6 1727
AnnaBridge 158:1c57384330a6 1728 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != RESET)
AnnaBridge 158:1c57384330a6 1729
AnnaBridge 158:1c57384330a6 1730 #if defined(SWPMI1)
AnnaBridge 158:1c57384330a6 1731 #define __HAL_RCC_SWPMI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) != RESET)
AnnaBridge 158:1c57384330a6 1732 #endif /* SWPMI1 */
AnnaBridge 158:1c57384330a6 1733
AnnaBridge 158:1c57384330a6 1734 #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != RESET)
AnnaBridge 158:1c57384330a6 1735
AnnaBridge 158:1c57384330a6 1736
AnnaBridge 158:1c57384330a6 1737 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == RESET)
AnnaBridge 158:1c57384330a6 1738
AnnaBridge 158:1c57384330a6 1739 #if defined(TIM3)
AnnaBridge 158:1c57384330a6 1740 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == RESET)
AnnaBridge 158:1c57384330a6 1741 #endif /* TIM3 */
AnnaBridge 158:1c57384330a6 1742
AnnaBridge 158:1c57384330a6 1743 #if defined(TIM4)
AnnaBridge 158:1c57384330a6 1744 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == RESET)
AnnaBridge 158:1c57384330a6 1745 #endif /* TIM4 */
AnnaBridge 158:1c57384330a6 1746
AnnaBridge 158:1c57384330a6 1747 #if defined(TIM5)
AnnaBridge 158:1c57384330a6 1748 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == RESET)
AnnaBridge 158:1c57384330a6 1749 #endif /* TIM5 */
AnnaBridge 158:1c57384330a6 1750
AnnaBridge 158:1c57384330a6 1751 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == RESET)
AnnaBridge 158:1c57384330a6 1752
AnnaBridge 158:1c57384330a6 1753 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == RESET)
AnnaBridge 158:1c57384330a6 1754
AnnaBridge 158:1c57384330a6 1755 #if defined(LCD)
AnnaBridge 158:1c57384330a6 1756 #define __HAL_RCC_LCD_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) == RESET)
AnnaBridge 158:1c57384330a6 1757 #endif /* LCD */
AnnaBridge 158:1c57384330a6 1758
AnnaBridge 158:1c57384330a6 1759 #if defined(RCC_APB1ENR1_RTCAPBEN)
AnnaBridge 158:1c57384330a6 1760 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) == RESET)
AnnaBridge 158:1c57384330a6 1761 #endif /* RCC_APB1ENR1_RTCAPBEN */
AnnaBridge 158:1c57384330a6 1762
AnnaBridge 158:1c57384330a6 1763 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == RESET)
AnnaBridge 158:1c57384330a6 1764
AnnaBridge 158:1c57384330a6 1765 #if defined(SPI2)
AnnaBridge 158:1c57384330a6 1766 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == RESET)
AnnaBridge 158:1c57384330a6 1767 #endif /* SPI2 */
AnnaBridge 158:1c57384330a6 1768
AnnaBridge 158:1c57384330a6 1769 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == RESET)
AnnaBridge 158:1c57384330a6 1770
AnnaBridge 158:1c57384330a6 1771 #define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == RESET)
AnnaBridge 158:1c57384330a6 1772
AnnaBridge 158:1c57384330a6 1773 #if defined(USART3)
AnnaBridge 158:1c57384330a6 1774 #define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == RESET)
AnnaBridge 158:1c57384330a6 1775 #endif /* USART3 */
AnnaBridge 158:1c57384330a6 1776
AnnaBridge 158:1c57384330a6 1777 #if defined(UART4)
AnnaBridge 158:1c57384330a6 1778 #define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == RESET)
AnnaBridge 158:1c57384330a6 1779 #endif /* UART4 */
AnnaBridge 158:1c57384330a6 1780
AnnaBridge 158:1c57384330a6 1781 #if defined(UART5)
AnnaBridge 158:1c57384330a6 1782 #define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == RESET)
AnnaBridge 158:1c57384330a6 1783 #endif /* UART5 */
AnnaBridge 158:1c57384330a6 1784
AnnaBridge 158:1c57384330a6 1785 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == RESET)
AnnaBridge 158:1c57384330a6 1786
AnnaBridge 158:1c57384330a6 1787 #if defined(I2C2)
AnnaBridge 158:1c57384330a6 1788 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == RESET)
AnnaBridge 158:1c57384330a6 1789 #endif /* I2C2 */
AnnaBridge 158:1c57384330a6 1790
AnnaBridge 158:1c57384330a6 1791 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == RESET)
AnnaBridge 158:1c57384330a6 1792
AnnaBridge 158:1c57384330a6 1793 #if defined(I2C4)
AnnaBridge 158:1c57384330a6 1794 #define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == RESET)
AnnaBridge 158:1c57384330a6 1795 #endif /* I2C4 */
AnnaBridge 158:1c57384330a6 1796
AnnaBridge 158:1c57384330a6 1797 #if defined(CRS)
AnnaBridge 158:1c57384330a6 1798 #define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == RESET)
AnnaBridge 158:1c57384330a6 1799 #endif /* CRS */
AnnaBridge 158:1c57384330a6 1800
AnnaBridge 158:1c57384330a6 1801 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) == RESET)
AnnaBridge 158:1c57384330a6 1802
AnnaBridge 158:1c57384330a6 1803 #if defined(CAN2)
AnnaBridge 158:1c57384330a6 1804 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) == RESET)
AnnaBridge 158:1c57384330a6 1805 #endif /* CAN2 */
AnnaBridge 158:1c57384330a6 1806
AnnaBridge 158:1c57384330a6 1807 #if defined(USB)
AnnaBridge 158:1c57384330a6 1808 #define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) == RESET)
AnnaBridge 158:1c57384330a6 1809 #endif /* USB */
AnnaBridge 158:1c57384330a6 1810
AnnaBridge 158:1c57384330a6 1811 #define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == RESET)
AnnaBridge 158:1c57384330a6 1812
AnnaBridge 158:1c57384330a6 1813 #define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) == RESET)
AnnaBridge 158:1c57384330a6 1814
AnnaBridge 158:1c57384330a6 1815 #define __HAL_RCC_OPAMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) == RESET)
AnnaBridge 158:1c57384330a6 1816
AnnaBridge 158:1c57384330a6 1817 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == RESET)
AnnaBridge 158:1c57384330a6 1818
AnnaBridge 158:1c57384330a6 1819 #define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == RESET)
AnnaBridge 158:1c57384330a6 1820
AnnaBridge 158:1c57384330a6 1821 #if defined(SWPMI1)
AnnaBridge 158:1c57384330a6 1822 #define __HAL_RCC_SWPMI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) == RESET)
AnnaBridge 158:1c57384330a6 1823 #endif /* SWPMI1 */
AnnaBridge 158:1c57384330a6 1824
AnnaBridge 158:1c57384330a6 1825 #define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) == RESET)
AnnaBridge 158:1c57384330a6 1826
AnnaBridge 158:1c57384330a6 1827 /**
AnnaBridge 158:1c57384330a6 1828 * @}
AnnaBridge 158:1c57384330a6 1829 */
AnnaBridge 158:1c57384330a6 1830
AnnaBridge 158:1c57384330a6 1831 /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status
AnnaBridge 158:1c57384330a6 1832 * @brief Check whether the APB2 peripheral clock is enabled or not.
AnnaBridge 158:1c57384330a6 1833 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 158:1c57384330a6 1834 * is disabled and the application software has to enable this clock before
AnnaBridge 158:1c57384330a6 1835 * using it.
AnnaBridge 158:1c57384330a6 1836 * @{
AnnaBridge 158:1c57384330a6 1837 */
AnnaBridge 158:1c57384330a6 1838
AnnaBridge 158:1c57384330a6 1839 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != RESET)
AnnaBridge 158:1c57384330a6 1840
AnnaBridge 158:1c57384330a6 1841 #define __HAL_RCC_FIREWALL_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN) != RESET)
AnnaBridge 158:1c57384330a6 1842
AnnaBridge 158:1c57384330a6 1843 #if defined(SDMMC1)
AnnaBridge 158:1c57384330a6 1844 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) != RESET)
AnnaBridge 158:1c57384330a6 1845 #endif /* SDMMC1 */
AnnaBridge 158:1c57384330a6 1846
AnnaBridge 158:1c57384330a6 1847 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != RESET)
AnnaBridge 158:1c57384330a6 1848
AnnaBridge 158:1c57384330a6 1849 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != RESET)
AnnaBridge 158:1c57384330a6 1850
AnnaBridge 158:1c57384330a6 1851 #if defined(TIM8)
AnnaBridge 158:1c57384330a6 1852 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != RESET)
AnnaBridge 158:1c57384330a6 1853 #endif /* TIM8 */
AnnaBridge 158:1c57384330a6 1854
AnnaBridge 158:1c57384330a6 1855 #define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != RESET)
AnnaBridge 158:1c57384330a6 1856
AnnaBridge 158:1c57384330a6 1857 #define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != RESET)
AnnaBridge 158:1c57384330a6 1858
AnnaBridge 158:1c57384330a6 1859 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != RESET)
AnnaBridge 158:1c57384330a6 1860
AnnaBridge 158:1c57384330a6 1861 #if defined(TIM17)
AnnaBridge 158:1c57384330a6 1862 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != RESET)
AnnaBridge 158:1c57384330a6 1863 #endif /* TIM17 */
AnnaBridge 158:1c57384330a6 1864
AnnaBridge 158:1c57384330a6 1865 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != RESET)
AnnaBridge 158:1c57384330a6 1866
AnnaBridge 158:1c57384330a6 1867 #if defined(SAI2)
AnnaBridge 158:1c57384330a6 1868 #define __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != RESET)
AnnaBridge 158:1c57384330a6 1869 #endif /* SAI2 */
AnnaBridge 158:1c57384330a6 1870
AnnaBridge 158:1c57384330a6 1871 #if defined(DFSDM1_Filter0)
AnnaBridge 158:1c57384330a6 1872 #define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) != RESET)
AnnaBridge 158:1c57384330a6 1873 #endif /* DFSDM1_Filter0 */
AnnaBridge 158:1c57384330a6 1874
AnnaBridge 158:1c57384330a6 1875
AnnaBridge 158:1c57384330a6 1876 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == RESET)
AnnaBridge 158:1c57384330a6 1877
AnnaBridge 158:1c57384330a6 1878 #if defined(SDMMC1)
AnnaBridge 158:1c57384330a6 1879 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) == RESET)
AnnaBridge 158:1c57384330a6 1880 #endif /* SDMMC1 */
AnnaBridge 158:1c57384330a6 1881
AnnaBridge 158:1c57384330a6 1882 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == RESET)
AnnaBridge 158:1c57384330a6 1883
AnnaBridge 158:1c57384330a6 1884 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == RESET)
AnnaBridge 158:1c57384330a6 1885
AnnaBridge 158:1c57384330a6 1886 #if defined(TIM8)
AnnaBridge 158:1c57384330a6 1887 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == RESET)
AnnaBridge 158:1c57384330a6 1888 #endif /* TIM8 */
AnnaBridge 158:1c57384330a6 1889
AnnaBridge 158:1c57384330a6 1890 #define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == RESET)
AnnaBridge 158:1c57384330a6 1891
AnnaBridge 158:1c57384330a6 1892 #define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == RESET)
AnnaBridge 158:1c57384330a6 1893
AnnaBridge 158:1c57384330a6 1894 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == RESET)
AnnaBridge 158:1c57384330a6 1895
AnnaBridge 158:1c57384330a6 1896 #if defined(TIM17)
AnnaBridge 158:1c57384330a6 1897 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == RESET)
AnnaBridge 158:1c57384330a6 1898 #endif /* TIM17 */
AnnaBridge 158:1c57384330a6 1899
AnnaBridge 158:1c57384330a6 1900 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == RESET)
AnnaBridge 158:1c57384330a6 1901
AnnaBridge 158:1c57384330a6 1902 #if defined(SAI2)
AnnaBridge 158:1c57384330a6 1903 #define __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == RESET)
AnnaBridge 158:1c57384330a6 1904 #endif /* SAI2 */
AnnaBridge 158:1c57384330a6 1905
AnnaBridge 158:1c57384330a6 1906 #if defined(DFSDM1_Filter0)
AnnaBridge 158:1c57384330a6 1907 #define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) == RESET)
AnnaBridge 158:1c57384330a6 1908 #endif /* DFSDM1_Filter0 */
AnnaBridge 158:1c57384330a6 1909
AnnaBridge 158:1c57384330a6 1910 /**
AnnaBridge 158:1c57384330a6 1911 * @}
AnnaBridge 158:1c57384330a6 1912 */
AnnaBridge 158:1c57384330a6 1913
AnnaBridge 158:1c57384330a6 1914 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset
AnnaBridge 158:1c57384330a6 1915 * @brief Force or release AHB1 peripheral reset.
AnnaBridge 158:1c57384330a6 1916 * @{
AnnaBridge 158:1c57384330a6 1917 */
AnnaBridge 158:1c57384330a6 1918 #define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFU)
AnnaBridge 158:1c57384330a6 1919
AnnaBridge 158:1c57384330a6 1920 #define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
AnnaBridge 158:1c57384330a6 1921
AnnaBridge 158:1c57384330a6 1922 #define __HAL_RCC_DMA2_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
AnnaBridge 158:1c57384330a6 1923
AnnaBridge 158:1c57384330a6 1924 #define __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
AnnaBridge 158:1c57384330a6 1925
AnnaBridge 158:1c57384330a6 1926 #define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
AnnaBridge 158:1c57384330a6 1927
AnnaBridge 158:1c57384330a6 1928 #define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)
AnnaBridge 158:1c57384330a6 1929
AnnaBridge 158:1c57384330a6 1930 #if defined(DMA2D)
AnnaBridge 158:1c57384330a6 1931 #define __HAL_RCC_DMA2D_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST)
AnnaBridge 158:1c57384330a6 1932 #endif /* DMA2D */
AnnaBridge 158:1c57384330a6 1933
AnnaBridge 158:1c57384330a6 1934
AnnaBridge 158:1c57384330a6 1935 #define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U)
AnnaBridge 158:1c57384330a6 1936
AnnaBridge 158:1c57384330a6 1937 #define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
AnnaBridge 158:1c57384330a6 1938
AnnaBridge 158:1c57384330a6 1939 #define __HAL_RCC_DMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
AnnaBridge 158:1c57384330a6 1940
AnnaBridge 158:1c57384330a6 1941 #define __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
AnnaBridge 158:1c57384330a6 1942
AnnaBridge 158:1c57384330a6 1943 #define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
AnnaBridge 158:1c57384330a6 1944
AnnaBridge 158:1c57384330a6 1945 #define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)
AnnaBridge 158:1c57384330a6 1946
AnnaBridge 158:1c57384330a6 1947 #if defined(DMA2D)
AnnaBridge 158:1c57384330a6 1948 #define __HAL_RCC_DMA2D_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST)
AnnaBridge 158:1c57384330a6 1949 #endif /* DMA2D */
AnnaBridge 158:1c57384330a6 1950
AnnaBridge 158:1c57384330a6 1951 /**
AnnaBridge 158:1c57384330a6 1952 * @}
AnnaBridge 158:1c57384330a6 1953 */
AnnaBridge 158:1c57384330a6 1954
AnnaBridge 158:1c57384330a6 1955 /** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset
AnnaBridge 158:1c57384330a6 1956 * @brief Force or release AHB2 peripheral reset.
AnnaBridge 158:1c57384330a6 1957 * @{
AnnaBridge 158:1c57384330a6 1958 */
AnnaBridge 158:1c57384330a6 1959 #define __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFFU)
AnnaBridge 158:1c57384330a6 1960
AnnaBridge 158:1c57384330a6 1961 #define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
AnnaBridge 158:1c57384330a6 1962
AnnaBridge 158:1c57384330a6 1963 #define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
AnnaBridge 158:1c57384330a6 1964
AnnaBridge 158:1c57384330a6 1965 #define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
AnnaBridge 158:1c57384330a6 1966
AnnaBridge 158:1c57384330a6 1967 #if defined(GPIOD)
AnnaBridge 158:1c57384330a6 1968 #define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
AnnaBridge 158:1c57384330a6 1969 #endif /* GPIOD */
AnnaBridge 158:1c57384330a6 1970
AnnaBridge 158:1c57384330a6 1971 #if defined(GPIOE)
AnnaBridge 158:1c57384330a6 1972 #define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
AnnaBridge 158:1c57384330a6 1973 #endif /* GPIOE */
AnnaBridge 158:1c57384330a6 1974
AnnaBridge 158:1c57384330a6 1975 #if defined(GPIOF)
AnnaBridge 158:1c57384330a6 1976 #define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
AnnaBridge 158:1c57384330a6 1977 #endif /* GPIOF */
AnnaBridge 158:1c57384330a6 1978
AnnaBridge 158:1c57384330a6 1979 #if defined(GPIOG)
AnnaBridge 158:1c57384330a6 1980 #define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
AnnaBridge 158:1c57384330a6 1981 #endif /* GPIOG */
AnnaBridge 158:1c57384330a6 1982
AnnaBridge 158:1c57384330a6 1983 #define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST)
AnnaBridge 158:1c57384330a6 1984
AnnaBridge 158:1c57384330a6 1985 #if defined(GPIOI)
AnnaBridge 158:1c57384330a6 1986 #define __HAL_RCC_GPIOI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOIRST)
AnnaBridge 158:1c57384330a6 1987 #endif /* GPIOI */
AnnaBridge 158:1c57384330a6 1988
AnnaBridge 158:1c57384330a6 1989 #if defined(USB_OTG_FS)
AnnaBridge 158:1c57384330a6 1990 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST)
AnnaBridge 158:1c57384330a6 1991 #endif /* USB_OTG_FS */
AnnaBridge 158:1c57384330a6 1992
AnnaBridge 158:1c57384330a6 1993 #define __HAL_RCC_ADC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST)
AnnaBridge 158:1c57384330a6 1994
AnnaBridge 158:1c57384330a6 1995 #if defined(DCMI)
AnnaBridge 158:1c57384330a6 1996 #define __HAL_RCC_DCMI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DCMIRST)
AnnaBridge 158:1c57384330a6 1997 #endif /* DCMI */
AnnaBridge 158:1c57384330a6 1998
AnnaBridge 158:1c57384330a6 1999 #if defined(AES)
AnnaBridge 158:1c57384330a6 2000 #define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
AnnaBridge 158:1c57384330a6 2001 #endif /* AES */
AnnaBridge 158:1c57384330a6 2002
AnnaBridge 158:1c57384330a6 2003 #if defined(HASH)
AnnaBridge 158:1c57384330a6 2004 #define __HAL_RCC_HASH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST)
AnnaBridge 158:1c57384330a6 2005 #endif /* HASH */
AnnaBridge 158:1c57384330a6 2006
AnnaBridge 158:1c57384330a6 2007 #define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
AnnaBridge 158:1c57384330a6 2008
AnnaBridge 158:1c57384330a6 2009
AnnaBridge 158:1c57384330a6 2010 #define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000U)
AnnaBridge 158:1c57384330a6 2011
AnnaBridge 158:1c57384330a6 2012 #define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
AnnaBridge 158:1c57384330a6 2013
AnnaBridge 158:1c57384330a6 2014 #define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
AnnaBridge 158:1c57384330a6 2015
AnnaBridge 158:1c57384330a6 2016 #define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
AnnaBridge 158:1c57384330a6 2017
AnnaBridge 158:1c57384330a6 2018 #if defined(GPIOD)
AnnaBridge 158:1c57384330a6 2019 #define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
AnnaBridge 158:1c57384330a6 2020 #endif /* GPIOD */
AnnaBridge 158:1c57384330a6 2021
AnnaBridge 158:1c57384330a6 2022 #if defined(GPIOE)
AnnaBridge 158:1c57384330a6 2023 #define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
AnnaBridge 158:1c57384330a6 2024 #endif /* GPIOE */
AnnaBridge 158:1c57384330a6 2025
AnnaBridge 158:1c57384330a6 2026 #if defined(GPIOF)
AnnaBridge 158:1c57384330a6 2027 #define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
AnnaBridge 158:1c57384330a6 2028 #endif /* GPIOF */
AnnaBridge 158:1c57384330a6 2029
AnnaBridge 158:1c57384330a6 2030 #if defined(GPIOG)
AnnaBridge 158:1c57384330a6 2031 #define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
AnnaBridge 158:1c57384330a6 2032 #endif /* GPIOG */
AnnaBridge 158:1c57384330a6 2033
AnnaBridge 158:1c57384330a6 2034 #define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST)
AnnaBridge 158:1c57384330a6 2035
AnnaBridge 158:1c57384330a6 2036 #if defined(GPIOI)
AnnaBridge 158:1c57384330a6 2037 #define __HAL_RCC_GPIOI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOIRST)
AnnaBridge 158:1c57384330a6 2038 #endif /* GPIOI */
AnnaBridge 158:1c57384330a6 2039
AnnaBridge 158:1c57384330a6 2040 #if defined(USB_OTG_FS)
AnnaBridge 158:1c57384330a6 2041 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST)
AnnaBridge 158:1c57384330a6 2042 #endif /* USB_OTG_FS */
AnnaBridge 158:1c57384330a6 2043
AnnaBridge 158:1c57384330a6 2044 #define __HAL_RCC_ADC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST)
AnnaBridge 158:1c57384330a6 2045
AnnaBridge 158:1c57384330a6 2046 #if defined(DCMI)
AnnaBridge 158:1c57384330a6 2047 #define __HAL_RCC_DCMI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DCMIRST)
AnnaBridge 158:1c57384330a6 2048 #endif /* DCMI */
AnnaBridge 158:1c57384330a6 2049
AnnaBridge 158:1c57384330a6 2050 #if defined(AES)
AnnaBridge 158:1c57384330a6 2051 #define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
AnnaBridge 158:1c57384330a6 2052 #endif /* AES */
AnnaBridge 158:1c57384330a6 2053
AnnaBridge 158:1c57384330a6 2054 #if defined(HASH)
AnnaBridge 158:1c57384330a6 2055 #define __HAL_RCC_HASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST)
AnnaBridge 158:1c57384330a6 2056 #endif /* HASH */
AnnaBridge 158:1c57384330a6 2057
AnnaBridge 158:1c57384330a6 2058 #define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
AnnaBridge 158:1c57384330a6 2059
AnnaBridge 158:1c57384330a6 2060 /**
AnnaBridge 158:1c57384330a6 2061 * @}
AnnaBridge 158:1c57384330a6 2062 */
AnnaBridge 158:1c57384330a6 2063
AnnaBridge 158:1c57384330a6 2064 /** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset
AnnaBridge 158:1c57384330a6 2065 * @brief Force or release AHB3 peripheral reset.
AnnaBridge 158:1c57384330a6 2066 * @{
AnnaBridge 158:1c57384330a6 2067 */
AnnaBridge 158:1c57384330a6 2068 #define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFFU)
AnnaBridge 158:1c57384330a6 2069
AnnaBridge 158:1c57384330a6 2070 #if defined(FMC_BANK1)
AnnaBridge 158:1c57384330a6 2071 #define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
AnnaBridge 158:1c57384330a6 2072 #endif /* FMC_BANK1 */
AnnaBridge 158:1c57384330a6 2073
AnnaBridge 158:1c57384330a6 2074 #if defined(QUADSPI)
AnnaBridge 158:1c57384330a6 2075 #define __HAL_RCC_QSPI_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
AnnaBridge 158:1c57384330a6 2076 #endif /* QUADSPI */
AnnaBridge 158:1c57384330a6 2077
AnnaBridge 158:1c57384330a6 2078 #define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000U)
AnnaBridge 158:1c57384330a6 2079
AnnaBridge 158:1c57384330a6 2080 #if defined(FMC_BANK1)
AnnaBridge 158:1c57384330a6 2081 #define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
AnnaBridge 158:1c57384330a6 2082 #endif /* FMC_BANK1 */
AnnaBridge 158:1c57384330a6 2083
AnnaBridge 158:1c57384330a6 2084 #if defined(QUADSPI)
AnnaBridge 158:1c57384330a6 2085 #define __HAL_RCC_QSPI_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
AnnaBridge 158:1c57384330a6 2086 #endif /* QUADSPI */
AnnaBridge 158:1c57384330a6 2087
AnnaBridge 158:1c57384330a6 2088 /**
AnnaBridge 158:1c57384330a6 2089 * @}
AnnaBridge 158:1c57384330a6 2090 */
AnnaBridge 158:1c57384330a6 2091
AnnaBridge 158:1c57384330a6 2092 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset
AnnaBridge 158:1c57384330a6 2093 * @brief Force or release APB1 peripheral reset.
AnnaBridge 158:1c57384330a6 2094 * @{
AnnaBridge 158:1c57384330a6 2095 */
AnnaBridge 158:1c57384330a6 2096 #define __HAL_RCC_APB1_FORCE_RESET() WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFU)
AnnaBridge 158:1c57384330a6 2097
AnnaBridge 158:1c57384330a6 2098 #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
AnnaBridge 158:1c57384330a6 2099
AnnaBridge 158:1c57384330a6 2100 #if defined(TIM3)
AnnaBridge 158:1c57384330a6 2101 #define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
AnnaBridge 158:1c57384330a6 2102 #endif /* TIM3 */
AnnaBridge 158:1c57384330a6 2103
AnnaBridge 158:1c57384330a6 2104 #if defined(TIM4)
AnnaBridge 158:1c57384330a6 2105 #define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
AnnaBridge 158:1c57384330a6 2106 #endif /* TIM4 */
AnnaBridge 158:1c57384330a6 2107
AnnaBridge 158:1c57384330a6 2108 #if defined(TIM5)
AnnaBridge 158:1c57384330a6 2109 #define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
AnnaBridge 158:1c57384330a6 2110 #endif /* TIM5 */
AnnaBridge 158:1c57384330a6 2111
AnnaBridge 158:1c57384330a6 2112 #define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
AnnaBridge 158:1c57384330a6 2113
AnnaBridge 158:1c57384330a6 2114 #define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
AnnaBridge 158:1c57384330a6 2115
AnnaBridge 158:1c57384330a6 2116 #if defined(LCD)
AnnaBridge 158:1c57384330a6 2117 #define __HAL_RCC_LCD_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST)
AnnaBridge 158:1c57384330a6 2118 #endif /* LCD */
AnnaBridge 158:1c57384330a6 2119
AnnaBridge 158:1c57384330a6 2120 #if defined(SPI2)
AnnaBridge 158:1c57384330a6 2121 #define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
AnnaBridge 158:1c57384330a6 2122 #endif /* SPI2 */
AnnaBridge 158:1c57384330a6 2123
AnnaBridge 158:1c57384330a6 2124 #define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
AnnaBridge 158:1c57384330a6 2125
AnnaBridge 158:1c57384330a6 2126 #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
AnnaBridge 158:1c57384330a6 2127
AnnaBridge 158:1c57384330a6 2128 #if defined(USART3)
AnnaBridge 158:1c57384330a6 2129 #define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
AnnaBridge 158:1c57384330a6 2130 #endif /* USART3 */
AnnaBridge 158:1c57384330a6 2131
AnnaBridge 158:1c57384330a6 2132 #if defined(UART4)
AnnaBridge 158:1c57384330a6 2133 #define __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
AnnaBridge 158:1c57384330a6 2134 #endif /* UART4 */
AnnaBridge 158:1c57384330a6 2135
AnnaBridge 158:1c57384330a6 2136 #if defined(UART5)
AnnaBridge 158:1c57384330a6 2137 #define __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
AnnaBridge 158:1c57384330a6 2138 #endif /* UART5 */
AnnaBridge 158:1c57384330a6 2139
AnnaBridge 158:1c57384330a6 2140 #define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
AnnaBridge 158:1c57384330a6 2141
AnnaBridge 158:1c57384330a6 2142 #if defined(I2C2)
AnnaBridge 158:1c57384330a6 2143 #define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
AnnaBridge 158:1c57384330a6 2144 #endif /* I2C2 */
AnnaBridge 158:1c57384330a6 2145
AnnaBridge 158:1c57384330a6 2146 #define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
AnnaBridge 158:1c57384330a6 2147
AnnaBridge 158:1c57384330a6 2148 #if defined(I2C4)
AnnaBridge 158:1c57384330a6 2149 #define __HAL_RCC_I2C4_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST)
AnnaBridge 158:1c57384330a6 2150 #endif /* I2C4 */
AnnaBridge 158:1c57384330a6 2151
AnnaBridge 158:1c57384330a6 2152 #if defined(CRS)
AnnaBridge 158:1c57384330a6 2153 #define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)
AnnaBridge 158:1c57384330a6 2154 #endif /* CRS */
AnnaBridge 158:1c57384330a6 2155
AnnaBridge 158:1c57384330a6 2156 #define __HAL_RCC_CAN1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST)
AnnaBridge 158:1c57384330a6 2157
AnnaBridge 158:1c57384330a6 2158 #if defined(CAN2)
AnnaBridge 158:1c57384330a6 2159 #define __HAL_RCC_CAN2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN2RST)
AnnaBridge 158:1c57384330a6 2160 #endif /* CAN2 */
AnnaBridge 158:1c57384330a6 2161
AnnaBridge 158:1c57384330a6 2162 #if defined(USB)
AnnaBridge 158:1c57384330a6 2163 #define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBFSRST)
AnnaBridge 158:1c57384330a6 2164 #endif /* USB */
AnnaBridge 158:1c57384330a6 2165
AnnaBridge 158:1c57384330a6 2166 #define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
AnnaBridge 158:1c57384330a6 2167
AnnaBridge 158:1c57384330a6 2168 #define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST)
AnnaBridge 158:1c57384330a6 2169
AnnaBridge 158:1c57384330a6 2170 #define __HAL_RCC_OPAMP_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST)
AnnaBridge 158:1c57384330a6 2171
AnnaBridge 158:1c57384330a6 2172 #define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
AnnaBridge 158:1c57384330a6 2173
AnnaBridge 158:1c57384330a6 2174 #define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
AnnaBridge 158:1c57384330a6 2175
AnnaBridge 158:1c57384330a6 2176 #if defined(SWPMI1)
AnnaBridge 158:1c57384330a6 2177 #define __HAL_RCC_SWPMI1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST)
AnnaBridge 158:1c57384330a6 2178 #endif /* SWPMI1 */
AnnaBridge 158:1c57384330a6 2179
AnnaBridge 158:1c57384330a6 2180 #define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)
AnnaBridge 158:1c57384330a6 2181
AnnaBridge 158:1c57384330a6 2182
AnnaBridge 158:1c57384330a6 2183 #define __HAL_RCC_APB1_RELEASE_RESET() WRITE_REG(RCC->APB1RSTR1, 0x00000000U)
AnnaBridge 158:1c57384330a6 2184
AnnaBridge 158:1c57384330a6 2185 #define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
AnnaBridge 158:1c57384330a6 2186
AnnaBridge 158:1c57384330a6 2187 #if defined(TIM3)
AnnaBridge 158:1c57384330a6 2188 #define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
AnnaBridge 158:1c57384330a6 2189 #endif /* TIM3 */
AnnaBridge 158:1c57384330a6 2190
AnnaBridge 158:1c57384330a6 2191 #if defined(TIM4)
AnnaBridge 158:1c57384330a6 2192 #define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
AnnaBridge 158:1c57384330a6 2193 #endif /* TIM4 */
AnnaBridge 158:1c57384330a6 2194
AnnaBridge 158:1c57384330a6 2195 #if defined(TIM5)
AnnaBridge 158:1c57384330a6 2196 #define __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
AnnaBridge 158:1c57384330a6 2197 #endif /* TIM5 */
AnnaBridge 158:1c57384330a6 2198
AnnaBridge 158:1c57384330a6 2199 #define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
AnnaBridge 158:1c57384330a6 2200
AnnaBridge 158:1c57384330a6 2201 #define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
AnnaBridge 158:1c57384330a6 2202
AnnaBridge 158:1c57384330a6 2203 #if defined(LCD)
AnnaBridge 158:1c57384330a6 2204 #define __HAL_RCC_LCD_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST)
AnnaBridge 158:1c57384330a6 2205 #endif /* LCD */
AnnaBridge 158:1c57384330a6 2206
AnnaBridge 158:1c57384330a6 2207 #if defined(SPI2)
AnnaBridge 158:1c57384330a6 2208 #define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
AnnaBridge 158:1c57384330a6 2209 #endif /* SPI2 */
AnnaBridge 158:1c57384330a6 2210
AnnaBridge 158:1c57384330a6 2211 #define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
AnnaBridge 158:1c57384330a6 2212
AnnaBridge 158:1c57384330a6 2213 #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
AnnaBridge 158:1c57384330a6 2214
AnnaBridge 158:1c57384330a6 2215 #if defined(USART3)
AnnaBridge 158:1c57384330a6 2216 #define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
AnnaBridge 158:1c57384330a6 2217 #endif /* USART3 */
AnnaBridge 158:1c57384330a6 2218
AnnaBridge 158:1c57384330a6 2219 #if defined(UART4)
AnnaBridge 158:1c57384330a6 2220 #define __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
AnnaBridge 158:1c57384330a6 2221 #endif /* UART4 */
AnnaBridge 158:1c57384330a6 2222
AnnaBridge 158:1c57384330a6 2223 #if defined(UART5)
AnnaBridge 158:1c57384330a6 2224 #define __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
AnnaBridge 158:1c57384330a6 2225 #endif /* UART5 */
AnnaBridge 158:1c57384330a6 2226
AnnaBridge 158:1c57384330a6 2227 #define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
AnnaBridge 158:1c57384330a6 2228
AnnaBridge 158:1c57384330a6 2229 #if defined(I2C2)
AnnaBridge 158:1c57384330a6 2230 #define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
AnnaBridge 158:1c57384330a6 2231 #endif /* I2C2 */
AnnaBridge 158:1c57384330a6 2232
AnnaBridge 158:1c57384330a6 2233 #define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
AnnaBridge 158:1c57384330a6 2234
AnnaBridge 158:1c57384330a6 2235 #if defined(I2C4)
AnnaBridge 158:1c57384330a6 2236 #define __HAL_RCC_I2C4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST)
AnnaBridge 158:1c57384330a6 2237 #endif /* I2C4 */
AnnaBridge 158:1c57384330a6 2238
AnnaBridge 158:1c57384330a6 2239 #if defined(CRS)
AnnaBridge 158:1c57384330a6 2240 #define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)
AnnaBridge 158:1c57384330a6 2241 #endif /* CRS */
AnnaBridge 158:1c57384330a6 2242
AnnaBridge 158:1c57384330a6 2243 #define __HAL_RCC_CAN1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST)
AnnaBridge 158:1c57384330a6 2244
AnnaBridge 158:1c57384330a6 2245 #if defined(CAN2)
AnnaBridge 158:1c57384330a6 2246 #define __HAL_RCC_CAN2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN2RST)
AnnaBridge 158:1c57384330a6 2247 #endif /* CAN2 */
AnnaBridge 158:1c57384330a6 2248
AnnaBridge 158:1c57384330a6 2249 #if defined(USB)
AnnaBridge 158:1c57384330a6 2250 #define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBFSRST)
AnnaBridge 158:1c57384330a6 2251 #endif /* USB */
AnnaBridge 158:1c57384330a6 2252
AnnaBridge 158:1c57384330a6 2253 #define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
AnnaBridge 158:1c57384330a6 2254
AnnaBridge 158:1c57384330a6 2255 #define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST)
AnnaBridge 158:1c57384330a6 2256
AnnaBridge 158:1c57384330a6 2257 #define __HAL_RCC_OPAMP_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST)
AnnaBridge 158:1c57384330a6 2258
AnnaBridge 158:1c57384330a6 2259 #define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
AnnaBridge 158:1c57384330a6 2260
AnnaBridge 158:1c57384330a6 2261 #define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
AnnaBridge 158:1c57384330a6 2262
AnnaBridge 158:1c57384330a6 2263 #if defined(SWPMI1)
AnnaBridge 158:1c57384330a6 2264 #define __HAL_RCC_SWPMI1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST)
AnnaBridge 158:1c57384330a6 2265 #endif /* SWPMI1 */
AnnaBridge 158:1c57384330a6 2266
AnnaBridge 158:1c57384330a6 2267 #define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)
AnnaBridge 158:1c57384330a6 2268
AnnaBridge 158:1c57384330a6 2269 /**
AnnaBridge 158:1c57384330a6 2270 * @}
AnnaBridge 158:1c57384330a6 2271 */
AnnaBridge 158:1c57384330a6 2272
AnnaBridge 158:1c57384330a6 2273 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset
AnnaBridge 158:1c57384330a6 2274 * @brief Force or release APB2 peripheral reset.
AnnaBridge 158:1c57384330a6 2275 * @{
AnnaBridge 158:1c57384330a6 2276 */
AnnaBridge 158:1c57384330a6 2277 #define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFU)
AnnaBridge 158:1c57384330a6 2278
AnnaBridge 158:1c57384330a6 2279 #define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
AnnaBridge 158:1c57384330a6 2280
AnnaBridge 158:1c57384330a6 2281 #if defined(SDMMC1)
AnnaBridge 158:1c57384330a6 2282 #define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST)
AnnaBridge 158:1c57384330a6 2283 #endif /* SDMMC1 */
AnnaBridge 158:1c57384330a6 2284
AnnaBridge 158:1c57384330a6 2285 #define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
AnnaBridge 158:1c57384330a6 2286
AnnaBridge 158:1c57384330a6 2287 #define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
AnnaBridge 158:1c57384330a6 2288
AnnaBridge 158:1c57384330a6 2289 #if defined(TIM8)
AnnaBridge 158:1c57384330a6 2290 #define __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
AnnaBridge 158:1c57384330a6 2291 #endif /* TIM8 */
AnnaBridge 158:1c57384330a6 2292
AnnaBridge 158:1c57384330a6 2293 #define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
AnnaBridge 158:1c57384330a6 2294
AnnaBridge 158:1c57384330a6 2295 #define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
AnnaBridge 158:1c57384330a6 2296
AnnaBridge 158:1c57384330a6 2297 #define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
AnnaBridge 158:1c57384330a6 2298
AnnaBridge 158:1c57384330a6 2299 #if defined(TIM17)
AnnaBridge 158:1c57384330a6 2300 #define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
AnnaBridge 158:1c57384330a6 2301 #endif /* TIM17 */
AnnaBridge 158:1c57384330a6 2302
AnnaBridge 158:1c57384330a6 2303 #define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
AnnaBridge 158:1c57384330a6 2304
AnnaBridge 158:1c57384330a6 2305 #if defined(SAI2)
AnnaBridge 158:1c57384330a6 2306 #define __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)
AnnaBridge 158:1c57384330a6 2307 #endif /* SAI2 */
AnnaBridge 158:1c57384330a6 2308
AnnaBridge 158:1c57384330a6 2309 #if defined(DFSDM1_Filter0)
AnnaBridge 158:1c57384330a6 2310 #define __HAL_RCC_DFSDM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST)
AnnaBridge 158:1c57384330a6 2311 #endif /* DFSDM1_Filter0 */
AnnaBridge 158:1c57384330a6 2312
AnnaBridge 158:1c57384330a6 2313
AnnaBridge 158:1c57384330a6 2314 #define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U)
AnnaBridge 158:1c57384330a6 2315
AnnaBridge 158:1c57384330a6 2316 #define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
AnnaBridge 158:1c57384330a6 2317
AnnaBridge 158:1c57384330a6 2318 #if defined(SDMMC1)
AnnaBridge 158:1c57384330a6 2319 #define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST)
AnnaBridge 158:1c57384330a6 2320 #endif /* SDMMC1 */
AnnaBridge 158:1c57384330a6 2321
AnnaBridge 158:1c57384330a6 2322 #define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
AnnaBridge 158:1c57384330a6 2323
AnnaBridge 158:1c57384330a6 2324 #define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
AnnaBridge 158:1c57384330a6 2325
AnnaBridge 158:1c57384330a6 2326 #if defined(TIM8)
AnnaBridge 158:1c57384330a6 2327 #define __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
AnnaBridge 158:1c57384330a6 2328 #endif /* TIM8 */
AnnaBridge 158:1c57384330a6 2329
AnnaBridge 158:1c57384330a6 2330 #define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
AnnaBridge 158:1c57384330a6 2331
AnnaBridge 158:1c57384330a6 2332 #define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
AnnaBridge 158:1c57384330a6 2333
AnnaBridge 158:1c57384330a6 2334 #define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
AnnaBridge 158:1c57384330a6 2335
AnnaBridge 158:1c57384330a6 2336 #if defined(TIM17)
AnnaBridge 158:1c57384330a6 2337 #define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
AnnaBridge 158:1c57384330a6 2338 #endif /* TIM17 */
AnnaBridge 158:1c57384330a6 2339
AnnaBridge 158:1c57384330a6 2340 #define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
AnnaBridge 158:1c57384330a6 2341
AnnaBridge 158:1c57384330a6 2342 #if defined(SAI2)
AnnaBridge 158:1c57384330a6 2343 #define __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)
AnnaBridge 158:1c57384330a6 2344 #endif /* SAI2 */
AnnaBridge 158:1c57384330a6 2345
AnnaBridge 158:1c57384330a6 2346 #if defined(DFSDM1_Filter0)
AnnaBridge 158:1c57384330a6 2347 #define __HAL_RCC_DFSDM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST)
AnnaBridge 158:1c57384330a6 2348 #endif /* DFSDM1_Filter0 */
AnnaBridge 158:1c57384330a6 2349
AnnaBridge 158:1c57384330a6 2350 /**
AnnaBridge 158:1c57384330a6 2351 * @}
AnnaBridge 158:1c57384330a6 2352 */
AnnaBridge 158:1c57384330a6 2353
AnnaBridge 158:1c57384330a6 2354 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable
AnnaBridge 158:1c57384330a6 2355 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge 158:1c57384330a6 2356 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge 158:1c57384330a6 2357 * power consumption.
AnnaBridge 158:1c57384330a6 2358 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge 158:1c57384330a6 2359 * @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge 158:1c57384330a6 2360 * @{
AnnaBridge 158:1c57384330a6 2361 */
AnnaBridge 158:1c57384330a6 2362
AnnaBridge 158:1c57384330a6 2363 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
AnnaBridge 158:1c57384330a6 2364
AnnaBridge 158:1c57384330a6 2365 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
AnnaBridge 158:1c57384330a6 2366
AnnaBridge 158:1c57384330a6 2367 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
AnnaBridge 158:1c57384330a6 2368
AnnaBridge 158:1c57384330a6 2369 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
AnnaBridge 158:1c57384330a6 2370
AnnaBridge 158:1c57384330a6 2371 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
AnnaBridge 158:1c57384330a6 2372
AnnaBridge 158:1c57384330a6 2373 #define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)
AnnaBridge 158:1c57384330a6 2374
AnnaBridge 158:1c57384330a6 2375 #if defined(DMA2D)
AnnaBridge 158:1c57384330a6 2376 #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN)
AnnaBridge 158:1c57384330a6 2377 #endif /* DMA2D */
AnnaBridge 158:1c57384330a6 2378
AnnaBridge 158:1c57384330a6 2379
AnnaBridge 158:1c57384330a6 2380 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
AnnaBridge 158:1c57384330a6 2381
AnnaBridge 158:1c57384330a6 2382 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
AnnaBridge 158:1c57384330a6 2383
AnnaBridge 158:1c57384330a6 2384 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
AnnaBridge 158:1c57384330a6 2385
AnnaBridge 158:1c57384330a6 2386 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
AnnaBridge 158:1c57384330a6 2387
AnnaBridge 158:1c57384330a6 2388 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
AnnaBridge 158:1c57384330a6 2389
AnnaBridge 158:1c57384330a6 2390 #define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)
AnnaBridge 158:1c57384330a6 2391
AnnaBridge 158:1c57384330a6 2392 #if defined(DMA2D)
AnnaBridge 158:1c57384330a6 2393 #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN)
AnnaBridge 158:1c57384330a6 2394 #endif /* DMA2D */
AnnaBridge 158:1c57384330a6 2395
AnnaBridge 158:1c57384330a6 2396 /**
AnnaBridge 158:1c57384330a6 2397 * @}
AnnaBridge 158:1c57384330a6 2398 */
AnnaBridge 158:1c57384330a6 2399
AnnaBridge 158:1c57384330a6 2400 /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable
AnnaBridge 158:1c57384330a6 2401 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge 158:1c57384330a6 2402 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge 158:1c57384330a6 2403 * power consumption.
AnnaBridge 158:1c57384330a6 2404 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge 158:1c57384330a6 2405 * @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge 158:1c57384330a6 2406 * @{
AnnaBridge 158:1c57384330a6 2407 */
AnnaBridge 158:1c57384330a6 2408
AnnaBridge 158:1c57384330a6 2409 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
AnnaBridge 158:1c57384330a6 2410
AnnaBridge 158:1c57384330a6 2411 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
AnnaBridge 158:1c57384330a6 2412
AnnaBridge 158:1c57384330a6 2413 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
AnnaBridge 158:1c57384330a6 2414
AnnaBridge 158:1c57384330a6 2415 #if defined(GPIOD)
AnnaBridge 158:1c57384330a6 2416 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
AnnaBridge 158:1c57384330a6 2417 #endif /* GPIOD */
AnnaBridge 158:1c57384330a6 2418
AnnaBridge 158:1c57384330a6 2419 #if defined(GPIOE)
AnnaBridge 158:1c57384330a6 2420 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
AnnaBridge 158:1c57384330a6 2421 #endif /* GPIOE */
AnnaBridge 158:1c57384330a6 2422
AnnaBridge 158:1c57384330a6 2423 #if defined(GPIOF)
AnnaBridge 158:1c57384330a6 2424 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
AnnaBridge 158:1c57384330a6 2425 #endif /* GPIOF */
AnnaBridge 158:1c57384330a6 2426
AnnaBridge 158:1c57384330a6 2427 #if defined(GPIOG)
AnnaBridge 158:1c57384330a6 2428 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
AnnaBridge 158:1c57384330a6 2429 #endif /* GPIOG */
AnnaBridge 158:1c57384330a6 2430
AnnaBridge 158:1c57384330a6 2431 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN)
AnnaBridge 158:1c57384330a6 2432
AnnaBridge 158:1c57384330a6 2433 #if defined(GPIOI)
AnnaBridge 158:1c57384330a6 2434 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN)
AnnaBridge 158:1c57384330a6 2435 #endif /* GPIOI */
AnnaBridge 158:1c57384330a6 2436
AnnaBridge 158:1c57384330a6 2437 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
AnnaBridge 158:1c57384330a6 2438
AnnaBridge 158:1c57384330a6 2439 #if defined(USB_OTG_FS)
AnnaBridge 158:1c57384330a6 2440 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN)
AnnaBridge 158:1c57384330a6 2441 #endif /* USB_OTG_FS */
AnnaBridge 158:1c57384330a6 2442
AnnaBridge 158:1c57384330a6 2443 #define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN)
AnnaBridge 158:1c57384330a6 2444
AnnaBridge 158:1c57384330a6 2445 #if defined(DCMI)
AnnaBridge 158:1c57384330a6 2446 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN)
AnnaBridge 158:1c57384330a6 2447 #endif /* DCMI */
AnnaBridge 158:1c57384330a6 2448
AnnaBridge 158:1c57384330a6 2449 #if defined(AES)
AnnaBridge 158:1c57384330a6 2450 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)
AnnaBridge 158:1c57384330a6 2451 #endif /* AES */
AnnaBridge 158:1c57384330a6 2452
AnnaBridge 158:1c57384330a6 2453 #if defined(HASH)
AnnaBridge 158:1c57384330a6 2454 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN)
AnnaBridge 158:1c57384330a6 2455 #endif /* HASH */
AnnaBridge 158:1c57384330a6 2456
AnnaBridge 158:1c57384330a6 2457 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
AnnaBridge 158:1c57384330a6 2458
AnnaBridge 158:1c57384330a6 2459
AnnaBridge 158:1c57384330a6 2460 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
AnnaBridge 158:1c57384330a6 2461
AnnaBridge 158:1c57384330a6 2462 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
AnnaBridge 158:1c57384330a6 2463
AnnaBridge 158:1c57384330a6 2464 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
AnnaBridge 158:1c57384330a6 2465
AnnaBridge 158:1c57384330a6 2466 #if defined(GPIOD)
AnnaBridge 158:1c57384330a6 2467 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
AnnaBridge 158:1c57384330a6 2468 #endif /* GPIOD */
AnnaBridge 158:1c57384330a6 2469
AnnaBridge 158:1c57384330a6 2470 #if defined(GPIOE)
AnnaBridge 158:1c57384330a6 2471 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
AnnaBridge 158:1c57384330a6 2472 #endif /* GPIOE */
AnnaBridge 158:1c57384330a6 2473
AnnaBridge 158:1c57384330a6 2474 #if defined(GPIOF)
AnnaBridge 158:1c57384330a6 2475 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
AnnaBridge 158:1c57384330a6 2476 #endif /* GPIOF */
AnnaBridge 158:1c57384330a6 2477
AnnaBridge 158:1c57384330a6 2478 #if defined(GPIOG)
AnnaBridge 158:1c57384330a6 2479 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
AnnaBridge 158:1c57384330a6 2480 #endif /* GPIOG */
AnnaBridge 158:1c57384330a6 2481
AnnaBridge 158:1c57384330a6 2482 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN)
AnnaBridge 158:1c57384330a6 2483
AnnaBridge 158:1c57384330a6 2484 #if defined(GPIOI)
AnnaBridge 158:1c57384330a6 2485 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN)
AnnaBridge 158:1c57384330a6 2486 #endif /* GPIOI */
AnnaBridge 158:1c57384330a6 2487
AnnaBridge 158:1c57384330a6 2488 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
AnnaBridge 158:1c57384330a6 2489
AnnaBridge 158:1c57384330a6 2490 #if defined(USB_OTG_FS)
AnnaBridge 158:1c57384330a6 2491 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN)
AnnaBridge 158:1c57384330a6 2492 #endif /* USB_OTG_FS */
AnnaBridge 158:1c57384330a6 2493
AnnaBridge 158:1c57384330a6 2494 #define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN)
AnnaBridge 158:1c57384330a6 2495
AnnaBridge 158:1c57384330a6 2496 #if defined(DCMI)
AnnaBridge 158:1c57384330a6 2497 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN)
AnnaBridge 158:1c57384330a6 2498 #endif /* DCMI */
AnnaBridge 158:1c57384330a6 2499
AnnaBridge 158:1c57384330a6 2500 #if defined(AES)
AnnaBridge 158:1c57384330a6 2501 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)
AnnaBridge 158:1c57384330a6 2502 #endif /* AES */
AnnaBridge 158:1c57384330a6 2503
AnnaBridge 158:1c57384330a6 2504 #if defined(HASH)
AnnaBridge 158:1c57384330a6 2505 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN)
AnnaBridge 158:1c57384330a6 2506 #endif /* HASH */
AnnaBridge 158:1c57384330a6 2507
AnnaBridge 158:1c57384330a6 2508 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
AnnaBridge 158:1c57384330a6 2509
AnnaBridge 158:1c57384330a6 2510 /**
AnnaBridge 158:1c57384330a6 2511 * @}
AnnaBridge 158:1c57384330a6 2512 */
AnnaBridge 158:1c57384330a6 2513
AnnaBridge 158:1c57384330a6 2514 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable
AnnaBridge 158:1c57384330a6 2515 * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
AnnaBridge 158:1c57384330a6 2516 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge 158:1c57384330a6 2517 * power consumption.
AnnaBridge 158:1c57384330a6 2518 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge 158:1c57384330a6 2519 * @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge 158:1c57384330a6 2520 * @{
AnnaBridge 158:1c57384330a6 2521 */
AnnaBridge 158:1c57384330a6 2522
AnnaBridge 158:1c57384330a6 2523 #if defined(QUADSPI)
AnnaBridge 158:1c57384330a6 2524 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
AnnaBridge 158:1c57384330a6 2525 #endif /* QUADSPI */
AnnaBridge 158:1c57384330a6 2526
AnnaBridge 158:1c57384330a6 2527 #if defined(FMC_BANK1)
AnnaBridge 158:1c57384330a6 2528 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
AnnaBridge 158:1c57384330a6 2529 #endif /* FMC_BANK1 */
AnnaBridge 158:1c57384330a6 2530
AnnaBridge 158:1c57384330a6 2531 #if defined(QUADSPI)
AnnaBridge 158:1c57384330a6 2532 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
AnnaBridge 158:1c57384330a6 2533 #endif /* QUADSPI */
AnnaBridge 158:1c57384330a6 2534
AnnaBridge 158:1c57384330a6 2535 #if defined(FMC_BANK1)
AnnaBridge 158:1c57384330a6 2536 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
AnnaBridge 158:1c57384330a6 2537 #endif /* FMC_BANK1 */
AnnaBridge 158:1c57384330a6 2538
AnnaBridge 158:1c57384330a6 2539 /**
AnnaBridge 158:1c57384330a6 2540 * @}
AnnaBridge 158:1c57384330a6 2541 */
AnnaBridge 158:1c57384330a6 2542
AnnaBridge 158:1c57384330a6 2543 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable
AnnaBridge 158:1c57384330a6 2544 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge 158:1c57384330a6 2545 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge 158:1c57384330a6 2546 * power consumption.
AnnaBridge 158:1c57384330a6 2547 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge 158:1c57384330a6 2548 * @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge 158:1c57384330a6 2549 * @{
AnnaBridge 158:1c57384330a6 2550 */
AnnaBridge 158:1c57384330a6 2551
AnnaBridge 158:1c57384330a6 2552 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
AnnaBridge 158:1c57384330a6 2553
AnnaBridge 158:1c57384330a6 2554 #if defined(TIM3)
AnnaBridge 158:1c57384330a6 2555 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
AnnaBridge 158:1c57384330a6 2556 #endif /* TIM3 */
AnnaBridge 158:1c57384330a6 2557
AnnaBridge 158:1c57384330a6 2558 #if defined(TIM4)
AnnaBridge 158:1c57384330a6 2559 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
AnnaBridge 158:1c57384330a6 2560 #endif /* TIM4 */
AnnaBridge 158:1c57384330a6 2561
AnnaBridge 158:1c57384330a6 2562 #if defined(TIM5)
AnnaBridge 158:1c57384330a6 2563 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
AnnaBridge 158:1c57384330a6 2564 #endif /* TIM5 */
AnnaBridge 158:1c57384330a6 2565
AnnaBridge 158:1c57384330a6 2566 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
AnnaBridge 158:1c57384330a6 2567
AnnaBridge 158:1c57384330a6 2568 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
AnnaBridge 158:1c57384330a6 2569
AnnaBridge 158:1c57384330a6 2570 #if defined(LCD)
AnnaBridge 158:1c57384330a6 2571 #define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN)
AnnaBridge 158:1c57384330a6 2572 #endif /* LCD */
AnnaBridge 158:1c57384330a6 2573
AnnaBridge 158:1c57384330a6 2574 #if defined(RCC_APB1SMENR1_RTCAPBSMEN)
AnnaBridge 158:1c57384330a6 2575 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)
AnnaBridge 158:1c57384330a6 2576 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */
AnnaBridge 158:1c57384330a6 2577
AnnaBridge 158:1c57384330a6 2578 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
AnnaBridge 158:1c57384330a6 2579
AnnaBridge 158:1c57384330a6 2580 #if defined(SPI2)
AnnaBridge 158:1c57384330a6 2581 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
AnnaBridge 158:1c57384330a6 2582 #endif /* SPI2 */
AnnaBridge 158:1c57384330a6 2583
AnnaBridge 158:1c57384330a6 2584 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
AnnaBridge 158:1c57384330a6 2585
AnnaBridge 158:1c57384330a6 2586 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
AnnaBridge 158:1c57384330a6 2587
AnnaBridge 158:1c57384330a6 2588 #if defined(USART3)
AnnaBridge 158:1c57384330a6 2589 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
AnnaBridge 158:1c57384330a6 2590 #endif /* USART3 */
AnnaBridge 158:1c57384330a6 2591
AnnaBridge 158:1c57384330a6 2592 #if defined(UART4)
AnnaBridge 158:1c57384330a6 2593 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
AnnaBridge 158:1c57384330a6 2594 #endif /* UART4 */
AnnaBridge 158:1c57384330a6 2595
AnnaBridge 158:1c57384330a6 2596 #if defined(UART5)
AnnaBridge 158:1c57384330a6 2597 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
AnnaBridge 158:1c57384330a6 2598 #endif /* UART5 */
AnnaBridge 158:1c57384330a6 2599
AnnaBridge 158:1c57384330a6 2600 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
AnnaBridge 158:1c57384330a6 2601
AnnaBridge 158:1c57384330a6 2602 #if defined(I2C2)
AnnaBridge 158:1c57384330a6 2603 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
AnnaBridge 158:1c57384330a6 2604 #endif /* I2C2 */
AnnaBridge 158:1c57384330a6 2605
AnnaBridge 158:1c57384330a6 2606 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
AnnaBridge 158:1c57384330a6 2607
AnnaBridge 158:1c57384330a6 2608 #if defined(I2C4)
AnnaBridge 158:1c57384330a6 2609 #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN)
AnnaBridge 158:1c57384330a6 2610 #endif /* I2C4 */
AnnaBridge 158:1c57384330a6 2611
AnnaBridge 158:1c57384330a6 2612 #if defined(CRS)
AnnaBridge 158:1c57384330a6 2613 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)
AnnaBridge 158:1c57384330a6 2614 #endif /* CRS */
AnnaBridge 158:1c57384330a6 2615
AnnaBridge 158:1c57384330a6 2616 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN)
AnnaBridge 158:1c57384330a6 2617
AnnaBridge 158:1c57384330a6 2618 #if defined(CAN2)
AnnaBridge 158:1c57384330a6 2619 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN)
AnnaBridge 158:1c57384330a6 2620 #endif /* CAN2 */
AnnaBridge 158:1c57384330a6 2621
AnnaBridge 158:1c57384330a6 2622 #if defined(USB)
AnnaBridge 158:1c57384330a6 2623 #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN)
AnnaBridge 158:1c57384330a6 2624 #endif /* USB */
AnnaBridge 158:1c57384330a6 2625
AnnaBridge 158:1c57384330a6 2626 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
AnnaBridge 158:1c57384330a6 2627
AnnaBridge 158:1c57384330a6 2628 #define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN)
AnnaBridge 158:1c57384330a6 2629
AnnaBridge 158:1c57384330a6 2630 #define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN)
AnnaBridge 158:1c57384330a6 2631
AnnaBridge 158:1c57384330a6 2632 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
AnnaBridge 158:1c57384330a6 2633
AnnaBridge 158:1c57384330a6 2634 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
AnnaBridge 158:1c57384330a6 2635
AnnaBridge 158:1c57384330a6 2636 #if defined(SWPMI1)
AnnaBridge 158:1c57384330a6 2637 #define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN)
AnnaBridge 158:1c57384330a6 2638 #endif /* SWPMI1 */
AnnaBridge 158:1c57384330a6 2639
AnnaBridge 158:1c57384330a6 2640 #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)
AnnaBridge 158:1c57384330a6 2641
AnnaBridge 158:1c57384330a6 2642
AnnaBridge 158:1c57384330a6 2643 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
AnnaBridge 158:1c57384330a6 2644
AnnaBridge 158:1c57384330a6 2645 #if defined(TIM3)
AnnaBridge 158:1c57384330a6 2646 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
AnnaBridge 158:1c57384330a6 2647 #endif /* TIM3 */
AnnaBridge 158:1c57384330a6 2648
AnnaBridge 158:1c57384330a6 2649 #if defined(TIM4)
AnnaBridge 158:1c57384330a6 2650 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
AnnaBridge 158:1c57384330a6 2651 #endif /* TIM4 */
AnnaBridge 158:1c57384330a6 2652
AnnaBridge 158:1c57384330a6 2653 #if defined(TIM5)
AnnaBridge 158:1c57384330a6 2654 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
AnnaBridge 158:1c57384330a6 2655 #endif /* TIM5 */
AnnaBridge 158:1c57384330a6 2656
AnnaBridge 158:1c57384330a6 2657 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
AnnaBridge 158:1c57384330a6 2658
AnnaBridge 158:1c57384330a6 2659 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
AnnaBridge 158:1c57384330a6 2660
AnnaBridge 158:1c57384330a6 2661 #if defined(LCD)
AnnaBridge 158:1c57384330a6 2662 #define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN)
AnnaBridge 158:1c57384330a6 2663 #endif /* LCD */
AnnaBridge 158:1c57384330a6 2664
AnnaBridge 158:1c57384330a6 2665 #if defined(RCC_APB1SMENR1_RTCAPBSMEN)
AnnaBridge 158:1c57384330a6 2666 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)
AnnaBridge 158:1c57384330a6 2667 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */
AnnaBridge 158:1c57384330a6 2668
AnnaBridge 158:1c57384330a6 2669 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
AnnaBridge 158:1c57384330a6 2670
AnnaBridge 158:1c57384330a6 2671 #if defined(SPI2)
AnnaBridge 158:1c57384330a6 2672 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
AnnaBridge 158:1c57384330a6 2673 #endif /* SPI2 */
AnnaBridge 158:1c57384330a6 2674
AnnaBridge 158:1c57384330a6 2675 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
AnnaBridge 158:1c57384330a6 2676
AnnaBridge 158:1c57384330a6 2677 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
AnnaBridge 158:1c57384330a6 2678
AnnaBridge 158:1c57384330a6 2679 #if defined(USART3)
AnnaBridge 158:1c57384330a6 2680 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
AnnaBridge 158:1c57384330a6 2681 #endif /* USART3 */
AnnaBridge 158:1c57384330a6 2682
AnnaBridge 158:1c57384330a6 2683 #if defined(UART4)
AnnaBridge 158:1c57384330a6 2684 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
AnnaBridge 158:1c57384330a6 2685 #endif /* UART4 */
AnnaBridge 158:1c57384330a6 2686
AnnaBridge 158:1c57384330a6 2687 #if defined(UART5)
AnnaBridge 158:1c57384330a6 2688 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
AnnaBridge 158:1c57384330a6 2689 #endif /* UART5 */
AnnaBridge 158:1c57384330a6 2690
AnnaBridge 158:1c57384330a6 2691 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
AnnaBridge 158:1c57384330a6 2692
AnnaBridge 158:1c57384330a6 2693 #if defined(I2C2)
AnnaBridge 158:1c57384330a6 2694 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
AnnaBridge 158:1c57384330a6 2695 #endif /* I2C2 */
AnnaBridge 158:1c57384330a6 2696
AnnaBridge 158:1c57384330a6 2697 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
AnnaBridge 158:1c57384330a6 2698
AnnaBridge 158:1c57384330a6 2699 #if defined(I2C4)
AnnaBridge 158:1c57384330a6 2700 #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN)
AnnaBridge 158:1c57384330a6 2701 #endif /* I2C4 */
AnnaBridge 158:1c57384330a6 2702
AnnaBridge 158:1c57384330a6 2703 #if defined(CRS)
AnnaBridge 158:1c57384330a6 2704 #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)
AnnaBridge 158:1c57384330a6 2705 #endif /* CRS */
AnnaBridge 158:1c57384330a6 2706
AnnaBridge 158:1c57384330a6 2707 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN)
AnnaBridge 158:1c57384330a6 2708
AnnaBridge 158:1c57384330a6 2709 #if defined(CAN2)
AnnaBridge 158:1c57384330a6 2710 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN)
AnnaBridge 158:1c57384330a6 2711 #endif /* CAN2 */
AnnaBridge 158:1c57384330a6 2712
AnnaBridge 158:1c57384330a6 2713 #if defined(USB)
AnnaBridge 158:1c57384330a6 2714 #define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN)
AnnaBridge 158:1c57384330a6 2715 #endif /* USB */
AnnaBridge 158:1c57384330a6 2716
AnnaBridge 158:1c57384330a6 2717 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
AnnaBridge 158:1c57384330a6 2718
AnnaBridge 158:1c57384330a6 2719 #define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN)
AnnaBridge 158:1c57384330a6 2720
AnnaBridge 158:1c57384330a6 2721 #define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN)
AnnaBridge 158:1c57384330a6 2722
AnnaBridge 158:1c57384330a6 2723 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
AnnaBridge 158:1c57384330a6 2724
AnnaBridge 158:1c57384330a6 2725 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
AnnaBridge 158:1c57384330a6 2726
AnnaBridge 158:1c57384330a6 2727 #if defined(SWPMI1)
AnnaBridge 158:1c57384330a6 2728 #define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN)
AnnaBridge 158:1c57384330a6 2729 #endif /* SWPMI1 */
AnnaBridge 158:1c57384330a6 2730
AnnaBridge 158:1c57384330a6 2731 #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)
AnnaBridge 158:1c57384330a6 2732
AnnaBridge 158:1c57384330a6 2733 /**
AnnaBridge 158:1c57384330a6 2734 * @}
AnnaBridge 158:1c57384330a6 2735 */
AnnaBridge 158:1c57384330a6 2736
AnnaBridge 158:1c57384330a6 2737 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable
AnnaBridge 158:1c57384330a6 2738 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge 158:1c57384330a6 2739 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge 158:1c57384330a6 2740 * power consumption.
AnnaBridge 158:1c57384330a6 2741 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge 158:1c57384330a6 2742 * @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge 158:1c57384330a6 2743 * @{
AnnaBridge 158:1c57384330a6 2744 */
AnnaBridge 158:1c57384330a6 2745
AnnaBridge 158:1c57384330a6 2746 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
AnnaBridge 158:1c57384330a6 2747
AnnaBridge 158:1c57384330a6 2748 #if defined(SDMMC1)
AnnaBridge 158:1c57384330a6 2749 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN)
AnnaBridge 158:1c57384330a6 2750 #endif /* SDMMC1 */
AnnaBridge 158:1c57384330a6 2751
AnnaBridge 158:1c57384330a6 2752 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
AnnaBridge 158:1c57384330a6 2753
AnnaBridge 158:1c57384330a6 2754 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
AnnaBridge 158:1c57384330a6 2755
AnnaBridge 158:1c57384330a6 2756 #if defined(TIM8)
AnnaBridge 158:1c57384330a6 2757 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
AnnaBridge 158:1c57384330a6 2758 #endif /* TIM8 */
AnnaBridge 158:1c57384330a6 2759
AnnaBridge 158:1c57384330a6 2760 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
AnnaBridge 158:1c57384330a6 2761
AnnaBridge 158:1c57384330a6 2762 #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
AnnaBridge 158:1c57384330a6 2763
AnnaBridge 158:1c57384330a6 2764 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
AnnaBridge 158:1c57384330a6 2765
AnnaBridge 158:1c57384330a6 2766 #if defined(TIM17)
AnnaBridge 158:1c57384330a6 2767 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
AnnaBridge 158:1c57384330a6 2768 #endif /* TIM17 */
AnnaBridge 158:1c57384330a6 2769
AnnaBridge 158:1c57384330a6 2770 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
AnnaBridge 158:1c57384330a6 2771
AnnaBridge 158:1c57384330a6 2772 #if defined(SAI2)
AnnaBridge 158:1c57384330a6 2773 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)
AnnaBridge 158:1c57384330a6 2774 #endif /* SAI2 */
AnnaBridge 158:1c57384330a6 2775
AnnaBridge 158:1c57384330a6 2776 #if defined(DFSDM1_Filter0)
AnnaBridge 158:1c57384330a6 2777 #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN)
AnnaBridge 158:1c57384330a6 2778 #endif /* DFSDM1_Filter0 */
AnnaBridge 158:1c57384330a6 2779
AnnaBridge 158:1c57384330a6 2780
AnnaBridge 158:1c57384330a6 2781 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
AnnaBridge 158:1c57384330a6 2782
AnnaBridge 158:1c57384330a6 2783 #if defined(SDMMC1)
AnnaBridge 158:1c57384330a6 2784 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN)
AnnaBridge 158:1c57384330a6 2785 #endif /* SDMMC1 */
AnnaBridge 158:1c57384330a6 2786
AnnaBridge 158:1c57384330a6 2787 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
AnnaBridge 158:1c57384330a6 2788
AnnaBridge 158:1c57384330a6 2789 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
AnnaBridge 158:1c57384330a6 2790
AnnaBridge 158:1c57384330a6 2791 #if defined(TIM8)
AnnaBridge 158:1c57384330a6 2792 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
AnnaBridge 158:1c57384330a6 2793 #endif /* TIM8 */
AnnaBridge 158:1c57384330a6 2794
AnnaBridge 158:1c57384330a6 2795 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
AnnaBridge 158:1c57384330a6 2796
AnnaBridge 158:1c57384330a6 2797 #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
AnnaBridge 158:1c57384330a6 2798
AnnaBridge 158:1c57384330a6 2799 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
AnnaBridge 158:1c57384330a6 2800
AnnaBridge 158:1c57384330a6 2801 #if defined(TIM17)
AnnaBridge 158:1c57384330a6 2802 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
AnnaBridge 158:1c57384330a6 2803 #endif /* TIM17 */
AnnaBridge 158:1c57384330a6 2804
AnnaBridge 158:1c57384330a6 2805 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
AnnaBridge 158:1c57384330a6 2806
AnnaBridge 158:1c57384330a6 2807 #if defined(SAI2)
AnnaBridge 158:1c57384330a6 2808 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)
AnnaBridge 158:1c57384330a6 2809 #endif /* SAI2 */
AnnaBridge 158:1c57384330a6 2810
AnnaBridge 158:1c57384330a6 2811 #if defined(DFSDM1_Filter0)
AnnaBridge 158:1c57384330a6 2812 #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN)
AnnaBridge 158:1c57384330a6 2813 #endif /* DFSDM1_Filter0 */
AnnaBridge 158:1c57384330a6 2814
AnnaBridge 158:1c57384330a6 2815 /**
AnnaBridge 158:1c57384330a6 2816 * @}
AnnaBridge 158:1c57384330a6 2817 */
AnnaBridge 158:1c57384330a6 2818
AnnaBridge 158:1c57384330a6 2819 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enabled or Disabled Status
AnnaBridge 158:1c57384330a6 2820 * @brief Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
AnnaBridge 158:1c57384330a6 2821 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge 158:1c57384330a6 2822 * power consumption.
AnnaBridge 158:1c57384330a6 2823 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge 158:1c57384330a6 2824 * @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge 158:1c57384330a6 2825 * @{
AnnaBridge 158:1c57384330a6 2826 */
AnnaBridge 158:1c57384330a6 2827
AnnaBridge 158:1c57384330a6 2828 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != RESET)
AnnaBridge 158:1c57384330a6 2829
AnnaBridge 158:1c57384330a6 2830 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != RESET)
AnnaBridge 158:1c57384330a6 2831
AnnaBridge 158:1c57384330a6 2832 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != RESET)
AnnaBridge 158:1c57384330a6 2833
AnnaBridge 158:1c57384330a6 2834 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != RESET)
AnnaBridge 158:1c57384330a6 2835
AnnaBridge 158:1c57384330a6 2836 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != RESET)
AnnaBridge 158:1c57384330a6 2837
AnnaBridge 158:1c57384330a6 2838 #define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != RESET)
AnnaBridge 158:1c57384330a6 2839
AnnaBridge 158:1c57384330a6 2840 #if defined(DMA2D)
AnnaBridge 158:1c57384330a6 2841 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) != RESET)
AnnaBridge 158:1c57384330a6 2842 #endif /* DMA2D */
AnnaBridge 158:1c57384330a6 2843
AnnaBridge 158:1c57384330a6 2844
AnnaBridge 158:1c57384330a6 2845 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == RESET)
AnnaBridge 158:1c57384330a6 2846
AnnaBridge 158:1c57384330a6 2847 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == RESET)
AnnaBridge 158:1c57384330a6 2848
AnnaBridge 158:1c57384330a6 2849 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == RESET)
AnnaBridge 158:1c57384330a6 2850
AnnaBridge 158:1c57384330a6 2851 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == RESET)
AnnaBridge 158:1c57384330a6 2852
AnnaBridge 158:1c57384330a6 2853 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == RESET)
AnnaBridge 158:1c57384330a6 2854
AnnaBridge 158:1c57384330a6 2855 #define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) == RESET)
AnnaBridge 158:1c57384330a6 2856
AnnaBridge 158:1c57384330a6 2857 #if defined(DMA2D)
AnnaBridge 158:1c57384330a6 2858 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) == RESET)
AnnaBridge 158:1c57384330a6 2859 #endif /* DMA2D */
AnnaBridge 158:1c57384330a6 2860
AnnaBridge 158:1c57384330a6 2861 /**
AnnaBridge 158:1c57384330a6 2862 * @}
AnnaBridge 158:1c57384330a6 2863 */
AnnaBridge 158:1c57384330a6 2864
AnnaBridge 158:1c57384330a6 2865 /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enabled or Disabled Status
AnnaBridge 158:1c57384330a6 2866 * @brief Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
AnnaBridge 158:1c57384330a6 2867 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge 158:1c57384330a6 2868 * power consumption.
AnnaBridge 158:1c57384330a6 2869 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge 158:1c57384330a6 2870 * @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge 158:1c57384330a6 2871 * @{
AnnaBridge 158:1c57384330a6 2872 */
AnnaBridge 158:1c57384330a6 2873
AnnaBridge 158:1c57384330a6 2874 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != RESET)
AnnaBridge 158:1c57384330a6 2875
AnnaBridge 158:1c57384330a6 2876 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != RESET)
AnnaBridge 158:1c57384330a6 2877
AnnaBridge 158:1c57384330a6 2878 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != RESET)
AnnaBridge 158:1c57384330a6 2879
AnnaBridge 158:1c57384330a6 2880 #if defined(GPIOD)
AnnaBridge 158:1c57384330a6 2881 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != RESET)
AnnaBridge 158:1c57384330a6 2882 #endif /* GPIOD */
AnnaBridge 158:1c57384330a6 2883
AnnaBridge 158:1c57384330a6 2884 #if defined(GPIOE)
AnnaBridge 158:1c57384330a6 2885 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != RESET)
AnnaBridge 158:1c57384330a6 2886 #endif /* GPIOE */
AnnaBridge 158:1c57384330a6 2887
AnnaBridge 158:1c57384330a6 2888 #if defined(GPIOF)
AnnaBridge 158:1c57384330a6 2889 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != RESET)
AnnaBridge 158:1c57384330a6 2890 #endif /* GPIOF */
AnnaBridge 158:1c57384330a6 2891
AnnaBridge 158:1c57384330a6 2892 #if defined(GPIOG)
AnnaBridge 158:1c57384330a6 2893 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != RESET)
AnnaBridge 158:1c57384330a6 2894 #endif /* GPIOG */
AnnaBridge 158:1c57384330a6 2895
AnnaBridge 158:1c57384330a6 2896 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != RESET)
AnnaBridge 158:1c57384330a6 2897
AnnaBridge 158:1c57384330a6 2898 #if defined(GPIOI)
AnnaBridge 158:1c57384330a6 2899 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) != RESET)
AnnaBridge 158:1c57384330a6 2900 #endif /* GPIOI */
AnnaBridge 158:1c57384330a6 2901
AnnaBridge 158:1c57384330a6 2902 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != RESET)
AnnaBridge 158:1c57384330a6 2903
AnnaBridge 158:1c57384330a6 2904 #if defined(USB_OTG_FS)
AnnaBridge 158:1c57384330a6 2905 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) != RESET)
AnnaBridge 158:1c57384330a6 2906 #endif /* USB_OTG_FS */
AnnaBridge 158:1c57384330a6 2907
AnnaBridge 158:1c57384330a6 2908 #define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) != RESET)
AnnaBridge 158:1c57384330a6 2909
AnnaBridge 158:1c57384330a6 2910 #if defined(DCMI)
AnnaBridge 158:1c57384330a6 2911 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) != RESET)
AnnaBridge 158:1c57384330a6 2912 #endif /* DCMI */
AnnaBridge 158:1c57384330a6 2913
AnnaBridge 158:1c57384330a6 2914 #if defined(AES)
AnnaBridge 158:1c57384330a6 2915 #define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != RESET)
AnnaBridge 158:1c57384330a6 2916 #endif /* AES */
AnnaBridge 158:1c57384330a6 2917
AnnaBridge 158:1c57384330a6 2918 #if defined(HASH)
AnnaBridge 158:1c57384330a6 2919 #define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) != RESET)
AnnaBridge 158:1c57384330a6 2920 #endif /* HASH */
AnnaBridge 158:1c57384330a6 2921
AnnaBridge 158:1c57384330a6 2922 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != RESET)
AnnaBridge 158:1c57384330a6 2923
AnnaBridge 158:1c57384330a6 2924
AnnaBridge 158:1c57384330a6 2925 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == RESET)
AnnaBridge 158:1c57384330a6 2926
AnnaBridge 158:1c57384330a6 2927 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == RESET)
AnnaBridge 158:1c57384330a6 2928
AnnaBridge 158:1c57384330a6 2929 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == RESET)
AnnaBridge 158:1c57384330a6 2930
AnnaBridge 158:1c57384330a6 2931 #if defined(GPIOD)
AnnaBridge 158:1c57384330a6 2932 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == RESET)
AnnaBridge 158:1c57384330a6 2933 #endif /* GPIOD */
AnnaBridge 158:1c57384330a6 2934
AnnaBridge 158:1c57384330a6 2935 #if defined(GPIOE)
AnnaBridge 158:1c57384330a6 2936 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == RESET)
AnnaBridge 158:1c57384330a6 2937 #endif /* GPIOE */
AnnaBridge 158:1c57384330a6 2938
AnnaBridge 158:1c57384330a6 2939 #if defined(GPIOF)
AnnaBridge 158:1c57384330a6 2940 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == RESET)
AnnaBridge 158:1c57384330a6 2941 #endif /* GPIOF */
AnnaBridge 158:1c57384330a6 2942
AnnaBridge 158:1c57384330a6 2943 #if defined(GPIOG)
AnnaBridge 158:1c57384330a6 2944 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == RESET)
AnnaBridge 158:1c57384330a6 2945 #endif /* GPIOG */
AnnaBridge 158:1c57384330a6 2946
AnnaBridge 158:1c57384330a6 2947 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == RESET)
AnnaBridge 158:1c57384330a6 2948
AnnaBridge 158:1c57384330a6 2949 #if defined(GPIOI)
AnnaBridge 158:1c57384330a6 2950 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) == RESET)
AnnaBridge 158:1c57384330a6 2951 #endif /* GPIOI */
AnnaBridge 158:1c57384330a6 2952
AnnaBridge 158:1c57384330a6 2953 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == RESET)
AnnaBridge 158:1c57384330a6 2954
AnnaBridge 158:1c57384330a6 2955 #if defined(USB_OTG_FS)
AnnaBridge 158:1c57384330a6 2956 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) == RESET)
AnnaBridge 158:1c57384330a6 2957 #endif /* USB_OTG_FS */
AnnaBridge 158:1c57384330a6 2958
AnnaBridge 158:1c57384330a6 2959 #define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) == RESET)
AnnaBridge 158:1c57384330a6 2960
AnnaBridge 158:1c57384330a6 2961 #if defined(DCMI)
AnnaBridge 158:1c57384330a6 2962 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) == RESET)
AnnaBridge 158:1c57384330a6 2963 #endif /* DCMI */
AnnaBridge 158:1c57384330a6 2964
AnnaBridge 158:1c57384330a6 2965 #if defined(AES)
AnnaBridge 158:1c57384330a6 2966 #define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == RESET)
AnnaBridge 158:1c57384330a6 2967 #endif /* AES */
AnnaBridge 158:1c57384330a6 2968
AnnaBridge 158:1c57384330a6 2969 #if defined(HASH)
AnnaBridge 158:1c57384330a6 2970 #define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) == RESET)
AnnaBridge 158:1c57384330a6 2971 #endif /* HASH */
AnnaBridge 158:1c57384330a6 2972
AnnaBridge 158:1c57384330a6 2973 #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == RESET)
AnnaBridge 158:1c57384330a6 2974
AnnaBridge 158:1c57384330a6 2975 /**
AnnaBridge 158:1c57384330a6 2976 * @}
AnnaBridge 158:1c57384330a6 2977 */
AnnaBridge 158:1c57384330a6 2978
AnnaBridge 158:1c57384330a6 2979 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock Sleep Enabled or Disabled Status
AnnaBridge 158:1c57384330a6 2980 * @brief Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not.
AnnaBridge 158:1c57384330a6 2981 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge 158:1c57384330a6 2982 * power consumption.
AnnaBridge 158:1c57384330a6 2983 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge 158:1c57384330a6 2984 * @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge 158:1c57384330a6 2985 * @{
AnnaBridge 158:1c57384330a6 2986 */
AnnaBridge 158:1c57384330a6 2987
AnnaBridge 158:1c57384330a6 2988 #if defined(QUADSPI)
AnnaBridge 158:1c57384330a6 2989 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != RESET)
AnnaBridge 158:1c57384330a6 2990 #endif /* QUADSPI */
AnnaBridge 158:1c57384330a6 2991
AnnaBridge 158:1c57384330a6 2992 #if defined(FMC_BANK1)
AnnaBridge 158:1c57384330a6 2993 #define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != RESET)
AnnaBridge 158:1c57384330a6 2994 #endif /* FMC_BANK1 */
AnnaBridge 158:1c57384330a6 2995
AnnaBridge 158:1c57384330a6 2996 #if defined(QUADSPI)
AnnaBridge 158:1c57384330a6 2997 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == RESET)
AnnaBridge 158:1c57384330a6 2998 #endif /* QUADSPI */
AnnaBridge 158:1c57384330a6 2999
AnnaBridge 158:1c57384330a6 3000 #if defined(FMC_BANK1)
AnnaBridge 158:1c57384330a6 3001 #define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == RESET)
AnnaBridge 158:1c57384330a6 3002 #endif /* FMC_BANK1 */
AnnaBridge 158:1c57384330a6 3003
AnnaBridge 158:1c57384330a6 3004 /**
AnnaBridge 158:1c57384330a6 3005 * @}
AnnaBridge 158:1c57384330a6 3006 */
AnnaBridge 158:1c57384330a6 3007
AnnaBridge 158:1c57384330a6 3008 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status
AnnaBridge 158:1c57384330a6 3009 * @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
AnnaBridge 158:1c57384330a6 3010 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge 158:1c57384330a6 3011 * power consumption.
AnnaBridge 158:1c57384330a6 3012 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge 158:1c57384330a6 3013 * @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge 158:1c57384330a6 3014 * @{
AnnaBridge 158:1c57384330a6 3015 */
AnnaBridge 158:1c57384330a6 3016
AnnaBridge 158:1c57384330a6 3017 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != RESET)
AnnaBridge 158:1c57384330a6 3018
AnnaBridge 158:1c57384330a6 3019 #if defined(TIM3)
AnnaBridge 158:1c57384330a6 3020 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != RESET)
AnnaBridge 158:1c57384330a6 3021 #endif /* TIM3 */
AnnaBridge 158:1c57384330a6 3022
AnnaBridge 158:1c57384330a6 3023 #if defined(TIM4)
AnnaBridge 158:1c57384330a6 3024 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != RESET)
AnnaBridge 158:1c57384330a6 3025 #endif /* TIM4 */
AnnaBridge 158:1c57384330a6 3026
AnnaBridge 158:1c57384330a6 3027 #if defined(TIM5)
AnnaBridge 158:1c57384330a6 3028 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != RESET)
AnnaBridge 158:1c57384330a6 3029 #endif /* TIM5 */
AnnaBridge 158:1c57384330a6 3030
AnnaBridge 158:1c57384330a6 3031 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != RESET)
AnnaBridge 158:1c57384330a6 3032
AnnaBridge 158:1c57384330a6 3033 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != RESET)
AnnaBridge 158:1c57384330a6 3034
AnnaBridge 158:1c57384330a6 3035 #if defined(LCD)
AnnaBridge 158:1c57384330a6 3036 #define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) != RESET)
AnnaBridge 158:1c57384330a6 3037 #endif /* LCD */
AnnaBridge 158:1c57384330a6 3038
AnnaBridge 158:1c57384330a6 3039 #if defined(RCC_APB1SMENR1_RTCAPBSMEN)
AnnaBridge 158:1c57384330a6 3040 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != RESET)
AnnaBridge 158:1c57384330a6 3041 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */
AnnaBridge 158:1c57384330a6 3042
AnnaBridge 158:1c57384330a6 3043 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != RESET)
AnnaBridge 158:1c57384330a6 3044
AnnaBridge 158:1c57384330a6 3045 #if defined(SPI2)
AnnaBridge 158:1c57384330a6 3046 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != RESET)
AnnaBridge 158:1c57384330a6 3047 #endif /* SPI2 */
AnnaBridge 158:1c57384330a6 3048
AnnaBridge 158:1c57384330a6 3049 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != RESET)
AnnaBridge 158:1c57384330a6 3050
AnnaBridge 158:1c57384330a6 3051 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != RESET)
AnnaBridge 158:1c57384330a6 3052
AnnaBridge 158:1c57384330a6 3053 #if defined(USART3)
AnnaBridge 158:1c57384330a6 3054 #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != RESET)
AnnaBridge 158:1c57384330a6 3055 #endif /* USART3 */
AnnaBridge 158:1c57384330a6 3056
AnnaBridge 158:1c57384330a6 3057 #if defined(UART4)
AnnaBridge 158:1c57384330a6 3058 #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != RESET)
AnnaBridge 158:1c57384330a6 3059 #endif /* UART4 */
AnnaBridge 158:1c57384330a6 3060
AnnaBridge 158:1c57384330a6 3061 #if defined(UART5)
AnnaBridge 158:1c57384330a6 3062 #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != RESET)
AnnaBridge 158:1c57384330a6 3063 #endif /* UART5 */
AnnaBridge 158:1c57384330a6 3064
AnnaBridge 158:1c57384330a6 3065 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != RESET)
AnnaBridge 158:1c57384330a6 3066
AnnaBridge 158:1c57384330a6 3067 #if defined(I2C2)
AnnaBridge 158:1c57384330a6 3068 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != RESET)
AnnaBridge 158:1c57384330a6 3069 #endif /* I2C2 */
AnnaBridge 158:1c57384330a6 3070
AnnaBridge 158:1c57384330a6 3071 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != RESET)
AnnaBridge 158:1c57384330a6 3072
AnnaBridge 158:1c57384330a6 3073 #if defined(I2C4)
AnnaBridge 158:1c57384330a6 3074 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) != RESET)
AnnaBridge 158:1c57384330a6 3075 #endif /* I2C4 */
AnnaBridge 158:1c57384330a6 3076
AnnaBridge 158:1c57384330a6 3077 #if defined(CRS)
AnnaBridge 158:1c57384330a6 3078 #define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != RESET)
AnnaBridge 158:1c57384330a6 3079 #endif /* CRS */
AnnaBridge 158:1c57384330a6 3080
AnnaBridge 158:1c57384330a6 3081 #define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) != RESET)
AnnaBridge 158:1c57384330a6 3082
AnnaBridge 158:1c57384330a6 3083 #if defined(CAN2)
AnnaBridge 158:1c57384330a6 3084 #define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) != RESET)
AnnaBridge 158:1c57384330a6 3085 #endif /* CAN2 */
AnnaBridge 158:1c57384330a6 3086
AnnaBridge 158:1c57384330a6 3087 #if defined(USB)
AnnaBridge 158:1c57384330a6 3088 #define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) != RESET)
AnnaBridge 158:1c57384330a6 3089 #endif /* USB */
AnnaBridge 158:1c57384330a6 3090
AnnaBridge 158:1c57384330a6 3091 #define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != RESET)
AnnaBridge 158:1c57384330a6 3092
AnnaBridge 158:1c57384330a6 3093 #define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) != RESET)
AnnaBridge 158:1c57384330a6 3094
AnnaBridge 158:1c57384330a6 3095 #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) != RESET)
AnnaBridge 158:1c57384330a6 3096
AnnaBridge 158:1c57384330a6 3097 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != RESET)
AnnaBridge 158:1c57384330a6 3098
AnnaBridge 158:1c57384330a6 3099 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != RESET)
AnnaBridge 158:1c57384330a6 3100
AnnaBridge 158:1c57384330a6 3101 #if defined(SWPMI1)
AnnaBridge 158:1c57384330a6 3102 #define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) != RESET)
AnnaBridge 158:1c57384330a6 3103 #endif /* SWPMI1 */
AnnaBridge 158:1c57384330a6 3104
AnnaBridge 158:1c57384330a6 3105 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != RESET)
AnnaBridge 158:1c57384330a6 3106
AnnaBridge 158:1c57384330a6 3107
AnnaBridge 158:1c57384330a6 3108 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == RESET)
AnnaBridge 158:1c57384330a6 3109
AnnaBridge 158:1c57384330a6 3110 #if defined(TIM3)
AnnaBridge 158:1c57384330a6 3111 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == RESET)
AnnaBridge 158:1c57384330a6 3112 #endif /* TIM3 */
AnnaBridge 158:1c57384330a6 3113
AnnaBridge 158:1c57384330a6 3114 #if defined(TIM4)
AnnaBridge 158:1c57384330a6 3115 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == RESET)
AnnaBridge 158:1c57384330a6 3116 #endif /* TIM4 */
AnnaBridge 158:1c57384330a6 3117
AnnaBridge 158:1c57384330a6 3118 #if defined(TIM5)
AnnaBridge 158:1c57384330a6 3119 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == RESET)
AnnaBridge 158:1c57384330a6 3120 #endif /* TIM5 */
AnnaBridge 158:1c57384330a6 3121
AnnaBridge 158:1c57384330a6 3122 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == RESET)
AnnaBridge 158:1c57384330a6 3123
AnnaBridge 158:1c57384330a6 3124 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == RESET)
AnnaBridge 158:1c57384330a6 3125
AnnaBridge 158:1c57384330a6 3126 #if defined(LCD)
AnnaBridge 158:1c57384330a6 3127 #define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) == RESET)
AnnaBridge 158:1c57384330a6 3128 #endif /* LCD */
AnnaBridge 158:1c57384330a6 3129
AnnaBridge 158:1c57384330a6 3130 #if defined(RCC_APB1SMENR1_RTCAPBSMEN)
AnnaBridge 158:1c57384330a6 3131 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == RESET)
AnnaBridge 158:1c57384330a6 3132 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */
AnnaBridge 158:1c57384330a6 3133
AnnaBridge 158:1c57384330a6 3134 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == RESET)
AnnaBridge 158:1c57384330a6 3135
AnnaBridge 158:1c57384330a6 3136 #if defined(SPI2)
AnnaBridge 158:1c57384330a6 3137 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == RESET)
AnnaBridge 158:1c57384330a6 3138 #endif /* SPI2 */
AnnaBridge 158:1c57384330a6 3139
AnnaBridge 158:1c57384330a6 3140 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == RESET)
AnnaBridge 158:1c57384330a6 3141
AnnaBridge 158:1c57384330a6 3142 #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == RESET)
AnnaBridge 158:1c57384330a6 3143
AnnaBridge 158:1c57384330a6 3144 #if defined(USART3)
AnnaBridge 158:1c57384330a6 3145 #define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == RESET)
AnnaBridge 158:1c57384330a6 3146 #endif /* USART3 */
AnnaBridge 158:1c57384330a6 3147
AnnaBridge 158:1c57384330a6 3148 #if defined(UART4)
AnnaBridge 158:1c57384330a6 3149 #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == RESET)
AnnaBridge 158:1c57384330a6 3150 #endif /* UART4 */
AnnaBridge 158:1c57384330a6 3151
AnnaBridge 158:1c57384330a6 3152 #if defined(UART5)
AnnaBridge 158:1c57384330a6 3153 #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == RESET)
AnnaBridge 158:1c57384330a6 3154 #endif /* UART5 */
AnnaBridge 158:1c57384330a6 3155
AnnaBridge 158:1c57384330a6 3156 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == RESET)
AnnaBridge 158:1c57384330a6 3157
AnnaBridge 158:1c57384330a6 3158 #if defined(I2C2)
AnnaBridge 158:1c57384330a6 3159 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == RESET)
AnnaBridge 158:1c57384330a6 3160 #endif /* I2C2 */
AnnaBridge 158:1c57384330a6 3161
AnnaBridge 158:1c57384330a6 3162 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == RESET)
AnnaBridge 158:1c57384330a6 3163
AnnaBridge 158:1c57384330a6 3164 #if defined(I2C4)
AnnaBridge 158:1c57384330a6 3165 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) == RESET)
AnnaBridge 158:1c57384330a6 3166 #endif /* I2C4 */
AnnaBridge 158:1c57384330a6 3167
AnnaBridge 158:1c57384330a6 3168 #if defined(CRS)
AnnaBridge 158:1c57384330a6 3169 #define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == RESET)
AnnaBridge 158:1c57384330a6 3170 #endif /* CRS */
AnnaBridge 158:1c57384330a6 3171
AnnaBridge 158:1c57384330a6 3172 #define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) == RESET)
AnnaBridge 158:1c57384330a6 3173
AnnaBridge 158:1c57384330a6 3174 #if defined(CAN2)
AnnaBridge 158:1c57384330a6 3175 #define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) == RESET)
AnnaBridge 158:1c57384330a6 3176 #endif /* CAN2 */
AnnaBridge 158:1c57384330a6 3177
AnnaBridge 158:1c57384330a6 3178 #if defined(USB)
AnnaBridge 158:1c57384330a6 3179 #define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) == RESET)
AnnaBridge 158:1c57384330a6 3180 #endif /* USB */
AnnaBridge 158:1c57384330a6 3181
AnnaBridge 158:1c57384330a6 3182 #define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == RESET)
AnnaBridge 158:1c57384330a6 3183
AnnaBridge 158:1c57384330a6 3184 #define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) == RESET)
AnnaBridge 158:1c57384330a6 3185
AnnaBridge 158:1c57384330a6 3186 #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) == RESET)
AnnaBridge 158:1c57384330a6 3187
AnnaBridge 158:1c57384330a6 3188 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == RESET)
AnnaBridge 158:1c57384330a6 3189
AnnaBridge 158:1c57384330a6 3190 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == RESET)
AnnaBridge 158:1c57384330a6 3191
AnnaBridge 158:1c57384330a6 3192 #if defined(SWPMI1)
AnnaBridge 158:1c57384330a6 3193 #define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) == RESET)
AnnaBridge 158:1c57384330a6 3194 #endif /* SWPMI1 */
AnnaBridge 158:1c57384330a6 3195
AnnaBridge 158:1c57384330a6 3196 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) == RESET)
AnnaBridge 158:1c57384330a6 3197
AnnaBridge 158:1c57384330a6 3198 /**
AnnaBridge 158:1c57384330a6 3199 * @}
AnnaBridge 158:1c57384330a6 3200 */
AnnaBridge 158:1c57384330a6 3201
AnnaBridge 158:1c57384330a6 3202 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status
AnnaBridge 158:1c57384330a6 3203 * @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
AnnaBridge 158:1c57384330a6 3204 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge 158:1c57384330a6 3205 * power consumption.
AnnaBridge 158:1c57384330a6 3206 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge 158:1c57384330a6 3207 * @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge 158:1c57384330a6 3208 * @{
AnnaBridge 158:1c57384330a6 3209 */
AnnaBridge 158:1c57384330a6 3210
AnnaBridge 158:1c57384330a6 3211 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != RESET)
AnnaBridge 158:1c57384330a6 3212
AnnaBridge 158:1c57384330a6 3213 #if defined(SDMMC1)
AnnaBridge 158:1c57384330a6 3214 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) != RESET)
AnnaBridge 158:1c57384330a6 3215 #endif /* SDMMC1 */
AnnaBridge 158:1c57384330a6 3216
AnnaBridge 158:1c57384330a6 3217 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != RESET)
AnnaBridge 158:1c57384330a6 3218
AnnaBridge 158:1c57384330a6 3219 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != RESET)
AnnaBridge 158:1c57384330a6 3220
AnnaBridge 158:1c57384330a6 3221 #if defined(TIM8)
AnnaBridge 158:1c57384330a6 3222 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != RESET)
AnnaBridge 158:1c57384330a6 3223 #endif /* TIM8 */
AnnaBridge 158:1c57384330a6 3224
AnnaBridge 158:1c57384330a6 3225 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != RESET)
AnnaBridge 158:1c57384330a6 3226
AnnaBridge 158:1c57384330a6 3227 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != RESET)
AnnaBridge 158:1c57384330a6 3228
AnnaBridge 158:1c57384330a6 3229 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != RESET)
AnnaBridge 158:1c57384330a6 3230
AnnaBridge 158:1c57384330a6 3231 #if defined(TIM17)
AnnaBridge 158:1c57384330a6 3232 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != RESET)
AnnaBridge 158:1c57384330a6 3233 #endif /* TIM17 */
AnnaBridge 158:1c57384330a6 3234
AnnaBridge 158:1c57384330a6 3235 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != RESET)
AnnaBridge 158:1c57384330a6 3236
AnnaBridge 158:1c57384330a6 3237 #if defined(SAI2)
AnnaBridge 158:1c57384330a6 3238 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) != RESET)
AnnaBridge 158:1c57384330a6 3239 #endif /* SAI2 */
AnnaBridge 158:1c57384330a6 3240
AnnaBridge 158:1c57384330a6 3241 #if defined(DFSDM1_Filter0)
AnnaBridge 158:1c57384330a6 3242 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) != RESET)
AnnaBridge 158:1c57384330a6 3243 #endif /* DFSDM1_Filter0 */
AnnaBridge 158:1c57384330a6 3244
AnnaBridge 158:1c57384330a6 3245
AnnaBridge 158:1c57384330a6 3246 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == RESET)
AnnaBridge 158:1c57384330a6 3247
AnnaBridge 158:1c57384330a6 3248 #if defined(SDMMC1)
AnnaBridge 158:1c57384330a6 3249 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) == RESET)
AnnaBridge 158:1c57384330a6 3250 #endif /* SDMMC1 */
AnnaBridge 158:1c57384330a6 3251
AnnaBridge 158:1c57384330a6 3252 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == RESET)
AnnaBridge 158:1c57384330a6 3253
AnnaBridge 158:1c57384330a6 3254 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == RESET)
AnnaBridge 158:1c57384330a6 3255
AnnaBridge 158:1c57384330a6 3256 #if defined(TIM8)
AnnaBridge 158:1c57384330a6 3257 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == RESET)
AnnaBridge 158:1c57384330a6 3258 #endif /* TIM8 */
AnnaBridge 158:1c57384330a6 3259
AnnaBridge 158:1c57384330a6 3260 #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == RESET)
AnnaBridge 158:1c57384330a6 3261
AnnaBridge 158:1c57384330a6 3262 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == RESET)
AnnaBridge 158:1c57384330a6 3263
AnnaBridge 158:1c57384330a6 3264 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == RESET)
AnnaBridge 158:1c57384330a6 3265
AnnaBridge 158:1c57384330a6 3266 #if defined(TIM17)
AnnaBridge 158:1c57384330a6 3267 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == RESET)
AnnaBridge 158:1c57384330a6 3268 #endif /* TIM17 */
AnnaBridge 158:1c57384330a6 3269
AnnaBridge 158:1c57384330a6 3270 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == RESET)
AnnaBridge 158:1c57384330a6 3271
AnnaBridge 158:1c57384330a6 3272 #if defined(SAI2)
AnnaBridge 158:1c57384330a6 3273 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) == RESET)
AnnaBridge 158:1c57384330a6 3274 #endif /* SAI2 */
AnnaBridge 158:1c57384330a6 3275
AnnaBridge 158:1c57384330a6 3276 #if defined(DFSDM1_Filter0)
AnnaBridge 158:1c57384330a6 3277 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) == RESET)
AnnaBridge 158:1c57384330a6 3278 #endif /* DFSDM1_Filter0 */
AnnaBridge 158:1c57384330a6 3279
AnnaBridge 158:1c57384330a6 3280 /**
AnnaBridge 158:1c57384330a6 3281 * @}
AnnaBridge 158:1c57384330a6 3282 */
AnnaBridge 158:1c57384330a6 3283
AnnaBridge 158:1c57384330a6 3284 /** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset
AnnaBridge 158:1c57384330a6 3285 * @{
AnnaBridge 158:1c57384330a6 3286 */
AnnaBridge 158:1c57384330a6 3287
AnnaBridge 158:1c57384330a6 3288 /** @brief Macros to force or release the Backup domain reset.
AnnaBridge 158:1c57384330a6 3289 * @note This function resets the RTC peripheral (including the backup registers)
AnnaBridge 158:1c57384330a6 3290 * and the RTC clock source selection in RCC_CSR register.
AnnaBridge 158:1c57384330a6 3291 * @note The BKPSRAM is not affected by this reset.
AnnaBridge 158:1c57384330a6 3292 * @retval None
AnnaBridge 158:1c57384330a6 3293 */
AnnaBridge 158:1c57384330a6 3294 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
AnnaBridge 158:1c57384330a6 3295
AnnaBridge 158:1c57384330a6 3296 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
AnnaBridge 158:1c57384330a6 3297
AnnaBridge 158:1c57384330a6 3298 /**
AnnaBridge 158:1c57384330a6 3299 * @}
AnnaBridge 158:1c57384330a6 3300 */
AnnaBridge 158:1c57384330a6 3301
AnnaBridge 158:1c57384330a6 3302 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
AnnaBridge 158:1c57384330a6 3303 * @{
AnnaBridge 158:1c57384330a6 3304 */
AnnaBridge 158:1c57384330a6 3305
AnnaBridge 158:1c57384330a6 3306 /** @brief Macros to enable or disable the RTC clock.
AnnaBridge 158:1c57384330a6 3307 * @note As the RTC is in the Backup domain and write access is denied to
AnnaBridge 158:1c57384330a6 3308 * this domain after reset, you have to enable write access using
AnnaBridge 158:1c57384330a6 3309 * HAL_PWR_EnableBkUpAccess() function before to configure the RTC
AnnaBridge 158:1c57384330a6 3310 * (to be done once after reset).
AnnaBridge 158:1c57384330a6 3311 * @note These macros must be used after the RTC clock source was selected.
AnnaBridge 158:1c57384330a6 3312 * @retval None
AnnaBridge 158:1c57384330a6 3313 */
AnnaBridge 158:1c57384330a6 3314 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
AnnaBridge 158:1c57384330a6 3315
AnnaBridge 158:1c57384330a6 3316 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
AnnaBridge 158:1c57384330a6 3317
AnnaBridge 158:1c57384330a6 3318 /**
AnnaBridge 158:1c57384330a6 3319 * @}
AnnaBridge 158:1c57384330a6 3320 */
AnnaBridge 158:1c57384330a6 3321
AnnaBridge 158:1c57384330a6 3322 /** @brief Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI).
AnnaBridge 158:1c57384330a6 3323 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
AnnaBridge 158:1c57384330a6 3324 * It is used (enabled by hardware) as system clock source after startup
AnnaBridge 158:1c57384330a6 3325 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
AnnaBridge 158:1c57384330a6 3326 * of the HSE used directly or indirectly as system clock (if the Clock
AnnaBridge 158:1c57384330a6 3327 * Security System CSS is enabled).
AnnaBridge 158:1c57384330a6 3328 * @note HSI can not be stopped if it is used as system clock source. In this case,
AnnaBridge 158:1c57384330a6 3329 * you have to select another source of the system clock then stop the HSI.
AnnaBridge 158:1c57384330a6 3330 * @note After enabling the HSI, the application software should wait on HSIRDY
AnnaBridge 158:1c57384330a6 3331 * flag to be set indicating that HSI clock is stable and can be used as
AnnaBridge 158:1c57384330a6 3332 * system clock source.
AnnaBridge 158:1c57384330a6 3333 * This parameter can be: ENABLE or DISABLE.
AnnaBridge 158:1c57384330a6 3334 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
AnnaBridge 158:1c57384330a6 3335 * clock cycles.
AnnaBridge 158:1c57384330a6 3336 * @retval None
AnnaBridge 158:1c57384330a6 3337 */
AnnaBridge 158:1c57384330a6 3338 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
AnnaBridge 158:1c57384330a6 3339
AnnaBridge 158:1c57384330a6 3340 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
AnnaBridge 158:1c57384330a6 3341
AnnaBridge 158:1c57384330a6 3342 /** @brief Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value.
AnnaBridge 158:1c57384330a6 3343 * @note The calibration is used to compensate for the variations in voltage
AnnaBridge 158:1c57384330a6 3344 * and temperature that influence the frequency of the internal HSI RC.
AnnaBridge 158:1c57384330a6 3345 * @param __HSICALIBRATIONVALUE__: specifies the calibration trimming value
AnnaBridge 158:1c57384330a6 3346 * (default is RCC_HSICALIBRATION_DEFAULT).
AnnaBridge 158:1c57384330a6 3347 * This parameter must be a number between 0 and 0x1F (STM32L43x/STM32L44x/STM32L47x/STM32L48x) or 0x7F (for other devices).
AnnaBridge 158:1c57384330a6 3348 * @retval None
AnnaBridge 158:1c57384330a6 3349 */
AnnaBridge 158:1c57384330a6 3350 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \
AnnaBridge 158:1c57384330a6 3351 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << POSITION_VAL(RCC_ICSCR_HSITRIM))
AnnaBridge 158:1c57384330a6 3352
AnnaBridge 158:1c57384330a6 3353 /**
AnnaBridge 158:1c57384330a6 3354 * @brief Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI)
AnnaBridge 158:1c57384330a6 3355 * in parallel to the Internal Multi Speed oscillator (MSI) used at system wakeup.
AnnaBridge 158:1c57384330a6 3356 * @note The enable of this function has not effect on the HSION bit.
AnnaBridge 158:1c57384330a6 3357 * This parameter can be: ENABLE or DISABLE.
AnnaBridge 158:1c57384330a6 3358 * @retval None
AnnaBridge 158:1c57384330a6 3359 */
AnnaBridge 158:1c57384330a6 3360 #define __HAL_RCC_HSIAUTOMATIC_START_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIASFS)
AnnaBridge 158:1c57384330a6 3361
AnnaBridge 158:1c57384330a6 3362 #define __HAL_RCC_HSIAUTOMATIC_START_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS)
AnnaBridge 158:1c57384330a6 3363
AnnaBridge 158:1c57384330a6 3364 /**
AnnaBridge 158:1c57384330a6 3365 * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
AnnaBridge 158:1c57384330a6 3366 * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.
AnnaBridge 158:1c57384330a6 3367 * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication
AnnaBridge 158:1c57384330a6 3368 * speed because of the HSI startup time.
AnnaBridge 158:1c57384330a6 3369 * @note The enable of this function has not effect on the HSION bit.
AnnaBridge 158:1c57384330a6 3370 * This parameter can be: ENABLE or DISABLE.
AnnaBridge 158:1c57384330a6 3371 * @retval None
AnnaBridge 158:1c57384330a6 3372 */
AnnaBridge 158:1c57384330a6 3373 #define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
AnnaBridge 158:1c57384330a6 3374
AnnaBridge 158:1c57384330a6 3375 #define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
AnnaBridge 158:1c57384330a6 3376
AnnaBridge 158:1c57384330a6 3377 /**
AnnaBridge 158:1c57384330a6 3378 * @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI).
AnnaBridge 158:1c57384330a6 3379 * @note The MSI is stopped by hardware when entering STOP and STANDBY modes.
AnnaBridge 158:1c57384330a6 3380 * It is used (enabled by hardware) as system clock source after
AnnaBridge 158:1c57384330a6 3381 * startup from Reset, wakeup from STOP and STANDBY mode, or in case
AnnaBridge 158:1c57384330a6 3382 * of failure of the HSE used directly or indirectly as system clock
AnnaBridge 158:1c57384330a6 3383 * (if the Clock Security System CSS is enabled).
AnnaBridge 158:1c57384330a6 3384 * @note MSI can not be stopped if it is used as system clock source.
AnnaBridge 158:1c57384330a6 3385 * In this case, you have to select another source of the system
AnnaBridge 158:1c57384330a6 3386 * clock then stop the MSI.
AnnaBridge 158:1c57384330a6 3387 * @note After enabling the MSI, the application software should wait on
AnnaBridge 158:1c57384330a6 3388 * MSIRDY flag to be set indicating that MSI clock is stable and can
AnnaBridge 158:1c57384330a6 3389 * be used as system clock source.
AnnaBridge 158:1c57384330a6 3390 * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
AnnaBridge 158:1c57384330a6 3391 * clock cycles.
AnnaBridge 158:1c57384330a6 3392 * @retval None
AnnaBridge 158:1c57384330a6 3393 */
AnnaBridge 158:1c57384330a6 3394 #define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSION)
AnnaBridge 158:1c57384330a6 3395
AnnaBridge 158:1c57384330a6 3396 #define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION)
AnnaBridge 158:1c57384330a6 3397
AnnaBridge 158:1c57384330a6 3398 /** @brief Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value.
AnnaBridge 158:1c57384330a6 3399 * @note The calibration is used to compensate for the variations in voltage
AnnaBridge 158:1c57384330a6 3400 * and temperature that influence the frequency of the internal MSI RC.
AnnaBridge 158:1c57384330a6 3401 * Refer to the Application Note AN3300 for more details on how to
AnnaBridge 158:1c57384330a6 3402 * calibrate the MSI.
AnnaBridge 158:1c57384330a6 3403 * @param __MSICALIBRATIONVALUE__: specifies the calibration trimming value
AnnaBridge 158:1c57384330a6 3404 * (default is RCC_MSICALIBRATION_DEFAULT).
AnnaBridge 158:1c57384330a6 3405 * This parameter must be a number between 0 and 255.
AnnaBridge 158:1c57384330a6 3406 * @retval None
AnnaBridge 158:1c57384330a6 3407 */
AnnaBridge 158:1c57384330a6 3408 #define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) \
AnnaBridge 158:1c57384330a6 3409 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(__MSICALIBRATIONVALUE__) << 8)
AnnaBridge 158:1c57384330a6 3410
AnnaBridge 158:1c57384330a6 3411 /**
AnnaBridge 158:1c57384330a6 3412 * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode
AnnaBridge 158:1c57384330a6 3413 * @note After restart from Reset , the MSI clock is around 4 MHz.
AnnaBridge 158:1c57384330a6 3414 * After stop the startup clock can be MSI (at any of its possible
AnnaBridge 158:1c57384330a6 3415 * frequencies, the one that was used before entering stop mode) or HSI.
AnnaBridge 158:1c57384330a6 3416 * After Standby its frequency can be selected between 4 possible values
AnnaBridge 158:1c57384330a6 3417 * (1, 2, 4 or 8 MHz).
AnnaBridge 158:1c57384330a6 3418 * @note MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready
AnnaBridge 158:1c57384330a6 3419 * (MSIRDY=1).
AnnaBridge 158:1c57384330a6 3420 * @note The MSI clock range after reset can be modified on the fly.
AnnaBridge 158:1c57384330a6 3421 * @param __MSIRANGEVALUE__: specifies the MSI clock range.
AnnaBridge 158:1c57384330a6 3422 * This parameter must be one of the following values:
AnnaBridge 158:1c57384330a6 3423 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz
AnnaBridge 158:1c57384330a6 3424 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz
AnnaBridge 158:1c57384330a6 3425 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz
AnnaBridge 158:1c57384330a6 3426 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz
AnnaBridge 158:1c57384330a6 3427 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz
AnnaBridge 158:1c57384330a6 3428 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz
AnnaBridge 158:1c57384330a6 3429 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset)
AnnaBridge 158:1c57384330a6 3430 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz
AnnaBridge 158:1c57384330a6 3431 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz
AnnaBridge 158:1c57384330a6 3432 * @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz
AnnaBridge 158:1c57384330a6 3433 * @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz
AnnaBridge 158:1c57384330a6 3434 * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz
AnnaBridge 158:1c57384330a6 3435 * @retval None
AnnaBridge 158:1c57384330a6 3436 */
AnnaBridge 158:1c57384330a6 3437 #define __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__) \
AnnaBridge 158:1c57384330a6 3438 do { \
AnnaBridge 158:1c57384330a6 3439 SET_BIT(RCC->CR, RCC_CR_MSIRGSEL); \
AnnaBridge 158:1c57384330a6 3440 MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, (__MSIRANGEVALUE__)); \
AnnaBridge 158:1c57384330a6 3441 } while(0)
AnnaBridge 158:1c57384330a6 3442
AnnaBridge 158:1c57384330a6 3443 /**
AnnaBridge 158:1c57384330a6 3444 * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode
AnnaBridge 158:1c57384330a6 3445 * After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz).
AnnaBridge 158:1c57384330a6 3446 * @param __MSIRANGEVALUE__: specifies the MSI clock range.
AnnaBridge 158:1c57384330a6 3447 * This parameter must be one of the following values:
AnnaBridge 158:1c57384330a6 3448 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz
AnnaBridge 158:1c57384330a6 3449 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz
AnnaBridge 158:1c57384330a6 3450 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset)
AnnaBridge 158:1c57384330a6 3451 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz
AnnaBridge 158:1c57384330a6 3452 * @retval None
AnnaBridge 158:1c57384330a6 3453 */
AnnaBridge 158:1c57384330a6 3454 #define __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) \
AnnaBridge 158:1c57384330a6 3455 MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, (__MSIRANGEVALUE__) << 4U)
AnnaBridge 158:1c57384330a6 3456
AnnaBridge 158:1c57384330a6 3457 /** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode
AnnaBridge 158:1c57384330a6 3458 * @retval MSI clock range.
AnnaBridge 158:1c57384330a6 3459 * This parameter must be one of the following values:
AnnaBridge 158:1c57384330a6 3460 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz
AnnaBridge 158:1c57384330a6 3461 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz
AnnaBridge 158:1c57384330a6 3462 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz
AnnaBridge 158:1c57384330a6 3463 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz
AnnaBridge 158:1c57384330a6 3464 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz
AnnaBridge 158:1c57384330a6 3465 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz
AnnaBridge 158:1c57384330a6 3466 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset)
AnnaBridge 158:1c57384330a6 3467 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz
AnnaBridge 158:1c57384330a6 3468 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz
AnnaBridge 158:1c57384330a6 3469 * @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz
AnnaBridge 158:1c57384330a6 3470 * @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz
AnnaBridge 158:1c57384330a6 3471 * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz
AnnaBridge 158:1c57384330a6 3472 */
AnnaBridge 158:1c57384330a6 3473 #define __HAL_RCC_GET_MSI_RANGE() \
AnnaBridge 158:1c57384330a6 3474 ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != RESET) ? \
AnnaBridge 158:1c57384330a6 3475 (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE)) : \
AnnaBridge 158:1c57384330a6 3476 (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4))
AnnaBridge 158:1c57384330a6 3477
AnnaBridge 158:1c57384330a6 3478 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
AnnaBridge 158:1c57384330a6 3479 * @note After enabling the LSI, the application software should wait on
AnnaBridge 158:1c57384330a6 3480 * LSIRDY flag to be set indicating that LSI clock is stable and can
AnnaBridge 158:1c57384330a6 3481 * be used to clock the IWDG and/or the RTC.
AnnaBridge 158:1c57384330a6 3482 * @note LSI can not be disabled if the IWDG is running.
AnnaBridge 158:1c57384330a6 3483 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
AnnaBridge 158:1c57384330a6 3484 * clock cycles.
AnnaBridge 158:1c57384330a6 3485 * @retval None
AnnaBridge 158:1c57384330a6 3486 */
AnnaBridge 158:1c57384330a6 3487 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
AnnaBridge 158:1c57384330a6 3488
AnnaBridge 158:1c57384330a6 3489 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
AnnaBridge 158:1c57384330a6 3490
AnnaBridge 158:1c57384330a6 3491 /**
AnnaBridge 158:1c57384330a6 3492 * @brief Macro to configure the External High Speed oscillator (HSE).
AnnaBridge 158:1c57384330a6 3493 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
AnnaBridge 158:1c57384330a6 3494 * supported by this macro. User should request a transition to HSE Off
AnnaBridge 158:1c57384330a6 3495 * first and then HSE On or HSE Bypass.
AnnaBridge 158:1c57384330a6 3496 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
AnnaBridge 158:1c57384330a6 3497 * software should wait on HSERDY flag to be set indicating that HSE clock
AnnaBridge 158:1c57384330a6 3498 * is stable and can be used to clock the PLL and/or system clock.
AnnaBridge 158:1c57384330a6 3499 * @note HSE state can not be changed if it is used directly or through the
AnnaBridge 158:1c57384330a6 3500 * PLL as system clock. In this case, you have to select another source
AnnaBridge 158:1c57384330a6 3501 * of the system clock then change the HSE state (ex. disable it).
AnnaBridge 158:1c57384330a6 3502 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
AnnaBridge 158:1c57384330a6 3503 * @note This function reset the CSSON bit, so if the clock security system(CSS)
AnnaBridge 158:1c57384330a6 3504 * was previously enabled you have to enable it again after calling this
AnnaBridge 158:1c57384330a6 3505 * function.
AnnaBridge 158:1c57384330a6 3506 * @param __STATE__: specifies the new state of the HSE.
AnnaBridge 158:1c57384330a6 3507 * This parameter can be one of the following values:
AnnaBridge 158:1c57384330a6 3508 * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after
AnnaBridge 158:1c57384330a6 3509 * 6 HSE oscillator clock cycles.
AnnaBridge 158:1c57384330a6 3510 * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator.
AnnaBridge 158:1c57384330a6 3511 * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock.
AnnaBridge 158:1c57384330a6 3512 * @retval None
AnnaBridge 158:1c57384330a6 3513 */
AnnaBridge 158:1c57384330a6 3514 #define __HAL_RCC_HSE_CONFIG(__STATE__) \
AnnaBridge 158:1c57384330a6 3515 do { \
AnnaBridge 158:1c57384330a6 3516 if((__STATE__) == RCC_HSE_ON) \
AnnaBridge 158:1c57384330a6 3517 { \
AnnaBridge 158:1c57384330a6 3518 SET_BIT(RCC->CR, RCC_CR_HSEON); \
AnnaBridge 158:1c57384330a6 3519 } \
AnnaBridge 158:1c57384330a6 3520 else if((__STATE__) == RCC_HSE_BYPASS) \
AnnaBridge 158:1c57384330a6 3521 { \
AnnaBridge 158:1c57384330a6 3522 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
AnnaBridge 158:1c57384330a6 3523 SET_BIT(RCC->CR, RCC_CR_HSEON); \
AnnaBridge 158:1c57384330a6 3524 } \
AnnaBridge 158:1c57384330a6 3525 else \
AnnaBridge 158:1c57384330a6 3526 { \
AnnaBridge 158:1c57384330a6 3527 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
AnnaBridge 158:1c57384330a6 3528 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
AnnaBridge 158:1c57384330a6 3529 } \
AnnaBridge 158:1c57384330a6 3530 } while(0)
AnnaBridge 158:1c57384330a6 3531
AnnaBridge 158:1c57384330a6 3532 /**
AnnaBridge 158:1c57384330a6 3533 * @brief Macro to configure the External Low Speed oscillator (LSE).
AnnaBridge 158:1c57384330a6 3534 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
AnnaBridge 158:1c57384330a6 3535 * supported by this macro. User should request a transition to LSE Off
AnnaBridge 158:1c57384330a6 3536 * first and then LSE On or LSE Bypass.
AnnaBridge 158:1c57384330a6 3537 * @note As the LSE is in the Backup domain and write access is denied to
AnnaBridge 158:1c57384330a6 3538 * this domain after reset, you have to enable write access using
AnnaBridge 158:1c57384330a6 3539 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
AnnaBridge 158:1c57384330a6 3540 * (to be done once after reset).
AnnaBridge 158:1c57384330a6 3541 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
AnnaBridge 158:1c57384330a6 3542 * software should wait on LSERDY flag to be set indicating that LSE clock
AnnaBridge 158:1c57384330a6 3543 * is stable and can be used to clock the RTC.
AnnaBridge 158:1c57384330a6 3544 * @param __STATE__: specifies the new state of the LSE.
AnnaBridge 158:1c57384330a6 3545 * This parameter can be one of the following values:
AnnaBridge 158:1c57384330a6 3546 * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after
AnnaBridge 158:1c57384330a6 3547 * 6 LSE oscillator clock cycles.
AnnaBridge 158:1c57384330a6 3548 * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator.
AnnaBridge 158:1c57384330a6 3549 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
AnnaBridge 158:1c57384330a6 3550 * @retval None
AnnaBridge 158:1c57384330a6 3551 */
AnnaBridge 158:1c57384330a6 3552 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
AnnaBridge 158:1c57384330a6 3553 do { \
AnnaBridge 158:1c57384330a6 3554 if((__STATE__) == RCC_LSE_ON) \
AnnaBridge 158:1c57384330a6 3555 { \
AnnaBridge 158:1c57384330a6 3556 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
AnnaBridge 158:1c57384330a6 3557 } \
AnnaBridge 158:1c57384330a6 3558 else if((__STATE__) == RCC_LSE_BYPASS) \
AnnaBridge 158:1c57384330a6 3559 { \
AnnaBridge 158:1c57384330a6 3560 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
AnnaBridge 158:1c57384330a6 3561 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
AnnaBridge 158:1c57384330a6 3562 } \
AnnaBridge 158:1c57384330a6 3563 else \
AnnaBridge 158:1c57384330a6 3564 { \
AnnaBridge 158:1c57384330a6 3565 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
AnnaBridge 158:1c57384330a6 3566 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
AnnaBridge 158:1c57384330a6 3567 } \
AnnaBridge 158:1c57384330a6 3568 } while(0)
AnnaBridge 158:1c57384330a6 3569
AnnaBridge 158:1c57384330a6 3570 #if defined(RCC_HSI48_SUPPORT)
AnnaBridge 158:1c57384330a6 3571
AnnaBridge 158:1c57384330a6 3572 /** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48).
AnnaBridge 158:1c57384330a6 3573 * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
AnnaBridge 158:1c57384330a6 3574 * @note After enabling the HSI48, the application software should wait on HSI48RDY
AnnaBridge 158:1c57384330a6 3575 * flag to be set indicating that HSI48 clock is stable.
AnnaBridge 158:1c57384330a6 3576 * This parameter can be: ENABLE or DISABLE.
AnnaBridge 158:1c57384330a6 3577 * @retval None
AnnaBridge 158:1c57384330a6 3578 */
AnnaBridge 158:1c57384330a6 3579 #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)
AnnaBridge 158:1c57384330a6 3580
AnnaBridge 158:1c57384330a6 3581 #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)
AnnaBridge 158:1c57384330a6 3582
AnnaBridge 158:1c57384330a6 3583 #endif /* RCC_HSI48_SUPPORT */
AnnaBridge 158:1c57384330a6 3584
AnnaBridge 158:1c57384330a6 3585 /** @brief Macros to configure the RTC clock (RTCCLK).
AnnaBridge 158:1c57384330a6 3586 * @note As the RTC clock configuration bits are in the Backup domain and write
AnnaBridge 158:1c57384330a6 3587 * access is denied to this domain after reset, you have to enable write
AnnaBridge 158:1c57384330a6 3588 * access using the Power Backup Access macro before to configure
AnnaBridge 158:1c57384330a6 3589 * the RTC clock source (to be done once after reset).
AnnaBridge 158:1c57384330a6 3590 * @note Once the RTC clock is configured it cannot be changed unless the
AnnaBridge 158:1c57384330a6 3591 * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by
AnnaBridge 158:1c57384330a6 3592 * a Power On Reset (POR).
AnnaBridge 158:1c57384330a6 3593 *
AnnaBridge 158:1c57384330a6 3594 * @param __RTC_CLKSOURCE__: specifies the RTC clock source.
AnnaBridge 158:1c57384330a6 3595 * This parameter can be one of the following values:
AnnaBridge 158:1c57384330a6 3596 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock.
AnnaBridge 158:1c57384330a6 3597 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock.
AnnaBridge 158:1c57384330a6 3598 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock.
AnnaBridge 158:1c57384330a6 3599 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected
AnnaBridge 158:1c57384330a6 3600 *
AnnaBridge 158:1c57384330a6 3601 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
AnnaBridge 158:1c57384330a6 3602 * work in STOP and STANDBY modes, and can be used as wakeup source.
AnnaBridge 158:1c57384330a6 3603 * However, when the HSE clock is used as RTC clock source, the RTC
AnnaBridge 158:1c57384330a6 3604 * cannot be used in STOP and STANDBY modes.
AnnaBridge 158:1c57384330a6 3605 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
AnnaBridge 158:1c57384330a6 3606 * RTC clock source).
AnnaBridge 158:1c57384330a6 3607 * @retval None
AnnaBridge 158:1c57384330a6 3608 */
AnnaBridge 158:1c57384330a6 3609 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \
AnnaBridge 158:1c57384330a6 3610 MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
AnnaBridge 158:1c57384330a6 3611
AnnaBridge 158:1c57384330a6 3612
AnnaBridge 158:1c57384330a6 3613 /** @brief Macro to get the RTC clock source.
AnnaBridge 158:1c57384330a6 3614 * @retval The returned value can be one of the following:
AnnaBridge 158:1c57384330a6 3615 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock.
AnnaBridge 158:1c57384330a6 3616 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock.
AnnaBridge 158:1c57384330a6 3617 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock.
AnnaBridge 158:1c57384330a6 3618 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected
AnnaBridge 158:1c57384330a6 3619 */
AnnaBridge 158:1c57384330a6 3620 #define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
AnnaBridge 158:1c57384330a6 3621
AnnaBridge 158:1c57384330a6 3622 /** @brief Macros to enable or disable the main PLL.
AnnaBridge 158:1c57384330a6 3623 * @note After enabling the main PLL, the application software should wait on
AnnaBridge 158:1c57384330a6 3624 * PLLRDY flag to be set indicating that PLL clock is stable and can
AnnaBridge 158:1c57384330a6 3625 * be used as system clock source.
AnnaBridge 158:1c57384330a6 3626 * @note The main PLL can not be disabled if it is used as system clock source
AnnaBridge 158:1c57384330a6 3627 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
AnnaBridge 158:1c57384330a6 3628 * @retval None
AnnaBridge 158:1c57384330a6 3629 */
AnnaBridge 158:1c57384330a6 3630 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
AnnaBridge 158:1c57384330a6 3631
AnnaBridge 158:1c57384330a6 3632 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
AnnaBridge 158:1c57384330a6 3633
AnnaBridge 158:1c57384330a6 3634 /** @brief Macro to configure the PLL clock source.
AnnaBridge 158:1c57384330a6 3635 * @note This function must be used only when the main PLL is disabled.
AnnaBridge 158:1c57384330a6 3636 * @param __PLLSOURCE__: specifies the PLL entry clock source.
AnnaBridge 158:1c57384330a6 3637 * This parameter can be one of the following values:
AnnaBridge 158:1c57384330a6 3638 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry
AnnaBridge 158:1c57384330a6 3639 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry
AnnaBridge 158:1c57384330a6 3640 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
AnnaBridge 158:1c57384330a6 3641 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
AnnaBridge 158:1c57384330a6 3642 * @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2).
AnnaBridge 158:1c57384330a6 3643 * @retval None
AnnaBridge 158:1c57384330a6 3644 *
AnnaBridge 158:1c57384330a6 3645 */
AnnaBridge 158:1c57384330a6 3646 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \
AnnaBridge 158:1c57384330a6 3647 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
AnnaBridge 158:1c57384330a6 3648
AnnaBridge 158:1c57384330a6 3649 /** @brief Macro to configure the PLL source division factor M.
AnnaBridge 158:1c57384330a6 3650 * @note This function must be used only when the main PLL is disabled.
AnnaBridge 158:1c57384330a6 3651 * @param __PLLM__: specifies the division factor for PLL VCO input clock
AnnaBridge 158:1c57384330a6 3652 * This parameter must be a number between Min_Data = 1 and Max_Data = 8.
AnnaBridge 158:1c57384330a6 3653 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
AnnaBridge 158:1c57384330a6 3654 * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency
AnnaBridge 158:1c57384330a6 3655 * of 16 MHz to limit PLL jitter.
AnnaBridge 158:1c57384330a6 3656 * @retval None
AnnaBridge 158:1c57384330a6 3657 *
AnnaBridge 158:1c57384330a6 3658 */
AnnaBridge 158:1c57384330a6 3659 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \
AnnaBridge 158:1c57384330a6 3660 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << 4U)
AnnaBridge 158:1c57384330a6 3661
AnnaBridge 158:1c57384330a6 3662 /**
AnnaBridge 158:1c57384330a6 3663 * @brief Macro to configure the main PLL clock source, multiplication and division factors.
AnnaBridge 158:1c57384330a6 3664 * @note This function must be used only when the main PLL is disabled.
AnnaBridge 158:1c57384330a6 3665 *
AnnaBridge 158:1c57384330a6 3666 * @param __PLLSOURCE__: specifies the PLL entry clock source.
AnnaBridge 158:1c57384330a6 3667 * This parameter can be one of the following values:
AnnaBridge 158:1c57384330a6 3668 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry
AnnaBridge 158:1c57384330a6 3669 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry
AnnaBridge 158:1c57384330a6 3670 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
AnnaBridge 158:1c57384330a6 3671 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
AnnaBridge 158:1c57384330a6 3672 * @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2).
AnnaBridge 158:1c57384330a6 3673 *
AnnaBridge 158:1c57384330a6 3674 * @param __PLLM__: specifies the division factor for PLL VCO input clock.
AnnaBridge 158:1c57384330a6 3675 * This parameter must be a number between 1 and 8.
AnnaBridge 158:1c57384330a6 3676 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
AnnaBridge 158:1c57384330a6 3677 * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency
AnnaBridge 158:1c57384330a6 3678 * of 16 MHz to limit PLL jitter.
AnnaBridge 158:1c57384330a6 3679 *
AnnaBridge 158:1c57384330a6 3680 * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock.
AnnaBridge 158:1c57384330a6 3681 * This parameter must be a number between 8 and 86.
AnnaBridge 158:1c57384330a6 3682 * @note You have to set the PLLN parameter correctly to ensure that the VCO
AnnaBridge 158:1c57384330a6 3683 * output frequency is between 64 and 344 MHz.
AnnaBridge 158:1c57384330a6 3684 *
AnnaBridge 158:1c57384330a6 3685 * @param __PLLP__: specifies the division factor for SAI clock.
AnnaBridge 158:1c57384330a6 3686 * This parameter must be a number in the range (7 or 17) for STM32L47x/STM32L48x
AnnaBridge 158:1c57384330a6 3687 * else (2 to 31).
AnnaBridge 158:1c57384330a6 3688 *
AnnaBridge 158:1c57384330a6 3689 * @param __PLLQ__: specifies the division factor for OTG FS, SDMMC1 and RNG clocks.
AnnaBridge 158:1c57384330a6 3690 * This parameter must be in the range (2, 4, 6 or 8).
AnnaBridge 158:1c57384330a6 3691 * @note If the USB OTG FS is used in your application, you have to set the
AnnaBridge 158:1c57384330a6 3692 * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
AnnaBridge 158:1c57384330a6 3693 * the SDMMC1 and RNG need a frequency lower than or equal to 48 MHz to work
AnnaBridge 158:1c57384330a6 3694 * correctly.
AnnaBridge 158:1c57384330a6 3695 * @param __PLLR__: specifies the division factor for the main system clock.
AnnaBridge 158:1c57384330a6 3696 * @note You have to set the PLLR parameter correctly to not exceed 80MHZ.
AnnaBridge 158:1c57384330a6 3697 * This parameter must be in the range (2, 4, 6 or 8).
AnnaBridge 158:1c57384330a6 3698 * @retval None
AnnaBridge 158:1c57384330a6 3699 */
AnnaBridge 158:1c57384330a6 3700 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
AnnaBridge 158:1c57384330a6 3701
AnnaBridge 158:1c57384330a6 3702 #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \
AnnaBridge 158:1c57384330a6 3703 (RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) | (uint32_t)((__PLLN__) << 8U) | \
AnnaBridge 158:1c57384330a6 3704 (uint32_t)(__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U) | \
AnnaBridge 158:1c57384330a6 3705 (uint32_t)((__PLLP__) << 27U))
AnnaBridge 158:1c57384330a6 3706
AnnaBridge 158:1c57384330a6 3707 #else
AnnaBridge 158:1c57384330a6 3708
AnnaBridge 158:1c57384330a6 3709 #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \
AnnaBridge 158:1c57384330a6 3710 (RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) | (uint32_t)((__PLLN__) << 8U) | (uint32_t)(((__PLLP__) >> 4U ) << 17U) | \
AnnaBridge 158:1c57384330a6 3711 (uint32_t)(__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U))
AnnaBridge 158:1c57384330a6 3712
AnnaBridge 158:1c57384330a6 3713 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */
AnnaBridge 158:1c57384330a6 3714
AnnaBridge 158:1c57384330a6 3715 /** @brief Macro to get the oscillator used as PLL clock source.
AnnaBridge 158:1c57384330a6 3716 * @retval The oscillator used as PLL clock source. The returned value can be one
AnnaBridge 158:1c57384330a6 3717 * of the following:
AnnaBridge 158:1c57384330a6 3718 * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source.
AnnaBridge 158:1c57384330a6 3719 * - RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source.
AnnaBridge 158:1c57384330a6 3720 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
AnnaBridge 158:1c57384330a6 3721 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
AnnaBridge 158:1c57384330a6 3722 */
AnnaBridge 158:1c57384330a6 3723 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
AnnaBridge 158:1c57384330a6 3724
AnnaBridge 158:1c57384330a6 3725 /**
AnnaBridge 158:1c57384330a6 3726 * @brief Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)
AnnaBridge 158:1c57384330a6 3727 * @note Enabling/disabling clock outputs RCC_PLL_SAI3CLK and RCC_PLL_48M1CLK can be done at anytime
AnnaBridge 158:1c57384330a6 3728 * without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot
AnnaBridge 158:1c57384330a6 3729 * be stopped if used as System Clock.
AnnaBridge 158:1c57384330a6 3730 * @param __PLLCLOCKOUT__: specifies the PLL clock to be output.
AnnaBridge 158:1c57384330a6 3731 * This parameter can be one or a combination of the following values:
AnnaBridge 158:1c57384330a6 3732 * @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve
AnnaBridge 158:1c57384330a6 3733 * high-quality audio performance on SAI interface in case.
AnnaBridge 158:1c57384330a6 3734 * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB OTG FS (48 MHz),
AnnaBridge 158:1c57384330a6 3735 * the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
AnnaBridge 158:1c57384330a6 3736 * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 80MHz)
AnnaBridge 158:1c57384330a6 3737 * @retval None
AnnaBridge 158:1c57384330a6 3738 */
AnnaBridge 158:1c57384330a6 3739 #define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
AnnaBridge 158:1c57384330a6 3740
AnnaBridge 158:1c57384330a6 3741 #define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
AnnaBridge 158:1c57384330a6 3742
AnnaBridge 158:1c57384330a6 3743 /**
AnnaBridge 158:1c57384330a6 3744 * @brief Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)
AnnaBridge 158:1c57384330a6 3745 * @param __PLLCLOCKOUT__: specifies the output PLL clock to be checked.
AnnaBridge 158:1c57384330a6 3746 * This parameter can be one of the following values:
AnnaBridge 158:1c57384330a6 3747 * @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve
AnnaBridge 158:1c57384330a6 3748 * high-quality audio performance on SAI interface in case.
AnnaBridge 158:1c57384330a6 3749 * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB OTG FS (48 MHz),
AnnaBridge 158:1c57384330a6 3750 * the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
AnnaBridge 158:1c57384330a6 3751 * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 80MHz)
AnnaBridge 158:1c57384330a6 3752 * @retval SET / RESET
AnnaBridge 158:1c57384330a6 3753 */
AnnaBridge 158:1c57384330a6 3754 #define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
AnnaBridge 158:1c57384330a6 3755
AnnaBridge 158:1c57384330a6 3756 /**
AnnaBridge 158:1c57384330a6 3757 * @brief Macro to configure the system clock source.
AnnaBridge 158:1c57384330a6 3758 * @param __SYSCLKSOURCE__: specifies the system clock source.
AnnaBridge 158:1c57384330a6 3759 * This parameter can be one of the following values:
AnnaBridge 158:1c57384330a6 3760 * - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source.
AnnaBridge 158:1c57384330a6 3761 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
AnnaBridge 158:1c57384330a6 3762 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
AnnaBridge 158:1c57384330a6 3763 * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
AnnaBridge 158:1c57384330a6 3764 * @retval None
AnnaBridge 158:1c57384330a6 3765 */
AnnaBridge 158:1c57384330a6 3766 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
AnnaBridge 158:1c57384330a6 3767 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
AnnaBridge 158:1c57384330a6 3768
AnnaBridge 158:1c57384330a6 3769 /** @brief Macro to get the clock source used as system clock.
AnnaBridge 158:1c57384330a6 3770 * @retval The clock source used as system clock. The returned value can be one
AnnaBridge 158:1c57384330a6 3771 * of the following:
AnnaBridge 158:1c57384330a6 3772 * - RCC_SYSCLKSOURCE_STATUS_MSI: MSI used as system clock.
AnnaBridge 158:1c57384330a6 3773 * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
AnnaBridge 158:1c57384330a6 3774 * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
AnnaBridge 158:1c57384330a6 3775 * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
AnnaBridge 158:1c57384330a6 3776 */
AnnaBridge 158:1c57384330a6 3777 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
AnnaBridge 158:1c57384330a6 3778
AnnaBridge 158:1c57384330a6 3779 /**
AnnaBridge 158:1c57384330a6 3780 * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability.
AnnaBridge 158:1c57384330a6 3781 * @note As the LSE is in the Backup domain and write access is denied to
AnnaBridge 158:1c57384330a6 3782 * this domain after reset, you have to enable write access using
AnnaBridge 158:1c57384330a6 3783 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
AnnaBridge 158:1c57384330a6 3784 * (to be done once after reset).
AnnaBridge 158:1c57384330a6 3785 * @param __LSEDRIVE__: specifies the new state of the LSE drive capability.
AnnaBridge 158:1c57384330a6 3786 * This parameter can be one of the following values:
AnnaBridge 158:1c57384330a6 3787 * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability.
AnnaBridge 158:1c57384330a6 3788 * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability.
AnnaBridge 158:1c57384330a6 3789 * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability.
AnnaBridge 158:1c57384330a6 3790 * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability.
AnnaBridge 158:1c57384330a6 3791 * @retval None
AnnaBridge 158:1c57384330a6 3792 */
AnnaBridge 158:1c57384330a6 3793 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \
AnnaBridge 158:1c57384330a6 3794 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__))
AnnaBridge 158:1c57384330a6 3795
AnnaBridge 158:1c57384330a6 3796 /**
AnnaBridge 158:1c57384330a6 3797 * @brief Macro to configure the wake up from stop clock.
AnnaBridge 158:1c57384330a6 3798 * @param __STOPWUCLK__: specifies the clock source used after wake up from stop.
AnnaBridge 158:1c57384330a6 3799 * This parameter can be one of the following values:
AnnaBridge 158:1c57384330a6 3800 * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source
AnnaBridge 158:1c57384330a6 3801 * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source
AnnaBridge 158:1c57384330a6 3802 * @retval None
AnnaBridge 158:1c57384330a6 3803 */
AnnaBridge 158:1c57384330a6 3804 #define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) \
AnnaBridge 158:1c57384330a6 3805 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__STOPWUCLK__))
AnnaBridge 158:1c57384330a6 3806
AnnaBridge 158:1c57384330a6 3807
AnnaBridge 158:1c57384330a6 3808 /** @brief Macro to configure the MCO clock.
AnnaBridge 158:1c57384330a6 3809 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
AnnaBridge 158:1c57384330a6 3810 * This parameter can be one of the following values:
AnnaBridge 158:1c57384330a6 3811 * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled
AnnaBridge 158:1c57384330a6 3812 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source
AnnaBridge 158:1c57384330a6 3813 * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source
AnnaBridge 158:1c57384330a6 3814 * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source
AnnaBridge 158:1c57384330a6 3815 * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee
AnnaBridge 158:1c57384330a6 3816 * @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source
AnnaBridge 158:1c57384330a6 3817 * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source
AnnaBridge 158:1c57384330a6 3818 * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source
AnnaBridge 158:1c57384330a6 3819 @if STM32L443xx
AnnaBridge 158:1c57384330a6 3820 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48
AnnaBridge 158:1c57384330a6 3821 @endif
AnnaBridge 158:1c57384330a6 3822 @if STM32L462xx
AnnaBridge 158:1c57384330a6 3823 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48
AnnaBridge 158:1c57384330a6 3824 @endif
AnnaBridge 158:1c57384330a6 3825 @if STM32L4A6xx
AnnaBridge 158:1c57384330a6 3826 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48
AnnaBridge 158:1c57384330a6 3827 @endif
AnnaBridge 158:1c57384330a6 3828 * @param __MCODIV__ specifies the MCO clock prescaler.
AnnaBridge 158:1c57384330a6 3829 * This parameter can be one of the following values:
AnnaBridge 158:1c57384330a6 3830 * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1
AnnaBridge 158:1c57384330a6 3831 * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2
AnnaBridge 158:1c57384330a6 3832 * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4
AnnaBridge 158:1c57384330a6 3833 * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8
AnnaBridge 158:1c57384330a6 3834 * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16
AnnaBridge 158:1c57384330a6 3835 */
AnnaBridge 158:1c57384330a6 3836 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
AnnaBridge 158:1c57384330a6 3837 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
AnnaBridge 158:1c57384330a6 3838
AnnaBridge 158:1c57384330a6 3839 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
AnnaBridge 158:1c57384330a6 3840 * @brief macros to manage the specified RCC Flags and interrupts.
AnnaBridge 158:1c57384330a6 3841 * @{
AnnaBridge 158:1c57384330a6 3842 */
AnnaBridge 158:1c57384330a6 3843
AnnaBridge 158:1c57384330a6 3844 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
AnnaBridge 158:1c57384330a6 3845 * the selected interrupts).
AnnaBridge 158:1c57384330a6 3846 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
AnnaBridge 158:1c57384330a6 3847 * This parameter can be any combination of the following values:
AnnaBridge 158:1c57384330a6 3848 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
AnnaBridge 158:1c57384330a6 3849 * @arg @ref RCC_IT_LSERDY LSE ready interrupt
AnnaBridge 158:1c57384330a6 3850 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt
AnnaBridge 158:1c57384330a6 3851 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
AnnaBridge 158:1c57384330a6 3852 * @arg @ref RCC_IT_HSERDY HSE ready interrupt
AnnaBridge 158:1c57384330a6 3853 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
AnnaBridge 158:1c57384330a6 3854 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt
AnnaBridge 158:1c57384330a6 3855 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2
AnnaBridge 158:1c57384330a6 3856 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
AnnaBridge 158:1c57384330a6 3857 @if STM32L443xx
AnnaBridge 158:1c57384330a6 3858 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
AnnaBridge 158:1c57384330a6 3859 @endif
AnnaBridge 158:1c57384330a6 3860 @if STM32L462xx
AnnaBridge 158:1c57384330a6 3861 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
AnnaBridge 158:1c57384330a6 3862 @endif
AnnaBridge 158:1c57384330a6 3863 @if STM32L4A6xx
AnnaBridge 158:1c57384330a6 3864 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
AnnaBridge 158:1c57384330a6 3865 @endif
AnnaBridge 158:1c57384330a6 3866 * @retval None
AnnaBridge 158:1c57384330a6 3867 */
AnnaBridge 158:1c57384330a6 3868 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
AnnaBridge 158:1c57384330a6 3869
AnnaBridge 158:1c57384330a6 3870 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
AnnaBridge 158:1c57384330a6 3871 * the selected interrupts).
AnnaBridge 158:1c57384330a6 3872 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
AnnaBridge 158:1c57384330a6 3873 * This parameter can be any combination of the following values:
AnnaBridge 158:1c57384330a6 3874 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
AnnaBridge 158:1c57384330a6 3875 * @arg @ref RCC_IT_LSERDY LSE ready interrupt
AnnaBridge 158:1c57384330a6 3876 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt
AnnaBridge 158:1c57384330a6 3877 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
AnnaBridge 158:1c57384330a6 3878 * @arg @ref RCC_IT_HSERDY HSE ready interrupt
AnnaBridge 158:1c57384330a6 3879 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
AnnaBridge 158:1c57384330a6 3880 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt
AnnaBridge 158:1c57384330a6 3881 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2
AnnaBridge 158:1c57384330a6 3882 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
AnnaBridge 158:1c57384330a6 3883 @if STM32L443xx
AnnaBridge 158:1c57384330a6 3884 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
AnnaBridge 158:1c57384330a6 3885 @endif
AnnaBridge 158:1c57384330a6 3886 @if STM32L462xx
AnnaBridge 158:1c57384330a6 3887 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
AnnaBridge 158:1c57384330a6 3888 @endif
AnnaBridge 158:1c57384330a6 3889 @if STM32L4A6xx
AnnaBridge 158:1c57384330a6 3890 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
AnnaBridge 158:1c57384330a6 3891 @endif
AnnaBridge 158:1c57384330a6 3892 * @retval None
AnnaBridge 158:1c57384330a6 3893 */
AnnaBridge 158:1c57384330a6 3894 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
AnnaBridge 158:1c57384330a6 3895
AnnaBridge 158:1c57384330a6 3896 /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
AnnaBridge 158:1c57384330a6 3897 * bits to clear the selected interrupt pending bits.
AnnaBridge 158:1c57384330a6 3898 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
AnnaBridge 158:1c57384330a6 3899 * This parameter can be any combination of the following values:
AnnaBridge 158:1c57384330a6 3900 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
AnnaBridge 158:1c57384330a6 3901 * @arg @ref RCC_IT_LSERDY LSE ready interrupt
AnnaBridge 158:1c57384330a6 3902 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt
AnnaBridge 158:1c57384330a6 3903 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
AnnaBridge 158:1c57384330a6 3904 * @arg @ref RCC_IT_HSERDY HSE ready interrupt
AnnaBridge 158:1c57384330a6 3905 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
AnnaBridge 158:1c57384330a6 3906 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt
AnnaBridge 158:1c57384330a6 3907 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2
AnnaBridge 158:1c57384330a6 3908 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt
AnnaBridge 158:1c57384330a6 3909 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
AnnaBridge 158:1c57384330a6 3910 @if STM32L443xx
AnnaBridge 158:1c57384330a6 3911 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
AnnaBridge 158:1c57384330a6 3912 @endif
AnnaBridge 158:1c57384330a6 3913 @if STM32L462xx
AnnaBridge 158:1c57384330a6 3914 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
AnnaBridge 158:1c57384330a6 3915 @endif
AnnaBridge 158:1c57384330a6 3916 @if STM32L4A6xx
AnnaBridge 158:1c57384330a6 3917 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
AnnaBridge 158:1c57384330a6 3918 @endif
AnnaBridge 158:1c57384330a6 3919 * @retval None
AnnaBridge 158:1c57384330a6 3920 */
AnnaBridge 158:1c57384330a6 3921 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
AnnaBridge 158:1c57384330a6 3922
AnnaBridge 158:1c57384330a6 3923 /** @brief Check whether the RCC interrupt has occurred or not.
AnnaBridge 158:1c57384330a6 3924 * @param __INTERRUPT__: specifies the RCC interrupt source to check.
AnnaBridge 158:1c57384330a6 3925 * This parameter can be one of the following values:
AnnaBridge 158:1c57384330a6 3926 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
AnnaBridge 158:1c57384330a6 3927 * @arg @ref RCC_IT_LSERDY LSE ready interrupt
AnnaBridge 158:1c57384330a6 3928 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt
AnnaBridge 158:1c57384330a6 3929 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
AnnaBridge 158:1c57384330a6 3930 * @arg @ref RCC_IT_HSERDY HSE ready interrupt
AnnaBridge 158:1c57384330a6 3931 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
AnnaBridge 158:1c57384330a6 3932 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt
AnnaBridge 158:1c57384330a6 3933 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2
AnnaBridge 158:1c57384330a6 3934 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt
AnnaBridge 158:1c57384330a6 3935 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
AnnaBridge 158:1c57384330a6 3936 @if STM32L443xx
AnnaBridge 158:1c57384330a6 3937 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
AnnaBridge 158:1c57384330a6 3938 @endif
AnnaBridge 158:1c57384330a6 3939 @if STM32L462xx
AnnaBridge 158:1c57384330a6 3940 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
AnnaBridge 158:1c57384330a6 3941 @endif
AnnaBridge 158:1c57384330a6 3942 @if STM32L4A6xx
AnnaBridge 158:1c57384330a6 3943 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
AnnaBridge 158:1c57384330a6 3944 @endif
AnnaBridge 158:1c57384330a6 3945 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
AnnaBridge 158:1c57384330a6 3946 */
AnnaBridge 158:1c57384330a6 3947 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
AnnaBridge 158:1c57384330a6 3948
AnnaBridge 158:1c57384330a6 3949 /** @brief Set RMVF bit to clear the reset flags.
AnnaBridge 158:1c57384330a6 3950 * The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST,
AnnaBridge 158:1c57384330a6 3951 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
AnnaBridge 158:1c57384330a6 3952 * @retval None
AnnaBridge 158:1c57384330a6 3953 */
AnnaBridge 158:1c57384330a6 3954 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
AnnaBridge 158:1c57384330a6 3955
AnnaBridge 158:1c57384330a6 3956 /** @brief Check whether the selected RCC flag is set or not.
AnnaBridge 158:1c57384330a6 3957 * @param __FLAG__: specifies the flag to check.
AnnaBridge 158:1c57384330a6 3958 * This parameter can be one of the following values:
AnnaBridge 158:1c57384330a6 3959 * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready
AnnaBridge 158:1c57384330a6 3960 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready
AnnaBridge 158:1c57384330a6 3961 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready
AnnaBridge 158:1c57384330a6 3962 * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready
AnnaBridge 158:1c57384330a6 3963 * @arg @ref RCC_FLAG_PLLSAI1RDY PLLSAI1 clock ready
AnnaBridge 158:1c57384330a6 3964 * @arg @ref RCC_FLAG_PLLSAI2RDY PLLSAI2 clock ready for devices with PLLSAI2
AnnaBridge 158:1c57384330a6 3965 @if STM32L443xx
AnnaBridge 158:1c57384330a6 3966 * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48
AnnaBridge 158:1c57384330a6 3967 @endif
AnnaBridge 158:1c57384330a6 3968 @if STM32L462xx
AnnaBridge 158:1c57384330a6 3969 * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48
AnnaBridge 158:1c57384330a6 3970 @endif
AnnaBridge 158:1c57384330a6 3971 @if STM32L4A6xx
AnnaBridge 158:1c57384330a6 3972 * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48
AnnaBridge 158:1c57384330a6 3973 @endif
AnnaBridge 158:1c57384330a6 3974 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready
AnnaBridge 158:1c57384330a6 3975 * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection
AnnaBridge 158:1c57384330a6 3976 * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready
AnnaBridge 158:1c57384330a6 3977 * @arg @ref RCC_FLAG_BORRST BOR reset
AnnaBridge 158:1c57384330a6 3978 * @arg @ref RCC_FLAG_OBLRST OBLRST reset
AnnaBridge 158:1c57384330a6 3979 * @arg @ref RCC_FLAG_PINRST Pin reset
AnnaBridge 158:1c57384330a6 3980 * @arg @ref RCC_FLAG_FWRST FIREWALL reset
AnnaBridge 158:1c57384330a6 3981 * @arg @ref RCC_FLAG_RMVF Remove reset Flag
AnnaBridge 158:1c57384330a6 3982 * @arg @ref RCC_FLAG_SFTRST Software reset
AnnaBridge 158:1c57384330a6 3983 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset
AnnaBridge 158:1c57384330a6 3984 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset
AnnaBridge 158:1c57384330a6 3985 * @arg @ref RCC_FLAG_LPWRRST Low Power reset
AnnaBridge 158:1c57384330a6 3986 * @retval The new state of __FLAG__ (TRUE or FALSE).
AnnaBridge 158:1c57384330a6 3987 */
AnnaBridge 158:1c57384330a6 3988 #if defined(RCC_HSI48_SUPPORT)
AnnaBridge 158:1c57384330a6 3989 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \
AnnaBridge 158:1c57384330a6 3990 ((((__FLAG__) >> 5U) == 4U) ? RCC->CRRCR : \
AnnaBridge 158:1c57384330a6 3991 ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
AnnaBridge 158:1c57384330a6 3992 ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \
AnnaBridge 158:1c57384330a6 3993 ((uint32_t)1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) \
AnnaBridge 158:1c57384330a6 3994 ? 1U : 0U)
AnnaBridge 158:1c57384330a6 3995 #else
AnnaBridge 158:1c57384330a6 3996 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \
AnnaBridge 158:1c57384330a6 3997 ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
AnnaBridge 158:1c57384330a6 3998 ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR))) & \
AnnaBridge 158:1c57384330a6 3999 ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) \
AnnaBridge 158:1c57384330a6 4000 ? 1U : 0U)
AnnaBridge 158:1c57384330a6 4001 #endif /* RCC_HSI48_SUPPORT */
AnnaBridge 158:1c57384330a6 4002
AnnaBridge 158:1c57384330a6 4003 /**
AnnaBridge 158:1c57384330a6 4004 * @}
AnnaBridge 158:1c57384330a6 4005 */
AnnaBridge 158:1c57384330a6 4006
AnnaBridge 158:1c57384330a6 4007 /**
AnnaBridge 158:1c57384330a6 4008 * @}
AnnaBridge 158:1c57384330a6 4009 */
AnnaBridge 158:1c57384330a6 4010
AnnaBridge 158:1c57384330a6 4011 /* Private constants ---------------------------------------------------------*/
AnnaBridge 158:1c57384330a6 4012 /** @defgroup RCC_Private_Constants RCC Private Constants
AnnaBridge 158:1c57384330a6 4013 * @{
AnnaBridge 158:1c57384330a6 4014 */
AnnaBridge 158:1c57384330a6 4015 /* Defines used for Flags */
AnnaBridge 158:1c57384330a6 4016 #define CR_REG_INDEX ((uint32_t)1U)
AnnaBridge 158:1c57384330a6 4017 #define BDCR_REG_INDEX ((uint32_t)2U)
AnnaBridge 158:1c57384330a6 4018 #define CSR_REG_INDEX ((uint32_t)3U)
AnnaBridge 158:1c57384330a6 4019 #if defined(RCC_HSI48_SUPPORT)
AnnaBridge 158:1c57384330a6 4020 #define CRRCR_REG_INDEX ((uint32_t)4U)
AnnaBridge 158:1c57384330a6 4021 #endif /* RCC_HSI48_SUPPORT */
AnnaBridge 158:1c57384330a6 4022
AnnaBridge 158:1c57384330a6 4023 #define RCC_FLAG_MASK ((uint32_t)0x1FU)
AnnaBridge 158:1c57384330a6 4024 /**
AnnaBridge 158:1c57384330a6 4025 * @}
AnnaBridge 158:1c57384330a6 4026 */
AnnaBridge 158:1c57384330a6 4027
AnnaBridge 158:1c57384330a6 4028 /* Private macros ------------------------------------------------------------*/
AnnaBridge 158:1c57384330a6 4029 /** @addtogroup RCC_Private_Macros
AnnaBridge 158:1c57384330a6 4030 * @{
AnnaBridge 158:1c57384330a6 4031 */
AnnaBridge 158:1c57384330a6 4032
AnnaBridge 158:1c57384330a6 4033 #if defined(RCC_HSI48_SUPPORT)
AnnaBridge 158:1c57384330a6 4034 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
AnnaBridge 158:1c57384330a6 4035 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
AnnaBridge 158:1c57384330a6 4036 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
AnnaBridge 158:1c57384330a6 4037 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \
AnnaBridge 158:1c57384330a6 4038 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \
AnnaBridge 158:1c57384330a6 4039 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
AnnaBridge 158:1c57384330a6 4040 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
AnnaBridge 158:1c57384330a6 4041 #else
AnnaBridge 158:1c57384330a6 4042 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
AnnaBridge 158:1c57384330a6 4043 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
AnnaBridge 158:1c57384330a6 4044 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
AnnaBridge 158:1c57384330a6 4045 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \
AnnaBridge 158:1c57384330a6 4046 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
AnnaBridge 158:1c57384330a6 4047 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
AnnaBridge 158:1c57384330a6 4048 #endif /* RCC_HSI48_SUPPORT */
AnnaBridge 158:1c57384330a6 4049
AnnaBridge 158:1c57384330a6 4050 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
AnnaBridge 158:1c57384330a6 4051 ((__HSE__) == RCC_HSE_BYPASS))
AnnaBridge 158:1c57384330a6 4052
AnnaBridge 158:1c57384330a6 4053 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
AnnaBridge 158:1c57384330a6 4054 ((__LSE__) == RCC_LSE_BYPASS))
AnnaBridge 158:1c57384330a6 4055
AnnaBridge 158:1c57384330a6 4056 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
AnnaBridge 158:1c57384330a6 4057
AnnaBridge 158:1c57384330a6 4058 #define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)( RCC_ICSCR_HSITRIM >> POSITION_VAL(RCC_ICSCR_HSITRIM)))
AnnaBridge 158:1c57384330a6 4059
AnnaBridge 158:1c57384330a6 4060 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
AnnaBridge 158:1c57384330a6 4061
AnnaBridge 158:1c57384330a6 4062 #define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON))
AnnaBridge 158:1c57384330a6 4063
AnnaBridge 158:1c57384330a6 4064 #define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)255U)
AnnaBridge 158:1c57384330a6 4065
AnnaBridge 158:1c57384330a6 4066 #if defined(RCC_HSI48_SUPPORT)
AnnaBridge 158:1c57384330a6 4067 #define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON))
AnnaBridge 158:1c57384330a6 4068 #endif /* RCC_HSI48_SUPPORT */
AnnaBridge 158:1c57384330a6 4069
AnnaBridge 158:1c57384330a6 4070 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \
AnnaBridge 158:1c57384330a6 4071 ((__PLL__) == RCC_PLL_ON))
AnnaBridge 158:1c57384330a6 4072
AnnaBridge 158:1c57384330a6 4073 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) || \
AnnaBridge 158:1c57384330a6 4074 ((__SOURCE__) == RCC_PLLSOURCE_MSI) || \
AnnaBridge 158:1c57384330a6 4075 ((__SOURCE__) == RCC_PLLSOURCE_HSI) || \
AnnaBridge 158:1c57384330a6 4076 ((__SOURCE__) == RCC_PLLSOURCE_HSE))
AnnaBridge 158:1c57384330a6 4077
AnnaBridge 158:1c57384330a6 4078 #define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))
AnnaBridge 158:1c57384330a6 4079
AnnaBridge 158:1c57384330a6 4080 #define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
AnnaBridge 158:1c57384330a6 4081
AnnaBridge 158:1c57384330a6 4082 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
AnnaBridge 158:1c57384330a6 4083 #define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))
AnnaBridge 158:1c57384330a6 4084 #else
AnnaBridge 158:1c57384330a6 4085 #define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U))
AnnaBridge 158:1c57384330a6 4086 #endif /*RCC_PLLP_DIV_2_31_SUPPORT */
AnnaBridge 158:1c57384330a6 4087
AnnaBridge 158:1c57384330a6 4088 #define IS_RCC_PLLQ_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
AnnaBridge 158:1c57384330a6 4089 ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
AnnaBridge 158:1c57384330a6 4090
AnnaBridge 158:1c57384330a6 4091 #define IS_RCC_PLLR_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
AnnaBridge 158:1c57384330a6 4092 ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
AnnaBridge 158:1c57384330a6 4093
AnnaBridge 158:1c57384330a6 4094 #define IS_RCC_PLLSAI1CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI1_SAI1CLK) == RCC_PLLSAI1_SAI1CLK) || \
AnnaBridge 158:1c57384330a6 4095 (((__VALUE__) & RCC_PLLSAI1_48M2CLK) == RCC_PLLSAI1_48M2CLK) || \
AnnaBridge 158:1c57384330a6 4096 (((__VALUE__) & RCC_PLLSAI1_ADC1CLK) == RCC_PLLSAI1_ADC1CLK)) && \
AnnaBridge 158:1c57384330a6 4097 (((__VALUE__) & ~(RCC_PLLSAI1_SAI1CLK|RCC_PLLSAI1_48M2CLK|RCC_PLLSAI1_ADC1CLK)) == 0U))
AnnaBridge 158:1c57384330a6 4098
AnnaBridge 158:1c57384330a6 4099 #if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge 158:1c57384330a6 4100 #define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK) || \
AnnaBridge 158:1c57384330a6 4101 (((__VALUE__) & RCC_PLLSAI2_ADC2CLK) == RCC_PLLSAI2_ADC2CLK)) && \
AnnaBridge 158:1c57384330a6 4102 (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK|RCC_PLLSAI2_ADC2CLK)) == 0U))
AnnaBridge 158:1c57384330a6 4103 #endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge 158:1c57384330a6 4104
AnnaBridge 158:1c57384330a6 4105 #define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \
AnnaBridge 158:1c57384330a6 4106 ((__RANGE__) == RCC_MSIRANGE_1) || \
AnnaBridge 158:1c57384330a6 4107 ((__RANGE__) == RCC_MSIRANGE_2) || \
AnnaBridge 158:1c57384330a6 4108 ((__RANGE__) == RCC_MSIRANGE_3) || \
AnnaBridge 158:1c57384330a6 4109 ((__RANGE__) == RCC_MSIRANGE_4) || \
AnnaBridge 158:1c57384330a6 4110 ((__RANGE__) == RCC_MSIRANGE_5) || \
AnnaBridge 158:1c57384330a6 4111 ((__RANGE__) == RCC_MSIRANGE_6) || \
AnnaBridge 158:1c57384330a6 4112 ((__RANGE__) == RCC_MSIRANGE_7) || \
AnnaBridge 158:1c57384330a6 4113 ((__RANGE__) == RCC_MSIRANGE_8) || \
AnnaBridge 158:1c57384330a6 4114 ((__RANGE__) == RCC_MSIRANGE_9) || \
AnnaBridge 158:1c57384330a6 4115 ((__RANGE__) == RCC_MSIRANGE_10) || \
AnnaBridge 158:1c57384330a6 4116 ((__RANGE__) == RCC_MSIRANGE_11))
AnnaBridge 158:1c57384330a6 4117
AnnaBridge 158:1c57384330a6 4118 #define IS_RCC_MSI_STANDBY_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_4) || \
AnnaBridge 158:1c57384330a6 4119 ((__RANGE__) == RCC_MSIRANGE_5) || \
AnnaBridge 158:1c57384330a6 4120 ((__RANGE__) == RCC_MSIRANGE_6) || \
AnnaBridge 158:1c57384330a6 4121 ((__RANGE__) == RCC_MSIRANGE_7))
AnnaBridge 158:1c57384330a6 4122
AnnaBridge 158:1c57384330a6 4123 #define IS_RCC_CLOCKTYPE(__CLK__) ((1U <= (__CLK__)) && ((__CLK__) <= 15U))
AnnaBridge 158:1c57384330a6 4124
AnnaBridge 158:1c57384330a6 4125 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \
AnnaBridge 158:1c57384330a6 4126 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
AnnaBridge 158:1c57384330a6 4127 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
AnnaBridge 158:1c57384330a6 4128 ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
AnnaBridge 158:1c57384330a6 4129
AnnaBridge 158:1c57384330a6 4130 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
AnnaBridge 158:1c57384330a6 4131 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
AnnaBridge 158:1c57384330a6 4132 ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
AnnaBridge 158:1c57384330a6 4133 ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
AnnaBridge 158:1c57384330a6 4134 ((__HCLK__) == RCC_SYSCLK_DIV512))
AnnaBridge 158:1c57384330a6 4135
AnnaBridge 158:1c57384330a6 4136 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
AnnaBridge 158:1c57384330a6 4137 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
AnnaBridge 158:1c57384330a6 4138 ((__PCLK__) == RCC_HCLK_DIV16))
AnnaBridge 158:1c57384330a6 4139
AnnaBridge 158:1c57384330a6 4140 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \
AnnaBridge 158:1c57384330a6 4141 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
AnnaBridge 158:1c57384330a6 4142 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
AnnaBridge 158:1c57384330a6 4143 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
AnnaBridge 158:1c57384330a6 4144
AnnaBridge 158:1c57384330a6 4145 #define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1)
AnnaBridge 158:1c57384330a6 4146
AnnaBridge 158:1c57384330a6 4147 #if defined(RCC_HSI48_SUPPORT)
AnnaBridge 158:1c57384330a6 4148 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \
AnnaBridge 158:1c57384330a6 4149 ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
AnnaBridge 158:1c57384330a6 4150 ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \
AnnaBridge 158:1c57384330a6 4151 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \
AnnaBridge 158:1c57384330a6 4152 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \
AnnaBridge 158:1c57384330a6 4153 ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
AnnaBridge 158:1c57384330a6 4154 ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \
AnnaBridge 158:1c57384330a6 4155 ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \
AnnaBridge 158:1c57384330a6 4156 ((__SOURCE__) == RCC_MCO1SOURCE_HSI48))
AnnaBridge 158:1c57384330a6 4157 #else
AnnaBridge 158:1c57384330a6 4158 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \
AnnaBridge 158:1c57384330a6 4159 ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
AnnaBridge 158:1c57384330a6 4160 ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \
AnnaBridge 158:1c57384330a6 4161 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \
AnnaBridge 158:1c57384330a6 4162 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \
AnnaBridge 158:1c57384330a6 4163 ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
AnnaBridge 158:1c57384330a6 4164 ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \
AnnaBridge 158:1c57384330a6 4165 ((__SOURCE__) == RCC_MCO1SOURCE_LSE))
AnnaBridge 158:1c57384330a6 4166 #endif /* RCC_HSI48_SUPPORT */
AnnaBridge 158:1c57384330a6 4167
AnnaBridge 158:1c57384330a6 4168 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \
AnnaBridge 158:1c57384330a6 4169 ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \
AnnaBridge 158:1c57384330a6 4170 ((__DIV__) == RCC_MCODIV_16))
AnnaBridge 158:1c57384330a6 4171
AnnaBridge 158:1c57384330a6 4172 #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \
AnnaBridge 158:1c57384330a6 4173 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \
AnnaBridge 158:1c57384330a6 4174 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \
AnnaBridge 158:1c57384330a6 4175 ((__DRIVE__) == RCC_LSEDRIVE_HIGH))
AnnaBridge 158:1c57384330a6 4176
AnnaBridge 158:1c57384330a6 4177 #define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) || \
AnnaBridge 158:1c57384330a6 4178 ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI))
AnnaBridge 158:1c57384330a6 4179 /**
AnnaBridge 158:1c57384330a6 4180 * @}
AnnaBridge 158:1c57384330a6 4181 */
AnnaBridge 158:1c57384330a6 4182
AnnaBridge 158:1c57384330a6 4183 /* Include RCC HAL Extended module */
AnnaBridge 158:1c57384330a6 4184 #include "stm32l4xx_hal_rcc_ex.h"
AnnaBridge 158:1c57384330a6 4185
AnnaBridge 158:1c57384330a6 4186 /* Exported functions --------------------------------------------------------*/
AnnaBridge 158:1c57384330a6 4187 /** @addtogroup RCC_Exported_Functions
AnnaBridge 158:1c57384330a6 4188 * @{
AnnaBridge 158:1c57384330a6 4189 */
AnnaBridge 158:1c57384330a6 4190
AnnaBridge 158:1c57384330a6 4191
AnnaBridge 158:1c57384330a6 4192 /** @addtogroup RCC_Exported_Functions_Group1
AnnaBridge 158:1c57384330a6 4193 * @{
AnnaBridge 158:1c57384330a6 4194 */
AnnaBridge 158:1c57384330a6 4195
AnnaBridge 158:1c57384330a6 4196 /* Initialization and de-initialization functions ******************************/
AnnaBridge 158:1c57384330a6 4197 void HAL_RCC_DeInit(void);
AnnaBridge 158:1c57384330a6 4198 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
AnnaBridge 158:1c57384330a6 4199 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
AnnaBridge 158:1c57384330a6 4200
AnnaBridge 158:1c57384330a6 4201 /**
AnnaBridge 158:1c57384330a6 4202 * @}
AnnaBridge 158:1c57384330a6 4203 */
AnnaBridge 158:1c57384330a6 4204
AnnaBridge 158:1c57384330a6 4205 /** @addtogroup RCC_Exported_Functions_Group2
AnnaBridge 158:1c57384330a6 4206 * @{
AnnaBridge 158:1c57384330a6 4207 */
AnnaBridge 158:1c57384330a6 4208
AnnaBridge 158:1c57384330a6 4209 /* Peripheral Control functions ************************************************/
AnnaBridge 158:1c57384330a6 4210 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
AnnaBridge 158:1c57384330a6 4211 void HAL_RCC_EnableCSS(void);
AnnaBridge 158:1c57384330a6 4212 uint32_t HAL_RCC_GetSysClockFreq(void);
AnnaBridge 158:1c57384330a6 4213 uint32_t HAL_RCC_GetHCLKFreq(void);
AnnaBridge 158:1c57384330a6 4214 uint32_t HAL_RCC_GetPCLK1Freq(void);
AnnaBridge 158:1c57384330a6 4215 uint32_t HAL_RCC_GetPCLK2Freq(void);
AnnaBridge 158:1c57384330a6 4216 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
AnnaBridge 158:1c57384330a6 4217 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
AnnaBridge 158:1c57384330a6 4218 /* CSS NMI IRQ handler */
AnnaBridge 158:1c57384330a6 4219 void HAL_RCC_NMI_IRQHandler(void);
AnnaBridge 158:1c57384330a6 4220 /* User Callbacks in non blocking mode (IT mode) */
AnnaBridge 158:1c57384330a6 4221 void HAL_RCC_CSSCallback(void);
AnnaBridge 158:1c57384330a6 4222
AnnaBridge 158:1c57384330a6 4223 /**
AnnaBridge 158:1c57384330a6 4224 * @}
AnnaBridge 158:1c57384330a6 4225 */
AnnaBridge 158:1c57384330a6 4226
AnnaBridge 158:1c57384330a6 4227 /**
AnnaBridge 158:1c57384330a6 4228 * @}
AnnaBridge 158:1c57384330a6 4229 */
AnnaBridge 158:1c57384330a6 4230
AnnaBridge 158:1c57384330a6 4231 /**
AnnaBridge 158:1c57384330a6 4232 * @}
AnnaBridge 158:1c57384330a6 4233 */
AnnaBridge 158:1c57384330a6 4234
AnnaBridge 158:1c57384330a6 4235 /**
AnnaBridge 158:1c57384330a6 4236 * @}
AnnaBridge 158:1c57384330a6 4237 */
AnnaBridge 158:1c57384330a6 4238
AnnaBridge 158:1c57384330a6 4239 #ifdef __cplusplus
AnnaBridge 158:1c57384330a6 4240 }
AnnaBridge 158:1c57384330a6 4241 #endif
AnnaBridge 158:1c57384330a6 4242
AnnaBridge 158:1c57384330a6 4243 #endif /* __STM32L4xx_HAL_RCC_H */
AnnaBridge 158:1c57384330a6 4244
AnnaBridge 158:1c57384330a6 4245 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/