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Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

TARGET_NUCLEO_L432KC/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L432KC/device/stm32l432xx.h@129:0ab6a29f35bf, 2016-11-08 (annotated)

Committer:
<>
Date:
Tue Nov 08 17:28:34 2016 +0000
Revision:
129:0ab6a29f35bf
Parent:
128:9bcdf88f62b0 
Release 129 of the mbed library



Ports for Upcoming Targets



3011: Add u-blox Sara-N target. https://github.com/ARMmbed/mbed-os/pull/3011

3099: MAX32625 https://github.com/ARMmbed/mbed-os/pull/3099

3151: Add support for FRDM-K82F https://github.com/ARMmbed/mbed-os/pull/3151

3177: New mcu k22512 fixing pr 3136 https://github.com/ARMmbed/mbed-os/pull/3177



Fixes and Changes



3008: NUCLEO_F072RB: Fix wrong timer channel number on pwm PB_5 pin https://github.com/ARMmbed/mbed-os/pull/3008

3013: STM32xx - Change how the ADC internal pins are checked before pinmap_ https://github.com/ARMmbed/mbed-os/pull/3013

3041: [nRF5] - added implementation of API of serial port flow control configuration. https://github.com/ARMmbed/mbed-os/pull/3041

3084: [nrf5] fix in Digital I/O : a gpioe pin was uninitialized badly https://github.com/ARMmbed/mbed-os/pull/3084

3009: TRNG enabled. TRNG APIs implemented. REV A/B/C/D flags removed. Warnings removed https://github.com/ARMmbed/mbed-os/pull/3009

3074: Target stm init gcc alignement https://github.com/ARMmbed/mbed-os/pull/3074

2988: Update of can_api.c fixing #2987 https://github.com/ARMmbed/mbed-os/pull/2988

3173: [Exporters] Add a device_name to microbit entry in targets.json https://github.com/ARMmbed/mbed-os/pull/3173

2969: [nRF52] - switch irq priorities of driver handlers to the lowest level https://github.com/ARMmbed/mbed-os/pull/2969

3184: #3183 Compiler warning in trng_api.c with K64F  https://github.com/ARMmbed/mbed-os/pull/3184

3104: [NuMaker] Support CAN and fix PWM CLK error https://github.com/ARMmbed/mbed-os/pull/3104

3186: MultiTech mDot - add back SPI3 pins https://github.com/ARMmbed/mbed-os/pull/3186

3075: nsapi - Add standardized return types for size and errors https://github.com/ARMmbed/mbed-os/pull/3075

3221: u-blox odin w2 drivers update https://github.com/ARMmbed/mbed-os/pull/3221

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 122:f9eeca106725 1 /**
Kojto 122:f9eeca106725 2 ******************************************************************************
Kojto 122:f9eeca106725 3 * @file stm32l432xx.h
Kojto 122:f9eeca106725 4 * @author MCD Application Team
Kojto 122:f9eeca106725 5 * @version V1.1.1
Kojto 122:f9eeca106725 6 * @date 29-April-2016
Kojto 122:f9eeca106725 7 * @brief CMSIS STM32L432xx Device Peripheral Access Layer Header File.
Kojto 122:f9eeca106725 8 *
Kojto 122:f9eeca106725 9 * This file contains:
Kojto 122:f9eeca106725 10 * - Data structures and the address mapping for all peripherals
Kojto 122:f9eeca106725 11 * - Peripheral's registers declarations and bits definition
Kojto 122:f9eeca106725 12 * - Macros to access peripheral�s registers hardware
Kojto 122:f9eeca106725 13 *
Kojto 122:f9eeca106725 14 ******************************************************************************
Kojto 122:f9eeca106725 15 * @attention
Kojto 122:f9eeca106725 16 *
Kojto 122:f9eeca106725 17 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
Kojto 122:f9eeca106725 18 *
Kojto 122:f9eeca106725 19 * Redistribution and use in source and binary forms, with or without modification,
Kojto 122:f9eeca106725 20 * are permitted provided that the following conditions are met:
Kojto 122:f9eeca106725 21 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 122:f9eeca106725 22 * this list of conditions and the following disclaimer.
Kojto 122:f9eeca106725 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 122:f9eeca106725 24 * this list of conditions and the following disclaimer in the documentation
Kojto 122:f9eeca106725 25 * and/or other materials provided with the distribution.
Kojto 122:f9eeca106725 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 122:f9eeca106725 27 * may be used to endorse or promote products derived from this software
Kojto 122:f9eeca106725 28 * without specific prior written permission.
Kojto 122:f9eeca106725 29 *
Kojto 122:f9eeca106725 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 122:f9eeca106725 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 122:f9eeca106725 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 122:f9eeca106725 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 122:f9eeca106725 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 122:f9eeca106725 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 122:f9eeca106725 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 122:f9eeca106725 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 122:f9eeca106725 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 122:f9eeca106725 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 122:f9eeca106725 40 *
Kojto 122:f9eeca106725 41 ******************************************************************************
Kojto 122:f9eeca106725 42 */
Kojto 122:f9eeca106725 43
Kojto 122:f9eeca106725 44 /** @addtogroup CMSIS_Device
Kojto 122:f9eeca106725 45 * @{
Kojto 122:f9eeca106725 46 */
Kojto 122:f9eeca106725 47
Kojto 122:f9eeca106725 48 /** @addtogroup stm32l432xx
Kojto 122:f9eeca106725 49 * @{
Kojto 122:f9eeca106725 50 */
Kojto 122:f9eeca106725 51
Kojto 122:f9eeca106725 52 #ifndef __STM32L432xx_H
Kojto 122:f9eeca106725 53 #define __STM32L432xx_H
Kojto 122:f9eeca106725 54
Kojto 122:f9eeca106725 55 #ifdef __cplusplus
Kojto 122:f9eeca106725 56 extern "C" {
Kojto 122:f9eeca106725 57 #endif /* __cplusplus */
Kojto 122:f9eeca106725 58
Kojto 122:f9eeca106725 59 /** @addtogroup Configuration_section_for_CMSIS
Kojto 122:f9eeca106725 60 * @{
Kojto 122:f9eeca106725 61 */
Kojto 122:f9eeca106725 62
Kojto 122:f9eeca106725 63 /**
Kojto 122:f9eeca106725 64 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
Kojto 122:f9eeca106725 65 */
Kojto 122:f9eeca106725 66 #define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
Kojto 122:f9eeca106725 67 #define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
Kojto 122:f9eeca106725 68 #define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
Kojto 122:f9eeca106725 69 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
Kojto 122:f9eeca106725 70 #define __FPU_PRESENT 1 /*!< FPU present */
Kojto 122:f9eeca106725 71
Kojto 122:f9eeca106725 72 /**
Kojto 122:f9eeca106725 73 * @}
Kojto 122:f9eeca106725 74 */
Kojto 122:f9eeca106725 75
Kojto 122:f9eeca106725 76 /** @addtogroup Peripheral_interrupt_number_definition
Kojto 122:f9eeca106725 77 * @{
Kojto 122:f9eeca106725 78 */
Kojto 122:f9eeca106725 79
Kojto 122:f9eeca106725 80 /**
Kojto 122:f9eeca106725 81 * @brief STM32L4XX Interrupt Number Definition, according to the selected device
Kojto 122:f9eeca106725 82 * in @ref Library_configuration_section
Kojto 122:f9eeca106725 83 */
Kojto 122:f9eeca106725 84 typedef enum
Kojto 122:f9eeca106725 85 {
Kojto 122:f9eeca106725 86 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
Kojto 122:f9eeca106725 87 NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
Kojto 122:f9eeca106725 88 HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
Kojto 122:f9eeca106725 89 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
Kojto 122:f9eeca106725 90 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
Kojto 122:f9eeca106725 91 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
Kojto 122:f9eeca106725 92 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
Kojto 122:f9eeca106725 93 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
Kojto 122:f9eeca106725 94 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
Kojto 122:f9eeca106725 95 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
Kojto 122:f9eeca106725 96 /****** STM32 specific Interrupt Numbers **********************************************************************/
Kojto 122:f9eeca106725 97 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
Kojto 122:f9eeca106725 98 PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */
Kojto 122:f9eeca106725 99 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
Kojto 122:f9eeca106725 100 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
Kojto 122:f9eeca106725 101 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
Kojto 122:f9eeca106725 102 RCC_IRQn = 5, /*!< RCC global Interrupt */
Kojto 122:f9eeca106725 103 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
Kojto 122:f9eeca106725 104 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
Kojto 122:f9eeca106725 105 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
Kojto 122:f9eeca106725 106 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
Kojto 122:f9eeca106725 107 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
Kojto 122:f9eeca106725 108 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
Kojto 122:f9eeca106725 109 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
Kojto 122:f9eeca106725 110 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
Kojto 122:f9eeca106725 111 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
Kojto 122:f9eeca106725 112 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
Kojto 122:f9eeca106725 113 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
Kojto 122:f9eeca106725 114 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
Kojto 122:f9eeca106725 115 ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
Kojto 122:f9eeca106725 116 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
Kojto 122:f9eeca106725 117 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
Kojto 122:f9eeca106725 118 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
Kojto 122:f9eeca106725 119 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
Kojto 122:f9eeca106725 120 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
Kojto 122:f9eeca106725 121 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break interrupt and TIM15 global interrupt */
Kojto 122:f9eeca106725 122 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */
Kojto 122:f9eeca106725 123 TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
Kojto 122:f9eeca106725 124 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
Kojto 122:f9eeca106725 125 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
Kojto 122:f9eeca106725 126 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
Kojto 122:f9eeca106725 127 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
Kojto 122:f9eeca106725 128 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
Kojto 122:f9eeca106725 129 USART1_IRQn = 37, /*!< USART1 global Interrupt */
Kojto 122:f9eeca106725 130 USART2_IRQn = 38, /*!< USART2 global Interrupt */
Kojto 122:f9eeca106725 131 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
Kojto 122:f9eeca106725 132 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
Kojto 122:f9eeca106725 133 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
Kojto 122:f9eeca106725 134 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
Kojto 122:f9eeca106725 135 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
Kojto 122:f9eeca106725 136 DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
Kojto 122:f9eeca106725 137 DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
Kojto 122:f9eeca106725 138 DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
Kojto 122:f9eeca106725 139 DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
Kojto 122:f9eeca106725 140 DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
Kojto 122:f9eeca106725 141 COMP_IRQn = 64, /*!< COMP1 and COMP2 Interrupts */
Kojto 122:f9eeca106725 142 LPTIM1_IRQn = 65, /*!< LP TIM1 interrupt */
Kojto 122:f9eeca106725 143 LPTIM2_IRQn = 66, /*!< LP TIM2 interrupt */
Kojto 122:f9eeca106725 144 USB_IRQn = 67, /*!< USB event Interrupt */
Kojto 122:f9eeca106725 145 DMA2_Channel6_IRQn = 68, /*!< DMA2 Channel 6 global interrupt */
Kojto 122:f9eeca106725 146 DMA2_Channel7_IRQn = 69, /*!< DMA2 Channel 7 global interrupt */
Kojto 122:f9eeca106725 147 LPUART1_IRQn = 70, /*!< LP UART1 interrupt */
Kojto 122:f9eeca106725 148 QUADSPI_IRQn = 71, /*!< Quad SPI global interrupt */
Kojto 122:f9eeca106725 149 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
Kojto 122:f9eeca106725 150 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
Kojto 122:f9eeca106725 151 SAI1_IRQn = 74, /*!< Serial Audio Interface 1 global interrupt */
Kojto 122:f9eeca106725 152 SWPMI1_IRQn = 76, /*!< Serial Wire Interface 1 global interrupt */
Kojto 122:f9eeca106725 153 TSC_IRQn = 77, /*!< Touch Sense Controller global interrupt */
Kojto 122:f9eeca106725 154 RNG_IRQn = 80, /*!< RNG global interrupt */
Kojto 122:f9eeca106725 155 FPU_IRQn = 81, /*!< FPU global interrupt */
Kojto 122:f9eeca106725 156 CRS_IRQn = 82 /*!< CRS global interrupt */
Kojto 122:f9eeca106725 157 } IRQn_Type;
Kojto 122:f9eeca106725 158
Kojto 122:f9eeca106725 159 /**
Kojto 122:f9eeca106725 160 * @}
Kojto 122:f9eeca106725 161 */
Kojto 122:f9eeca106725 162
Kojto 122:f9eeca106725 163 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
Kojto 122:f9eeca106725 164 #include "system_stm32l4xx.h"
Kojto 122:f9eeca106725 165 #include <stdint.h>
Kojto 122:f9eeca106725 166
Kojto 122:f9eeca106725 167 /** @addtogroup Peripheral_registers_structures
Kojto 122:f9eeca106725 168 * @{
Kojto 122:f9eeca106725 169 */
Kojto 122:f9eeca106725 170
Kojto 122:f9eeca106725 171 /**
Kojto 122:f9eeca106725 172 * @brief Analog to Digital Converter
Kojto 122:f9eeca106725 173 */
Kojto 122:f9eeca106725 174
Kojto 122:f9eeca106725 175 typedef struct
Kojto 122:f9eeca106725 176 {
Kojto 122:f9eeca106725 177 __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */
Kojto 122:f9eeca106725 178 __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */
Kojto 122:f9eeca106725 179 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
Kojto 122:f9eeca106725 180 __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */
Kojto 122:f9eeca106725 181 __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */
Kojto 122:f9eeca106725 182 __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */
Kojto 122:f9eeca106725 183 __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */
Kojto 122:f9eeca106725 184 uint32_t RESERVED1; /*!< Reserved, 0x1C */
Kojto 122:f9eeca106725 185 __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
Kojto 122:f9eeca106725 186 __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */
Kojto 122:f9eeca106725 187 __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */
Kojto 122:f9eeca106725 188 uint32_t RESERVED2; /*!< Reserved, 0x2C */
Kojto 122:f9eeca106725 189 __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */
Kojto 122:f9eeca106725 190 __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */
Kojto 122:f9eeca106725 191 __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */
Kojto 122:f9eeca106725 192 __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */
Kojto 122:f9eeca106725 193 __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */
Kojto 122:f9eeca106725 194 uint32_t RESERVED3; /*!< Reserved, 0x44 */
Kojto 122:f9eeca106725 195 uint32_t RESERVED4; /*!< Reserved, 0x48 */
Kojto 122:f9eeca106725 196 __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */
Kojto 122:f9eeca106725 197 uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */
Kojto 122:f9eeca106725 198 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
Kojto 122:f9eeca106725 199 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
Kojto 122:f9eeca106725 200 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
Kojto 122:f9eeca106725 201 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
Kojto 122:f9eeca106725 202 uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */
Kojto 122:f9eeca106725 203 __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */
Kojto 122:f9eeca106725 204 __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */
Kojto 122:f9eeca106725 205 __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */
Kojto 122:f9eeca106725 206 __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */
Kojto 122:f9eeca106725 207 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
Kojto 122:f9eeca106725 208 __IO uint32_t AWD2CR; /*!< ADC analog watchdog 1 configuration register, Address offset: 0xA0 */
Kojto 122:f9eeca106725 209 __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */
Kojto 122:f9eeca106725 210 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
Kojto 122:f9eeca106725 211 uint32_t RESERVED9; /*!< Reserved, 0x0AC */
Kojto 122:f9eeca106725 212 __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */
Kojto 122:f9eeca106725 213 __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */
Kojto 122:f9eeca106725 214
Kojto 122:f9eeca106725 215 } ADC_TypeDef;
Kojto 122:f9eeca106725 216
Kojto 122:f9eeca106725 217 typedef struct
Kojto 122:f9eeca106725 218 {
Kojto 122:f9eeca106725 219 uint32_t RESERVED1; /*!< Reserved, Address offset: ADC1 base address + 0x300 */
Kojto 122:f9eeca106725 220 uint32_t RESERVED2; /*!< Reserved, Address offset: ADC1 base address + 0x304 */
Kojto 122:f9eeca106725 221 __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */
Kojto 122:f9eeca106725 222 uint32_t RESERVED3; /*!< Reserved, Address offset: ADC1 base address + 0x30C */
Kojto 122:f9eeca106725 223 } ADC_Common_TypeDef;
Kojto 122:f9eeca106725 224
Kojto 122:f9eeca106725 225
Kojto 122:f9eeca106725 226 /**
Kojto 122:f9eeca106725 227 * @brief Controller Area Network TxMailBox
Kojto 122:f9eeca106725 228 */
Kojto 122:f9eeca106725 229
Kojto 122:f9eeca106725 230 typedef struct
Kojto 122:f9eeca106725 231 {
Kojto 122:f9eeca106725 232 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
Kojto 122:f9eeca106725 233 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
Kojto 122:f9eeca106725 234 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
Kojto 122:f9eeca106725 235 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
Kojto 122:f9eeca106725 236 } CAN_TxMailBox_TypeDef;
Kojto 122:f9eeca106725 237
Kojto 122:f9eeca106725 238 /**
Kojto 122:f9eeca106725 239 * @brief Controller Area Network FIFOMailBox
Kojto 122:f9eeca106725 240 */
Kojto 122:f9eeca106725 241
Kojto 122:f9eeca106725 242 typedef struct
Kojto 122:f9eeca106725 243 {
Kojto 122:f9eeca106725 244 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
Kojto 122:f9eeca106725 245 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
Kojto 122:f9eeca106725 246 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
Kojto 122:f9eeca106725 247 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
Kojto 122:f9eeca106725 248 } CAN_FIFOMailBox_TypeDef;
Kojto 122:f9eeca106725 249
Kojto 122:f9eeca106725 250 /**
Kojto 122:f9eeca106725 251 * @brief Controller Area Network FilterRegister
Kojto 122:f9eeca106725 252 */
Kojto 122:f9eeca106725 253
Kojto 122:f9eeca106725 254 typedef struct
Kojto 122:f9eeca106725 255 {
Kojto 122:f9eeca106725 256 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
Kojto 122:f9eeca106725 257 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
Kojto 122:f9eeca106725 258 } CAN_FilterRegister_TypeDef;
Kojto 122:f9eeca106725 259
Kojto 122:f9eeca106725 260 /**
Kojto 122:f9eeca106725 261 * @brief Controller Area Network
Kojto 122:f9eeca106725 262 */
Kojto 122:f9eeca106725 263
Kojto 122:f9eeca106725 264 typedef struct
Kojto 122:f9eeca106725 265 {
Kojto 122:f9eeca106725 266 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
Kojto 122:f9eeca106725 267 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
Kojto 122:f9eeca106725 268 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
Kojto 122:f9eeca106725 269 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
Kojto 122:f9eeca106725 270 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
Kojto 122:f9eeca106725 271 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
Kojto 122:f9eeca106725 272 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
Kojto 122:f9eeca106725 273 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
Kojto 122:f9eeca106725 274 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
Kojto 122:f9eeca106725 275 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
Kojto 122:f9eeca106725 276 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
Kojto 122:f9eeca106725 277 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
Kojto 122:f9eeca106725 278 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
Kojto 122:f9eeca106725 279 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
Kojto 122:f9eeca106725 280 uint32_t RESERVED2; /*!< Reserved, 0x208 */
Kojto 122:f9eeca106725 281 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
Kojto 122:f9eeca106725 282 uint32_t RESERVED3; /*!< Reserved, 0x210 */
Kojto 122:f9eeca106725 283 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
Kojto 122:f9eeca106725 284 uint32_t RESERVED4; /*!< Reserved, 0x218 */
Kojto 122:f9eeca106725 285 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
Kojto 122:f9eeca106725 286 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
Kojto 122:f9eeca106725 287 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
Kojto 122:f9eeca106725 288 } CAN_TypeDef;
Kojto 122:f9eeca106725 289
Kojto 122:f9eeca106725 290
Kojto 122:f9eeca106725 291 /**
Kojto 122:f9eeca106725 292 * @brief Comparator
Kojto 122:f9eeca106725 293 */
Kojto 122:f9eeca106725 294
Kojto 122:f9eeca106725 295 typedef struct
Kojto 122:f9eeca106725 296 {
Kojto 122:f9eeca106725 297 __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */
Kojto 122:f9eeca106725 298 } COMP_TypeDef;
Kojto 122:f9eeca106725 299
Kojto 122:f9eeca106725 300 typedef struct
Kojto 122:f9eeca106725 301 {
Kojto 122:f9eeca106725 302 __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
Kojto 122:f9eeca106725 303 } COMP_Common_TypeDef;
Kojto 122:f9eeca106725 304
Kojto 122:f9eeca106725 305 /**
Kojto 122:f9eeca106725 306 * @brief CRC calculation unit
Kojto 122:f9eeca106725 307 */
Kojto 122:f9eeca106725 308
Kojto 122:f9eeca106725 309 typedef struct
Kojto 122:f9eeca106725 310 {
Kojto 122:f9eeca106725 311 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
Kojto 122:f9eeca106725 312 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
Kojto 122:f9eeca106725 313 uint8_t RESERVED0; /*!< Reserved, 0x05 */
Kojto 122:f9eeca106725 314 uint16_t RESERVED1; /*!< Reserved, 0x06 */
Kojto 122:f9eeca106725 315 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
Kojto 122:f9eeca106725 316 uint32_t RESERVED2; /*!< Reserved, 0x0C */
Kojto 122:f9eeca106725 317 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
Kojto 122:f9eeca106725 318 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
Kojto 122:f9eeca106725 319 } CRC_TypeDef;
Kojto 122:f9eeca106725 320
Kojto 122:f9eeca106725 321 /**
Kojto 122:f9eeca106725 322 * @brief Clock Recovery System
Kojto 122:f9eeca106725 323 */
Kojto 122:f9eeca106725 324 typedef struct
Kojto 122:f9eeca106725 325 {
Kojto 122:f9eeca106725 326 __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
Kojto 122:f9eeca106725 327 __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
Kojto 122:f9eeca106725 328 __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
Kojto 122:f9eeca106725 329 __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
Kojto 122:f9eeca106725 330 } CRS_TypeDef;
Kojto 122:f9eeca106725 331
Kojto 122:f9eeca106725 332 /**
Kojto 122:f9eeca106725 333 * @brief Digital to Analog Converter
Kojto 122:f9eeca106725 334 */
Kojto 122:f9eeca106725 335
Kojto 122:f9eeca106725 336 typedef struct
Kojto 122:f9eeca106725 337 {
Kojto 122:f9eeca106725 338 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
Kojto 122:f9eeca106725 339 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
Kojto 122:f9eeca106725 340 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
Kojto 122:f9eeca106725 341 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
Kojto 122:f9eeca106725 342 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
Kojto 122:f9eeca106725 343 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
Kojto 122:f9eeca106725 344 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
Kojto 122:f9eeca106725 345 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
Kojto 122:f9eeca106725 346 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
Kojto 122:f9eeca106725 347 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
Kojto 122:f9eeca106725 348 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
Kojto 122:f9eeca106725 349 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
Kojto 122:f9eeca106725 350 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
Kojto 122:f9eeca106725 351 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
Kojto 122:f9eeca106725 352 __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
Kojto 122:f9eeca106725 353 __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
Kojto 122:f9eeca106725 354 __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
Kojto 122:f9eeca106725 355 __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
Kojto 122:f9eeca106725 356 __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
Kojto 122:f9eeca106725 357 __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
Kojto 122:f9eeca106725 358 } DAC_TypeDef;
Kojto 122:f9eeca106725 359
Kojto 122:f9eeca106725 360
Kojto 122:f9eeca106725 361 /**
Kojto 122:f9eeca106725 362 * @brief Debug MCU
Kojto 122:f9eeca106725 363 */
Kojto 122:f9eeca106725 364
Kojto 122:f9eeca106725 365 typedef struct
Kojto 122:f9eeca106725 366 {
Kojto 122:f9eeca106725 367 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
Kojto 122:f9eeca106725 368 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
Kojto 122:f9eeca106725 369 __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */
Kojto 122:f9eeca106725 370 __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */
Kojto 122:f9eeca106725 371 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */
Kojto 122:f9eeca106725 372 } DBGMCU_TypeDef;
Kojto 122:f9eeca106725 373
Kojto 122:f9eeca106725 374
Kojto 122:f9eeca106725 375 /**
Kojto 122:f9eeca106725 376 * @brief DMA Controller
Kojto 122:f9eeca106725 377 */
Kojto 122:f9eeca106725 378
Kojto 122:f9eeca106725 379 typedef struct
Kojto 122:f9eeca106725 380 {
Kojto 122:f9eeca106725 381 __IO uint32_t CCR; /*!< DMA channel x configuration register */
Kojto 122:f9eeca106725 382 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
Kojto 122:f9eeca106725 383 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
Kojto 122:f9eeca106725 384 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
Kojto 122:f9eeca106725 385 } DMA_Channel_TypeDef;
Kojto 122:f9eeca106725 386
Kojto 122:f9eeca106725 387 typedef struct
Kojto 122:f9eeca106725 388 {
Kojto 122:f9eeca106725 389 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
Kojto 122:f9eeca106725 390 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
Kojto 122:f9eeca106725 391 } DMA_TypeDef;
Kojto 122:f9eeca106725 392
Kojto 122:f9eeca106725 393 typedef struct
Kojto 122:f9eeca106725 394 {
Kojto 122:f9eeca106725 395 __IO uint32_t CSELR; /*!< DMA channel selection register */
Kojto 122:f9eeca106725 396 } DMA_Request_TypeDef;
Kojto 122:f9eeca106725 397
Kojto 122:f9eeca106725 398 /* Legacy define */
Kojto 122:f9eeca106725 399 #define DMA_request_TypeDef DMA_Request_TypeDef
Kojto 122:f9eeca106725 400
Kojto 122:f9eeca106725 401
Kojto 122:f9eeca106725 402 /**
Kojto 122:f9eeca106725 403 * @brief External Interrupt/Event Controller
Kojto 122:f9eeca106725 404 */
Kojto 122:f9eeca106725 405
Kojto 122:f9eeca106725 406 typedef struct
Kojto 122:f9eeca106725 407 {
Kojto 122:f9eeca106725 408 __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */
Kojto 122:f9eeca106725 409 __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */
Kojto 122:f9eeca106725 410 __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */
Kojto 122:f9eeca106725 411 __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */
Kojto 122:f9eeca106725 412 __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */
Kojto 122:f9eeca106725 413 __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */
Kojto 122:f9eeca106725 414 uint32_t RESERVED1; /*!< Reserved, 0x18 */
Kojto 122:f9eeca106725 415 uint32_t RESERVED2; /*!< Reserved, 0x1C */
Kojto 122:f9eeca106725 416 __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */
Kojto 122:f9eeca106725 417 __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */
Kojto 122:f9eeca106725 418 __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */
Kojto 122:f9eeca106725 419 __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */
Kojto 122:f9eeca106725 420 __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */
Kojto 122:f9eeca106725 421 __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */
Kojto 122:f9eeca106725 422 } EXTI_TypeDef;
Kojto 122:f9eeca106725 423
Kojto 122:f9eeca106725 424
Kojto 122:f9eeca106725 425 /**
Kojto 122:f9eeca106725 426 * @brief Firewall
Kojto 122:f9eeca106725 427 */
Kojto 122:f9eeca106725 428
Kojto 122:f9eeca106725 429 typedef struct
Kojto 122:f9eeca106725 430 {
Kojto 122:f9eeca106725 431 __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */
Kojto 122:f9eeca106725 432 __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */
Kojto 122:f9eeca106725 433 __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */
Kojto 122:f9eeca106725 434 __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */
Kojto 122:f9eeca106725 435 __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */
Kojto 122:f9eeca106725 436 __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */
Kojto 122:f9eeca106725 437 uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x18 */
Kojto 122:f9eeca106725 438 uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */
Kojto 122:f9eeca106725 439 __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */
Kojto 122:f9eeca106725 440 } FIREWALL_TypeDef;
Kojto 122:f9eeca106725 441
Kojto 122:f9eeca106725 442
Kojto 122:f9eeca106725 443 /**
Kojto 122:f9eeca106725 444 * @brief FLASH Registers
Kojto 122:f9eeca106725 445 */
Kojto 122:f9eeca106725 446
Kojto 122:f9eeca106725 447 typedef struct
Kojto 122:f9eeca106725 448 {
Kojto 122:f9eeca106725 449 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
Kojto 122:f9eeca106725 450 __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */
Kojto 122:f9eeca106725 451 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */
Kojto 122:f9eeca106725 452 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */
Kojto 122:f9eeca106725 453 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */
Kojto 122:f9eeca106725 454 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */
Kojto 122:f9eeca106725 455 __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */
Kojto 122:f9eeca106725 456 __IO uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */
Kojto 122:f9eeca106725 457 __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */
Kojto 122:f9eeca106725 458 __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */
Kojto 122:f9eeca106725 459 __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */
Kojto 122:f9eeca106725 460 __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */
Kojto 122:f9eeca106725 461 __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */
Kojto 122:f9eeca106725 462 } FLASH_TypeDef;
Kojto 122:f9eeca106725 463
Kojto 122:f9eeca106725 464
Kojto 122:f9eeca106725 465
Kojto 122:f9eeca106725 466 /**
Kojto 122:f9eeca106725 467 * @brief General Purpose I/O
Kojto 122:f9eeca106725 468 */
Kojto 122:f9eeca106725 469
Kojto 122:f9eeca106725 470 typedef struct
Kojto 122:f9eeca106725 471 {
Kojto 122:f9eeca106725 472 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
Kojto 122:f9eeca106725 473 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
Kojto 122:f9eeca106725 474 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
Kojto 122:f9eeca106725 475 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
Kojto 122:f9eeca106725 476 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
Kojto 122:f9eeca106725 477 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
Kojto 122:f9eeca106725 478 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
Kojto 122:f9eeca106725 479 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
Kojto 122:f9eeca106725 480 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
Kojto 122:f9eeca106725 481 __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */
Kojto 122:f9eeca106725 482
Kojto 122:f9eeca106725 483 } GPIO_TypeDef;
Kojto 122:f9eeca106725 484
Kojto 122:f9eeca106725 485
Kojto 122:f9eeca106725 486 /**
Kojto 122:f9eeca106725 487 * @brief Inter-integrated Circuit Interface
Kojto 122:f9eeca106725 488 */
Kojto 122:f9eeca106725 489
Kojto 122:f9eeca106725 490 typedef struct
Kojto 122:f9eeca106725 491 {
Kojto 122:f9eeca106725 492 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
Kojto 122:f9eeca106725 493 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
Kojto 122:f9eeca106725 494 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
Kojto 122:f9eeca106725 495 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
Kojto 122:f9eeca106725 496 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
Kojto 122:f9eeca106725 497 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
Kojto 122:f9eeca106725 498 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
Kojto 122:f9eeca106725 499 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
Kojto 122:f9eeca106725 500 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
Kojto 122:f9eeca106725 501 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
Kojto 122:f9eeca106725 502 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
Kojto 122:f9eeca106725 503 } I2C_TypeDef;
Kojto 122:f9eeca106725 504
Kojto 122:f9eeca106725 505 /**
Kojto 122:f9eeca106725 506 * @brief Independent WATCHDOG
Kojto 122:f9eeca106725 507 */
Kojto 122:f9eeca106725 508
Kojto 122:f9eeca106725 509 typedef struct
Kojto 122:f9eeca106725 510 {
Kojto 122:f9eeca106725 511 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
Kojto 122:f9eeca106725 512 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
Kojto 122:f9eeca106725 513 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
Kojto 122:f9eeca106725 514 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
Kojto 122:f9eeca106725 515 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
Kojto 122:f9eeca106725 516 } IWDG_TypeDef;
Kojto 122:f9eeca106725 517
Kojto 122:f9eeca106725 518 /**
Kojto 122:f9eeca106725 519 * @brief LPTIMER
Kojto 122:f9eeca106725 520 */
Kojto 122:f9eeca106725 521 typedef struct
Kojto 122:f9eeca106725 522 {
Kojto 122:f9eeca106725 523 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
Kojto 122:f9eeca106725 524 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
Kojto 122:f9eeca106725 525 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
Kojto 122:f9eeca106725 526 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
Kojto 122:f9eeca106725 527 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
Kojto 122:f9eeca106725 528 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
Kojto 122:f9eeca106725 529 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
Kojto 122:f9eeca106725 530 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
Kojto 122:f9eeca106725 531 __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
Kojto 122:f9eeca106725 532 } LPTIM_TypeDef;
Kojto 122:f9eeca106725 533
Kojto 122:f9eeca106725 534 /**
Kojto 122:f9eeca106725 535 * @brief Operational Amplifier (OPAMP)
Kojto 122:f9eeca106725 536 */
Kojto 122:f9eeca106725 537
Kojto 122:f9eeca106725 538 typedef struct
Kojto 122:f9eeca106725 539 {
Kojto 122:f9eeca106725 540 __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
Kojto 122:f9eeca106725 541 __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
Kojto 122:f9eeca106725 542 __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
Kojto 122:f9eeca106725 543 } OPAMP_TypeDef;
Kojto 122:f9eeca106725 544
Kojto 122:f9eeca106725 545 typedef struct
Kojto 122:f9eeca106725 546 {
Kojto 122:f9eeca106725 547 __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */
Kojto 122:f9eeca106725 548 } OPAMP_Common_TypeDef;
Kojto 122:f9eeca106725 549
Kojto 122:f9eeca106725 550 /**
Kojto 122:f9eeca106725 551 * @brief Power Control
Kojto 122:f9eeca106725 552 */
Kojto 122:f9eeca106725 553
Kojto 122:f9eeca106725 554 typedef struct
Kojto 122:f9eeca106725 555 {
Kojto 122:f9eeca106725 556 __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
Kojto 122:f9eeca106725 557 __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */
Kojto 122:f9eeca106725 558 __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */
Kojto 122:f9eeca106725 559 __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */
Kojto 122:f9eeca106725 560 __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */
Kojto 122:f9eeca106725 561 __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */
Kojto 122:f9eeca106725 562 __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */
Kojto 122:f9eeca106725 563 uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */
Kojto 122:f9eeca106725 564 __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */
Kojto 122:f9eeca106725 565 __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */
Kojto 122:f9eeca106725 566 __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */
Kojto 122:f9eeca106725 567 __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */
Kojto 122:f9eeca106725 568 __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */
Kojto 122:f9eeca106725 569 __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */
Kojto 122:f9eeca106725 570 __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */
Kojto 122:f9eeca106725 571 __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */
Kojto 122:f9eeca106725 572 __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */
Kojto 122:f9eeca106725 573 __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */
Kojto 122:f9eeca106725 574 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x48 */
Kojto 122:f9eeca106725 575 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x4C */
Kojto 122:f9eeca106725 576 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x50 */
Kojto 122:f9eeca106725 577 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x54 */
Kojto 122:f9eeca106725 578 __IO uint32_t PUCRH; /*!< Pull_up control register of portH, Address offset: 0x58 */
Kojto 122:f9eeca106725 579 __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */
Kojto 122:f9eeca106725 580 } PWR_TypeDef;
Kojto 122:f9eeca106725 581
Kojto 122:f9eeca106725 582
Kojto 122:f9eeca106725 583 /**
Kojto 122:f9eeca106725 584 * @brief QUAD Serial Peripheral Interface
Kojto 122:f9eeca106725 585 */
Kojto 122:f9eeca106725 586
Kojto 122:f9eeca106725 587 typedef struct
Kojto 122:f9eeca106725 588 {
Kojto 122:f9eeca106725 589 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
Kojto 122:f9eeca106725 590 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
Kojto 122:f9eeca106725 591 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
Kojto 122:f9eeca106725 592 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
Kojto 122:f9eeca106725 593 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
Kojto 122:f9eeca106725 594 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
Kojto 122:f9eeca106725 595 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
Kojto 122:f9eeca106725 596 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
Kojto 122:f9eeca106725 597 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
Kojto 122:f9eeca106725 598 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
Kojto 122:f9eeca106725 599 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
Kojto 122:f9eeca106725 600 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
Kojto 122:f9eeca106725 601 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
Kojto 122:f9eeca106725 602 } QUADSPI_TypeDef;
Kojto 122:f9eeca106725 603
Kojto 122:f9eeca106725 604
Kojto 122:f9eeca106725 605 /**
Kojto 122:f9eeca106725 606 * @brief Reset and Clock Control
Kojto 122:f9eeca106725 607 */
Kojto 122:f9eeca106725 608
Kojto 122:f9eeca106725 609 typedef struct
Kojto 122:f9eeca106725 610 {
Kojto 122:f9eeca106725 611 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
Kojto 122:f9eeca106725 612 __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */
Kojto 122:f9eeca106725 613 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
Kojto 122:f9eeca106725 614 __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */
Kojto 122:f9eeca106725 615 __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration register, Address offset: 0x10 */
Kojto 122:f9eeca106725 616 uint32_t RESERVED; /*!< Reserved, Address offset: 0x14 */
Kojto 122:f9eeca106725 617 __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */
Kojto 122:f9eeca106725 618 __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */
Kojto 122:f9eeca106725 619 __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */
Kojto 122:f9eeca106725 620 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x24 */
Kojto 122:f9eeca106725 621 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */
Kojto 122:f9eeca106725 622 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */
Kojto 122:f9eeca106725 623 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */
Kojto 122:f9eeca106725 624 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x34 */
Kojto 122:f9eeca106725 625 __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */
Kojto 122:f9eeca106725 626 __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */
Kojto 122:f9eeca106725 627 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */
Kojto 122:f9eeca106725 628 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x44 */
Kojto 122:f9eeca106725 629 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */
Kojto 122:f9eeca106725 630 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */
Kojto 122:f9eeca106725 631 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */
Kojto 122:f9eeca106725 632 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x54 */
Kojto 122:f9eeca106725 633 __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */
Kojto 122:f9eeca106725 634 __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */
Kojto 122:f9eeca106725 635 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */
Kojto 122:f9eeca106725 636 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x64 */
Kojto 122:f9eeca106725 637 __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */
Kojto 122:f9eeca106725 638 __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */
Kojto 122:f9eeca106725 639 __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */
Kojto 122:f9eeca106725 640 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x74 */
Kojto 122:f9eeca106725 641 __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
Kojto 122:f9eeca106725 642 __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
Kojto 122:f9eeca106725 643 __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
Kojto 122:f9eeca106725 644 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x84 */
Kojto 122:f9eeca106725 645 __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */
Kojto 122:f9eeca106725 646 __IO uint32_t RESERVED7; /*!< Reserved, Address offset: 0x8C */
Kojto 122:f9eeca106725 647 __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */
Kojto 122:f9eeca106725 648 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */
Kojto 122:f9eeca106725 649 __IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */
Kojto 122:f9eeca106725 650 } RCC_TypeDef;
Kojto 122:f9eeca106725 651
Kojto 122:f9eeca106725 652 /**
Kojto 122:f9eeca106725 653 * @brief Real-Time Clock
Kojto 122:f9eeca106725 654 */
Kojto 122:f9eeca106725 655
Kojto 122:f9eeca106725 656 typedef struct
Kojto 122:f9eeca106725 657 {
Kojto 122:f9eeca106725 658 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
Kojto 122:f9eeca106725 659 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
Kojto 122:f9eeca106725 660 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
Kojto 122:f9eeca106725 661 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
Kojto 122:f9eeca106725 662 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
Kojto 122:f9eeca106725 663 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
Kojto 122:f9eeca106725 664 uint32_t reserved; /*!< Reserved */
Kojto 122:f9eeca106725 665 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
Kojto 122:f9eeca106725 666 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
Kojto 122:f9eeca106725 667 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
Kojto 122:f9eeca106725 668 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
Kojto 122:f9eeca106725 669 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
Kojto 122:f9eeca106725 670 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
Kojto 122:f9eeca106725 671 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
Kojto 122:f9eeca106725 672 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
Kojto 122:f9eeca106725 673 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
Kojto 122:f9eeca106725 674 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
Kojto 122:f9eeca106725 675 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
Kojto 122:f9eeca106725 676 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
Kojto 122:f9eeca106725 677 __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
Kojto 122:f9eeca106725 678 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
Kojto 122:f9eeca106725 679 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
Kojto 122:f9eeca106725 680 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
Kojto 122:f9eeca106725 681 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
Kojto 122:f9eeca106725 682 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
Kojto 122:f9eeca106725 683 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
Kojto 122:f9eeca106725 684 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
Kojto 122:f9eeca106725 685 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
Kojto 122:f9eeca106725 686 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
Kojto 122:f9eeca106725 687 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
Kojto 122:f9eeca106725 688 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
Kojto 122:f9eeca106725 689 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
Kojto 122:f9eeca106725 690 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
Kojto 122:f9eeca106725 691 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
Kojto 122:f9eeca106725 692 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
Kojto 122:f9eeca106725 693 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
Kojto 122:f9eeca106725 694 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
Kojto 122:f9eeca106725 695 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
Kojto 122:f9eeca106725 696 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
Kojto 122:f9eeca106725 697 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
Kojto 122:f9eeca106725 698 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
Kojto 122:f9eeca106725 699 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
Kojto 122:f9eeca106725 700 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
Kojto 122:f9eeca106725 701 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
Kojto 122:f9eeca106725 702 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
Kojto 122:f9eeca106725 703 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
Kojto 122:f9eeca106725 704 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
Kojto 122:f9eeca106725 705 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
Kojto 122:f9eeca106725 706 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
Kojto 122:f9eeca106725 707 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
Kojto 122:f9eeca106725 708 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
Kojto 122:f9eeca106725 709 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
Kojto 122:f9eeca106725 710 } RTC_TypeDef;
Kojto 122:f9eeca106725 711
Kojto 122:f9eeca106725 712
Kojto 122:f9eeca106725 713 /**
Kojto 122:f9eeca106725 714 * @brief Serial Audio Interface
Kojto 122:f9eeca106725 715 */
Kojto 122:f9eeca106725 716
Kojto 122:f9eeca106725 717 typedef struct
Kojto 122:f9eeca106725 718 {
Kojto 122:f9eeca106725 719 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
Kojto 122:f9eeca106725 720 } SAI_TypeDef;
Kojto 122:f9eeca106725 721
Kojto 122:f9eeca106725 722 typedef struct
Kojto 122:f9eeca106725 723 {
Kojto 122:f9eeca106725 724 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
Kojto 122:f9eeca106725 725 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
Kojto 122:f9eeca106725 726 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
Kojto 122:f9eeca106725 727 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
Kojto 122:f9eeca106725 728 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
Kojto 122:f9eeca106725 729 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
Kojto 122:f9eeca106725 730 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
Kojto 122:f9eeca106725 731 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
Kojto 122:f9eeca106725 732 } SAI_Block_TypeDef;
Kojto 122:f9eeca106725 733
Kojto 122:f9eeca106725 734
Kojto 122:f9eeca106725 735 /**
Kojto 122:f9eeca106725 736 * @brief Serial Peripheral Interface
Kojto 122:f9eeca106725 737 */
Kojto 122:f9eeca106725 738
Kojto 122:f9eeca106725 739 typedef struct
Kojto 122:f9eeca106725 740 {
Kojto 122:f9eeca106725 741 __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
Kojto 122:f9eeca106725 742 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
Kojto 122:f9eeca106725 743 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
Kojto 122:f9eeca106725 744 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
Kojto 122:f9eeca106725 745 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
Kojto 122:f9eeca106725 746 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
Kojto 122:f9eeca106725 747 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
Kojto 122:f9eeca106725 748 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
Kojto 122:f9eeca106725 749 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
Kojto 122:f9eeca106725 750 } SPI_TypeDef;
Kojto 122:f9eeca106725 751
Kojto 122:f9eeca106725 752
Kojto 122:f9eeca106725 753 /**
Kojto 122:f9eeca106725 754 * @brief Single Wire Protocol Master Interface SPWMI
Kojto 122:f9eeca106725 755 */
Kojto 122:f9eeca106725 756
Kojto 122:f9eeca106725 757 typedef struct
Kojto 122:f9eeca106725 758 {
Kojto 122:f9eeca106725 759 __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */
Kojto 122:f9eeca106725 760 __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */
Kojto 122:f9eeca106725 761 uint32_t RESERVED1; /*!< Reserved, 0x08 */
Kojto 122:f9eeca106725 762 __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */
Kojto 122:f9eeca106725 763 __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */
Kojto 122:f9eeca106725 764 __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */
Kojto 122:f9eeca106725 765 __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */
Kojto 122:f9eeca106725 766 __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */
Kojto 122:f9eeca106725 767 __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */
Kojto 122:f9eeca106725 768 __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */
Kojto 122:f9eeca106725 769 } SWPMI_TypeDef;
Kojto 122:f9eeca106725 770
Kojto 122:f9eeca106725 771
Kojto 122:f9eeca106725 772 /**
Kojto 122:f9eeca106725 773 * @brief System configuration controller
Kojto 122:f9eeca106725 774 */
Kojto 122:f9eeca106725 775
Kojto 122:f9eeca106725 776 typedef struct
Kojto 122:f9eeca106725 777 {
Kojto 122:f9eeca106725 778 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
Kojto 122:f9eeca106725 779 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */
Kojto 122:f9eeca106725 780 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
Kojto 122:f9eeca106725 781 __IO uint32_t SCSR; /*!< SYSCFG SRAM2 control and status register, Address offset: 0x18 */
Kojto 122:f9eeca106725 782 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */
Kojto 122:f9eeca106725 783 __IO uint32_t SWPR; /*!< SYSCFG SRAM2 write protection register, Address offset: 0x20 */
Kojto 122:f9eeca106725 784 __IO uint32_t SKR; /*!< SYSCFG SRAM2 key register, Address offset: 0x24 */
Kojto 122:f9eeca106725 785 } SYSCFG_TypeDef;
Kojto 122:f9eeca106725 786
Kojto 122:f9eeca106725 787
Kojto 122:f9eeca106725 788 /**
Kojto 122:f9eeca106725 789 * @brief TIM
Kojto 122:f9eeca106725 790 */
Kojto 122:f9eeca106725 791
Kojto 122:f9eeca106725 792 typedef struct
Kojto 122:f9eeca106725 793 {
Kojto 122:f9eeca106725 794 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
Kojto 122:f9eeca106725 795 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
Kojto 122:f9eeca106725 796 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
Kojto 122:f9eeca106725 797 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
Kojto 122:f9eeca106725 798 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
Kojto 122:f9eeca106725 799 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
Kojto 122:f9eeca106725 800 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
Kojto 122:f9eeca106725 801 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
Kojto 122:f9eeca106725 802 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
Kojto 122:f9eeca106725 803 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
Kojto 122:f9eeca106725 804 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
Kojto 122:f9eeca106725 805 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
Kojto 122:f9eeca106725 806 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
Kojto 122:f9eeca106725 807 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
Kojto 122:f9eeca106725 808 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
Kojto 122:f9eeca106725 809 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
Kojto 122:f9eeca106725 810 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
Kojto 122:f9eeca106725 811 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
Kojto 122:f9eeca106725 812 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
Kojto 122:f9eeca106725 813 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
Kojto 122:f9eeca106725 814 __IO uint32_t OR1; /*!< TIM option register 1, Address offset: 0x50 */
Kojto 122:f9eeca106725 815 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
Kojto 122:f9eeca106725 816 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
Kojto 122:f9eeca106725 817 __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
Kojto 122:f9eeca106725 818 __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */
Kojto 122:f9eeca106725 819 __IO uint32_t OR3; /*!< TIM option register 3, Address offset: 0x64 */
Kojto 122:f9eeca106725 820 } TIM_TypeDef;
Kojto 122:f9eeca106725 821
Kojto 122:f9eeca106725 822
Kojto 122:f9eeca106725 823 /**
Kojto 122:f9eeca106725 824 * @brief Touch Sensing Controller (TSC)
Kojto 122:f9eeca106725 825 */
Kojto 122:f9eeca106725 826
Kojto 122:f9eeca106725 827 typedef struct
Kojto 122:f9eeca106725 828 {
Kojto 122:f9eeca106725 829 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
Kojto 122:f9eeca106725 830 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
Kojto 122:f9eeca106725 831 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
Kojto 122:f9eeca106725 832 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
Kojto 122:f9eeca106725 833 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
Kojto 122:f9eeca106725 834 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
Kojto 122:f9eeca106725 835 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
Kojto 122:f9eeca106725 836 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
Kojto 122:f9eeca106725 837 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
Kojto 122:f9eeca106725 838 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
Kojto 122:f9eeca106725 839 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
Kojto 122:f9eeca106725 840 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
Kojto 122:f9eeca106725 841 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
Kojto 122:f9eeca106725 842 __IO uint32_t IOGXCR[7]; /*!< TSC I/O group x counter register, Address offset: 0x34-4C */
Kojto 122:f9eeca106725 843 } TSC_TypeDef;
Kojto 122:f9eeca106725 844
Kojto 122:f9eeca106725 845 /**
Kojto 122:f9eeca106725 846 * @brief Universal Synchronous Asynchronous Receiver Transmitter
Kojto 122:f9eeca106725 847 */
Kojto 122:f9eeca106725 848
Kojto 122:f9eeca106725 849 typedef struct
Kojto 122:f9eeca106725 850 {
Kojto 122:f9eeca106725 851 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
Kojto 122:f9eeca106725 852 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
Kojto 122:f9eeca106725 853 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
Kojto 122:f9eeca106725 854 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
Kojto 122:f9eeca106725 855 __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
Kojto 122:f9eeca106725 856 uint16_t RESERVED2; /*!< Reserved, 0x12 */
Kojto 122:f9eeca106725 857 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
Kojto 122:f9eeca106725 858 __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */
Kojto 122:f9eeca106725 859 uint16_t RESERVED3; /*!< Reserved, 0x1A */
Kojto 122:f9eeca106725 860 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
Kojto 122:f9eeca106725 861 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
Kojto 122:f9eeca106725 862 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
Kojto 122:f9eeca106725 863 uint16_t RESERVED4; /*!< Reserved, 0x26 */
Kojto 122:f9eeca106725 864 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
Kojto 122:f9eeca106725 865 uint16_t RESERVED5; /*!< Reserved, 0x2A */
Kojto 122:f9eeca106725 866 } USART_TypeDef;
Kojto 122:f9eeca106725 867
Kojto 122:f9eeca106725 868 /**
Kojto 122:f9eeca106725 869 * @brief Universal Serial Bus Full Speed Device
Kojto 122:f9eeca106725 870 */
Kojto 122:f9eeca106725 871
Kojto 122:f9eeca106725 872 typedef struct
Kojto 122:f9eeca106725 873 {
Kojto 122:f9eeca106725 874 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
Kojto 122:f9eeca106725 875 __IO uint16_t RESERVED0; /*!< Reserved */
Kojto 122:f9eeca106725 876 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
Kojto 122:f9eeca106725 877 __IO uint16_t RESERVED1; /*!< Reserved */
Kojto 122:f9eeca106725 878 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
Kojto 122:f9eeca106725 879 __IO uint16_t RESERVED2; /*!< Reserved */
Kojto 122:f9eeca106725 880 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
Kojto 122:f9eeca106725 881 __IO uint16_t RESERVED3; /*!< Reserved */
Kojto 122:f9eeca106725 882 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
Kojto 122:f9eeca106725 883 __IO uint16_t RESERVED4; /*!< Reserved */
Kojto 122:f9eeca106725 884 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
Kojto 122:f9eeca106725 885 __IO uint16_t RESERVED5; /*!< Reserved */
Kojto 122:f9eeca106725 886 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
Kojto 122:f9eeca106725 887 __IO uint16_t RESERVED6; /*!< Reserved */
Kojto 122:f9eeca106725 888 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
Kojto 122:f9eeca106725 889 __IO uint16_t RESERVED7[17]; /*!< Reserved */
Kojto 122:f9eeca106725 890 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
Kojto 122:f9eeca106725 891 __IO uint16_t RESERVED8; /*!< Reserved */
Kojto 122:f9eeca106725 892 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
Kojto 122:f9eeca106725 893 __IO uint16_t RESERVED9; /*!< Reserved */
Kojto 122:f9eeca106725 894 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
Kojto 122:f9eeca106725 895 __IO uint16_t RESERVEDA; /*!< Reserved */
Kojto 122:f9eeca106725 896 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
Kojto 122:f9eeca106725 897 __IO uint16_t RESERVEDB; /*!< Reserved */
Kojto 122:f9eeca106725 898 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
Kojto 122:f9eeca106725 899 __IO uint16_t RESERVEDC; /*!< Reserved */
Kojto 122:f9eeca106725 900 __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
Kojto 122:f9eeca106725 901 __IO uint16_t RESERVEDD; /*!< Reserved */
Kojto 122:f9eeca106725 902 __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */
Kojto 122:f9eeca106725 903 __IO uint16_t RESERVEDE; /*!< Reserved */
Kojto 122:f9eeca106725 904 } USB_TypeDef;
Kojto 122:f9eeca106725 905
Kojto 122:f9eeca106725 906
Kojto 122:f9eeca106725 907 /**
Kojto 122:f9eeca106725 908 * @brief Window WATCHDOG
Kojto 122:f9eeca106725 909 */
Kojto 122:f9eeca106725 910
Kojto 122:f9eeca106725 911 typedef struct
Kojto 122:f9eeca106725 912 {
Kojto 122:f9eeca106725 913 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
Kojto 122:f9eeca106725 914 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
Kojto 122:f9eeca106725 915 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
Kojto 122:f9eeca106725 916 } WWDG_TypeDef;
Kojto 122:f9eeca106725 917
Kojto 122:f9eeca106725 918 /**
Kojto 122:f9eeca106725 919 * @brief RNG
Kojto 122:f9eeca106725 920 */
Kojto 122:f9eeca106725 921
Kojto 122:f9eeca106725 922 typedef struct
Kojto 122:f9eeca106725 923 {
Kojto 122:f9eeca106725 924 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
Kojto 122:f9eeca106725 925 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
Kojto 122:f9eeca106725 926 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
Kojto 122:f9eeca106725 927 } RNG_TypeDef;
Kojto 122:f9eeca106725 928
Kojto 122:f9eeca106725 929 /**
Kojto 122:f9eeca106725 930 * @}
Kojto 122:f9eeca106725 931 */
Kojto 122:f9eeca106725 932
Kojto 122:f9eeca106725 933 /** @addtogroup Peripheral_memory_map
Kojto 122:f9eeca106725 934 * @{
Kojto 122:f9eeca106725 935 */
Kojto 122:f9eeca106725 936 #define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address */
Kojto 122:f9eeca106725 937 #define SRAM1_BASE ((uint32_t)0x20000000U) /*!< SRAM1(up to 48 KB) base address */
Kojto 122:f9eeca106725 938 #define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address */
Kojto 122:f9eeca106725 939 #define SRAM2_BASE ((uint32_t)0x10000000U) /*!< SRAM2(16 KB) base address */
Kojto 122:f9eeca106725 940 #define QSPI_BASE ((uint32_t)0x90000000U) /*!< QSPI memories accessible over AHB base address */
Kojto 122:f9eeca106725 941 #define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
Kojto 122:f9eeca106725 942 #define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
Kojto 122:f9eeca106725 943 #define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
Kojto 122:f9eeca106725 944 #define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
Kojto 122:f9eeca106725 945
Kojto 122:f9eeca106725 946 /* Legacy defines */
Kojto 122:f9eeca106725 947 #define SRAM_BASE SRAM1_BASE
Kojto 122:f9eeca106725 948 #define SRAM_BB_BASE SRAM1_BB_BASE
Kojto 122:f9eeca106725 949
Kojto 122:f9eeca106725 950 #define SRAM1_SIZE_MAX ((uint32_t)0x0000C000U) /*!< maximum SRAM1 size (up to 48 KBytes) */
Kojto 122:f9eeca106725 951 #define SRAM2_SIZE ((uint32_t)0x00004000U) /*!< SRAM2 size (16 KBytes) */
Kojto 122:f9eeca106725 952
Kojto 122:f9eeca106725 953 /*!< Peripheral memory map */
Kojto 122:f9eeca106725 954 #define APB1PERIPH_BASE PERIPH_BASE
Kojto 122:f9eeca106725 955 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
Kojto 122:f9eeca106725 956 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
Kojto 122:f9eeca106725 957 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000U)
Kojto 122:f9eeca106725 958
Kojto 122:f9eeca106725 959
Kojto 122:f9eeca106725 960 /*!< APB1 peripherals */
Kojto 122:f9eeca106725 961 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
Kojto 122:f9eeca106725 962 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
Kojto 122:f9eeca106725 963 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
Kojto 122:f9eeca106725 964 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
Kojto 122:f9eeca106725 965 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
Kojto 122:f9eeca106725 966 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
Kojto 122:f9eeca106725 967 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
Kojto 122:f9eeca106725 968 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
Kojto 122:f9eeca106725 969 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
Kojto 122:f9eeca106725 970 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
Kojto 122:f9eeca106725 971 #define CRS_BASE (APB1PERIPH_BASE + 0x6000U)
Kojto 122:f9eeca106725 972 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
Kojto 122:f9eeca106725 973 #define USB_BASE (APB1PERIPH_BASE + 0x6800U) /*!< USB_IP Peripheral Registers base address */
Kojto 122:f9eeca106725 974 #define USB_PMAADDR (APB1PERIPH_BASE + 0x6C00U) /*!< USB_IP Packet Memory Area base address */
Kojto 122:f9eeca106725 975 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
Kojto 122:f9eeca106725 976 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
Kojto 122:f9eeca106725 977 #define DAC1_BASE (APB1PERIPH_BASE + 0x7400U)
Kojto 122:f9eeca106725 978 #define OPAMP_BASE (APB1PERIPH_BASE + 0x7800U)
Kojto 122:f9eeca106725 979 #define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800U)
Kojto 122:f9eeca106725 980 #define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00U)
Kojto 122:f9eeca106725 981 #define LPUART1_BASE (APB1PERIPH_BASE + 0x8000U)
Kojto 122:f9eeca106725 982 #define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800U)
Kojto 122:f9eeca106725 983 #define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400U)
Kojto 122:f9eeca106725 984
Kojto 122:f9eeca106725 985
Kojto 122:f9eeca106725 986 /*!< APB2 peripherals */
Kojto 122:f9eeca106725 987 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000U)
Kojto 122:f9eeca106725 988 #define COMP1_BASE (APB2PERIPH_BASE + 0x0200U)
Kojto 122:f9eeca106725 989 #define COMP2_BASE (APB2PERIPH_BASE + 0x0204U)
Kojto 122:f9eeca106725 990 #define EXTI_BASE (APB2PERIPH_BASE + 0x0400U)
Kojto 122:f9eeca106725 991 #define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00U)
Kojto 122:f9eeca106725 992 #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00U)
Kojto 122:f9eeca106725 993 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
Kojto 122:f9eeca106725 994 #define USART1_BASE (APB2PERIPH_BASE + 0x3800U)
Kojto 122:f9eeca106725 995 #define TIM15_BASE (APB2PERIPH_BASE + 0x4000U)
Kojto 122:f9eeca106725 996 #define TIM16_BASE (APB2PERIPH_BASE + 0x4400U)
Kojto 122:f9eeca106725 997 #define SAI1_BASE (APB2PERIPH_BASE + 0x5400U)
Kojto 122:f9eeca106725 998 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
Kojto 122:f9eeca106725 999 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
Kojto 122:f9eeca106725 1000
Kojto 122:f9eeca106725 1001 /*!< AHB1 peripherals */
Kojto 122:f9eeca106725 1002 #define DMA1_BASE (AHB1PERIPH_BASE)
Kojto 122:f9eeca106725 1003 #define DMA2_BASE (AHB1PERIPH_BASE + 0x0400U)
Kojto 122:f9eeca106725 1004 #define RCC_BASE (AHB1PERIPH_BASE + 0x1000U)
Kojto 122:f9eeca106725 1005 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000U)
Kojto 122:f9eeca106725 1006 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
Kojto 122:f9eeca106725 1007 #define TSC_BASE (AHB1PERIPH_BASE + 0x4000U)
Kojto 122:f9eeca106725 1008
Kojto 122:f9eeca106725 1009
Kojto 122:f9eeca106725 1010 #define DMA1_Channel1_BASE (DMA1_BASE + 0x0008U)
Kojto 122:f9eeca106725 1011 #define DMA1_Channel2_BASE (DMA1_BASE + 0x001CU)
Kojto 122:f9eeca106725 1012 #define DMA1_Channel3_BASE (DMA1_BASE + 0x0030U)
Kojto 122:f9eeca106725 1013 #define DMA1_Channel4_BASE (DMA1_BASE + 0x0044U)
Kojto 122:f9eeca106725 1014 #define DMA1_Channel5_BASE (DMA1_BASE + 0x0058U)
Kojto 122:f9eeca106725 1015 #define DMA1_Channel6_BASE (DMA1_BASE + 0x006CU)
Kojto 122:f9eeca106725 1016 #define DMA1_Channel7_BASE (DMA1_BASE + 0x0080U)
Kojto 122:f9eeca106725 1017 #define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8U)
Kojto 122:f9eeca106725 1018
Kojto 122:f9eeca106725 1019
Kojto 122:f9eeca106725 1020 #define DMA2_Channel1_BASE (DMA2_BASE + 0x0008U)
Kojto 122:f9eeca106725 1021 #define DMA2_Channel2_BASE (DMA2_BASE + 0x001CU)
Kojto 122:f9eeca106725 1022 #define DMA2_Channel3_BASE (DMA2_BASE + 0x0030U)
Kojto 122:f9eeca106725 1023 #define DMA2_Channel4_BASE (DMA2_BASE + 0x0044U)
Kojto 122:f9eeca106725 1024 #define DMA2_Channel5_BASE (DMA2_BASE + 0x0058U)
Kojto 122:f9eeca106725 1025 #define DMA2_Channel6_BASE (DMA2_BASE + 0x006CU)
Kojto 122:f9eeca106725 1026 #define DMA2_Channel7_BASE (DMA2_BASE + 0x0080U)
Kojto 122:f9eeca106725 1027 #define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8U)
Kojto 122:f9eeca106725 1028
Kojto 122:f9eeca106725 1029
Kojto 122:f9eeca106725 1030 /*!< AHB2 peripherals */
Kojto 122:f9eeca106725 1031 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000U)
Kojto 122:f9eeca106725 1032 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400U)
Kojto 122:f9eeca106725 1033 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800U)
Kojto 122:f9eeca106725 1034 #define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00U)
Kojto 122:f9eeca106725 1035
Kojto 122:f9eeca106725 1036
Kojto 122:f9eeca106725 1037 #define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000U)
Kojto 122:f9eeca106725 1038 #define ADC1_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300U)
Kojto 122:f9eeca106725 1039
Kojto 122:f9eeca106725 1040
Kojto 122:f9eeca106725 1041 #define RNG_BASE (AHB2PERIPH_BASE + 0x08060800U)
Kojto 122:f9eeca106725 1042
Kojto 122:f9eeca106725 1043
Kojto 122:f9eeca106725 1044
Kojto 122:f9eeca106725 1045 /* Debug MCU registers base address */
Kojto 122:f9eeca106725 1046 #define DBGMCU_BASE ((uint32_t)0xE0042000U)
Kojto 122:f9eeca106725 1047
Kojto 122:f9eeca106725 1048
Kojto 122:f9eeca106725 1049 #define PACKAGE_BASE ((uint32_t)0x1FFF7500U) /*!< Package data register base address */
Kojto 122:f9eeca106725 1050 #define UID_BASE ((uint32_t)0x1FFF7590U) /*!< Unique device ID register base address */
Kojto 122:f9eeca106725 1051 #define FLASHSIZE_BASE ((uint32_t)0x1FFF75E0U) /*!< Flash size data register base address */
Kojto 122:f9eeca106725 1052 /**
Kojto 122:f9eeca106725 1053 * @}
Kojto 122:f9eeca106725 1054 */
Kojto 122:f9eeca106725 1055
Kojto 122:f9eeca106725 1056 /** @addtogroup Peripheral_declaration
Kojto 122:f9eeca106725 1057 * @{
Kojto 122:f9eeca106725 1058 */
Kojto 122:f9eeca106725 1059 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
Kojto 122:f9eeca106725 1060 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
Kojto 122:f9eeca106725 1061 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
Kojto 122:f9eeca106725 1062 #define RTC ((RTC_TypeDef *) RTC_BASE)
Kojto 122:f9eeca106725 1063 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
Kojto 122:f9eeca106725 1064 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
Kojto 122:f9eeca106725 1065 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
Kojto 122:f9eeca106725 1066 #define USART2 ((USART_TypeDef *) USART2_BASE)
Kojto 122:f9eeca106725 1067 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
Kojto 122:f9eeca106725 1068 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
Kojto 122:f9eeca106725 1069 #define CRS ((CRS_TypeDef *) CRS_BASE)
Kojto 122:f9eeca106725 1070 //#define CAN ((CAN_TypeDef *) CAN1_BASE)
Kojto 122:f9eeca106725 1071 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
Kojto 122:f9eeca106725 1072 #define USB ((USB_TypeDef *) USB_BASE)
Kojto 122:f9eeca106725 1073 #define PWR ((PWR_TypeDef *) PWR_BASE)
Kojto 122:f9eeca106725 1074 #define DAC ((DAC_TypeDef *) DAC1_BASE)
Kojto 122:f9eeca106725 1075 #define DAC1 ((DAC_TypeDef *) DAC1_BASE)
Kojto 122:f9eeca106725 1076 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
Kojto 122:f9eeca106725 1077 #define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
Kojto 122:f9eeca106725 1078 #define OPAMP1_COMMON ((OPAMP_Common_TypeDef *) OPAMP1_BASE)
Kojto 122:f9eeca106725 1079 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
Kojto 122:f9eeca106725 1080 #define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
Kojto 122:f9eeca106725 1081 #define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)
Kojto 122:f9eeca106725 1082 #define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
Kojto 122:f9eeca106725 1083
Kojto 122:f9eeca106725 1084 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
Kojto 122:f9eeca106725 1085 #define COMP1 ((COMP_TypeDef *) COMP1_BASE)
Kojto 122:f9eeca106725 1086 #define COMP2 ((COMP_TypeDef *) COMP2_BASE)
Kojto 122:f9eeca106725 1087 #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
Kojto 122:f9eeca106725 1088 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
Kojto 122:f9eeca106725 1089 #define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)
Kojto 122:f9eeca106725 1090 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
Kojto 122:f9eeca106725 1091 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
Kojto 122:f9eeca106725 1092 #define USART1 ((USART_TypeDef *) USART1_BASE)
Kojto 122:f9eeca106725 1093 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
Kojto 122:f9eeca106725 1094 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
Kojto 122:f9eeca106725 1095 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
Kojto 122:f9eeca106725 1096 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
Kojto 122:f9eeca106725 1097 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
Kojto 122:f9eeca106725 1098 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
Kojto 122:f9eeca106725 1099 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
Kojto 122:f9eeca106725 1100 #define RCC ((RCC_TypeDef *) RCC_BASE)
Kojto 122:f9eeca106725 1101 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
Kojto 122:f9eeca106725 1102 #define CRC ((CRC_TypeDef *) CRC_BASE)
Kojto 122:f9eeca106725 1103 #define TSC ((TSC_TypeDef *) TSC_BASE)
Kojto 122:f9eeca106725 1104
Kojto 122:f9eeca106725 1105 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
Kojto 122:f9eeca106725 1106 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
Kojto 122:f9eeca106725 1107 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
Kojto 122:f9eeca106725 1108 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
Kojto 122:f9eeca106725 1109 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
Kojto 122:f9eeca106725 1110 #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
Kojto 122:f9eeca106725 1111 #define RNG ((RNG_TypeDef *) RNG_BASE)
Kojto 122:f9eeca106725 1112
Kojto 122:f9eeca106725 1113
Kojto 122:f9eeca106725 1114 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
Kojto 122:f9eeca106725 1115 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
Kojto 122:f9eeca106725 1116 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
Kojto 122:f9eeca106725 1117 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
Kojto 122:f9eeca106725 1118 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
Kojto 122:f9eeca106725 1119 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
Kojto 122:f9eeca106725 1120 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
Kojto 122:f9eeca106725 1121 #define DMA1_CSELR ((DMA_request_TypeDef *) DMA1_CSELR_BASE)
Kojto 122:f9eeca106725 1122
Kojto 122:f9eeca106725 1123
Kojto 122:f9eeca106725 1124 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
Kojto 122:f9eeca106725 1125 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
Kojto 122:f9eeca106725 1126 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
Kojto 122:f9eeca106725 1127 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
Kojto 122:f9eeca106725 1128 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
Kojto 122:f9eeca106725 1129 #define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
Kojto 122:f9eeca106725 1130 #define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
Kojto 122:f9eeca106725 1131 #define DMA2_CSELR ((DMA_request_TypeDef *) DMA2_CSELR_BASE)
Kojto 122:f9eeca106725 1132
Kojto 122:f9eeca106725 1133
Kojto 122:f9eeca106725 1134
Kojto 122:f9eeca106725 1135 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
Kojto 122:f9eeca106725 1136
Kojto 122:f9eeca106725 1137 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
Kojto 122:f9eeca106725 1138
Kojto 122:f9eeca106725 1139 /**
Kojto 122:f9eeca106725 1140 * @}
Kojto 122:f9eeca106725 1141 */
Kojto 122:f9eeca106725 1142
Kojto 122:f9eeca106725 1143 /** @addtogroup Exported_constants
Kojto 122:f9eeca106725 1144 * @{
Kojto 122:f9eeca106725 1145 */
Kojto 122:f9eeca106725 1146
Kojto 122:f9eeca106725 1147 /** @addtogroup Peripheral_Registers_Bits_Definition
Kojto 122:f9eeca106725 1148 * @{
Kojto 122:f9eeca106725 1149 */
Kojto 122:f9eeca106725 1150
Kojto 122:f9eeca106725 1151 /******************************************************************************/
Kojto 122:f9eeca106725 1152 /* Peripheral Registers_Bits_Definition */
Kojto 122:f9eeca106725 1153 /******************************************************************************/
Kojto 122:f9eeca106725 1154
Kojto 122:f9eeca106725 1155 /******************************************************************************/
Kojto 122:f9eeca106725 1156 /* */
Kojto 122:f9eeca106725 1157 /* Analog to Digital Converter */
Kojto 122:f9eeca106725 1158 /* */
Kojto 122:f9eeca106725 1159 /******************************************************************************/
Kojto 122:f9eeca106725 1160
Kojto 122:f9eeca106725 1161 /*
Kojto 122:f9eeca106725 1162 * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
Kojto 122:f9eeca106725 1163 */
Kojto 122:f9eeca106725 1164 /* Note: No specific macro feature on this device */
Kojto 122:f9eeca106725 1165
Kojto 122:f9eeca106725 1166 /******************** Bit definition for ADC_ISR register *******************/
Kojto 122:f9eeca106725 1167 #define ADC_ISR_ADRDY_Pos (0U)
Kojto 122:f9eeca106725 1168 #define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1169 #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */
Kojto 122:f9eeca106725 1170 #define ADC_ISR_EOSMP_Pos (1U)
Kojto 122:f9eeca106725 1171 #define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1172 #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */
Kojto 122:f9eeca106725 1173 #define ADC_ISR_EOC_Pos (2U)
Kojto 122:f9eeca106725 1174 #define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1175 #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */
Kojto 122:f9eeca106725 1176 #define ADC_ISR_EOS_Pos (3U)
Kojto 122:f9eeca106725 1177 #define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1178 #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
Kojto 122:f9eeca106725 1179 #define ADC_ISR_OVR_Pos (4U)
Kojto 122:f9eeca106725 1180 #define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1181 #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */
Kojto 122:f9eeca106725 1182 #define ADC_ISR_JEOC_Pos (5U)
Kojto 122:f9eeca106725 1183 #define ADC_ISR_JEOC_Msk (0x1U << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1184 #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */
Kojto 122:f9eeca106725 1185 #define ADC_ISR_JEOS_Pos (6U)
Kojto 122:f9eeca106725 1186 #define ADC_ISR_JEOS_Msk (0x1U << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1187 #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
Kojto 122:f9eeca106725 1188 #define ADC_ISR_AWD1_Pos (7U)
Kojto 122:f9eeca106725 1189 #define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1190 #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */
Kojto 122:f9eeca106725 1191 #define ADC_ISR_AWD2_Pos (8U)
Kojto 122:f9eeca106725 1192 #define ADC_ISR_AWD2_Msk (0x1U << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1193 #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */
Kojto 122:f9eeca106725 1194 #define ADC_ISR_AWD3_Pos (9U)
Kojto 122:f9eeca106725 1195 #define ADC_ISR_AWD3_Msk (0x1U << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1196 #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */
Kojto 122:f9eeca106725 1197 #define ADC_ISR_JQOVF_Pos (10U)
Kojto 122:f9eeca106725 1198 #define ADC_ISR_JQOVF_Msk (0x1U << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1199 #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */
Kojto 122:f9eeca106725 1200
Kojto 122:f9eeca106725 1201 /******************** Bit definition for ADC_IER register *******************/
Kojto 122:f9eeca106725 1202 #define ADC_IER_ADRDYIE_Pos (0U)
Kojto 122:f9eeca106725 1203 #define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1204 #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */
Kojto 122:f9eeca106725 1205 #define ADC_IER_EOSMPIE_Pos (1U)
Kojto 122:f9eeca106725 1206 #define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1207 #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */
Kojto 122:f9eeca106725 1208 #define ADC_IER_EOCIE_Pos (2U)
Kojto 122:f9eeca106725 1209 #define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1210 #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */
Kojto 122:f9eeca106725 1211 #define ADC_IER_EOSIE_Pos (3U)
Kojto 122:f9eeca106725 1212 #define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1213 #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
Kojto 122:f9eeca106725 1214 #define ADC_IER_OVRIE_Pos (4U)
Kojto 122:f9eeca106725 1215 #define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1216 #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */
Kojto 122:f9eeca106725 1217 #define ADC_IER_JEOCIE_Pos (5U)
Kojto 122:f9eeca106725 1218 #define ADC_IER_JEOCIE_Msk (0x1U << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1219 #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */
Kojto 122:f9eeca106725 1220 #define ADC_IER_JEOSIE_Pos (6U)
Kojto 122:f9eeca106725 1221 #define ADC_IER_JEOSIE_Msk (0x1U << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1222 #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
Kojto 122:f9eeca106725 1223 #define ADC_IER_AWD1IE_Pos (7U)
Kojto 122:f9eeca106725 1224 #define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1225 #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */
Kojto 122:f9eeca106725 1226 #define ADC_IER_AWD2IE_Pos (8U)
Kojto 122:f9eeca106725 1227 #define ADC_IER_AWD2IE_Msk (0x1U << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1228 #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */
Kojto 122:f9eeca106725 1229 #define ADC_IER_AWD3IE_Pos (9U)
Kojto 122:f9eeca106725 1230 #define ADC_IER_AWD3IE_Msk (0x1U << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1231 #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */
Kojto 122:f9eeca106725 1232 #define ADC_IER_JQOVFIE_Pos (10U)
Kojto 122:f9eeca106725 1233 #define ADC_IER_JQOVFIE_Msk (0x1U << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1234 #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */
Kojto 122:f9eeca106725 1235
Kojto 122:f9eeca106725 1236 /* Legacy defines */
Kojto 122:f9eeca106725 1237 #define ADC_IER_ADRDY (ADC_IER_ADRDYIE)
Kojto 122:f9eeca106725 1238 #define ADC_IER_EOSMP (ADC_IER_EOSMPIE)
Kojto 122:f9eeca106725 1239 #define ADC_IER_EOC (ADC_IER_EOCIE)
Kojto 122:f9eeca106725 1240 #define ADC_IER_EOS (ADC_IER_EOSIE)
Kojto 122:f9eeca106725 1241 #define ADC_IER_OVR (ADC_IER_OVRIE)
Kojto 122:f9eeca106725 1242 #define ADC_IER_JEOC (ADC_IER_JEOCIE)
Kojto 122:f9eeca106725 1243 #define ADC_IER_JEOS (ADC_IER_JEOSIE)
Kojto 122:f9eeca106725 1244 #define ADC_IER_AWD1 (ADC_IER_AWD1IE)
Kojto 122:f9eeca106725 1245 #define ADC_IER_AWD2 (ADC_IER_AWD2IE)
Kojto 122:f9eeca106725 1246 #define ADC_IER_AWD3 (ADC_IER_AWD3IE)
Kojto 122:f9eeca106725 1247 #define ADC_IER_JQOVF (ADC_IER_JQOVFIE)
Kojto 122:f9eeca106725 1248
Kojto 122:f9eeca106725 1249 /******************** Bit definition for ADC_CR register ********************/
Kojto 122:f9eeca106725 1250 #define ADC_CR_ADEN_Pos (0U)
Kojto 122:f9eeca106725 1251 #define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1252 #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */
Kojto 122:f9eeca106725 1253 #define ADC_CR_ADDIS_Pos (1U)
Kojto 122:f9eeca106725 1254 #define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1255 #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */
Kojto 122:f9eeca106725 1256 #define ADC_CR_ADSTART_Pos (2U)
Kojto 122:f9eeca106725 1257 #define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1258 #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */
Kojto 122:f9eeca106725 1259 #define ADC_CR_JADSTART_Pos (3U)
Kojto 122:f9eeca106725 1260 #define ADC_CR_JADSTART_Msk (0x1U << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1261 #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */
Kojto 122:f9eeca106725 1262 #define ADC_CR_ADSTP_Pos (4U)
Kojto 122:f9eeca106725 1263 #define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1264 #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */
Kojto 122:f9eeca106725 1265 #define ADC_CR_JADSTP_Pos (5U)
Kojto 122:f9eeca106725 1266 #define ADC_CR_JADSTP_Msk (0x1U << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1267 #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */
Kojto 122:f9eeca106725 1268 #define ADC_CR_ADVREGEN_Pos (28U)
Kojto 122:f9eeca106725 1269 #define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 1270 #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */
Kojto 122:f9eeca106725 1271 #define ADC_CR_DEEPPWD_Pos (29U)
Kojto 122:f9eeca106725 1272 #define ADC_CR_DEEPPWD_Msk (0x1U << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 1273 #define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */
Kojto 122:f9eeca106725 1274 #define ADC_CR_ADCALDIF_Pos (30U)
Kojto 122:f9eeca106725 1275 #define ADC_CR_ADCALDIF_Msk (0x1U << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 1276 #define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */
Kojto 122:f9eeca106725 1277 #define ADC_CR_ADCAL_Pos (31U)
Kojto 122:f9eeca106725 1278 #define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 1279 #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
Kojto 122:f9eeca106725 1280
Kojto 122:f9eeca106725 1281 /******************** Bit definition for ADC_CFGR register ******************/
Kojto 122:f9eeca106725 1282 #define ADC_CFGR_DMAEN_Pos (0U)
Kojto 122:f9eeca106725 1283 #define ADC_CFGR_DMAEN_Msk (0x1U << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1284 #define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */
Kojto 122:f9eeca106725 1285 #define ADC_CFGR_DMACFG_Pos (1U)
Kojto 122:f9eeca106725 1286 #define ADC_CFGR_DMACFG_Msk (0x1U << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1287 #define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */
Kojto 122:f9eeca106725 1288
Kojto 122:f9eeca106725 1289 #define ADC_CFGR_RES_Pos (3U)
Kojto 122:f9eeca106725 1290 #define ADC_CFGR_RES_Msk (0x3U << ADC_CFGR_RES_Pos) /*!< 0x00000018 */
Kojto 122:f9eeca106725 1291 #define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */
Kojto 122:f9eeca106725 1292 #define ADC_CFGR_RES_0 (0x1U << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1293 #define ADC_CFGR_RES_1 (0x2U << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1294
Kojto 122:f9eeca106725 1295 #define ADC_CFGR_ALIGN_Pos (5U)
Kojto 122:f9eeca106725 1296 #define ADC_CFGR_ALIGN_Msk (0x1U << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1297 #define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
Kojto 122:f9eeca106725 1298
Kojto 122:f9eeca106725 1299 #define ADC_CFGR_EXTSEL_Pos (6U)
Kojto 122:f9eeca106725 1300 #define ADC_CFGR_EXTSEL_Msk (0xFU << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
Kojto 122:f9eeca106725 1301 #define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */
Kojto 122:f9eeca106725 1302 #define ADC_CFGR_EXTSEL_0 (0x1U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1303 #define ADC_CFGR_EXTSEL_1 (0x2U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1304 #define ADC_CFGR_EXTSEL_2 (0x4U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1305 #define ADC_CFGR_EXTSEL_3 (0x8U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1306
Kojto 122:f9eeca106725 1307 #define ADC_CFGR_EXTEN_Pos (10U)
Kojto 122:f9eeca106725 1308 #define ADC_CFGR_EXTEN_Msk (0x3U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
Kojto 122:f9eeca106725 1309 #define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */
Kojto 122:f9eeca106725 1310 #define ADC_CFGR_EXTEN_0 (0x1U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1311 #define ADC_CFGR_EXTEN_1 (0x2U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 1312
Kojto 122:f9eeca106725 1313 #define ADC_CFGR_OVRMOD_Pos (12U)
Kojto 122:f9eeca106725 1314 #define ADC_CFGR_OVRMOD_Msk (0x1U << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 1315 #define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */
Kojto 122:f9eeca106725 1316 #define ADC_CFGR_CONT_Pos (13U)
Kojto 122:f9eeca106725 1317 #define ADC_CFGR_CONT_Msk (0x1U << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 1318 #define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */
Kojto 122:f9eeca106725 1319 #define ADC_CFGR_AUTDLY_Pos (14U)
Kojto 122:f9eeca106725 1320 #define ADC_CFGR_AUTDLY_Msk (0x1U << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 1321 #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */
Kojto 122:f9eeca106725 1322
Kojto 122:f9eeca106725 1323 #define ADC_CFGR_DISCEN_Pos (16U)
Kojto 122:f9eeca106725 1324 #define ADC_CFGR_DISCEN_Msk (0x1U << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 1325 #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
Kojto 122:f9eeca106725 1326
Kojto 122:f9eeca106725 1327 #define ADC_CFGR_DISCNUM_Pos (17U)
Kojto 122:f9eeca106725 1328 #define ADC_CFGR_DISCNUM_Msk (0x7U << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
Kojto 122:f9eeca106725 1329 #define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
Kojto 122:f9eeca106725 1330 #define ADC_CFGR_DISCNUM_0 (0x1U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 1331 #define ADC_CFGR_DISCNUM_1 (0x2U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 1332 #define ADC_CFGR_DISCNUM_2 (0x4U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 1333
Kojto 122:f9eeca106725 1334 #define ADC_CFGR_JDISCEN_Pos (20U)
Kojto 122:f9eeca106725 1335 #define ADC_CFGR_JDISCEN_Msk (0x1U << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 1336 #define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
Kojto 122:f9eeca106725 1337 #define ADC_CFGR_JQM_Pos (21U)
Kojto 122:f9eeca106725 1338 #define ADC_CFGR_JQM_Msk (0x1U << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 1339 #define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */
Kojto 122:f9eeca106725 1340 #define ADC_CFGR_AWD1SGL_Pos (22U)
Kojto 122:f9eeca106725 1341 #define ADC_CFGR_AWD1SGL_Msk (0x1U << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 1342 #define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
Kojto 122:f9eeca106725 1343 #define ADC_CFGR_AWD1EN_Pos (23U)
Kojto 122:f9eeca106725 1344 #define ADC_CFGR_AWD1EN_Msk (0x1U << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 1345 #define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
Kojto 122:f9eeca106725 1346 #define ADC_CFGR_JAWD1EN_Pos (24U)
Kojto 122:f9eeca106725 1347 #define ADC_CFGR_JAWD1EN_Msk (0x1U << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 1348 #define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
Kojto 122:f9eeca106725 1349 #define ADC_CFGR_JAUTO_Pos (25U)
Kojto 122:f9eeca106725 1350 #define ADC_CFGR_JAUTO_Msk (0x1U << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 1351 #define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
Kojto 122:f9eeca106725 1352
Kojto 122:f9eeca106725 1353 #define ADC_CFGR_AWD1CH_Pos (26U)
Kojto 122:f9eeca106725 1354 #define ADC_CFGR_AWD1CH_Msk (0x1FU << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
Kojto 122:f9eeca106725 1355 #define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
Kojto 122:f9eeca106725 1356 #define ADC_CFGR_AWD1CH_0 (0x01U << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 1357 #define ADC_CFGR_AWD1CH_1 (0x02U << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 1358 #define ADC_CFGR_AWD1CH_2 (0x04U << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 1359 #define ADC_CFGR_AWD1CH_3 (0x08U << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 1360 #define ADC_CFGR_AWD1CH_4 (0x10U << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 1361
Kojto 122:f9eeca106725 1362 #define ADC_CFGR_JQDIS_Pos (31U)
Kojto 122:f9eeca106725 1363 #define ADC_CFGR_JQDIS_Msk (0x1U << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 1364 #define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */
Kojto 122:f9eeca106725 1365
Kojto 122:f9eeca106725 1366 /******************** Bit definition for ADC_CFGR2 register *****************/
Kojto 122:f9eeca106725 1367 #define ADC_CFGR2_ROVSE_Pos (0U)
Kojto 122:f9eeca106725 1368 #define ADC_CFGR2_ROVSE_Msk (0x1U << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1369 #define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */
Kojto 122:f9eeca106725 1370 #define ADC_CFGR2_JOVSE_Pos (1U)
Kojto 122:f9eeca106725 1371 #define ADC_CFGR2_JOVSE_Msk (0x1U << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1372 #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */
Kojto 122:f9eeca106725 1373
Kojto 122:f9eeca106725 1374 #define ADC_CFGR2_OVSR_Pos (2U)
Kojto 122:f9eeca106725 1375 #define ADC_CFGR2_OVSR_Msk (0x7U << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
Kojto 122:f9eeca106725 1376 #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */
Kojto 122:f9eeca106725 1377 #define ADC_CFGR2_OVSR_0 (0x1U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1378 #define ADC_CFGR2_OVSR_1 (0x2U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1379 #define ADC_CFGR2_OVSR_2 (0x4U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1380
Kojto 122:f9eeca106725 1381 #define ADC_CFGR2_OVSS_Pos (5U)
Kojto 122:f9eeca106725 1382 #define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
Kojto 122:f9eeca106725 1383 #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */
Kojto 122:f9eeca106725 1384 #define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1385 #define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1386 #define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1387 #define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1388
Kojto 122:f9eeca106725 1389 #define ADC_CFGR2_TROVS_Pos (9U)
Kojto 122:f9eeca106725 1390 #define ADC_CFGR2_TROVS_Msk (0x1U << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1391 #define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
Kojto 122:f9eeca106725 1392 #define ADC_CFGR2_ROVSM_Pos (10U)
Kojto 122:f9eeca106725 1393 #define ADC_CFGR2_ROVSM_Msk (0x1U << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1394 #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
Kojto 122:f9eeca106725 1395
Kojto 122:f9eeca106725 1396 /******************** Bit definition for ADC_SMPR1 register *****************/
Kojto 122:f9eeca106725 1397 #define ADC_SMPR1_SMP0_Pos (0U)
Kojto 122:f9eeca106725 1398 #define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
Kojto 122:f9eeca106725 1399 #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */
Kojto 122:f9eeca106725 1400 #define ADC_SMPR1_SMP0_0 (0x1U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1401 #define ADC_SMPR1_SMP0_1 (0x2U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1402 #define ADC_SMPR1_SMP0_2 (0x4U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1403
Kojto 122:f9eeca106725 1404 #define ADC_SMPR1_SMP1_Pos (3U)
Kojto 122:f9eeca106725 1405 #define ADC_SMPR1_SMP1_Msk (0x7U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
Kojto 122:f9eeca106725 1406 #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */
Kojto 122:f9eeca106725 1407 #define ADC_SMPR1_SMP1_0 (0x1U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1408 #define ADC_SMPR1_SMP1_1 (0x2U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1409 #define ADC_SMPR1_SMP1_2 (0x4U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1410
Kojto 122:f9eeca106725 1411 #define ADC_SMPR1_SMP2_Pos (6U)
Kojto 122:f9eeca106725 1412 #define ADC_SMPR1_SMP2_Msk (0x7U << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
Kojto 122:f9eeca106725 1413 #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */
Kojto 122:f9eeca106725 1414 #define ADC_SMPR1_SMP2_0 (0x1U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1415 #define ADC_SMPR1_SMP2_1 (0x2U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1416 #define ADC_SMPR1_SMP2_2 (0x4U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1417
Kojto 122:f9eeca106725 1418 #define ADC_SMPR1_SMP3_Pos (9U)
Kojto 122:f9eeca106725 1419 #define ADC_SMPR1_SMP3_Msk (0x7U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
Kojto 122:f9eeca106725 1420 #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */
Kojto 122:f9eeca106725 1421 #define ADC_SMPR1_SMP3_0 (0x1U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1422 #define ADC_SMPR1_SMP3_1 (0x2U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1423 #define ADC_SMPR1_SMP3_2 (0x4U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 1424
Kojto 122:f9eeca106725 1425 #define ADC_SMPR1_SMP4_Pos (12U)
Kojto 122:f9eeca106725 1426 #define ADC_SMPR1_SMP4_Msk (0x7U << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
Kojto 122:f9eeca106725 1427 #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */
Kojto 122:f9eeca106725 1428 #define ADC_SMPR1_SMP4_0 (0x1U << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 1429 #define ADC_SMPR1_SMP4_1 (0x2U << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 1430 #define ADC_SMPR1_SMP4_2 (0x4U << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 1431
Kojto 122:f9eeca106725 1432 #define ADC_SMPR1_SMP5_Pos (15U)
Kojto 122:f9eeca106725 1433 #define ADC_SMPR1_SMP5_Msk (0x7U << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
Kojto 122:f9eeca106725 1434 #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */
Kojto 122:f9eeca106725 1435 #define ADC_SMPR1_SMP5_0 (0x1U << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 1436 #define ADC_SMPR1_SMP5_1 (0x2U << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 1437 #define ADC_SMPR1_SMP5_2 (0x4U << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 1438
Kojto 122:f9eeca106725 1439 #define ADC_SMPR1_SMP6_Pos (18U)
Kojto 122:f9eeca106725 1440 #define ADC_SMPR1_SMP6_Msk (0x7U << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
Kojto 122:f9eeca106725 1441 #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */
Kojto 122:f9eeca106725 1442 #define ADC_SMPR1_SMP6_0 (0x1U << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 1443 #define ADC_SMPR1_SMP6_1 (0x2U << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 1444 #define ADC_SMPR1_SMP6_2 (0x4U << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 1445
Kojto 122:f9eeca106725 1446 #define ADC_SMPR1_SMP7_Pos (21U)
Kojto 122:f9eeca106725 1447 #define ADC_SMPR1_SMP7_Msk (0x7U << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
Kojto 122:f9eeca106725 1448 #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */
Kojto 122:f9eeca106725 1449 #define ADC_SMPR1_SMP7_0 (0x1U << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 1450 #define ADC_SMPR1_SMP7_1 (0x2U << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 1451 #define ADC_SMPR1_SMP7_2 (0x4U << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 1452
Kojto 122:f9eeca106725 1453 #define ADC_SMPR1_SMP8_Pos (24U)
Kojto 122:f9eeca106725 1454 #define ADC_SMPR1_SMP8_Msk (0x7U << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
Kojto 122:f9eeca106725 1455 #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */
Kojto 122:f9eeca106725 1456 #define ADC_SMPR1_SMP8_0 (0x1U << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 1457 #define ADC_SMPR1_SMP8_1 (0x2U << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 1458 #define ADC_SMPR1_SMP8_2 (0x4U << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 1459
Kojto 122:f9eeca106725 1460 #define ADC_SMPR1_SMP9_Pos (27U)
Kojto 122:f9eeca106725 1461 #define ADC_SMPR1_SMP9_Msk (0x7U << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
Kojto 122:f9eeca106725 1462 #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */
Kojto 122:f9eeca106725 1463 #define ADC_SMPR1_SMP9_0 (0x1U << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 1464 #define ADC_SMPR1_SMP9_1 (0x2U << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 1465 #define ADC_SMPR1_SMP9_2 (0x4U << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 1466
Kojto 122:f9eeca106725 1467 /******************** Bit definition for ADC_SMPR2 register *****************/
Kojto 122:f9eeca106725 1468 #define ADC_SMPR2_SMP10_Pos (0U)
Kojto 122:f9eeca106725 1469 #define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
Kojto 122:f9eeca106725 1470 #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */
Kojto 122:f9eeca106725 1471 #define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1472 #define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1473 #define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1474
Kojto 122:f9eeca106725 1475 #define ADC_SMPR2_SMP11_Pos (3U)
Kojto 122:f9eeca106725 1476 #define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
Kojto 122:f9eeca106725 1477 #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */
Kojto 122:f9eeca106725 1478 #define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1479 #define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1480 #define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1481
Kojto 122:f9eeca106725 1482 #define ADC_SMPR2_SMP12_Pos (6U)
Kojto 122:f9eeca106725 1483 #define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
Kojto 122:f9eeca106725 1484 #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */
Kojto 122:f9eeca106725 1485 #define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1486 #define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1487 #define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1488
Kojto 122:f9eeca106725 1489 #define ADC_SMPR2_SMP13_Pos (9U)
Kojto 122:f9eeca106725 1490 #define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
Kojto 122:f9eeca106725 1491 #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */
Kojto 122:f9eeca106725 1492 #define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1493 #define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1494 #define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 1495
Kojto 122:f9eeca106725 1496 #define ADC_SMPR2_SMP14_Pos (12U)
Kojto 122:f9eeca106725 1497 #define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
Kojto 122:f9eeca106725 1498 #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */
Kojto 122:f9eeca106725 1499 #define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 1500 #define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 1501 #define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 1502
Kojto 122:f9eeca106725 1503 #define ADC_SMPR2_SMP15_Pos (15U)
Kojto 122:f9eeca106725 1504 #define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
Kojto 122:f9eeca106725 1505 #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */
Kojto 122:f9eeca106725 1506 #define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 1507 #define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 1508 #define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 1509
Kojto 122:f9eeca106725 1510 #define ADC_SMPR2_SMP16_Pos (18U)
Kojto 122:f9eeca106725 1511 #define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
Kojto 122:f9eeca106725 1512 #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */
Kojto 122:f9eeca106725 1513 #define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 1514 #define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 1515 #define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 1516
Kojto 122:f9eeca106725 1517 #define ADC_SMPR2_SMP17_Pos (21U)
Kojto 122:f9eeca106725 1518 #define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
Kojto 122:f9eeca106725 1519 #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */
Kojto 122:f9eeca106725 1520 #define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 1521 #define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 1522 #define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 1523
Kojto 122:f9eeca106725 1524 #define ADC_SMPR2_SMP18_Pos (24U)
Kojto 122:f9eeca106725 1525 #define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
Kojto 122:f9eeca106725 1526 #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */
Kojto 122:f9eeca106725 1527 #define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 1528 #define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 1529 #define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 1530
Kojto 122:f9eeca106725 1531 /******************** Bit definition for ADC_TR1 register *******************/
Kojto 122:f9eeca106725 1532 #define ADC_TR1_LT1_Pos (0U)
Kojto 122:f9eeca106725 1533 #define ADC_TR1_LT1_Msk (0xFFFU << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */
Kojto 122:f9eeca106725 1534 #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
Kojto 122:f9eeca106725 1535 #define ADC_TR1_LT1_0 (0x001U << ADC_TR1_LT1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1536 #define ADC_TR1_LT1_1 (0x002U << ADC_TR1_LT1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1537 #define ADC_TR1_LT1_2 (0x004U << ADC_TR1_LT1_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1538 #define ADC_TR1_LT1_3 (0x008U << ADC_TR1_LT1_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1539 #define ADC_TR1_LT1_4 (0x010U << ADC_TR1_LT1_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1540 #define ADC_TR1_LT1_5 (0x020U << ADC_TR1_LT1_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1541 #define ADC_TR1_LT1_6 (0x040U << ADC_TR1_LT1_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1542 #define ADC_TR1_LT1_7 (0x080U << ADC_TR1_LT1_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1543 #define ADC_TR1_LT1_8 (0x100U << ADC_TR1_LT1_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1544 #define ADC_TR1_LT1_9 (0x200U << ADC_TR1_LT1_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1545 #define ADC_TR1_LT1_10 (0x400U << ADC_TR1_LT1_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1546 #define ADC_TR1_LT1_11 (0x800U << ADC_TR1_LT1_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 1547
Kojto 122:f9eeca106725 1548 #define ADC_TR1_HT1_Pos (16U)
Kojto 122:f9eeca106725 1549 #define ADC_TR1_HT1_Msk (0xFFFU << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */
Kojto 122:f9eeca106725 1550 #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */
Kojto 122:f9eeca106725 1551 #define ADC_TR1_HT1_0 (0x001U << ADC_TR1_HT1_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 1552 #define ADC_TR1_HT1_1 (0x002U << ADC_TR1_HT1_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 1553 #define ADC_TR1_HT1_2 (0x004U << ADC_TR1_HT1_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 1554 #define ADC_TR1_HT1_3 (0x008U << ADC_TR1_HT1_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 1555 #define ADC_TR1_HT1_4 (0x010U << ADC_TR1_HT1_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 1556 #define ADC_TR1_HT1_5 (0x020U << ADC_TR1_HT1_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 1557 #define ADC_TR1_HT1_6 (0x040U << ADC_TR1_HT1_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 1558 #define ADC_TR1_HT1_7 (0x080U << ADC_TR1_HT1_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 1559 #define ADC_TR1_HT1_8 (0x100U << ADC_TR1_HT1_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 1560 #define ADC_TR1_HT1_9 (0x200U << ADC_TR1_HT1_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 1561 #define ADC_TR1_HT1_10 (0x400U << ADC_TR1_HT1_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 1562 #define ADC_TR1_HT1_11 (0x800U << ADC_TR1_HT1_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 1563
Kojto 122:f9eeca106725 1564 /******************** Bit definition for ADC_TR2 register *******************/
Kojto 122:f9eeca106725 1565 #define ADC_TR2_LT2_Pos (0U)
Kojto 122:f9eeca106725 1566 #define ADC_TR2_LT2_Msk (0xFFU << ADC_TR2_LT2_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 1567 #define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */
Kojto 122:f9eeca106725 1568 #define ADC_TR2_LT2_0 (0x01U << ADC_TR2_LT2_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1569 #define ADC_TR2_LT2_1 (0x02U << ADC_TR2_LT2_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1570 #define ADC_TR2_LT2_2 (0x04U << ADC_TR2_LT2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1571 #define ADC_TR2_LT2_3 (0x08U << ADC_TR2_LT2_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1572 #define ADC_TR2_LT2_4 (0x10U << ADC_TR2_LT2_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1573 #define ADC_TR2_LT2_5 (0x20U << ADC_TR2_LT2_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1574 #define ADC_TR2_LT2_6 (0x40U << ADC_TR2_LT2_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1575 #define ADC_TR2_LT2_7 (0x80U << ADC_TR2_LT2_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1576
Kojto 122:f9eeca106725 1577 #define ADC_TR2_HT2_Pos (16U)
Kojto 122:f9eeca106725 1578 #define ADC_TR2_HT2_Msk (0xFFU << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 1579 #define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */
Kojto 122:f9eeca106725 1580 #define ADC_TR2_HT2_0 (0x01U << ADC_TR2_HT2_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 1581 #define ADC_TR2_HT2_1 (0x02U << ADC_TR2_HT2_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 1582 #define ADC_TR2_HT2_2 (0x04U << ADC_TR2_HT2_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 1583 #define ADC_TR2_HT2_3 (0x08U << ADC_TR2_HT2_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 1584 #define ADC_TR2_HT2_4 (0x10U << ADC_TR2_HT2_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 1585 #define ADC_TR2_HT2_5 (0x20U << ADC_TR2_HT2_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 1586 #define ADC_TR2_HT2_6 (0x40U << ADC_TR2_HT2_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 1587 #define ADC_TR2_HT2_7 (0x80U << ADC_TR2_HT2_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 1588
Kojto 122:f9eeca106725 1589 /******************** Bit definition for ADC_TR3 register *******************/
Kojto 122:f9eeca106725 1590 #define ADC_TR3_LT3_Pos (0U)
Kojto 122:f9eeca106725 1591 #define ADC_TR3_LT3_Msk (0xFFU << ADC_TR3_LT3_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 1592 #define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */
Kojto 122:f9eeca106725 1593 #define ADC_TR3_LT3_0 (0x01U << ADC_TR3_LT3_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1594 #define ADC_TR3_LT3_1 (0x02U << ADC_TR3_LT3_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1595 #define ADC_TR3_LT3_2 (0x04U << ADC_TR3_LT3_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1596 #define ADC_TR3_LT3_3 (0x08U << ADC_TR3_LT3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1597 #define ADC_TR3_LT3_4 (0x10U << ADC_TR3_LT3_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1598 #define ADC_TR3_LT3_5 (0x20U << ADC_TR3_LT3_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1599 #define ADC_TR3_LT3_6 (0x40U << ADC_TR3_LT3_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1600 #define ADC_TR3_LT3_7 (0x80U << ADC_TR3_LT3_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1601
Kojto 122:f9eeca106725 1602 #define ADC_TR3_HT3_Pos (16U)
Kojto 122:f9eeca106725 1603 #define ADC_TR3_HT3_Msk (0xFFU << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 1604 #define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */
Kojto 122:f9eeca106725 1605 #define ADC_TR3_HT3_0 (0x01U << ADC_TR3_HT3_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 1606 #define ADC_TR3_HT3_1 (0x02U << ADC_TR3_HT3_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 1607 #define ADC_TR3_HT3_2 (0x04U << ADC_TR3_HT3_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 1608 #define ADC_TR3_HT3_3 (0x08U << ADC_TR3_HT3_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 1609 #define ADC_TR3_HT3_4 (0x10U << ADC_TR3_HT3_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 1610 #define ADC_TR3_HT3_5 (0x20U << ADC_TR3_HT3_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 1611 #define ADC_TR3_HT3_6 (0x40U << ADC_TR3_HT3_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 1612 #define ADC_TR3_HT3_7 (0x80U << ADC_TR3_HT3_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 1613
Kojto 122:f9eeca106725 1614 /******************** Bit definition for ADC_SQR1 register ******************/
Kojto 122:f9eeca106725 1615 #define ADC_SQR1_L_Pos (0U)
Kojto 122:f9eeca106725 1616 #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 1617 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
Kojto 122:f9eeca106725 1618 #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1619 #define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1620 #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1621 #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1622
Kojto 122:f9eeca106725 1623 #define ADC_SQR1_SQ1_Pos (6U)
Kojto 122:f9eeca106725 1624 #define ADC_SQR1_SQ1_Msk (0x1FU << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
Kojto 122:f9eeca106725 1625 #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
Kojto 122:f9eeca106725 1626 #define ADC_SQR1_SQ1_0 (0x01U << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1627 #define ADC_SQR1_SQ1_1 (0x02U << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1628 #define ADC_SQR1_SQ1_2 (0x04U << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1629 #define ADC_SQR1_SQ1_3 (0x08U << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1630 #define ADC_SQR1_SQ1_4 (0x10U << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1631
Kojto 122:f9eeca106725 1632 #define ADC_SQR1_SQ2_Pos (12U)
Kojto 122:f9eeca106725 1633 #define ADC_SQR1_SQ2_Msk (0x1FU << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
Kojto 122:f9eeca106725 1634 #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
Kojto 122:f9eeca106725 1635 #define ADC_SQR1_SQ2_0 (0x01U << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 1636 #define ADC_SQR1_SQ2_1 (0x02U << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 1637 #define ADC_SQR1_SQ2_2 (0x04U << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 1638 #define ADC_SQR1_SQ2_3 (0x08U << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 1639 #define ADC_SQR1_SQ2_4 (0x10U << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 1640
Kojto 122:f9eeca106725 1641 #define ADC_SQR1_SQ3_Pos (18U)
Kojto 122:f9eeca106725 1642 #define ADC_SQR1_SQ3_Msk (0x1FU << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
Kojto 122:f9eeca106725 1643 #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
Kojto 122:f9eeca106725 1644 #define ADC_SQR1_SQ3_0 (0x01U << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 1645 #define ADC_SQR1_SQ3_1 (0x02U << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 1646 #define ADC_SQR1_SQ3_2 (0x04U << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 1647 #define ADC_SQR1_SQ3_3 (0x08U << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 1648 #define ADC_SQR1_SQ3_4 (0x10U << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 1649
Kojto 122:f9eeca106725 1650 #define ADC_SQR1_SQ4_Pos (24U)
Kojto 122:f9eeca106725 1651 #define ADC_SQR1_SQ4_Msk (0x1FU << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
Kojto 122:f9eeca106725 1652 #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
Kojto 122:f9eeca106725 1653 #define ADC_SQR1_SQ4_0 (0x01U << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 1654 #define ADC_SQR1_SQ4_1 (0x02U << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 1655 #define ADC_SQR1_SQ4_2 (0x04U << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 1656 #define ADC_SQR1_SQ4_3 (0x08U << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 1657 #define ADC_SQR1_SQ4_4 (0x10U << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 1658
Kojto 122:f9eeca106725 1659 /******************** Bit definition for ADC_SQR2 register ******************/
Kojto 122:f9eeca106725 1660 #define ADC_SQR2_SQ5_Pos (0U)
Kojto 122:f9eeca106725 1661 #define ADC_SQR2_SQ5_Msk (0x1FU << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
Kojto 122:f9eeca106725 1662 #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
Kojto 122:f9eeca106725 1663 #define ADC_SQR2_SQ5_0 (0x01U << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1664 #define ADC_SQR2_SQ5_1 (0x02U << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1665 #define ADC_SQR2_SQ5_2 (0x04U << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1666 #define ADC_SQR2_SQ5_3 (0x08U << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1667 #define ADC_SQR2_SQ5_4 (0x10U << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1668
Kojto 122:f9eeca106725 1669 #define ADC_SQR2_SQ6_Pos (6U)
Kojto 122:f9eeca106725 1670 #define ADC_SQR2_SQ6_Msk (0x1FU << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
Kojto 122:f9eeca106725 1671 #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
Kojto 122:f9eeca106725 1672 #define ADC_SQR2_SQ6_0 (0x01U << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1673 #define ADC_SQR2_SQ6_1 (0x02U << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1674 #define ADC_SQR2_SQ6_2 (0x04U << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1675 #define ADC_SQR2_SQ6_3 (0x08U << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1676 #define ADC_SQR2_SQ6_4 (0x10U << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1677
Kojto 122:f9eeca106725 1678 #define ADC_SQR2_SQ7_Pos (12U)
Kojto 122:f9eeca106725 1679 #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
Kojto 122:f9eeca106725 1680 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
Kojto 122:f9eeca106725 1681 #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 1682 #define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 1683 #define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 1684 #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 1685 #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 1686
Kojto 122:f9eeca106725 1687 #define ADC_SQR2_SQ8_Pos (18U)
Kojto 122:f9eeca106725 1688 #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
Kojto 122:f9eeca106725 1689 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
Kojto 122:f9eeca106725 1690 #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 1691 #define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 1692 #define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 1693 #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 1694 #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 1695
Kojto 122:f9eeca106725 1696 #define ADC_SQR2_SQ9_Pos (24U)
Kojto 122:f9eeca106725 1697 #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
Kojto 122:f9eeca106725 1698 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
Kojto 122:f9eeca106725 1699 #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 1700 #define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 1701 #define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 1702 #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 1703 #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 1704
Kojto 122:f9eeca106725 1705 /******************** Bit definition for ADC_SQR3 register ******************/
Kojto 122:f9eeca106725 1706 #define ADC_SQR3_SQ10_Pos (0U)
Kojto 122:f9eeca106725 1707 #define ADC_SQR3_SQ10_Msk (0x1FU << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
Kojto 122:f9eeca106725 1708 #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
Kojto 122:f9eeca106725 1709 #define ADC_SQR3_SQ10_0 (0x01U << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1710 #define ADC_SQR3_SQ10_1 (0x02U << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1711 #define ADC_SQR3_SQ10_2 (0x04U << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1712 #define ADC_SQR3_SQ10_3 (0x08U << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1713 #define ADC_SQR3_SQ10_4 (0x10U << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1714
Kojto 122:f9eeca106725 1715 #define ADC_SQR3_SQ11_Pos (6U)
Kojto 122:f9eeca106725 1716 #define ADC_SQR3_SQ11_Msk (0x1FU << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
Kojto 122:f9eeca106725 1717 #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */
Kojto 122:f9eeca106725 1718 #define ADC_SQR3_SQ11_0 (0x01U << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1719 #define ADC_SQR3_SQ11_1 (0x02U << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1720 #define ADC_SQR3_SQ11_2 (0x04U << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1721 #define ADC_SQR3_SQ11_3 (0x08U << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1722 #define ADC_SQR3_SQ11_4 (0x10U << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1723
Kojto 122:f9eeca106725 1724 #define ADC_SQR3_SQ12_Pos (12U)
Kojto 122:f9eeca106725 1725 #define ADC_SQR3_SQ12_Msk (0x1FU << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
Kojto 122:f9eeca106725 1726 #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
Kojto 122:f9eeca106725 1727 #define ADC_SQR3_SQ12_0 (0x01U << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 1728 #define ADC_SQR3_SQ12_1 (0x02U << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 1729 #define ADC_SQR3_SQ12_2 (0x04U << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 1730 #define ADC_SQR3_SQ12_3 (0x08U << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 1731 #define ADC_SQR3_SQ12_4 (0x10U << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 1732
Kojto 122:f9eeca106725 1733 #define ADC_SQR3_SQ13_Pos (18U)
Kojto 122:f9eeca106725 1734 #define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
Kojto 122:f9eeca106725 1735 #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
Kojto 122:f9eeca106725 1736 #define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 1737 #define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 1738 #define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 1739 #define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 1740 #define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 1741
Kojto 122:f9eeca106725 1742 #define ADC_SQR3_SQ14_Pos (24U)
Kojto 122:f9eeca106725 1743 #define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
Kojto 122:f9eeca106725 1744 #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
Kojto 122:f9eeca106725 1745 #define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 1746 #define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 1747 #define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 1748 #define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 1749 #define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 1750
Kojto 122:f9eeca106725 1751 /******************** Bit definition for ADC_SQR4 register ******************/
Kojto 122:f9eeca106725 1752 #define ADC_SQR4_SQ15_Pos (0U)
Kojto 122:f9eeca106725 1753 #define ADC_SQR4_SQ15_Msk (0x1FU << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
Kojto 122:f9eeca106725 1754 #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
Kojto 122:f9eeca106725 1755 #define ADC_SQR4_SQ15_0 (0x01U << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1756 #define ADC_SQR4_SQ15_1 (0x02U << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1757 #define ADC_SQR4_SQ15_2 (0x04U << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1758 #define ADC_SQR4_SQ15_3 (0x08U << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1759 #define ADC_SQR4_SQ15_4 (0x10U << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1760
Kojto 122:f9eeca106725 1761 #define ADC_SQR4_SQ16_Pos (6U)
Kojto 122:f9eeca106725 1762 #define ADC_SQR4_SQ16_Msk (0x1FU << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
Kojto 122:f9eeca106725 1763 #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
Kojto 122:f9eeca106725 1764 #define ADC_SQR4_SQ16_0 (0x01U << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1765 #define ADC_SQR4_SQ16_1 (0x02U << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1766 #define ADC_SQR4_SQ16_2 (0x04U << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1767 #define ADC_SQR4_SQ16_3 (0x08U << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1768 #define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1769
Kojto 122:f9eeca106725 1770 /******************** Bit definition for ADC_DR register ********************/
Kojto 122:f9eeca106725 1771 #define ADC_DR_RDATA_Pos (0U)
Kojto 122:f9eeca106725 1772 #define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 1773 #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */
Kojto 122:f9eeca106725 1774 #define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1775 #define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1776 #define ADC_DR_RDATA_2 (0x0004U << ADC_DR_RDATA_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1777 #define ADC_DR_RDATA_3 (0x0008U << ADC_DR_RDATA_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1778 #define ADC_DR_RDATA_4 (0x0010U << ADC_DR_RDATA_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1779 #define ADC_DR_RDATA_5 (0x0020U << ADC_DR_RDATA_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1780 #define ADC_DR_RDATA_6 (0x0040U << ADC_DR_RDATA_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1781 #define ADC_DR_RDATA_7 (0x0080U << ADC_DR_RDATA_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1782 #define ADC_DR_RDATA_8 (0x0100U << ADC_DR_RDATA_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1783 #define ADC_DR_RDATA_9 (0x0200U << ADC_DR_RDATA_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1784 #define ADC_DR_RDATA_10 (0x0400U << ADC_DR_RDATA_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1785 #define ADC_DR_RDATA_11 (0x0800U << ADC_DR_RDATA_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 1786 #define ADC_DR_RDATA_12 (0x1000U << ADC_DR_RDATA_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 1787 #define ADC_DR_RDATA_13 (0x2000U << ADC_DR_RDATA_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 1788 #define ADC_DR_RDATA_14 (0x4000U << ADC_DR_RDATA_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 1789 #define ADC_DR_RDATA_15 (0x8000U << ADC_DR_RDATA_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 1790
Kojto 122:f9eeca106725 1791 /******************** Bit definition for ADC_JSQR register ******************/
Kojto 122:f9eeca106725 1792 #define ADC_JSQR_JL_Pos (0U)
Kojto 122:f9eeca106725 1793 #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 1794 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
Kojto 122:f9eeca106725 1795 #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1796 #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1797
Kojto 122:f9eeca106725 1798 #define ADC_JSQR_JEXTSEL_Pos (2U)
Kojto 122:f9eeca106725 1799 #define ADC_JSQR_JEXTSEL_Msk (0xFU << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */
Kojto 122:f9eeca106725 1800 #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */
Kojto 122:f9eeca106725 1801 #define ADC_JSQR_JEXTSEL_0 (0x1U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1802 #define ADC_JSQR_JEXTSEL_1 (0x2U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1803 #define ADC_JSQR_JEXTSEL_2 (0x4U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1804 #define ADC_JSQR_JEXTSEL_3 (0x8U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1805
Kojto 122:f9eeca106725 1806 #define ADC_JSQR_JEXTEN_Pos (6U)
Kojto 122:f9eeca106725 1807 #define ADC_JSQR_JEXTEN_Msk (0x3U << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */
Kojto 122:f9eeca106725 1808 #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */
Kojto 122:f9eeca106725 1809 #define ADC_JSQR_JEXTEN_0 (0x1U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1810 #define ADC_JSQR_JEXTEN_1 (0x2U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1811
Kojto 122:f9eeca106725 1812 #define ADC_JSQR_JSQ1_Pos (8U)
Kojto 122:f9eeca106725 1813 #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */
Kojto 122:f9eeca106725 1814 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
Kojto 122:f9eeca106725 1815 #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1816 #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1817 #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1818 #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 1819 #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 1820
Kojto 122:f9eeca106725 1821 #define ADC_JSQR_JSQ2_Pos (14U)
Kojto 122:f9eeca106725 1822 #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */
Kojto 122:f9eeca106725 1823 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
Kojto 122:f9eeca106725 1824 #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 1825 #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 1826 #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 1827 #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 1828 #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 1829
Kojto 122:f9eeca106725 1830 #define ADC_JSQR_JSQ3_Pos (20U)
Kojto 122:f9eeca106725 1831 #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */
Kojto 122:f9eeca106725 1832 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
Kojto 122:f9eeca106725 1833 #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 1834 #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 1835 #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 1836 #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 1837 #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 1838
Kojto 122:f9eeca106725 1839 #define ADC_JSQR_JSQ4_Pos (26U)
Kojto 122:f9eeca106725 1840 #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */
Kojto 122:f9eeca106725 1841 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
Kojto 122:f9eeca106725 1842 #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 1843 #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 1844 #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 1845 #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 1846 #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 1847
Kojto 122:f9eeca106725 1848
Kojto 122:f9eeca106725 1849 /******************** Bit definition for ADC_OFR1 register ******************/
Kojto 122:f9eeca106725 1850 #define ADC_OFR1_OFFSET1_Pos (0U)
Kojto 122:f9eeca106725 1851 #define ADC_OFR1_OFFSET1_Msk (0xFFFU << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */
Kojto 122:f9eeca106725 1852 #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */
Kojto 122:f9eeca106725 1853 #define ADC_OFR1_OFFSET1_0 (0x001U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1854 #define ADC_OFR1_OFFSET1_1 (0x002U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1855 #define ADC_OFR1_OFFSET1_2 (0x004U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1856 #define ADC_OFR1_OFFSET1_3 (0x008U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1857 #define ADC_OFR1_OFFSET1_4 (0x010U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1858 #define ADC_OFR1_OFFSET1_5 (0x020U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1859 #define ADC_OFR1_OFFSET1_6 (0x040U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1860 #define ADC_OFR1_OFFSET1_7 (0x080U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1861 #define ADC_OFR1_OFFSET1_8 (0x100U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1862 #define ADC_OFR1_OFFSET1_9 (0x200U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1863 #define ADC_OFR1_OFFSET1_10 (0x400U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1864 #define ADC_OFR1_OFFSET1_11 (0x800U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 1865
Kojto 122:f9eeca106725 1866 #define ADC_OFR1_OFFSET1_CH_Pos (26U)
Kojto 122:f9eeca106725 1867 #define ADC_OFR1_OFFSET1_CH_Msk (0x1FU << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
Kojto 122:f9eeca106725 1868 #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */
Kojto 122:f9eeca106725 1869 #define ADC_OFR1_OFFSET1_CH_0 (0x01U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 1870 #define ADC_OFR1_OFFSET1_CH_1 (0x02U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 1871 #define ADC_OFR1_OFFSET1_CH_2 (0x04U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 1872 #define ADC_OFR1_OFFSET1_CH_3 (0x08U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 1873 #define ADC_OFR1_OFFSET1_CH_4 (0x10U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 1874
Kojto 122:f9eeca106725 1875 #define ADC_OFR1_OFFSET1_EN_Pos (31U)
Kojto 122:f9eeca106725 1876 #define ADC_OFR1_OFFSET1_EN_Msk (0x1U << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 1877 #define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */
Kojto 122:f9eeca106725 1878
Kojto 122:f9eeca106725 1879 /******************** Bit definition for ADC_OFR2 register ******************/
Kojto 122:f9eeca106725 1880 #define ADC_OFR2_OFFSET2_Pos (0U)
Kojto 122:f9eeca106725 1881 #define ADC_OFR2_OFFSET2_Msk (0xFFFU << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */
Kojto 122:f9eeca106725 1882 #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */
Kojto 122:f9eeca106725 1883 #define ADC_OFR2_OFFSET2_0 (0x001U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1884 #define ADC_OFR2_OFFSET2_1 (0x002U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1885 #define ADC_OFR2_OFFSET2_2 (0x004U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1886 #define ADC_OFR2_OFFSET2_3 (0x008U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1887 #define ADC_OFR2_OFFSET2_4 (0x010U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1888 #define ADC_OFR2_OFFSET2_5 (0x020U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1889 #define ADC_OFR2_OFFSET2_6 (0x040U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1890 #define ADC_OFR2_OFFSET2_7 (0x080U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1891 #define ADC_OFR2_OFFSET2_8 (0x100U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1892 #define ADC_OFR2_OFFSET2_9 (0x200U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1893 #define ADC_OFR2_OFFSET2_10 (0x400U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1894 #define ADC_OFR2_OFFSET2_11 (0x800U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 1895
Kojto 122:f9eeca106725 1896 #define ADC_OFR2_OFFSET2_CH_Pos (26U)
Kojto 122:f9eeca106725 1897 #define ADC_OFR2_OFFSET2_CH_Msk (0x1FU << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
Kojto 122:f9eeca106725 1898 #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */
Kojto 122:f9eeca106725 1899 #define ADC_OFR2_OFFSET2_CH_0 (0x01U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 1900 #define ADC_OFR2_OFFSET2_CH_1 (0x02U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 1901 #define ADC_OFR2_OFFSET2_CH_2 (0x04U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 1902 #define ADC_OFR2_OFFSET2_CH_3 (0x08U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 1903 #define ADC_OFR2_OFFSET2_CH_4 (0x10U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 1904
Kojto 122:f9eeca106725 1905 #define ADC_OFR2_OFFSET2_EN_Pos (31U)
Kojto 122:f9eeca106725 1906 #define ADC_OFR2_OFFSET2_EN_Msk (0x1U << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 1907 #define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */
Kojto 122:f9eeca106725 1908
Kojto 122:f9eeca106725 1909 /******************** Bit definition for ADC_OFR3 register ******************/
Kojto 122:f9eeca106725 1910 #define ADC_OFR3_OFFSET3_Pos (0U)
Kojto 122:f9eeca106725 1911 #define ADC_OFR3_OFFSET3_Msk (0xFFFU << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */
Kojto 122:f9eeca106725 1912 #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */
Kojto 122:f9eeca106725 1913 #define ADC_OFR3_OFFSET3_0 (0x001U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1914 #define ADC_OFR3_OFFSET3_1 (0x002U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1915 #define ADC_OFR3_OFFSET3_2 (0x004U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1916 #define ADC_OFR3_OFFSET3_3 (0x008U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1917 #define ADC_OFR3_OFFSET3_4 (0x010U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1918 #define ADC_OFR3_OFFSET3_5 (0x020U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1919 #define ADC_OFR3_OFFSET3_6 (0x040U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1920 #define ADC_OFR3_OFFSET3_7 (0x080U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1921 #define ADC_OFR3_OFFSET3_8 (0x100U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1922 #define ADC_OFR3_OFFSET3_9 (0x200U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1923 #define ADC_OFR3_OFFSET3_10 (0x400U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1924 #define ADC_OFR3_OFFSET3_11 (0x800U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 1925
Kojto 122:f9eeca106725 1926 #define ADC_OFR3_OFFSET3_CH_Pos (26U)
Kojto 122:f9eeca106725 1927 #define ADC_OFR3_OFFSET3_CH_Msk (0x1FU << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
Kojto 122:f9eeca106725 1928 #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */
Kojto 122:f9eeca106725 1929 #define ADC_OFR3_OFFSET3_CH_0 (0x01U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 1930 #define ADC_OFR3_OFFSET3_CH_1 (0x02U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 1931 #define ADC_OFR3_OFFSET3_CH_2 (0x04U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 1932 #define ADC_OFR3_OFFSET3_CH_3 (0x08U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 1933 #define ADC_OFR3_OFFSET3_CH_4 (0x10U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 1934
Kojto 122:f9eeca106725 1935 #define ADC_OFR3_OFFSET3_EN_Pos (31U)
Kojto 122:f9eeca106725 1936 #define ADC_OFR3_OFFSET3_EN_Msk (0x1U << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 1937 #define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */
Kojto 122:f9eeca106725 1938
Kojto 122:f9eeca106725 1939 /******************** Bit definition for ADC_OFR4 register ******************/
Kojto 122:f9eeca106725 1940 #define ADC_OFR4_OFFSET4_Pos (0U)
Kojto 122:f9eeca106725 1941 #define ADC_OFR4_OFFSET4_Msk (0xFFFU << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */
Kojto 122:f9eeca106725 1942 #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */
Kojto 122:f9eeca106725 1943 #define ADC_OFR4_OFFSET4_0 (0x001U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1944 #define ADC_OFR4_OFFSET4_1 (0x002U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1945 #define ADC_OFR4_OFFSET4_2 (0x004U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1946 #define ADC_OFR4_OFFSET4_3 (0x008U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1947 #define ADC_OFR4_OFFSET4_4 (0x010U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1948 #define ADC_OFR4_OFFSET4_5 (0x020U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1949 #define ADC_OFR4_OFFSET4_6 (0x040U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1950 #define ADC_OFR4_OFFSET4_7 (0x080U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1951 #define ADC_OFR4_OFFSET4_8 (0x100U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1952 #define ADC_OFR4_OFFSET4_9 (0x200U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1953 #define ADC_OFR4_OFFSET4_10 (0x400U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1954 #define ADC_OFR4_OFFSET4_11 (0x800U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 1955
Kojto 122:f9eeca106725 1956 #define ADC_OFR4_OFFSET4_CH_Pos (26U)
Kojto 122:f9eeca106725 1957 #define ADC_OFR4_OFFSET4_CH_Msk (0x1FU << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
Kojto 122:f9eeca106725 1958 #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */
Kojto 122:f9eeca106725 1959 #define ADC_OFR4_OFFSET4_CH_0 (0x01U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 1960 #define ADC_OFR4_OFFSET4_CH_1 (0x02U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 1961 #define ADC_OFR4_OFFSET4_CH_2 (0x04U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 1962 #define ADC_OFR4_OFFSET4_CH_3 (0x08U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 1963 #define ADC_OFR4_OFFSET4_CH_4 (0x10U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 1964
Kojto 122:f9eeca106725 1965 #define ADC_OFR4_OFFSET4_EN_Pos (31U)
Kojto 122:f9eeca106725 1966 #define ADC_OFR4_OFFSET4_EN_Msk (0x1U << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 1967 #define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */
Kojto 122:f9eeca106725 1968
Kojto 122:f9eeca106725 1969 /******************** Bit definition for ADC_JDR1 register ******************/
Kojto 122:f9eeca106725 1970 #define ADC_JDR1_JDATA_Pos (0U)
Kojto 122:f9eeca106725 1971 #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 1972 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
Kojto 122:f9eeca106725 1973 #define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1974 #define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1975 #define ADC_JDR1_JDATA_2 (0x0004U << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1976 #define ADC_JDR1_JDATA_3 (0x0008U << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1977 #define ADC_JDR1_JDATA_4 (0x0010U << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1978 #define ADC_JDR1_JDATA_5 (0x0020U << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1979 #define ADC_JDR1_JDATA_6 (0x0040U << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1980 #define ADC_JDR1_JDATA_7 (0x0080U << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1981 #define ADC_JDR1_JDATA_8 (0x0100U << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1982 #define ADC_JDR1_JDATA_9 (0x0200U << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1983 #define ADC_JDR1_JDATA_10 (0x0400U << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1984 #define ADC_JDR1_JDATA_11 (0x0800U << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 1985 #define ADC_JDR1_JDATA_12 (0x1000U << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 1986 #define ADC_JDR1_JDATA_13 (0x2000U << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 1987 #define ADC_JDR1_JDATA_14 (0x4000U << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 1988 #define ADC_JDR1_JDATA_15 (0x8000U << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 1989
Kojto 122:f9eeca106725 1990 /******************** Bit definition for ADC_JDR2 register ******************/
Kojto 122:f9eeca106725 1991 #define ADC_JDR2_JDATA_Pos (0U)
Kojto 122:f9eeca106725 1992 #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 1993 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
Kojto 122:f9eeca106725 1994 #define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1995 #define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1996 #define ADC_JDR2_JDATA_2 (0x0004U << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1997 #define ADC_JDR2_JDATA_3 (0x0008U << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1998 #define ADC_JDR2_JDATA_4 (0x0010U << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1999 #define ADC_JDR2_JDATA_5 (0x0020U << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 2000 #define ADC_JDR2_JDATA_6 (0x0040U << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 2001 #define ADC_JDR2_JDATA_7 (0x0080U << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 2002 #define ADC_JDR2_JDATA_8 (0x0100U << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2003 #define ADC_JDR2_JDATA_9 (0x0200U << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 2004 #define ADC_JDR2_JDATA_10 (0x0400U << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2005 #define ADC_JDR2_JDATA_11 (0x0800U << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 2006 #define ADC_JDR2_JDATA_12 (0x1000U << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 2007 #define ADC_JDR2_JDATA_13 (0x2000U << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 2008 #define ADC_JDR2_JDATA_14 (0x4000U << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 2009 #define ADC_JDR2_JDATA_15 (0x8000U << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 2010
Kojto 122:f9eeca106725 2011 /******************** Bit definition for ADC_JDR3 register ******************/
Kojto 122:f9eeca106725 2012 #define ADC_JDR3_JDATA_Pos (0U)
Kojto 122:f9eeca106725 2013 #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 2014 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
Kojto 122:f9eeca106725 2015 #define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2016 #define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2017 #define ADC_JDR3_JDATA_2 (0x0004U << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2018 #define ADC_JDR3_JDATA_3 (0x0008U << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2019 #define ADC_JDR3_JDATA_4 (0x0010U << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 2020 #define ADC_JDR3_JDATA_5 (0x0020U << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 2021 #define ADC_JDR3_JDATA_6 (0x0040U << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 2022 #define ADC_JDR3_JDATA_7 (0x0080U << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 2023 #define ADC_JDR3_JDATA_8 (0x0100U << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2024 #define ADC_JDR3_JDATA_9 (0x0200U << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 2025 #define ADC_JDR3_JDATA_10 (0x0400U << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2026 #define ADC_JDR3_JDATA_11 (0x0800U << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 2027 #define ADC_JDR3_JDATA_12 (0x1000U << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 2028 #define ADC_JDR3_JDATA_13 (0x2000U << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 2029 #define ADC_JDR3_JDATA_14 (0x4000U << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 2030 #define ADC_JDR3_JDATA_15 (0x8000U << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 2031
Kojto 122:f9eeca106725 2032 /******************** Bit definition for ADC_JDR4 register ******************/
Kojto 122:f9eeca106725 2033 #define ADC_JDR4_JDATA_Pos (0U)
Kojto 122:f9eeca106725 2034 #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 2035 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
Kojto 122:f9eeca106725 2036 #define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2037 #define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2038 #define ADC_JDR4_JDATA_2 (0x0004U << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2039 #define ADC_JDR4_JDATA_3 (0x0008U << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2040 #define ADC_JDR4_JDATA_4 (0x0010U << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 2041 #define ADC_JDR4_JDATA_5 (0x0020U << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 2042 #define ADC_JDR4_JDATA_6 (0x0040U << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 2043 #define ADC_JDR4_JDATA_7 (0x0080U << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 2044 #define ADC_JDR4_JDATA_8 (0x0100U << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2045 #define ADC_JDR4_JDATA_9 (0x0200U << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 2046 #define ADC_JDR4_JDATA_10 (0x0400U << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2047 #define ADC_JDR4_JDATA_11 (0x0800U << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 2048 #define ADC_JDR4_JDATA_12 (0x1000U << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 2049 #define ADC_JDR4_JDATA_13 (0x2000U << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 2050 #define ADC_JDR4_JDATA_14 (0x4000U << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 2051 #define ADC_JDR4_JDATA_15 (0x8000U << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 2052
Kojto 122:f9eeca106725 2053 /******************** Bit definition for ADC_AWD2CR register ****************/
Kojto 122:f9eeca106725 2054 #define ADC_AWD2CR_AWD2CH_Pos (0U)
Kojto 122:f9eeca106725 2055 #define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFU << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */
Kojto 122:f9eeca106725 2056 #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */
Kojto 122:f9eeca106725 2057 #define ADC_AWD2CR_AWD2CH_0 (0x00001U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2058 #define ADC_AWD2CR_AWD2CH_1 (0x00002U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2059 #define ADC_AWD2CR_AWD2CH_2 (0x00004U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2060 #define ADC_AWD2CR_AWD2CH_3 (0x00008U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2061 #define ADC_AWD2CR_AWD2CH_4 (0x00010U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 2062 #define ADC_AWD2CR_AWD2CH_5 (0x00020U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 2063 #define ADC_AWD2CR_AWD2CH_6 (0x00040U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 2064 #define ADC_AWD2CR_AWD2CH_7 (0x00080U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 2065 #define ADC_AWD2CR_AWD2CH_8 (0x00100U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2066 #define ADC_AWD2CR_AWD2CH_9 (0x00200U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 2067 #define ADC_AWD2CR_AWD2CH_10 (0x00400U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2068 #define ADC_AWD2CR_AWD2CH_11 (0x00800U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 2069 #define ADC_AWD2CR_AWD2CH_12 (0x01000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 2070 #define ADC_AWD2CR_AWD2CH_13 (0x02000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 2071 #define ADC_AWD2CR_AWD2CH_14 (0x04000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 2072 #define ADC_AWD2CR_AWD2CH_15 (0x08000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 2073 #define ADC_AWD2CR_AWD2CH_16 (0x10000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 2074 #define ADC_AWD2CR_AWD2CH_17 (0x20000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 2075 #define ADC_AWD2CR_AWD2CH_18 (0x40000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 2076
Kojto 122:f9eeca106725 2077 /******************** Bit definition for ADC_AWD3CR register ****************/
Kojto 122:f9eeca106725 2078 #define ADC_AWD3CR_AWD3CH_Pos (0U)
Kojto 122:f9eeca106725 2079 #define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFU << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */
Kojto 122:f9eeca106725 2080 #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */
Kojto 122:f9eeca106725 2081 #define ADC_AWD3CR_AWD3CH_0 (0x00001U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2082 #define ADC_AWD3CR_AWD3CH_1 (0x00002U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2083 #define ADC_AWD3CR_AWD3CH_2 (0x00004U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2084 #define ADC_AWD3CR_AWD3CH_3 (0x00008U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2085 #define ADC_AWD3CR_AWD3CH_4 (0x00010U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 2086 #define ADC_AWD3CR_AWD3CH_5 (0x00020U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 2087 #define ADC_AWD3CR_AWD3CH_6 (0x00040U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 2088 #define ADC_AWD3CR_AWD3CH_7 (0x00080U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 2089 #define ADC_AWD3CR_AWD3CH_8 (0x00100U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2090 #define ADC_AWD3CR_AWD3CH_9 (0x00200U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 2091 #define ADC_AWD3CR_AWD3CH_10 (0x00400U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2092 #define ADC_AWD3CR_AWD3CH_11 (0x00800U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 2093 #define ADC_AWD3CR_AWD3CH_12 (0x01000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 2094 #define ADC_AWD3CR_AWD3CH_13 (0x02000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 2095 #define ADC_AWD3CR_AWD3CH_14 (0x04000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 2096 #define ADC_AWD3CR_AWD3CH_15 (0x08000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 2097 #define ADC_AWD3CR_AWD3CH_16 (0x10000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 2098 #define ADC_AWD3CR_AWD3CH_17 (0x20000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 2099 #define ADC_AWD3CR_AWD3CH_18 (0x40000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 2100
Kojto 122:f9eeca106725 2101 /******************** Bit definition for ADC_DIFSEL register ****************/
Kojto 122:f9eeca106725 2102 #define ADC_DIFSEL_DIFSEL_Pos (0U)
Kojto 122:f9eeca106725 2103 #define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFU << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */
Kojto 122:f9eeca106725 2104 #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */
Kojto 122:f9eeca106725 2105 #define ADC_DIFSEL_DIFSEL_0 (0x00001U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2106 #define ADC_DIFSEL_DIFSEL_1 (0x00002U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2107 #define ADC_DIFSEL_DIFSEL_2 (0x00004U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2108 #define ADC_DIFSEL_DIFSEL_3 (0x00008U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2109 #define ADC_DIFSEL_DIFSEL_4 (0x00010U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 2110 #define ADC_DIFSEL_DIFSEL_5 (0x00020U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 2111 #define ADC_DIFSEL_DIFSEL_6 (0x00040U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 2112 #define ADC_DIFSEL_DIFSEL_7 (0x00080U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 2113 #define ADC_DIFSEL_DIFSEL_8 (0x00100U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2114 #define ADC_DIFSEL_DIFSEL_9 (0x00200U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 2115 #define ADC_DIFSEL_DIFSEL_10 (0x00400U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2116 #define ADC_DIFSEL_DIFSEL_11 (0x00800U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 2117 #define ADC_DIFSEL_DIFSEL_12 (0x01000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 2118 #define ADC_DIFSEL_DIFSEL_13 (0x02000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 2119 #define ADC_DIFSEL_DIFSEL_14 (0x04000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 2120 #define ADC_DIFSEL_DIFSEL_15 (0x08000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 2121 #define ADC_DIFSEL_DIFSEL_16 (0x10000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 2122 #define ADC_DIFSEL_DIFSEL_17 (0x20000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 2123 #define ADC_DIFSEL_DIFSEL_18 (0x40000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 2124
Kojto 122:f9eeca106725 2125 /******************** Bit definition for ADC_CALFACT register ***************/
Kojto 122:f9eeca106725 2126 #define ADC_CALFACT_CALFACT_S_Pos (0U)
Kojto 122:f9eeca106725 2127 #define ADC_CALFACT_CALFACT_S_Msk (0x7FU << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */
Kojto 122:f9eeca106725 2128 #define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */
Kojto 122:f9eeca106725 2129 #define ADC_CALFACT_CALFACT_S_0 (0x01U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2130 #define ADC_CALFACT_CALFACT_S_1 (0x02U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2131 #define ADC_CALFACT_CALFACT_S_2 (0x04U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2132 #define ADC_CALFACT_CALFACT_S_3 (0x08U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2133 #define ADC_CALFACT_CALFACT_S_4 (0x10U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 2134 #define ADC_CALFACT_CALFACT_S_5 (0x20U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 2135 #define ADC_CALFACT_CALFACT_S_6 (0x40U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 2136
Kojto 122:f9eeca106725 2137 #define ADC_CALFACT_CALFACT_D_Pos (16U)
Kojto 122:f9eeca106725 2138 #define ADC_CALFACT_CALFACT_D_Msk (0x7FU << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */
Kojto 122:f9eeca106725 2139 #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */
Kojto 122:f9eeca106725 2140 #define ADC_CALFACT_CALFACT_D_0 (0x01U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 2141 #define ADC_CALFACT_CALFACT_D_1 (0x02U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 2142 #define ADC_CALFACT_CALFACT_D_2 (0x04U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 2143 #define ADC_CALFACT_CALFACT_D_3 (0x08U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 2144 #define ADC_CALFACT_CALFACT_D_4 (0x10U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 2145 #define ADC_CALFACT_CALFACT_D_5 (0x20U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 2146 #define ADC_CALFACT_CALFACT_D_6 (0x40U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 2147
Kojto 122:f9eeca106725 2148 /************************* ADC Common registers *****************************/
Kojto 122:f9eeca106725 2149 /******************** Bit definition for ADC_CCR register *******************/
Kojto 122:f9eeca106725 2150 #define ADC_CCR_CKMODE_Pos (16U)
Kojto 122:f9eeca106725 2151 #define ADC_CCR_CKMODE_Msk (0x3U << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
Kojto 122:f9eeca106725 2152 #define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
Kojto 122:f9eeca106725 2153 #define ADC_CCR_CKMODE_0 (0x1U << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 2154 #define ADC_CCR_CKMODE_1 (0x2U << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 2155
Kojto 122:f9eeca106725 2156 #define ADC_CCR_PRESC_Pos (18U)
Kojto 122:f9eeca106725 2157 #define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
Kojto 122:f9eeca106725 2158 #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */
Kojto 122:f9eeca106725 2159 #define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 2160 #define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 2161 #define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 2162 #define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 2163
Kojto 122:f9eeca106725 2164 #define ADC_CCR_VREFEN_Pos (22U)
Kojto 122:f9eeca106725 2165 #define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 2166 #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */
Kojto 122:f9eeca106725 2167 #define ADC_CCR_TSEN_Pos (23U)
Kojto 122:f9eeca106725 2168 #define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 2169 #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */
Kojto 122:f9eeca106725 2170 #define ADC_CCR_VBATEN_Pos (24U)
Kojto 122:f9eeca106725 2171 #define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 2172 #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */
Kojto 122:f9eeca106725 2173
Kojto 122:f9eeca106725 2174 /******************************************************************************/
Kojto 122:f9eeca106725 2175 /* */
Kojto 122:f9eeca106725 2176 /* Controller Area Network */
Kojto 122:f9eeca106725 2177 /* */
Kojto 122:f9eeca106725 2178 /******************************************************************************/
Kojto 122:f9eeca106725 2179 /******************* Bit definition for CAN_MCR register ********************/
Kojto 122:f9eeca106725 2180 #define CAN_MCR_INRQ_Pos (0U)
Kojto 122:f9eeca106725 2181 #define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2182 #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
Kojto 122:f9eeca106725 2183 #define CAN_MCR_SLEEP_Pos (1U)
Kojto 122:f9eeca106725 2184 #define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2185 #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
Kojto 122:f9eeca106725 2186 #define CAN_MCR_TXFP_Pos (2U)
Kojto 122:f9eeca106725 2187 #define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2188 #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
Kojto 122:f9eeca106725 2189 #define CAN_MCR_RFLM_Pos (3U)
Kojto 122:f9eeca106725 2190 #define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2191 #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
Kojto 122:f9eeca106725 2192 #define CAN_MCR_NART_Pos (4U)
Kojto 122:f9eeca106725 2193 #define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 2194 #define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
Kojto 122:f9eeca106725 2195 #define CAN_MCR_AWUM_Pos (5U)
Kojto 122:f9eeca106725 2196 #define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 2197 #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
Kojto 122:f9eeca106725 2198 #define CAN_MCR_ABOM_Pos (6U)
Kojto 122:f9eeca106725 2199 #define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 2200 #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
Kojto 122:f9eeca106725 2201 #define CAN_MCR_TTCM_Pos (7U)
Kojto 122:f9eeca106725 2202 #define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 2203 #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
Kojto 122:f9eeca106725 2204 #define CAN_MCR_RESET_Pos (15U)
Kojto 122:f9eeca106725 2205 #define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 2206 #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
Kojto 122:f9eeca106725 2207
Kojto 122:f9eeca106725 2208 /******************* Bit definition for CAN_MSR register ********************/
Kojto 122:f9eeca106725 2209 #define CAN_MSR_INAK_Pos (0U)
Kojto 122:f9eeca106725 2210 #define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2211 #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
Kojto 122:f9eeca106725 2212 #define CAN_MSR_SLAK_Pos (1U)
Kojto 122:f9eeca106725 2213 #define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2214 #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
Kojto 122:f9eeca106725 2215 #define CAN_MSR_ERRI_Pos (2U)
Kojto 122:f9eeca106725 2216 #define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2217 #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
Kojto 122:f9eeca106725 2218 #define CAN_MSR_WKUI_Pos (3U)
Kojto 122:f9eeca106725 2219 #define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2220 #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
Kojto 122:f9eeca106725 2221 #define CAN_MSR_SLAKI_Pos (4U)
Kojto 122:f9eeca106725 2222 #define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 2223 #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
Kojto 122:f9eeca106725 2224 #define CAN_MSR_TXM_Pos (8U)
Kojto 122:f9eeca106725 2225 #define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2226 #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
Kojto 122:f9eeca106725 2227 #define CAN_MSR_RXM_Pos (9U)
Kojto 122:f9eeca106725 2228 #define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 2229 #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
Kojto 122:f9eeca106725 2230 #define CAN_MSR_SAMP_Pos (10U)
Kojto 122:f9eeca106725 2231 #define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2232 #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
Kojto 122:f9eeca106725 2233 #define CAN_MSR_RX_Pos (11U)
Kojto 122:f9eeca106725 2234 #define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 2235 #define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
Kojto 122:f9eeca106725 2236
Kojto 122:f9eeca106725 2237 /******************* Bit definition for CAN_TSR register ********************/
Kojto 122:f9eeca106725 2238 #define CAN_TSR_RQCP0_Pos (0U)
Kojto 122:f9eeca106725 2239 #define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2240 #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
Kojto 122:f9eeca106725 2241 #define CAN_TSR_TXOK0_Pos (1U)
Kojto 122:f9eeca106725 2242 #define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2243 #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
Kojto 122:f9eeca106725 2244 #define CAN_TSR_ALST0_Pos (2U)
Kojto 122:f9eeca106725 2245 #define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2246 #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
Kojto 122:f9eeca106725 2247 #define CAN_TSR_TERR0_Pos (3U)
Kojto 122:f9eeca106725 2248 #define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2249 #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
Kojto 122:f9eeca106725 2250 #define CAN_TSR_ABRQ0_Pos (7U)
Kojto 122:f9eeca106725 2251 #define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 2252 #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
Kojto 122:f9eeca106725 2253 #define CAN_TSR_RQCP1_Pos (8U)
Kojto 122:f9eeca106725 2254 #define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2255 #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
Kojto 122:f9eeca106725 2256 #define CAN_TSR_TXOK1_Pos (9U)
Kojto 122:f9eeca106725 2257 #define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 2258 #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
Kojto 122:f9eeca106725 2259 #define CAN_TSR_ALST1_Pos (10U)
Kojto 122:f9eeca106725 2260 #define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2261 #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
Kojto 122:f9eeca106725 2262 #define CAN_TSR_TERR1_Pos (11U)
Kojto 122:f9eeca106725 2263 #define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 2264 #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
Kojto 122:f9eeca106725 2265 #define CAN_TSR_ABRQ1_Pos (15U)
Kojto 122:f9eeca106725 2266 #define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 2267 #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
Kojto 122:f9eeca106725 2268 #define CAN_TSR_RQCP2_Pos (16U)
Kojto 122:f9eeca106725 2269 #define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 2270 #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
Kojto 122:f9eeca106725 2271 #define CAN_TSR_TXOK2_Pos (17U)
Kojto 122:f9eeca106725 2272 #define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 2273 #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
Kojto 122:f9eeca106725 2274 #define CAN_TSR_ALST2_Pos (18U)
Kojto 122:f9eeca106725 2275 #define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 2276 #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
Kojto 122:f9eeca106725 2277 #define CAN_TSR_TERR2_Pos (19U)
Kojto 122:f9eeca106725 2278 #define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 2279 #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
Kojto 122:f9eeca106725 2280 #define CAN_TSR_ABRQ2_Pos (23U)
Kojto 122:f9eeca106725 2281 #define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 2282 #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
Kojto 122:f9eeca106725 2283 #define CAN_TSR_CODE_Pos (24U)
Kojto 122:f9eeca106725 2284 #define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
Kojto 122:f9eeca106725 2285 #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
Kojto 122:f9eeca106725 2286
Kojto 122:f9eeca106725 2287 #define CAN_TSR_TME_Pos (26U)
Kojto 122:f9eeca106725 2288 #define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
Kojto 122:f9eeca106725 2289 #define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
Kojto 122:f9eeca106725 2290 #define CAN_TSR_TME0_Pos (26U)
Kojto 122:f9eeca106725 2291 #define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 2292 #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
Kojto 122:f9eeca106725 2293 #define CAN_TSR_TME1_Pos (27U)
Kojto 122:f9eeca106725 2294 #define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 2295 #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
Kojto 122:f9eeca106725 2296 #define CAN_TSR_TME2_Pos (28U)
Kojto 122:f9eeca106725 2297 #define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 2298 #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
Kojto 122:f9eeca106725 2299
Kojto 122:f9eeca106725 2300 #define CAN_TSR_LOW_Pos (29U)
Kojto 122:f9eeca106725 2301 #define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
Kojto 122:f9eeca106725 2302 #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
Kojto 122:f9eeca106725 2303 #define CAN_TSR_LOW0_Pos (29U)
Kojto 122:f9eeca106725 2304 #define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 2305 #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
Kojto 122:f9eeca106725 2306 #define CAN_TSR_LOW1_Pos (30U)
Kojto 122:f9eeca106725 2307 #define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 2308 #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
Kojto 122:f9eeca106725 2309 #define CAN_TSR_LOW2_Pos (31U)
Kojto 122:f9eeca106725 2310 #define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 2311 #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
Kojto 122:f9eeca106725 2312
Kojto 122:f9eeca106725 2313 /******************* Bit definition for CAN_RF0R register *******************/
Kojto 122:f9eeca106725 2314 #define CAN_RF0R_FMP0_Pos (0U)
Kojto 122:f9eeca106725 2315 #define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 2316 #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
Kojto 122:f9eeca106725 2317 #define CAN_RF0R_FULL0_Pos (3U)
Kojto 122:f9eeca106725 2318 #define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2319 #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
Kojto 122:f9eeca106725 2320 #define CAN_RF0R_FOVR0_Pos (4U)
Kojto 122:f9eeca106725 2321 #define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 2322 #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
Kojto 122:f9eeca106725 2323 #define CAN_RF0R_RFOM0_Pos (5U)
Kojto 122:f9eeca106725 2324 #define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 2325 #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
Kojto 122:f9eeca106725 2326
Kojto 122:f9eeca106725 2327 /******************* Bit definition for CAN_RF1R register *******************/
Kojto 122:f9eeca106725 2328 #define CAN_RF1R_FMP1_Pos (0U)
Kojto 122:f9eeca106725 2329 #define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 2330 #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
Kojto 122:f9eeca106725 2331 #define CAN_RF1R_FULL1_Pos (3U)
Kojto 122:f9eeca106725 2332 #define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2333 #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
Kojto 122:f9eeca106725 2334 #define CAN_RF1R_FOVR1_Pos (4U)
Kojto 122:f9eeca106725 2335 #define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 2336 #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
Kojto 122:f9eeca106725 2337 #define CAN_RF1R_RFOM1_Pos (5U)
Kojto 122:f9eeca106725 2338 #define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 2339 #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
Kojto 122:f9eeca106725 2340
Kojto 122:f9eeca106725 2341 /******************** Bit definition for CAN_IER register *******************/
Kojto 122:f9eeca106725 2342 #define CAN_IER_TMEIE_Pos (0U)
Kojto 122:f9eeca106725 2343 #define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2344 #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
Kojto 122:f9eeca106725 2345 #define CAN_IER_FMPIE0_Pos (1U)
Kojto 122:f9eeca106725 2346 #define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2347 #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
Kojto 122:f9eeca106725 2348 #define CAN_IER_FFIE0_Pos (2U)
Kojto 122:f9eeca106725 2349 #define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2350 #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
Kojto 122:f9eeca106725 2351 #define CAN_IER_FOVIE0_Pos (3U)
Kojto 122:f9eeca106725 2352 #define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2353 #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
Kojto 122:f9eeca106725 2354 #define CAN_IER_FMPIE1_Pos (4U)
Kojto 122:f9eeca106725 2355 #define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 2356 #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
Kojto 122:f9eeca106725 2357 #define CAN_IER_FFIE1_Pos (5U)
Kojto 122:f9eeca106725 2358 #define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 2359 #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
Kojto 122:f9eeca106725 2360 #define CAN_IER_FOVIE1_Pos (6U)
Kojto 122:f9eeca106725 2361 #define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 2362 #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
Kojto 122:f9eeca106725 2363 #define CAN_IER_EWGIE_Pos (8U)
Kojto 122:f9eeca106725 2364 #define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2365 #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
Kojto 122:f9eeca106725 2366 #define CAN_IER_EPVIE_Pos (9U)
Kojto 122:f9eeca106725 2367 #define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 2368 #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
Kojto 122:f9eeca106725 2369 #define CAN_IER_BOFIE_Pos (10U)
Kojto 122:f9eeca106725 2370 #define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2371 #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
Kojto 122:f9eeca106725 2372 #define CAN_IER_LECIE_Pos (11U)
Kojto 122:f9eeca106725 2373 #define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 2374 #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
Kojto 122:f9eeca106725 2375 #define CAN_IER_ERRIE_Pos (15U)
Kojto 122:f9eeca106725 2376 #define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 2377 #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
Kojto 122:f9eeca106725 2378 #define CAN_IER_WKUIE_Pos (16U)
Kojto 122:f9eeca106725 2379 #define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 2380 #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
Kojto 122:f9eeca106725 2381 #define CAN_IER_SLKIE_Pos (17U)
Kojto 122:f9eeca106725 2382 #define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 2383 #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
Kojto 122:f9eeca106725 2384
Kojto 122:f9eeca106725 2385 /******************** Bit definition for CAN_ESR register *******************/
Kojto 122:f9eeca106725 2386 #define CAN_ESR_EWGF_Pos (0U)
Kojto 122:f9eeca106725 2387 #define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2388 #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
Kojto 122:f9eeca106725 2389 #define CAN_ESR_EPVF_Pos (1U)
Kojto 122:f9eeca106725 2390 #define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2391 #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
Kojto 122:f9eeca106725 2392 #define CAN_ESR_BOFF_Pos (2U)
Kojto 122:f9eeca106725 2393 #define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2394 #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
Kojto 122:f9eeca106725 2395
Kojto 122:f9eeca106725 2396 #define CAN_ESR_LEC_Pos (4U)
Kojto 122:f9eeca106725 2397 #define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
Kojto 122:f9eeca106725 2398 #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
Kojto 122:f9eeca106725 2399 #define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 2400 #define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 2401 #define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 2402
Kojto 122:f9eeca106725 2403 #define CAN_ESR_TEC_Pos (16U)
Kojto 122:f9eeca106725 2404 #define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 2405 #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
Kojto 122:f9eeca106725 2406 #define CAN_ESR_REC_Pos (24U)
Kojto 122:f9eeca106725 2407 #define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 2408 #define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
Kojto 122:f9eeca106725 2409
Kojto 122:f9eeca106725 2410 /******************* Bit definition for CAN_BTR register ********************/
Kojto 122:f9eeca106725 2411 #define CAN_BTR_BRP_Pos (0U)
Kojto 122:f9eeca106725 2412 #define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
Kojto 122:f9eeca106725 2413 #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
Kojto 122:f9eeca106725 2414 #define CAN_BTR_TS1_Pos (16U)
Kojto 122:f9eeca106725 2415 #define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
Kojto 122:f9eeca106725 2416 #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
Kojto 122:f9eeca106725 2417 #define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 2418 #define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 2419 #define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 2420 #define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 2421 #define CAN_BTR_TS2_Pos (20U)
Kojto 122:f9eeca106725 2422 #define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
Kojto 122:f9eeca106725 2423 #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
Kojto 122:f9eeca106725 2424 #define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 2425 #define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 2426 #define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 2427 #define CAN_BTR_SJW_Pos (24U)
Kojto 122:f9eeca106725 2428 #define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
Kojto 122:f9eeca106725 2429 #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
Kojto 122:f9eeca106725 2430 #define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 2431 #define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 2432 #define CAN_BTR_LBKM_Pos (30U)
Kojto 122:f9eeca106725 2433 #define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 2434 #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
Kojto 122:f9eeca106725 2435 #define CAN_BTR_SILM_Pos (31U)
Kojto 122:f9eeca106725 2436 #define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 2437 #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
Kojto 122:f9eeca106725 2438
Kojto 122:f9eeca106725 2439 /*!<Mailbox registers */
Kojto 122:f9eeca106725 2440 /****************** Bit definition for CAN_TI0R register ********************/
Kojto 122:f9eeca106725 2441 #define CAN_TI0R_TXRQ_Pos (0U)
Kojto 122:f9eeca106725 2442 #define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2443 #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
Kojto 122:f9eeca106725 2444 #define CAN_TI0R_RTR_Pos (1U)
Kojto 122:f9eeca106725 2445 #define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2446 #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
Kojto 122:f9eeca106725 2447 #define CAN_TI0R_IDE_Pos (2U)
Kojto 122:f9eeca106725 2448 #define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2449 #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
Kojto 122:f9eeca106725 2450 #define CAN_TI0R_EXID_Pos (3U)
Kojto 122:f9eeca106725 2451 #define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
Kojto 122:f9eeca106725 2452 #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
Kojto 122:f9eeca106725 2453 #define CAN_TI0R_STID_Pos (21U)
Kojto 122:f9eeca106725 2454 #define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
Kojto 122:f9eeca106725 2455 #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
Kojto 122:f9eeca106725 2456
Kojto 122:f9eeca106725 2457 /****************** Bit definition for CAN_TDT0R register *******************/
Kojto 122:f9eeca106725 2458 #define CAN_TDT0R_DLC_Pos (0U)
Kojto 122:f9eeca106725 2459 #define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 2460 #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
Kojto 122:f9eeca106725 2461 #define CAN_TDT0R_TGT_Pos (8U)
Kojto 122:f9eeca106725 2462 #define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2463 #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
Kojto 122:f9eeca106725 2464 #define CAN_TDT0R_TIME_Pos (16U)
Kojto 122:f9eeca106725 2465 #define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
Kojto 122:f9eeca106725 2466 #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
Kojto 122:f9eeca106725 2467
Kojto 122:f9eeca106725 2468 /****************** Bit definition for CAN_TDL0R register *******************/
Kojto 122:f9eeca106725 2469 #define CAN_TDL0R_DATA0_Pos (0U)
Kojto 122:f9eeca106725 2470 #define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 2471 #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
Kojto 122:f9eeca106725 2472 #define CAN_TDL0R_DATA1_Pos (8U)
Kojto 122:f9eeca106725 2473 #define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 2474 #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
Kojto 122:f9eeca106725 2475 #define CAN_TDL0R_DATA2_Pos (16U)
Kojto 122:f9eeca106725 2476 #define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 2477 #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
Kojto 122:f9eeca106725 2478 #define CAN_TDL0R_DATA3_Pos (24U)
Kojto 122:f9eeca106725 2479 #define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 2480 #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
Kojto 122:f9eeca106725 2481
Kojto 122:f9eeca106725 2482 /****************** Bit definition for CAN_TDH0R register *******************/
Kojto 122:f9eeca106725 2483 #define CAN_TDH0R_DATA4_Pos (0U)
Kojto 122:f9eeca106725 2484 #define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 2485 #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
Kojto 122:f9eeca106725 2486 #define CAN_TDH0R_DATA5_Pos (8U)
Kojto 122:f9eeca106725 2487 #define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 2488 #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
Kojto 122:f9eeca106725 2489 #define CAN_TDH0R_DATA6_Pos (16U)
Kojto 122:f9eeca106725 2490 #define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 2491 #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
Kojto 122:f9eeca106725 2492 #define CAN_TDH0R_DATA7_Pos (24U)
Kojto 122:f9eeca106725 2493 #define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 2494 #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
Kojto 122:f9eeca106725 2495
Kojto 122:f9eeca106725 2496 /******************* Bit definition for CAN_TI1R register *******************/
Kojto 122:f9eeca106725 2497 #define CAN_TI1R_TXRQ_Pos (0U)
Kojto 122:f9eeca106725 2498 #define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2499 #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
Kojto 122:f9eeca106725 2500 #define CAN_TI1R_RTR_Pos (1U)
Kojto 122:f9eeca106725 2501 #define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2502 #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
Kojto 122:f9eeca106725 2503 #define CAN_TI1R_IDE_Pos (2U)
Kojto 122:f9eeca106725 2504 #define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2505 #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
Kojto 122:f9eeca106725 2506 #define CAN_TI1R_EXID_Pos (3U)
Kojto 122:f9eeca106725 2507 #define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
Kojto 122:f9eeca106725 2508 #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
Kojto 122:f9eeca106725 2509 #define CAN_TI1R_STID_Pos (21U)
Kojto 122:f9eeca106725 2510 #define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
Kojto 122:f9eeca106725 2511 #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
Kojto 122:f9eeca106725 2512
Kojto 122:f9eeca106725 2513 /******************* Bit definition for CAN_TDT1R register ******************/
Kojto 122:f9eeca106725 2514 #define CAN_TDT1R_DLC_Pos (0U)
Kojto 122:f9eeca106725 2515 #define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 2516 #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
Kojto 122:f9eeca106725 2517 #define CAN_TDT1R_TGT_Pos (8U)
Kojto 122:f9eeca106725 2518 #define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2519 #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
Kojto 122:f9eeca106725 2520 #define CAN_TDT1R_TIME_Pos (16U)
Kojto 122:f9eeca106725 2521 #define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
Kojto 122:f9eeca106725 2522 #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
Kojto 122:f9eeca106725 2523
Kojto 122:f9eeca106725 2524 /******************* Bit definition for CAN_TDL1R register ******************/
Kojto 122:f9eeca106725 2525 #define CAN_TDL1R_DATA0_Pos (0U)
Kojto 122:f9eeca106725 2526 #define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 2527 #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
Kojto 122:f9eeca106725 2528 #define CAN_TDL1R_DATA1_Pos (8U)
Kojto 122:f9eeca106725 2529 #define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 2530 #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
Kojto 122:f9eeca106725 2531 #define CAN_TDL1R_DATA2_Pos (16U)
Kojto 122:f9eeca106725 2532 #define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 2533 #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
Kojto 122:f9eeca106725 2534 #define CAN_TDL1R_DATA3_Pos (24U)
Kojto 122:f9eeca106725 2535 #define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 2536 #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
Kojto 122:f9eeca106725 2537
Kojto 122:f9eeca106725 2538 /******************* Bit definition for CAN_TDH1R register ******************/
Kojto 122:f9eeca106725 2539 #define CAN_TDH1R_DATA4_Pos (0U)
Kojto 122:f9eeca106725 2540 #define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 2541 #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
Kojto 122:f9eeca106725 2542 #define CAN_TDH1R_DATA5_Pos (8U)
Kojto 122:f9eeca106725 2543 #define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 2544 #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
Kojto 122:f9eeca106725 2545 #define CAN_TDH1R_DATA6_Pos (16U)
Kojto 122:f9eeca106725 2546 #define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 2547 #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
Kojto 122:f9eeca106725 2548 #define CAN_TDH1R_DATA7_Pos (24U)
Kojto 122:f9eeca106725 2549 #define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 2550 #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
Kojto 122:f9eeca106725 2551
Kojto 122:f9eeca106725 2552 /******************* Bit definition for CAN_TI2R register *******************/
Kojto 122:f9eeca106725 2553 #define CAN_TI2R_TXRQ_Pos (0U)
Kojto 122:f9eeca106725 2554 #define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2555 #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
Kojto 122:f9eeca106725 2556 #define CAN_TI2R_RTR_Pos (1U)
Kojto 122:f9eeca106725 2557 #define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2558 #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
Kojto 122:f9eeca106725 2559 #define CAN_TI2R_IDE_Pos (2U)
Kojto 122:f9eeca106725 2560 #define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2561 #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
Kojto 122:f9eeca106725 2562 #define CAN_TI2R_EXID_Pos (3U)
Kojto 122:f9eeca106725 2563 #define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
Kojto 122:f9eeca106725 2564 #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
Kojto 122:f9eeca106725 2565 #define CAN_TI2R_STID_Pos (21U)
Kojto 122:f9eeca106725 2566 #define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
Kojto 122:f9eeca106725 2567 #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
Kojto 122:f9eeca106725 2568
Kojto 122:f9eeca106725 2569 /******************* Bit definition for CAN_TDT2R register ******************/
Kojto 122:f9eeca106725 2570 #define CAN_TDT2R_DLC_Pos (0U)
Kojto 122:f9eeca106725 2571 #define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 2572 #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
Kojto 122:f9eeca106725 2573 #define CAN_TDT2R_TGT_Pos (8U)
Kojto 122:f9eeca106725 2574 #define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2575 #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
Kojto 122:f9eeca106725 2576 #define CAN_TDT2R_TIME_Pos (16U)
Kojto 122:f9eeca106725 2577 #define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
Kojto 122:f9eeca106725 2578 #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
Kojto 122:f9eeca106725 2579
Kojto 122:f9eeca106725 2580 /******************* Bit definition for CAN_TDL2R register ******************/
Kojto 122:f9eeca106725 2581 #define CAN_TDL2R_DATA0_Pos (0U)
Kojto 122:f9eeca106725 2582 #define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 2583 #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
Kojto 122:f9eeca106725 2584 #define CAN_TDL2R_DATA1_Pos (8U)
Kojto 122:f9eeca106725 2585 #define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 2586 #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
Kojto 122:f9eeca106725 2587 #define CAN_TDL2R_DATA2_Pos (16U)
Kojto 122:f9eeca106725 2588 #define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 2589 #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
Kojto 122:f9eeca106725 2590 #define CAN_TDL2R_DATA3_Pos (24U)
Kojto 122:f9eeca106725 2591 #define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 2592 #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
Kojto 122:f9eeca106725 2593
Kojto 122:f9eeca106725 2594 /******************* Bit definition for CAN_TDH2R register ******************/
Kojto 122:f9eeca106725 2595 #define CAN_TDH2R_DATA4_Pos (0U)
Kojto 122:f9eeca106725 2596 #define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 2597 #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
Kojto 122:f9eeca106725 2598 #define CAN_TDH2R_DATA5_Pos (8U)
Kojto 122:f9eeca106725 2599 #define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 2600 #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
Kojto 122:f9eeca106725 2601 #define CAN_TDH2R_DATA6_Pos (16U)
Kojto 122:f9eeca106725 2602 #define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 2603 #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
Kojto 122:f9eeca106725 2604 #define CAN_TDH2R_DATA7_Pos (24U)
Kojto 122:f9eeca106725 2605 #define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 2606 #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
Kojto 122:f9eeca106725 2607
Kojto 122:f9eeca106725 2608 /******************* Bit definition for CAN_RI0R register *******************/
Kojto 122:f9eeca106725 2609 #define CAN_RI0R_RTR_Pos (1U)
Kojto 122:f9eeca106725 2610 #define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2611 #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
Kojto 122:f9eeca106725 2612 #define CAN_RI0R_IDE_Pos (2U)
Kojto 122:f9eeca106725 2613 #define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2614 #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
Kojto 122:f9eeca106725 2615 #define CAN_RI0R_EXID_Pos (3U)
Kojto 122:f9eeca106725 2616 #define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
Kojto 122:f9eeca106725 2617 #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
Kojto 122:f9eeca106725 2618 #define CAN_RI0R_STID_Pos (21U)
Kojto 122:f9eeca106725 2619 #define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
Kojto 122:f9eeca106725 2620 #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
Kojto 122:f9eeca106725 2621
Kojto 122:f9eeca106725 2622 /******************* Bit definition for CAN_RDT0R register ******************/
Kojto 122:f9eeca106725 2623 #define CAN_RDT0R_DLC_Pos (0U)
Kojto 122:f9eeca106725 2624 #define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 2625 #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
Kojto 122:f9eeca106725 2626 #define CAN_RDT0R_FMI_Pos (8U)
Kojto 122:f9eeca106725 2627 #define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 2628 #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
Kojto 122:f9eeca106725 2629 #define CAN_RDT0R_TIME_Pos (16U)
Kojto 122:f9eeca106725 2630 #define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
Kojto 122:f9eeca106725 2631 #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
Kojto 122:f9eeca106725 2632
Kojto 122:f9eeca106725 2633 /******************* Bit definition for CAN_RDL0R register ******************/
Kojto 122:f9eeca106725 2634 #define CAN_RDL0R_DATA0_Pos (0U)
Kojto 122:f9eeca106725 2635 #define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 2636 #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
Kojto 122:f9eeca106725 2637 #define CAN_RDL0R_DATA1_Pos (8U)
Kojto 122:f9eeca106725 2638 #define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 2639 #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
Kojto 122:f9eeca106725 2640 #define CAN_RDL0R_DATA2_Pos (16U)
Kojto 122:f9eeca106725 2641 #define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 2642 #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
Kojto 122:f9eeca106725 2643 #define CAN_RDL0R_DATA3_Pos (24U)
Kojto 122:f9eeca106725 2644 #define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 2645 #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
Kojto 122:f9eeca106725 2646
Kojto 122:f9eeca106725 2647 /******************* Bit definition for CAN_RDH0R register ******************/
Kojto 122:f9eeca106725 2648 #define CAN_RDH0R_DATA4_Pos (0U)
Kojto 122:f9eeca106725 2649 #define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 2650 #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
Kojto 122:f9eeca106725 2651 #define CAN_RDH0R_DATA5_Pos (8U)
Kojto 122:f9eeca106725 2652 #define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 2653 #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
Kojto 122:f9eeca106725 2654 #define CAN_RDH0R_DATA6_Pos (16U)
Kojto 122:f9eeca106725 2655 #define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 2656 #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
Kojto 122:f9eeca106725 2657 #define CAN_RDH0R_DATA7_Pos (24U)
Kojto 122:f9eeca106725 2658 #define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 2659 #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
Kojto 122:f9eeca106725 2660
Kojto 122:f9eeca106725 2661 /******************* Bit definition for CAN_RI1R register *******************/
Kojto 122:f9eeca106725 2662 #define CAN_RI1R_RTR_Pos (1U)
Kojto 122:f9eeca106725 2663 #define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2664 #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
Kojto 122:f9eeca106725 2665 #define CAN_RI1R_IDE_Pos (2U)
Kojto 122:f9eeca106725 2666 #define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2667 #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
Kojto 122:f9eeca106725 2668 #define CAN_RI1R_EXID_Pos (3U)
Kojto 122:f9eeca106725 2669 #define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
Kojto 122:f9eeca106725 2670 #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
Kojto 122:f9eeca106725 2671 #define CAN_RI1R_STID_Pos (21U)
Kojto 122:f9eeca106725 2672 #define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
Kojto 122:f9eeca106725 2673 #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
Kojto 122:f9eeca106725 2674
Kojto 122:f9eeca106725 2675 /******************* Bit definition for CAN_RDT1R register ******************/
Kojto 122:f9eeca106725 2676 #define CAN_RDT1R_DLC_Pos (0U)
Kojto 122:f9eeca106725 2677 #define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 2678 #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
Kojto 122:f9eeca106725 2679 #define CAN_RDT1R_FMI_Pos (8U)
Kojto 122:f9eeca106725 2680 #define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 2681 #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
Kojto 122:f9eeca106725 2682 #define CAN_RDT1R_TIME_Pos (16U)
Kojto 122:f9eeca106725 2683 #define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
Kojto 122:f9eeca106725 2684 #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
Kojto 122:f9eeca106725 2685
Kojto 122:f9eeca106725 2686 /******************* Bit definition for CAN_RDL1R register ******************/
Kojto 122:f9eeca106725 2687 #define CAN_RDL1R_DATA0_Pos (0U)
Kojto 122:f9eeca106725 2688 #define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 2689 #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
Kojto 122:f9eeca106725 2690 #define CAN_RDL1R_DATA1_Pos (8U)
Kojto 122:f9eeca106725 2691 #define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 2692 #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
Kojto 122:f9eeca106725 2693 #define CAN_RDL1R_DATA2_Pos (16U)
Kojto 122:f9eeca106725 2694 #define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 2695 #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
Kojto 122:f9eeca106725 2696 #define CAN_RDL1R_DATA3_Pos (24U)
Kojto 122:f9eeca106725 2697 #define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 2698 #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
Kojto 122:f9eeca106725 2699
Kojto 122:f9eeca106725 2700 /******************* Bit definition for CAN_RDH1R register ******************/
Kojto 122:f9eeca106725 2701 #define CAN_RDH1R_DATA4_Pos (0U)
Kojto 122:f9eeca106725 2702 #define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 2703 #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
Kojto 122:f9eeca106725 2704 #define CAN_RDH1R_DATA5_Pos (8U)
Kojto 122:f9eeca106725 2705 #define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 2706 #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
Kojto 122:f9eeca106725 2707 #define CAN_RDH1R_DATA6_Pos (16U)
Kojto 122:f9eeca106725 2708 #define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 2709 #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
Kojto 122:f9eeca106725 2710 #define CAN_RDH1R_DATA7_Pos (24U)
Kojto 122:f9eeca106725 2711 #define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 2712 #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
Kojto 122:f9eeca106725 2713
Kojto 122:f9eeca106725 2714 /*!<CAN filter registers */
Kojto 122:f9eeca106725 2715 /******************* Bit definition for CAN_FMR register ********************/
Kojto 122:f9eeca106725 2716 #define CAN_FMR_FINIT_Pos (0U)
Kojto 122:f9eeca106725 2717 #define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2718 #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
Kojto 122:f9eeca106725 2719
Kojto 122:f9eeca106725 2720 /******************* Bit definition for CAN_FM1R register *******************/
Kojto 122:f9eeca106725 2721 #define CAN_FM1R_FBM_Pos (0U)
Kojto 122:f9eeca106725 2722 #define CAN_FM1R_FBM_Msk (0x3FFFU << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */
Kojto 122:f9eeca106725 2723 #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
Kojto 122:f9eeca106725 2724 #define CAN_FM1R_FBM0_Pos (0U)
Kojto 122:f9eeca106725 2725 #define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2726 #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
Kojto 122:f9eeca106725 2727 #define CAN_FM1R_FBM1_Pos (1U)
Kojto 122:f9eeca106725 2728 #define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2729 #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
Kojto 122:f9eeca106725 2730 #define CAN_FM1R_FBM2_Pos (2U)
Kojto 122:f9eeca106725 2731 #define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2732 #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
Kojto 122:f9eeca106725 2733 #define CAN_FM1R_FBM3_Pos (3U)
Kojto 122:f9eeca106725 2734 #define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2735 #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
Kojto 122:f9eeca106725 2736 #define CAN_FM1R_FBM4_Pos (4U)
Kojto 122:f9eeca106725 2737 #define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 2738 #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
Kojto 122:f9eeca106725 2739 #define CAN_FM1R_FBM5_Pos (5U)
Kojto 122:f9eeca106725 2740 #define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 2741 #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
Kojto 122:f9eeca106725 2742 #define CAN_FM1R_FBM6_Pos (6U)
Kojto 122:f9eeca106725 2743 #define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 2744 #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
Kojto 122:f9eeca106725 2745 #define CAN_FM1R_FBM7_Pos (7U)
Kojto 122:f9eeca106725 2746 #define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 2747 #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
Kojto 122:f9eeca106725 2748 #define CAN_FM1R_FBM8_Pos (8U)
Kojto 122:f9eeca106725 2749 #define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2750 #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
Kojto 122:f9eeca106725 2751 #define CAN_FM1R_FBM9_Pos (9U)
Kojto 122:f9eeca106725 2752 #define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 2753 #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
Kojto 122:f9eeca106725 2754 #define CAN_FM1R_FBM10_Pos (10U)
Kojto 122:f9eeca106725 2755 #define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2756 #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
Kojto 122:f9eeca106725 2757 #define CAN_FM1R_FBM11_Pos (11U)
Kojto 122:f9eeca106725 2758 #define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 2759 #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
Kojto 122:f9eeca106725 2760 #define CAN_FM1R_FBM12_Pos (12U)
Kojto 122:f9eeca106725 2761 #define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 2762 #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
Kojto 122:f9eeca106725 2763 #define CAN_FM1R_FBM13_Pos (13U)
Kojto 122:f9eeca106725 2764 #define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 2765 #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
Kojto 122:f9eeca106725 2766
Kojto 122:f9eeca106725 2767 /******************* Bit definition for CAN_FS1R register *******************/
Kojto 122:f9eeca106725 2768 #define CAN_FS1R_FSC_Pos (0U)
Kojto 122:f9eeca106725 2769 #define CAN_FS1R_FSC_Msk (0x3FFFU << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */
Kojto 122:f9eeca106725 2770 #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
Kojto 122:f9eeca106725 2771 #define CAN_FS1R_FSC0_Pos (0U)
Kojto 122:f9eeca106725 2772 #define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2773 #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
Kojto 122:f9eeca106725 2774 #define CAN_FS1R_FSC1_Pos (1U)
Kojto 122:f9eeca106725 2775 #define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2776 #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
Kojto 122:f9eeca106725 2777 #define CAN_FS1R_FSC2_Pos (2U)
Kojto 122:f9eeca106725 2778 #define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2779 #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
Kojto 122:f9eeca106725 2780 #define CAN_FS1R_FSC3_Pos (3U)
Kojto 122:f9eeca106725 2781 #define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2782 #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
Kojto 122:f9eeca106725 2783 #define CAN_FS1R_FSC4_Pos (4U)
Kojto 122:f9eeca106725 2784 #define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 2785 #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
Kojto 122:f9eeca106725 2786 #define CAN_FS1R_FSC5_Pos (5U)
Kojto 122:f9eeca106725 2787 #define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 2788 #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
Kojto 122:f9eeca106725 2789 #define CAN_FS1R_FSC6_Pos (6U)
Kojto 122:f9eeca106725 2790 #define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 2791 #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
Kojto 122:f9eeca106725 2792 #define CAN_FS1R_FSC7_Pos (7U)
Kojto 122:f9eeca106725 2793 #define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 2794 #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
Kojto 122:f9eeca106725 2795 #define CAN_FS1R_FSC8_Pos (8U)
Kojto 122:f9eeca106725 2796 #define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2797 #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
Kojto 122:f9eeca106725 2798 #define CAN_FS1R_FSC9_Pos (9U)
Kojto 122:f9eeca106725 2799 #define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 2800 #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
Kojto 122:f9eeca106725 2801 #define CAN_FS1R_FSC10_Pos (10U)
Kojto 122:f9eeca106725 2802 #define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2803 #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
Kojto 122:f9eeca106725 2804 #define CAN_FS1R_FSC11_Pos (11U)
Kojto 122:f9eeca106725 2805 #define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 2806 #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
Kojto 122:f9eeca106725 2807 #define CAN_FS1R_FSC12_Pos (12U)
Kojto 122:f9eeca106725 2808 #define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 2809 #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
Kojto 122:f9eeca106725 2810 #define CAN_FS1R_FSC13_Pos (13U)
Kojto 122:f9eeca106725 2811 #define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 2812 #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
Kojto 122:f9eeca106725 2813
Kojto 122:f9eeca106725 2814 /****************** Bit definition for CAN_FFA1R register *******************/
Kojto 122:f9eeca106725 2815 #define CAN_FFA1R_FFA_Pos (0U)
Kojto 122:f9eeca106725 2816 #define CAN_FFA1R_FFA_Msk (0x3FFFU << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */
Kojto 122:f9eeca106725 2817 #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
Kojto 122:f9eeca106725 2818 #define CAN_FFA1R_FFA0_Pos (0U)
Kojto 122:f9eeca106725 2819 #define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2820 #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment for Filter 0 */
Kojto 122:f9eeca106725 2821 #define CAN_FFA1R_FFA1_Pos (1U)
Kojto 122:f9eeca106725 2822 #define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2823 #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment for Filter 1 */
Kojto 122:f9eeca106725 2824 #define CAN_FFA1R_FFA2_Pos (2U)
Kojto 122:f9eeca106725 2825 #define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2826 #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment for Filter 2 */
Kojto 122:f9eeca106725 2827 #define CAN_FFA1R_FFA3_Pos (3U)
Kojto 122:f9eeca106725 2828 #define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2829 #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment for Filter 3 */
Kojto 122:f9eeca106725 2830 #define CAN_FFA1R_FFA4_Pos (4U)
Kojto 122:f9eeca106725 2831 #define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 2832 #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment for Filter 4 */
Kojto 122:f9eeca106725 2833 #define CAN_FFA1R_FFA5_Pos (5U)
Kojto 122:f9eeca106725 2834 #define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 2835 #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment for Filter 5 */
Kojto 122:f9eeca106725 2836 #define CAN_FFA1R_FFA6_Pos (6U)
Kojto 122:f9eeca106725 2837 #define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 2838 #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment for Filter 6 */
Kojto 122:f9eeca106725 2839 #define CAN_FFA1R_FFA7_Pos (7U)
Kojto 122:f9eeca106725 2840 #define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 2841 #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment for Filter 7 */
Kojto 122:f9eeca106725 2842 #define CAN_FFA1R_FFA8_Pos (8U)
Kojto 122:f9eeca106725 2843 #define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2844 #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment for Filter 8 */
Kojto 122:f9eeca106725 2845 #define CAN_FFA1R_FFA9_Pos (9U)
Kojto 122:f9eeca106725 2846 #define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 2847 #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment for Filter 9 */
Kojto 122:f9eeca106725 2848 #define CAN_FFA1R_FFA10_Pos (10U)
Kojto 122:f9eeca106725 2849 #define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2850 #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment for Filter 10 */
Kojto 122:f9eeca106725 2851 #define CAN_FFA1R_FFA11_Pos (11U)
Kojto 122:f9eeca106725 2852 #define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 2853 #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment for Filter 11 */
Kojto 122:f9eeca106725 2854 #define CAN_FFA1R_FFA12_Pos (12U)
Kojto 122:f9eeca106725 2855 #define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 2856 #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment for Filter 12 */
Kojto 122:f9eeca106725 2857 #define CAN_FFA1R_FFA13_Pos (13U)
Kojto 122:f9eeca106725 2858 #define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 2859 #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment for Filter 13 */
Kojto 122:f9eeca106725 2860
Kojto 122:f9eeca106725 2861 /******************* Bit definition for CAN_FA1R register *******************/
Kojto 122:f9eeca106725 2862 #define CAN_FA1R_FACT_Pos (0U)
Kojto 122:f9eeca106725 2863 #define CAN_FA1R_FACT_Msk (0x3FFFU << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */
Kojto 122:f9eeca106725 2864 #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
Kojto 122:f9eeca106725 2865 #define CAN_FA1R_FACT0_Pos (0U)
Kojto 122:f9eeca106725 2866 #define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2867 #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter 0 Active */
Kojto 122:f9eeca106725 2868 #define CAN_FA1R_FACT1_Pos (1U)
Kojto 122:f9eeca106725 2869 #define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2870 #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter 1 Active */
Kojto 122:f9eeca106725 2871 #define CAN_FA1R_FACT2_Pos (2U)
Kojto 122:f9eeca106725 2872 #define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2873 #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter 2 Active */
Kojto 122:f9eeca106725 2874 #define CAN_FA1R_FACT3_Pos (3U)
Kojto 122:f9eeca106725 2875 #define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2876 #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter 3 Active */
Kojto 122:f9eeca106725 2877 #define CAN_FA1R_FACT4_Pos (4U)
Kojto 122:f9eeca106725 2878 #define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 2879 #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter 4 Active */
Kojto 122:f9eeca106725 2880 #define CAN_FA1R_FACT5_Pos (5U)
Kojto 122:f9eeca106725 2881 #define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 2882 #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter 5 Active */
Kojto 122:f9eeca106725 2883 #define CAN_FA1R_FACT6_Pos (6U)
Kojto 122:f9eeca106725 2884 #define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 2885 #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter 6 Active */
Kojto 122:f9eeca106725 2886 #define CAN_FA1R_FACT7_Pos (7U)
Kojto 122:f9eeca106725 2887 #define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 2888 #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter 7 Active */
Kojto 122:f9eeca106725 2889 #define CAN_FA1R_FACT8_Pos (8U)
Kojto 122:f9eeca106725 2890 #define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2891 #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter 8 Active */
Kojto 122:f9eeca106725 2892 #define CAN_FA1R_FACT9_Pos (9U)
Kojto 122:f9eeca106725 2893 #define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 2894 #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter 9 Active */
Kojto 122:f9eeca106725 2895 #define CAN_FA1R_FACT10_Pos (10U)
Kojto 122:f9eeca106725 2896 #define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2897 #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter 10 Active */
Kojto 122:f9eeca106725 2898 #define CAN_FA1R_FACT11_Pos (11U)
Kojto 122:f9eeca106725 2899 #define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 2900 #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter 11 Active */
Kojto 122:f9eeca106725 2901 #define CAN_FA1R_FACT12_Pos (12U)
Kojto 122:f9eeca106725 2902 #define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 2903 #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter 12 Active */
Kojto 122:f9eeca106725 2904 #define CAN_FA1R_FACT13_Pos (13U)
Kojto 122:f9eeca106725 2905 #define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 2906 #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter 13 Active */
Kojto 122:f9eeca106725 2907
Kojto 122:f9eeca106725 2908 /******************* Bit definition for CAN_F0R1 register *******************/
Kojto 122:f9eeca106725 2909 #define CAN_F0R1_FB0_Pos (0U)
Kojto 122:f9eeca106725 2910 #define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2911 #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2912 #define CAN_F0R1_FB1_Pos (1U)
Kojto 122:f9eeca106725 2913 #define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2914 #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2915 #define CAN_F0R1_FB2_Pos (2U)
Kojto 122:f9eeca106725 2916 #define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2917 #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2918 #define CAN_F0R1_FB3_Pos (3U)
Kojto 122:f9eeca106725 2919 #define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2920 #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2921 #define CAN_F0R1_FB4_Pos (4U)
Kojto 122:f9eeca106725 2922 #define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 2923 #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2924 #define CAN_F0R1_FB5_Pos (5U)
Kojto 122:f9eeca106725 2925 #define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 2926 #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2927 #define CAN_F0R1_FB6_Pos (6U)
Kojto 122:f9eeca106725 2928 #define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 2929 #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2930 #define CAN_F0R1_FB7_Pos (7U)
Kojto 122:f9eeca106725 2931 #define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 2932 #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2933 #define CAN_F0R1_FB8_Pos (8U)
Kojto 122:f9eeca106725 2934 #define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2935 #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2936 #define CAN_F0R1_FB9_Pos (9U)
Kojto 122:f9eeca106725 2937 #define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 2938 #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2939 #define CAN_F0R1_FB10_Pos (10U)
Kojto 122:f9eeca106725 2940 #define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2941 #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2942 #define CAN_F0R1_FB11_Pos (11U)
Kojto 122:f9eeca106725 2943 #define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 2944 #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2945 #define CAN_F0R1_FB12_Pos (12U)
Kojto 122:f9eeca106725 2946 #define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 2947 #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2948 #define CAN_F0R1_FB13_Pos (13U)
Kojto 122:f9eeca106725 2949 #define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 2950 #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2951 #define CAN_F0R1_FB14_Pos (14U)
Kojto 122:f9eeca106725 2952 #define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 2953 #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2954 #define CAN_F0R1_FB15_Pos (15U)
Kojto 122:f9eeca106725 2955 #define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 2956 #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2957 #define CAN_F0R1_FB16_Pos (16U)
Kojto 122:f9eeca106725 2958 #define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 2959 #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2960 #define CAN_F0R1_FB17_Pos (17U)
Kojto 122:f9eeca106725 2961 #define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 2962 #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2963 #define CAN_F0R1_FB18_Pos (18U)
Kojto 122:f9eeca106725 2964 #define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 2965 #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2966 #define CAN_F0R1_FB19_Pos (19U)
Kojto 122:f9eeca106725 2967 #define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 2968 #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2969 #define CAN_F0R1_FB20_Pos (20U)
Kojto 122:f9eeca106725 2970 #define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 2971 #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2972 #define CAN_F0R1_FB21_Pos (21U)
Kojto 122:f9eeca106725 2973 #define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 2974 #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2975 #define CAN_F0R1_FB22_Pos (22U)
Kojto 122:f9eeca106725 2976 #define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 2977 #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2978 #define CAN_F0R1_FB23_Pos (23U)
Kojto 122:f9eeca106725 2979 #define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 2980 #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2981 #define CAN_F0R1_FB24_Pos (24U)
Kojto 122:f9eeca106725 2982 #define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 2983 #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2984 #define CAN_F0R1_FB25_Pos (25U)
Kojto 122:f9eeca106725 2985 #define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 2986 #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2987 #define CAN_F0R1_FB26_Pos (26U)
Kojto 122:f9eeca106725 2988 #define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 2989 #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2990 #define CAN_F0R1_FB27_Pos (27U)
Kojto 122:f9eeca106725 2991 #define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 2992 #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2993 #define CAN_F0R1_FB28_Pos (28U)
Kojto 122:f9eeca106725 2994 #define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 2995 #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2996 #define CAN_F0R1_FB29_Pos (29U)
Kojto 122:f9eeca106725 2997 #define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 2998 #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2999 #define CAN_F0R1_FB30_Pos (30U)
Kojto 122:f9eeca106725 3000 #define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 3001 #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 3002 #define CAN_F0R1_FB31_Pos (31U)
Kojto 122:f9eeca106725 3003 #define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 3004 #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
Kojto 122:f9eeca106725 3005
Kojto 122:f9eeca106725 3006 /******************* Bit definition for CAN_F1R1 register *******************/
Kojto 122:f9eeca106725 3007 #define CAN_F1R1_FB0_Pos (0U)
Kojto 122:f9eeca106725 3008 #define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3009 #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 3010 #define CAN_F1R1_FB1_Pos (1U)
Kojto 122:f9eeca106725 3011 #define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3012 #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 3013 #define CAN_F1R1_FB2_Pos (2U)
Kojto 122:f9eeca106725 3014 #define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 3015 #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 3016 #define CAN_F1R1_FB3_Pos (3U)
Kojto 122:f9eeca106725 3017 #define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 3018 #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 3019 #define CAN_F1R1_FB4_Pos (4U)
Kojto 122:f9eeca106725 3020 #define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3021 #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 3022 #define CAN_F1R1_FB5_Pos (5U)
Kojto 122:f9eeca106725 3023 #define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 3024 #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 3025 #define CAN_F1R1_FB6_Pos (6U)
Kojto 122:f9eeca106725 3026 #define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 3027 #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 3028 #define CAN_F1R1_FB7_Pos (7U)
Kojto 122:f9eeca106725 3029 #define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 3030 #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 3031 #define CAN_F1R1_FB8_Pos (8U)
Kojto 122:f9eeca106725 3032 #define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 3033 #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 3034 #define CAN_F1R1_FB9_Pos (9U)
Kojto 122:f9eeca106725 3035 #define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 3036 #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 3037 #define CAN_F1R1_FB10_Pos (10U)
Kojto 122:f9eeca106725 3038 #define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 3039 #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 3040 #define CAN_F1R1_FB11_Pos (11U)
Kojto 122:f9eeca106725 3041 #define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 3042 #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 3043 #define CAN_F1R1_FB12_Pos (12U)
Kojto 122:f9eeca106725 3044 #define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 3045 #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 3046 #define CAN_F1R1_FB13_Pos (13U)
Kojto 122:f9eeca106725 3047 #define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 3048 #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 3049 #define CAN_F1R1_FB14_Pos (14U)
Kojto 122:f9eeca106725 3050 #define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 3051 #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 3052 #define CAN_F1R1_FB15_Pos (15U)
Kojto 122:f9eeca106725 3053 #define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 3054 #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 3055 #define CAN_F1R1_FB16_Pos (16U)
Kojto 122:f9eeca106725 3056 #define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 3057 #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 3058 #define CAN_F1R1_FB17_Pos (17U)
Kojto 122:f9eeca106725 3059 #define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 3060 #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 3061 #define CAN_F1R1_FB18_Pos (18U)
Kojto 122:f9eeca106725 3062 #define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 3063 #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 3064 #define CAN_F1R1_FB19_Pos (19U)
Kojto 122:f9eeca106725 3065 #define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 3066 #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 3067 #define CAN_F1R1_FB20_Pos (20U)
Kojto 122:f9eeca106725 3068 #define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 3069 #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 3070 #define CAN_F1R1_FB21_Pos (21U)
Kojto 122:f9eeca106725 3071 #define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 3072 #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 3073 #define CAN_F1R1_FB22_Pos (22U)
Kojto 122:f9eeca106725 3074 #define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 3075 #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 3076 #define CAN_F1R1_FB23_Pos (23U)
Kojto 122:f9eeca106725 3077 #define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 3078 #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 3079 #define CAN_F1R1_FB24_Pos (24U)
Kojto 122:f9eeca106725 3080 #define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 3081 #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 3082 #define CAN_F1R1_FB25_Pos (25U)
Kojto 122:f9eeca106725 3083 #define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 3084 #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 3085 #define CAN_F1R1_FB26_Pos (26U)
Kojto 122:f9eeca106725 3086 #define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 3087 #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 3088 #define CAN_F1R1_FB27_Pos (27U)
Kojto 122:f9eeca106725 3089 #define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 3090 #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 3091 #define CAN_F1R1_FB28_Pos (28U)
Kojto 122:f9eeca106725 3092 #define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 3093 #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 3094 #define CAN_F1R1_FB29_Pos (29U)
Kojto 122:f9eeca106725 3095 #define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 3096 #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 3097 #define CAN_F1R1_FB30_Pos (30U)
Kojto 122:f9eeca106725 3098 #define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 3099 #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 3100 #define CAN_F1R1_FB31_Pos (31U)
Kojto 122:f9eeca106725 3101 #define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 3102 #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
Kojto 122:f9eeca106725 3103
Kojto 122:f9eeca106725 3104 /******************* Bit definition for CAN_F2R1 register *******************/
Kojto 122:f9eeca106725 3105 #define CAN_F2R1_FB0_Pos (0U)
Kojto 122:f9eeca106725 3106 #define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3107 #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 3108 #define CAN_F2R1_FB1_Pos (1U)
Kojto 122:f9eeca106725 3109 #define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3110 #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 3111 #define CAN_F2R1_FB2_Pos (2U)
Kojto 122:f9eeca106725 3112 #define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 3113 #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 3114 #define CAN_F2R1_FB3_Pos (3U)
Kojto 122:f9eeca106725 3115 #define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 3116 #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 3117 #define CAN_F2R1_FB4_Pos (4U)
Kojto 122:f9eeca106725 3118 #define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3119 #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 3120 #define CAN_F2R1_FB5_Pos (5U)
Kojto 122:f9eeca106725 3121 #define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 3122 #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 3123 #define CAN_F2R1_FB6_Pos (6U)
Kojto 122:f9eeca106725 3124 #define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 3125 #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 3126 #define CAN_F2R1_FB7_Pos (7U)
Kojto 122:f9eeca106725 3127 #define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 3128 #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 3129 #define CAN_F2R1_FB8_Pos (8U)
Kojto 122:f9eeca106725 3130 #define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 3131 #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 3132 #define CAN_F2R1_FB9_Pos (9U)
Kojto 122:f9eeca106725 3133 #define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 3134 #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 3135 #define CAN_F2R1_FB10_Pos (10U)
Kojto 122:f9eeca106725 3136 #define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 3137 #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 3138 #define CAN_F2R1_FB11_Pos (11U)
Kojto 122:f9eeca106725 3139 #define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 3140 #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 3141 #define CAN_F2R1_FB12_Pos (12U)
Kojto 122:f9eeca106725 3142 #define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 3143 #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 3144 #define CAN_F2R1_FB13_Pos (13U)
Kojto 122:f9eeca106725 3145 #define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 3146 #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 3147 #define CAN_F2R1_FB14_Pos (14U)
Kojto 122:f9eeca106725 3148 #define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 3149 #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 3150 #define CAN_F2R1_FB15_Pos (15U)
Kojto 122:f9eeca106725 3151 #define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 3152 #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 3153 #define CAN_F2R1_FB16_Pos (16U)
Kojto 122:f9eeca106725 3154 #define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 3155 #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 3156 #define CAN_F2R1_FB17_Pos (17U)
Kojto 122:f9eeca106725 3157 #define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 3158 #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 3159 #define CAN_F2R1_FB18_Pos (18U)
Kojto 122:f9eeca106725 3160 #define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 3161 #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 3162 #define CAN_F2R1_FB19_Pos (19U)
Kojto 122:f9eeca106725 3163 #define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 3164 #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 3165 #define CAN_F2R1_FB20_Pos (20U)
Kojto 122:f9eeca106725 3166 #define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 3167 #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 3168 #define CAN_F2R1_FB21_Pos (21U)
Kojto 122:f9eeca106725 3169 #define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 3170 #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 3171 #define CAN_F2R1_FB22_Pos (22U)
Kojto 122:f9eeca106725 3172 #define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 3173 #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 3174 #define CAN_F2R1_FB23_Pos (23U)
Kojto 122:f9eeca106725 3175 #define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 3176 #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 3177 #define CAN_F2R1_FB24_Pos (24U)
Kojto 122:f9eeca106725 3178 #define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 3179 #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 3180 #define CAN_F2R1_FB25_Pos (25U)
Kojto 122:f9eeca106725 3181 #define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 3182 #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 3183 #define CAN_F2R1_FB26_Pos (26U)
Kojto 122:f9eeca106725 3184 #define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 3185 #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 3186 #define CAN_F2R1_FB27_Pos (27U)
Kojto 122:f9eeca106725 3187 #define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 3188 #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 3189 #define CAN_F2R1_FB28_Pos (28U)
Kojto 122:f9eeca106725 3190 #define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 3191 #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 3192 #define CAN_F2R1_FB29_Pos (29U)
Kojto 122:f9eeca106725 3193 #define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 3194 #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 3195 #define CAN_F2R1_FB30_Pos (30U)
Kojto 122:f9eeca106725 3196 #define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 3197 #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 3198 #define CAN_F2R1_FB31_Pos (31U)
Kojto 122:f9eeca106725 3199 #define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 3200 #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
Kojto 122:f9eeca106725 3201
Kojto 122:f9eeca106725 3202 /******************* Bit definition for CAN_F3R1 register *******************/
Kojto 122:f9eeca106725 3203 #define CAN_F3R1_FB0_Pos (0U)
Kojto 122:f9eeca106725 3204 #define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3205 #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 3206 #define CAN_F3R1_FB1_Pos (1U)
Kojto 122:f9eeca106725 3207 #define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3208 #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 3209 #define CAN_F3R1_FB2_Pos (2U)
Kojto 122:f9eeca106725 3210 #define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 3211 #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 3212 #define CAN_F3R1_FB3_Pos (3U)
Kojto 122:f9eeca106725 3213 #define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 3214 #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 3215 #define CAN_F3R1_FB4_Pos (4U)
Kojto 122:f9eeca106725 3216 #define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3217 #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 3218 #define CAN_F3R1_FB5_Pos (5U)
Kojto 122:f9eeca106725 3219 #define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 3220 #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 3221 #define CAN_F3R1_FB6_Pos (6U)
Kojto 122:f9eeca106725 3222 #define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 3223 #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 3224 #define CAN_F3R1_FB7_Pos (7U)
Kojto 122:f9eeca106725 3225 #define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 3226 #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 3227 #define CAN_F3R1_FB8_Pos (8U)
Kojto 122:f9eeca106725 3228 #define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 3229 #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 3230 #define CAN_F3R1_FB9_Pos (9U)
Kojto 122:f9eeca106725 3231 #define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 3232 #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 3233 #define CAN_F3R1_FB10_Pos (10U)
Kojto 122:f9eeca106725 3234 #define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 3235 #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 3236 #define CAN_F3R1_FB11_Pos (11U)
Kojto 122:f9eeca106725 3237 #define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 3238 #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 3239 #define CAN_F3R1_FB12_Pos (12U)
Kojto 122:f9eeca106725 3240 #define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 3241 #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 3242 #define CAN_F3R1_FB13_Pos (13U)
Kojto 122:f9eeca106725 3243 #define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 3244 #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 3245 #define CAN_F3R1_FB14_Pos (14U)
Kojto 122:f9eeca106725 3246 #define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 3247 #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 3248 #define CAN_F3R1_FB15_Pos (15U)
Kojto 122:f9eeca106725 3249 #define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 3250 #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 3251 #define CAN_F3R1_FB16_Pos (16U)
Kojto 122:f9eeca106725 3252 #define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 3253 #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 3254 #define CAN_F3R1_FB17_Pos (17U)
Kojto 122:f9eeca106725 3255 #define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 3256 #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 3257 #define CAN_F3R1_FB18_Pos (18U)
Kojto 122:f9eeca106725 3258 #define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 3259 #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 3260 #define CAN_F3R1_FB19_Pos (19U)
Kojto 122:f9eeca106725 3261 #define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 3262 #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 3263 #define CAN_F3R1_FB20_Pos (20U)
Kojto 122:f9eeca106725 3264 #define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 3265 #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 3266 #define CAN_F3R1_FB21_Pos (21U)
Kojto 122:f9eeca106725 3267 #define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 3268 #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 3269 #define CAN_F3R1_FB22_Pos (22U)
Kojto 122:f9eeca106725 3270 #define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 3271 #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 3272 #define CAN_F3R1_FB23_Pos (23U)
Kojto 122:f9eeca106725 3273 #define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 3274 #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 3275 #define CAN_F3R1_FB24_Pos (24U)
Kojto 122:f9eeca106725 3276 #define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 3277 #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 3278 #define CAN_F3R1_FB25_Pos (25U)
Kojto 122:f9eeca106725 3279 #define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 3280 #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 3281 #define CAN_F3R1_FB26_Pos (26U)
Kojto 122:f9eeca106725 3282 #define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 3283 #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 3284 #define CAN_F3R1_FB27_Pos (27U)
Kojto 122:f9eeca106725 3285 #define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 3286 #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 3287 #define CAN_F3R1_FB28_Pos (28U)
Kojto 122:f9eeca106725 3288 #define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 3289 #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 3290 #define CAN_F3R1_FB29_Pos (29U)
Kojto 122:f9eeca106725 3291 #define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 3292 #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 3293 #define CAN_F3R1_FB30_Pos (30U)
Kojto 122:f9eeca106725 3294 #define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 3295 #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 3296 #define CAN_F3R1_FB31_Pos (31U)
Kojto 122:f9eeca106725 3297 #define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 3298 #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
Kojto 122:f9eeca106725 3299
Kojto 122:f9eeca106725 3300 /******************* Bit definition for CAN_F4R1 register *******************/
Kojto 122:f9eeca106725 3301 #define CAN_F4R1_FB0_Pos (0U)
Kojto 122:f9eeca106725 3302 #define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3303 #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 3304 #define CAN_F4R1_FB1_Pos (1U)
Kojto 122:f9eeca106725 3305 #define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3306 #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 3307 #define CAN_F4R1_FB2_Pos (2U)
Kojto 122:f9eeca106725 3308 #define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 3309 #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 3310 #define CAN_F4R1_FB3_Pos (3U)
Kojto 122:f9eeca106725 3311 #define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 3312 #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 3313 #define CAN_F4R1_FB4_Pos (4U)
Kojto 122:f9eeca106725 3314 #define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3315 #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 3316 #define CAN_F4R1_FB5_Pos (5U)
Kojto 122:f9eeca106725 3317 #define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 3318 #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 3319 #define CAN_F4R1_FB6_Pos (6U)
Kojto 122:f9eeca106725 3320 #define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 3321 #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 3322 #define CAN_F4R1_FB7_Pos (7U)
Kojto 122:f9eeca106725 3323 #define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 3324 #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 3325 #define CAN_F4R1_FB8_Pos (8U)
Kojto 122:f9eeca106725 3326 #define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 3327 #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 3328 #define CAN_F4R1_FB9_Pos (9U)
Kojto 122:f9eeca106725 3329 #define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 3330 #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 3331 #define CAN_F4R1_FB10_Pos (10U)
Kojto 122:f9eeca106725 3332 #define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 3333 #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 3334 #define CAN_F4R1_FB11_Pos (11U)
Kojto 122:f9eeca106725 3335 #define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 3336 #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 3337 #define CAN_F4R1_FB12_Pos (12U)
Kojto 122:f9eeca106725 3338 #define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 3339 #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 3340 #define CAN_F4R1_FB13_Pos (13U)
Kojto 122:f9eeca106725 3341 #define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 3342 #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 3343 #define CAN_F4R1_FB14_Pos (14U)
Kojto 122:f9eeca106725 3344 #define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 3345 #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 3346 #define CAN_F4R1_FB15_Pos (15U)
Kojto 122:f9eeca106725 3347 #define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 3348 #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 3349 #define CAN_F4R1_FB16_Pos (16U)
Kojto 122:f9eeca106725 3350 #define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 3351 #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 3352 #define CAN_F4R1_FB17_Pos (17U)
Kojto 122:f9eeca106725 3353 #define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 3354 #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 3355 #define CAN_F4R1_FB18_Pos (18U)
Kojto 122:f9eeca106725 3356 #define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 3357 #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 3358 #define CAN_F4R1_FB19_Pos (19U)
Kojto 122:f9eeca106725 3359 #define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 3360 #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 3361 #define CAN_F4R1_FB20_Pos (20U)
Kojto 122:f9eeca106725 3362 #define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 3363 #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 3364 #define CAN_F4R1_FB21_Pos (21U)
Kojto 122:f9eeca106725 3365 #define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 3366 #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 3367 #define CAN_F4R1_FB22_Pos (22U)
Kojto 122:f9eeca106725 3368 #define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 3369 #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 3370 #define CAN_F4R1_FB23_Pos (23U)
Kojto 122:f9eeca106725 3371 #define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 3372 #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 3373 #define CAN_F4R1_FB24_Pos (24U)
Kojto 122:f9eeca106725 3374 #define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 3375 #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 3376 #define CAN_F4R1_FB25_Pos (25U)
Kojto 122:f9eeca106725 3377 #define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 3378 #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 3379 #define CAN_F4R1_FB26_Pos (26U)
Kojto 122:f9eeca106725 3380 #define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 3381 #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 3382 #define CAN_F4R1_FB27_Pos (27U)
Kojto 122:f9eeca106725 3383 #define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 3384 #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 3385 #define CAN_F4R1_FB28_Pos (28U)
Kojto 122:f9eeca106725 3386 #define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 3387 #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 3388 #define CAN_F4R1_FB29_Pos (29U)
Kojto 122:f9eeca106725 3389 #define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 3390 #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 3391 #define CAN_F4R1_FB30_Pos (30U)
Kojto 122:f9eeca106725 3392 #define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 3393 #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 3394 #define CAN_F4R1_FB31_Pos (31U)
Kojto 122:f9eeca106725 3395 #define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 3396 #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
Kojto 122:f9eeca106725 3397
Kojto 122:f9eeca106725 3398 /******************* Bit definition for CAN_F5R1 register *******************/
Kojto 122:f9eeca106725 3399 #define CAN_F5R1_FB0_Pos (0U)
Kojto 122:f9eeca106725 3400 #define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3401 #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 3402 #define CAN_F5R1_FB1_Pos (1U)
Kojto 122:f9eeca106725 3403 #define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3404 #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 3405 #define CAN_F5R1_FB2_Pos (2U)
Kojto 122:f9eeca106725 3406 #define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 3407 #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 3408 #define CAN_F5R1_FB3_Pos (3U)
Kojto 122:f9eeca106725 3409 #define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 3410 #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 3411 #define CAN_F5R1_FB4_Pos (4U)
Kojto 122:f9eeca106725 3412 #define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3413 #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 3414 #define CAN_F5R1_FB5_Pos (5U)
Kojto 122:f9eeca106725 3415 #define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 3416 #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 3417 #define CAN_F5R1_FB6_Pos (6U)
Kojto 122:f9eeca106725 3418 #define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 3419 #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 3420 #define CAN_F5R1_FB7_Pos (7U)
Kojto 122:f9eeca106725 3421 #define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 3422 #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 3423 #define CAN_F5R1_FB8_Pos (8U)
Kojto 122:f9eeca106725 3424 #define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 3425 #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 3426 #define CAN_F5R1_FB9_Pos (9U)
Kojto 122:f9eeca106725 3427 #define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 3428 #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 3429 #define CAN_F5R1_FB10_Pos (10U)
Kojto 122:f9eeca106725 3430 #define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 3431 #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 3432 #define CAN_F5R1_FB11_Pos (11U)
Kojto 122:f9eeca106725 3433 #define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 3434 #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 3435 #define CAN_F5R1_FB12_Pos (12U)
Kojto 122:f9eeca106725 3436 #define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 3437 #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 3438 #define CAN_F5R1_FB13_Pos (13U)
Kojto 122:f9eeca106725 3439 #define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 3440 #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 3441 #define CAN_F5R1_FB14_Pos (14U)
Kojto 122:f9eeca106725 3442 #define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 3443 #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 3444 #define CAN_F5R1_FB15_Pos (15U)
Kojto 122:f9eeca106725 3445 #define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 3446 #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 3447 #define CAN_F5R1_FB16_Pos (16U)
Kojto 122:f9eeca106725 3448 #define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 3449 #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 3450 #define CAN_F5R1_FB17_Pos (17U)
Kojto 122:f9eeca106725 3451 #define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 3452 #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 3453 #define CAN_F5R1_FB18_Pos (18U)
Kojto 122:f9eeca106725 3454 #define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 3455 #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 3456 #define CAN_F5R1_FB19_Pos (19U)
Kojto 122:f9eeca106725 3457 #define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 3458 #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 3459 #define CAN_F5R1_FB20_Pos (20U)
Kojto 122:f9eeca106725 3460 #define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 3461 #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 3462 #define CAN_F5R1_FB21_Pos (21U)
Kojto 122:f9eeca106725 3463 #define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 3464 #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 3465 #define CAN_F5R1_FB22_Pos (22U)
Kojto 122:f9eeca106725 3466 #define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 3467 #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 3468 #define CAN_F5R1_FB23_Pos (23U)
Kojto 122:f9eeca106725 3469 #define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 3470 #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 3471 #define CAN_F5R1_FB24_Pos (24U)
Kojto 122:f9eeca106725 3472 #define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 3473 #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 3474 #define CAN_F5R1_FB25_Pos (25U)
Kojto 122:f9eeca106725 3475 #define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 3476 #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 3477 #define CAN_F5R1_FB26_Pos (26U)
Kojto 122:f9eeca106725 3478 #define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 3479 #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 3480 #define CAN_F5R1_FB27_Pos (27U)
Kojto 122:f9eeca106725 3481 #define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 3482 #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 3483 #define CAN_F5R1_FB28_Pos (28U)
Kojto 122:f9eeca106725 3484 #define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 3485 #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 3486 #define CAN_F5R1_FB29_Pos (29U)
Kojto 122:f9eeca106725 3487 #define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 3488 #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 3489 #define CAN_F5R1_FB30_Pos (30U)
Kojto 122:f9eeca106725 3490 #define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 3491 #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 3492 #define CAN_F5R1_FB31_Pos (31U)
Kojto 122:f9eeca106725 3493 #define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 3494 #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
Kojto 122:f9eeca106725 3495
Kojto 122:f9eeca106725 3496 /******************* Bit definition for CAN_F6R1 register *******************/
Kojto 122:f9eeca106725 3497 #define CAN_F6R1_FB0_Pos (0U)
Kojto 122:f9eeca106725 3498 #define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3499 #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 3500 #define CAN_F6R1_FB1_Pos (1U)
Kojto 122:f9eeca106725 3501 #define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3502 #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 3503 #define CAN_F6R1_FB2_Pos (2U)
Kojto 122:f9eeca106725 3504 #define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 3505 #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 3506 #define CAN_F6R1_FB3_Pos (3U)
Kojto 122:f9eeca106725 3507 #define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 3508 #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 3509 #define CAN_F6R1_FB4_Pos (4U)
Kojto 122:f9eeca106725 3510 #define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3511 #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 3512 #define CAN_F6R1_FB5_Pos (5U)
Kojto 122:f9eeca106725 3513 #define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 3514 #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 3515 #define CAN_F6R1_FB6_Pos (6U)
Kojto 122:f9eeca106725 3516 #define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 3517 #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 3518 #define CAN_F6R1_FB7_Pos (7U)
Kojto 122:f9eeca106725 3519 #define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 3520 #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 3521 #define CAN_F6R1_FB8_Pos (8U)
Kojto 122:f9eeca106725 3522 #define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 3523 #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 3524 #define CAN_F6R1_FB9_Pos (9U)
Kojto 122:f9eeca106725 3525 #define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 3526 #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 3527 #define CAN_F6R1_FB10_Pos (10U)
Kojto 122:f9eeca106725 3528 #define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 3529 #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 3530 #define CAN_F6R1_FB11_Pos (11U)
Kojto 122:f9eeca106725 3531 #define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 3532 #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 3533 #define CAN_F6R1_FB12_Pos (12U)
Kojto 122:f9eeca106725 3534 #define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 3535 #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 3536 #define CAN_F6R1_FB13_Pos (13U)
Kojto 122:f9eeca106725 3537 #define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 3538 #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 3539 #define CAN_F6R1_FB14_Pos (14U)
Kojto 122:f9eeca106725 3540 #define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 3541 #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 3542 #define CAN_F6R1_FB15_Pos (15U)
Kojto 122:f9eeca106725 3543 #define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 3544 #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 3545 #define CAN_F6R1_FB16_Pos (16U)
Kojto 122:f9eeca106725 3546 #define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 3547 #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 3548 #define CAN_F6R1_FB17_Pos (17U)
Kojto 122:f9eeca106725 3549 #define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 3550 #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 3551 #define CAN_F6R1_FB18_Pos (18U)
Kojto 122:f9eeca106725 3552 #define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 3553 #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 3554 #define CAN_F6R1_FB19_Pos (19U)
Kojto 122:f9eeca106725 3555 #define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 3556 #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 3557 #define CAN_F6R1_FB20_Pos (20U)
Kojto 122:f9eeca106725 3558 #define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 3559 #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 3560 #define CAN_F6R1_FB21_Pos (21U)
Kojto 122:f9eeca106725 3561 #define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 3562 #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 3563 #define CAN_F6R1_FB22_Pos (22U)
Kojto 122:f9eeca106725 3564 #define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 3565 #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 3566 #define CAN_F6R1_FB23_Pos (23U)
Kojto 122:f9eeca106725 3567 #define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 3568 #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 3569 #define CAN_F6R1_FB24_Pos (24U)
Kojto 122:f9eeca106725 3570 #define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 3571 #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 3572 #define CAN_F6R1_FB25_Pos (25U)
Kojto 122:f9eeca106725 3573 #define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 3574 #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 3575 #define CAN_F6R1_FB26_Pos (26U)
Kojto 122:f9eeca106725 3576 #define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 3577 #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 3578 #define CAN_F6R1_FB27_Pos (27U)
Kojto 122:f9eeca106725 3579 #define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 3580 #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 3581 #define CAN_F6R1_FB28_Pos (28U)
Kojto 122:f9eeca106725 3582 #define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 3583 #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 3584 #define CAN_F6R1_FB29_Pos (29U)
Kojto 122:f9eeca106725 3585 #define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 3586 #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 3587 #define CAN_F6R1_FB30_Pos (30U)
Kojto 122:f9eeca106725 3588 #define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 3589 #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 3590 #define CAN_F6R1_FB31_Pos (31U)
Kojto 122:f9eeca106725 3591 #define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 3592 #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
Kojto 122:f9eeca106725 3593
Kojto 122:f9eeca106725 3594 /******************* Bit definition for CAN_F7R1 register *******************/
Kojto 122:f9eeca106725 3595 #define CAN_F7R1_FB0_Pos (0U)
Kojto 122:f9eeca106725 3596 #define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3597 #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 3598 #define CAN_F7R1_FB1_Pos (1U)
Kojto 122:f9eeca106725 3599 #define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3600 #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 3601 #define CAN_F7R1_FB2_Pos (2U)
Kojto 122:f9eeca106725 3602 #define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 3603 #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 3604 #define CAN_F7R1_FB3_Pos (3U)
Kojto 122:f9eeca106725 3605 #define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 3606 #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 3607 #define CAN_F7R1_FB4_Pos (4U)
Kojto 122:f9eeca106725 3608 #define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3609 #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 3610 #define CAN_F7R1_FB5_Pos (5U)
Kojto 122:f9eeca106725 3611 #define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 3612 #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 3613 #define CAN_F7R1_FB6_Pos (6U)
Kojto 122:f9eeca106725 3614 #define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 3615 #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 3616 #define CAN_F7R1_FB7_Pos (7U)
Kojto 122:f9eeca106725 3617 #define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 3618 #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 3619 #define CAN_F7R1_FB8_Pos (8U)
Kojto 122:f9eeca106725 3620 #define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 3621 #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 3622 #define CAN_F7R1_FB9_Pos (9U)
Kojto 122:f9eeca106725 3623 #define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 3624 #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 3625 #define CAN_F7R1_FB10_Pos (10U)
Kojto 122:f9eeca106725 3626 #define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 3627 #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 3628 #define CAN_F7R1_FB11_Pos (11U)
Kojto 122:f9eeca106725 3629 #define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 3630 #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 3631 #define CAN_F7R1_FB12_Pos (12U)
Kojto 122:f9eeca106725 3632 #define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 3633 #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 3634 #define CAN_F7R1_FB13_Pos (13U)
Kojto 122:f9eeca106725 3635 #define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 3636 #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 3637 #define CAN_F7R1_FB14_Pos (14U)
Kojto 122:f9eeca106725 3638 #define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 3639 #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 3640 #define CAN_F7R1_FB15_Pos (15U)
Kojto 122:f9eeca106725 3641 #define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 3642 #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 3643 #define CAN_F7R1_FB16_Pos (16U)
Kojto 122:f9eeca106725 3644 #define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 3645 #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 3646 #define CAN_F7R1_FB17_Pos (17U)
Kojto 122:f9eeca106725 3647 #define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 3648 #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 3649 #define CAN_F7R1_FB18_Pos (18U)
Kojto 122:f9eeca106725 3650 #define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 3651 #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 3652 #define CAN_F7R1_FB19_Pos (19U)
Kojto 122:f9eeca106725 3653 #define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 3654 #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 3655 #define CAN_F7R1_FB20_Pos (20U)
Kojto 122:f9eeca106725 3656 #define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 3657 #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 3658 #define CAN_F7R1_FB21_Pos (21U)
Kojto 122:f9eeca106725 3659 #define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 3660 #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 3661 #define CAN_F7R1_FB22_Pos (22U)
Kojto 122:f9eeca106725 3662 #define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 3663 #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 3664 #define CAN_F7R1_FB23_Pos (23U)
Kojto 122:f9eeca106725 3665 #define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 3666 #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 3667 #define CAN_F7R1_FB24_Pos (24U)
Kojto 122:f9eeca106725 3668 #define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 3669 #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 3670 #define CAN_F7R1_FB25_Pos (25U)
Kojto 122:f9eeca106725 3671 #define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 3672 #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 3673 #define CAN_F7R1_FB26_Pos (26U)
Kojto 122:f9eeca106725 3674 #define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 3675 #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 3676 #define CAN_F7R1_FB27_Pos (27U)
Kojto 122:f9eeca106725 3677 #define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 3678 #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 3679 #define CAN_F7R1_FB28_Pos (28U)
Kojto 122:f9eeca106725 3680 #define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 3681 #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 3682 #define CAN_F7R1_FB29_Pos (29U)
Kojto 122:f9eeca106725 3683 #define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 3684 #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 3685 #define CAN_F7R1_FB30_Pos (30U)
Kojto 122:f9eeca106725 3686 #define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 3687 #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 3688 #define CAN_F7R1_FB31_Pos (31U)
Kojto 122:f9eeca106725 3689 #define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 3690 #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
Kojto 122:f9eeca106725 3691
Kojto 122:f9eeca106725 3692 /******************* Bit definition for CAN_F8R1 register *******************/
Kojto 122:f9eeca106725 3693 #define CAN_F8R1_FB0_Pos (0U)
Kojto 122:f9eeca106725 3694 #define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3695 #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 3696 #define CAN_F8R1_FB1_Pos (1U)
Kojto 122:f9eeca106725 3697 #define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3698 #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 3699 #define CAN_F8R1_FB2_Pos (2U)
Kojto 122:f9eeca106725 3700 #define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 3701 #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 3702 #define CAN_F8R1_FB3_Pos (3U)
Kojto 122:f9eeca106725 3703 #define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 3704 #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 3705 #define CAN_F8R1_FB4_Pos (4U)
Kojto 122:f9eeca106725 3706 #define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3707 #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 3708 #define CAN_F8R1_FB5_Pos (5U)
Kojto 122:f9eeca106725 3709 #define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 3710 #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 3711 #define CAN_F8R1_FB6_Pos (6U)
Kojto 122:f9eeca106725 3712 #define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 3713 #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 3714 #define CAN_F8R1_FB7_Pos (7U)
Kojto 122:f9eeca106725 3715 #define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 3716 #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 3717 #define CAN_F8R1_FB8_Pos (8U)
Kojto 122:f9eeca106725 3718 #define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 3719 #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 3720 #define CAN_F8R1_FB9_Pos (9U)
Kojto 122:f9eeca106725 3721 #define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 3722 #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 3723 #define CAN_F8R1_FB10_Pos (10U)
Kojto 122:f9eeca106725 3724 #define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 3725 #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 3726 #define CAN_F8R1_FB11_Pos (11U)
Kojto 122:f9eeca106725 3727 #define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 3728 #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 3729 #define CAN_F8R1_FB12_Pos (12U)
Kojto 122:f9eeca106725 3730 #define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 3731 #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 3732 #define CAN_F8R1_FB13_Pos (13U)
Kojto 122:f9eeca106725 3733 #define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 3734 #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 3735 #define CAN_F8R1_FB14_Pos (14U)
Kojto 122:f9eeca106725 3736 #define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 3737 #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 3738 #define CAN_F8R1_FB15_Pos (15U)
Kojto 122:f9eeca106725 3739 #define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 3740 #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 3741 #define CAN_F8R1_FB16_Pos (16U)
Kojto 122:f9eeca106725 3742 #define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 3743 #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 3744 #define CAN_F8R1_FB17_Pos (17U)
Kojto 122:f9eeca106725 3745 #define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 3746 #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 3747 #define CAN_F8R1_FB18_Pos (18U)
Kojto 122:f9eeca106725 3748 #define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 3749 #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 3750 #define CAN_F8R1_FB19_Pos (19U)
Kojto 122:f9eeca106725 3751 #define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 3752 #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 3753 #define CAN_F8R1_FB20_Pos (20U)
Kojto 122:f9eeca106725 3754 #define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 3755 #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 3756 #define CAN_F8R1_FB21_Pos (21U)
Kojto 122:f9eeca106725 3757 #define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 3758 #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 3759 #define CAN_F8R1_FB22_Pos (22U)
Kojto 122:f9eeca106725 3760 #define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 3761 #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 3762 #define CAN_F8R1_FB23_Pos (23U)
Kojto 122:f9eeca106725 3763 #define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 3764 #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 3765 #define CAN_F8R1_FB24_Pos (24U)
Kojto 122:f9eeca106725 3766 #define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 3767 #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 3768 #define CAN_F8R1_FB25_Pos (25U)
Kojto 122:f9eeca106725 3769 #define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 3770 #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 3771 #define CAN_F8R1_FB26_Pos (26U)
Kojto 122:f9eeca106725 3772 #define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 3773 #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 3774 #define CAN_F8R1_FB27_Pos (27U)
Kojto 122:f9eeca106725 3775 #define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 3776 #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 3777 #define CAN_F8R1_FB28_Pos (28U)
Kojto 122:f9eeca106725 3778 #define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 3779 #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 3780 #define CAN_F8R1_FB29_Pos (29U)
Kojto 122:f9eeca106725 3781 #define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 3782 #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 3783 #define CAN_F8R1_FB30_Pos (30U)
Kojto 122:f9eeca106725 3784 #define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 3785 #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 3786 #define CAN_F8R1_FB31_Pos (31U)
Kojto 122:f9eeca106725 3787 #define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 3788 #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
Kojto 122:f9eeca106725 3789
Kojto 122:f9eeca106725 3790 /******************* Bit definition for CAN_F9R1 register *******************/
Kojto 122:f9eeca106725 3791 #define CAN_F9R1_FB0_Pos (0U)
Kojto 122:f9eeca106725 3792 #define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3793 #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 3794 #define CAN_F9R1_FB1_Pos (1U)
Kojto 122:f9eeca106725 3795 #define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3796 #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 3797 #define CAN_F9R1_FB2_Pos (2U)
Kojto 122:f9eeca106725 3798 #define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 3799 #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 3800 #define CAN_F9R1_FB3_Pos (3U)
Kojto 122:f9eeca106725 3801 #define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 3802 #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 3803 #define CAN_F9R1_FB4_Pos (4U)
Kojto 122:f9eeca106725 3804 #define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3805 #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 3806 #define CAN_F9R1_FB5_Pos (5U)
Kojto 122:f9eeca106725 3807 #define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 3808 #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 3809 #define CAN_F9R1_FB6_Pos (6U)
Kojto 122:f9eeca106725 3810 #define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 3811 #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 3812 #define CAN_F9R1_FB7_Pos (7U)
Kojto 122:f9eeca106725 3813 #define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 3814 #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 3815 #define CAN_F9R1_FB8_Pos (8U)
Kojto 122:f9eeca106725 3816 #define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 3817 #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 3818 #define CAN_F9R1_FB9_Pos (9U)
Kojto 122:f9eeca106725 3819 #define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 3820 #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 3821 #define CAN_F9R1_FB10_Pos (10U)
Kojto 122:f9eeca106725 3822 #define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 3823 #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 3824 #define CAN_F9R1_FB11_Pos (11U)
Kojto 122:f9eeca106725 3825 #define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 3826 #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 3827 #define CAN_F9R1_FB12_Pos (12U)
Kojto 122:f9eeca106725 3828 #define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 3829 #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 3830 #define CAN_F9R1_FB13_Pos (13U)
Kojto 122:f9eeca106725 3831 #define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 3832 #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 3833 #define CAN_F9R1_FB14_Pos (14U)
Kojto 122:f9eeca106725 3834 #define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 3835 #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 3836 #define CAN_F9R1_FB15_Pos (15U)
Kojto 122:f9eeca106725 3837 #define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 3838 #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 3839 #define CAN_F9R1_FB16_Pos (16U)
Kojto 122:f9eeca106725 3840 #define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 3841 #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 3842 #define CAN_F9R1_FB17_Pos (17U)
Kojto 122:f9eeca106725 3843 #define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 3844 #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 3845 #define CAN_F9R1_FB18_Pos (18U)
Kojto 122:f9eeca106725 3846 #define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 3847 #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 3848 #define CAN_F9R1_FB19_Pos (19U)
Kojto 122:f9eeca106725 3849 #define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 3850 #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 3851 #define CAN_F9R1_FB20_Pos (20U)
Kojto 122:f9eeca106725 3852 #define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 3853 #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 3854 #define CAN_F9R1_FB21_Pos (21U)
Kojto 122:f9eeca106725 3855 #define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 3856 #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 3857 #define CAN_F9R1_FB22_Pos (22U)
Kojto 122:f9eeca106725 3858 #define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 3859 #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 3860 #define CAN_F9R1_FB23_Pos (23U)
Kojto 122:f9eeca106725 3861 #define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 3862 #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 3863 #define CAN_F9R1_FB24_Pos (24U)
Kojto 122:f9eeca106725 3864 #define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 3865 #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 3866 #define CAN_F9R1_FB25_Pos (25U)
Kojto 122:f9eeca106725 3867 #define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 3868 #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 3869 #define CAN_F9R1_FB26_Pos (26U)
Kojto 122:f9eeca106725 3870 #define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 3871 #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 3872 #define CAN_F9R1_FB27_Pos (27U)
Kojto 122:f9eeca106725 3873 #define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 3874 #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 3875 #define CAN_F9R1_FB28_Pos (28U)
Kojto 122:f9eeca106725 3876 #define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 3877 #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 3878 #define CAN_F9R1_FB29_Pos (29U)
Kojto 122:f9eeca106725 3879 #define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 3880 #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 3881 #define CAN_F9R1_FB30_Pos (30U)
Kojto 122:f9eeca106725 3882 #define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 3883 #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 3884 #define CAN_F9R1_FB31_Pos (31U)
Kojto 122:f9eeca106725 3885 #define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 3886 #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
Kojto 122:f9eeca106725 3887
Kojto 122:f9eeca106725 3888 /******************* Bit definition for CAN_F10R1 register ******************/
Kojto 122:f9eeca106725 3889 #define CAN_F10R1_FB0_Pos (0U)
Kojto 122:f9eeca106725 3890 #define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3891 #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 3892 #define CAN_F10R1_FB1_Pos (1U)
Kojto 122:f9eeca106725 3893 #define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3894 #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 3895 #define CAN_F10R1_FB2_Pos (2U)
Kojto 122:f9eeca106725 3896 #define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 3897 #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 3898 #define CAN_F10R1_FB3_Pos (3U)
Kojto 122:f9eeca106725 3899 #define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 3900 #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 3901 #define CAN_F10R1_FB4_Pos (4U)
Kojto 122:f9eeca106725 3902 #define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3903 #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 3904 #define CAN_F10R1_FB5_Pos (5U)
Kojto 122:f9eeca106725 3905 #define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 3906 #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 3907 #define CAN_F10R1_FB6_Pos (6U)
Kojto 122:f9eeca106725 3908 #define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 3909 #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 3910 #define CAN_F10R1_FB7_Pos (7U)
Kojto 122:f9eeca106725 3911 #define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 3912 #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 3913 #define CAN_F10R1_FB8_Pos (8U)
Kojto 122:f9eeca106725 3914 #define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 3915 #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 3916 #define CAN_F10R1_FB9_Pos (9U)
Kojto 122:f9eeca106725 3917 #define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 3918 #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 3919 #define CAN_F10R1_FB10_Pos (10U)
Kojto 122:f9eeca106725 3920 #define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 3921 #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 3922 #define CAN_F10R1_FB11_Pos (11U)
Kojto 122:f9eeca106725 3923 #define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 3924 #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 3925 #define CAN_F10R1_FB12_Pos (12U)
Kojto 122:f9eeca106725 3926 #define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 3927 #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 3928 #define CAN_F10R1_FB13_Pos (13U)
Kojto 122:f9eeca106725 3929 #define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 3930 #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 3931 #define CAN_F10R1_FB14_Pos (14U)
Kojto 122:f9eeca106725 3932 #define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 3933 #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 3934 #define CAN_F10R1_FB15_Pos (15U)
Kojto 122:f9eeca106725 3935 #define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 3936 #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 3937 #define CAN_F10R1_FB16_Pos (16U)
Kojto 122:f9eeca106725 3938 #define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 3939 #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 3940 #define CAN_F10R1_FB17_Pos (17U)
Kojto 122:f9eeca106725 3941 #define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 3942 #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 3943 #define CAN_F10R1_FB18_Pos (18U)
Kojto 122:f9eeca106725 3944 #define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 3945 #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 3946 #define CAN_F10R1_FB19_Pos (19U)
Kojto 122:f9eeca106725 3947 #define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 3948 #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 3949 #define CAN_F10R1_FB20_Pos (20U)
Kojto 122:f9eeca106725 3950 #define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 3951 #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 3952 #define CAN_F10R1_FB21_Pos (21U)
Kojto 122:f9eeca106725 3953 #define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 3954 #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 3955 #define CAN_F10R1_FB22_Pos (22U)
Kojto 122:f9eeca106725 3956 #define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 3957 #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 3958 #define CAN_F10R1_FB23_Pos (23U)
Kojto 122:f9eeca106725 3959 #define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 3960 #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 3961 #define CAN_F10R1_FB24_Pos (24U)
Kojto 122:f9eeca106725 3962 #define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 3963 #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 3964 #define CAN_F10R1_FB25_Pos (25U)
Kojto 122:f9eeca106725 3965 #define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 3966 #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 3967 #define CAN_F10R1_FB26_Pos (26U)
Kojto 122:f9eeca106725 3968 #define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 3969 #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 3970 #define CAN_F10R1_FB27_Pos (27U)
Kojto 122:f9eeca106725 3971 #define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 3972 #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 3973 #define CAN_F10R1_FB28_Pos (28U)
Kojto 122:f9eeca106725 3974 #define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 3975 #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 3976 #define CAN_F10R1_FB29_Pos (29U)
Kojto 122:f9eeca106725 3977 #define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 3978 #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 3979 #define CAN_F10R1_FB30_Pos (30U)
Kojto 122:f9eeca106725 3980 #define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 3981 #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 3982 #define CAN_F10R1_FB31_Pos (31U)
Kojto 122:f9eeca106725 3983 #define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 3984 #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
Kojto 122:f9eeca106725 3985
Kojto 122:f9eeca106725 3986 /******************* Bit definition for CAN_F11R1 register ******************/
Kojto 122:f9eeca106725 3987 #define CAN_F11R1_FB0_Pos (0U)
Kojto 122:f9eeca106725 3988 #define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3989 #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 3990 #define CAN_F11R1_FB1_Pos (1U)
Kojto 122:f9eeca106725 3991 #define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3992 #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 3993 #define CAN_F11R1_FB2_Pos (2U)
Kojto 122:f9eeca106725 3994 #define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 3995 #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 3996 #define CAN_F11R1_FB3_Pos (3U)
Kojto 122:f9eeca106725 3997 #define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 3998 #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 3999 #define CAN_F11R1_FB4_Pos (4U)
Kojto 122:f9eeca106725 4000 #define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4001 #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 4002 #define CAN_F11R1_FB5_Pos (5U)
Kojto 122:f9eeca106725 4003 #define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 4004 #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 4005 #define CAN_F11R1_FB6_Pos (6U)
Kojto 122:f9eeca106725 4006 #define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4007 #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 4008 #define CAN_F11R1_FB7_Pos (7U)
Kojto 122:f9eeca106725 4009 #define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 4010 #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 4011 #define CAN_F11R1_FB8_Pos (8U)
Kojto 122:f9eeca106725 4012 #define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 4013 #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 4014 #define CAN_F11R1_FB9_Pos (9U)
Kojto 122:f9eeca106725 4015 #define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 4016 #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 4017 #define CAN_F11R1_FB10_Pos (10U)
Kojto 122:f9eeca106725 4018 #define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4019 #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 4020 #define CAN_F11R1_FB11_Pos (11U)
Kojto 122:f9eeca106725 4021 #define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 4022 #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 4023 #define CAN_F11R1_FB12_Pos (12U)
Kojto 122:f9eeca106725 4024 #define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 4025 #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 4026 #define CAN_F11R1_FB13_Pos (13U)
Kojto 122:f9eeca106725 4027 #define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 4028 #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 4029 #define CAN_F11R1_FB14_Pos (14U)
Kojto 122:f9eeca106725 4030 #define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 4031 #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 4032 #define CAN_F11R1_FB15_Pos (15U)
Kojto 122:f9eeca106725 4033 #define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 4034 #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 4035 #define CAN_F11R1_FB16_Pos (16U)
Kojto 122:f9eeca106725 4036 #define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 4037 #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 4038 #define CAN_F11R1_FB17_Pos (17U)
Kojto 122:f9eeca106725 4039 #define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 4040 #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 4041 #define CAN_F11R1_FB18_Pos (18U)
Kojto 122:f9eeca106725 4042 #define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 4043 #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 4044 #define CAN_F11R1_FB19_Pos (19U)
Kojto 122:f9eeca106725 4045 #define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 4046 #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 4047 #define CAN_F11R1_FB20_Pos (20U)
Kojto 122:f9eeca106725 4048 #define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 4049 #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 4050 #define CAN_F11R1_FB21_Pos (21U)
Kojto 122:f9eeca106725 4051 #define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 4052 #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 4053 #define CAN_F11R1_FB22_Pos (22U)
Kojto 122:f9eeca106725 4054 #define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 4055 #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 4056 #define CAN_F11R1_FB23_Pos (23U)
Kojto 122:f9eeca106725 4057 #define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 4058 #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 4059 #define CAN_F11R1_FB24_Pos (24U)
Kojto 122:f9eeca106725 4060 #define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 4061 #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 4062 #define CAN_F11R1_FB25_Pos (25U)
Kojto 122:f9eeca106725 4063 #define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 4064 #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 4065 #define CAN_F11R1_FB26_Pos (26U)
Kojto 122:f9eeca106725 4066 #define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 4067 #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 4068 #define CAN_F11R1_FB27_Pos (27U)
Kojto 122:f9eeca106725 4069 #define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 4070 #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 4071 #define CAN_F11R1_FB28_Pos (28U)
Kojto 122:f9eeca106725 4072 #define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 4073 #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 4074 #define CAN_F11R1_FB29_Pos (29U)
Kojto 122:f9eeca106725 4075 #define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 4076 #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 4077 #define CAN_F11R1_FB30_Pos (30U)
Kojto 122:f9eeca106725 4078 #define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 4079 #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 4080 #define CAN_F11R1_FB31_Pos (31U)
Kojto 122:f9eeca106725 4081 #define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 4082 #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
Kojto 122:f9eeca106725 4083
Kojto 122:f9eeca106725 4084 /******************* Bit definition for CAN_F12R1 register ******************/
Kojto 122:f9eeca106725 4085 #define CAN_F12R1_FB0_Pos (0U)
Kojto 122:f9eeca106725 4086 #define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4087 #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 4088 #define CAN_F12R1_FB1_Pos (1U)
Kojto 122:f9eeca106725 4089 #define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 4090 #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 4091 #define CAN_F12R1_FB2_Pos (2U)
Kojto 122:f9eeca106725 4092 #define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4093 #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 4094 #define CAN_F12R1_FB3_Pos (3U)
Kojto 122:f9eeca106725 4095 #define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4096 #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 4097 #define CAN_F12R1_FB4_Pos (4U)
Kojto 122:f9eeca106725 4098 #define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4099 #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 4100 #define CAN_F12R1_FB5_Pos (5U)
Kojto 122:f9eeca106725 4101 #define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 4102 #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 4103 #define CAN_F12R1_FB6_Pos (6U)
Kojto 122:f9eeca106725 4104 #define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4105 #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 4106 #define CAN_F12R1_FB7_Pos (7U)
Kojto 122:f9eeca106725 4107 #define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 4108 #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 4109 #define CAN_F12R1_FB8_Pos (8U)
Kojto 122:f9eeca106725 4110 #define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 4111 #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 4112 #define CAN_F12R1_FB9_Pos (9U)
Kojto 122:f9eeca106725 4113 #define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 4114 #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 4115 #define CAN_F12R1_FB10_Pos (10U)
Kojto 122:f9eeca106725 4116 #define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4117 #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 4118 #define CAN_F12R1_FB11_Pos (11U)
Kojto 122:f9eeca106725 4119 #define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 4120 #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 4121 #define CAN_F12R1_FB12_Pos (12U)
Kojto 122:f9eeca106725 4122 #define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 4123 #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 4124 #define CAN_F12R1_FB13_Pos (13U)
Kojto 122:f9eeca106725 4125 #define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 4126 #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 4127 #define CAN_F12R1_FB14_Pos (14U)
Kojto 122:f9eeca106725 4128 #define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 4129 #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 4130 #define CAN_F12R1_FB15_Pos (15U)
Kojto 122:f9eeca106725 4131 #define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 4132 #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 4133 #define CAN_F12R1_FB16_Pos (16U)
Kojto 122:f9eeca106725 4134 #define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 4135 #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 4136 #define CAN_F12R1_FB17_Pos (17U)
Kojto 122:f9eeca106725 4137 #define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 4138 #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 4139 #define CAN_F12R1_FB18_Pos (18U)
Kojto 122:f9eeca106725 4140 #define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 4141 #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 4142 #define CAN_F12R1_FB19_Pos (19U)
Kojto 122:f9eeca106725 4143 #define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 4144 #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 4145 #define CAN_F12R1_FB20_Pos (20U)
Kojto 122:f9eeca106725 4146 #define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 4147 #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 4148 #define CAN_F12R1_FB21_Pos (21U)
Kojto 122:f9eeca106725 4149 #define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 4150 #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 4151 #define CAN_F12R1_FB22_Pos (22U)
Kojto 122:f9eeca106725 4152 #define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 4153 #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 4154 #define CAN_F12R1_FB23_Pos (23U)
Kojto 122:f9eeca106725 4155 #define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 4156 #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 4157 #define CAN_F12R1_FB24_Pos (24U)
Kojto 122:f9eeca106725 4158 #define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 4159 #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 4160 #define CAN_F12R1_FB25_Pos (25U)
Kojto 122:f9eeca106725 4161 #define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 4162 #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 4163 #define CAN_F12R1_FB26_Pos (26U)
Kojto 122:f9eeca106725 4164 #define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 4165 #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 4166 #define CAN_F12R1_FB27_Pos (27U)
Kojto 122:f9eeca106725 4167 #define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 4168 #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 4169 #define CAN_F12R1_FB28_Pos (28U)
Kojto 122:f9eeca106725 4170 #define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 4171 #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 4172 #define CAN_F12R1_FB29_Pos (29U)
Kojto 122:f9eeca106725 4173 #define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 4174 #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 4175 #define CAN_F12R1_FB30_Pos (30U)
Kojto 122:f9eeca106725 4176 #define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 4177 #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 4178 #define CAN_F12R1_FB31_Pos (31U)
Kojto 122:f9eeca106725 4179 #define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 4180 #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
Kojto 122:f9eeca106725 4181
Kojto 122:f9eeca106725 4182 /******************* Bit definition for CAN_F13R1 register ******************/
Kojto 122:f9eeca106725 4183 #define CAN_F13R1_FB0_Pos (0U)
Kojto 122:f9eeca106725 4184 #define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4185 #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 4186 #define CAN_F13R1_FB1_Pos (1U)
Kojto 122:f9eeca106725 4187 #define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 4188 #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 4189 #define CAN_F13R1_FB2_Pos (2U)
Kojto 122:f9eeca106725 4190 #define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4191 #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 4192 #define CAN_F13R1_FB3_Pos (3U)
Kojto 122:f9eeca106725 4193 #define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4194 #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 4195 #define CAN_F13R1_FB4_Pos (4U)
Kojto 122:f9eeca106725 4196 #define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4197 #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 4198 #define CAN_F13R1_FB5_Pos (5U)
Kojto 122:f9eeca106725 4199 #define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 4200 #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 4201 #define CAN_F13R1_FB6_Pos (6U)
Kojto 122:f9eeca106725 4202 #define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4203 #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 4204 #define CAN_F13R1_FB7_Pos (7U)
Kojto 122:f9eeca106725 4205 #define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 4206 #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 4207 #define CAN_F13R1_FB8_Pos (8U)
Kojto 122:f9eeca106725 4208 #define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 4209 #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 4210 #define CAN_F13R1_FB9_Pos (9U)
Kojto 122:f9eeca106725 4211 #define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 4212 #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 4213 #define CAN_F13R1_FB10_Pos (10U)
Kojto 122:f9eeca106725 4214 #define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4215 #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 4216 #define CAN_F13R1_FB11_Pos (11U)
Kojto 122:f9eeca106725 4217 #define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 4218 #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 4219 #define CAN_F13R1_FB12_Pos (12U)
Kojto 122:f9eeca106725 4220 #define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 4221 #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 4222 #define CAN_F13R1_FB13_Pos (13U)
Kojto 122:f9eeca106725 4223 #define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 4224 #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 4225 #define CAN_F13R1_FB14_Pos (14U)
Kojto 122:f9eeca106725 4226 #define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 4227 #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 4228 #define CAN_F13R1_FB15_Pos (15U)
Kojto 122:f9eeca106725 4229 #define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 4230 #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 4231 #define CAN_F13R1_FB16_Pos (16U)
Kojto 122:f9eeca106725 4232 #define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 4233 #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 4234 #define CAN_F13R1_FB17_Pos (17U)
Kojto 122:f9eeca106725 4235 #define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 4236 #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 4237 #define CAN_F13R1_FB18_Pos (18U)
Kojto 122:f9eeca106725 4238 #define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 4239 #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 4240 #define CAN_F13R1_FB19_Pos (19U)
Kojto 122:f9eeca106725 4241 #define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 4242 #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 4243 #define CAN_F13R1_FB20_Pos (20U)
Kojto 122:f9eeca106725 4244 #define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 4245 #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 4246 #define CAN_F13R1_FB21_Pos (21U)
Kojto 122:f9eeca106725 4247 #define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 4248 #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 4249 #define CAN_F13R1_FB22_Pos (22U)
Kojto 122:f9eeca106725 4250 #define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 4251 #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 4252 #define CAN_F13R1_FB23_Pos (23U)
Kojto 122:f9eeca106725 4253 #define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 4254 #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 4255 #define CAN_F13R1_FB24_Pos (24U)
Kojto 122:f9eeca106725 4256 #define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 4257 #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 4258 #define CAN_F13R1_FB25_Pos (25U)
Kojto 122:f9eeca106725 4259 #define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 4260 #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 4261 #define CAN_F13R1_FB26_Pos (26U)
Kojto 122:f9eeca106725 4262 #define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 4263 #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 4264 #define CAN_F13R1_FB27_Pos (27U)
Kojto 122:f9eeca106725 4265 #define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 4266 #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 4267 #define CAN_F13R1_FB28_Pos (28U)
Kojto 122:f9eeca106725 4268 #define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 4269 #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 4270 #define CAN_F13R1_FB29_Pos (29U)
Kojto 122:f9eeca106725 4271 #define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 4272 #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 4273 #define CAN_F13R1_FB30_Pos (30U)
Kojto 122:f9eeca106725 4274 #define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 4275 #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 4276 #define CAN_F13R1_FB31_Pos (31U)
Kojto 122:f9eeca106725 4277 #define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 4278 #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
Kojto 122:f9eeca106725 4279
Kojto 122:f9eeca106725 4280 /******************* Bit definition for CAN_F0R2 register *******************/
Kojto 122:f9eeca106725 4281 #define CAN_F0R2_FB0_Pos (0U)
Kojto 122:f9eeca106725 4282 #define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4283 #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 4284 #define CAN_F0R2_FB1_Pos (1U)
Kojto 122:f9eeca106725 4285 #define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 4286 #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 4287 #define CAN_F0R2_FB2_Pos (2U)
Kojto 122:f9eeca106725 4288 #define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4289 #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 4290 #define CAN_F0R2_FB3_Pos (3U)
Kojto 122:f9eeca106725 4291 #define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4292 #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 4293 #define CAN_F0R2_FB4_Pos (4U)
Kojto 122:f9eeca106725 4294 #define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4295 #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 4296 #define CAN_F0R2_FB5_Pos (5U)
Kojto 122:f9eeca106725 4297 #define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 4298 #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 4299 #define CAN_F0R2_FB6_Pos (6U)
Kojto 122:f9eeca106725 4300 #define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4301 #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 4302 #define CAN_F0R2_FB7_Pos (7U)
Kojto 122:f9eeca106725 4303 #define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 4304 #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 4305 #define CAN_F0R2_FB8_Pos (8U)
Kojto 122:f9eeca106725 4306 #define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 4307 #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 4308 #define CAN_F0R2_FB9_Pos (9U)
Kojto 122:f9eeca106725 4309 #define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 4310 #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 4311 #define CAN_F0R2_FB10_Pos (10U)
Kojto 122:f9eeca106725 4312 #define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4313 #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 4314 #define CAN_F0R2_FB11_Pos (11U)
Kojto 122:f9eeca106725 4315 #define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 4316 #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 4317 #define CAN_F0R2_FB12_Pos (12U)
Kojto 122:f9eeca106725 4318 #define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 4319 #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 4320 #define CAN_F0R2_FB13_Pos (13U)
Kojto 122:f9eeca106725 4321 #define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 4322 #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 4323 #define CAN_F0R2_FB14_Pos (14U)
Kojto 122:f9eeca106725 4324 #define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 4325 #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 4326 #define CAN_F0R2_FB15_Pos (15U)
Kojto 122:f9eeca106725 4327 #define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 4328 #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 4329 #define CAN_F0R2_FB16_Pos (16U)
Kojto 122:f9eeca106725 4330 #define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 4331 #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 4332 #define CAN_F0R2_FB17_Pos (17U)
Kojto 122:f9eeca106725 4333 #define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 4334 #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 4335 #define CAN_F0R2_FB18_Pos (18U)
Kojto 122:f9eeca106725 4336 #define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 4337 #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 4338 #define CAN_F0R2_FB19_Pos (19U)
Kojto 122:f9eeca106725 4339 #define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 4340 #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 4341 #define CAN_F0R2_FB20_Pos (20U)
Kojto 122:f9eeca106725 4342 #define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 4343 #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 4344 #define CAN_F0R2_FB21_Pos (21U)
Kojto 122:f9eeca106725 4345 #define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 4346 #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 4347 #define CAN_F0R2_FB22_Pos (22U)
Kojto 122:f9eeca106725 4348 #define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 4349 #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 4350 #define CAN_F0R2_FB23_Pos (23U)
Kojto 122:f9eeca106725 4351 #define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 4352 #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 4353 #define CAN_F0R2_FB24_Pos (24U)
Kojto 122:f9eeca106725 4354 #define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 4355 #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 4356 #define CAN_F0R2_FB25_Pos (25U)
Kojto 122:f9eeca106725 4357 #define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 4358 #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 4359 #define CAN_F0R2_FB26_Pos (26U)
Kojto 122:f9eeca106725 4360 #define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 4361 #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 4362 #define CAN_F0R2_FB27_Pos (27U)
Kojto 122:f9eeca106725 4363 #define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 4364 #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 4365 #define CAN_F0R2_FB28_Pos (28U)
Kojto 122:f9eeca106725 4366 #define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 4367 #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 4368 #define CAN_F0R2_FB29_Pos (29U)
Kojto 122:f9eeca106725 4369 #define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 4370 #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 4371 #define CAN_F0R2_FB30_Pos (30U)
Kojto 122:f9eeca106725 4372 #define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 4373 #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 4374 #define CAN_F0R2_FB31_Pos (31U)
Kojto 122:f9eeca106725 4375 #define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 4376 #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
Kojto 122:f9eeca106725 4377
Kojto 122:f9eeca106725 4378 /******************* Bit definition for CAN_F1R2 register *******************/
Kojto 122:f9eeca106725 4379 #define CAN_F1R2_FB0_Pos (0U)
Kojto 122:f9eeca106725 4380 #define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4381 #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 4382 #define CAN_F1R2_FB1_Pos (1U)
Kojto 122:f9eeca106725 4383 #define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 4384 #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 4385 #define CAN_F1R2_FB2_Pos (2U)
Kojto 122:f9eeca106725 4386 #define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4387 #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 4388 #define CAN_F1R2_FB3_Pos (3U)
Kojto 122:f9eeca106725 4389 #define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4390 #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 4391 #define CAN_F1R2_FB4_Pos (4U)
Kojto 122:f9eeca106725 4392 #define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4393 #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 4394 #define CAN_F1R2_FB5_Pos (5U)
Kojto 122:f9eeca106725 4395 #define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 4396 #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 4397 #define CAN_F1R2_FB6_Pos (6U)
Kojto 122:f9eeca106725 4398 #define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4399 #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 4400 #define CAN_F1R2_FB7_Pos (7U)
Kojto 122:f9eeca106725 4401 #define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 4402 #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 4403 #define CAN_F1R2_FB8_Pos (8U)
Kojto 122:f9eeca106725 4404 #define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 4405 #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 4406 #define CAN_F1R2_FB9_Pos (9U)
Kojto 122:f9eeca106725 4407 #define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 4408 #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 4409 #define CAN_F1R2_FB10_Pos (10U)
Kojto 122:f9eeca106725 4410 #define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4411 #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 4412 #define CAN_F1R2_FB11_Pos (11U)
Kojto 122:f9eeca106725 4413 #define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 4414 #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 4415 #define CAN_F1R2_FB12_Pos (12U)
Kojto 122:f9eeca106725 4416 #define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 4417 #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 4418 #define CAN_F1R2_FB13_Pos (13U)
Kojto 122:f9eeca106725 4419 #define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 4420 #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 4421 #define CAN_F1R2_FB14_Pos (14U)
Kojto 122:f9eeca106725 4422 #define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 4423 #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 4424 #define CAN_F1R2_FB15_Pos (15U)
Kojto 122:f9eeca106725 4425 #define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 4426 #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 4427 #define CAN_F1R2_FB16_Pos (16U)
Kojto 122:f9eeca106725 4428 #define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 4429 #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 4430 #define CAN_F1R2_FB17_Pos (17U)
Kojto 122:f9eeca106725 4431 #define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 4432 #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 4433 #define CAN_F1R2_FB18_Pos (18U)
Kojto 122:f9eeca106725 4434 #define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 4435 #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 4436 #define CAN_F1R2_FB19_Pos (19U)
Kojto 122:f9eeca106725 4437 #define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 4438 #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 4439 #define CAN_F1R2_FB20_Pos (20U)
Kojto 122:f9eeca106725 4440 #define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 4441 #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 4442 #define CAN_F1R2_FB21_Pos (21U)
Kojto 122:f9eeca106725 4443 #define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 4444 #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 4445 #define CAN_F1R2_FB22_Pos (22U)
Kojto 122:f9eeca106725 4446 #define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 4447 #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 4448 #define CAN_F1R2_FB23_Pos (23U)
Kojto 122:f9eeca106725 4449 #define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 4450 #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 4451 #define CAN_F1R2_FB24_Pos (24U)
Kojto 122:f9eeca106725 4452 #define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 4453 #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 4454 #define CAN_F1R2_FB25_Pos (25U)
Kojto 122:f9eeca106725 4455 #define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 4456 #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 4457 #define CAN_F1R2_FB26_Pos (26U)
Kojto 122:f9eeca106725 4458 #define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 4459 #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 4460 #define CAN_F1R2_FB27_Pos (27U)
Kojto 122:f9eeca106725 4461 #define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 4462 #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 4463 #define CAN_F1R2_FB28_Pos (28U)
Kojto 122:f9eeca106725 4464 #define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 4465 #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 4466 #define CAN_F1R2_FB29_Pos (29U)
Kojto 122:f9eeca106725 4467 #define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 4468 #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 4469 #define CAN_F1R2_FB30_Pos (30U)
Kojto 122:f9eeca106725 4470 #define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 4471 #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 4472 #define CAN_F1R2_FB31_Pos (31U)
Kojto 122:f9eeca106725 4473 #define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 4474 #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
Kojto 122:f9eeca106725 4475
Kojto 122:f9eeca106725 4476 /******************* Bit definition for CAN_F2R2 register *******************/
Kojto 122:f9eeca106725 4477 #define CAN_F2R2_FB0_Pos (0U)
Kojto 122:f9eeca106725 4478 #define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4479 #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 4480 #define CAN_F2R2_FB1_Pos (1U)
Kojto 122:f9eeca106725 4481 #define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 4482 #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 4483 #define CAN_F2R2_FB2_Pos (2U)
Kojto 122:f9eeca106725 4484 #define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4485 #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 4486 #define CAN_F2R2_FB3_Pos (3U)
Kojto 122:f9eeca106725 4487 #define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4488 #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 4489 #define CAN_F2R2_FB4_Pos (4U)
Kojto 122:f9eeca106725 4490 #define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4491 #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 4492 #define CAN_F2R2_FB5_Pos (5U)
Kojto 122:f9eeca106725 4493 #define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 4494 #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 4495 #define CAN_F2R2_FB6_Pos (6U)
Kojto 122:f9eeca106725 4496 #define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4497 #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 4498 #define CAN_F2R2_FB7_Pos (7U)
Kojto 122:f9eeca106725 4499 #define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 4500 #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 4501 #define CAN_F2R2_FB8_Pos (8U)
Kojto 122:f9eeca106725 4502 #define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 4503 #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 4504 #define CAN_F2R2_FB9_Pos (9U)
Kojto 122:f9eeca106725 4505 #define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 4506 #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 4507 #define CAN_F2R2_FB10_Pos (10U)
Kojto 122:f9eeca106725 4508 #define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4509 #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 4510 #define CAN_F2R2_FB11_Pos (11U)
Kojto 122:f9eeca106725 4511 #define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 4512 #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 4513 #define CAN_F2R2_FB12_Pos (12U)
Kojto 122:f9eeca106725 4514 #define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 4515 #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 4516 #define CAN_F2R2_FB13_Pos (13U)
Kojto 122:f9eeca106725 4517 #define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 4518 #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 4519 #define CAN_F2R2_FB14_Pos (14U)
Kojto 122:f9eeca106725 4520 #define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 4521 #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 4522 #define CAN_F2R2_FB15_Pos (15U)
Kojto 122:f9eeca106725 4523 #define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 4524 #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 4525 #define CAN_F2R2_FB16_Pos (16U)
Kojto 122:f9eeca106725 4526 #define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 4527 #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 4528 #define CAN_F2R2_FB17_Pos (17U)
Kojto 122:f9eeca106725 4529 #define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 4530 #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 4531 #define CAN_F2R2_FB18_Pos (18U)
Kojto 122:f9eeca106725 4532 #define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 4533 #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 4534 #define CAN_F2R2_FB19_Pos (19U)
Kojto 122:f9eeca106725 4535 #define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 4536 #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 4537 #define CAN_F2R2_FB20_Pos (20U)
Kojto 122:f9eeca106725 4538 #define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 4539 #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 4540 #define CAN_F2R2_FB21_Pos (21U)
Kojto 122:f9eeca106725 4541 #define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 4542 #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 4543 #define CAN_F2R2_FB22_Pos (22U)
Kojto 122:f9eeca106725 4544 #define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 4545 #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 4546 #define CAN_F2R2_FB23_Pos (23U)
Kojto 122:f9eeca106725 4547 #define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 4548 #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 4549 #define CAN_F2R2_FB24_Pos (24U)
Kojto 122:f9eeca106725 4550 #define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 4551 #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 4552 #define CAN_F2R2_FB25_Pos (25U)
Kojto 122:f9eeca106725 4553 #define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 4554 #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 4555 #define CAN_F2R2_FB26_Pos (26U)
Kojto 122:f9eeca106725 4556 #define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 4557 #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 4558 #define CAN_F2R2_FB27_Pos (27U)
Kojto 122:f9eeca106725 4559 #define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 4560 #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 4561 #define CAN_F2R2_FB28_Pos (28U)
Kojto 122:f9eeca106725 4562 #define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 4563 #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 4564 #define CAN_F2R2_FB29_Pos (29U)
Kojto 122:f9eeca106725 4565 #define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 4566 #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 4567 #define CAN_F2R2_FB30_Pos (30U)
Kojto 122:f9eeca106725 4568 #define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 4569 #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 4570 #define CAN_F2R2_FB31_Pos (31U)
Kojto 122:f9eeca106725 4571 #define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 4572 #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
Kojto 122:f9eeca106725 4573
Kojto 122:f9eeca106725 4574 /******************* Bit definition for CAN_F3R2 register *******************/
Kojto 122:f9eeca106725 4575 #define CAN_F3R2_FB0_Pos (0U)
Kojto 122:f9eeca106725 4576 #define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4577 #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 4578 #define CAN_F3R2_FB1_Pos (1U)
Kojto 122:f9eeca106725 4579 #define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 4580 #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 4581 #define CAN_F3R2_FB2_Pos (2U)
Kojto 122:f9eeca106725 4582 #define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4583 #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 4584 #define CAN_F3R2_FB3_Pos (3U)
Kojto 122:f9eeca106725 4585 #define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4586 #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 4587 #define CAN_F3R2_FB4_Pos (4U)
Kojto 122:f9eeca106725 4588 #define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4589 #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 4590 #define CAN_F3R2_FB5_Pos (5U)
Kojto 122:f9eeca106725 4591 #define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 4592 #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 4593 #define CAN_F3R2_FB6_Pos (6U)
Kojto 122:f9eeca106725 4594 #define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4595 #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 4596 #define CAN_F3R2_FB7_Pos (7U)
Kojto 122:f9eeca106725 4597 #define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 4598 #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 4599 #define CAN_F3R2_FB8_Pos (8U)
Kojto 122:f9eeca106725 4600 #define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 4601 #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 4602 #define CAN_F3R2_FB9_Pos (9U)
Kojto 122:f9eeca106725 4603 #define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 4604 #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 4605 #define CAN_F3R2_FB10_Pos (10U)
Kojto 122:f9eeca106725 4606 #define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4607 #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 4608 #define CAN_F3R2_FB11_Pos (11U)
Kojto 122:f9eeca106725 4609 #define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 4610 #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 4611 #define CAN_F3R2_FB12_Pos (12U)
Kojto 122:f9eeca106725 4612 #define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 4613 #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 4614 #define CAN_F3R2_FB13_Pos (13U)
Kojto 122:f9eeca106725 4615 #define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 4616 #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 4617 #define CAN_F3R2_FB14_Pos (14U)
Kojto 122:f9eeca106725 4618 #define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 4619 #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 4620 #define CAN_F3R2_FB15_Pos (15U)
Kojto 122:f9eeca106725 4621 #define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 4622 #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 4623 #define CAN_F3R2_FB16_Pos (16U)
Kojto 122:f9eeca106725 4624 #define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 4625 #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 4626 #define CAN_F3R2_FB17_Pos (17U)
Kojto 122:f9eeca106725 4627 #define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 4628 #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 4629 #define CAN_F3R2_FB18_Pos (18U)
Kojto 122:f9eeca106725 4630 #define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 4631 #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 4632 #define CAN_F3R2_FB19_Pos (19U)
Kojto 122:f9eeca106725 4633 #define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 4634 #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 4635 #define CAN_F3R2_FB20_Pos (20U)
Kojto 122:f9eeca106725 4636 #define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 4637 #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 4638 #define CAN_F3R2_FB21_Pos (21U)
Kojto 122:f9eeca106725 4639 #define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 4640 #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 4641 #define CAN_F3R2_FB22_Pos (22U)
Kojto 122:f9eeca106725 4642 #define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 4643 #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 4644 #define CAN_F3R2_FB23_Pos (23U)
Kojto 122:f9eeca106725 4645 #define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 4646 #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 4647 #define CAN_F3R2_FB24_Pos (24U)
Kojto 122:f9eeca106725 4648 #define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 4649 #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 4650 #define CAN_F3R2_FB25_Pos (25U)
Kojto 122:f9eeca106725 4651 #define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 4652 #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 4653 #define CAN_F3R2_FB26_Pos (26U)
Kojto 122:f9eeca106725 4654 #define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 4655 #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 4656 #define CAN_F3R2_FB27_Pos (27U)
Kojto 122:f9eeca106725 4657 #define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 4658 #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 4659 #define CAN_F3R2_FB28_Pos (28U)
Kojto 122:f9eeca106725 4660 #define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 4661 #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 4662 #define CAN_F3R2_FB29_Pos (29U)
Kojto 122:f9eeca106725 4663 #define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 4664 #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 4665 #define CAN_F3R2_FB30_Pos (30U)
Kojto 122:f9eeca106725 4666 #define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 4667 #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 4668 #define CAN_F3R2_FB31_Pos (31U)
Kojto 122:f9eeca106725 4669 #define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 4670 #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
Kojto 122:f9eeca106725 4671
Kojto 122:f9eeca106725 4672 /******************* Bit definition for CAN_F4R2 register *******************/
Kojto 122:f9eeca106725 4673 #define CAN_F4R2_FB0_Pos (0U)
Kojto 122:f9eeca106725 4674 #define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4675 #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 4676 #define CAN_F4R2_FB1_Pos (1U)
Kojto 122:f9eeca106725 4677 #define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 4678 #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 4679 #define CAN_F4R2_FB2_Pos (2U)
Kojto 122:f9eeca106725 4680 #define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4681 #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 4682 #define CAN_F4R2_FB3_Pos (3U)
Kojto 122:f9eeca106725 4683 #define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4684 #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 4685 #define CAN_F4R2_FB4_Pos (4U)
Kojto 122:f9eeca106725 4686 #define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4687 #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 4688 #define CAN_F4R2_FB5_Pos (5U)
Kojto 122:f9eeca106725 4689 #define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 4690 #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 4691 #define CAN_F4R2_FB6_Pos (6U)
Kojto 122:f9eeca106725 4692 #define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4693 #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 4694 #define CAN_F4R2_FB7_Pos (7U)
Kojto 122:f9eeca106725 4695 #define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 4696 #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 4697 #define CAN_F4R2_FB8_Pos (8U)
Kojto 122:f9eeca106725 4698 #define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 4699 #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 4700 #define CAN_F4R2_FB9_Pos (9U)
Kojto 122:f9eeca106725 4701 #define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 4702 #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 4703 #define CAN_F4R2_FB10_Pos (10U)
Kojto 122:f9eeca106725 4704 #define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4705 #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 4706 #define CAN_F4R2_FB11_Pos (11U)
Kojto 122:f9eeca106725 4707 #define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 4708 #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 4709 #define CAN_F4R2_FB12_Pos (12U)
Kojto 122:f9eeca106725 4710 #define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 4711 #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 4712 #define CAN_F4R2_FB13_Pos (13U)
Kojto 122:f9eeca106725 4713 #define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 4714 #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 4715 #define CAN_F4R2_FB14_Pos (14U)
Kojto 122:f9eeca106725 4716 #define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 4717 #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 4718 #define CAN_F4R2_FB15_Pos (15U)
Kojto 122:f9eeca106725 4719 #define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 4720 #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 4721 #define CAN_F4R2_FB16_Pos (16U)
Kojto 122:f9eeca106725 4722 #define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 4723 #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 4724 #define CAN_F4R2_FB17_Pos (17U)
Kojto 122:f9eeca106725 4725 #define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 4726 #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 4727 #define CAN_F4R2_FB18_Pos (18U)
Kojto 122:f9eeca106725 4728 #define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 4729 #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 4730 #define CAN_F4R2_FB19_Pos (19U)
Kojto 122:f9eeca106725 4731 #define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 4732 #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 4733 #define CAN_F4R2_FB20_Pos (20U)
Kojto 122:f9eeca106725 4734 #define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 4735 #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 4736 #define CAN_F4R2_FB21_Pos (21U)
Kojto 122:f9eeca106725 4737 #define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 4738 #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 4739 #define CAN_F4R2_FB22_Pos (22U)
Kojto 122:f9eeca106725 4740 #define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 4741 #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 4742 #define CAN_F4R2_FB23_Pos (23U)
Kojto 122:f9eeca106725 4743 #define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 4744 #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 4745 #define CAN_F4R2_FB24_Pos (24U)
Kojto 122:f9eeca106725 4746 #define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 4747 #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 4748 #define CAN_F4R2_FB25_Pos (25U)
Kojto 122:f9eeca106725 4749 #define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 4750 #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 4751 #define CAN_F4R2_FB26_Pos (26U)
Kojto 122:f9eeca106725 4752 #define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 4753 #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 4754 #define CAN_F4R2_FB27_Pos (27U)
Kojto 122:f9eeca106725 4755 #define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 4756 #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 4757 #define CAN_F4R2_FB28_Pos (28U)
Kojto 122:f9eeca106725 4758 #define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 4759 #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 4760 #define CAN_F4R2_FB29_Pos (29U)
Kojto 122:f9eeca106725 4761 #define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 4762 #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 4763 #define CAN_F4R2_FB30_Pos (30U)
Kojto 122:f9eeca106725 4764 #define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 4765 #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 4766 #define CAN_F4R2_FB31_Pos (31U)
Kojto 122:f9eeca106725 4767 #define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 4768 #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
Kojto 122:f9eeca106725 4769
Kojto 122:f9eeca106725 4770 /******************* Bit definition for CAN_F5R2 register *******************/
Kojto 122:f9eeca106725 4771 #define CAN_F5R2_FB0_Pos (0U)
Kojto 122:f9eeca106725 4772 #define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4773 #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 4774 #define CAN_F5R2_FB1_Pos (1U)
Kojto 122:f9eeca106725 4775 #define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 4776 #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 4777 #define CAN_F5R2_FB2_Pos (2U)
Kojto 122:f9eeca106725 4778 #define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4779 #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 4780 #define CAN_F5R2_FB3_Pos (3U)
Kojto 122:f9eeca106725 4781 #define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4782 #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 4783 #define CAN_F5R2_FB4_Pos (4U)
Kojto 122:f9eeca106725 4784 #define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4785 #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 4786 #define CAN_F5R2_FB5_Pos (5U)
Kojto 122:f9eeca106725 4787 #define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 4788 #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 4789 #define CAN_F5R2_FB6_Pos (6U)
Kojto 122:f9eeca106725 4790 #define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4791 #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 4792 #define CAN_F5R2_FB7_Pos (7U)
Kojto 122:f9eeca106725 4793 #define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 4794 #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 4795 #define CAN_F5R2_FB8_Pos (8U)
Kojto 122:f9eeca106725 4796 #define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 4797 #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 4798 #define CAN_F5R2_FB9_Pos (9U)
Kojto 122:f9eeca106725 4799 #define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 4800 #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 4801 #define CAN_F5R2_FB10_Pos (10U)
Kojto 122:f9eeca106725 4802 #define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4803 #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 4804 #define CAN_F5R2_FB11_Pos (11U)
Kojto 122:f9eeca106725 4805 #define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 4806 #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 4807 #define CAN_F5R2_FB12_Pos (12U)
Kojto 122:f9eeca106725 4808 #define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 4809 #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 4810 #define CAN_F5R2_FB13_Pos (13U)
Kojto 122:f9eeca106725 4811 #define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 4812 #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 4813 #define CAN_F5R2_FB14_Pos (14U)
Kojto 122:f9eeca106725 4814 #define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 4815 #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 4816 #define CAN_F5R2_FB15_Pos (15U)
Kojto 122:f9eeca106725 4817 #define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 4818 #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 4819 #define CAN_F5R2_FB16_Pos (16U)
Kojto 122:f9eeca106725 4820 #define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 4821 #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 4822 #define CAN_F5R2_FB17_Pos (17U)
Kojto 122:f9eeca106725 4823 #define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 4824 #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 4825 #define CAN_F5R2_FB18_Pos (18U)
Kojto 122:f9eeca106725 4826 #define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 4827 #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 4828 #define CAN_F5R2_FB19_Pos (19U)
Kojto 122:f9eeca106725 4829 #define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 4830 #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 4831 #define CAN_F5R2_FB20_Pos (20U)
Kojto 122:f9eeca106725 4832 #define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 4833 #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 4834 #define CAN_F5R2_FB21_Pos (21U)
Kojto 122:f9eeca106725 4835 #define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 4836 #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 4837 #define CAN_F5R2_FB22_Pos (22U)
Kojto 122:f9eeca106725 4838 #define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 4839 #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 4840 #define CAN_F5R2_FB23_Pos (23U)
Kojto 122:f9eeca106725 4841 #define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 4842 #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 4843 #define CAN_F5R2_FB24_Pos (24U)
Kojto 122:f9eeca106725 4844 #define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 4845 #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 4846 #define CAN_F5R2_FB25_Pos (25U)
Kojto 122:f9eeca106725 4847 #define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 4848 #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 4849 #define CAN_F5R2_FB26_Pos (26U)
Kojto 122:f9eeca106725 4850 #define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 4851 #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 4852 #define CAN_F5R2_FB27_Pos (27U)
Kojto 122:f9eeca106725 4853 #define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 4854 #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 4855 #define CAN_F5R2_FB28_Pos (28U)
Kojto 122:f9eeca106725 4856 #define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 4857 #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 4858 #define CAN_F5R2_FB29_Pos (29U)
Kojto 122:f9eeca106725 4859 #define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 4860 #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 4861 #define CAN_F5R2_FB30_Pos (30U)
Kojto 122:f9eeca106725 4862 #define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 4863 #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 4864 #define CAN_F5R2_FB31_Pos (31U)
Kojto 122:f9eeca106725 4865 #define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 4866 #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
Kojto 122:f9eeca106725 4867
Kojto 122:f9eeca106725 4868 /******************* Bit definition for CAN_F6R2 register *******************/
Kojto 122:f9eeca106725 4869 #define CAN_F6R2_FB0_Pos (0U)
Kojto 122:f9eeca106725 4870 #define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4871 #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 4872 #define CAN_F6R2_FB1_Pos (1U)
Kojto 122:f9eeca106725 4873 #define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 4874 #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 4875 #define CAN_F6R2_FB2_Pos (2U)
Kojto 122:f9eeca106725 4876 #define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4877 #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 4878 #define CAN_F6R2_FB3_Pos (3U)
Kojto 122:f9eeca106725 4879 #define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4880 #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 4881 #define CAN_F6R2_FB4_Pos (4U)
Kojto 122:f9eeca106725 4882 #define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4883 #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 4884 #define CAN_F6R2_FB5_Pos (5U)
Kojto 122:f9eeca106725 4885 #define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 4886 #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 4887 #define CAN_F6R2_FB6_Pos (6U)
Kojto 122:f9eeca106725 4888 #define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4889 #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 4890 #define CAN_F6R2_FB7_Pos (7U)
Kojto 122:f9eeca106725 4891 #define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 4892 #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 4893 #define CAN_F6R2_FB8_Pos (8U)
Kojto 122:f9eeca106725 4894 #define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 4895 #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 4896 #define CAN_F6R2_FB9_Pos (9U)
Kojto 122:f9eeca106725 4897 #define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 4898 #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 4899 #define CAN_F6R2_FB10_Pos (10U)
Kojto 122:f9eeca106725 4900 #define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4901 #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 4902 #define CAN_F6R2_FB11_Pos (11U)
Kojto 122:f9eeca106725 4903 #define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 4904 #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 4905 #define CAN_F6R2_FB12_Pos (12U)
Kojto 122:f9eeca106725 4906 #define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 4907 #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 4908 #define CAN_F6R2_FB13_Pos (13U)
Kojto 122:f9eeca106725 4909 #define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 4910 #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 4911 #define CAN_F6R2_FB14_Pos (14U)
Kojto 122:f9eeca106725 4912 #define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 4913 #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 4914 #define CAN_F6R2_FB15_Pos (15U)
Kojto 122:f9eeca106725 4915 #define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 4916 #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 4917 #define CAN_F6R2_FB16_Pos (16U)
Kojto 122:f9eeca106725 4918 #define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 4919 #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 4920 #define CAN_F6R2_FB17_Pos (17U)
Kojto 122:f9eeca106725 4921 #define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 4922 #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 4923 #define CAN_F6R2_FB18_Pos (18U)
Kojto 122:f9eeca106725 4924 #define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 4925 #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 4926 #define CAN_F6R2_FB19_Pos (19U)
Kojto 122:f9eeca106725 4927 #define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 4928 #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 4929 #define CAN_F6R2_FB20_Pos (20U)
Kojto 122:f9eeca106725 4930 #define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 4931 #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 4932 #define CAN_F6R2_FB21_Pos (21U)
Kojto 122:f9eeca106725 4933 #define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 4934 #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 4935 #define CAN_F6R2_FB22_Pos (22U)
Kojto 122:f9eeca106725 4936 #define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 4937 #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 4938 #define CAN_F6R2_FB23_Pos (23U)
Kojto 122:f9eeca106725 4939 #define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 4940 #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 4941 #define CAN_F6R2_FB24_Pos (24U)
Kojto 122:f9eeca106725 4942 #define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 4943 #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 4944 #define CAN_F6R2_FB25_Pos (25U)
Kojto 122:f9eeca106725 4945 #define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 4946 #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 4947 #define CAN_F6R2_FB26_Pos (26U)
Kojto 122:f9eeca106725 4948 #define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 4949 #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 4950 #define CAN_F6R2_FB27_Pos (27U)
Kojto 122:f9eeca106725 4951 #define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 4952 #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 4953 #define CAN_F6R2_FB28_Pos (28U)
Kojto 122:f9eeca106725 4954 #define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 4955 #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 4956 #define CAN_F6R2_FB29_Pos (29U)
Kojto 122:f9eeca106725 4957 #define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 4958 #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 4959 #define CAN_F6R2_FB30_Pos (30U)
Kojto 122:f9eeca106725 4960 #define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 4961 #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 4962 #define CAN_F6R2_FB31_Pos (31U)
Kojto 122:f9eeca106725 4963 #define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 4964 #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
Kojto 122:f9eeca106725 4965
Kojto 122:f9eeca106725 4966 /******************* Bit definition for CAN_F7R2 register *******************/
Kojto 122:f9eeca106725 4967 #define CAN_F7R2_FB0_Pos (0U)
Kojto 122:f9eeca106725 4968 #define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4969 #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 4970 #define CAN_F7R2_FB1_Pos (1U)
Kojto 122:f9eeca106725 4971 #define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 4972 #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 4973 #define CAN_F7R2_FB2_Pos (2U)
Kojto 122:f9eeca106725 4974 #define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4975 #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 4976 #define CAN_F7R2_FB3_Pos (3U)
Kojto 122:f9eeca106725 4977 #define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4978 #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 4979 #define CAN_F7R2_FB4_Pos (4U)
Kojto 122:f9eeca106725 4980 #define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4981 #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 4982 #define CAN_F7R2_FB5_Pos (5U)
Kojto 122:f9eeca106725 4983 #define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 4984 #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 4985 #define CAN_F7R2_FB6_Pos (6U)
Kojto 122:f9eeca106725 4986 #define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4987 #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 4988 #define CAN_F7R2_FB7_Pos (7U)
Kojto 122:f9eeca106725 4989 #define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 4990 #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 4991 #define CAN_F7R2_FB8_Pos (8U)
Kojto 122:f9eeca106725 4992 #define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 4993 #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 4994 #define CAN_F7R2_FB9_Pos (9U)
Kojto 122:f9eeca106725 4995 #define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 4996 #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 4997 #define CAN_F7R2_FB10_Pos (10U)
Kojto 122:f9eeca106725 4998 #define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4999 #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 5000 #define CAN_F7R2_FB11_Pos (11U)
Kojto 122:f9eeca106725 5001 #define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 5002 #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 5003 #define CAN_F7R2_FB12_Pos (12U)
Kojto 122:f9eeca106725 5004 #define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 5005 #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 5006 #define CAN_F7R2_FB13_Pos (13U)
Kojto 122:f9eeca106725 5007 #define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 5008 #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 5009 #define CAN_F7R2_FB14_Pos (14U)
Kojto 122:f9eeca106725 5010 #define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 5011 #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 5012 #define CAN_F7R2_FB15_Pos (15U)
Kojto 122:f9eeca106725 5013 #define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 5014 #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 5015 #define CAN_F7R2_FB16_Pos (16U)
Kojto 122:f9eeca106725 5016 #define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 5017 #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 5018 #define CAN_F7R2_FB17_Pos (17U)
Kojto 122:f9eeca106725 5019 #define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 5020 #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 5021 #define CAN_F7R2_FB18_Pos (18U)
Kojto 122:f9eeca106725 5022 #define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 5023 #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 5024 #define CAN_F7R2_FB19_Pos (19U)
Kojto 122:f9eeca106725 5025 #define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 5026 #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 5027 #define CAN_F7R2_FB20_Pos (20U)
Kojto 122:f9eeca106725 5028 #define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 5029 #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 5030 #define CAN_F7R2_FB21_Pos (21U)
Kojto 122:f9eeca106725 5031 #define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 5032 #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 5033 #define CAN_F7R2_FB22_Pos (22U)
Kojto 122:f9eeca106725 5034 #define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 5035 #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 5036 #define CAN_F7R2_FB23_Pos (23U)
Kojto 122:f9eeca106725 5037 #define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 5038 #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 5039 #define CAN_F7R2_FB24_Pos (24U)
Kojto 122:f9eeca106725 5040 #define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 5041 #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 5042 #define CAN_F7R2_FB25_Pos (25U)
Kojto 122:f9eeca106725 5043 #define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 5044 #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 5045 #define CAN_F7R2_FB26_Pos (26U)
Kojto 122:f9eeca106725 5046 #define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 5047 #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 5048 #define CAN_F7R2_FB27_Pos (27U)
Kojto 122:f9eeca106725 5049 #define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 5050 #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 5051 #define CAN_F7R2_FB28_Pos (28U)
Kojto 122:f9eeca106725 5052 #define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 5053 #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 5054 #define CAN_F7R2_FB29_Pos (29U)
Kojto 122:f9eeca106725 5055 #define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 5056 #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 5057 #define CAN_F7R2_FB30_Pos (30U)
Kojto 122:f9eeca106725 5058 #define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 5059 #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 5060 #define CAN_F7R2_FB31_Pos (31U)
Kojto 122:f9eeca106725 5061 #define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 5062 #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
Kojto 122:f9eeca106725 5063
Kojto 122:f9eeca106725 5064 /******************* Bit definition for CAN_F8R2 register *******************/
Kojto 122:f9eeca106725 5065 #define CAN_F8R2_FB0_Pos (0U)
Kojto 122:f9eeca106725 5066 #define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 5067 #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 5068 #define CAN_F8R2_FB1_Pos (1U)
Kojto 122:f9eeca106725 5069 #define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 5070 #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 5071 #define CAN_F8R2_FB2_Pos (2U)
Kojto 122:f9eeca106725 5072 #define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 5073 #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 5074 #define CAN_F8R2_FB3_Pos (3U)
Kojto 122:f9eeca106725 5075 #define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 5076 #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 5077 #define CAN_F8R2_FB4_Pos (4U)
Kojto 122:f9eeca106725 5078 #define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 5079 #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 5080 #define CAN_F8R2_FB5_Pos (5U)
Kojto 122:f9eeca106725 5081 #define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 5082 #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 5083 #define CAN_F8R2_FB6_Pos (6U)
Kojto 122:f9eeca106725 5084 #define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 5085 #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 5086 #define CAN_F8R2_FB7_Pos (7U)
Kojto 122:f9eeca106725 5087 #define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 5088 #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 5089 #define CAN_F8R2_FB8_Pos (8U)
Kojto 122:f9eeca106725 5090 #define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 5091 #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 5092 #define CAN_F8R2_FB9_Pos (9U)
Kojto 122:f9eeca106725 5093 #define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 5094 #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 5095 #define CAN_F8R2_FB10_Pos (10U)
Kojto 122:f9eeca106725 5096 #define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 5097 #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 5098 #define CAN_F8R2_FB11_Pos (11U)
Kojto 122:f9eeca106725 5099 #define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 5100 #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 5101 #define CAN_F8R2_FB12_Pos (12U)
Kojto 122:f9eeca106725 5102 #define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 5103 #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 5104 #define CAN_F8R2_FB13_Pos (13U)
Kojto 122:f9eeca106725 5105 #define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 5106 #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 5107 #define CAN_F8R2_FB14_Pos (14U)
Kojto 122:f9eeca106725 5108 #define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 5109 #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 5110 #define CAN_F8R2_FB15_Pos (15U)
Kojto 122:f9eeca106725 5111 #define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 5112 #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 5113 #define CAN_F8R2_FB16_Pos (16U)
Kojto 122:f9eeca106725 5114 #define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 5115 #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 5116 #define CAN_F8R2_FB17_Pos (17U)
Kojto 122:f9eeca106725 5117 #define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 5118 #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 5119 #define CAN_F8R2_FB18_Pos (18U)
Kojto 122:f9eeca106725 5120 #define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 5121 #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 5122 #define CAN_F8R2_FB19_Pos (19U)
Kojto 122:f9eeca106725 5123 #define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 5124 #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 5125 #define CAN_F8R2_FB20_Pos (20U)
Kojto 122:f9eeca106725 5126 #define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 5127 #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 5128 #define CAN_F8R2_FB21_Pos (21U)
Kojto 122:f9eeca106725 5129 #define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 5130 #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 5131 #define CAN_F8R2_FB22_Pos (22U)
Kojto 122:f9eeca106725 5132 #define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 5133 #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 5134 #define CAN_F8R2_FB23_Pos (23U)
Kojto 122:f9eeca106725 5135 #define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 5136 #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 5137 #define CAN_F8R2_FB24_Pos (24U)
Kojto 122:f9eeca106725 5138 #define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 5139 #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 5140 #define CAN_F8R2_FB25_Pos (25U)
Kojto 122:f9eeca106725 5141 #define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 5142 #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 5143 #define CAN_F8R2_FB26_Pos (26U)
Kojto 122:f9eeca106725 5144 #define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 5145 #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 5146 #define CAN_F8R2_FB27_Pos (27U)
Kojto 122:f9eeca106725 5147 #define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 5148 #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 5149 #define CAN_F8R2_FB28_Pos (28U)
Kojto 122:f9eeca106725 5150 #define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 5151 #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 5152 #define CAN_F8R2_FB29_Pos (29U)
Kojto 122:f9eeca106725 5153 #define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 5154 #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 5155 #define CAN_F8R2_FB30_Pos (30U)
Kojto 122:f9eeca106725 5156 #define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 5157 #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 5158 #define CAN_F8R2_FB31_Pos (31U)
Kojto 122:f9eeca106725 5159 #define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 5160 #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
Kojto 122:f9eeca106725 5161
Kojto 122:f9eeca106725 5162 /******************* Bit definition for CAN_F9R2 register *******************/
Kojto 122:f9eeca106725 5163 #define CAN_F9R2_FB0_Pos (0U)
Kojto 122:f9eeca106725 5164 #define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 5165 #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 5166 #define CAN_F9R2_FB1_Pos (1U)
Kojto 122:f9eeca106725 5167 #define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 5168 #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 5169 #define CAN_F9R2_FB2_Pos (2U)
Kojto 122:f9eeca106725 5170 #define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 5171 #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 5172 #define CAN_F9R2_FB3_Pos (3U)
Kojto 122:f9eeca106725 5173 #define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 5174 #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 5175 #define CAN_F9R2_FB4_Pos (4U)
Kojto 122:f9eeca106725 5176 #define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 5177 #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 5178 #define CAN_F9R2_FB5_Pos (5U)
Kojto 122:f9eeca106725 5179 #define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 5180 #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 5181 #define CAN_F9R2_FB6_Pos (6U)
Kojto 122:f9eeca106725 5182 #define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 5183 #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 5184 #define CAN_F9R2_FB7_Pos (7U)
Kojto 122:f9eeca106725 5185 #define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 5186 #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 5187 #define CAN_F9R2_FB8_Pos (8U)
Kojto 122:f9eeca106725 5188 #define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 5189 #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 5190 #define CAN_F9R2_FB9_Pos (9U)
Kojto 122:f9eeca106725 5191 #define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 5192 #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 5193 #define CAN_F9R2_FB10_Pos (10U)
Kojto 122:f9eeca106725 5194 #define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 5195 #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 5196 #define CAN_F9R2_FB11_Pos (11U)
Kojto 122:f9eeca106725 5197 #define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 5198 #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 5199 #define CAN_F9R2_FB12_Pos (12U)
Kojto 122:f9eeca106725 5200 #define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 5201 #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 5202 #define CAN_F9R2_FB13_Pos (13U)
Kojto 122:f9eeca106725 5203 #define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 5204 #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 5205 #define CAN_F9R2_FB14_Pos (14U)
Kojto 122:f9eeca106725 5206 #define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 5207 #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 5208 #define CAN_F9R2_FB15_Pos (15U)
Kojto 122:f9eeca106725 5209 #define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 5210 #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 5211 #define CAN_F9R2_FB16_Pos (16U)
Kojto 122:f9eeca106725 5212 #define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 5213 #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 5214 #define CAN_F9R2_FB17_Pos (17U)
Kojto 122:f9eeca106725 5215 #define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 5216 #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 5217 #define CAN_F9R2_FB18_Pos (18U)
Kojto 122:f9eeca106725 5218 #define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 5219 #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 5220 #define CAN_F9R2_FB19_Pos (19U)
Kojto 122:f9eeca106725 5221 #define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 5222 #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 5223 #define CAN_F9R2_FB20_Pos (20U)
Kojto 122:f9eeca106725 5224 #define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 5225 #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 5226 #define CAN_F9R2_FB21_Pos (21U)
Kojto 122:f9eeca106725 5227 #define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 5228 #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 5229 #define CAN_F9R2_FB22_Pos (22U)
Kojto 122:f9eeca106725 5230 #define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 5231 #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 5232 #define CAN_F9R2_FB23_Pos (23U)
Kojto 122:f9eeca106725 5233 #define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 5234 #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 5235 #define CAN_F9R2_FB24_Pos (24U)
Kojto 122:f9eeca106725 5236 #define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 5237 #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 5238 #define CAN_F9R2_FB25_Pos (25U)
Kojto 122:f9eeca106725 5239 #define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 5240 #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 5241 #define CAN_F9R2_FB26_Pos (26U)
Kojto 122:f9eeca106725 5242 #define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 5243 #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 5244 #define CAN_F9R2_FB27_Pos (27U)
Kojto 122:f9eeca106725 5245 #define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 5246 #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 5247 #define CAN_F9R2_FB28_Pos (28U)
Kojto 122:f9eeca106725 5248 #define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 5249 #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 5250 #define CAN_F9R2_FB29_Pos (29U)
Kojto 122:f9eeca106725 5251 #define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 5252 #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 5253 #define CAN_F9R2_FB30_Pos (30U)
Kojto 122:f9eeca106725 5254 #define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 5255 #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 5256 #define CAN_F9R2_FB31_Pos (31U)
Kojto 122:f9eeca106725 5257 #define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 5258 #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
Kojto 122:f9eeca106725 5259
Kojto 122:f9eeca106725 5260 /******************* Bit definition for CAN_F10R2 register ******************/
Kojto 122:f9eeca106725 5261 #define CAN_F10R2_FB0_Pos (0U)
Kojto 122:f9eeca106725 5262 #define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 5263 #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 5264 #define CAN_F10R2_FB1_Pos (1U)
Kojto 122:f9eeca106725 5265 #define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 5266 #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 5267 #define CAN_F10R2_FB2_Pos (2U)
Kojto 122:f9eeca106725 5268 #define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 5269 #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 5270 #define CAN_F10R2_FB3_Pos (3U)
Kojto 122:f9eeca106725 5271 #define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 5272 #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 5273 #define CAN_F10R2_FB4_Pos (4U)
Kojto 122:f9eeca106725 5274 #define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 5275 #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 5276 #define CAN_F10R2_FB5_Pos (5U)
Kojto 122:f9eeca106725 5277 #define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 5278 #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 5279 #define CAN_F10R2_FB6_Pos (6U)
Kojto 122:f9eeca106725 5280 #define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 5281 #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 5282 #define CAN_F10R2_FB7_Pos (7U)
Kojto 122:f9eeca106725 5283 #define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 5284 #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 5285 #define CAN_F10R2_FB8_Pos (8U)
Kojto 122:f9eeca106725 5286 #define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 5287 #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 5288 #define CAN_F10R2_FB9_Pos (9U)
Kojto 122:f9eeca106725 5289 #define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 5290 #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 5291 #define CAN_F10R2_FB10_Pos (10U)
Kojto 122:f9eeca106725 5292 #define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 5293 #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 5294 #define CAN_F10R2_FB11_Pos (11U)
Kojto 122:f9eeca106725 5295 #define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 5296 #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 5297 #define CAN_F10R2_FB12_Pos (12U)
Kojto 122:f9eeca106725 5298 #define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 5299 #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 5300 #define CAN_F10R2_FB13_Pos (13U)
Kojto 122:f9eeca106725 5301 #define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 5302 #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 5303 #define CAN_F10R2_FB14_Pos (14U)
Kojto 122:f9eeca106725 5304 #define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 5305 #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 5306 #define CAN_F10R2_FB15_Pos (15U)
Kojto 122:f9eeca106725 5307 #define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 5308 #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 5309 #define CAN_F10R2_FB16_Pos (16U)
Kojto 122:f9eeca106725 5310 #define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 5311 #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 5312 #define CAN_F10R2_FB17_Pos (17U)
Kojto 122:f9eeca106725 5313 #define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 5314 #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 5315 #define CAN_F10R2_FB18_Pos (18U)
Kojto 122:f9eeca106725 5316 #define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 5317 #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 5318 #define CAN_F10R2_FB19_Pos (19U)
Kojto 122:f9eeca106725 5319 #define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 5320 #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 5321 #define CAN_F10R2_FB20_Pos (20U)
Kojto 122:f9eeca106725 5322 #define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 5323 #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 5324 #define CAN_F10R2_FB21_Pos (21U)
Kojto 122:f9eeca106725 5325 #define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 5326 #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 5327 #define CAN_F10R2_FB22_Pos (22U)
Kojto 122:f9eeca106725 5328 #define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 5329 #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 5330 #define CAN_F10R2_FB23_Pos (23U)
Kojto 122:f9eeca106725 5331 #define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 5332 #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 5333 #define CAN_F10R2_FB24_Pos (24U)
Kojto 122:f9eeca106725 5334 #define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 5335 #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 5336 #define CAN_F10R2_FB25_Pos (25U)
Kojto 122:f9eeca106725 5337 #define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 5338 #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 5339 #define CAN_F10R2_FB26_Pos (26U)
Kojto 122:f9eeca106725 5340 #define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 5341 #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 5342 #define CAN_F10R2_FB27_Pos (27U)
Kojto 122:f9eeca106725 5343 #define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 5344 #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 5345 #define CAN_F10R2_FB28_Pos (28U)
Kojto 122:f9eeca106725 5346 #define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 5347 #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 5348 #define CAN_F10R2_FB29_Pos (29U)
Kojto 122:f9eeca106725 5349 #define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 5350 #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 5351 #define CAN_F10R2_FB30_Pos (30U)
Kojto 122:f9eeca106725 5352 #define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 5353 #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 5354 #define CAN_F10R2_FB31_Pos (31U)
Kojto 122:f9eeca106725 5355 #define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 5356 #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
Kojto 122:f9eeca106725 5357
Kojto 122:f9eeca106725 5358 /******************* Bit definition for CAN_F11R2 register ******************/
Kojto 122:f9eeca106725 5359 #define CAN_F11R2_FB0_Pos (0U)
Kojto 122:f9eeca106725 5360 #define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 5361 #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 5362 #define CAN_F11R2_FB1_Pos (1U)
Kojto 122:f9eeca106725 5363 #define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 5364 #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 5365 #define CAN_F11R2_FB2_Pos (2U)
Kojto 122:f9eeca106725 5366 #define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 5367 #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 5368 #define CAN_F11R2_FB3_Pos (3U)
Kojto 122:f9eeca106725 5369 #define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 5370 #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 5371 #define CAN_F11R2_FB4_Pos (4U)
Kojto 122:f9eeca106725 5372 #define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 5373 #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 5374 #define CAN_F11R2_FB5_Pos (5U)
Kojto 122:f9eeca106725 5375 #define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 5376 #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 5377 #define CAN_F11R2_FB6_Pos (6U)
Kojto 122:f9eeca106725 5378 #define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 5379 #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 5380 #define CAN_F11R2_FB7_Pos (7U)
Kojto 122:f9eeca106725 5381 #define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 5382 #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 5383 #define CAN_F11R2_FB8_Pos (8U)
Kojto 122:f9eeca106725 5384 #define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 5385 #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 5386 #define CAN_F11R2_FB9_Pos (9U)
Kojto 122:f9eeca106725 5387 #define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 5388 #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 5389 #define CAN_F11R2_FB10_Pos (10U)
Kojto 122:f9eeca106725 5390 #define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 5391 #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 5392 #define CAN_F11R2_FB11_Pos (11U)
Kojto 122:f9eeca106725 5393 #define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 5394 #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 5395 #define CAN_F11R2_FB12_Pos (12U)
Kojto 122:f9eeca106725 5396 #define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 5397 #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 5398 #define CAN_F11R2_FB13_Pos (13U)
Kojto 122:f9eeca106725 5399 #define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 5400 #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 5401 #define CAN_F11R2_FB14_Pos (14U)
Kojto 122:f9eeca106725 5402 #define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 5403 #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 5404 #define CAN_F11R2_FB15_Pos (15U)
Kojto 122:f9eeca106725 5405 #define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 5406 #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 5407 #define CAN_F11R2_FB16_Pos (16U)
Kojto 122:f9eeca106725 5408 #define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 5409 #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 5410 #define CAN_F11R2_FB17_Pos (17U)
Kojto 122:f9eeca106725 5411 #define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 5412 #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 5413 #define CAN_F11R2_FB18_Pos (18U)
Kojto 122:f9eeca106725 5414 #define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 5415 #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 5416 #define CAN_F11R2_FB19_Pos (19U)
Kojto 122:f9eeca106725 5417 #define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 5418 #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 5419 #define CAN_F11R2_FB20_Pos (20U)
Kojto 122:f9eeca106725 5420 #define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 5421 #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 5422 #define CAN_F11R2_FB21_Pos (21U)
Kojto 122:f9eeca106725 5423 #define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 5424 #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 5425 #define CAN_F11R2_FB22_Pos (22U)
Kojto 122:f9eeca106725 5426 #define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 5427 #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 5428 #define CAN_F11R2_FB23_Pos (23U)
Kojto 122:f9eeca106725 5429 #define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 5430 #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 5431 #define CAN_F11R2_FB24_Pos (24U)
Kojto 122:f9eeca106725 5432 #define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 5433 #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 5434 #define CAN_F11R2_FB25_Pos (25U)
Kojto 122:f9eeca106725 5435 #define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 5436 #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 5437 #define CAN_F11R2_FB26_Pos (26U)
Kojto 122:f9eeca106725 5438 #define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 5439 #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 5440 #define CAN_F11R2_FB27_Pos (27U)
Kojto 122:f9eeca106725 5441 #define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 5442 #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 5443 #define CAN_F11R2_FB28_Pos (28U)
Kojto 122:f9eeca106725 5444 #define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 5445 #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 5446 #define CAN_F11R2_FB29_Pos (29U)
Kojto 122:f9eeca106725 5447 #define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 5448 #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 5449 #define CAN_F11R2_FB30_Pos (30U)
Kojto 122:f9eeca106725 5450 #define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 5451 #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 5452 #define CAN_F11R2_FB31_Pos (31U)
Kojto 122:f9eeca106725 5453 #define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 5454 #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
Kojto 122:f9eeca106725 5455
Kojto 122:f9eeca106725 5456 /******************* Bit definition for CAN_F12R2 register ******************/
Kojto 122:f9eeca106725 5457 #define CAN_F12R2_FB0_Pos (0U)
Kojto 122:f9eeca106725 5458 #define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 5459 #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 5460 #define CAN_F12R2_FB1_Pos (1U)
Kojto 122:f9eeca106725 5461 #define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 5462 #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 5463 #define CAN_F12R2_FB2_Pos (2U)
Kojto 122:f9eeca106725 5464 #define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 5465 #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 5466 #define CAN_F12R2_FB3_Pos (3U)
Kojto 122:f9eeca106725 5467 #define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 5468 #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 5469 #define CAN_F12R2_FB4_Pos (4U)
Kojto 122:f9eeca106725 5470 #define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 5471 #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 5472 #define CAN_F12R2_FB5_Pos (5U)
Kojto 122:f9eeca106725 5473 #define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 5474 #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 5475 #define CAN_F12R2_FB6_Pos (6U)
Kojto 122:f9eeca106725 5476 #define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 5477 #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 5478 #define CAN_F12R2_FB7_Pos (7U)
Kojto 122:f9eeca106725 5479 #define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 5480 #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 5481 #define CAN_F12R2_FB8_Pos (8U)
Kojto 122:f9eeca106725 5482 #define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 5483 #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 5484 #define CAN_F12R2_FB9_Pos (9U)
Kojto 122:f9eeca106725 5485 #define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 5486 #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 5487 #define CAN_F12R2_FB10_Pos (10U)
Kojto 122:f9eeca106725 5488 #define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 5489 #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 5490 #define CAN_F12R2_FB11_Pos (11U)
Kojto 122:f9eeca106725 5491 #define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 5492 #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 5493 #define CAN_F12R2_FB12_Pos (12U)
Kojto 122:f9eeca106725 5494 #define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 5495 #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 5496 #define CAN_F12R2_FB13_Pos (13U)
Kojto 122:f9eeca106725 5497 #define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 5498 #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 5499 #define CAN_F12R2_FB14_Pos (14U)
Kojto 122:f9eeca106725 5500 #define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 5501 #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 5502 #define CAN_F12R2_FB15_Pos (15U)
Kojto 122:f9eeca106725 5503 #define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 5504 #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 5505 #define CAN_F12R2_FB16_Pos (16U)
Kojto 122:f9eeca106725 5506 #define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 5507 #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 5508 #define CAN_F12R2_FB17_Pos (17U)
Kojto 122:f9eeca106725 5509 #define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 5510 #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 5511 #define CAN_F12R2_FB18_Pos (18U)
Kojto 122:f9eeca106725 5512 #define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 5513 #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 5514 #define CAN_F12R2_FB19_Pos (19U)
Kojto 122:f9eeca106725 5515 #define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 5516 #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 5517 #define CAN_F12R2_FB20_Pos (20U)
Kojto 122:f9eeca106725 5518 #define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 5519 #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 5520 #define CAN_F12R2_FB21_Pos (21U)
Kojto 122:f9eeca106725 5521 #define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 5522 #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 5523 #define CAN_F12R2_FB22_Pos (22U)
Kojto 122:f9eeca106725 5524 #define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 5525 #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 5526 #define CAN_F12R2_FB23_Pos (23U)
Kojto 122:f9eeca106725 5527 #define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 5528 #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 5529 #define CAN_F12R2_FB24_Pos (24U)
Kojto 122:f9eeca106725 5530 #define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 5531 #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 5532 #define CAN_F12R2_FB25_Pos (25U)
Kojto 122:f9eeca106725 5533 #define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 5534 #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 5535 #define CAN_F12R2_FB26_Pos (26U)
Kojto 122:f9eeca106725 5536 #define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 5537 #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 5538 #define CAN_F12R2_FB27_Pos (27U)
Kojto 122:f9eeca106725 5539 #define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 5540 #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 5541 #define CAN_F12R2_FB28_Pos (28U)
Kojto 122:f9eeca106725 5542 #define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 5543 #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 5544 #define CAN_F12R2_FB29_Pos (29U)
Kojto 122:f9eeca106725 5545 #define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 5546 #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 5547 #define CAN_F12R2_FB30_Pos (30U)
Kojto 122:f9eeca106725 5548 #define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 5549 #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 5550 #define CAN_F12R2_FB31_Pos (31U)
Kojto 122:f9eeca106725 5551 #define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 5552 #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
Kojto 122:f9eeca106725 5553
Kojto 122:f9eeca106725 5554 /******************* Bit definition for CAN_F13R2 register ******************/
Kojto 122:f9eeca106725 5555 #define CAN_F13R2_FB0_Pos (0U)
Kojto 122:f9eeca106725 5556 #define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 5557 #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
Kojto 122:f9eeca106725 5558 #define CAN_F13R2_FB1_Pos (1U)
Kojto 122:f9eeca106725 5559 #define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 5560 #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
Kojto 122:f9eeca106725 5561 #define CAN_F13R2_FB2_Pos (2U)
Kojto 122:f9eeca106725 5562 #define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 5563 #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
Kojto 122:f9eeca106725 5564 #define CAN_F13R2_FB3_Pos (3U)
Kojto 122:f9eeca106725 5565 #define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 5566 #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
Kojto 122:f9eeca106725 5567 #define CAN_F13R2_FB4_Pos (4U)
Kojto 122:f9eeca106725 5568 #define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 5569 #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
Kojto 122:f9eeca106725 5570 #define CAN_F13R2_FB5_Pos (5U)
Kojto 122:f9eeca106725 5571 #define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 5572 #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
Kojto 122:f9eeca106725 5573 #define CAN_F13R2_FB6_Pos (6U)
Kojto 122:f9eeca106725 5574 #define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 5575 #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
Kojto 122:f9eeca106725 5576 #define CAN_F13R2_FB7_Pos (7U)
Kojto 122:f9eeca106725 5577 #define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 5578 #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
Kojto 122:f9eeca106725 5579 #define CAN_F13R2_FB8_Pos (8U)
Kojto 122:f9eeca106725 5580 #define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 5581 #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
Kojto 122:f9eeca106725 5582 #define CAN_F13R2_FB9_Pos (9U)
Kojto 122:f9eeca106725 5583 #define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 5584 #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
Kojto 122:f9eeca106725 5585 #define CAN_F13R2_FB10_Pos (10U)
Kojto 122:f9eeca106725 5586 #define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 5587 #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
Kojto 122:f9eeca106725 5588 #define CAN_F13R2_FB11_Pos (11U)
Kojto 122:f9eeca106725 5589 #define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 5590 #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
Kojto 122:f9eeca106725 5591 #define CAN_F13R2_FB12_Pos (12U)
Kojto 122:f9eeca106725 5592 #define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 5593 #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
Kojto 122:f9eeca106725 5594 #define CAN_F13R2_FB13_Pos (13U)
Kojto 122:f9eeca106725 5595 #define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 5596 #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
Kojto 122:f9eeca106725 5597 #define CAN_F13R2_FB14_Pos (14U)
Kojto 122:f9eeca106725 5598 #define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 5599 #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
Kojto 122:f9eeca106725 5600 #define CAN_F13R2_FB15_Pos (15U)
Kojto 122:f9eeca106725 5601 #define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 5602 #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
Kojto 122:f9eeca106725 5603 #define CAN_F13R2_FB16_Pos (16U)
Kojto 122:f9eeca106725 5604 #define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 5605 #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
Kojto 122:f9eeca106725 5606 #define CAN_F13R2_FB17_Pos (17U)
Kojto 122:f9eeca106725 5607 #define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 5608 #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
Kojto 122:f9eeca106725 5609 #define CAN_F13R2_FB18_Pos (18U)
Kojto 122:f9eeca106725 5610 #define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 5611 #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
Kojto 122:f9eeca106725 5612 #define CAN_F13R2_FB19_Pos (19U)
Kojto 122:f9eeca106725 5613 #define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 5614 #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
Kojto 122:f9eeca106725 5615 #define CAN_F13R2_FB20_Pos (20U)
Kojto 122:f9eeca106725 5616 #define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 5617 #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
Kojto 122:f9eeca106725 5618 #define CAN_F13R2_FB21_Pos (21U)
Kojto 122:f9eeca106725 5619 #define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 5620 #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
Kojto 122:f9eeca106725 5621 #define CAN_F13R2_FB22_Pos (22U)
Kojto 122:f9eeca106725 5622 #define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 5623 #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
Kojto 122:f9eeca106725 5624 #define CAN_F13R2_FB23_Pos (23U)
Kojto 122:f9eeca106725 5625 #define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 5626 #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
Kojto 122:f9eeca106725 5627 #define CAN_F13R2_FB24_Pos (24U)
Kojto 122:f9eeca106725 5628 #define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 5629 #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
Kojto 122:f9eeca106725 5630 #define CAN_F13R2_FB25_Pos (25U)
Kojto 122:f9eeca106725 5631 #define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 5632 #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
Kojto 122:f9eeca106725 5633 #define CAN_F13R2_FB26_Pos (26U)
Kojto 122:f9eeca106725 5634 #define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 5635 #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
Kojto 122:f9eeca106725 5636 #define CAN_F13R2_FB27_Pos (27U)
Kojto 122:f9eeca106725 5637 #define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 5638 #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
Kojto 122:f9eeca106725 5639 #define CAN_F13R2_FB28_Pos (28U)
Kojto 122:f9eeca106725 5640 #define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 5641 #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
Kojto 122:f9eeca106725 5642 #define CAN_F13R2_FB29_Pos (29U)
Kojto 122:f9eeca106725 5643 #define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 5644 #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
Kojto 122:f9eeca106725 5645 #define CAN_F13R2_FB30_Pos (30U)
Kojto 122:f9eeca106725 5646 #define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 5647 #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
Kojto 122:f9eeca106725 5648 #define CAN_F13R2_FB31_Pos (31U)
Kojto 122:f9eeca106725 5649 #define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 5650 #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
Kojto 122:f9eeca106725 5651
Kojto 122:f9eeca106725 5652 /******************************************************************************/
Kojto 122:f9eeca106725 5653 /* */
Kojto 122:f9eeca106725 5654 /* CRC calculation unit */
Kojto 122:f9eeca106725 5655 /* */
Kojto 122:f9eeca106725 5656 /******************************************************************************/
Kojto 122:f9eeca106725 5657 /******************* Bit definition for CRC_DR register *********************/
Kojto 122:f9eeca106725 5658 #define CRC_DR_DR_Pos (0U)
Kojto 122:f9eeca106725 5659 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 5660 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
Kojto 122:f9eeca106725 5661
Kojto 122:f9eeca106725 5662 /******************* Bit definition for CRC_IDR register ********************/
Kojto 122:f9eeca106725 5663 #define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */
Kojto 122:f9eeca106725 5664
Kojto 122:f9eeca106725 5665 /******************** Bit definition for CRC_CR register ********************/
Kojto 122:f9eeca106725 5666 #define CRC_CR_RESET_Pos (0U)
Kojto 122:f9eeca106725 5667 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 5668 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
Kojto 122:f9eeca106725 5669 #define CRC_CR_POLYSIZE_Pos (3U)
Kojto 122:f9eeca106725 5670 #define CRC_CR_POLYSIZE_Msk (0x3U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
Kojto 122:f9eeca106725 5671 #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
Kojto 122:f9eeca106725 5672 #define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 5673 #define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 5674 #define CRC_CR_REV_IN_Pos (5U)
Kojto 122:f9eeca106725 5675 #define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
Kojto 122:f9eeca106725 5676 #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
Kojto 122:f9eeca106725 5677 #define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 5678 #define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 5679 #define CRC_CR_REV_OUT_Pos (7U)
Kojto 122:f9eeca106725 5680 #define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 5681 #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
Kojto 122:f9eeca106725 5682
Kojto 122:f9eeca106725 5683 /******************* Bit definition for CRC_INIT register *******************/
Kojto 122:f9eeca106725 5684 #define CRC_INIT_INIT_Pos (0U)
Kojto 122:f9eeca106725 5685 #define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 5686 #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
Kojto 122:f9eeca106725 5687
Kojto 122:f9eeca106725 5688 /******************* Bit definition for CRC_POL register ********************/
Kojto 122:f9eeca106725 5689 #define CRC_POL_POL_Pos (0U)
Kojto 122:f9eeca106725 5690 #define CRC_POL_POL_Msk (0xFFFFFFFFU << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 5691 #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
Kojto 122:f9eeca106725 5692
Kojto 122:f9eeca106725 5693 /******************************************************************************/
Kojto 122:f9eeca106725 5694 /* */
Kojto 122:f9eeca106725 5695 /* CRS Clock Recovery System */
Kojto 122:f9eeca106725 5696 /******************************************************************************/
Kojto 122:f9eeca106725 5697
Kojto 122:f9eeca106725 5698 /******************* Bit definition for CRS_CR register *********************/
Kojto 122:f9eeca106725 5699 #define CRS_CR_SYNCOKIE_Pos (0U)
Kojto 122:f9eeca106725 5700 #define CRS_CR_SYNCOKIE_Msk (0x1U << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 5701 #define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */
Kojto 122:f9eeca106725 5702 #define CRS_CR_SYNCWARNIE_Pos (1U)
Kojto 122:f9eeca106725 5703 #define CRS_CR_SYNCWARNIE_Msk (0x1U << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 5704 #define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */
Kojto 122:f9eeca106725 5705 #define CRS_CR_ERRIE_Pos (2U)
Kojto 122:f9eeca106725 5706 #define CRS_CR_ERRIE_Msk (0x1U << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 5707 #define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */
Kojto 122:f9eeca106725 5708 #define CRS_CR_ESYNCIE_Pos (3U)
Kojto 122:f9eeca106725 5709 #define CRS_CR_ESYNCIE_Msk (0x1U << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 5710 #define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */
Kojto 122:f9eeca106725 5711 #define CRS_CR_CEN_Pos (5U)
Kojto 122:f9eeca106725 5712 #define CRS_CR_CEN_Msk (0x1U << CRS_CR_CEN_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 5713 #define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */
Kojto 122:f9eeca106725 5714 #define CRS_CR_AUTOTRIMEN_Pos (6U)
Kojto 122:f9eeca106725 5715 #define CRS_CR_AUTOTRIMEN_Msk (0x1U << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 5716 #define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */
Kojto 122:f9eeca106725 5717 #define CRS_CR_SWSYNC_Pos (7U)
Kojto 122:f9eeca106725 5718 #define CRS_CR_SWSYNC_Msk (0x1U << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 5719 #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */
Kojto 122:f9eeca106725 5720 #define CRS_CR_TRIM_Pos (8U)
Kojto 122:f9eeca106725 5721 #define CRS_CR_TRIM_Msk (0x3FU << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */
Kojto 122:f9eeca106725 5722 #define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */
Kojto 122:f9eeca106725 5723
Kojto 122:f9eeca106725 5724 /******************* Bit definition for CRS_CFGR register *********************/
Kojto 122:f9eeca106725 5725 #define CRS_CFGR_RELOAD_Pos (0U)
Kojto 122:f9eeca106725 5726 #define CRS_CFGR_RELOAD_Msk (0xFFFFU << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 5727 #define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */
Kojto 122:f9eeca106725 5728 #define CRS_CFGR_FELIM_Pos (16U)
Kojto 122:f9eeca106725 5729 #define CRS_CFGR_FELIM_Msk (0xFFU << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 5730 #define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */
Kojto 122:f9eeca106725 5731
Kojto 122:f9eeca106725 5732 #define CRS_CFGR_SYNCDIV_Pos (24U)
Kojto 122:f9eeca106725 5733 #define CRS_CFGR_SYNCDIV_Msk (0x7U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */
Kojto 122:f9eeca106725 5734 #define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */
Kojto 122:f9eeca106725 5735 #define CRS_CFGR_SYNCDIV_0 (0x1U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 5736 #define CRS_CFGR_SYNCDIV_1 (0x2U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 5737 #define CRS_CFGR_SYNCDIV_2 (0x4U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 5738
Kojto 122:f9eeca106725 5739 #define CRS_CFGR_SYNCSRC_Pos (28U)
Kojto 122:f9eeca106725 5740 #define CRS_CFGR_SYNCSRC_Msk (0x3U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */
Kojto 122:f9eeca106725 5741 #define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */
Kojto 122:f9eeca106725 5742 #define CRS_CFGR_SYNCSRC_0 (0x1U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 5743 #define CRS_CFGR_SYNCSRC_1 (0x2U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 5744
Kojto 122:f9eeca106725 5745 #define CRS_CFGR_SYNCPOL_Pos (31U)
Kojto 122:f9eeca106725 5746 #define CRS_CFGR_SYNCPOL_Msk (0x1U << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 5747 #define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */
Kojto 122:f9eeca106725 5748
Kojto 122:f9eeca106725 5749 /******************* Bit definition for CRS_ISR register *********************/
Kojto 122:f9eeca106725 5750 #define CRS_ISR_SYNCOKF_Pos (0U)
Kojto 122:f9eeca106725 5751 #define CRS_ISR_SYNCOKF_Msk (0x1U << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 5752 #define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */
Kojto 122:f9eeca106725 5753 #define CRS_ISR_SYNCWARNF_Pos (1U)
Kojto 122:f9eeca106725 5754 #define CRS_ISR_SYNCWARNF_Msk (0x1U << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 5755 #define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */
Kojto 122:f9eeca106725 5756 #define CRS_ISR_ERRF_Pos (2U)
Kojto 122:f9eeca106725 5757 #define CRS_ISR_ERRF_Msk (0x1U << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 5758 #define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */
Kojto 122:f9eeca106725 5759 #define CRS_ISR_ESYNCF_Pos (3U)
Kojto 122:f9eeca106725 5760 #define CRS_ISR_ESYNCF_Msk (0x1U << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 5761 #define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */
Kojto 122:f9eeca106725 5762 #define CRS_ISR_SYNCERR_Pos (8U)
Kojto 122:f9eeca106725 5763 #define CRS_ISR_SYNCERR_Msk (0x1U << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 5764 #define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */
Kojto 122:f9eeca106725 5765 #define CRS_ISR_SYNCMISS_Pos (9U)
Kojto 122:f9eeca106725 5766 #define CRS_ISR_SYNCMISS_Msk (0x1U << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 5767 #define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */
Kojto 122:f9eeca106725 5768 #define CRS_ISR_TRIMOVF_Pos (10U)
Kojto 122:f9eeca106725 5769 #define CRS_ISR_TRIMOVF_Msk (0x1U << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 5770 #define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */
Kojto 122:f9eeca106725 5771 #define CRS_ISR_FEDIR_Pos (15U)
Kojto 122:f9eeca106725 5772 #define CRS_ISR_FEDIR_Msk (0x1U << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 5773 #define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */
Kojto 122:f9eeca106725 5774 #define CRS_ISR_FECAP_Pos (16U)
Kojto 122:f9eeca106725 5775 #define CRS_ISR_FECAP_Msk (0xFFFFU << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */
Kojto 122:f9eeca106725 5776 #define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */
Kojto 122:f9eeca106725 5777
Kojto 122:f9eeca106725 5778 /******************* Bit definition for CRS_ICR register *********************/
Kojto 122:f9eeca106725 5779 #define CRS_ICR_SYNCOKC_Pos (0U)
Kojto 122:f9eeca106725 5780 #define CRS_ICR_SYNCOKC_Msk (0x1U << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 5781 #define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */
Kojto 122:f9eeca106725 5782 #define CRS_ICR_SYNCWARNC_Pos (1U)
Kojto 122:f9eeca106725 5783 #define CRS_ICR_SYNCWARNC_Msk (0x1U << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 5784 #define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */
Kojto 122:f9eeca106725 5785 #define CRS_ICR_ERRC_Pos (2U)
Kojto 122:f9eeca106725 5786 #define CRS_ICR_ERRC_Msk (0x1U << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 5787 #define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */
Kojto 122:f9eeca106725 5788 #define CRS_ICR_ESYNCC_Pos (3U)
Kojto 122:f9eeca106725 5789 #define CRS_ICR_ESYNCC_Msk (0x1U << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 5790 #define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */
Kojto 122:f9eeca106725 5791
Kojto 122:f9eeca106725 5792 /******************************************************************************/
Kojto 122:f9eeca106725 5793 /* */
Kojto 122:f9eeca106725 5794 /* Digital to Analog Converter */
Kojto 122:f9eeca106725 5795 /* */
Kojto 122:f9eeca106725 5796 /******************************************************************************/
Kojto 122:f9eeca106725 5797 /******************** Bit definition for DAC_CR register ********************/
Kojto 122:f9eeca106725 5798 #define DAC_CR_EN1_Pos (0U)
Kojto 122:f9eeca106725 5799 #define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 5800 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
Kojto 122:f9eeca106725 5801 #define DAC_CR_TEN1_Pos (2U)
Kojto 122:f9eeca106725 5802 #define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 5803 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
Kojto 122:f9eeca106725 5804
Kojto 122:f9eeca106725 5805 #define DAC_CR_TSEL1_Pos (3U)
Kojto 122:f9eeca106725 5806 #define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
Kojto 122:f9eeca106725 5807 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
Kojto 122:f9eeca106725 5808 #define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 5809 #define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 5810 #define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 5811
Kojto 122:f9eeca106725 5812 #define DAC_CR_WAVE1_Pos (6U)
Kojto 122:f9eeca106725 5813 #define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
Kojto 122:f9eeca106725 5814 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
Kojto 122:f9eeca106725 5815 #define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 5816 #define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 5817
Kojto 122:f9eeca106725 5818 #define DAC_CR_MAMP1_Pos (8U)
Kojto 122:f9eeca106725 5819 #define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 5820 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
Kojto 122:f9eeca106725 5821 #define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 5822 #define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 5823 #define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 5824 #define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 5825
Kojto 122:f9eeca106725 5826 #define DAC_CR_DMAEN1_Pos (12U)
Kojto 122:f9eeca106725 5827 #define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 5828 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
Kojto 122:f9eeca106725 5829 #define DAC_CR_DMAUDRIE1_Pos (13U)
Kojto 122:f9eeca106725 5830 #define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 5831 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel 1 DMA underrun interrupt enable >*/
Kojto 122:f9eeca106725 5832 #define DAC_CR_CEN1_Pos (14U)
Kojto 122:f9eeca106725 5833 #define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 5834 #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!<DAC channel 1 calibration enable >*/
Kojto 122:f9eeca106725 5835
Kojto 122:f9eeca106725 5836 #define DAC_CR_EN2_Pos (16U)
Kojto 122:f9eeca106725 5837 #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 5838 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
Kojto 122:f9eeca106725 5839 #define DAC_CR_TEN2_Pos (18U)
Kojto 122:f9eeca106725 5840 #define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 5841 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
Kojto 122:f9eeca106725 5842
Kojto 122:f9eeca106725 5843 #define DAC_CR_TSEL2_Pos (19U)
Kojto 122:f9eeca106725 5844 #define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
Kojto 122:f9eeca106725 5845 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
Kojto 122:f9eeca106725 5846 #define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 5847 #define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 5848 #define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 5849
Kojto 122:f9eeca106725 5850 #define DAC_CR_WAVE2_Pos (22U)
Kojto 122:f9eeca106725 5851 #define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
Kojto 122:f9eeca106725 5852 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
Kojto 122:f9eeca106725 5853 #define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 5854 #define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 5855
Kojto 122:f9eeca106725 5856 #define DAC_CR_MAMP2_Pos (24U)
Kojto 122:f9eeca106725 5857 #define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
Kojto 122:f9eeca106725 5858 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
Kojto 122:f9eeca106725 5859 #define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 5860 #define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 5861 #define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 5862 #define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 5863
Kojto 122:f9eeca106725 5864 #define DAC_CR_DMAEN2_Pos (28U)
Kojto 122:f9eeca106725 5865 #define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 5866 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
Kojto 122:f9eeca106725 5867 #define DAC_CR_DMAUDRIE2_Pos (29U)
Kojto 122:f9eeca106725 5868 #define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 5869 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable >*/
Kojto 122:f9eeca106725 5870 #define DAC_CR_CEN2_Pos (30U)
Kojto 122:f9eeca106725 5871 #define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 5872 #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!<DAC channel2 calibration enable >*/
Kojto 122:f9eeca106725 5873
Kojto 122:f9eeca106725 5874 /***************** Bit definition for DAC_SWTRIGR register ******************/
Kojto 122:f9eeca106725 5875 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
Kojto 122:f9eeca106725 5876 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 5877 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
Kojto 122:f9eeca106725 5878 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
Kojto 122:f9eeca106725 5879 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 5880 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
Kojto 122:f9eeca106725 5881
Kojto 122:f9eeca106725 5882 /***************** Bit definition for DAC_DHR12R1 register ******************/
Kojto 122:f9eeca106725 5883 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
Kojto 122:f9eeca106725 5884 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
Kojto 122:f9eeca106725 5885 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
Kojto 122:f9eeca106725 5886
Kojto 122:f9eeca106725 5887 /***************** Bit definition for DAC_DHR12L1 register ******************/
Kojto 122:f9eeca106725 5888 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
Kojto 122:f9eeca106725 5889 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
Kojto 122:f9eeca106725 5890 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
Kojto 122:f9eeca106725 5891
Kojto 122:f9eeca106725 5892 /****************** Bit definition for DAC_DHR8R1 register ******************/
Kojto 122:f9eeca106725 5893 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
Kojto 122:f9eeca106725 5894 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 5895 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
Kojto 122:f9eeca106725 5896
Kojto 122:f9eeca106725 5897 /***************** Bit definition for DAC_DHR12R2 register ******************/
Kojto 122:f9eeca106725 5898 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
Kojto 122:f9eeca106725 5899 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
Kojto 122:f9eeca106725 5900 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
Kojto 122:f9eeca106725 5901
Kojto 122:f9eeca106725 5902 /***************** Bit definition for DAC_DHR12L2 register ******************/
Kojto 122:f9eeca106725 5903 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
Kojto 122:f9eeca106725 5904 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
Kojto 122:f9eeca106725 5905 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
Kojto 122:f9eeca106725 5906
Kojto 122:f9eeca106725 5907 /****************** Bit definition for DAC_DHR8R2 register ******************/
Kojto 122:f9eeca106725 5908 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
Kojto 122:f9eeca106725 5909 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 5910 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
Kojto 122:f9eeca106725 5911
Kojto 122:f9eeca106725 5912 /***************** Bit definition for DAC_DHR12RD register ******************/
Kojto 122:f9eeca106725 5913 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
Kojto 122:f9eeca106725 5914 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
Kojto 122:f9eeca106725 5915 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
Kojto 122:f9eeca106725 5916 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
Kojto 122:f9eeca106725 5917 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
Kojto 122:f9eeca106725 5918 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
Kojto 122:f9eeca106725 5919
Kojto 122:f9eeca106725 5920 /***************** Bit definition for DAC_DHR12LD register ******************/
Kojto 122:f9eeca106725 5921 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
Kojto 122:f9eeca106725 5922 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
Kojto 122:f9eeca106725 5923 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
Kojto 122:f9eeca106725 5924 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
Kojto 122:f9eeca106725 5925 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
Kojto 122:f9eeca106725 5926 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
Kojto 122:f9eeca106725 5927
Kojto 122:f9eeca106725 5928 /****************** Bit definition for DAC_DHR8RD register ******************/
Kojto 122:f9eeca106725 5929 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
Kojto 122:f9eeca106725 5930 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 5931 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
Kojto 122:f9eeca106725 5932 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
Kojto 122:f9eeca106725 5933 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 5934 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
Kojto 122:f9eeca106725 5935
Kojto 122:f9eeca106725 5936 /******************* Bit definition for DAC_DOR1 register *******************/
Kojto 122:f9eeca106725 5937 #define DAC_DOR1_DACC1DOR_Pos (0U)
Kojto 122:f9eeca106725 5938 #define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
Kojto 122:f9eeca106725 5939 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
Kojto 122:f9eeca106725 5940
Kojto 122:f9eeca106725 5941 /******************* Bit definition for DAC_DOR2 register *******************/
Kojto 122:f9eeca106725 5942 #define DAC_DOR2_DACC2DOR_Pos (0U)
Kojto 122:f9eeca106725 5943 #define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
Kojto 122:f9eeca106725 5944 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
Kojto 122:f9eeca106725 5945
Kojto 122:f9eeca106725 5946 /******************** Bit definition for DAC_SR register ********************/
Kojto 122:f9eeca106725 5947 #define DAC_SR_DMAUDR1_Pos (13U)
Kojto 122:f9eeca106725 5948 #define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 5949 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
Kojto 122:f9eeca106725 5950 #define DAC_SR_CAL_FLAG1_Pos (14U)
Kojto 122:f9eeca106725 5951 #define DAC_SR_CAL_FLAG1_Msk (0x1U << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 5952 #define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!<DAC channel1 calibration offset status */
Kojto 122:f9eeca106725 5953 #define DAC_SR_BWST1_Pos (15U)
Kojto 122:f9eeca106725 5954 #define DAC_SR_BWST1_Msk (0x4001U << DAC_SR_BWST1_Pos) /*!< 0x20008000 */
Kojto 122:f9eeca106725 5955 #define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */
Kojto 122:f9eeca106725 5956
Kojto 122:f9eeca106725 5957 #define DAC_SR_DMAUDR2_Pos (29U)
Kojto 122:f9eeca106725 5958 #define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 5959 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
Kojto 122:f9eeca106725 5960 #define DAC_SR_CAL_FLAG2_Pos (30U)
Kojto 122:f9eeca106725 5961 #define DAC_SR_CAL_FLAG2_Msk (0x1U << DAC_SR_CAL_FLAG2_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 5962 #define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk /*!<DAC channel2 calibration offset status */
Kojto 122:f9eeca106725 5963 #define DAC_SR_BWST2_Pos (31U)
Kojto 122:f9eeca106725 5964 #define DAC_SR_BWST2_Msk (0x1U << DAC_SR_BWST2_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 5965 #define DAC_SR_BWST2 DAC_SR_BWST2_Msk /*!<DAC channel2 busy writing sample time flag */
Kojto 122:f9eeca106725 5966
Kojto 122:f9eeca106725 5967 /******************* Bit definition for DAC_CCR register ********************/
Kojto 122:f9eeca106725 5968 #define DAC_CCR_OTRIM1_Pos (0U)
Kojto 122:f9eeca106725 5969 #define DAC_CCR_OTRIM1_Msk (0x1FU << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */
Kojto 122:f9eeca106725 5970 #define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!<DAC channel1 offset trimming value */
Kojto 122:f9eeca106725 5971 #define DAC_CCR_OTRIM2_Pos (16U)
Kojto 122:f9eeca106725 5972 #define DAC_CCR_OTRIM2_Msk (0x1FU << DAC_CCR_OTRIM2_Pos) /*!< 0x001F0000 */
Kojto 122:f9eeca106725 5973 #define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk /*!<DAC channel2 offset trimming value */
Kojto 122:f9eeca106725 5974
Kojto 122:f9eeca106725 5975 /******************* Bit definition for DAC_MCR register *******************/
Kojto 122:f9eeca106725 5976 #define DAC_MCR_MODE1_Pos (0U)
Kojto 122:f9eeca106725 5977 #define DAC_MCR_MODE1_Msk (0x7U << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */
Kojto 122:f9eeca106725 5978 #define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!<MODE1[2:0] (DAC channel1 mode) */
Kojto 122:f9eeca106725 5979 #define DAC_MCR_MODE1_0 (0x1U << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 5980 #define DAC_MCR_MODE1_1 (0x2U << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 5981 #define DAC_MCR_MODE1_2 (0x4U << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 5982
Kojto 122:f9eeca106725 5983 #define DAC_MCR_MODE2_Pos (16U)
Kojto 122:f9eeca106725 5984 #define DAC_MCR_MODE2_Msk (0x7U << DAC_MCR_MODE2_Pos) /*!< 0x00070000 */
Kojto 122:f9eeca106725 5985 #define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk /*!<MODE2[2:0] (DAC channel2 mode) */
Kojto 122:f9eeca106725 5986 #define DAC_MCR_MODE2_0 (0x1U << DAC_MCR_MODE2_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 5987 #define DAC_MCR_MODE2_1 (0x2U << DAC_MCR_MODE2_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 5988 #define DAC_MCR_MODE2_2 (0x4U << DAC_MCR_MODE2_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 5989
Kojto 122:f9eeca106725 5990 /****************** Bit definition for DAC_SHSR1 register ******************/
Kojto 122:f9eeca106725 5991 #define DAC_SHSR1_TSAMPLE1_Pos (0U)
Kojto 122:f9eeca106725 5992 #define DAC_SHSR1_TSAMPLE1_Msk (0x3FFU << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */
Kojto 122:f9eeca106725 5993 #define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!<DAC channel1 sample time */
Kojto 122:f9eeca106725 5994
Kojto 122:f9eeca106725 5995 /****************** Bit definition for DAC_SHSR2 register ******************/
Kojto 122:f9eeca106725 5996 #define DAC_SHSR2_TSAMPLE2_Pos (0U)
Kojto 122:f9eeca106725 5997 #define DAC_SHSR2_TSAMPLE2_Msk (0x3FFU << DAC_SHSR2_TSAMPLE2_Pos) /*!< 0x000003FF */
Kojto 122:f9eeca106725 5998 #define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk /*!<DAC channel2 sample time */
Kojto 122:f9eeca106725 5999
Kojto 122:f9eeca106725 6000 /****************** Bit definition for DAC_SHHR register ******************/
Kojto 122:f9eeca106725 6001 #define DAC_SHHR_THOLD1_Pos (0U)
Kojto 122:f9eeca106725 6002 #define DAC_SHHR_THOLD1_Msk (0x3FFU << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */
Kojto 122:f9eeca106725 6003 #define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!<DAC channel1 hold time */
Kojto 122:f9eeca106725 6004 #define DAC_SHHR_THOLD2_Pos (16U)
Kojto 122:f9eeca106725 6005 #define DAC_SHHR_THOLD2_Msk (0x3FFU << DAC_SHHR_THOLD2_Pos) /*!< 0x03FF0000 */
Kojto 122:f9eeca106725 6006 #define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk /*!<DAC channel2 hold time */
Kojto 122:f9eeca106725 6007
Kojto 122:f9eeca106725 6008 /****************** Bit definition for DAC_SHRR register ******************/
Kojto 122:f9eeca106725 6009 #define DAC_SHRR_TREFRESH1_Pos (0U)
Kojto 122:f9eeca106725 6010 #define DAC_SHRR_TREFRESH1_Msk (0xFFU << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 6011 #define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!<DAC channel1 refresh time */
Kojto 122:f9eeca106725 6012 #define DAC_SHRR_TREFRESH2_Pos (16U)
Kojto 122:f9eeca106725 6013 #define DAC_SHRR_TREFRESH2_Msk (0xFFU << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 6014 #define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!<DAC channel2 refresh time */
Kojto 122:f9eeca106725 6015
Kojto 122:f9eeca106725 6016 /******************************************************************************/
Kojto 122:f9eeca106725 6017 /* */
Kojto 122:f9eeca106725 6018 /* DMA Controller (DMA) */
Kojto 122:f9eeca106725 6019 /* */
Kojto 122:f9eeca106725 6020 /******************************************************************************/
Kojto 122:f9eeca106725 6021
Kojto 122:f9eeca106725 6022 /******************* Bit definition for DMA_ISR register ********************/
Kojto 122:f9eeca106725 6023 #define DMA_ISR_GIF1_Pos (0U)
Kojto 122:f9eeca106725 6024 #define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 6025 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
Kojto 122:f9eeca106725 6026 #define DMA_ISR_TCIF1_Pos (1U)
Kojto 122:f9eeca106725 6027 #define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 6028 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
Kojto 122:f9eeca106725 6029 #define DMA_ISR_HTIF1_Pos (2U)
Kojto 122:f9eeca106725 6030 #define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 6031 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
Kojto 122:f9eeca106725 6032 #define DMA_ISR_TEIF1_Pos (3U)
Kojto 122:f9eeca106725 6033 #define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 6034 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
Kojto 122:f9eeca106725 6035 #define DMA_ISR_GIF2_Pos (4U)
Kojto 122:f9eeca106725 6036 #define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 6037 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
Kojto 122:f9eeca106725 6038 #define DMA_ISR_TCIF2_Pos (5U)
Kojto 122:f9eeca106725 6039 #define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 6040 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
Kojto 122:f9eeca106725 6041 #define DMA_ISR_HTIF2_Pos (6U)
Kojto 122:f9eeca106725 6042 #define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 6043 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
Kojto 122:f9eeca106725 6044 #define DMA_ISR_TEIF2_Pos (7U)
Kojto 122:f9eeca106725 6045 #define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 6046 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
Kojto 122:f9eeca106725 6047 #define DMA_ISR_GIF3_Pos (8U)
Kojto 122:f9eeca106725 6048 #define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 6049 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
Kojto 122:f9eeca106725 6050 #define DMA_ISR_TCIF3_Pos (9U)
Kojto 122:f9eeca106725 6051 #define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 6052 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
Kojto 122:f9eeca106725 6053 #define DMA_ISR_HTIF3_Pos (10U)
Kojto 122:f9eeca106725 6054 #define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 6055 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
Kojto 122:f9eeca106725 6056 #define DMA_ISR_TEIF3_Pos (11U)
Kojto 122:f9eeca106725 6057 #define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 6058 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
Kojto 122:f9eeca106725 6059 #define DMA_ISR_GIF4_Pos (12U)
Kojto 122:f9eeca106725 6060 #define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 6061 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
Kojto 122:f9eeca106725 6062 #define DMA_ISR_TCIF4_Pos (13U)
Kojto 122:f9eeca106725 6063 #define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 6064 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
Kojto 122:f9eeca106725 6065 #define DMA_ISR_HTIF4_Pos (14U)
Kojto 122:f9eeca106725 6066 #define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 6067 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
Kojto 122:f9eeca106725 6068 #define DMA_ISR_TEIF4_Pos (15U)
Kojto 122:f9eeca106725 6069 #define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 6070 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
Kojto 122:f9eeca106725 6071 #define DMA_ISR_GIF5_Pos (16U)
Kojto 122:f9eeca106725 6072 #define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 6073 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
Kojto 122:f9eeca106725 6074 #define DMA_ISR_TCIF5_Pos (17U)
Kojto 122:f9eeca106725 6075 #define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 6076 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
Kojto 122:f9eeca106725 6077 #define DMA_ISR_HTIF5_Pos (18U)
Kojto 122:f9eeca106725 6078 #define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 6079 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
Kojto 122:f9eeca106725 6080 #define DMA_ISR_TEIF5_Pos (19U)
Kojto 122:f9eeca106725 6081 #define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 6082 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
Kojto 122:f9eeca106725 6083 #define DMA_ISR_GIF6_Pos (20U)
Kojto 122:f9eeca106725 6084 #define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 6085 #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
Kojto 122:f9eeca106725 6086 #define DMA_ISR_TCIF6_Pos (21U)
Kojto 122:f9eeca106725 6087 #define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 6088 #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
Kojto 122:f9eeca106725 6089 #define DMA_ISR_HTIF6_Pos (22U)
Kojto 122:f9eeca106725 6090 #define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 6091 #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
Kojto 122:f9eeca106725 6092 #define DMA_ISR_TEIF6_Pos (23U)
Kojto 122:f9eeca106725 6093 #define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 6094 #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
Kojto 122:f9eeca106725 6095 #define DMA_ISR_GIF7_Pos (24U)
Kojto 122:f9eeca106725 6096 #define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 6097 #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
Kojto 122:f9eeca106725 6098 #define DMA_ISR_TCIF7_Pos (25U)
Kojto 122:f9eeca106725 6099 #define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 6100 #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
Kojto 122:f9eeca106725 6101 #define DMA_ISR_HTIF7_Pos (26U)
Kojto 122:f9eeca106725 6102 #define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 6103 #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
Kojto 122:f9eeca106725 6104 #define DMA_ISR_TEIF7_Pos (27U)
Kojto 122:f9eeca106725 6105 #define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 6106 #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
Kojto 122:f9eeca106725 6107
Kojto 122:f9eeca106725 6108 /******************* Bit definition for DMA_IFCR register *******************/
Kojto 122:f9eeca106725 6109 #define DMA_IFCR_CGIF1_Pos (0U)
Kojto 122:f9eeca106725 6110 #define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 6111 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */
Kojto 122:f9eeca106725 6112 #define DMA_IFCR_CTCIF1_Pos (1U)
Kojto 122:f9eeca106725 6113 #define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 6114 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
Kojto 122:f9eeca106725 6115 #define DMA_IFCR_CHTIF1_Pos (2U)
Kojto 122:f9eeca106725 6116 #define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 6117 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
Kojto 122:f9eeca106725 6118 #define DMA_IFCR_CTEIF1_Pos (3U)
Kojto 122:f9eeca106725 6119 #define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 6120 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
Kojto 122:f9eeca106725 6121 #define DMA_IFCR_CGIF2_Pos (4U)
Kojto 122:f9eeca106725 6122 #define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 6123 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
Kojto 122:f9eeca106725 6124 #define DMA_IFCR_CTCIF2_Pos (5U)
Kojto 122:f9eeca106725 6125 #define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 6126 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
Kojto 122:f9eeca106725 6127 #define DMA_IFCR_CHTIF2_Pos (6U)
Kojto 122:f9eeca106725 6128 #define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 6129 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
Kojto 122:f9eeca106725 6130 #define DMA_IFCR_CTEIF2_Pos (7U)
Kojto 122:f9eeca106725 6131 #define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 6132 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
Kojto 122:f9eeca106725 6133 #define DMA_IFCR_CGIF3_Pos (8U)
Kojto 122:f9eeca106725 6134 #define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 6135 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
Kojto 122:f9eeca106725 6136 #define DMA_IFCR_CTCIF3_Pos (9U)
Kojto 122:f9eeca106725 6137 #define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 6138 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
Kojto 122:f9eeca106725 6139 #define DMA_IFCR_CHTIF3_Pos (10U)
Kojto 122:f9eeca106725 6140 #define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 6141 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
Kojto 122:f9eeca106725 6142 #define DMA_IFCR_CTEIF3_Pos (11U)
Kojto 122:f9eeca106725 6143 #define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 6144 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
Kojto 122:f9eeca106725 6145 #define DMA_IFCR_CGIF4_Pos (12U)
Kojto 122:f9eeca106725 6146 #define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 6147 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
Kojto 122:f9eeca106725 6148 #define DMA_IFCR_CTCIF4_Pos (13U)
Kojto 122:f9eeca106725 6149 #define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 6150 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
Kojto 122:f9eeca106725 6151 #define DMA_IFCR_CHTIF4_Pos (14U)
Kojto 122:f9eeca106725 6152 #define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 6153 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
Kojto 122:f9eeca106725 6154 #define DMA_IFCR_CTEIF4_Pos (15U)
Kojto 122:f9eeca106725 6155 #define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 6156 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
Kojto 122:f9eeca106725 6157 #define DMA_IFCR_CGIF5_Pos (16U)
Kojto 122:f9eeca106725 6158 #define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 6159 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
Kojto 122:f9eeca106725 6160 #define DMA_IFCR_CTCIF5_Pos (17U)
Kojto 122:f9eeca106725 6161 #define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 6162 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
Kojto 122:f9eeca106725 6163 #define DMA_IFCR_CHTIF5_Pos (18U)
Kojto 122:f9eeca106725 6164 #define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 6165 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
Kojto 122:f9eeca106725 6166 #define DMA_IFCR_CTEIF5_Pos (19U)
Kojto 122:f9eeca106725 6167 #define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 6168 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
Kojto 122:f9eeca106725 6169 #define DMA_IFCR_CGIF6_Pos (20U)
Kojto 122:f9eeca106725 6170 #define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 6171 #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
Kojto 122:f9eeca106725 6172 #define DMA_IFCR_CTCIF6_Pos (21U)
Kojto 122:f9eeca106725 6173 #define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 6174 #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
Kojto 122:f9eeca106725 6175 #define DMA_IFCR_CHTIF6_Pos (22U)
Kojto 122:f9eeca106725 6176 #define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 6177 #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
Kojto 122:f9eeca106725 6178 #define DMA_IFCR_CTEIF6_Pos (23U)
Kojto 122:f9eeca106725 6179 #define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 6180 #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
Kojto 122:f9eeca106725 6181 #define DMA_IFCR_CGIF7_Pos (24U)
Kojto 122:f9eeca106725 6182 #define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 6183 #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
Kojto 122:f9eeca106725 6184 #define DMA_IFCR_CTCIF7_Pos (25U)
Kojto 122:f9eeca106725 6185 #define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 6186 #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
Kojto 122:f9eeca106725 6187 #define DMA_IFCR_CHTIF7_Pos (26U)
Kojto 122:f9eeca106725 6188 #define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 6189 #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
Kojto 122:f9eeca106725 6190 #define DMA_IFCR_CTEIF7_Pos (27U)
Kojto 122:f9eeca106725 6191 #define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 6192 #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
Kojto 122:f9eeca106725 6193
Kojto 122:f9eeca106725 6194 /******************* Bit definition for DMA_CCR register ********************/
Kojto 122:f9eeca106725 6195 #define DMA_CCR_EN_Pos (0U)
Kojto 122:f9eeca106725 6196 #define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 6197 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
Kojto 122:f9eeca106725 6198 #define DMA_CCR_TCIE_Pos (1U)
Kojto 122:f9eeca106725 6199 #define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 6200 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
Kojto 122:f9eeca106725 6201 #define DMA_CCR_HTIE_Pos (2U)
Kojto 122:f9eeca106725 6202 #define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 6203 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
Kojto 122:f9eeca106725 6204 #define DMA_CCR_TEIE_Pos (3U)
Kojto 122:f9eeca106725 6205 #define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 6206 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
Kojto 122:f9eeca106725 6207 #define DMA_CCR_DIR_Pos (4U)
Kojto 122:f9eeca106725 6208 #define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 6209 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
Kojto 122:f9eeca106725 6210 #define DMA_CCR_CIRC_Pos (5U)
Kojto 122:f9eeca106725 6211 #define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 6212 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
Kojto 122:f9eeca106725 6213 #define DMA_CCR_PINC_Pos (6U)
Kojto 122:f9eeca106725 6214 #define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 6215 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
Kojto 122:f9eeca106725 6216 #define DMA_CCR_MINC_Pos (7U)
Kojto 122:f9eeca106725 6217 #define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 6218 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
Kojto 122:f9eeca106725 6219
Kojto 122:f9eeca106725 6220 #define DMA_CCR_PSIZE_Pos (8U)
Kojto 122:f9eeca106725 6221 #define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 6222 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
Kojto 122:f9eeca106725 6223 #define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 6224 #define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 6225
Kojto 122:f9eeca106725 6226 #define DMA_CCR_MSIZE_Pos (10U)
Kojto 122:f9eeca106725 6227 #define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
Kojto 122:f9eeca106725 6228 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
Kojto 122:f9eeca106725 6229 #define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 6230 #define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 6231
Kojto 122:f9eeca106725 6232 #define DMA_CCR_PL_Pos (12U)
Kojto 122:f9eeca106725 6233 #define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
Kojto 122:f9eeca106725 6234 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
Kojto 122:f9eeca106725 6235 #define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 6236 #define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 6237
Kojto 122:f9eeca106725 6238 #define DMA_CCR_MEM2MEM_Pos (14U)
Kojto 122:f9eeca106725 6239 #define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 6240 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
Kojto 122:f9eeca106725 6241
Kojto 122:f9eeca106725 6242 /****************** Bit definition for DMA_CNDTR register *******************/
Kojto 122:f9eeca106725 6243 #define DMA_CNDTR_NDT_Pos (0U)
Kojto 122:f9eeca106725 6244 #define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 6245 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
Kojto 122:f9eeca106725 6246
Kojto 122:f9eeca106725 6247 /****************** Bit definition for DMA_CPAR register ********************/
Kojto 122:f9eeca106725 6248 #define DMA_CPAR_PA_Pos (0U)
Kojto 122:f9eeca106725 6249 #define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 6250 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
Kojto 122:f9eeca106725 6251
Kojto 122:f9eeca106725 6252 /****************** Bit definition for DMA_CMAR register ********************/
Kojto 122:f9eeca106725 6253 #define DMA_CMAR_MA_Pos (0U)
Kojto 122:f9eeca106725 6254 #define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 6255 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
Kojto 122:f9eeca106725 6256
Kojto 122:f9eeca106725 6257
Kojto 122:f9eeca106725 6258 /******************* Bit definition for DMA_CSELR register *******************/
Kojto 122:f9eeca106725 6259 #define DMA_CSELR_C1S_Pos (0U)
Kojto 122:f9eeca106725 6260 #define DMA_CSELR_C1S_Msk (0xFU << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 6261 #define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */
Kojto 122:f9eeca106725 6262 #define DMA_CSELR_C2S_Pos (4U)
Kojto 122:f9eeca106725 6263 #define DMA_CSELR_C2S_Msk (0xFU << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */
Kojto 122:f9eeca106725 6264 #define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */
Kojto 122:f9eeca106725 6265 #define DMA_CSELR_C3S_Pos (8U)
Kojto 122:f9eeca106725 6266 #define DMA_CSELR_C3S_Msk (0xFU << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 6267 #define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */
Kojto 122:f9eeca106725 6268 #define DMA_CSELR_C4S_Pos (12U)
Kojto 122:f9eeca106725 6269 #define DMA_CSELR_C4S_Msk (0xFU << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */
Kojto 122:f9eeca106725 6270 #define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */
Kojto 122:f9eeca106725 6271 #define DMA_CSELR_C5S_Pos (16U)
Kojto 122:f9eeca106725 6272 #define DMA_CSELR_C5S_Msk (0xFU << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */
Kojto 122:f9eeca106725 6273 #define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */
Kojto 122:f9eeca106725 6274 #define DMA_CSELR_C6S_Pos (20U)
Kojto 122:f9eeca106725 6275 #define DMA_CSELR_C6S_Msk (0xFU << DMA_CSELR_C6S_Pos) /*!< 0x00F00000 */
Kojto 122:f9eeca106725 6276 #define DMA_CSELR_C6S DMA_CSELR_C6S_Msk /*!< Channel 6 Selection */
Kojto 122:f9eeca106725 6277 #define DMA_CSELR_C7S_Pos (24U)
Kojto 122:f9eeca106725 6278 #define DMA_CSELR_C7S_Msk (0xFU << DMA_CSELR_C7S_Pos) /*!< 0x0F000000 */
Kojto 122:f9eeca106725 6279 #define DMA_CSELR_C7S DMA_CSELR_C7S_Msk /*!< Channel 7 Selection */
Kojto 122:f9eeca106725 6280
Kojto 122:f9eeca106725 6281 /******************************************************************************/
Kojto 122:f9eeca106725 6282 /* */
Kojto 122:f9eeca106725 6283 /* External Interrupt/Event Controller */
Kojto 122:f9eeca106725 6284 /* */
Kojto 122:f9eeca106725 6285 /******************************************************************************/
Kojto 122:f9eeca106725 6286 /******************* Bit definition for EXTI_IMR1 register ******************/
Kojto 122:f9eeca106725 6287 #define EXTI_IMR1_IM0_Pos (0U)
Kojto 122:f9eeca106725 6288 #define EXTI_IMR1_IM0_Msk (0x1U << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 6289 #define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */
Kojto 122:f9eeca106725 6290 #define EXTI_IMR1_IM1_Pos (1U)
Kojto 122:f9eeca106725 6291 #define EXTI_IMR1_IM1_Msk (0x1U << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 6292 #define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */
Kojto 122:f9eeca106725 6293 #define EXTI_IMR1_IM2_Pos (2U)
Kojto 122:f9eeca106725 6294 #define EXTI_IMR1_IM2_Msk (0x1U << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 6295 #define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */
Kojto 122:f9eeca106725 6296 #define EXTI_IMR1_IM3_Pos (3U)
Kojto 122:f9eeca106725 6297 #define EXTI_IMR1_IM3_Msk (0x1U << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 6298 #define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */
Kojto 122:f9eeca106725 6299 #define EXTI_IMR1_IM4_Pos (4U)
Kojto 122:f9eeca106725 6300 #define EXTI_IMR1_IM4_Msk (0x1U << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 6301 #define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */
Kojto 122:f9eeca106725 6302 #define EXTI_IMR1_IM5_Pos (5U)
Kojto 122:f9eeca106725 6303 #define EXTI_IMR1_IM5_Msk (0x1U << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 6304 #define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */
Kojto 122:f9eeca106725 6305 #define EXTI_IMR1_IM6_Pos (6U)
Kojto 122:f9eeca106725 6306 #define EXTI_IMR1_IM6_Msk (0x1U << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 6307 #define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */
Kojto 122:f9eeca106725 6308 #define EXTI_IMR1_IM7_Pos (7U)
Kojto 122:f9eeca106725 6309 #define EXTI_IMR1_IM7_Msk (0x1U << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 6310 #define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */
Kojto 122:f9eeca106725 6311 #define EXTI_IMR1_IM8_Pos (8U)
Kojto 122:f9eeca106725 6312 #define EXTI_IMR1_IM8_Msk (0x1U << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 6313 #define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */
Kojto 122:f9eeca106725 6314 #define EXTI_IMR1_IM9_Pos (9U)
Kojto 122:f9eeca106725 6315 #define EXTI_IMR1_IM9_Msk (0x1U << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 6316 #define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */
Kojto 122:f9eeca106725 6317 #define EXTI_IMR1_IM10_Pos (10U)
Kojto 122:f9eeca106725 6318 #define EXTI_IMR1_IM10_Msk (0x1U << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 6319 #define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */
Kojto 122:f9eeca106725 6320 #define EXTI_IMR1_IM11_Pos (11U)
Kojto 122:f9eeca106725 6321 #define EXTI_IMR1_IM11_Msk (0x1U << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 6322 #define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */
Kojto 122:f9eeca106725 6323 #define EXTI_IMR1_IM12_Pos (12U)
Kojto 122:f9eeca106725 6324 #define EXTI_IMR1_IM12_Msk (0x1U << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 6325 #define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */
Kojto 122:f9eeca106725 6326 #define EXTI_IMR1_IM13_Pos (13U)
Kojto 122:f9eeca106725 6327 #define EXTI_IMR1_IM13_Msk (0x1U << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 6328 #define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */
Kojto 122:f9eeca106725 6329 #define EXTI_IMR1_IM14_Pos (14U)
Kojto 122:f9eeca106725 6330 #define EXTI_IMR1_IM14_Msk (0x1U << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 6331 #define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */
Kojto 122:f9eeca106725 6332 #define EXTI_IMR1_IM15_Pos (15U)
Kojto 122:f9eeca106725 6333 #define EXTI_IMR1_IM15_Msk (0x1U << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 6334 #define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */
Kojto 122:f9eeca106725 6335 #define EXTI_IMR1_IM16_Pos (16U)
Kojto 122:f9eeca106725 6336 #define EXTI_IMR1_IM16_Msk (0x1U << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 6337 #define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */
Kojto 122:f9eeca106725 6338 #define EXTI_IMR1_IM17_Pos (17U)
Kojto 122:f9eeca106725 6339 #define EXTI_IMR1_IM17_Msk (0x1U << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 6340 #define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */
Kojto 122:f9eeca106725 6341 #define EXTI_IMR1_IM18_Pos (18U)
Kojto 122:f9eeca106725 6342 #define EXTI_IMR1_IM18_Msk (0x1U << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 6343 #define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */
Kojto 122:f9eeca106725 6344 #define EXTI_IMR1_IM19_Pos (19U)
Kojto 122:f9eeca106725 6345 #define EXTI_IMR1_IM19_Msk (0x1U << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 6346 #define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */
Kojto 122:f9eeca106725 6347 #define EXTI_IMR1_IM20_Pos (20U)
Kojto 122:f9eeca106725 6348 #define EXTI_IMR1_IM20_Msk (0x1U << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 6349 #define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */
Kojto 122:f9eeca106725 6350 #define EXTI_IMR1_IM21_Pos (21U)
Kojto 122:f9eeca106725 6351 #define EXTI_IMR1_IM21_Msk (0x1U << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 6352 #define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */
Kojto 122:f9eeca106725 6353 #define EXTI_IMR1_IM22_Pos (22U)
Kojto 122:f9eeca106725 6354 #define EXTI_IMR1_IM22_Msk (0x1U << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 6355 #define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */
Kojto 122:f9eeca106725 6356 #define EXTI_IMR1_IM23_Pos (23U)
Kojto 122:f9eeca106725 6357 #define EXTI_IMR1_IM23_Msk (0x1U << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 6358 #define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */
Kojto 122:f9eeca106725 6359 #define EXTI_IMR1_IM24_Pos (24U)
Kojto 122:f9eeca106725 6360 #define EXTI_IMR1_IM24_Msk (0x1U << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 6361 #define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */
Kojto 122:f9eeca106725 6362 #define EXTI_IMR1_IM25_Pos (25U)
Kojto 122:f9eeca106725 6363 #define EXTI_IMR1_IM25_Msk (0x1U << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 6364 #define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */
Kojto 122:f9eeca106725 6365 #define EXTI_IMR1_IM26_Pos (26U)
Kojto 122:f9eeca106725 6366 #define EXTI_IMR1_IM26_Msk (0x1U << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 6367 #define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */
Kojto 122:f9eeca106725 6368 #define EXTI_IMR1_IM27_Pos (27U)
Kojto 122:f9eeca106725 6369 #define EXTI_IMR1_IM27_Msk (0x1U << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 6370 #define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< Interrupt Mask on line 27 */
Kojto 122:f9eeca106725 6371 #define EXTI_IMR1_IM28_Pos (28U)
Kojto 122:f9eeca106725 6372 #define EXTI_IMR1_IM28_Msk (0x1U << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 6373 #define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */
Kojto 122:f9eeca106725 6374 #define EXTI_IMR1_IM31_Pos (31U)
Kojto 122:f9eeca106725 6375 #define EXTI_IMR1_IM31_Msk (0x1U << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 6376 #define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */
Kojto 122:f9eeca106725 6377 #define EXTI_IMR1_IM_Pos (0U)
Kojto 122:f9eeca106725 6378 #define EXTI_IMR1_IM_Msk (0x9FFFFFFFU << EXTI_IMR1_IM_Pos) /*!< 0x9FFFFFFF */
Kojto 122:f9eeca106725 6379 #define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */
Kojto 122:f9eeca106725 6380
Kojto 122:f9eeca106725 6381 /******************* Bit definition for EXTI_EMR1 register ******************/
Kojto 122:f9eeca106725 6382 #define EXTI_EMR1_EM0_Pos (0U)
Kojto 122:f9eeca106725 6383 #define EXTI_EMR1_EM0_Msk (0x1U << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 6384 #define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */
Kojto 122:f9eeca106725 6385 #define EXTI_EMR1_EM1_Pos (1U)
Kojto 122:f9eeca106725 6386 #define EXTI_EMR1_EM1_Msk (0x1U << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 6387 #define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */
Kojto 122:f9eeca106725 6388 #define EXTI_EMR1_EM2_Pos (2U)
Kojto 122:f9eeca106725 6389 #define EXTI_EMR1_EM2_Msk (0x1U << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 6390 #define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */
Kojto 122:f9eeca106725 6391 #define EXTI_EMR1_EM3_Pos (3U)
Kojto 122:f9eeca106725 6392 #define EXTI_EMR1_EM3_Msk (0x1U << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 6393 #define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */
Kojto 122:f9eeca106725 6394 #define EXTI_EMR1_EM4_Pos (4U)
Kojto 122:f9eeca106725 6395 #define EXTI_EMR1_EM4_Msk (0x1U << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 6396 #define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */
Kojto 122:f9eeca106725 6397 #define EXTI_EMR1_EM5_Pos (5U)
Kojto 122:f9eeca106725 6398 #define EXTI_EMR1_EM5_Msk (0x1U << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 6399 #define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */
Kojto 122:f9eeca106725 6400 #define EXTI_EMR1_EM6_Pos (6U)
Kojto 122:f9eeca106725 6401 #define EXTI_EMR1_EM6_Msk (0x1U << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 6402 #define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */
Kojto 122:f9eeca106725 6403 #define EXTI_EMR1_EM7_Pos (7U)
Kojto 122:f9eeca106725 6404 #define EXTI_EMR1_EM7_Msk (0x1U << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 6405 #define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */
Kojto 122:f9eeca106725 6406 #define EXTI_EMR1_EM8_Pos (8U)
Kojto 122:f9eeca106725 6407 #define EXTI_EMR1_EM8_Msk (0x1U << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 6408 #define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */
Kojto 122:f9eeca106725 6409 #define EXTI_EMR1_EM9_Pos (9U)
Kojto 122:f9eeca106725 6410 #define EXTI_EMR1_EM9_Msk (0x1U << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 6411 #define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */
Kojto 122:f9eeca106725 6412 #define EXTI_EMR1_EM10_Pos (10U)
Kojto 122:f9eeca106725 6413 #define EXTI_EMR1_EM10_Msk (0x1U << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 6414 #define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */
Kojto 122:f9eeca106725 6415 #define EXTI_EMR1_EM11_Pos (11U)
Kojto 122:f9eeca106725 6416 #define EXTI_EMR1_EM11_Msk (0x1U << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 6417 #define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */
Kojto 122:f9eeca106725 6418 #define EXTI_EMR1_EM12_Pos (12U)
Kojto 122:f9eeca106725 6419 #define EXTI_EMR1_EM12_Msk (0x1U << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 6420 #define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */
Kojto 122:f9eeca106725 6421 #define EXTI_EMR1_EM13_Pos (13U)
Kojto 122:f9eeca106725 6422 #define EXTI_EMR1_EM13_Msk (0x1U << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 6423 #define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */
Kojto 122:f9eeca106725 6424 #define EXTI_EMR1_EM14_Pos (14U)
Kojto 122:f9eeca106725 6425 #define EXTI_EMR1_EM14_Msk (0x1U << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 6426 #define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */
Kojto 122:f9eeca106725 6427 #define EXTI_EMR1_EM15_Pos (15U)
Kojto 122:f9eeca106725 6428 #define EXTI_EMR1_EM15_Msk (0x1U << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 6429 #define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */
Kojto 122:f9eeca106725 6430 #define EXTI_EMR1_EM16_Pos (16U)
Kojto 122:f9eeca106725 6431 #define EXTI_EMR1_EM16_Msk (0x1U << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 6432 #define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */
Kojto 122:f9eeca106725 6433 #define EXTI_EMR1_EM17_Pos (17U)
Kojto 122:f9eeca106725 6434 #define EXTI_EMR1_EM17_Msk (0x1U << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 6435 #define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */
Kojto 122:f9eeca106725 6436 #define EXTI_EMR1_EM18_Pos (18U)
Kojto 122:f9eeca106725 6437 #define EXTI_EMR1_EM18_Msk (0x1U << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 6438 #define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */
Kojto 122:f9eeca106725 6439 #define EXTI_EMR1_EM19_Pos (19U)
Kojto 122:f9eeca106725 6440 #define EXTI_EMR1_EM19_Msk (0x1U << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 6441 #define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */
Kojto 122:f9eeca106725 6442 #define EXTI_EMR1_EM20_Pos (20U)
Kojto 122:f9eeca106725 6443 #define EXTI_EMR1_EM20_Msk (0x1U << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 6444 #define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< Event Mask on line 20 */
Kojto 122:f9eeca106725 6445 #define EXTI_EMR1_EM21_Pos (21U)
Kojto 122:f9eeca106725 6446 #define EXTI_EMR1_EM21_Msk (0x1U << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 6447 #define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */
Kojto 122:f9eeca106725 6448 #define EXTI_EMR1_EM22_Pos (22U)
Kojto 122:f9eeca106725 6449 #define EXTI_EMR1_EM22_Msk (0x1U << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 6450 #define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< Event Mask on line 22 */
Kojto 122:f9eeca106725 6451 #define EXTI_EMR1_EM23_Pos (23U)
Kojto 122:f9eeca106725 6452 #define EXTI_EMR1_EM23_Msk (0x1U << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 6453 #define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */
Kojto 122:f9eeca106725 6454 #define EXTI_EMR1_EM24_Pos (24U)
Kojto 122:f9eeca106725 6455 #define EXTI_EMR1_EM24_Msk (0x1U << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 6456 #define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< Event Mask on line 24 */
Kojto 122:f9eeca106725 6457 #define EXTI_EMR1_EM25_Pos (25U)
Kojto 122:f9eeca106725 6458 #define EXTI_EMR1_EM25_Msk (0x1U << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 6459 #define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */
Kojto 122:f9eeca106725 6460 #define EXTI_EMR1_EM26_Pos (26U)
Kojto 122:f9eeca106725 6461 #define EXTI_EMR1_EM26_Msk (0x1U << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 6462 #define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */
Kojto 122:f9eeca106725 6463 #define EXTI_EMR1_EM27_Pos (27U)
Kojto 122:f9eeca106725 6464 #define EXTI_EMR1_EM27_Msk (0x1U << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 6465 #define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< Event Mask on line 27 */
Kojto 122:f9eeca106725 6466 #define EXTI_EMR1_EM28_Pos (28U)
Kojto 122:f9eeca106725 6467 #define EXTI_EMR1_EM28_Msk (0x1U << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 6468 #define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */
Kojto 122:f9eeca106725 6469 #define EXTI_EMR1_EM31_Pos (31U)
Kojto 122:f9eeca106725 6470 #define EXTI_EMR1_EM31_Msk (0x1U << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 6471 #define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */
Kojto 122:f9eeca106725 6472
Kojto 122:f9eeca106725 6473 /****************** Bit definition for EXTI_RTSR1 register ******************/
Kojto 122:f9eeca106725 6474 #define EXTI_RTSR1_RT0_Pos (0U)
Kojto 122:f9eeca106725 6475 #define EXTI_RTSR1_RT0_Msk (0x1U << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 6476 #define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
Kojto 122:f9eeca106725 6477 #define EXTI_RTSR1_RT1_Pos (1U)
Kojto 122:f9eeca106725 6478 #define EXTI_RTSR1_RT1_Msk (0x1U << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 6479 #define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
Kojto 122:f9eeca106725 6480 #define EXTI_RTSR1_RT2_Pos (2U)
Kojto 122:f9eeca106725 6481 #define EXTI_RTSR1_RT2_Msk (0x1U << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 6482 #define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
Kojto 122:f9eeca106725 6483 #define EXTI_RTSR1_RT3_Pos (3U)
Kojto 122:f9eeca106725 6484 #define EXTI_RTSR1_RT3_Msk (0x1U << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 6485 #define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
Kojto 122:f9eeca106725 6486 #define EXTI_RTSR1_RT4_Pos (4U)
Kojto 122:f9eeca106725 6487 #define EXTI_RTSR1_RT4_Msk (0x1U << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 6488 #define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
Kojto 122:f9eeca106725 6489 #define EXTI_RTSR1_RT5_Pos (5U)
Kojto 122:f9eeca106725 6490 #define EXTI_RTSR1_RT5_Msk (0x1U << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 6491 #define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
Kojto 122:f9eeca106725 6492 #define EXTI_RTSR1_RT6_Pos (6U)
Kojto 122:f9eeca106725 6493 #define EXTI_RTSR1_RT6_Msk (0x1U << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 6494 #define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
Kojto 122:f9eeca106725 6495 #define EXTI_RTSR1_RT7_Pos (7U)
Kojto 122:f9eeca106725 6496 #define EXTI_RTSR1_RT7_Msk (0x1U << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 6497 #define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
Kojto 122:f9eeca106725 6498 #define EXTI_RTSR1_RT8_Pos (8U)
Kojto 122:f9eeca106725 6499 #define EXTI_RTSR1_RT8_Msk (0x1U << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 6500 #define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
Kojto 122:f9eeca106725 6501 #define EXTI_RTSR1_RT9_Pos (9U)
Kojto 122:f9eeca106725 6502 #define EXTI_RTSR1_RT9_Msk (0x1U << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 6503 #define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
Kojto 122:f9eeca106725 6504 #define EXTI_RTSR1_RT10_Pos (10U)
Kojto 122:f9eeca106725 6505 #define EXTI_RTSR1_RT10_Msk (0x1U << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 6506 #define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
Kojto 122:f9eeca106725 6507 #define EXTI_RTSR1_RT11_Pos (11U)
Kojto 122:f9eeca106725 6508 #define EXTI_RTSR1_RT11_Msk (0x1U << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 6509 #define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
Kojto 122:f9eeca106725 6510 #define EXTI_RTSR1_RT12_Pos (12U)
Kojto 122:f9eeca106725 6511 #define EXTI_RTSR1_RT12_Msk (0x1U << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 6512 #define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
Kojto 122:f9eeca106725 6513 #define EXTI_RTSR1_RT13_Pos (13U)
Kojto 122:f9eeca106725 6514 #define EXTI_RTSR1_RT13_Msk (0x1U << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 6515 #define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
Kojto 122:f9eeca106725 6516 #define EXTI_RTSR1_RT14_Pos (14U)
Kojto 122:f9eeca106725 6517 #define EXTI_RTSR1_RT14_Msk (0x1U << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 6518 #define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
Kojto 122:f9eeca106725 6519 #define EXTI_RTSR1_RT15_Pos (15U)
Kojto 122:f9eeca106725 6520 #define EXTI_RTSR1_RT15_Msk (0x1U << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 6521 #define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
Kojto 122:f9eeca106725 6522 #define EXTI_RTSR1_RT16_Pos (16U)
Kojto 122:f9eeca106725 6523 #define EXTI_RTSR1_RT16_Msk (0x1U << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 6524 #define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
Kojto 122:f9eeca106725 6525 #define EXTI_RTSR1_RT18_Pos (18U)
Kojto 122:f9eeca106725 6526 #define EXTI_RTSR1_RT18_Msk (0x1U << EXTI_RTSR1_RT18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 6527 #define EXTI_RTSR1_RT18 EXTI_RTSR1_RT18_Msk /*!< Rising trigger event configuration bit of line 18 */
Kojto 122:f9eeca106725 6528 #define EXTI_RTSR1_RT19_Pos (19U)
Kojto 122:f9eeca106725 6529 #define EXTI_RTSR1_RT19_Msk (0x1U << EXTI_RTSR1_RT19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 6530 #define EXTI_RTSR1_RT19 EXTI_RTSR1_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
Kojto 122:f9eeca106725 6531 #define EXTI_RTSR1_RT20_Pos (20U)
Kojto 122:f9eeca106725 6532 #define EXTI_RTSR1_RT20_Msk (0x1U << EXTI_RTSR1_RT20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 6533 #define EXTI_RTSR1_RT20 EXTI_RTSR1_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
Kojto 122:f9eeca106725 6534 #define EXTI_RTSR1_RT21_Pos (21U)
Kojto 122:f9eeca106725 6535 #define EXTI_RTSR1_RT21_Msk (0x1U << EXTI_RTSR1_RT21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 6536 #define EXTI_RTSR1_RT21 EXTI_RTSR1_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
Kojto 122:f9eeca106725 6537 #define EXTI_RTSR1_RT22_Pos (22U)
Kojto 122:f9eeca106725 6538 #define EXTI_RTSR1_RT22_Msk (0x1U << EXTI_RTSR1_RT22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 6539 #define EXTI_RTSR1_RT22 EXTI_RTSR1_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
Kojto 122:f9eeca106725 6540
Kojto 122:f9eeca106725 6541 /****************** Bit definition for EXTI_FTSR1 register ******************/
Kojto 122:f9eeca106725 6542 #define EXTI_FTSR1_FT0_Pos (0U)
Kojto 122:f9eeca106725 6543 #define EXTI_FTSR1_FT0_Msk (0x1U << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 6544 #define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
Kojto 122:f9eeca106725 6545 #define EXTI_FTSR1_FT1_Pos (1U)
Kojto 122:f9eeca106725 6546 #define EXTI_FTSR1_FT1_Msk (0x1U << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 6547 #define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
Kojto 122:f9eeca106725 6548 #define EXTI_FTSR1_FT2_Pos (2U)
Kojto 122:f9eeca106725 6549 #define EXTI_FTSR1_FT2_Msk (0x1U << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 6550 #define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
Kojto 122:f9eeca106725 6551 #define EXTI_FTSR1_FT3_Pos (3U)
Kojto 122:f9eeca106725 6552 #define EXTI_FTSR1_FT3_Msk (0x1U << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 6553 #define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
Kojto 122:f9eeca106725 6554 #define EXTI_FTSR1_FT4_Pos (4U)
Kojto 122:f9eeca106725 6555 #define EXTI_FTSR1_FT4_Msk (0x1U << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 6556 #define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
Kojto 122:f9eeca106725 6557 #define EXTI_FTSR1_FT5_Pos (5U)
Kojto 122:f9eeca106725 6558 #define EXTI_FTSR1_FT5_Msk (0x1U << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 6559 #define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
Kojto 122:f9eeca106725 6560 #define EXTI_FTSR1_FT6_Pos (6U)
Kojto 122:f9eeca106725 6561 #define EXTI_FTSR1_FT6_Msk (0x1U << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 6562 #define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
Kojto 122:f9eeca106725 6563 #define EXTI_FTSR1_FT7_Pos (7U)
Kojto 122:f9eeca106725 6564 #define EXTI_FTSR1_FT7_Msk (0x1U << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 6565 #define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
Kojto 122:f9eeca106725 6566 #define EXTI_FTSR1_FT8_Pos (8U)
Kojto 122:f9eeca106725 6567 #define EXTI_FTSR1_FT8_Msk (0x1U << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 6568 #define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
Kojto 122:f9eeca106725 6569 #define EXTI_FTSR1_FT9_Pos (9U)
Kojto 122:f9eeca106725 6570 #define EXTI_FTSR1_FT9_Msk (0x1U << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 6571 #define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
Kojto 122:f9eeca106725 6572 #define EXTI_FTSR1_FT10_Pos (10U)
Kojto 122:f9eeca106725 6573 #define EXTI_FTSR1_FT10_Msk (0x1U << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 6574 #define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
Kojto 122:f9eeca106725 6575 #define EXTI_FTSR1_FT11_Pos (11U)
Kojto 122:f9eeca106725 6576 #define EXTI_FTSR1_FT11_Msk (0x1U << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 6577 #define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
Kojto 122:f9eeca106725 6578 #define EXTI_FTSR1_FT12_Pos (12U)
Kojto 122:f9eeca106725 6579 #define EXTI_FTSR1_FT12_Msk (0x1U << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 6580 #define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
Kojto 122:f9eeca106725 6581 #define EXTI_FTSR1_FT13_Pos (13U)
Kojto 122:f9eeca106725 6582 #define EXTI_FTSR1_FT13_Msk (0x1U << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 6583 #define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
Kojto 122:f9eeca106725 6584 #define EXTI_FTSR1_FT14_Pos (14U)
Kojto 122:f9eeca106725 6585 #define EXTI_FTSR1_FT14_Msk (0x1U << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 6586 #define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
Kojto 122:f9eeca106725 6587 #define EXTI_FTSR1_FT15_Pos (15U)
Kojto 122:f9eeca106725 6588 #define EXTI_FTSR1_FT15_Msk (0x1U << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 6589 #define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
Kojto 122:f9eeca106725 6590 #define EXTI_FTSR1_FT16_Pos (16U)
Kojto 122:f9eeca106725 6591 #define EXTI_FTSR1_FT16_Msk (0x1U << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 6592 #define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
Kojto 122:f9eeca106725 6593 #define EXTI_FTSR1_FT18_Pos (18U)
Kojto 122:f9eeca106725 6594 #define EXTI_FTSR1_FT18_Msk (0x1U << EXTI_FTSR1_FT18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 6595 #define EXTI_FTSR1_FT18 EXTI_FTSR1_FT18_Msk /*!< Falling trigger event configuration bit of line 18 */
Kojto 122:f9eeca106725 6596 #define EXTI_FTSR1_FT19_Pos (19U)
Kojto 122:f9eeca106725 6597 #define EXTI_FTSR1_FT19_Msk (0x1U << EXTI_FTSR1_FT19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 6598 #define EXTI_FTSR1_FT19 EXTI_FTSR1_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
Kojto 122:f9eeca106725 6599 #define EXTI_FTSR1_FT20_Pos (20U)
Kojto 122:f9eeca106725 6600 #define EXTI_FTSR1_FT20_Msk (0x1U << EXTI_FTSR1_FT20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 6601 #define EXTI_FTSR1_FT20 EXTI_FTSR1_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
Kojto 122:f9eeca106725 6602 #define EXTI_FTSR1_FT21_Pos (21U)
Kojto 122:f9eeca106725 6603 #define EXTI_FTSR1_FT21_Msk (0x1U << EXTI_FTSR1_FT21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 6604 #define EXTI_FTSR1_FT21 EXTI_FTSR1_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
Kojto 122:f9eeca106725 6605 #define EXTI_FTSR1_FT22_Pos (22U)
Kojto 122:f9eeca106725 6606 #define EXTI_FTSR1_FT22_Msk (0x1U << EXTI_FTSR1_FT22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 6607 #define EXTI_FTSR1_FT22 EXTI_FTSR1_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
Kojto 122:f9eeca106725 6608
Kojto 122:f9eeca106725 6609 /****************** Bit definition for EXTI_SWIER1 register *****************/
Kojto 122:f9eeca106725 6610 #define EXTI_SWIER1_SWI0_Pos (0U)
Kojto 122:f9eeca106725 6611 #define EXTI_SWIER1_SWI0_Msk (0x1U << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 6612 #define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */
Kojto 122:f9eeca106725 6613 #define EXTI_SWIER1_SWI1_Pos (1U)
Kojto 122:f9eeca106725 6614 #define EXTI_SWIER1_SWI1_Msk (0x1U << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 6615 #define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */
Kojto 122:f9eeca106725 6616 #define EXTI_SWIER1_SWI2_Pos (2U)
Kojto 122:f9eeca106725 6617 #define EXTI_SWIER1_SWI2_Msk (0x1U << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 6618 #define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */
Kojto 122:f9eeca106725 6619 #define EXTI_SWIER1_SWI3_Pos (3U)
Kojto 122:f9eeca106725 6620 #define EXTI_SWIER1_SWI3_Msk (0x1U << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 6621 #define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */
Kojto 122:f9eeca106725 6622 #define EXTI_SWIER1_SWI4_Pos (4U)
Kojto 122:f9eeca106725 6623 #define EXTI_SWIER1_SWI4_Msk (0x1U << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 6624 #define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */
Kojto 122:f9eeca106725 6625 #define EXTI_SWIER1_SWI5_Pos (5U)
Kojto 122:f9eeca106725 6626 #define EXTI_SWIER1_SWI5_Msk (0x1U << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 6627 #define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */
Kojto 122:f9eeca106725 6628 #define EXTI_SWIER1_SWI6_Pos (6U)
Kojto 122:f9eeca106725 6629 #define EXTI_SWIER1_SWI6_Msk (0x1U << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 6630 #define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */
Kojto 122:f9eeca106725 6631 #define EXTI_SWIER1_SWI7_Pos (7U)
Kojto 122:f9eeca106725 6632 #define EXTI_SWIER1_SWI7_Msk (0x1U << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 6633 #define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */
Kojto 122:f9eeca106725 6634 #define EXTI_SWIER1_SWI8_Pos (8U)
Kojto 122:f9eeca106725 6635 #define EXTI_SWIER1_SWI8_Msk (0x1U << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 6636 #define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */
Kojto 122:f9eeca106725 6637 #define EXTI_SWIER1_SWI9_Pos (9U)
Kojto 122:f9eeca106725 6638 #define EXTI_SWIER1_SWI9_Msk (0x1U << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 6639 #define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */
Kojto 122:f9eeca106725 6640 #define EXTI_SWIER1_SWI10_Pos (10U)
Kojto 122:f9eeca106725 6641 #define EXTI_SWIER1_SWI10_Msk (0x1U << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 6642 #define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */
Kojto 122:f9eeca106725 6643 #define EXTI_SWIER1_SWI11_Pos (11U)
Kojto 122:f9eeca106725 6644 #define EXTI_SWIER1_SWI11_Msk (0x1U << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 6645 #define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */
Kojto 122:f9eeca106725 6646 #define EXTI_SWIER1_SWI12_Pos (12U)
Kojto 122:f9eeca106725 6647 #define EXTI_SWIER1_SWI12_Msk (0x1U << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 6648 #define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */
Kojto 122:f9eeca106725 6649 #define EXTI_SWIER1_SWI13_Pos (13U)
Kojto 122:f9eeca106725 6650 #define EXTI_SWIER1_SWI13_Msk (0x1U << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 6651 #define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */
Kojto 122:f9eeca106725 6652 #define EXTI_SWIER1_SWI14_Pos (14U)
Kojto 122:f9eeca106725 6653 #define EXTI_SWIER1_SWI14_Msk (0x1U << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 6654 #define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */
Kojto 122:f9eeca106725 6655 #define EXTI_SWIER1_SWI15_Pos (15U)
Kojto 122:f9eeca106725 6656 #define EXTI_SWIER1_SWI15_Msk (0x1U << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 6657 #define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */
Kojto 122:f9eeca106725 6658 #define EXTI_SWIER1_SWI16_Pos (16U)
Kojto 122:f9eeca106725 6659 #define EXTI_SWIER1_SWI16_Msk (0x1U << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 6660 #define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software Interrupt on line 16 */
Kojto 122:f9eeca106725 6661 #define EXTI_SWIER1_SWI18_Pos (18U)
Kojto 122:f9eeca106725 6662 #define EXTI_SWIER1_SWI18_Msk (0x1U << EXTI_SWIER1_SWI18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 6663 #define EXTI_SWIER1_SWI18 EXTI_SWIER1_SWI18_Msk /*!< Software Interrupt on line 18 */
Kojto 122:f9eeca106725 6664 #define EXTI_SWIER1_SWI19_Pos (19U)
Kojto 122:f9eeca106725 6665 #define EXTI_SWIER1_SWI19_Msk (0x1U << EXTI_SWIER1_SWI19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 6666 #define EXTI_SWIER1_SWI19 EXTI_SWIER1_SWI19_Msk /*!< Software Interrupt on line 19 */
Kojto 122:f9eeca106725 6667 #define EXTI_SWIER1_SWI20_Pos (20U)
Kojto 122:f9eeca106725 6668 #define EXTI_SWIER1_SWI20_Msk (0x1U << EXTI_SWIER1_SWI20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 6669 #define EXTI_SWIER1_SWI20 EXTI_SWIER1_SWI20_Msk /*!< Software Interrupt on line 20 */
Kojto 122:f9eeca106725 6670 #define EXTI_SWIER1_SWI21_Pos (21U)
Kojto 122:f9eeca106725 6671 #define EXTI_SWIER1_SWI21_Msk (0x1U << EXTI_SWIER1_SWI21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 6672 #define EXTI_SWIER1_SWI21 EXTI_SWIER1_SWI21_Msk /*!< Software Interrupt on line 21 */
Kojto 122:f9eeca106725 6673 #define EXTI_SWIER1_SWI22_Pos (22U)
Kojto 122:f9eeca106725 6674 #define EXTI_SWIER1_SWI22_Msk (0x1U << EXTI_SWIER1_SWI22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 6675 #define EXTI_SWIER1_SWI22 EXTI_SWIER1_SWI22_Msk /*!< Software Interrupt on line 22 */
Kojto 122:f9eeca106725 6676
Kojto 122:f9eeca106725 6677 /******************* Bit definition for EXTI_PR1 register *******************/
Kojto 122:f9eeca106725 6678 #define EXTI_PR1_PIF0_Pos (0U)
Kojto 122:f9eeca106725 6679 #define EXTI_PR1_PIF0_Msk (0x1U << EXTI_PR1_PIF0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 6680 #define EXTI_PR1_PIF0 EXTI_PR1_PIF0_Msk /*!< Pending bit for line 0 */
Kojto 122:f9eeca106725 6681 #define EXTI_PR1_PIF1_Pos (1U)
Kojto 122:f9eeca106725 6682 #define EXTI_PR1_PIF1_Msk (0x1U << EXTI_PR1_PIF1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 6683 #define EXTI_PR1_PIF1 EXTI_PR1_PIF1_Msk /*!< Pending bit for line 1 */
Kojto 122:f9eeca106725 6684 #define EXTI_PR1_PIF2_Pos (2U)
Kojto 122:f9eeca106725 6685 #define EXTI_PR1_PIF2_Msk (0x1U << EXTI_PR1_PIF2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 6686 #define EXTI_PR1_PIF2 EXTI_PR1_PIF2_Msk /*!< Pending bit for line 2 */
Kojto 122:f9eeca106725 6687 #define EXTI_PR1_PIF3_Pos (3U)
Kojto 122:f9eeca106725 6688 #define EXTI_PR1_PIF3_Msk (0x1U << EXTI_PR1_PIF3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 6689 #define EXTI_PR1_PIF3 EXTI_PR1_PIF3_Msk /*!< Pending bit for line 3 */
Kojto 122:f9eeca106725 6690 #define EXTI_PR1_PIF4_Pos (4U)
Kojto 122:f9eeca106725 6691 #define EXTI_PR1_PIF4_Msk (0x1U << EXTI_PR1_PIF4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 6692 #define EXTI_PR1_PIF4 EXTI_PR1_PIF4_Msk /*!< Pending bit for line 4 */
Kojto 122:f9eeca106725 6693 #define EXTI_PR1_PIF5_Pos (5U)
Kojto 122:f9eeca106725 6694 #define EXTI_PR1_PIF5_Msk (0x1U << EXTI_PR1_PIF5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 6695 #define EXTI_PR1_PIF5 EXTI_PR1_PIF5_Msk /*!< Pending bit for line 5 */
Kojto 122:f9eeca106725 6696 #define EXTI_PR1_PIF6_Pos (6U)
Kojto 122:f9eeca106725 6697 #define EXTI_PR1_PIF6_Msk (0x1U << EXTI_PR1_PIF6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 6698 #define EXTI_PR1_PIF6 EXTI_PR1_PIF6_Msk /*!< Pending bit for line 6 */
Kojto 122:f9eeca106725 6699 #define EXTI_PR1_PIF7_Pos (7U)
Kojto 122:f9eeca106725 6700 #define EXTI_PR1_PIF7_Msk (0x1U << EXTI_PR1_PIF7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 6701 #define EXTI_PR1_PIF7 EXTI_PR1_PIF7_Msk /*!< Pending bit for line 7 */
Kojto 122:f9eeca106725 6702 #define EXTI_PR1_PIF8_Pos (8U)
Kojto 122:f9eeca106725 6703 #define EXTI_PR1_PIF8_Msk (0x1U << EXTI_PR1_PIF8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 6704 #define EXTI_PR1_PIF8 EXTI_PR1_PIF8_Msk /*!< Pending bit for line 8 */
Kojto 122:f9eeca106725 6705 #define EXTI_PR1_PIF9_Pos (9U)
Kojto 122:f9eeca106725 6706 #define EXTI_PR1_PIF9_Msk (0x1U << EXTI_PR1_PIF9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 6707 #define EXTI_PR1_PIF9 EXTI_PR1_PIF9_Msk /*!< Pending bit for line 9 */
Kojto 122:f9eeca106725 6708 #define EXTI_PR1_PIF10_Pos (10U)
Kojto 122:f9eeca106725 6709 #define EXTI_PR1_PIF10_Msk (0x1U << EXTI_PR1_PIF10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 6710 #define EXTI_PR1_PIF10 EXTI_PR1_PIF10_Msk /*!< Pending bit for line 10 */
Kojto 122:f9eeca106725 6711 #define EXTI_PR1_PIF11_Pos (11U)
Kojto 122:f9eeca106725 6712 #define EXTI_PR1_PIF11_Msk (0x1U << EXTI_PR1_PIF11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 6713 #define EXTI_PR1_PIF11 EXTI_PR1_PIF11_Msk /*!< Pending bit for line 11 */
Kojto 122:f9eeca106725 6714 #define EXTI_PR1_PIF12_Pos (12U)
Kojto 122:f9eeca106725 6715 #define EXTI_PR1_PIF12_Msk (0x1U << EXTI_PR1_PIF12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 6716 #define EXTI_PR1_PIF12 EXTI_PR1_PIF12_Msk /*!< Pending bit for line 12 */
Kojto 122:f9eeca106725 6717 #define EXTI_PR1_PIF13_Pos (13U)
Kojto 122:f9eeca106725 6718 #define EXTI_PR1_PIF13_Msk (0x1U << EXTI_PR1_PIF13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 6719 #define EXTI_PR1_PIF13 EXTI_PR1_PIF13_Msk /*!< Pending bit for line 13 */
Kojto 122:f9eeca106725 6720 #define EXTI_PR1_PIF14_Pos (14U)
Kojto 122:f9eeca106725 6721 #define EXTI_PR1_PIF14_Msk (0x1U << EXTI_PR1_PIF14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 6722 #define EXTI_PR1_PIF14 EXTI_PR1_PIF14_Msk /*!< Pending bit for line 14 */
Kojto 122:f9eeca106725 6723 #define EXTI_PR1_PIF15_Pos (15U)
Kojto 122:f9eeca106725 6724 #define EXTI_PR1_PIF15_Msk (0x1U << EXTI_PR1_PIF15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 6725 #define EXTI_PR1_PIF15 EXTI_PR1_PIF15_Msk /*!< Pending bit for line 15 */
Kojto 122:f9eeca106725 6726 #define EXTI_PR1_PIF16_Pos (16U)
Kojto 122:f9eeca106725 6727 #define EXTI_PR1_PIF16_Msk (0x1U << EXTI_PR1_PIF16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 6728 #define EXTI_PR1_PIF16 EXTI_PR1_PIF16_Msk /*!< Pending bit for line 16 */
Kojto 122:f9eeca106725 6729 #define EXTI_PR1_PIF18_Pos (18U)
Kojto 122:f9eeca106725 6730 #define EXTI_PR1_PIF18_Msk (0x1U << EXTI_PR1_PIF18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 6731 #define EXTI_PR1_PIF18 EXTI_PR1_PIF18_Msk /*!< Pending bit for line 18 */
Kojto 122:f9eeca106725 6732 #define EXTI_PR1_PIF19_Pos (19U)
Kojto 122:f9eeca106725 6733 #define EXTI_PR1_PIF19_Msk (0x1U << EXTI_PR1_PIF19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 6734 #define EXTI_PR1_PIF19 EXTI_PR1_PIF19_Msk /*!< Pending bit for line 19 */
Kojto 122:f9eeca106725 6735 #define EXTI_PR1_PIF20_Pos (20U)
Kojto 122:f9eeca106725 6736 #define EXTI_PR1_PIF20_Msk (0x1U << EXTI_PR1_PIF20_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 6737 #define EXTI_PR1_PIF20 EXTI_PR1_PIF20_Msk /*!< Pending bit for line 20 */
Kojto 122:f9eeca106725 6738 #define EXTI_PR1_PIF21_Pos (21U)
Kojto 122:f9eeca106725 6739 #define EXTI_PR1_PIF21_Msk (0x1U << EXTI_PR1_PIF21_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 6740 #define EXTI_PR1_PIF21 EXTI_PR1_PIF21_Msk /*!< Pending bit for line 21 */
Kojto 122:f9eeca106725 6741 #define EXTI_PR1_PIF22_Pos (22U)
Kojto 122:f9eeca106725 6742 #define EXTI_PR1_PIF22_Msk (0x1U << EXTI_PR1_PIF22_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 6743 #define EXTI_PR1_PIF22 EXTI_PR1_PIF22_Msk /*!< Pending bit for line 22 */
Kojto 122:f9eeca106725 6744
Kojto 122:f9eeca106725 6745 /******************* Bit definition for EXTI_IMR2 register ******************/
Kojto 122:f9eeca106725 6746 #define EXTI_IMR2_IM32_Pos (0U)
Kojto 122:f9eeca106725 6747 #define EXTI_IMR2_IM32_Msk (0x1U << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 6748 #define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< Interrupt Mask on line 32 */
Kojto 122:f9eeca106725 6749 #define EXTI_IMR2_IM33_Pos (1U)
Kojto 122:f9eeca106725 6750 #define EXTI_IMR2_IM33_Msk (0x1U << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 6751 #define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< Interrupt Mask on line 33 */
Kojto 122:f9eeca106725 6752 #define EXTI_IMR2_IM34_Pos (2U)
Kojto 122:f9eeca106725 6753 #define EXTI_IMR2_IM34_Msk (0x1U << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 6754 #define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< Interrupt Mask on line 34 */
Kojto 122:f9eeca106725 6755 #define EXTI_IMR2_IM35_Pos (3U)
Kojto 122:f9eeca106725 6756 #define EXTI_IMR2_IM35_Msk (0x1U << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 6757 #define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
Kojto 122:f9eeca106725 6758 #define EXTI_IMR2_IM36_Pos (4U)
Kojto 122:f9eeca106725 6759 #define EXTI_IMR2_IM36_Msk (0x1U << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 6760 #define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */
Kojto 122:f9eeca106725 6761 #define EXTI_IMR2_IM37_Pos (5U)
Kojto 122:f9eeca106725 6762 #define EXTI_IMR2_IM37_Msk (0x1U << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 6763 #define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
Kojto 122:f9eeca106725 6764 #define EXTI_IMR2_IM38_Pos (6U)
Kojto 122:f9eeca106725 6765 #define EXTI_IMR2_IM38_Msk (0x1U << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 6766 #define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
Kojto 122:f9eeca106725 6767 #define EXTI_IMR2_IM39_Pos (7U)
Kojto 122:f9eeca106725 6768 #define EXTI_IMR2_IM39_Msk (0x1U << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 6769 #define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
Kojto 122:f9eeca106725 6770 #define EXTI_IMR2_IM_Pos (0U)
Kojto 122:f9eeca106725 6771 #define EXTI_IMR2_IM_Msk (0xFFU << EXTI_IMR2_IM_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 6772 #define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */
Kojto 122:f9eeca106725 6773
Kojto 122:f9eeca106725 6774 /******************* Bit definition for EXTI_EMR2 register ******************/
Kojto 122:f9eeca106725 6775 #define EXTI_EMR2_EM32_Pos (0U)
Kojto 122:f9eeca106725 6776 #define EXTI_EMR2_EM32_Msk (0x1U << EXTI_EMR2_EM32_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 6777 #define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk /*!< Event Mask on line 32 */
Kojto 122:f9eeca106725 6778 #define EXTI_EMR2_EM33_Pos (1U)
Kojto 122:f9eeca106725 6779 #define EXTI_EMR2_EM33_Msk (0x1U << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 6780 #define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33 */
Kojto 122:f9eeca106725 6781 #define EXTI_EMR2_EM34_Pos (2U)
Kojto 122:f9eeca106725 6782 #define EXTI_EMR2_EM34_Msk (0x1U << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 6783 #define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< Event Mask on line 34 */
Kojto 122:f9eeca106725 6784 #define EXTI_EMR2_EM35_Pos (3U)
Kojto 122:f9eeca106725 6785 #define EXTI_EMR2_EM35_Msk (0x1U << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 6786 #define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35 */
Kojto 122:f9eeca106725 6787 #define EXTI_EMR2_EM36_Pos (4U)
Kojto 122:f9eeca106725 6788 #define EXTI_EMR2_EM36_Msk (0x1U << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 6789 #define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36 */
Kojto 122:f9eeca106725 6790 #define EXTI_EMR2_EM37_Pos (5U)
Kojto 122:f9eeca106725 6791 #define EXTI_EMR2_EM37_Msk (0x1U << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 6792 #define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37 */
Kojto 122:f9eeca106725 6793 #define EXTI_EMR2_EM38_Pos (6U)
Kojto 122:f9eeca106725 6794 #define EXTI_EMR2_EM38_Msk (0x1U << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 6795 #define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */
Kojto 122:f9eeca106725 6796 #define EXTI_EMR2_EM39_Pos (7U)
Kojto 122:f9eeca106725 6797 #define EXTI_EMR2_EM39_Msk (0x1U << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 6798 #define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
Kojto 122:f9eeca106725 6799
Kojto 122:f9eeca106725 6800 /****************** Bit definition for EXTI_RTSR2 register ******************/
Kojto 122:f9eeca106725 6801 #define EXTI_RTSR2_RT35_Pos (3U)
Kojto 122:f9eeca106725 6802 #define EXTI_RTSR2_RT35_Msk (0x1U << EXTI_RTSR2_RT35_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 6803 #define EXTI_RTSR2_RT35 EXTI_RTSR2_RT35_Msk /*!< Rising trigger event configuration bit of line 35 */
Kojto 122:f9eeca106725 6804 #define EXTI_RTSR2_RT36_Pos (4U)
Kojto 122:f9eeca106725 6805 #define EXTI_RTSR2_RT36_Msk (0x1U << EXTI_RTSR2_RT36_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 6806 #define EXTI_RTSR2_RT36 EXTI_RTSR2_RT36_Msk /*!< Rising trigger event configuration bit of line 36 */
Kojto 122:f9eeca106725 6807 #define EXTI_RTSR2_RT37_Pos (5U)
Kojto 122:f9eeca106725 6808 #define EXTI_RTSR2_RT37_Msk (0x1U << EXTI_RTSR2_RT37_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 6809 #define EXTI_RTSR2_RT37 EXTI_RTSR2_RT37_Msk /*!< Rising trigger event configuration bit of line 37 */
Kojto 122:f9eeca106725 6810 #define EXTI_RTSR2_RT38_Pos (6U)
Kojto 122:f9eeca106725 6811 #define EXTI_RTSR2_RT38_Msk (0x1U << EXTI_RTSR2_RT38_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 6812 #define EXTI_RTSR2_RT38 EXTI_RTSR2_RT38_Msk /*!< Rising trigger event configuration bit of line 38 */
Kojto 122:f9eeca106725 6813
Kojto 122:f9eeca106725 6814 /****************** Bit definition for EXTI_FTSR2 register ******************/
Kojto 122:f9eeca106725 6815 #define EXTI_FTSR2_FT35_Pos (3U)
Kojto 122:f9eeca106725 6816 #define EXTI_FTSR2_FT35_Msk (0x1U << EXTI_FTSR2_FT35_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 6817 #define EXTI_FTSR2_FT35 EXTI_FTSR2_FT35_Msk /*!< Falling trigger event configuration bit of line 35 */
Kojto 122:f9eeca106725 6818 #define EXTI_FTSR2_FT36_Pos (4U)
Kojto 122:f9eeca106725 6819 #define EXTI_FTSR2_FT36_Msk (0x1U << EXTI_FTSR2_FT36_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 6820 #define EXTI_FTSR2_FT36 EXTI_FTSR2_FT36_Msk /*!< Falling trigger event configuration bit of line 36 */
Kojto 122:f9eeca106725 6821 #define EXTI_FTSR2_FT37_Pos (5U)
Kojto 122:f9eeca106725 6822 #define EXTI_FTSR2_FT37_Msk (0x1U << EXTI_FTSR2_FT37_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 6823 #define EXTI_FTSR2_FT37 EXTI_FTSR2_FT37_Msk /*!< Falling trigger event configuration bit of line 37 */
Kojto 122:f9eeca106725 6824 #define EXTI_FTSR2_FT38_Pos (6U)
Kojto 122:f9eeca106725 6825 #define EXTI_FTSR2_FT38_Msk (0x1U << EXTI_FTSR2_FT38_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 6826 #define EXTI_FTSR2_FT38 EXTI_FTSR2_FT38_Msk /*!< Falling trigger event configuration bit of line 38 */
Kojto 122:f9eeca106725 6827
Kojto 122:f9eeca106725 6828 /****************** Bit definition for EXTI_SWIER2 register *****************/
Kojto 122:f9eeca106725 6829 #define EXTI_SWIER2_SWI35_Pos (3U)
Kojto 122:f9eeca106725 6830 #define EXTI_SWIER2_SWI35_Msk (0x1U << EXTI_SWIER2_SWI35_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 6831 #define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWI35_Msk /*!< Software Interrupt on line 35 */
Kojto 122:f9eeca106725 6832 #define EXTI_SWIER2_SWI36_Pos (4U)
Kojto 122:f9eeca106725 6833 #define EXTI_SWIER2_SWI36_Msk (0x1U << EXTI_SWIER2_SWI36_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 6834 #define EXTI_SWIER2_SWI36 EXTI_SWIER2_SWI36_Msk /*!< Software Interrupt on line 36 */
Kojto 122:f9eeca106725 6835 #define EXTI_SWIER2_SWI37_Pos (5U)
Kojto 122:f9eeca106725 6836 #define EXTI_SWIER2_SWI37_Msk (0x1U << EXTI_SWIER2_SWI37_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 6837 #define EXTI_SWIER2_SWI37 EXTI_SWIER2_SWI37_Msk /*!< Software Interrupt on line 37 */
Kojto 122:f9eeca106725 6838 #define EXTI_SWIER2_SWI38_Pos (6U)
Kojto 122:f9eeca106725 6839 #define EXTI_SWIER2_SWI38_Msk (0x1U << EXTI_SWIER2_SWI38_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 6840 #define EXTI_SWIER2_SWI38 EXTI_SWIER2_SWI38_Msk /*!< Software Interrupt on line 38 */
Kojto 122:f9eeca106725 6841
Kojto 122:f9eeca106725 6842 /******************* Bit definition for EXTI_PR2 register *******************/
Kojto 122:f9eeca106725 6843 #define EXTI_PR2_PIF35_Pos (3U)
Kojto 122:f9eeca106725 6844 #define EXTI_PR2_PIF35_Msk (0x1U << EXTI_PR2_PIF35_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 6845 #define EXTI_PR2_PIF35 EXTI_PR2_PIF35_Msk /*!< Pending bit for line 35 */
Kojto 122:f9eeca106725 6846 #define EXTI_PR2_PIF36_Pos (4U)
Kojto 122:f9eeca106725 6847 #define EXTI_PR2_PIF36_Msk (0x1U << EXTI_PR2_PIF36_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 6848 #define EXTI_PR2_PIF36 EXTI_PR2_PIF36_Msk /*!< Pending bit for line 36 */
Kojto 122:f9eeca106725 6849 #define EXTI_PR2_PIF37_Pos (5U)
Kojto 122:f9eeca106725 6850 #define EXTI_PR2_PIF37_Msk (0x1U << EXTI_PR2_PIF37_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 6851 #define EXTI_PR2_PIF37 EXTI_PR2_PIF37_Msk /*!< Pending bit for line 37 */
Kojto 122:f9eeca106725 6852 #define EXTI_PR2_PIF38_Pos (6U)
Kojto 122:f9eeca106725 6853 #define EXTI_PR2_PIF38_Msk (0x1U << EXTI_PR2_PIF38_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 6854 #define EXTI_PR2_PIF38 EXTI_PR2_PIF38_Msk /*!< Pending bit for line 38 */
Kojto 122:f9eeca106725 6855
Kojto 122:f9eeca106725 6856
Kojto 122:f9eeca106725 6857 /******************************************************************************/
Kojto 122:f9eeca106725 6858 /* */
Kojto 122:f9eeca106725 6859 /* FLASH */
Kojto 122:f9eeca106725 6860 /* */
Kojto 122:f9eeca106725 6861 /******************************************************************************/
Kojto 122:f9eeca106725 6862 /******************* Bits definition for FLASH_ACR register *****************/
Kojto 122:f9eeca106725 6863 #define FLASH_ACR_LATENCY_Pos (0U)
Kojto 122:f9eeca106725 6864 #define FLASH_ACR_LATENCY_Msk (0x7U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
Kojto 122:f9eeca106725 6865 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
Kojto 122:f9eeca106725 6866 #define FLASH_ACR_LATENCY_0WS (0x00000000U)
Kojto 122:f9eeca106725 6867 #define FLASH_ACR_LATENCY_1WS (0x00000001U)
Kojto 122:f9eeca106725 6868 #define FLASH_ACR_LATENCY_2WS (0x00000002U)
Kojto 122:f9eeca106725 6869 #define FLASH_ACR_LATENCY_3WS (0x00000003U)
Kojto 122:f9eeca106725 6870 #define FLASH_ACR_LATENCY_4WS (0x00000004U)
Kojto 122:f9eeca106725 6871 #define FLASH_ACR_PRFTEN_Pos (8U)
Kojto 122:f9eeca106725 6872 #define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 6873 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
Kojto 122:f9eeca106725 6874 #define FLASH_ACR_ICEN_Pos (9U)
Kojto 122:f9eeca106725 6875 #define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 6876 #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
Kojto 122:f9eeca106725 6877 #define FLASH_ACR_DCEN_Pos (10U)
Kojto 122:f9eeca106725 6878 #define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 6879 #define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
Kojto 122:f9eeca106725 6880 #define FLASH_ACR_ICRST_Pos (11U)
Kojto 122:f9eeca106725 6881 #define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 6882 #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
Kojto 122:f9eeca106725 6883 #define FLASH_ACR_DCRST_Pos (12U)
Kojto 122:f9eeca106725 6884 #define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 6885 #define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
Kojto 122:f9eeca106725 6886 #define FLASH_ACR_RUN_PD_Pos (13U)
Kojto 122:f9eeca106725 6887 #define FLASH_ACR_RUN_PD_Msk (0x1U << FLASH_ACR_RUN_PD_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 6888 #define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash power down mode during run */
Kojto 122:f9eeca106725 6889 #define FLASH_ACR_SLEEP_PD_Pos (14U)
Kojto 122:f9eeca106725 6890 #define FLASH_ACR_SLEEP_PD_Msk (0x1U << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 6891 #define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power down mode during sleep */
Kojto 122:f9eeca106725 6892
Kojto 122:f9eeca106725 6893 /******************* Bits definition for FLASH_SR register ******************/
Kojto 122:f9eeca106725 6894 #define FLASH_SR_EOP_Pos (0U)
Kojto 122:f9eeca106725 6895 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 6896 #define FLASH_SR_EOP FLASH_SR_EOP_Msk
Kojto 122:f9eeca106725 6897 #define FLASH_SR_OPERR_Pos (1U)
Kojto 122:f9eeca106725 6898 #define FLASH_SR_OPERR_Msk (0x1U << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 6899 #define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
Kojto 122:f9eeca106725 6900 #define FLASH_SR_PROGERR_Pos (3U)
Kojto 122:f9eeca106725 6901 #define FLASH_SR_PROGERR_Msk (0x1U << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 6902 #define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk
Kojto 122:f9eeca106725 6903 #define FLASH_SR_WRPERR_Pos (4U)
Kojto 122:f9eeca106725 6904 #define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 6905 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
Kojto 122:f9eeca106725 6906 #define FLASH_SR_PGAERR_Pos (5U)
Kojto 122:f9eeca106725 6907 #define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 6908 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
Kojto 122:f9eeca106725 6909 #define FLASH_SR_SIZERR_Pos (6U)
Kojto 122:f9eeca106725 6910 #define FLASH_SR_SIZERR_Msk (0x1U << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 6911 #define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk
Kojto 122:f9eeca106725 6912 #define FLASH_SR_PGSERR_Pos (7U)
Kojto 122:f9eeca106725 6913 #define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 6914 #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
Kojto 122:f9eeca106725 6915 #define FLASH_SR_MISERR_Pos (8U)
Kojto 122:f9eeca106725 6916 #define FLASH_SR_MISERR_Msk (0x1U << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 6917 #define FLASH_SR_MISERR FLASH_SR_MISERR_Msk
Kojto 122:f9eeca106725 6918 #define FLASH_SR_FASTERR_Pos (9U)
Kojto 122:f9eeca106725 6919 #define FLASH_SR_FASTERR_Msk (0x1U << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 6920 #define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk
Kojto 122:f9eeca106725 6921 #define FLASH_SR_RDERR_Pos (14U)
Kojto 122:f9eeca106725 6922 #define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 6923 #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
Kojto 122:f9eeca106725 6924 #define FLASH_SR_OPTVERR_Pos (15U)
Kojto 122:f9eeca106725 6925 #define FLASH_SR_OPTVERR_Msk (0x1U << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 6926 #define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk
Kojto 122:f9eeca106725 6927 #define FLASH_SR_BSY_Pos (16U)
Kojto 122:f9eeca106725 6928 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 6929 #define FLASH_SR_BSY FLASH_SR_BSY_Msk
Kojto 122:f9eeca106725 6930 #define FLASH_SR_PEMPTY_Pos (17U)
Kojto 122:f9eeca106725 6931 #define FLASH_SR_PEMPTY_Msk (0x1U << FLASH_SR_PEMPTY_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 6932 #define FLASH_SR_PEMPTY FLASH_SR_PEMPTY_Msk
Kojto 122:f9eeca106725 6933
Kojto 122:f9eeca106725 6934 /******************* Bits definition for FLASH_CR register ******************/
Kojto 122:f9eeca106725 6935 #define FLASH_CR_PG_Pos (0U)
Kojto 122:f9eeca106725 6936 #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 6937 #define FLASH_CR_PG FLASH_CR_PG_Msk
Kojto 122:f9eeca106725 6938 #define FLASH_CR_PER_Pos (1U)
Kojto 122:f9eeca106725 6939 #define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 6940 #define FLASH_CR_PER FLASH_CR_PER_Msk
Kojto 122:f9eeca106725 6941 #define FLASH_CR_MER1_Pos (2U)
Kojto 122:f9eeca106725 6942 #define FLASH_CR_MER1_Msk (0x1U << FLASH_CR_MER1_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 6943 #define FLASH_CR_MER1 FLASH_CR_MER1_Msk
Kojto 122:f9eeca106725 6944 #define FLASH_CR_PNB_Pos (3U)
Kojto 122:f9eeca106725 6945 #define FLASH_CR_PNB_Msk (0xFFU << FLASH_CR_PNB_Pos) /*!< 0x000007F8 */
Kojto 122:f9eeca106725 6946 #define FLASH_CR_PNB FLASH_CR_PNB_Msk
Kojto 122:f9eeca106725 6947 #define FLASH_CR_STRT_Pos (16U)
Kojto 122:f9eeca106725 6948 #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 6949 #define FLASH_CR_STRT FLASH_CR_STRT_Msk
Kojto 122:f9eeca106725 6950 #define FLASH_CR_OPTSTRT_Pos (17U)
Kojto 122:f9eeca106725 6951 #define FLASH_CR_OPTSTRT_Msk (0x1U << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 6952 #define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk
Kojto 122:f9eeca106725 6953 #define FLASH_CR_FSTPG_Pos (18U)
Kojto 122:f9eeca106725 6954 #define FLASH_CR_FSTPG_Msk (0x1U << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 6955 #define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk
Kojto 122:f9eeca106725 6956 #define FLASH_CR_EOPIE_Pos (24U)
Kojto 122:f9eeca106725 6957 #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 6958 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
Kojto 122:f9eeca106725 6959 #define FLASH_CR_ERRIE_Pos (25U)
Kojto 122:f9eeca106725 6960 #define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 6961 #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
Kojto 122:f9eeca106725 6962 #define FLASH_CR_RDERRIE_Pos (26U)
Kojto 122:f9eeca106725 6963 #define FLASH_CR_RDERRIE_Msk (0x1U << FLASH_CR_RDERRIE_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 6964 #define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk
Kojto 122:f9eeca106725 6965 #define FLASH_CR_OBL_LAUNCH_Pos (27U)
Kojto 122:f9eeca106725 6966 #define FLASH_CR_OBL_LAUNCH_Msk (0x1U << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 6967 #define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk
Kojto 122:f9eeca106725 6968 #define FLASH_CR_OPTLOCK_Pos (30U)
Kojto 122:f9eeca106725 6969 #define FLASH_CR_OPTLOCK_Msk (0x1U << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 6970 #define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk
Kojto 122:f9eeca106725 6971 #define FLASH_CR_LOCK_Pos (31U)
Kojto 122:f9eeca106725 6972 #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 6973 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
Kojto 122:f9eeca106725 6974
Kojto 122:f9eeca106725 6975 /******************* Bits definition for FLASH_ECCR register ***************/
Kojto 122:f9eeca106725 6976 #define FLASH_ECCR_ADDR_ECC_Pos (0U)
Kojto 122:f9eeca106725 6977 #define FLASH_ECCR_ADDR_ECC_Msk (0x7FFFFU << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0007FFFF */
Kojto 122:f9eeca106725 6978 #define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk
Kojto 122:f9eeca106725 6979 #define FLASH_ECCR_SYSF_ECC_Pos (20U)
Kojto 122:f9eeca106725 6980 #define FLASH_ECCR_SYSF_ECC_Msk (0x1U << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 6981 #define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk
Kojto 122:f9eeca106725 6982 #define FLASH_ECCR_ECCIE_Pos (24U)
Kojto 122:f9eeca106725 6983 #define FLASH_ECCR_ECCIE_Msk (0x1U << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 6984 #define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk
Kojto 122:f9eeca106725 6985 #define FLASH_ECCR_ECCC_Pos (30U)
Kojto 122:f9eeca106725 6986 #define FLASH_ECCR_ECCC_Msk (0x1U << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 6987 #define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk
Kojto 122:f9eeca106725 6988 #define FLASH_ECCR_ECCD_Pos (31U)
Kojto 122:f9eeca106725 6989 #define FLASH_ECCR_ECCD_Msk (0x1U << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 6990 #define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk
Kojto 122:f9eeca106725 6991
Kojto 122:f9eeca106725 6992 /******************* Bits definition for FLASH_OPTR register ***************/
Kojto 122:f9eeca106725 6993 #define FLASH_OPTR_RDP_Pos (0U)
Kojto 122:f9eeca106725 6994 #define FLASH_OPTR_RDP_Msk (0xFFU << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 6995 #define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk
Kojto 122:f9eeca106725 6996 #define FLASH_OPTR_BOR_LEV_Pos (8U)
Kojto 122:f9eeca106725 6997 #define FLASH_OPTR_BOR_LEV_Msk (0x7U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */
Kojto 122:f9eeca106725 6998 #define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk
Kojto 122:f9eeca106725 6999 #define FLASH_OPTR_BOR_LEV_0 (0x0U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000000 */
Kojto 122:f9eeca106725 7000 #define FLASH_OPTR_BOR_LEV_1 (0x1U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 7001 #define FLASH_OPTR_BOR_LEV_2 (0x2U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 7002 #define FLASH_OPTR_BOR_LEV_3 (0x3U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 7003 #define FLASH_OPTR_BOR_LEV_4 (0x4U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 7004 #define FLASH_OPTR_nRST_STOP_Pos (12U)
Kojto 122:f9eeca106725 7005 #define FLASH_OPTR_nRST_STOP_Msk (0x1U << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 7006 #define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk
Kojto 122:f9eeca106725 7007 #define FLASH_OPTR_nRST_STDBY_Pos (13U)
Kojto 122:f9eeca106725 7008 #define FLASH_OPTR_nRST_STDBY_Msk (0x1U << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 7009 #define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk
Kojto 122:f9eeca106725 7010 #define FLASH_OPTR_nRST_SHDW_Pos (14U)
Kojto 122:f9eeca106725 7011 #define FLASH_OPTR_nRST_SHDW_Msk (0x1U << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 7012 #define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk
Kojto 122:f9eeca106725 7013 #define FLASH_OPTR_IWDG_SW_Pos (16U)
Kojto 122:f9eeca106725 7014 #define FLASH_OPTR_IWDG_SW_Msk (0x1U << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 7015 #define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk
Kojto 122:f9eeca106725 7016 #define FLASH_OPTR_IWDG_STOP_Pos (17U)
Kojto 122:f9eeca106725 7017 #define FLASH_OPTR_IWDG_STOP_Msk (0x1U << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 7018 #define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk
Kojto 122:f9eeca106725 7019 #define FLASH_OPTR_IWDG_STDBY_Pos (18U)
Kojto 122:f9eeca106725 7020 #define FLASH_OPTR_IWDG_STDBY_Msk (0x1U << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 7021 #define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk
Kojto 122:f9eeca106725 7022 #define FLASH_OPTR_WWDG_SW_Pos (19U)
Kojto 122:f9eeca106725 7023 #define FLASH_OPTR_WWDG_SW_Msk (0x1U << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 7024 #define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk
Kojto 122:f9eeca106725 7025 #define FLASH_OPTR_nBOOT1_Pos (23U)
Kojto 122:f9eeca106725 7026 #define FLASH_OPTR_nBOOT1_Msk (0x1U << FLASH_OPTR_nBOOT1_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 7027 #define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk
Kojto 122:f9eeca106725 7028 #define FLASH_OPTR_SRAM2_PE_Pos (24U)
Kojto 122:f9eeca106725 7029 #define FLASH_OPTR_SRAM2_PE_Msk (0x1U << FLASH_OPTR_SRAM2_PE_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 7030 #define FLASH_OPTR_SRAM2_PE FLASH_OPTR_SRAM2_PE_Msk
Kojto 122:f9eeca106725 7031 #define FLASH_OPTR_SRAM2_RST_Pos (25U)
Kojto 122:f9eeca106725 7032 #define FLASH_OPTR_SRAM2_RST_Msk (0x1U << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 7033 #define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk
Kojto 122:f9eeca106725 7034 #define FLASH_OPTR_nSWBOOT0_Pos (26U)
Kojto 122:f9eeca106725 7035 #define FLASH_OPTR_nSWBOOT0_Msk (0x1U << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 7036 #define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk
Kojto 122:f9eeca106725 7037 #define FLASH_OPTR_nBOOT0_Pos (27U)
Kojto 122:f9eeca106725 7038 #define FLASH_OPTR_nBOOT0_Msk (0x1U << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 7039 #define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk
Kojto 122:f9eeca106725 7040
Kojto 122:f9eeca106725 7041 /****************** Bits definition for FLASH_PCROP1SR register **********/
Kojto 122:f9eeca106725 7042 #define FLASH_PCROP1SR_PCROP1_STRT_Pos (0U)
Kojto 122:f9eeca106725 7043 #define FLASH_PCROP1SR_PCROP1_STRT_Msk (0xFFFFU << FLASH_PCROP1SR_PCROP1_STRT_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 7044 #define FLASH_PCROP1SR_PCROP1_STRT FLASH_PCROP1SR_PCROP1_STRT_Msk
Kojto 122:f9eeca106725 7045
Kojto 122:f9eeca106725 7046 /****************** Bits definition for FLASH_PCROP1ER register ***********/
Kojto 122:f9eeca106725 7047 #define FLASH_PCROP1ER_PCROP1_END_Pos (0U)
Kojto 122:f9eeca106725 7048 #define FLASH_PCROP1ER_PCROP1_END_Msk (0xFFFFU << FLASH_PCROP1ER_PCROP1_END_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 7049 #define FLASH_PCROP1ER_PCROP1_END FLASH_PCROP1ER_PCROP1_END_Msk
Kojto 122:f9eeca106725 7050 #define FLASH_PCROP1ER_PCROP_RDP_Pos (31U)
Kojto 122:f9eeca106725 7051 #define FLASH_PCROP1ER_PCROP_RDP_Msk (0x1U << FLASH_PCROP1ER_PCROP_RDP_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 7052 #define FLASH_PCROP1ER_PCROP_RDP FLASH_PCROP1ER_PCROP_RDP_Msk
Kojto 122:f9eeca106725 7053
Kojto 122:f9eeca106725 7054 /****************** Bits definition for FLASH_WRP1AR register ***************/
Kojto 122:f9eeca106725 7055 #define FLASH_WRP1AR_WRP1A_STRT_Pos (0U)
Kojto 122:f9eeca106725 7056 #define FLASH_WRP1AR_WRP1A_STRT_Msk (0xFFU << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 7057 #define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk
Kojto 122:f9eeca106725 7058 #define FLASH_WRP1AR_WRP1A_END_Pos (16U)
Kojto 122:f9eeca106725 7059 #define FLASH_WRP1AR_WRP1A_END_Msk (0xFFU << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 7060 #define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk
Kojto 122:f9eeca106725 7061
Kojto 122:f9eeca106725 7062 /****************** Bits definition for FLASH_WRPB1R register ***************/
Kojto 122:f9eeca106725 7063 #define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)
Kojto 122:f9eeca106725 7064 #define FLASH_WRP1BR_WRP1B_STRT_Msk (0xFFU << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 7065 #define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk
Kojto 122:f9eeca106725 7066 #define FLASH_WRP1BR_WRP1B_END_Pos (16U)
Kojto 122:f9eeca106725 7067 #define FLASH_WRP1BR_WRP1B_END_Msk (0xFFU << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 7068 #define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk
Kojto 122:f9eeca106725 7069
Kojto 122:f9eeca106725 7070
Kojto 122:f9eeca106725 7071
Kojto 122:f9eeca106725 7072
Kojto 122:f9eeca106725 7073 /******************************************************************************/
Kojto 122:f9eeca106725 7074 /* */
Kojto 122:f9eeca106725 7075 /* General Purpose IOs (GPIO) */
Kojto 122:f9eeca106725 7076 /* */
Kojto 122:f9eeca106725 7077 /******************************************************************************/
Kojto 122:f9eeca106725 7078 /****************** Bits definition for GPIO_MODER register *****************/
Kojto 122:f9eeca106725 7079 #define GPIO_MODER_MODE0_Pos (0U)
Kojto 122:f9eeca106725 7080 #define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 7081 #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
Kojto 122:f9eeca106725 7082 #define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 7083 #define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 7084 #define GPIO_MODER_MODE1_Pos (2U)
Kojto 122:f9eeca106725 7085 #define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
Kojto 122:f9eeca106725 7086 #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
Kojto 122:f9eeca106725 7087 #define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 7088 #define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 7089 #define GPIO_MODER_MODE2_Pos (4U)
Kojto 122:f9eeca106725 7090 #define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
Kojto 122:f9eeca106725 7091 #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
Kojto 122:f9eeca106725 7092 #define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 7093 #define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 7094 #define GPIO_MODER_MODE3_Pos (6U)
Kojto 122:f9eeca106725 7095 #define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
Kojto 122:f9eeca106725 7096 #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
Kojto 122:f9eeca106725 7097 #define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 7098 #define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 7099 #define GPIO_MODER_MODE4_Pos (8U)
Kojto 122:f9eeca106725 7100 #define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 7101 #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
Kojto 122:f9eeca106725 7102 #define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 7103 #define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 7104 #define GPIO_MODER_MODE5_Pos (10U)
Kojto 122:f9eeca106725 7105 #define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
Kojto 122:f9eeca106725 7106 #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
Kojto 122:f9eeca106725 7107 #define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 7108 #define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 7109 #define GPIO_MODER_MODE6_Pos (12U)
Kojto 122:f9eeca106725 7110 #define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
Kojto 122:f9eeca106725 7111 #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
Kojto 122:f9eeca106725 7112 #define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 7113 #define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 7114 #define GPIO_MODER_MODE7_Pos (14U)
Kojto 122:f9eeca106725 7115 #define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
Kojto 122:f9eeca106725 7116 #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
Kojto 122:f9eeca106725 7117 #define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 7118 #define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 7119 #define GPIO_MODER_MODE8_Pos (16U)
Kojto 122:f9eeca106725 7120 #define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
Kojto 122:f9eeca106725 7121 #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
Kojto 122:f9eeca106725 7122 #define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 7123 #define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 7124 #define GPIO_MODER_MODE9_Pos (18U)
Kojto 122:f9eeca106725 7125 #define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
Kojto 122:f9eeca106725 7126 #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
Kojto 122:f9eeca106725 7127 #define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 7128 #define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 7129 #define GPIO_MODER_MODE10_Pos (20U)
Kojto 122:f9eeca106725 7130 #define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
Kojto 122:f9eeca106725 7131 #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
Kojto 122:f9eeca106725 7132 #define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 7133 #define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 7134 #define GPIO_MODER_MODE11_Pos (22U)
Kojto 122:f9eeca106725 7135 #define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
Kojto 122:f9eeca106725 7136 #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
Kojto 122:f9eeca106725 7137 #define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 7138 #define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 7139 #define GPIO_MODER_MODE12_Pos (24U)
Kojto 122:f9eeca106725 7140 #define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
Kojto 122:f9eeca106725 7141 #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
Kojto 122:f9eeca106725 7142 #define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 7143 #define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 7144 #define GPIO_MODER_MODE13_Pos (26U)
Kojto 122:f9eeca106725 7145 #define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
Kojto 122:f9eeca106725 7146 #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
Kojto 122:f9eeca106725 7147 #define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 7148 #define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 7149 #define GPIO_MODER_MODE14_Pos (28U)
Kojto 122:f9eeca106725 7150 #define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
Kojto 122:f9eeca106725 7151 #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
Kojto 122:f9eeca106725 7152 #define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 7153 #define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 7154 #define GPIO_MODER_MODE15_Pos (30U)
Kojto 122:f9eeca106725 7155 #define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
Kojto 122:f9eeca106725 7156 #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
Kojto 122:f9eeca106725 7157 #define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 7158 #define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 7159
Kojto 122:f9eeca106725 7160 /* Legacy defines */
Kojto 122:f9eeca106725 7161 #define GPIO_MODER_MODER0 GPIO_MODER_MODE0
Kojto 122:f9eeca106725 7162 #define GPIO_MODER_MODER0_0 GPIO_MODER_MODE0_0
Kojto 122:f9eeca106725 7163 #define GPIO_MODER_MODER0_1 GPIO_MODER_MODE0_1
Kojto 122:f9eeca106725 7164 #define GPIO_MODER_MODER1 GPIO_MODER_MODE1
Kojto 122:f9eeca106725 7165 #define GPIO_MODER_MODER1_0 GPIO_MODER_MODE1_0
Kojto 122:f9eeca106725 7166 #define GPIO_MODER_MODER1_1 GPIO_MODER_MODE1_1
Kojto 122:f9eeca106725 7167 #define GPIO_MODER_MODER2 GPIO_MODER_MODE2
Kojto 122:f9eeca106725 7168 #define GPIO_MODER_MODER2_0 GPIO_MODER_MODE2_0
Kojto 122:f9eeca106725 7169 #define GPIO_MODER_MODER2_1 GPIO_MODER_MODE2_1
Kojto 122:f9eeca106725 7170 #define GPIO_MODER_MODER3 GPIO_MODER_MODE3
Kojto 122:f9eeca106725 7171 #define GPIO_MODER_MODER3_0 GPIO_MODER_MODE3_0
Kojto 122:f9eeca106725 7172 #define GPIO_MODER_MODER3_1 GPIO_MODER_MODE3_1
Kojto 122:f9eeca106725 7173 #define GPIO_MODER_MODER4 GPIO_MODER_MODE4
Kojto 122:f9eeca106725 7174 #define GPIO_MODER_MODER4_0 GPIO_MODER_MODE4_0
Kojto 122:f9eeca106725 7175 #define GPIO_MODER_MODER4_1 GPIO_MODER_MODE4_1
Kojto 122:f9eeca106725 7176 #define GPIO_MODER_MODER5 GPIO_MODER_MODE5
Kojto 122:f9eeca106725 7177 #define GPIO_MODER_MODER5_0 GPIO_MODER_MODE5_0
Kojto 122:f9eeca106725 7178 #define GPIO_MODER_MODER5_1 GPIO_MODER_MODE5_1
Kojto 122:f9eeca106725 7179 #define GPIO_MODER_MODER6 GPIO_MODER_MODE6
Kojto 122:f9eeca106725 7180 #define GPIO_MODER_MODER6_0 GPIO_MODER_MODE6_0
Kojto 122:f9eeca106725 7181 #define GPIO_MODER_MODER6_1 GPIO_MODER_MODE6_1
Kojto 122:f9eeca106725 7182 #define GPIO_MODER_MODER7 GPIO_MODER_MODE7
Kojto 122:f9eeca106725 7183 #define GPIO_MODER_MODER7_0 GPIO_MODER_MODE7_0
Kojto 122:f9eeca106725 7184 #define GPIO_MODER_MODER7_1 GPIO_MODER_MODE7_1
Kojto 122:f9eeca106725 7185 #define GPIO_MODER_MODER8 GPIO_MODER_MODE8
Kojto 122:f9eeca106725 7186 #define GPIO_MODER_MODER8_0 GPIO_MODER_MODE8_0
Kojto 122:f9eeca106725 7187 #define GPIO_MODER_MODER8_1 GPIO_MODER_MODE8_1
Kojto 122:f9eeca106725 7188 #define GPIO_MODER_MODER9 GPIO_MODER_MODE9
Kojto 122:f9eeca106725 7189 #define GPIO_MODER_MODER9_0 GPIO_MODER_MODE9_0
Kojto 122:f9eeca106725 7190 #define GPIO_MODER_MODER9_1 GPIO_MODER_MODE9_1
Kojto 122:f9eeca106725 7191 #define GPIO_MODER_MODER10 GPIO_MODER_MODE10
Kojto 122:f9eeca106725 7192 #define GPIO_MODER_MODER10_0 GPIO_MODER_MODE10_0
Kojto 122:f9eeca106725 7193 #define GPIO_MODER_MODER10_1 GPIO_MODER_MODE10_1
Kojto 122:f9eeca106725 7194 #define GPIO_MODER_MODER11 GPIO_MODER_MODE11
Kojto 122:f9eeca106725 7195 #define GPIO_MODER_MODER11_0 GPIO_MODER_MODE11_0
Kojto 122:f9eeca106725 7196 #define GPIO_MODER_MODER11_1 GPIO_MODER_MODE11_1
Kojto 122:f9eeca106725 7197 #define GPIO_MODER_MODER12 GPIO_MODER_MODE12
Kojto 122:f9eeca106725 7198 #define GPIO_MODER_MODER12_0 GPIO_MODER_MODE12_0
Kojto 122:f9eeca106725 7199 #define GPIO_MODER_MODER12_1 GPIO_MODER_MODE12_1
Kojto 122:f9eeca106725 7200 #define GPIO_MODER_MODER13 GPIO_MODER_MODE13
Kojto 122:f9eeca106725 7201 #define GPIO_MODER_MODER13_0 GPIO_MODER_MODE13_0
Kojto 122:f9eeca106725 7202 #define GPIO_MODER_MODER13_1 GPIO_MODER_MODE13_1
Kojto 122:f9eeca106725 7203 #define GPIO_MODER_MODER14 GPIO_MODER_MODE14
Kojto 122:f9eeca106725 7204 #define GPIO_MODER_MODER14_0 GPIO_MODER_MODE14_0
Kojto 122:f9eeca106725 7205 #define GPIO_MODER_MODER14_1 GPIO_MODER_MODE14_1
Kojto 122:f9eeca106725 7206 #define GPIO_MODER_MODER15 GPIO_MODER_MODE15
Kojto 122:f9eeca106725 7207 #define GPIO_MODER_MODER15_0 GPIO_MODER_MODE15_0
Kojto 122:f9eeca106725 7208 #define GPIO_MODER_MODER15_1 GPIO_MODER_MODE15_1
Kojto 122:f9eeca106725 7209
Kojto 122:f9eeca106725 7210 /****************** Bits definition for GPIO_OTYPER register ****************/
Kojto 122:f9eeca106725 7211 #define GPIO_OTYPER_OT0_Pos (0U)
Kojto 122:f9eeca106725 7212 #define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 7213 #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
Kojto 122:f9eeca106725 7214 #define GPIO_OTYPER_OT1_Pos (1U)
Kojto 122:f9eeca106725 7215 #define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 7216 #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
Kojto 122:f9eeca106725 7217 #define GPIO_OTYPER_OT2_Pos (2U)
Kojto 122:f9eeca106725 7218 #define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 7219 #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
Kojto 122:f9eeca106725 7220 #define GPIO_OTYPER_OT3_Pos (3U)
Kojto 122:f9eeca106725 7221 #define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 7222 #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
Kojto 122:f9eeca106725 7223 #define GPIO_OTYPER_OT4_Pos (4U)
Kojto 122:f9eeca106725 7224 #define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 7225 #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
Kojto 122:f9eeca106725 7226 #define GPIO_OTYPER_OT5_Pos (5U)
Kojto 122:f9eeca106725 7227 #define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 7228 #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
Kojto 122:f9eeca106725 7229 #define GPIO_OTYPER_OT6_Pos (6U)
Kojto 122:f9eeca106725 7230 #define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 7231 #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
Kojto 122:f9eeca106725 7232 #define GPIO_OTYPER_OT7_Pos (7U)
Kojto 122:f9eeca106725 7233 #define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 7234 #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
Kojto 122:f9eeca106725 7235 #define GPIO_OTYPER_OT8_Pos (8U)
Kojto 122:f9eeca106725 7236 #define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 7237 #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
Kojto 122:f9eeca106725 7238 #define GPIO_OTYPER_OT9_Pos (9U)
Kojto 122:f9eeca106725 7239 #define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 7240 #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
Kojto 122:f9eeca106725 7241 #define GPIO_OTYPER_OT10_Pos (10U)
Kojto 122:f9eeca106725 7242 #define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 7243 #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
Kojto 122:f9eeca106725 7244 #define GPIO_OTYPER_OT11_Pos (11U)
Kojto 122:f9eeca106725 7245 #define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 7246 #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
Kojto 122:f9eeca106725 7247 #define GPIO_OTYPER_OT12_Pos (12U)
Kojto 122:f9eeca106725 7248 #define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 7249 #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
Kojto 122:f9eeca106725 7250 #define GPIO_OTYPER_OT13_Pos (13U)
Kojto 122:f9eeca106725 7251 #define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 7252 #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
Kojto 122:f9eeca106725 7253 #define GPIO_OTYPER_OT14_Pos (14U)
Kojto 122:f9eeca106725 7254 #define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 7255 #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
Kojto 122:f9eeca106725 7256 #define GPIO_OTYPER_OT15_Pos (15U)
Kojto 122:f9eeca106725 7257 #define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 7258 #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
Kojto 122:f9eeca106725 7259
Kojto 122:f9eeca106725 7260 /* Legacy defines */
Kojto 122:f9eeca106725 7261 #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
Kojto 122:f9eeca106725 7262 #define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
Kojto 122:f9eeca106725 7263 #define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
Kojto 122:f9eeca106725 7264 #define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
Kojto 122:f9eeca106725 7265 #define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
Kojto 122:f9eeca106725 7266 #define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
Kojto 122:f9eeca106725 7267 #define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
Kojto 122:f9eeca106725 7268 #define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
Kojto 122:f9eeca106725 7269 #define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
Kojto 122:f9eeca106725 7270 #define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
Kojto 122:f9eeca106725 7271 #define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
Kojto 122:f9eeca106725 7272 #define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
Kojto 122:f9eeca106725 7273 #define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
Kojto 122:f9eeca106725 7274 #define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
Kojto 122:f9eeca106725 7275 #define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
Kojto 122:f9eeca106725 7276 #define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
Kojto 122:f9eeca106725 7277
Kojto 122:f9eeca106725 7278 /****************** Bits definition for GPIO_OSPEEDR register ***************/
Kojto 122:f9eeca106725 7279 #define GPIO_OSPEEDR_OSPEED0_Pos (0U)
Kojto 122:f9eeca106725 7280 #define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 7281 #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
Kojto 122:f9eeca106725 7282 #define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 7283 #define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 7284 #define GPIO_OSPEEDR_OSPEED1_Pos (2U)
Kojto 122:f9eeca106725 7285 #define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
Kojto 122:f9eeca106725 7286 #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
Kojto 122:f9eeca106725 7287 #define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 7288 #define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 7289 #define GPIO_OSPEEDR_OSPEED2_Pos (4U)
Kojto 122:f9eeca106725 7290 #define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
Kojto 122:f9eeca106725 7291 #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
Kojto 122:f9eeca106725 7292 #define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 7293 #define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 7294 #define GPIO_OSPEEDR_OSPEED3_Pos (6U)
Kojto 122:f9eeca106725 7295 #define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
Kojto 122:f9eeca106725 7296 #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
Kojto 122:f9eeca106725 7297 #define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 7298 #define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 7299 #define GPIO_OSPEEDR_OSPEED4_Pos (8U)
Kojto 122:f9eeca106725 7300 #define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 7301 #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
Kojto 122:f9eeca106725 7302 #define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 7303 #define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 7304 #define GPIO_OSPEEDR_OSPEED5_Pos (10U)
Kojto 122:f9eeca106725 7305 #define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
Kojto 122:f9eeca106725 7306 #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
Kojto 122:f9eeca106725 7307 #define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 7308 #define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 7309 #define GPIO_OSPEEDR_OSPEED6_Pos (12U)
Kojto 122:f9eeca106725 7310 #define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
Kojto 122:f9eeca106725 7311 #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
Kojto 122:f9eeca106725 7312 #define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 7313 #define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 7314 #define GPIO_OSPEEDR_OSPEED7_Pos (14U)
Kojto 122:f9eeca106725 7315 #define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
Kojto 122:f9eeca106725 7316 #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
Kojto 122:f9eeca106725 7317 #define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 7318 #define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 7319 #define GPIO_OSPEEDR_OSPEED8_Pos (16U)
Kojto 122:f9eeca106725 7320 #define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
Kojto 122:f9eeca106725 7321 #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
Kojto 122:f9eeca106725 7322 #define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 7323 #define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 7324 #define GPIO_OSPEEDR_OSPEED9_Pos (18U)
Kojto 122:f9eeca106725 7325 #define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
Kojto 122:f9eeca106725 7326 #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
Kojto 122:f9eeca106725 7327 #define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 7328 #define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 7329 #define GPIO_OSPEEDR_OSPEED10_Pos (20U)
Kojto 122:f9eeca106725 7330 #define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
Kojto 122:f9eeca106725 7331 #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
Kojto 122:f9eeca106725 7332 #define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 7333 #define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 7334 #define GPIO_OSPEEDR_OSPEED11_Pos (22U)
Kojto 122:f9eeca106725 7335 #define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
Kojto 122:f9eeca106725 7336 #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
Kojto 122:f9eeca106725 7337 #define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 7338 #define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 7339 #define GPIO_OSPEEDR_OSPEED12_Pos (24U)
Kojto 122:f9eeca106725 7340 #define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
Kojto 122:f9eeca106725 7341 #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
Kojto 122:f9eeca106725 7342 #define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 7343 #define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 7344 #define GPIO_OSPEEDR_OSPEED13_Pos (26U)
Kojto 122:f9eeca106725 7345 #define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
Kojto 122:f9eeca106725 7346 #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
Kojto 122:f9eeca106725 7347 #define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 7348 #define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 7349 #define GPIO_OSPEEDR_OSPEED14_Pos (28U)
Kojto 122:f9eeca106725 7350 #define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
Kojto 122:f9eeca106725 7351 #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
Kojto 122:f9eeca106725 7352 #define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 7353 #define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 7354 #define GPIO_OSPEEDR_OSPEED15_Pos (30U)
Kojto 122:f9eeca106725 7355 #define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
Kojto 122:f9eeca106725 7356 #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
Kojto 122:f9eeca106725 7357 #define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 7358 #define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 7359
Kojto 122:f9eeca106725 7360 /* Legacy defines */
Kojto 122:f9eeca106725 7361 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
Kojto 122:f9eeca106725 7362 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
Kojto 122:f9eeca106725 7363 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
Kojto 122:f9eeca106725 7364 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
Kojto 122:f9eeca106725 7365 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
Kojto 122:f9eeca106725 7366 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
Kojto 122:f9eeca106725 7367 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
Kojto 122:f9eeca106725 7368 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
Kojto 122:f9eeca106725 7369 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
Kojto 122:f9eeca106725 7370 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
Kojto 122:f9eeca106725 7371 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
Kojto 122:f9eeca106725 7372 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
Kojto 122:f9eeca106725 7373 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
Kojto 122:f9eeca106725 7374 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
Kojto 122:f9eeca106725 7375 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
Kojto 122:f9eeca106725 7376 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
Kojto 122:f9eeca106725 7377 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
Kojto 122:f9eeca106725 7378 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
Kojto 122:f9eeca106725 7379 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
Kojto 122:f9eeca106725 7380 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
Kojto 122:f9eeca106725 7381 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
Kojto 122:f9eeca106725 7382 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
Kojto 122:f9eeca106725 7383 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
Kojto 122:f9eeca106725 7384 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
Kojto 122:f9eeca106725 7385 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
Kojto 122:f9eeca106725 7386 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
Kojto 122:f9eeca106725 7387 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
Kojto 122:f9eeca106725 7388 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
Kojto 122:f9eeca106725 7389 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
Kojto 122:f9eeca106725 7390 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
Kojto 122:f9eeca106725 7391 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
Kojto 122:f9eeca106725 7392 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
Kojto 122:f9eeca106725 7393 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
Kojto 122:f9eeca106725 7394 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
Kojto 122:f9eeca106725 7395 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
Kojto 122:f9eeca106725 7396 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
Kojto 122:f9eeca106725 7397 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
Kojto 122:f9eeca106725 7398 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
Kojto 122:f9eeca106725 7399 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
Kojto 122:f9eeca106725 7400 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
Kojto 122:f9eeca106725 7401 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
Kojto 122:f9eeca106725 7402 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
Kojto 122:f9eeca106725 7403 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
Kojto 122:f9eeca106725 7404 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
Kojto 122:f9eeca106725 7405 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
Kojto 122:f9eeca106725 7406 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
Kojto 122:f9eeca106725 7407 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
Kojto 122:f9eeca106725 7408 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
Kojto 122:f9eeca106725 7409
Kojto 122:f9eeca106725 7410 /****************** Bits definition for GPIO_PUPDR register *****************/
Kojto 122:f9eeca106725 7411 #define GPIO_PUPDR_PUPD0_Pos (0U)
Kojto 122:f9eeca106725 7412 #define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 7413 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
Kojto 122:f9eeca106725 7414 #define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 7415 #define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 7416 #define GPIO_PUPDR_PUPD1_Pos (2U)
Kojto 122:f9eeca106725 7417 #define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
Kojto 122:f9eeca106725 7418 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
Kojto 122:f9eeca106725 7419 #define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 7420 #define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 7421 #define GPIO_PUPDR_PUPD2_Pos (4U)
Kojto 122:f9eeca106725 7422 #define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
Kojto 122:f9eeca106725 7423 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
Kojto 122:f9eeca106725 7424 #define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 7425 #define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 7426 #define GPIO_PUPDR_PUPD3_Pos (6U)
Kojto 122:f9eeca106725 7427 #define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
Kojto 122:f9eeca106725 7428 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
Kojto 122:f9eeca106725 7429 #define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 7430 #define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 7431 #define GPIO_PUPDR_PUPD4_Pos (8U)
Kojto 122:f9eeca106725 7432 #define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 7433 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
Kojto 122:f9eeca106725 7434 #define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 7435 #define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 7436 #define GPIO_PUPDR_PUPD5_Pos (10U)
Kojto 122:f9eeca106725 7437 #define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
Kojto 122:f9eeca106725 7438 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
Kojto 122:f9eeca106725 7439 #define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 7440 #define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 7441 #define GPIO_PUPDR_PUPD6_Pos (12U)
Kojto 122:f9eeca106725 7442 #define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
Kojto 122:f9eeca106725 7443 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
Kojto 122:f9eeca106725 7444 #define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 7445 #define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 7446 #define GPIO_PUPDR_PUPD7_Pos (14U)
Kojto 122:f9eeca106725 7447 #define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
Kojto 122:f9eeca106725 7448 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
Kojto 122:f9eeca106725 7449 #define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 7450 #define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 7451 #define GPIO_PUPDR_PUPD8_Pos (16U)
Kojto 122:f9eeca106725 7452 #define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
Kojto 122:f9eeca106725 7453 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
Kojto 122:f9eeca106725 7454 #define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 7455 #define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 7456 #define GPIO_PUPDR_PUPD9_Pos (18U)
Kojto 122:f9eeca106725 7457 #define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
Kojto 122:f9eeca106725 7458 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
Kojto 122:f9eeca106725 7459 #define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 7460 #define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 7461 #define GPIO_PUPDR_PUPD10_Pos (20U)
Kojto 122:f9eeca106725 7462 #define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
Kojto 122:f9eeca106725 7463 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
Kojto 122:f9eeca106725 7464 #define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 7465 #define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 7466 #define GPIO_PUPDR_PUPD11_Pos (22U)
Kojto 122:f9eeca106725 7467 #define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
Kojto 122:f9eeca106725 7468 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
Kojto 122:f9eeca106725 7469 #define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 7470 #define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 7471 #define GPIO_PUPDR_PUPD12_Pos (24U)
Kojto 122:f9eeca106725 7472 #define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
Kojto 122:f9eeca106725 7473 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
Kojto 122:f9eeca106725 7474 #define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 7475 #define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 7476 #define GPIO_PUPDR_PUPD13_Pos (26U)
Kojto 122:f9eeca106725 7477 #define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
Kojto 122:f9eeca106725 7478 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
Kojto 122:f9eeca106725 7479 #define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 7480 #define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 7481 #define GPIO_PUPDR_PUPD14_Pos (28U)
Kojto 122:f9eeca106725 7482 #define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
Kojto 122:f9eeca106725 7483 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
Kojto 122:f9eeca106725 7484 #define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 7485 #define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 7486 #define GPIO_PUPDR_PUPD15_Pos (30U)
Kojto 122:f9eeca106725 7487 #define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
Kojto 122:f9eeca106725 7488 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
Kojto 122:f9eeca106725 7489 #define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 7490 #define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 7491
Kojto 122:f9eeca106725 7492 /* Legacy defines */
Kojto 122:f9eeca106725 7493 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
Kojto 122:f9eeca106725 7494 #define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
Kojto 122:f9eeca106725 7495 #define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
Kojto 122:f9eeca106725 7496 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
Kojto 122:f9eeca106725 7497 #define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
Kojto 122:f9eeca106725 7498 #define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
Kojto 122:f9eeca106725 7499 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
Kojto 122:f9eeca106725 7500 #define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
Kojto 122:f9eeca106725 7501 #define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
Kojto 122:f9eeca106725 7502 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
Kojto 122:f9eeca106725 7503 #define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
Kojto 122:f9eeca106725 7504 #define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
Kojto 122:f9eeca106725 7505 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
Kojto 122:f9eeca106725 7506 #define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
Kojto 122:f9eeca106725 7507 #define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
Kojto 122:f9eeca106725 7508 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
Kojto 122:f9eeca106725 7509 #define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
Kojto 122:f9eeca106725 7510 #define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
Kojto 122:f9eeca106725 7511 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
Kojto 122:f9eeca106725 7512 #define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
Kojto 122:f9eeca106725 7513 #define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
Kojto 122:f9eeca106725 7514 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
Kojto 122:f9eeca106725 7515 #define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
Kojto 122:f9eeca106725 7516 #define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
Kojto 122:f9eeca106725 7517 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
Kojto 122:f9eeca106725 7518 #define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
Kojto 122:f9eeca106725 7519 #define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
Kojto 122:f9eeca106725 7520 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
Kojto 122:f9eeca106725 7521 #define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
Kojto 122:f9eeca106725 7522 #define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
Kojto 122:f9eeca106725 7523 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
Kojto 122:f9eeca106725 7524 #define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
Kojto 122:f9eeca106725 7525 #define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
Kojto 122:f9eeca106725 7526 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
Kojto 122:f9eeca106725 7527 #define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
Kojto 122:f9eeca106725 7528 #define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
Kojto 122:f9eeca106725 7529 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
Kojto 122:f9eeca106725 7530 #define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
Kojto 122:f9eeca106725 7531 #define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
Kojto 122:f9eeca106725 7532 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
Kojto 122:f9eeca106725 7533 #define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
Kojto 122:f9eeca106725 7534 #define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
Kojto 122:f9eeca106725 7535 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
Kojto 122:f9eeca106725 7536 #define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
Kojto 122:f9eeca106725 7537 #define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
Kojto 122:f9eeca106725 7538 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
Kojto 122:f9eeca106725 7539 #define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
Kojto 122:f9eeca106725 7540 #define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
Kojto 122:f9eeca106725 7541
Kojto 122:f9eeca106725 7542 /****************** Bits definition for GPIO_IDR register *******************/
Kojto 122:f9eeca106725 7543 #define GPIO_IDR_ID0_Pos (0U)
Kojto 122:f9eeca106725 7544 #define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 7545 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
Kojto 122:f9eeca106725 7546 #define GPIO_IDR_ID1_Pos (1U)
Kojto 122:f9eeca106725 7547 #define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 7548 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
Kojto 122:f9eeca106725 7549 #define GPIO_IDR_ID2_Pos (2U)
Kojto 122:f9eeca106725 7550 #define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 7551 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
Kojto 122:f9eeca106725 7552 #define GPIO_IDR_ID3_Pos (3U)
Kojto 122:f9eeca106725 7553 #define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 7554 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
Kojto 122:f9eeca106725 7555 #define GPIO_IDR_ID4_Pos (4U)
Kojto 122:f9eeca106725 7556 #define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 7557 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
Kojto 122:f9eeca106725 7558 #define GPIO_IDR_ID5_Pos (5U)
Kojto 122:f9eeca106725 7559 #define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 7560 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
Kojto 122:f9eeca106725 7561 #define GPIO_IDR_ID6_Pos (6U)
Kojto 122:f9eeca106725 7562 #define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 7563 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
Kojto 122:f9eeca106725 7564 #define GPIO_IDR_ID7_Pos (7U)
Kojto 122:f9eeca106725 7565 #define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 7566 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
Kojto 122:f9eeca106725 7567 #define GPIO_IDR_ID8_Pos (8U)
Kojto 122:f9eeca106725 7568 #define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 7569 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
Kojto 122:f9eeca106725 7570 #define GPIO_IDR_ID9_Pos (9U)
Kojto 122:f9eeca106725 7571 #define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 7572 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
Kojto 122:f9eeca106725 7573 #define GPIO_IDR_ID10_Pos (10U)
Kojto 122:f9eeca106725 7574 #define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 7575 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
Kojto 122:f9eeca106725 7576 #define GPIO_IDR_ID11_Pos (11U)
Kojto 122:f9eeca106725 7577 #define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 7578 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
Kojto 122:f9eeca106725 7579 #define GPIO_IDR_ID12_Pos (12U)
Kojto 122:f9eeca106725 7580 #define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 7581 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
Kojto 122:f9eeca106725 7582 #define GPIO_IDR_ID13_Pos (13U)
Kojto 122:f9eeca106725 7583 #define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 7584 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
Kojto 122:f9eeca106725 7585 #define GPIO_IDR_ID14_Pos (14U)
Kojto 122:f9eeca106725 7586 #define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 7587 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
Kojto 122:f9eeca106725 7588 #define GPIO_IDR_ID15_Pos (15U)
Kojto 122:f9eeca106725 7589 #define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 7590 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
Kojto 122:f9eeca106725 7591
Kojto 122:f9eeca106725 7592 /* Legacy defines */
Kojto 122:f9eeca106725 7593 #define GPIO_IDR_IDR_0 GPIO_IDR_ID0
Kojto 122:f9eeca106725 7594 #define GPIO_IDR_IDR_1 GPIO_IDR_ID1
Kojto 122:f9eeca106725 7595 #define GPIO_IDR_IDR_2 GPIO_IDR_ID2
Kojto 122:f9eeca106725 7596 #define GPIO_IDR_IDR_3 GPIO_IDR_ID3
Kojto 122:f9eeca106725 7597 #define GPIO_IDR_IDR_4 GPIO_IDR_ID4
Kojto 122:f9eeca106725 7598 #define GPIO_IDR_IDR_5 GPIO_IDR_ID5
Kojto 122:f9eeca106725 7599 #define GPIO_IDR_IDR_6 GPIO_IDR_ID6
Kojto 122:f9eeca106725 7600 #define GPIO_IDR_IDR_7 GPIO_IDR_ID7
Kojto 122:f9eeca106725 7601 #define GPIO_IDR_IDR_8 GPIO_IDR_ID8
Kojto 122:f9eeca106725 7602 #define GPIO_IDR_IDR_9 GPIO_IDR_ID9
Kojto 122:f9eeca106725 7603 #define GPIO_IDR_IDR_10 GPIO_IDR_ID10
Kojto 122:f9eeca106725 7604 #define GPIO_IDR_IDR_11 GPIO_IDR_ID11
Kojto 122:f9eeca106725 7605 #define GPIO_IDR_IDR_12 GPIO_IDR_ID12
Kojto 122:f9eeca106725 7606 #define GPIO_IDR_IDR_13 GPIO_IDR_ID13
Kojto 122:f9eeca106725 7607 #define GPIO_IDR_IDR_14 GPIO_IDR_ID14
Kojto 122:f9eeca106725 7608 #define GPIO_IDR_IDR_15 GPIO_IDR_ID15
Kojto 122:f9eeca106725 7609
Kojto 122:f9eeca106725 7610 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
Kojto 122:f9eeca106725 7611 #define GPIO_OTYPER_IDR_0 GPIO_IDR_ID0
Kojto 122:f9eeca106725 7612 #define GPIO_OTYPER_IDR_1 GPIO_IDR_ID1
Kojto 122:f9eeca106725 7613 #define GPIO_OTYPER_IDR_2 GPIO_IDR_ID2
Kojto 122:f9eeca106725 7614 #define GPIO_OTYPER_IDR_3 GPIO_IDR_ID3
Kojto 122:f9eeca106725 7615 #define GPIO_OTYPER_IDR_4 GPIO_IDR_ID4
Kojto 122:f9eeca106725 7616 #define GPIO_OTYPER_IDR_5 GPIO_IDR_ID5
Kojto 122:f9eeca106725 7617 #define GPIO_OTYPER_IDR_6 GPIO_IDR_ID6
Kojto 122:f9eeca106725 7618 #define GPIO_OTYPER_IDR_7 GPIO_IDR_ID7
Kojto 122:f9eeca106725 7619 #define GPIO_OTYPER_IDR_8 GPIO_IDR_ID8
Kojto 122:f9eeca106725 7620 #define GPIO_OTYPER_IDR_9 GPIO_IDR_ID9
Kojto 122:f9eeca106725 7621 #define GPIO_OTYPER_IDR_10 GPIO_IDR_ID10
Kojto 122:f9eeca106725 7622 #define GPIO_OTYPER_IDR_11 GPIO_IDR_ID11
Kojto 122:f9eeca106725 7623 #define GPIO_OTYPER_IDR_12 GPIO_IDR_ID12
Kojto 122:f9eeca106725 7624 #define GPIO_OTYPER_IDR_13 GPIO_IDR_ID13
Kojto 122:f9eeca106725 7625 #define GPIO_OTYPER_IDR_14 GPIO_IDR_ID14
Kojto 122:f9eeca106725 7626 #define GPIO_OTYPER_IDR_15 GPIO_IDR_ID15
Kojto 122:f9eeca106725 7627
Kojto 122:f9eeca106725 7628 /****************** Bits definition for GPIO_ODR register *******************/
Kojto 122:f9eeca106725 7629 #define GPIO_ODR_OD0_Pos (0U)
Kojto 122:f9eeca106725 7630 #define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 7631 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
Kojto 122:f9eeca106725 7632 #define GPIO_ODR_OD1_Pos (1U)
Kojto 122:f9eeca106725 7633 #define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 7634 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
Kojto 122:f9eeca106725 7635 #define GPIO_ODR_OD2_Pos (2U)
Kojto 122:f9eeca106725 7636 #define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 7637 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
Kojto 122:f9eeca106725 7638 #define GPIO_ODR_OD3_Pos (3U)
Kojto 122:f9eeca106725 7639 #define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 7640 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
Kojto 122:f9eeca106725 7641 #define GPIO_ODR_OD4_Pos (4U)
Kojto 122:f9eeca106725 7642 #define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 7643 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
Kojto 122:f9eeca106725 7644 #define GPIO_ODR_OD5_Pos (5U)
Kojto 122:f9eeca106725 7645 #define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 7646 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
Kojto 122:f9eeca106725 7647 #define GPIO_ODR_OD6_Pos (6U)
Kojto 122:f9eeca106725 7648 #define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 7649 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
Kojto 122:f9eeca106725 7650 #define GPIO_ODR_OD7_Pos (7U)
Kojto 122:f9eeca106725 7651 #define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 7652 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
Kojto 122:f9eeca106725 7653 #define GPIO_ODR_OD8_Pos (8U)
Kojto 122:f9eeca106725 7654 #define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 7655 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
Kojto 122:f9eeca106725 7656 #define GPIO_ODR_OD9_Pos (9U)
Kojto 122:f9eeca106725 7657 #define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 7658 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
Kojto 122:f9eeca106725 7659 #define GPIO_ODR_OD10_Pos (10U)
Kojto 122:f9eeca106725 7660 #define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 7661 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
Kojto 122:f9eeca106725 7662 #define GPIO_ODR_OD11_Pos (11U)
Kojto 122:f9eeca106725 7663 #define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 7664 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
Kojto 122:f9eeca106725 7665 #define GPIO_ODR_OD12_Pos (12U)
Kojto 122:f9eeca106725 7666 #define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 7667 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
Kojto 122:f9eeca106725 7668 #define GPIO_ODR_OD13_Pos (13U)
Kojto 122:f9eeca106725 7669 #define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 7670 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
Kojto 122:f9eeca106725 7671 #define GPIO_ODR_OD14_Pos (14U)
Kojto 122:f9eeca106725 7672 #define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 7673 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
Kojto 122:f9eeca106725 7674 #define GPIO_ODR_OD15_Pos (15U)
Kojto 122:f9eeca106725 7675 #define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 7676 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
Kojto 122:f9eeca106725 7677
Kojto 122:f9eeca106725 7678 /* Legacy defines */
Kojto 122:f9eeca106725 7679 #define GPIO_ODR_ODR_0 GPIO_ODR_OD0
Kojto 122:f9eeca106725 7680 #define GPIO_ODR_ODR_1 GPIO_ODR_OD1
Kojto 122:f9eeca106725 7681 #define GPIO_ODR_ODR_2 GPIO_ODR_OD2
Kojto 122:f9eeca106725 7682 #define GPIO_ODR_ODR_3 GPIO_ODR_OD3
Kojto 122:f9eeca106725 7683 #define GPIO_ODR_ODR_4 GPIO_ODR_OD4
Kojto 122:f9eeca106725 7684 #define GPIO_ODR_ODR_5 GPIO_ODR_OD5
Kojto 122:f9eeca106725 7685 #define GPIO_ODR_ODR_6 GPIO_ODR_OD6
Kojto 122:f9eeca106725 7686 #define GPIO_ODR_ODR_7 GPIO_ODR_OD7
Kojto 122:f9eeca106725 7687 #define GPIO_ODR_ODR_8 GPIO_ODR_OD8
Kojto 122:f9eeca106725 7688 #define GPIO_ODR_ODR_9 GPIO_ODR_OD9
Kojto 122:f9eeca106725 7689 #define GPIO_ODR_ODR_10 GPIO_ODR_OD10
Kojto 122:f9eeca106725 7690 #define GPIO_ODR_ODR_11 GPIO_ODR_OD11
Kojto 122:f9eeca106725 7691 #define GPIO_ODR_ODR_12 GPIO_ODR_OD12
Kojto 122:f9eeca106725 7692 #define GPIO_ODR_ODR_13 GPIO_ODR_OD13
Kojto 122:f9eeca106725 7693 #define GPIO_ODR_ODR_14 GPIO_ODR_OD14
Kojto 122:f9eeca106725 7694 #define GPIO_ODR_ODR_15 GPIO_ODR_OD15
Kojto 122:f9eeca106725 7695
Kojto 122:f9eeca106725 7696 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
Kojto 122:f9eeca106725 7697 #define GPIO_OTYPER_ODR_0 GPIO_ODR_OD0
Kojto 122:f9eeca106725 7698 #define GPIO_OTYPER_ODR_1 GPIO_ODR_OD1
Kojto 122:f9eeca106725 7699 #define GPIO_OTYPER_ODR_2 GPIO_ODR_OD2
Kojto 122:f9eeca106725 7700 #define GPIO_OTYPER_ODR_3 GPIO_ODR_OD3
Kojto 122:f9eeca106725 7701 #define GPIO_OTYPER_ODR_4 GPIO_ODR_OD4
Kojto 122:f9eeca106725 7702 #define GPIO_OTYPER_ODR_5 GPIO_ODR_OD5
Kojto 122:f9eeca106725 7703 #define GPIO_OTYPER_ODR_6 GPIO_ODR_OD6
Kojto 122:f9eeca106725 7704 #define GPIO_OTYPER_ODR_7 GPIO_ODR_OD7
Kojto 122:f9eeca106725 7705 #define GPIO_OTYPER_ODR_8 GPIO_ODR_OD8
Kojto 122:f9eeca106725 7706 #define GPIO_OTYPER_ODR_9 GPIO_ODR_OD9
Kojto 122:f9eeca106725 7707 #define GPIO_OTYPER_ODR_10 GPIO_ODR_OD10
Kojto 122:f9eeca106725 7708 #define GPIO_OTYPER_ODR_11 GPIO_ODR_OD11
Kojto 122:f9eeca106725 7709 #define GPIO_OTYPER_ODR_12 GPIO_ODR_OD12
Kojto 122:f9eeca106725 7710 #define GPIO_OTYPER_ODR_13 GPIO_ODR_OD13
Kojto 122:f9eeca106725 7711 #define GPIO_OTYPER_ODR_14 GPIO_ODR_OD14
Kojto 122:f9eeca106725 7712 #define GPIO_OTYPER_ODR_15 GPIO_ODR_OD15
Kojto 122:f9eeca106725 7713
Kojto 122:f9eeca106725 7714 /****************** Bits definition for GPIO_BSRR register ******************/
Kojto 122:f9eeca106725 7715 #define GPIO_BSRR_BS0_Pos (0U)
Kojto 122:f9eeca106725 7716 #define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 7717 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
Kojto 122:f9eeca106725 7718 #define GPIO_BSRR_BS1_Pos (1U)
Kojto 122:f9eeca106725 7719 #define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 7720 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
Kojto 122:f9eeca106725 7721 #define GPIO_BSRR_BS2_Pos (2U)
Kojto 122:f9eeca106725 7722 #define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 7723 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
Kojto 122:f9eeca106725 7724 #define GPIO_BSRR_BS3_Pos (3U)
Kojto 122:f9eeca106725 7725 #define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 7726 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
Kojto 122:f9eeca106725 7727 #define GPIO_BSRR_BS4_Pos (4U)
Kojto 122:f9eeca106725 7728 #define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 7729 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
Kojto 122:f9eeca106725 7730 #define GPIO_BSRR_BS5_Pos (5U)
Kojto 122:f9eeca106725 7731 #define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 7732 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
Kojto 122:f9eeca106725 7733 #define GPIO_BSRR_BS6_Pos (6U)
Kojto 122:f9eeca106725 7734 #define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 7735 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
Kojto 122:f9eeca106725 7736 #define GPIO_BSRR_BS7_Pos (7U)
Kojto 122:f9eeca106725 7737 #define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 7738 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
Kojto 122:f9eeca106725 7739 #define GPIO_BSRR_BS8_Pos (8U)
Kojto 122:f9eeca106725 7740 #define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 7741 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
Kojto 122:f9eeca106725 7742 #define GPIO_BSRR_BS9_Pos (9U)
Kojto 122:f9eeca106725 7743 #define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 7744 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
Kojto 122:f9eeca106725 7745 #define GPIO_BSRR_BS10_Pos (10U)
Kojto 122:f9eeca106725 7746 #define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 7747 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
Kojto 122:f9eeca106725 7748 #define GPIO_BSRR_BS11_Pos (11U)
Kojto 122:f9eeca106725 7749 #define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 7750 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
Kojto 122:f9eeca106725 7751 #define GPIO_BSRR_BS12_Pos (12U)
Kojto 122:f9eeca106725 7752 #define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 7753 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
Kojto 122:f9eeca106725 7754 #define GPIO_BSRR_BS13_Pos (13U)
Kojto 122:f9eeca106725 7755 #define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 7756 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
Kojto 122:f9eeca106725 7757 #define GPIO_BSRR_BS14_Pos (14U)
Kojto 122:f9eeca106725 7758 #define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 7759 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
Kojto 122:f9eeca106725 7760 #define GPIO_BSRR_BS15_Pos (15U)
Kojto 122:f9eeca106725 7761 #define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 7762 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
Kojto 122:f9eeca106725 7763 #define GPIO_BSRR_BR0_Pos (16U)
Kojto 122:f9eeca106725 7764 #define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 7765 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
Kojto 122:f9eeca106725 7766 #define GPIO_BSRR_BR1_Pos (17U)
Kojto 122:f9eeca106725 7767 #define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 7768 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
Kojto 122:f9eeca106725 7769 #define GPIO_BSRR_BR2_Pos (18U)
Kojto 122:f9eeca106725 7770 #define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 7771 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
Kojto 122:f9eeca106725 7772 #define GPIO_BSRR_BR3_Pos (19U)
Kojto 122:f9eeca106725 7773 #define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 7774 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
Kojto 122:f9eeca106725 7775 #define GPIO_BSRR_BR4_Pos (20U)
Kojto 122:f9eeca106725 7776 #define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 7777 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
Kojto 122:f9eeca106725 7778 #define GPIO_BSRR_BR5_Pos (21U)
Kojto 122:f9eeca106725 7779 #define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 7780 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
Kojto 122:f9eeca106725 7781 #define GPIO_BSRR_BR6_Pos (22U)
Kojto 122:f9eeca106725 7782 #define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 7783 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
Kojto 122:f9eeca106725 7784 #define GPIO_BSRR_BR7_Pos (23U)
Kojto 122:f9eeca106725 7785 #define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 7786 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
Kojto 122:f9eeca106725 7787 #define GPIO_BSRR_BR8_Pos (24U)
Kojto 122:f9eeca106725 7788 #define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 7789 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
Kojto 122:f9eeca106725 7790 #define GPIO_BSRR_BR9_Pos (25U)
Kojto 122:f9eeca106725 7791 #define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 7792 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
Kojto 122:f9eeca106725 7793 #define GPIO_BSRR_BR10_Pos (26U)
Kojto 122:f9eeca106725 7794 #define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 7795 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
Kojto 122:f9eeca106725 7796 #define GPIO_BSRR_BR11_Pos (27U)
Kojto 122:f9eeca106725 7797 #define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 7798 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
Kojto 122:f9eeca106725 7799 #define GPIO_BSRR_BR12_Pos (28U)
Kojto 122:f9eeca106725 7800 #define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 7801 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
Kojto 122:f9eeca106725 7802 #define GPIO_BSRR_BR13_Pos (29U)
Kojto 122:f9eeca106725 7803 #define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 7804 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
Kojto 122:f9eeca106725 7805 #define GPIO_BSRR_BR14_Pos (30U)
Kojto 122:f9eeca106725 7806 #define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 7807 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
Kojto 122:f9eeca106725 7808 #define GPIO_BSRR_BR15_Pos (31U)
Kojto 122:f9eeca106725 7809 #define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 7810 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
Kojto 122:f9eeca106725 7811
Kojto 122:f9eeca106725 7812 /* Legacy defines */
Kojto 122:f9eeca106725 7813 #define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
Kojto 122:f9eeca106725 7814 #define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
Kojto 122:f9eeca106725 7815 #define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
Kojto 122:f9eeca106725 7816 #define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
Kojto 122:f9eeca106725 7817 #define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
Kojto 122:f9eeca106725 7818 #define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
Kojto 122:f9eeca106725 7819 #define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
Kojto 122:f9eeca106725 7820 #define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
Kojto 122:f9eeca106725 7821 #define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
Kojto 122:f9eeca106725 7822 #define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
Kojto 122:f9eeca106725 7823 #define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
Kojto 122:f9eeca106725 7824 #define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
Kojto 122:f9eeca106725 7825 #define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
Kojto 122:f9eeca106725 7826 #define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
Kojto 122:f9eeca106725 7827 #define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
Kojto 122:f9eeca106725 7828 #define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
Kojto 122:f9eeca106725 7829 #define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
Kojto 122:f9eeca106725 7830 #define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
Kojto 122:f9eeca106725 7831 #define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
Kojto 122:f9eeca106725 7832 #define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
Kojto 122:f9eeca106725 7833 #define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
Kojto 122:f9eeca106725 7834 #define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
Kojto 122:f9eeca106725 7835 #define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
Kojto 122:f9eeca106725 7836 #define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
Kojto 122:f9eeca106725 7837 #define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
Kojto 122:f9eeca106725 7838 #define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
Kojto 122:f9eeca106725 7839 #define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
Kojto 122:f9eeca106725 7840 #define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
Kojto 122:f9eeca106725 7841 #define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
Kojto 122:f9eeca106725 7842 #define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
Kojto 122:f9eeca106725 7843 #define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
Kojto 122:f9eeca106725 7844 #define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
Kojto 122:f9eeca106725 7845
Kojto 122:f9eeca106725 7846 /****************** Bit definition for GPIO_LCKR register *********************/
Kojto 122:f9eeca106725 7847 #define GPIO_LCKR_LCK0_Pos (0U)
Kojto 122:f9eeca106725 7848 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 7849 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
Kojto 122:f9eeca106725 7850 #define GPIO_LCKR_LCK1_Pos (1U)
Kojto 122:f9eeca106725 7851 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 7852 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
Kojto 122:f9eeca106725 7853 #define GPIO_LCKR_LCK2_Pos (2U)
Kojto 122:f9eeca106725 7854 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 7855 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
Kojto 122:f9eeca106725 7856 #define GPIO_LCKR_LCK3_Pos (3U)
Kojto 122:f9eeca106725 7857 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 7858 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
Kojto 122:f9eeca106725 7859 #define GPIO_LCKR_LCK4_Pos (4U)
Kojto 122:f9eeca106725 7860 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 7861 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
Kojto 122:f9eeca106725 7862 #define GPIO_LCKR_LCK5_Pos (5U)
Kojto 122:f9eeca106725 7863 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 7864 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
Kojto 122:f9eeca106725 7865 #define GPIO_LCKR_LCK6_Pos (6U)
Kojto 122:f9eeca106725 7866 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 7867 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
Kojto 122:f9eeca106725 7868 #define GPIO_LCKR_LCK7_Pos (7U)
Kojto 122:f9eeca106725 7869 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 7870 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
Kojto 122:f9eeca106725 7871 #define GPIO_LCKR_LCK8_Pos (8U)
Kojto 122:f9eeca106725 7872 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 7873 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
Kojto 122:f9eeca106725 7874 #define GPIO_LCKR_LCK9_Pos (9U)
Kojto 122:f9eeca106725 7875 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 7876 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
Kojto 122:f9eeca106725 7877 #define GPIO_LCKR_LCK10_Pos (10U)
Kojto 122:f9eeca106725 7878 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 7879 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
Kojto 122:f9eeca106725 7880 #define GPIO_LCKR_LCK11_Pos (11U)
Kojto 122:f9eeca106725 7881 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 7882 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
Kojto 122:f9eeca106725 7883 #define GPIO_LCKR_LCK12_Pos (12U)
Kojto 122:f9eeca106725 7884 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 7885 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
Kojto 122:f9eeca106725 7886 #define GPIO_LCKR_LCK13_Pos (13U)
Kojto 122:f9eeca106725 7887 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 7888 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
Kojto 122:f9eeca106725 7889 #define GPIO_LCKR_LCK14_Pos (14U)
Kojto 122:f9eeca106725 7890 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 7891 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
Kojto 122:f9eeca106725 7892 #define GPIO_LCKR_LCK15_Pos (15U)
Kojto 122:f9eeca106725 7893 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 7894 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
Kojto 122:f9eeca106725 7895 #define GPIO_LCKR_LCKK_Pos (16U)
Kojto 122:f9eeca106725 7896 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 7897 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
Kojto 122:f9eeca106725 7898
Kojto 122:f9eeca106725 7899 /****************** Bit definition for GPIO_AFRL register *********************/
Kojto 122:f9eeca106725 7900 #define GPIO_AFRL_AFSEL0_Pos (0U)
Kojto 122:f9eeca106725 7901 #define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 7902 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
Kojto 122:f9eeca106725 7903 #define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 7904 #define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 7905 #define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 7906 #define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 7907 #define GPIO_AFRL_AFSEL1_Pos (4U)
Kojto 122:f9eeca106725 7908 #define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
Kojto 122:f9eeca106725 7909 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
Kojto 122:f9eeca106725 7910 #define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 7911 #define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 7912 #define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 7913 #define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 7914 #define GPIO_AFRL_AFSEL2_Pos (8U)
Kojto 122:f9eeca106725 7915 #define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 7916 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
Kojto 122:f9eeca106725 7917 #define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 7918 #define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 7919 #define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 7920 #define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 7921 #define GPIO_AFRL_AFSEL3_Pos (12U)
Kojto 122:f9eeca106725 7922 #define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
Kojto 122:f9eeca106725 7923 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
Kojto 122:f9eeca106725 7924 #define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 7925 #define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 7926 #define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 7927 #define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 7928 #define GPIO_AFRL_AFSEL4_Pos (16U)
Kojto 122:f9eeca106725 7929 #define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
Kojto 122:f9eeca106725 7930 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
Kojto 122:f9eeca106725 7931 #define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 7932 #define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 7933 #define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 7934 #define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 7935 #define GPIO_AFRL_AFSEL5_Pos (20U)
Kojto 122:f9eeca106725 7936 #define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
Kojto 122:f9eeca106725 7937 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
Kojto 122:f9eeca106725 7938 #define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 7939 #define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 7940 #define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 7941 #define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 7942 #define GPIO_AFRL_AFSEL6_Pos (24U)
Kojto 122:f9eeca106725 7943 #define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
Kojto 122:f9eeca106725 7944 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
Kojto 122:f9eeca106725 7945 #define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 7946 #define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 7947 #define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 7948 #define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 7949 #define GPIO_AFRL_AFSEL7_Pos (28U)
Kojto 122:f9eeca106725 7950 #define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
Kojto 122:f9eeca106725 7951 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
Kojto 122:f9eeca106725 7952 #define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 7953 #define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 7954 #define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 7955 #define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 7956
Kojto 122:f9eeca106725 7957 /* Legacy defines */
Kojto 122:f9eeca106725 7958 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
Kojto 122:f9eeca106725 7959 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
Kojto 122:f9eeca106725 7960 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
Kojto 122:f9eeca106725 7961 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
Kojto 122:f9eeca106725 7962 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
Kojto 122:f9eeca106725 7963 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
Kojto 122:f9eeca106725 7964 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
Kojto 122:f9eeca106725 7965 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
Kojto 122:f9eeca106725 7966
Kojto 122:f9eeca106725 7967 /****************** Bit definition for GPIO_AFRH register *********************/
Kojto 122:f9eeca106725 7968 #define GPIO_AFRH_AFSEL8_Pos (0U)
Kojto 122:f9eeca106725 7969 #define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 7970 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
Kojto 122:f9eeca106725 7971 #define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 7972 #define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 7973 #define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 7974 #define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 7975 #define GPIO_AFRH_AFSEL9_Pos (4U)
Kojto 122:f9eeca106725 7976 #define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
Kojto 122:f9eeca106725 7977 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
Kojto 122:f9eeca106725 7978 #define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 7979 #define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 7980 #define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 7981 #define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 7982 #define GPIO_AFRH_AFSEL10_Pos (8U)
Kojto 122:f9eeca106725 7983 #define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 7984 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
Kojto 122:f9eeca106725 7985 #define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 7986 #define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 7987 #define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 7988 #define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 7989 #define GPIO_AFRH_AFSEL11_Pos (12U)
Kojto 122:f9eeca106725 7990 #define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
Kojto 122:f9eeca106725 7991 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
Kojto 122:f9eeca106725 7992 #define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 7993 #define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 7994 #define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 7995 #define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 7996 #define GPIO_AFRH_AFSEL12_Pos (16U)
Kojto 122:f9eeca106725 7997 #define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
Kojto 122:f9eeca106725 7998 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
Kojto 122:f9eeca106725 7999 #define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 8000 #define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 8001 #define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 8002 #define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 8003 #define GPIO_AFRH_AFSEL13_Pos (20U)
Kojto 122:f9eeca106725 8004 #define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
Kojto 122:f9eeca106725 8005 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
Kojto 122:f9eeca106725 8006 #define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 8007 #define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 8008 #define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 8009 #define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 8010 #define GPIO_AFRH_AFSEL14_Pos (24U)
Kojto 122:f9eeca106725 8011 #define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
Kojto 122:f9eeca106725 8012 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
Kojto 122:f9eeca106725 8013 #define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 8014 #define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 8015 #define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 8016 #define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 8017 #define GPIO_AFRH_AFSEL15_Pos (28U)
Kojto 122:f9eeca106725 8018 #define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
Kojto 122:f9eeca106725 8019 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
Kojto 122:f9eeca106725 8020 #define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 8021 #define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 8022 #define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 8023 #define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 8024
Kojto 122:f9eeca106725 8025 /* Legacy defines */
Kojto 122:f9eeca106725 8026 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
Kojto 122:f9eeca106725 8027 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
Kojto 122:f9eeca106725 8028 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
Kojto 122:f9eeca106725 8029 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
Kojto 122:f9eeca106725 8030 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
Kojto 122:f9eeca106725 8031 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
Kojto 122:f9eeca106725 8032 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
Kojto 122:f9eeca106725 8033 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
Kojto 122:f9eeca106725 8034
Kojto 122:f9eeca106725 8035 /****************** Bits definition for GPIO_BRR register ******************/
Kojto 122:f9eeca106725 8036 #define GPIO_BRR_BR0_Pos (0U)
Kojto 122:f9eeca106725 8037 #define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8038 #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
Kojto 122:f9eeca106725 8039 #define GPIO_BRR_BR1_Pos (1U)
Kojto 122:f9eeca106725 8040 #define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 8041 #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
Kojto 122:f9eeca106725 8042 #define GPIO_BRR_BR2_Pos (2U)
Kojto 122:f9eeca106725 8043 #define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 8044 #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
Kojto 122:f9eeca106725 8045 #define GPIO_BRR_BR3_Pos (3U)
Kojto 122:f9eeca106725 8046 #define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 8047 #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
Kojto 122:f9eeca106725 8048 #define GPIO_BRR_BR4_Pos (4U)
Kojto 122:f9eeca106725 8049 #define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 8050 #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
Kojto 122:f9eeca106725 8051 #define GPIO_BRR_BR5_Pos (5U)
Kojto 122:f9eeca106725 8052 #define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 8053 #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
Kojto 122:f9eeca106725 8054 #define GPIO_BRR_BR6_Pos (6U)
Kojto 122:f9eeca106725 8055 #define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 8056 #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
Kojto 122:f9eeca106725 8057 #define GPIO_BRR_BR7_Pos (7U)
Kojto 122:f9eeca106725 8058 #define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 8059 #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
Kojto 122:f9eeca106725 8060 #define GPIO_BRR_BR8_Pos (8U)
Kojto 122:f9eeca106725 8061 #define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 8062 #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
Kojto 122:f9eeca106725 8063 #define GPIO_BRR_BR9_Pos (9U)
Kojto 122:f9eeca106725 8064 #define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 8065 #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
Kojto 122:f9eeca106725 8066 #define GPIO_BRR_BR10_Pos (10U)
Kojto 122:f9eeca106725 8067 #define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 8068 #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
Kojto 122:f9eeca106725 8069 #define GPIO_BRR_BR11_Pos (11U)
Kojto 122:f9eeca106725 8070 #define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 8071 #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
Kojto 122:f9eeca106725 8072 #define GPIO_BRR_BR12_Pos (12U)
Kojto 122:f9eeca106725 8073 #define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 8074 #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
Kojto 122:f9eeca106725 8075 #define GPIO_BRR_BR13_Pos (13U)
Kojto 122:f9eeca106725 8076 #define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 8077 #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
Kojto 122:f9eeca106725 8078 #define GPIO_BRR_BR14_Pos (14U)
Kojto 122:f9eeca106725 8079 #define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 8080 #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
Kojto 122:f9eeca106725 8081 #define GPIO_BRR_BR15_Pos (15U)
Kojto 122:f9eeca106725 8082 #define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 8083 #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
Kojto 122:f9eeca106725 8084
Kojto 122:f9eeca106725 8085 /* Legacy defines */
Kojto 122:f9eeca106725 8086 #define GPIO_BRR_BR_0 GPIO_BRR_BR0
Kojto 122:f9eeca106725 8087 #define GPIO_BRR_BR_1 GPIO_BRR_BR1
Kojto 122:f9eeca106725 8088 #define GPIO_BRR_BR_2 GPIO_BRR_BR2
Kojto 122:f9eeca106725 8089 #define GPIO_BRR_BR_3 GPIO_BRR_BR3
Kojto 122:f9eeca106725 8090 #define GPIO_BRR_BR_4 GPIO_BRR_BR4
Kojto 122:f9eeca106725 8091 #define GPIO_BRR_BR_5 GPIO_BRR_BR5
Kojto 122:f9eeca106725 8092 #define GPIO_BRR_BR_6 GPIO_BRR_BR6
Kojto 122:f9eeca106725 8093 #define GPIO_BRR_BR_7 GPIO_BRR_BR7
Kojto 122:f9eeca106725 8094 #define GPIO_BRR_BR_8 GPIO_BRR_BR8
Kojto 122:f9eeca106725 8095 #define GPIO_BRR_BR_9 GPIO_BRR_BR9
Kojto 122:f9eeca106725 8096 #define GPIO_BRR_BR_10 GPIO_BRR_BR10
Kojto 122:f9eeca106725 8097 #define GPIO_BRR_BR_11 GPIO_BRR_BR11
Kojto 122:f9eeca106725 8098 #define GPIO_BRR_BR_12 GPIO_BRR_BR12
Kojto 122:f9eeca106725 8099 #define GPIO_BRR_BR_13 GPIO_BRR_BR13
Kojto 122:f9eeca106725 8100 #define GPIO_BRR_BR_14 GPIO_BRR_BR14
Kojto 122:f9eeca106725 8101 #define GPIO_BRR_BR_15 GPIO_BRR_BR15
Kojto 122:f9eeca106725 8102
Kojto 122:f9eeca106725 8103
Kojto 122:f9eeca106725 8104
Kojto 122:f9eeca106725 8105 /******************************************************************************/
Kojto 122:f9eeca106725 8106 /* */
Kojto 122:f9eeca106725 8107 /* Inter-integrated Circuit Interface (I2C) */
Kojto 122:f9eeca106725 8108 /* */
Kojto 122:f9eeca106725 8109 /******************************************************************************/
Kojto 122:f9eeca106725 8110 /******************* Bit definition for I2C_CR1 register *******************/
Kojto 122:f9eeca106725 8111 #define I2C_CR1_PE_Pos (0U)
Kojto 122:f9eeca106725 8112 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8113 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
Kojto 122:f9eeca106725 8114 #define I2C_CR1_TXIE_Pos (1U)
Kojto 122:f9eeca106725 8115 #define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 8116 #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
Kojto 122:f9eeca106725 8117 #define I2C_CR1_RXIE_Pos (2U)
Kojto 122:f9eeca106725 8118 #define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 8119 #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
Kojto 122:f9eeca106725 8120 #define I2C_CR1_ADDRIE_Pos (3U)
Kojto 122:f9eeca106725 8121 #define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 8122 #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
Kojto 122:f9eeca106725 8123 #define I2C_CR1_NACKIE_Pos (4U)
Kojto 122:f9eeca106725 8124 #define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 8125 #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
Kojto 122:f9eeca106725 8126 #define I2C_CR1_STOPIE_Pos (5U)
Kojto 122:f9eeca106725 8127 #define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 8128 #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
Kojto 122:f9eeca106725 8129 #define I2C_CR1_TCIE_Pos (6U)
Kojto 122:f9eeca106725 8130 #define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 8131 #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
Kojto 122:f9eeca106725 8132 #define I2C_CR1_ERRIE_Pos (7U)
Kojto 122:f9eeca106725 8133 #define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 8134 #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
Kojto 122:f9eeca106725 8135 #define I2C_CR1_DNF_Pos (8U)
Kojto 122:f9eeca106725 8136 #define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 8137 #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
Kojto 122:f9eeca106725 8138 #define I2C_CR1_ANFOFF_Pos (12U)
Kojto 122:f9eeca106725 8139 #define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 8140 #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
Kojto 122:f9eeca106725 8141 #define I2C_CR1_SWRST_Pos (13U)
Kojto 122:f9eeca106725 8142 #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 8143 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */
Kojto 122:f9eeca106725 8144 #define I2C_CR1_TXDMAEN_Pos (14U)
Kojto 122:f9eeca106725 8145 #define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 8146 #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
Kojto 122:f9eeca106725 8147 #define I2C_CR1_RXDMAEN_Pos (15U)
Kojto 122:f9eeca106725 8148 #define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 8149 #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
Kojto 122:f9eeca106725 8150 #define I2C_CR1_SBC_Pos (16U)
Kojto 122:f9eeca106725 8151 #define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 8152 #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
Kojto 122:f9eeca106725 8153 #define I2C_CR1_NOSTRETCH_Pos (17U)
Kojto 122:f9eeca106725 8154 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 8155 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
Kojto 122:f9eeca106725 8156 #define I2C_CR1_WUPEN_Pos (18U)
Kojto 122:f9eeca106725 8157 #define I2C_CR1_WUPEN_Msk (0x1U << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 8158 #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
Kojto 122:f9eeca106725 8159 #define I2C_CR1_GCEN_Pos (19U)
Kojto 122:f9eeca106725 8160 #define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 8161 #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
Kojto 122:f9eeca106725 8162 #define I2C_CR1_SMBHEN_Pos (20U)
Kojto 122:f9eeca106725 8163 #define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 8164 #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
Kojto 122:f9eeca106725 8165 #define I2C_CR1_SMBDEN_Pos (21U)
Kojto 122:f9eeca106725 8166 #define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 8167 #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
Kojto 122:f9eeca106725 8168 #define I2C_CR1_ALERTEN_Pos (22U)
Kojto 122:f9eeca106725 8169 #define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 8170 #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
Kojto 122:f9eeca106725 8171 #define I2C_CR1_PECEN_Pos (23U)
Kojto 122:f9eeca106725 8172 #define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 8173 #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
Kojto 122:f9eeca106725 8174
Kojto 122:f9eeca106725 8175 /****************** Bit definition for I2C_CR2 register ********************/
Kojto 122:f9eeca106725 8176 #define I2C_CR2_SADD_Pos (0U)
Kojto 122:f9eeca106725 8177 #define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
Kojto 122:f9eeca106725 8178 #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
Kojto 122:f9eeca106725 8179 #define I2C_CR2_RD_WRN_Pos (10U)
Kojto 122:f9eeca106725 8180 #define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 8181 #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
Kojto 122:f9eeca106725 8182 #define I2C_CR2_ADD10_Pos (11U)
Kojto 122:f9eeca106725 8183 #define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 8184 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
Kojto 122:f9eeca106725 8185 #define I2C_CR2_HEAD10R_Pos (12U)
Kojto 122:f9eeca106725 8186 #define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 8187 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
Kojto 122:f9eeca106725 8188 #define I2C_CR2_START_Pos (13U)
Kojto 122:f9eeca106725 8189 #define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 8190 #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
Kojto 122:f9eeca106725 8191 #define I2C_CR2_STOP_Pos (14U)
Kojto 122:f9eeca106725 8192 #define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 8193 #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
Kojto 122:f9eeca106725 8194 #define I2C_CR2_NACK_Pos (15U)
Kojto 122:f9eeca106725 8195 #define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 8196 #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
Kojto 122:f9eeca106725 8197 #define I2C_CR2_NBYTES_Pos (16U)
Kojto 122:f9eeca106725 8198 #define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 8199 #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
Kojto 122:f9eeca106725 8200 #define I2C_CR2_RELOAD_Pos (24U)
Kojto 122:f9eeca106725 8201 #define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 8202 #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
Kojto 122:f9eeca106725 8203 #define I2C_CR2_AUTOEND_Pos (25U)
Kojto 122:f9eeca106725 8204 #define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 8205 #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
Kojto 122:f9eeca106725 8206 #define I2C_CR2_PECBYTE_Pos (26U)
Kojto 122:f9eeca106725 8207 #define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 8208 #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
Kojto 122:f9eeca106725 8209
Kojto 122:f9eeca106725 8210 /******************* Bit definition for I2C_OAR1 register ******************/
Kojto 122:f9eeca106725 8211 #define I2C_OAR1_OA1_Pos (0U)
Kojto 122:f9eeca106725 8212 #define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
Kojto 122:f9eeca106725 8213 #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
Kojto 122:f9eeca106725 8214 #define I2C_OAR1_OA1MODE_Pos (10U)
Kojto 122:f9eeca106725 8215 #define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 8216 #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
Kojto 122:f9eeca106725 8217 #define I2C_OAR1_OA1EN_Pos (15U)
Kojto 122:f9eeca106725 8218 #define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 8219 #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
Kojto 122:f9eeca106725 8220
Kojto 122:f9eeca106725 8221 /******************* Bit definition for I2C_OAR2 register ******************/
Kojto 122:f9eeca106725 8222 #define I2C_OAR2_OA2_Pos (1U)
Kojto 122:f9eeca106725 8223 #define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
Kojto 122:f9eeca106725 8224 #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
Kojto 122:f9eeca106725 8225 #define I2C_OAR2_OA2MSK_Pos (8U)
Kojto 122:f9eeca106725 8226 #define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
Kojto 122:f9eeca106725 8227 #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
Kojto 122:f9eeca106725 8228 #define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
Kojto 122:f9eeca106725 8229 #define I2C_OAR2_OA2MASK01_Pos (8U)
Kojto 122:f9eeca106725 8230 #define I2C_OAR2_OA2MASK01_Msk (0x1U << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 8231 #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
Kojto 122:f9eeca106725 8232 #define I2C_OAR2_OA2MASK02_Pos (9U)
Kojto 122:f9eeca106725 8233 #define I2C_OAR2_OA2MASK02_Msk (0x1U << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 8234 #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
Kojto 122:f9eeca106725 8235 #define I2C_OAR2_OA2MASK03_Pos (8U)
Kojto 122:f9eeca106725 8236 #define I2C_OAR2_OA2MASK03_Msk (0x3U << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 8237 #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
Kojto 122:f9eeca106725 8238 #define I2C_OAR2_OA2MASK04_Pos (10U)
Kojto 122:f9eeca106725 8239 #define I2C_OAR2_OA2MASK04_Msk (0x1U << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 8240 #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
Kojto 122:f9eeca106725 8241 #define I2C_OAR2_OA2MASK05_Pos (8U)
Kojto 122:f9eeca106725 8242 #define I2C_OAR2_OA2MASK05_Msk (0x5U << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
Kojto 122:f9eeca106725 8243 #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
Kojto 122:f9eeca106725 8244 #define I2C_OAR2_OA2MASK06_Pos (9U)
Kojto 122:f9eeca106725 8245 #define I2C_OAR2_OA2MASK06_Msk (0x3U << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
Kojto 122:f9eeca106725 8246 #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
Kojto 122:f9eeca106725 8247 #define I2C_OAR2_OA2MASK07_Pos (8U)
Kojto 122:f9eeca106725 8248 #define I2C_OAR2_OA2MASK07_Msk (0x7U << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
Kojto 122:f9eeca106725 8249 #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
Kojto 122:f9eeca106725 8250 #define I2C_OAR2_OA2EN_Pos (15U)
Kojto 122:f9eeca106725 8251 #define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 8252 #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
Kojto 122:f9eeca106725 8253
Kojto 122:f9eeca106725 8254 /******************* Bit definition for I2C_TIMINGR register *******************/
Kojto 122:f9eeca106725 8255 #define I2C_TIMINGR_SCLL_Pos (0U)
Kojto 122:f9eeca106725 8256 #define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 8257 #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
Kojto 122:f9eeca106725 8258 #define I2C_TIMINGR_SCLH_Pos (8U)
Kojto 122:f9eeca106725 8259 #define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 8260 #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
Kojto 122:f9eeca106725 8261 #define I2C_TIMINGR_SDADEL_Pos (16U)
Kojto 122:f9eeca106725 8262 #define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
Kojto 122:f9eeca106725 8263 #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
Kojto 122:f9eeca106725 8264 #define I2C_TIMINGR_SCLDEL_Pos (20U)
Kojto 122:f9eeca106725 8265 #define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
Kojto 122:f9eeca106725 8266 #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
Kojto 122:f9eeca106725 8267 #define I2C_TIMINGR_PRESC_Pos (28U)
Kojto 122:f9eeca106725 8268 #define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
Kojto 122:f9eeca106725 8269 #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
Kojto 122:f9eeca106725 8270
Kojto 122:f9eeca106725 8271 /******************* Bit definition for I2C_TIMEOUTR register *******************/
Kojto 122:f9eeca106725 8272 #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
Kojto 122:f9eeca106725 8273 #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
Kojto 122:f9eeca106725 8274 #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
Kojto 122:f9eeca106725 8275 #define I2C_TIMEOUTR_TIDLE_Pos (12U)
Kojto 122:f9eeca106725 8276 #define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 8277 #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
Kojto 122:f9eeca106725 8278 #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
Kojto 122:f9eeca106725 8279 #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 8280 #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
Kojto 122:f9eeca106725 8281 #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
Kojto 122:f9eeca106725 8282 #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
Kojto 122:f9eeca106725 8283 #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B */
Kojto 122:f9eeca106725 8284 #define I2C_TIMEOUTR_TEXTEN_Pos (31U)
Kojto 122:f9eeca106725 8285 #define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 8286 #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
Kojto 122:f9eeca106725 8287
Kojto 122:f9eeca106725 8288 /****************** Bit definition for I2C_ISR register *********************/
Kojto 122:f9eeca106725 8289 #define I2C_ISR_TXE_Pos (0U)
Kojto 122:f9eeca106725 8290 #define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8291 #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
Kojto 122:f9eeca106725 8292 #define I2C_ISR_TXIS_Pos (1U)
Kojto 122:f9eeca106725 8293 #define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 8294 #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
Kojto 122:f9eeca106725 8295 #define I2C_ISR_RXNE_Pos (2U)
Kojto 122:f9eeca106725 8296 #define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 8297 #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
Kojto 122:f9eeca106725 8298 #define I2C_ISR_ADDR_Pos (3U)
Kojto 122:f9eeca106725 8299 #define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 8300 #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode) */
Kojto 122:f9eeca106725 8301 #define I2C_ISR_NACKF_Pos (4U)
Kojto 122:f9eeca106725 8302 #define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 8303 #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
Kojto 122:f9eeca106725 8304 #define I2C_ISR_STOPF_Pos (5U)
Kojto 122:f9eeca106725 8305 #define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 8306 #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
Kojto 122:f9eeca106725 8307 #define I2C_ISR_TC_Pos (6U)
Kojto 122:f9eeca106725 8308 #define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 8309 #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
Kojto 122:f9eeca106725 8310 #define I2C_ISR_TCR_Pos (7U)
Kojto 122:f9eeca106725 8311 #define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 8312 #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
Kojto 122:f9eeca106725 8313 #define I2C_ISR_BERR_Pos (8U)
Kojto 122:f9eeca106725 8314 #define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 8315 #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
Kojto 122:f9eeca106725 8316 #define I2C_ISR_ARLO_Pos (9U)
Kojto 122:f9eeca106725 8317 #define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 8318 #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
Kojto 122:f9eeca106725 8319 #define I2C_ISR_OVR_Pos (10U)
Kojto 122:f9eeca106725 8320 #define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 8321 #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
Kojto 122:f9eeca106725 8322 #define I2C_ISR_PECERR_Pos (11U)
Kojto 122:f9eeca106725 8323 #define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 8324 #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
Kojto 122:f9eeca106725 8325 #define I2C_ISR_TIMEOUT_Pos (12U)
Kojto 122:f9eeca106725 8326 #define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 8327 #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
Kojto 122:f9eeca106725 8328 #define I2C_ISR_ALERT_Pos (13U)
Kojto 122:f9eeca106725 8329 #define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 8330 #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
Kojto 122:f9eeca106725 8331 #define I2C_ISR_BUSY_Pos (15U)
Kojto 122:f9eeca106725 8332 #define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 8333 #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
Kojto 122:f9eeca106725 8334 #define I2C_ISR_DIR_Pos (16U)
Kojto 122:f9eeca106725 8335 #define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 8336 #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
Kojto 122:f9eeca106725 8337 #define I2C_ISR_ADDCODE_Pos (17U)
Kojto 122:f9eeca106725 8338 #define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
Kojto 122:f9eeca106725 8339 #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
Kojto 122:f9eeca106725 8340
Kojto 122:f9eeca106725 8341 /****************** Bit definition for I2C_ICR register *********************/
Kojto 122:f9eeca106725 8342 #define I2C_ICR_ADDRCF_Pos (3U)
Kojto 122:f9eeca106725 8343 #define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 8344 #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
Kojto 122:f9eeca106725 8345 #define I2C_ICR_NACKCF_Pos (4U)
Kojto 122:f9eeca106725 8346 #define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 8347 #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
Kojto 122:f9eeca106725 8348 #define I2C_ICR_STOPCF_Pos (5U)
Kojto 122:f9eeca106725 8349 #define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 8350 #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
Kojto 122:f9eeca106725 8351 #define I2C_ICR_BERRCF_Pos (8U)
Kojto 122:f9eeca106725 8352 #define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 8353 #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
Kojto 122:f9eeca106725 8354 #define I2C_ICR_ARLOCF_Pos (9U)
Kojto 122:f9eeca106725 8355 #define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 8356 #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
Kojto 122:f9eeca106725 8357 #define I2C_ICR_OVRCF_Pos (10U)
Kojto 122:f9eeca106725 8358 #define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 8359 #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
Kojto 122:f9eeca106725 8360 #define I2C_ICR_PECCF_Pos (11U)
Kojto 122:f9eeca106725 8361 #define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 8362 #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
Kojto 122:f9eeca106725 8363 #define I2C_ICR_TIMOUTCF_Pos (12U)
Kojto 122:f9eeca106725 8364 #define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 8365 #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
Kojto 122:f9eeca106725 8366 #define I2C_ICR_ALERTCF_Pos (13U)
Kojto 122:f9eeca106725 8367 #define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 8368 #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
Kojto 122:f9eeca106725 8369
Kojto 122:f9eeca106725 8370 /****************** Bit definition for I2C_PECR register *********************/
Kojto 122:f9eeca106725 8371 #define I2C_PECR_PEC_Pos (0U)
Kojto 122:f9eeca106725 8372 #define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 8373 #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
Kojto 122:f9eeca106725 8374
Kojto 122:f9eeca106725 8375 /****************** Bit definition for I2C_RXDR register *********************/
Kojto 122:f9eeca106725 8376 #define I2C_RXDR_RXDATA_Pos (0U)
Kojto 122:f9eeca106725 8377 #define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 8378 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
Kojto 122:f9eeca106725 8379
Kojto 122:f9eeca106725 8380 /****************** Bit definition for I2C_TXDR register *********************/
Kojto 122:f9eeca106725 8381 #define I2C_TXDR_TXDATA_Pos (0U)
Kojto 122:f9eeca106725 8382 #define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 8383 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
Kojto 122:f9eeca106725 8384
Kojto 122:f9eeca106725 8385 /******************************************************************************/
Kojto 122:f9eeca106725 8386 /* */
Kojto 122:f9eeca106725 8387 /* Independent WATCHDOG */
Kojto 122:f9eeca106725 8388 /* */
Kojto 122:f9eeca106725 8389 /******************************************************************************/
Kojto 122:f9eeca106725 8390 /******************* Bit definition for IWDG_KR register ********************/
Kojto 122:f9eeca106725 8391 #define IWDG_KR_KEY_Pos (0U)
Kojto 122:f9eeca106725 8392 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 8393 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
Kojto 122:f9eeca106725 8394
Kojto 122:f9eeca106725 8395 /******************* Bit definition for IWDG_PR register ********************/
Kojto 122:f9eeca106725 8396 #define IWDG_PR_PR_Pos (0U)
Kojto 122:f9eeca106725 8397 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
Kojto 122:f9eeca106725 8398 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
Kojto 122:f9eeca106725 8399 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8400 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 8401 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 8402
Kojto 122:f9eeca106725 8403 /******************* Bit definition for IWDG_RLR register *******************/
Kojto 122:f9eeca106725 8404 #define IWDG_RLR_RL_Pos (0U)
Kojto 122:f9eeca106725 8405 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
Kojto 122:f9eeca106725 8406 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
Kojto 122:f9eeca106725 8407
Kojto 122:f9eeca106725 8408 /******************* Bit definition for IWDG_SR register ********************/
Kojto 122:f9eeca106725 8409 #define IWDG_SR_PVU_Pos (0U)
Kojto 122:f9eeca106725 8410 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8411 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
Kojto 122:f9eeca106725 8412 #define IWDG_SR_RVU_Pos (1U)
Kojto 122:f9eeca106725 8413 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 8414 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
Kojto 122:f9eeca106725 8415 #define IWDG_SR_WVU_Pos (2U)
Kojto 122:f9eeca106725 8416 #define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 8417 #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
Kojto 122:f9eeca106725 8418
Kojto 122:f9eeca106725 8419 /******************* Bit definition for IWDG_KR register ********************/
Kojto 122:f9eeca106725 8420 #define IWDG_WINR_WIN_Pos (0U)
Kojto 122:f9eeca106725 8421 #define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
Kojto 122:f9eeca106725 8422 #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
Kojto 122:f9eeca106725 8423
Kojto 122:f9eeca106725 8424 /******************************************************************************/
Kojto 122:f9eeca106725 8425 /* */
Kojto 122:f9eeca106725 8426 /* Firewall */
Kojto 122:f9eeca106725 8427 /* */
Kojto 122:f9eeca106725 8428 /******************************************************************************/
Kojto 122:f9eeca106725 8429
Kojto 122:f9eeca106725 8430 /*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL;LSSA;LSL register */
Kojto 122:f9eeca106725 8431 #define FW_CSSA_ADD_Pos (8U)
Kojto 122:f9eeca106725 8432 #define FW_CSSA_ADD_Msk (0xFFFFU << FW_CSSA_ADD_Pos) /*!< 0x00FFFF00 */
Kojto 122:f9eeca106725 8433 #define FW_CSSA_ADD FW_CSSA_ADD_Msk /*!< Code Segment Start Address */
Kojto 122:f9eeca106725 8434 #define FW_CSL_LENG_Pos (8U)
Kojto 122:f9eeca106725 8435 #define FW_CSL_LENG_Msk (0x3FFFU << FW_CSL_LENG_Pos) /*!< 0x003FFF00 */
Kojto 122:f9eeca106725 8436 #define FW_CSL_LENG FW_CSL_LENG_Msk /*!< Code Segment Length */
Kojto 122:f9eeca106725 8437 #define FW_NVDSSA_ADD_Pos (8U)
Kojto 122:f9eeca106725 8438 #define FW_NVDSSA_ADD_Msk (0xFFFFU << FW_NVDSSA_ADD_Pos) /*!< 0x00FFFF00 */
Kojto 122:f9eeca106725 8439 #define FW_NVDSSA_ADD FW_NVDSSA_ADD_Msk /*!< Non Volatile Dat Segment Start Address */
Kojto 122:f9eeca106725 8440 #define FW_NVDSL_LENG_Pos (8U)
Kojto 122:f9eeca106725 8441 #define FW_NVDSL_LENG_Msk (0x3FFFU << FW_NVDSL_LENG_Pos) /*!< 0x003FFF00 */
Kojto 122:f9eeca106725 8442 #define FW_NVDSL_LENG FW_NVDSL_LENG_Msk /*!< Non Volatile Data Segment Length */
Kojto 122:f9eeca106725 8443 #define FW_VDSSA_ADD_Pos (6U)
Kojto 122:f9eeca106725 8444 #define FW_VDSSA_ADD_Msk (0x7FFU << FW_VDSSA_ADD_Pos) /*!< 0x0001FFC0 */
Kojto 122:f9eeca106725 8445 #define FW_VDSSA_ADD FW_VDSSA_ADD_Msk /*!< Volatile Data Segment Start Address */
Kojto 122:f9eeca106725 8446 #define FW_VDSL_LENG_Pos (6U)
Kojto 122:f9eeca106725 8447 #define FW_VDSL_LENG_Msk (0x7FFU << FW_VDSL_LENG_Pos) /*!< 0x0001FFC0 */
Kojto 122:f9eeca106725 8448 #define FW_VDSL_LENG FW_VDSL_LENG_Msk /*!< Volatile Data Segment Length */
Kojto 122:f9eeca106725 8449 #define FW_LSSA_ADD_Pos (7U)
Kojto 122:f9eeca106725 8450 #define FW_LSSA_ADD_Msk (0xFFFU << FW_LSSA_ADD_Pos) /*!< 0x0007FF80 */
Kojto 122:f9eeca106725 8451 #define FW_LSSA_ADD FW_LSSA_ADD_Msk /*!< Library Segment Start Address*/
Kojto 122:f9eeca106725 8452 #define FW_LSL_LENG_Pos (7U)
Kojto 122:f9eeca106725 8453 #define FW_LSL_LENG_Msk (0xFFFU << FW_LSL_LENG_Pos) /*!< 0x0007FF80 */
Kojto 122:f9eeca106725 8454 #define FW_LSL_LENG FW_LSL_LENG_Msk /*!< Library Segment Length*/
Kojto 122:f9eeca106725 8455
Kojto 122:f9eeca106725 8456 /**************************Bit definition for CR register *********************/
Kojto 122:f9eeca106725 8457 #define FW_CR_FPA_Pos (0U)
Kojto 122:f9eeca106725 8458 #define FW_CR_FPA_Msk (0x1U << FW_CR_FPA_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8459 #define FW_CR_FPA FW_CR_FPA_Msk /*!< Firewall Pre Arm*/
Kojto 122:f9eeca106725 8460 #define FW_CR_VDS_Pos (1U)
Kojto 122:f9eeca106725 8461 #define FW_CR_VDS_Msk (0x1U << FW_CR_VDS_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 8462 #define FW_CR_VDS FW_CR_VDS_Msk /*!< Volatile Data Sharing*/
Kojto 122:f9eeca106725 8463 #define FW_CR_VDE_Pos (2U)
Kojto 122:f9eeca106725 8464 #define FW_CR_VDE_Msk (0x1U << FW_CR_VDE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 8465 #define FW_CR_VDE FW_CR_VDE_Msk /*!< Volatile Data Execution*/
Kojto 122:f9eeca106725 8466
Kojto 122:f9eeca106725 8467 /******************************************************************************/
Kojto 122:f9eeca106725 8468 /* */
Kojto 122:f9eeca106725 8469 /* Power Control */
Kojto 122:f9eeca106725 8470 /* */
Kojto 122:f9eeca106725 8471 /******************************************************************************/
Kojto 122:f9eeca106725 8472
Kojto 122:f9eeca106725 8473 /******************** Bit definition for PWR_CR1 register ********************/
Kojto 122:f9eeca106725 8474
Kojto 122:f9eeca106725 8475 #define PWR_CR1_LPR_Pos (14U)
Kojto 122:f9eeca106725 8476 #define PWR_CR1_LPR_Msk (0x1U << PWR_CR1_LPR_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 8477 #define PWR_CR1_LPR PWR_CR1_LPR_Msk /*!< Regulator low-power mode */
Kojto 122:f9eeca106725 8478 #define PWR_CR1_VOS_Pos (9U)
Kojto 122:f9eeca106725 8479 #define PWR_CR1_VOS_Msk (0x3U << PWR_CR1_VOS_Pos) /*!< 0x00000600 */
Kojto 122:f9eeca106725 8480 #define PWR_CR1_VOS PWR_CR1_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
Kojto 122:f9eeca106725 8481 #define PWR_CR1_VOS_0 (0x1U << PWR_CR1_VOS_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 8482 #define PWR_CR1_VOS_1 (0x2U << PWR_CR1_VOS_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 8483 #define PWR_CR1_DBP_Pos (8U)
Kojto 122:f9eeca106725 8484 #define PWR_CR1_DBP_Msk (0x1U << PWR_CR1_DBP_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 8485 #define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up domain Protection */
Kojto 122:f9eeca106725 8486 #define PWR_CR1_LPMS_Pos (0U)
Kojto 122:f9eeca106725 8487 #define PWR_CR1_LPMS_Msk (0x7U << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
Kojto 122:f9eeca106725 8488 #define PWR_CR1_LPMS PWR_CR1_LPMS_Msk /*!< Low-power mode selection field */
Kojto 122:f9eeca106725 8489 #define PWR_CR1_LPMS_STOP0 (0x00000000U) /*!< Stop 0 mode */
Kojto 122:f9eeca106725 8490 #define PWR_CR1_LPMS_STOP1_Pos (0U)
Kojto 122:f9eeca106725 8491 #define PWR_CR1_LPMS_STOP1_Msk (0x1U << PWR_CR1_LPMS_STOP1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8492 #define PWR_CR1_LPMS_STOP1 PWR_CR1_LPMS_STOP1_Msk /*!< Stop 1 mode */
Kojto 122:f9eeca106725 8493 #define PWR_CR1_LPMS_STOP2_Pos (1U)
Kojto 122:f9eeca106725 8494 #define PWR_CR1_LPMS_STOP2_Msk (0x1U << PWR_CR1_LPMS_STOP2_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 8495 #define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_Msk /*!< Stop 2 mode */
Kojto 122:f9eeca106725 8496 #define PWR_CR1_LPMS_STANDBY_Pos (0U)
Kojto 122:f9eeca106725 8497 #define PWR_CR1_LPMS_STANDBY_Msk (0x3U << PWR_CR1_LPMS_STANDBY_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 8498 #define PWR_CR1_LPMS_STANDBY PWR_CR1_LPMS_STANDBY_Msk /*!< Stand-by mode */
Kojto 122:f9eeca106725 8499 #define PWR_CR1_LPMS_SHUTDOWN_Pos (2U)
Kojto 122:f9eeca106725 8500 #define PWR_CR1_LPMS_SHUTDOWN_Msk (0x1U << PWR_CR1_LPMS_SHUTDOWN_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 8501 #define PWR_CR1_LPMS_SHUTDOWN PWR_CR1_LPMS_SHUTDOWN_Msk /*!< Shut-down mode */
Kojto 122:f9eeca106725 8502
Kojto 122:f9eeca106725 8503
Kojto 122:f9eeca106725 8504 /******************** Bit definition for PWR_CR2 register ********************/
Kojto 122:f9eeca106725 8505 #define PWR_CR2_USV_Pos (10U)
Kojto 122:f9eeca106725 8506 #define PWR_CR2_USV_Msk (0x1U << PWR_CR2_USV_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 8507 #define PWR_CR2_USV PWR_CR2_USV_Msk /*!< VDD USB Supply Valid */
Kojto 122:f9eeca106725 8508 /*!< PVME Peripheral Voltage Monitor Enable */
Kojto 122:f9eeca106725 8509 #define PWR_CR2_PVME_Pos (4U)
Kojto 122:f9eeca106725 8510 #define PWR_CR2_PVME_Msk (0xDU << PWR_CR2_PVME_Pos) /*!< 0x000000D0 */
Kojto 122:f9eeca106725 8511 #define PWR_CR2_PVME PWR_CR2_PVME_Msk /*!< PVM bits field */
Kojto 122:f9eeca106725 8512 #define PWR_CR2_PVME4_Pos (7U)
Kojto 122:f9eeca106725 8513 #define PWR_CR2_PVME4_Msk (0x1U << PWR_CR2_PVME4_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 8514 #define PWR_CR2_PVME4 PWR_CR2_PVME4_Msk /*!< PVM 4 Enable */
Kojto 122:f9eeca106725 8515 #define PWR_CR2_PVME3_Pos (6U)
Kojto 122:f9eeca106725 8516 #define PWR_CR2_PVME3_Msk (0x1U << PWR_CR2_PVME3_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 8517 #define PWR_CR2_PVME3 PWR_CR2_PVME3_Msk /*!< PVM 3 Enable */
Kojto 122:f9eeca106725 8518 #define PWR_CR2_PVME1_Pos (4U)
Kojto 122:f9eeca106725 8519 #define PWR_CR2_PVME1_Msk (0x1U << PWR_CR2_PVME1_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 8520 #define PWR_CR2_PVME1 PWR_CR2_PVME1_Msk /*!< PVM 1 Enable */
Kojto 122:f9eeca106725 8521 /*!< PVD level configuration */
Kojto 122:f9eeca106725 8522 #define PWR_CR2_PLS_Pos (1U)
Kojto 122:f9eeca106725 8523 #define PWR_CR2_PLS_Msk (0x7U << PWR_CR2_PLS_Pos) /*!< 0x0000000E */
Kojto 122:f9eeca106725 8524 #define PWR_CR2_PLS PWR_CR2_PLS_Msk /*!< PVD level selection */
Kojto 122:f9eeca106725 8525 #define PWR_CR2_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
Kojto 122:f9eeca106725 8526 #define PWR_CR2_PLS_LEV1_Pos (1U)
Kojto 122:f9eeca106725 8527 #define PWR_CR2_PLS_LEV1_Msk (0x1U << PWR_CR2_PLS_LEV1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 8528 #define PWR_CR2_PLS_LEV1 PWR_CR2_PLS_LEV1_Msk /*!< PVD level 1 */
Kojto 122:f9eeca106725 8529 #define PWR_CR2_PLS_LEV2_Pos (2U)
Kojto 122:f9eeca106725 8530 #define PWR_CR2_PLS_LEV2_Msk (0x1U << PWR_CR2_PLS_LEV2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 8531 #define PWR_CR2_PLS_LEV2 PWR_CR2_PLS_LEV2_Msk /*!< PVD level 2 */
Kojto 122:f9eeca106725 8532 #define PWR_CR2_PLS_LEV3_Pos (1U)
Kojto 122:f9eeca106725 8533 #define PWR_CR2_PLS_LEV3_Msk (0x3U << PWR_CR2_PLS_LEV3_Pos) /*!< 0x00000006 */
Kojto 122:f9eeca106725 8534 #define PWR_CR2_PLS_LEV3 PWR_CR2_PLS_LEV3_Msk /*!< PVD level 3 */
Kojto 122:f9eeca106725 8535 #define PWR_CR2_PLS_LEV4_Pos (3U)
Kojto 122:f9eeca106725 8536 #define PWR_CR2_PLS_LEV4_Msk (0x1U << PWR_CR2_PLS_LEV4_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 8537 #define PWR_CR2_PLS_LEV4 PWR_CR2_PLS_LEV4_Msk /*!< PVD level 4 */
Kojto 122:f9eeca106725 8538 #define PWR_CR2_PLS_LEV5_Pos (1U)
Kojto 122:f9eeca106725 8539 #define PWR_CR2_PLS_LEV5_Msk (0x5U << PWR_CR2_PLS_LEV5_Pos) /*!< 0x0000000A */
Kojto 122:f9eeca106725 8540 #define PWR_CR2_PLS_LEV5 PWR_CR2_PLS_LEV5_Msk /*!< PVD level 5 */
Kojto 122:f9eeca106725 8541 #define PWR_CR2_PLS_LEV6_Pos (2U)
Kojto 122:f9eeca106725 8542 #define PWR_CR2_PLS_LEV6_Msk (0x3U << PWR_CR2_PLS_LEV6_Pos) /*!< 0x0000000C */
Kojto 122:f9eeca106725 8543 #define PWR_CR2_PLS_LEV6 PWR_CR2_PLS_LEV6_Msk /*!< PVD level 6 */
Kojto 122:f9eeca106725 8544 #define PWR_CR2_PLS_LEV7_Pos (1U)
Kojto 122:f9eeca106725 8545 #define PWR_CR2_PLS_LEV7_Msk (0x7U << PWR_CR2_PLS_LEV7_Pos) /*!< 0x0000000E */
Kojto 122:f9eeca106725 8546 #define PWR_CR2_PLS_LEV7 PWR_CR2_PLS_LEV7_Msk /*!< PVD level 7 */
Kojto 122:f9eeca106725 8547 #define PWR_CR2_PVDE_Pos (0U)
Kojto 122:f9eeca106725 8548 #define PWR_CR2_PVDE_Msk (0x1U << PWR_CR2_PVDE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8549 #define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Power Voltage Detector Enable */
Kojto 122:f9eeca106725 8550
Kojto 122:f9eeca106725 8551 /******************** Bit definition for PWR_CR3 register ********************/
Kojto 122:f9eeca106725 8552 #define PWR_CR3_EIWF_Pos (15U)
Kojto 122:f9eeca106725 8553 #define PWR_CR3_EIWF_Msk (0x1U << PWR_CR3_EIWF_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 8554 #define PWR_CR3_EIWF PWR_CR3_EIWF_Msk /*!< Enable Internal Wake-up line */
Kojto 122:f9eeca106725 8555 #define PWR_CR3_APC_Pos (10U)
Kojto 122:f9eeca106725 8556 #define PWR_CR3_APC_Msk (0x1U << PWR_CR3_APC_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 8557 #define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */
Kojto 122:f9eeca106725 8558 #define PWR_CR3_RRS_Pos (8U)
Kojto 122:f9eeca106725 8559 #define PWR_CR3_RRS_Msk (0x1U << PWR_CR3_RRS_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 8560 #define PWR_CR3_RRS PWR_CR3_RRS_Msk /*!< SRAM2 Retention in Stand-by mode */
Kojto 122:f9eeca106725 8561 #define PWR_CR3_EWUP5_Pos (4U)
Kojto 122:f9eeca106725 8562 #define PWR_CR3_EWUP5_Msk (0x1U << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 8563 #define PWR_CR3_EWUP5 PWR_CR3_EWUP5_Msk /*!< Enable Wake-Up Pin 5 */
Kojto 122:f9eeca106725 8564 #define PWR_CR3_EWUP4_Pos (3U)
Kojto 122:f9eeca106725 8565 #define PWR_CR3_EWUP4_Msk (0x1U << PWR_CR3_EWUP4_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 8566 #define PWR_CR3_EWUP4 PWR_CR3_EWUP4_Msk /*!< Enable Wake-Up Pin 4 */
Kojto 122:f9eeca106725 8567 #define PWR_CR3_EWUP3_Pos (2U)
Kojto 122:f9eeca106725 8568 #define PWR_CR3_EWUP3_Msk (0x1U << PWR_CR3_EWUP3_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 8569 #define PWR_CR3_EWUP3 PWR_CR3_EWUP3_Msk /*!< Enable Wake-Up Pin 3 */
Kojto 122:f9eeca106725 8570 #define PWR_CR3_EWUP2_Pos (1U)
Kojto 122:f9eeca106725 8571 #define PWR_CR3_EWUP2_Msk (0x1U << PWR_CR3_EWUP2_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 8572 #define PWR_CR3_EWUP2 PWR_CR3_EWUP2_Msk /*!< Enable Wake-Up Pin 2 */
Kojto 122:f9eeca106725 8573 #define PWR_CR3_EWUP1_Pos (0U)
Kojto 122:f9eeca106725 8574 #define PWR_CR3_EWUP1_Msk (0x1U << PWR_CR3_EWUP1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8575 #define PWR_CR3_EWUP1 PWR_CR3_EWUP1_Msk /*!< Enable Wake-Up Pin 1 */
Kojto 122:f9eeca106725 8576 #define PWR_CR3_EWUP_Pos (0U)
Kojto 122:f9eeca106725 8577 #define PWR_CR3_EWUP_Msk (0x1FU << PWR_CR3_EWUP_Pos) /*!< 0x0000001F */
Kojto 122:f9eeca106725 8578 #define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable Wake-Up Pins */
Kojto 122:f9eeca106725 8579
Kojto 122:f9eeca106725 8580 /******************** Bit definition for PWR_CR4 register ********************/
Kojto 122:f9eeca106725 8581 #define PWR_CR4_VBRS_Pos (9U)
Kojto 122:f9eeca106725 8582 #define PWR_CR4_VBRS_Msk (0x1U << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 8583 #define PWR_CR4_VBRS PWR_CR4_VBRS_Msk /*!< VBAT Battery charging Resistor Selection */
Kojto 122:f9eeca106725 8584 #define PWR_CR4_VBE_Pos (8U)
Kojto 122:f9eeca106725 8585 #define PWR_CR4_VBE_Msk (0x1U << PWR_CR4_VBE_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 8586 #define PWR_CR4_VBE PWR_CR4_VBE_Msk /*!< VBAT Battery charging Enable */
Kojto 122:f9eeca106725 8587 #define PWR_CR4_WP5_Pos (4U)
Kojto 122:f9eeca106725 8588 #define PWR_CR4_WP5_Msk (0x1U << PWR_CR4_WP5_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 8589 #define PWR_CR4_WP5 PWR_CR4_WP5_Msk /*!< Wake-Up Pin 5 polarity */
Kojto 122:f9eeca106725 8590 #define PWR_CR4_WP4_Pos (3U)
Kojto 122:f9eeca106725 8591 #define PWR_CR4_WP4_Msk (0x1U << PWR_CR4_WP4_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 8592 #define PWR_CR4_WP4 PWR_CR4_WP4_Msk /*!< Wake-Up Pin 4 polarity */
Kojto 122:f9eeca106725 8593 #define PWR_CR4_WP3_Pos (2U)
Kojto 122:f9eeca106725 8594 #define PWR_CR4_WP3_Msk (0x1U << PWR_CR4_WP3_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 8595 #define PWR_CR4_WP3 PWR_CR4_WP3_Msk /*!< Wake-Up Pin 3 polarity */
Kojto 122:f9eeca106725 8596 #define PWR_CR4_WP2_Pos (1U)
Kojto 122:f9eeca106725 8597 #define PWR_CR4_WP2_Msk (0x1U << PWR_CR4_WP2_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 8598 #define PWR_CR4_WP2 PWR_CR4_WP2_Msk /*!< Wake-Up Pin 2 polarity */
Kojto 122:f9eeca106725 8599 #define PWR_CR4_WP1_Pos (0U)
Kojto 122:f9eeca106725 8600 #define PWR_CR4_WP1_Msk (0x1U << PWR_CR4_WP1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8601 #define PWR_CR4_WP1 PWR_CR4_WP1_Msk /*!< Wake-Up Pin 1 polarity */
Kojto 122:f9eeca106725 8602
Kojto 122:f9eeca106725 8603 /******************** Bit definition for PWR_SR1 register ********************/
Kojto 122:f9eeca106725 8604 #define PWR_SR1_WUFI_Pos (15U)
Kojto 122:f9eeca106725 8605 #define PWR_SR1_WUFI_Msk (0x1U << PWR_SR1_WUFI_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 8606 #define PWR_SR1_WUFI PWR_SR1_WUFI_Msk /*!< Wake-Up Flag Internal */
Kojto 122:f9eeca106725 8607 #define PWR_SR1_SBF_Pos (8U)
Kojto 122:f9eeca106725 8608 #define PWR_SR1_SBF_Msk (0x1U << PWR_SR1_SBF_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 8609 #define PWR_SR1_SBF PWR_SR1_SBF_Msk /*!< Stand-By Flag */
Kojto 122:f9eeca106725 8610 #define PWR_SR1_WUF_Pos (0U)
Kojto 122:f9eeca106725 8611 #define PWR_SR1_WUF_Msk (0x1FU << PWR_SR1_WUF_Pos) /*!< 0x0000001F */
Kojto 122:f9eeca106725 8612 #define PWR_SR1_WUF PWR_SR1_WUF_Msk /*!< Wake-up Flags */
Kojto 122:f9eeca106725 8613 #define PWR_SR1_WUF5_Pos (4U)
Kojto 122:f9eeca106725 8614 #define PWR_SR1_WUF5_Msk (0x1U << PWR_SR1_WUF5_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 8615 #define PWR_SR1_WUF5 PWR_SR1_WUF5_Msk /*!< Wake-up Flag 5 */
Kojto 122:f9eeca106725 8616 #define PWR_SR1_WUF4_Pos (3U)
Kojto 122:f9eeca106725 8617 #define PWR_SR1_WUF4_Msk (0x1U << PWR_SR1_WUF4_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 8618 #define PWR_SR1_WUF4 PWR_SR1_WUF4_Msk /*!< Wake-up Flag 4 */
Kojto 122:f9eeca106725 8619 #define PWR_SR1_WUF3_Pos (2U)
Kojto 122:f9eeca106725 8620 #define PWR_SR1_WUF3_Msk (0x1U << PWR_SR1_WUF3_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 8621 #define PWR_SR1_WUF3 PWR_SR1_WUF3_Msk /*!< Wake-up Flag 3 */
Kojto 122:f9eeca106725 8622 #define PWR_SR1_WUF2_Pos (1U)
Kojto 122:f9eeca106725 8623 #define PWR_SR1_WUF2_Msk (0x1U << PWR_SR1_WUF2_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 8624 #define PWR_SR1_WUF2 PWR_SR1_WUF2_Msk /*!< Wake-up Flag 2 */
Kojto 122:f9eeca106725 8625 #define PWR_SR1_WUF1_Pos (0U)
Kojto 122:f9eeca106725 8626 #define PWR_SR1_WUF1_Msk (0x1U << PWR_SR1_WUF1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8627 #define PWR_SR1_WUF1 PWR_SR1_WUF1_Msk /*!< Wake-up Flag 1 */
Kojto 122:f9eeca106725 8628
Kojto 122:f9eeca106725 8629 /******************** Bit definition for PWR_SR2 register ********************/
Kojto 122:f9eeca106725 8630 #define PWR_SR2_PVMO4_Pos (15U)
Kojto 122:f9eeca106725 8631 #define PWR_SR2_PVMO4_Msk (0x1U << PWR_SR2_PVMO4_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 8632 #define PWR_SR2_PVMO4 PWR_SR2_PVMO4_Msk /*!< Peripheral Voltage Monitoring Output 4 */
Kojto 122:f9eeca106725 8633 #define PWR_SR2_PVMO3_Pos (14U)
Kojto 122:f9eeca106725 8634 #define PWR_SR2_PVMO3_Msk (0x1U << PWR_SR2_PVMO3_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 8635 #define PWR_SR2_PVMO3 PWR_SR2_PVMO3_Msk /*!< Peripheral Voltage Monitoring Output 3 */
Kojto 122:f9eeca106725 8636 #define PWR_SR2_PVMO1_Pos (12U)
Kojto 122:f9eeca106725 8637 #define PWR_SR2_PVMO1_Msk (0x1U << PWR_SR2_PVMO1_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 8638 #define PWR_SR2_PVMO1 PWR_SR2_PVMO1_Msk /*!< Peripheral Voltage Monitoring Output 1 */
Kojto 122:f9eeca106725 8639 #define PWR_SR2_PVDO_Pos (11U)
Kojto 122:f9eeca106725 8640 #define PWR_SR2_PVDO_Msk (0x1U << PWR_SR2_PVDO_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 8641 #define PWR_SR2_PVDO PWR_SR2_PVDO_Msk /*!< Power Voltage Detector Output */
Kojto 122:f9eeca106725 8642 #define PWR_SR2_VOSF_Pos (10U)
Kojto 122:f9eeca106725 8643 #define PWR_SR2_VOSF_Msk (0x1U << PWR_SR2_VOSF_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 8644 #define PWR_SR2_VOSF PWR_SR2_VOSF_Msk /*!< Voltage Scaling Flag */
Kojto 122:f9eeca106725 8645 #define PWR_SR2_REGLPF_Pos (9U)
Kojto 122:f9eeca106725 8646 #define PWR_SR2_REGLPF_Msk (0x1U << PWR_SR2_REGLPF_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 8647 #define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk /*!< Low-power Regulator Flag */
Kojto 122:f9eeca106725 8648 #define PWR_SR2_REGLPS_Pos (8U)
Kojto 122:f9eeca106725 8649 #define PWR_SR2_REGLPS_Msk (0x1U << PWR_SR2_REGLPS_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 8650 #define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk /*!< Low-power Regulator Started */
Kojto 122:f9eeca106725 8651
Kojto 122:f9eeca106725 8652 /******************** Bit definition for PWR_SCR register ********************/
Kojto 122:f9eeca106725 8653 #define PWR_SCR_CSBF_Pos (8U)
Kojto 122:f9eeca106725 8654 #define PWR_SCR_CSBF_Msk (0x1U << PWR_SCR_CSBF_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 8655 #define PWR_SCR_CSBF PWR_SCR_CSBF_Msk /*!< Clear Stand-By Flag */
Kojto 122:f9eeca106725 8656 #define PWR_SCR_CWUF_Pos (0U)
Kojto 122:f9eeca106725 8657 #define PWR_SCR_CWUF_Msk (0x1FU << PWR_SCR_CWUF_Pos) /*!< 0x0000001F */
Kojto 122:f9eeca106725 8658 #define PWR_SCR_CWUF PWR_SCR_CWUF_Msk /*!< Clear Wake-up Flags */
Kojto 122:f9eeca106725 8659 #define PWR_SCR_CWUF5_Pos (4U)
Kojto 122:f9eeca106725 8660 #define PWR_SCR_CWUF5_Msk (0x1U << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 8661 #define PWR_SCR_CWUF5 PWR_SCR_CWUF5_Msk /*!< Clear Wake-up Flag 5 */
Kojto 122:f9eeca106725 8662 #define PWR_SCR_CWUF4_Pos (3U)
Kojto 122:f9eeca106725 8663 #define PWR_SCR_CWUF4_Msk (0x1U << PWR_SCR_CWUF4_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 8664 #define PWR_SCR_CWUF4 PWR_SCR_CWUF4_Msk /*!< Clear Wake-up Flag 4 */
Kojto 122:f9eeca106725 8665 #define PWR_SCR_CWUF3_Pos (2U)
Kojto 122:f9eeca106725 8666 #define PWR_SCR_CWUF3_Msk (0x1U << PWR_SCR_CWUF3_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 8667 #define PWR_SCR_CWUF3 PWR_SCR_CWUF3_Msk /*!< Clear Wake-up Flag 3 */
Kojto 122:f9eeca106725 8668 #define PWR_SCR_CWUF2_Pos (1U)
Kojto 122:f9eeca106725 8669 #define PWR_SCR_CWUF2_Msk (0x1U << PWR_SCR_CWUF2_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 8670 #define PWR_SCR_CWUF2 PWR_SCR_CWUF2_Msk /*!< Clear Wake-up Flag 2 */
Kojto 122:f9eeca106725 8671 #define PWR_SCR_CWUF1_Pos (0U)
Kojto 122:f9eeca106725 8672 #define PWR_SCR_CWUF1_Msk (0x1U << PWR_SCR_CWUF1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8673 #define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk /*!< Clear Wake-up Flag 1 */
Kojto 122:f9eeca106725 8674
Kojto 122:f9eeca106725 8675 /******************** Bit definition for PWR_PUCRA register ********************/
Kojto 122:f9eeca106725 8676 #define PWR_PUCRA_PA15_Pos (15U)
Kojto 122:f9eeca106725 8677 #define PWR_PUCRA_PA15_Msk (0x1U << PWR_PUCRA_PA15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 8678 #define PWR_PUCRA_PA15 PWR_PUCRA_PA15_Msk /*!< Port PA15 Pull-Up set */
Kojto 122:f9eeca106725 8679 #define PWR_PUCRA_PA13_Pos (13U)
Kojto 122:f9eeca106725 8680 #define PWR_PUCRA_PA13_Msk (0x1U << PWR_PUCRA_PA13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 8681 #define PWR_PUCRA_PA13 PWR_PUCRA_PA13_Msk /*!< Port PA13 Pull-Up set */
Kojto 122:f9eeca106725 8682 #define PWR_PUCRA_PA12_Pos (12U)
Kojto 122:f9eeca106725 8683 #define PWR_PUCRA_PA12_Msk (0x1U << PWR_PUCRA_PA12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 8684 #define PWR_PUCRA_PA12 PWR_PUCRA_PA12_Msk /*!< Port PA12 Pull-Up set */
Kojto 122:f9eeca106725 8685 #define PWR_PUCRA_PA11_Pos (11U)
Kojto 122:f9eeca106725 8686 #define PWR_PUCRA_PA11_Msk (0x1U << PWR_PUCRA_PA11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 8687 #define PWR_PUCRA_PA11 PWR_PUCRA_PA11_Msk /*!< Port PA11 Pull-Up set */
Kojto 122:f9eeca106725 8688 #define PWR_PUCRA_PA10_Pos (10U)
Kojto 122:f9eeca106725 8689 #define PWR_PUCRA_PA10_Msk (0x1U << PWR_PUCRA_PA10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 8690 #define PWR_PUCRA_PA10 PWR_PUCRA_PA10_Msk /*!< Port PA10 Pull-Up set */
Kojto 122:f9eeca106725 8691 #define PWR_PUCRA_PA9_Pos (9U)
Kojto 122:f9eeca106725 8692 #define PWR_PUCRA_PA9_Msk (0x1U << PWR_PUCRA_PA9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 8693 #define PWR_PUCRA_PA9 PWR_PUCRA_PA9_Msk /*!< Port PA9 Pull-Up set */
Kojto 122:f9eeca106725 8694 #define PWR_PUCRA_PA8_Pos (8U)
Kojto 122:f9eeca106725 8695 #define PWR_PUCRA_PA8_Msk (0x1U << PWR_PUCRA_PA8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 8696 #define PWR_PUCRA_PA8 PWR_PUCRA_PA8_Msk /*!< Port PA8 Pull-Up set */
Kojto 122:f9eeca106725 8697 #define PWR_PUCRA_PA7_Pos (7U)
Kojto 122:f9eeca106725 8698 #define PWR_PUCRA_PA7_Msk (0x1U << PWR_PUCRA_PA7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 8699 #define PWR_PUCRA_PA7 PWR_PUCRA_PA7_Msk /*!< Port PA7 Pull-Up set */
Kojto 122:f9eeca106725 8700 #define PWR_PUCRA_PA6_Pos (6U)
Kojto 122:f9eeca106725 8701 #define PWR_PUCRA_PA6_Msk (0x1U << PWR_PUCRA_PA6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 8702 #define PWR_PUCRA_PA6 PWR_PUCRA_PA6_Msk /*!< Port PA6 Pull-Up set */
Kojto 122:f9eeca106725 8703 #define PWR_PUCRA_PA5_Pos (5U)
Kojto 122:f9eeca106725 8704 #define PWR_PUCRA_PA5_Msk (0x1U << PWR_PUCRA_PA5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 8705 #define PWR_PUCRA_PA5 PWR_PUCRA_PA5_Msk /*!< Port PA5 Pull-Up set */
Kojto 122:f9eeca106725 8706 #define PWR_PUCRA_PA4_Pos (4U)
Kojto 122:f9eeca106725 8707 #define PWR_PUCRA_PA4_Msk (0x1U << PWR_PUCRA_PA4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 8708 #define PWR_PUCRA_PA4 PWR_PUCRA_PA4_Msk /*!< Port PA4 Pull-Up set */
Kojto 122:f9eeca106725 8709 #define PWR_PUCRA_PA3_Pos (3U)
Kojto 122:f9eeca106725 8710 #define PWR_PUCRA_PA3_Msk (0x1U << PWR_PUCRA_PA3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 8711 #define PWR_PUCRA_PA3 PWR_PUCRA_PA3_Msk /*!< Port PA3 Pull-Up set */
Kojto 122:f9eeca106725 8712 #define PWR_PUCRA_PA2_Pos (2U)
Kojto 122:f9eeca106725 8713 #define PWR_PUCRA_PA2_Msk (0x1U << PWR_PUCRA_PA2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 8714 #define PWR_PUCRA_PA2 PWR_PUCRA_PA2_Msk /*!< Port PA2 Pull-Up set */
Kojto 122:f9eeca106725 8715 #define PWR_PUCRA_PA1_Pos (1U)
Kojto 122:f9eeca106725 8716 #define PWR_PUCRA_PA1_Msk (0x1U << PWR_PUCRA_PA1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 8717 #define PWR_PUCRA_PA1 PWR_PUCRA_PA1_Msk /*!< Port PA1 Pull-Up set */
Kojto 122:f9eeca106725 8718 #define PWR_PUCRA_PA0_Pos (0U)
Kojto 122:f9eeca106725 8719 #define PWR_PUCRA_PA0_Msk (0x1U << PWR_PUCRA_PA0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8720 #define PWR_PUCRA_PA0 PWR_PUCRA_PA0_Msk /*!< Port PA0 Pull-Up set */
Kojto 122:f9eeca106725 8721
Kojto 122:f9eeca106725 8722 /******************** Bit definition for PWR_PDCRA register ********************/
Kojto 122:f9eeca106725 8723 #define PWR_PDCRA_PA14_Pos (14U)
Kojto 122:f9eeca106725 8724 #define PWR_PDCRA_PA14_Msk (0x1U << PWR_PDCRA_PA14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 8725 #define PWR_PDCRA_PA14 PWR_PDCRA_PA14_Msk /*!< Port PA14 Pull-Down set */
Kojto 122:f9eeca106725 8726 #define PWR_PDCRA_PA12_Pos (12U)
Kojto 122:f9eeca106725 8727 #define PWR_PDCRA_PA12_Msk (0x1U << PWR_PDCRA_PA12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 8728 #define PWR_PDCRA_PA12 PWR_PDCRA_PA12_Msk /*!< Port PA12 Pull-Down set */
Kojto 122:f9eeca106725 8729 #define PWR_PDCRA_PA11_Pos (11U)
Kojto 122:f9eeca106725 8730 #define PWR_PDCRA_PA11_Msk (0x1U << PWR_PDCRA_PA11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 8731 #define PWR_PDCRA_PA11 PWR_PDCRA_PA11_Msk /*!< Port PA11 Pull-Down set */
Kojto 122:f9eeca106725 8732 #define PWR_PDCRA_PA10_Pos (10U)
Kojto 122:f9eeca106725 8733 #define PWR_PDCRA_PA10_Msk (0x1U << PWR_PDCRA_PA10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 8734 #define PWR_PDCRA_PA10 PWR_PDCRA_PA10_Msk /*!< Port PA10 Pull-Down set */
Kojto 122:f9eeca106725 8735 #define PWR_PDCRA_PA9_Pos (9U)
Kojto 122:f9eeca106725 8736 #define PWR_PDCRA_PA9_Msk (0x1U << PWR_PDCRA_PA9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 8737 #define PWR_PDCRA_PA9 PWR_PDCRA_PA9_Msk /*!< Port PA9 Pull-Down set */
Kojto 122:f9eeca106725 8738 #define PWR_PDCRA_PA8_Pos (8U)
Kojto 122:f9eeca106725 8739 #define PWR_PDCRA_PA8_Msk (0x1U << PWR_PDCRA_PA8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 8740 #define PWR_PDCRA_PA8 PWR_PDCRA_PA8_Msk /*!< Port PA8 Pull-Down set */
Kojto 122:f9eeca106725 8741 #define PWR_PDCRA_PA7_Pos (7U)
Kojto 122:f9eeca106725 8742 #define PWR_PDCRA_PA7_Msk (0x1U << PWR_PDCRA_PA7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 8743 #define PWR_PDCRA_PA7 PWR_PDCRA_PA7_Msk /*!< Port PA7 Pull-Down set */
Kojto 122:f9eeca106725 8744 #define PWR_PDCRA_PA6_Pos (6U)
Kojto 122:f9eeca106725 8745 #define PWR_PDCRA_PA6_Msk (0x1U << PWR_PDCRA_PA6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 8746 #define PWR_PDCRA_PA6 PWR_PDCRA_PA6_Msk /*!< Port PA6 Pull-Down set */
Kojto 122:f9eeca106725 8747 #define PWR_PDCRA_PA5_Pos (5U)
Kojto 122:f9eeca106725 8748 #define PWR_PDCRA_PA5_Msk (0x1U << PWR_PDCRA_PA5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 8749 #define PWR_PDCRA_PA5 PWR_PDCRA_PA5_Msk /*!< Port PA5 Pull-Down set */
Kojto 122:f9eeca106725 8750 #define PWR_PDCRA_PA4_Pos (4U)
Kojto 122:f9eeca106725 8751 #define PWR_PDCRA_PA4_Msk (0x1U << PWR_PDCRA_PA4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 8752 #define PWR_PDCRA_PA4 PWR_PDCRA_PA4_Msk /*!< Port PA4 Pull-Down set */
Kojto 122:f9eeca106725 8753 #define PWR_PDCRA_PA3_Pos (3U)
Kojto 122:f9eeca106725 8754 #define PWR_PDCRA_PA3_Msk (0x1U << PWR_PDCRA_PA3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 8755 #define PWR_PDCRA_PA3 PWR_PDCRA_PA3_Msk /*!< Port PA3 Pull-Down set */
Kojto 122:f9eeca106725 8756 #define PWR_PDCRA_PA2_Pos (2U)
Kojto 122:f9eeca106725 8757 #define PWR_PDCRA_PA2_Msk (0x1U << PWR_PDCRA_PA2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 8758 #define PWR_PDCRA_PA2 PWR_PDCRA_PA2_Msk /*!< Port PA2 Pull-Down set */
Kojto 122:f9eeca106725 8759 #define PWR_PDCRA_PA1_Pos (1U)
Kojto 122:f9eeca106725 8760 #define PWR_PDCRA_PA1_Msk (0x1U << PWR_PDCRA_PA1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 8761 #define PWR_PDCRA_PA1 PWR_PDCRA_PA1_Msk /*!< Port PA1 Pull-Down set */
Kojto 122:f9eeca106725 8762 #define PWR_PDCRA_PA0_Pos (0U)
Kojto 122:f9eeca106725 8763 #define PWR_PDCRA_PA0_Msk (0x1U << PWR_PDCRA_PA0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8764 #define PWR_PDCRA_PA0 PWR_PDCRA_PA0_Msk /*!< Port PA0 Pull-Down set */
Kojto 122:f9eeca106725 8765
Kojto 122:f9eeca106725 8766 /******************** Bit definition for PWR_PUCRB register ********************/
Kojto 122:f9eeca106725 8767 #define PWR_PUCRB_PB7_Pos (7U)
Kojto 122:f9eeca106725 8768 #define PWR_PUCRB_PB7_Msk (0x1U << PWR_PUCRB_PB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 8769 #define PWR_PUCRB_PB7 PWR_PUCRB_PB7_Msk /*!< Port PB7 Pull-Up set */
Kojto 122:f9eeca106725 8770 #define PWR_PUCRB_PB6_Pos (6U)
Kojto 122:f9eeca106725 8771 #define PWR_PUCRB_PB6_Msk (0x1U << PWR_PUCRB_PB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 8772 #define PWR_PUCRB_PB6 PWR_PUCRB_PB6_Msk /*!< Port PB6 Pull-Up set */
Kojto 122:f9eeca106725 8773 #define PWR_PUCRB_PB5_Pos (5U)
Kojto 122:f9eeca106725 8774 #define PWR_PUCRB_PB5_Msk (0x1U << PWR_PUCRB_PB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 8775 #define PWR_PUCRB_PB5 PWR_PUCRB_PB5_Msk /*!< Port PB5 Pull-Up set */
Kojto 122:f9eeca106725 8776 #define PWR_PUCRB_PB4_Pos (4U)
Kojto 122:f9eeca106725 8777 #define PWR_PUCRB_PB4_Msk (0x1U << PWR_PUCRB_PB4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 8778 #define PWR_PUCRB_PB4 PWR_PUCRB_PB4_Msk /*!< Port PB4 Pull-Up set */
Kojto 122:f9eeca106725 8779 #define PWR_PUCRB_PB3_Pos (3U)
Kojto 122:f9eeca106725 8780 #define PWR_PUCRB_PB3_Msk (0x1U << PWR_PUCRB_PB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 8781 #define PWR_PUCRB_PB3 PWR_PUCRB_PB3_Msk /*!< Port PB3 Pull-Up set */
Kojto 122:f9eeca106725 8782 #define PWR_PUCRB_PB1_Pos (1U)
Kojto 122:f9eeca106725 8783 #define PWR_PUCRB_PB1_Msk (0x1U << PWR_PUCRB_PB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 8784 #define PWR_PUCRB_PB1 PWR_PUCRB_PB1_Msk /*!< Port PB1 Pull-Up set */
Kojto 122:f9eeca106725 8785 #define PWR_PUCRB_PB0_Pos (0U)
Kojto 122:f9eeca106725 8786 #define PWR_PUCRB_PB0_Msk (0x1U << PWR_PUCRB_PB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8787 #define PWR_PUCRB_PB0 PWR_PUCRB_PB0_Msk /*!< Port PB0 Pull-Up set */
Kojto 122:f9eeca106725 8788
Kojto 122:f9eeca106725 8789 /******************** Bit definition for PWR_PDCRB register ********************/
Kojto 122:f9eeca106725 8790 #define PWR_PDCRB_PB7_Pos (7U)
Kojto 122:f9eeca106725 8791 #define PWR_PDCRB_PB7_Msk (0x1U << PWR_PDCRB_PB7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 8792 #define PWR_PDCRB_PB7 PWR_PDCRB_PB7_Msk /*!< Port PB7 Pull-Down set */
Kojto 122:f9eeca106725 8793 #define PWR_PDCRB_PB6_Pos (6U)
Kojto 122:f9eeca106725 8794 #define PWR_PDCRB_PB6_Msk (0x1U << PWR_PDCRB_PB6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 8795 #define PWR_PDCRB_PB6 PWR_PDCRB_PB6_Msk /*!< Port PB6 Pull-Down set */
Kojto 122:f9eeca106725 8796 #define PWR_PDCRB_PB5_Pos (5U)
Kojto 122:f9eeca106725 8797 #define PWR_PDCRB_PB5_Msk (0x1U << PWR_PDCRB_PB5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 8798 #define PWR_PDCRB_PB5 PWR_PDCRB_PB5_Msk /*!< Port PB5 Pull-Down set */
Kojto 122:f9eeca106725 8799 #define PWR_PDCRB_PB3_Pos (3U)
Kojto 122:f9eeca106725 8800 #define PWR_PDCRB_PB3_Msk (0x1U << PWR_PDCRB_PB3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 8801 #define PWR_PDCRB_PB3 PWR_PDCRB_PB3_Msk /*!< Port PB3 Pull-Down set */
Kojto 122:f9eeca106725 8802 #define PWR_PDCRB_PB1_Pos (1U)
Kojto 122:f9eeca106725 8803 #define PWR_PDCRB_PB1_Msk (0x1U << PWR_PDCRB_PB1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 8804 #define PWR_PDCRB_PB1 PWR_PDCRB_PB1_Msk /*!< Port PB1 Pull-Down set */
Kojto 122:f9eeca106725 8805 #define PWR_PDCRB_PB0_Pos (0U)
Kojto 122:f9eeca106725 8806 #define PWR_PDCRB_PB0_Msk (0x1U << PWR_PDCRB_PB0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8807 #define PWR_PDCRB_PB0 PWR_PDCRB_PB0_Msk /*!< Port PB0 Pull-Down set */
Kojto 122:f9eeca106725 8808
Kojto 122:f9eeca106725 8809 /******************** Bit definition for PWR_PUCRC register ********************/
Kojto 122:f9eeca106725 8810 #define PWR_PUCRC_PC15_Pos (15U)
Kojto 122:f9eeca106725 8811 #define PWR_PUCRC_PC15_Msk (0x1U << PWR_PUCRC_PC15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 8812 #define PWR_PUCRC_PC15 PWR_PUCRC_PC15_Msk /*!< Port PC15 Pull-Up set */
Kojto 122:f9eeca106725 8813 #define PWR_PUCRC_PC14_Pos (14U)
Kojto 122:f9eeca106725 8814 #define PWR_PUCRC_PC14_Msk (0x1U << PWR_PUCRC_PC14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 8815 #define PWR_PUCRC_PC14 PWR_PUCRC_PC14_Msk /*!< Port PC14 Pull-Up set */
Kojto 122:f9eeca106725 8816
Kojto 122:f9eeca106725 8817 /******************** Bit definition for PWR_PDCRC register ********************/
Kojto 122:f9eeca106725 8818 #define PWR_PDCRC_PC15_Pos (15U)
Kojto 122:f9eeca106725 8819 #define PWR_PDCRC_PC15_Msk (0x1U << PWR_PDCRC_PC15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 8820 #define PWR_PDCRC_PC15 PWR_PDCRC_PC15_Msk /*!< Port PC15 Pull-Down set */
Kojto 122:f9eeca106725 8821 #define PWR_PDCRC_PC14_Pos (14U)
Kojto 122:f9eeca106725 8822 #define PWR_PDCRC_PC14_Msk (0x1U << PWR_PDCRC_PC14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 8823 #define PWR_PDCRC_PC14 PWR_PDCRC_PC14_Msk /*!< Port PC14 Pull-Down set */
Kojto 122:f9eeca106725 8824
Kojto 122:f9eeca106725 8825
Kojto 122:f9eeca106725 8826
Kojto 122:f9eeca106725 8827
Kojto 122:f9eeca106725 8828 /******************** Bit definition for PWR_PUCRH register ********************/
Kojto 122:f9eeca106725 8829 #define PWR_PUCRH_PH3_Pos (3U)
Kojto 122:f9eeca106725 8830 #define PWR_PUCRH_PH3_Msk (0x1U << PWR_PUCRH_PH3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 8831 #define PWR_PUCRH_PH3 PWR_PUCRH_PH3_Msk /*!< Port PH3 Pull-Down set */
Kojto 122:f9eeca106725 8832
Kojto 122:f9eeca106725 8833 /******************** Bit definition for PWR_PDCRH register ********************/
Kojto 122:f9eeca106725 8834 #define PWR_PDCRH_PH3_Pos (3U)
Kojto 122:f9eeca106725 8835 #define PWR_PDCRH_PH3_Msk (0x1U << PWR_PDCRH_PH3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 8836 #define PWR_PDCRH_PH3 PWR_PDCRH_PH3_Msk /*!< Port PH3 Pull-Down set */
Kojto 122:f9eeca106725 8837
Kojto 122:f9eeca106725 8838
Kojto 122:f9eeca106725 8839 /******************************************************************************/
Kojto 122:f9eeca106725 8840 /* */
Kojto 122:f9eeca106725 8841 /* Reset and Clock Control */
Kojto 122:f9eeca106725 8842 /* */
Kojto 122:f9eeca106725 8843 /******************************************************************************/
Kojto 122:f9eeca106725 8844 /*
Kojto 122:f9eeca106725 8845 * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
Kojto 122:f9eeca106725 8846 */
Kojto 122:f9eeca106725 8847 #define RCC_HSI48_SUPPORT
Kojto 122:f9eeca106725 8848 #define RCC_PLLP_DIV_2_31_SUPPORT
Kojto 122:f9eeca106725 8849 #define RCC_PLLSAI1P_DIV_2_31_SUPPORT
Kojto 122:f9eeca106725 8850
Kojto 122:f9eeca106725 8851 /******************** Bit definition for RCC_CR register ********************/
Kojto 122:f9eeca106725 8852 #define RCC_CR_MSION_Pos (0U)
Kojto 122:f9eeca106725 8853 #define RCC_CR_MSION_Msk (0x1U << RCC_CR_MSION_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8854 #define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed oscillator (MSI) clock enable */
Kojto 122:f9eeca106725 8855 #define RCC_CR_MSIRDY_Pos (1U)
Kojto 122:f9eeca106725 8856 #define RCC_CR_MSIRDY_Msk (0x1U << RCC_CR_MSIRDY_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 8857 #define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed oscillator (MSI) clock ready flag */
Kojto 122:f9eeca106725 8858 #define RCC_CR_MSIPLLEN_Pos (2U)
Kojto 122:f9eeca106725 8859 #define RCC_CR_MSIPLLEN_Msk (0x1U << RCC_CR_MSIPLLEN_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 8860 #define RCC_CR_MSIPLLEN RCC_CR_MSIPLLEN_Msk /*!< Internal Multi Speed oscillator (MSI) PLL enable */
Kojto 122:f9eeca106725 8861 #define RCC_CR_MSIRGSEL_Pos (3U)
Kojto 122:f9eeca106725 8862 #define RCC_CR_MSIRGSEL_Msk (0x1U << RCC_CR_MSIRGSEL_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 8863 #define RCC_CR_MSIRGSEL RCC_CR_MSIRGSEL_Msk /*!< Internal Multi Speed oscillator (MSI) range selection */
Kojto 122:f9eeca106725 8864
Kojto 122:f9eeca106725 8865 /*!< MSIRANGE configuration : 12 frequency ranges available */
Kojto 122:f9eeca106725 8866 #define RCC_CR_MSIRANGE_Pos (4U)
Kojto 122:f9eeca106725 8867 #define RCC_CR_MSIRANGE_Msk (0xFU << RCC_CR_MSIRANGE_Pos) /*!< 0x000000F0 */
Kojto 122:f9eeca106725 8868 #define RCC_CR_MSIRANGE RCC_CR_MSIRANGE_Msk /*!< Internal Multi Speed oscillator (MSI) clock Range */
Kojto 122:f9eeca106725 8869 #define RCC_CR_MSIRANGE_0 (0x0U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000000 */
Kojto 122:f9eeca106725 8870 #define RCC_CR_MSIRANGE_1 (0x1U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 8871 #define RCC_CR_MSIRANGE_2 (0x2U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 8872 #define RCC_CR_MSIRANGE_3 (0x3U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000030 */
Kojto 122:f9eeca106725 8873 #define RCC_CR_MSIRANGE_4 (0x4U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 8874 #define RCC_CR_MSIRANGE_5 (0x5U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000050 */
Kojto 122:f9eeca106725 8875 #define RCC_CR_MSIRANGE_6 (0x6U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000060 */
Kojto 122:f9eeca106725 8876 #define RCC_CR_MSIRANGE_7 (0x7U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000070 */
Kojto 122:f9eeca106725 8877 #define RCC_CR_MSIRANGE_8 (0x8U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 8878 #define RCC_CR_MSIRANGE_9 (0x9U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000090 */
Kojto 122:f9eeca106725 8879 #define RCC_CR_MSIRANGE_10 (0xAU << RCC_CR_MSIRANGE_Pos) /*!< 0x000000A0 */
Kojto 122:f9eeca106725 8880 #define RCC_CR_MSIRANGE_11 (0xBU << RCC_CR_MSIRANGE_Pos) /*!< 0x000000B0 */
Kojto 122:f9eeca106725 8881
Kojto 122:f9eeca106725 8882 #define RCC_CR_HSION_Pos (8U)
Kojto 122:f9eeca106725 8883 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 8884 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed oscillator (HSI16) clock enable */
Kojto 122:f9eeca106725 8885 #define RCC_CR_HSIKERON_Pos (9U)
Kojto 122:f9eeca106725 8886 #define RCC_CR_HSIKERON_Msk (0x1U << RCC_CR_HSIKERON_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 8887 #define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
Kojto 122:f9eeca106725 8888 #define RCC_CR_HSIRDY_Pos (10U)
Kojto 122:f9eeca106725 8889 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 8890 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed oscillator (HSI16) clock ready flag */
Kojto 122:f9eeca106725 8891 #define RCC_CR_HSIASFS_Pos (11U)
Kojto 122:f9eeca106725 8892 #define RCC_CR_HSIASFS_Msk (0x1U << RCC_CR_HSIASFS_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 8893 #define RCC_CR_HSIASFS RCC_CR_HSIASFS_Msk /*!< HSI16 Automatic Start from Stop */
Kojto 122:f9eeca106725 8894
Kojto 122:f9eeca106725 8895 #define RCC_CR_HSEON_Pos (16U)
Kojto 122:f9eeca106725 8896 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 8897 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed oscillator (HSE) clock enable */
Kojto 122:f9eeca106725 8898 #define RCC_CR_HSERDY_Pos (17U)
Kojto 122:f9eeca106725 8899 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 8900 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed oscillator (HSE) clock ready */
Kojto 122:f9eeca106725 8901 #define RCC_CR_HSEBYP_Pos (18U)
Kojto 122:f9eeca106725 8902 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 8903 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed oscillator (HSE) clock bypass */
Kojto 122:f9eeca106725 8904 #define RCC_CR_CSSON_Pos (19U)
Kojto 122:f9eeca106725 8905 #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 8906 #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< HSE Clock Security System enable */
Kojto 122:f9eeca106725 8907
Kojto 122:f9eeca106725 8908 #define RCC_CR_PLLON_Pos (24U)
Kojto 122:f9eeca106725 8909 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 8910 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< System PLL clock enable */
Kojto 122:f9eeca106725 8911 #define RCC_CR_PLLRDY_Pos (25U)
Kojto 122:f9eeca106725 8912 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 8913 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */
Kojto 122:f9eeca106725 8914 #define RCC_CR_PLLSAI1ON_Pos (26U)
Kojto 122:f9eeca106725 8915 #define RCC_CR_PLLSAI1ON_Msk (0x1U << RCC_CR_PLLSAI1ON_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 8916 #define RCC_CR_PLLSAI1ON RCC_CR_PLLSAI1ON_Msk /*!< SAI1 PLL enable */
Kojto 122:f9eeca106725 8917 #define RCC_CR_PLLSAI1RDY_Pos (27U)
Kojto 122:f9eeca106725 8918 #define RCC_CR_PLLSAI1RDY_Msk (0x1U << RCC_CR_PLLSAI1RDY_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 8919 #define RCC_CR_PLLSAI1RDY RCC_CR_PLLSAI1RDY_Msk /*!< SAI1 PLL ready */
Kojto 122:f9eeca106725 8920
Kojto 122:f9eeca106725 8921 /******************** Bit definition for RCC_ICSCR register ***************/
Kojto 122:f9eeca106725 8922 /*!< MSICAL configuration */
Kojto 122:f9eeca106725 8923 #define RCC_ICSCR_MSICAL_Pos (0U)
Kojto 122:f9eeca106725 8924 #define RCC_ICSCR_MSICAL_Msk (0xFFU << RCC_ICSCR_MSICAL_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 8925 #define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< MSICAL[7:0] bits */
Kojto 122:f9eeca106725 8926 #define RCC_ICSCR_MSICAL_0 (0x01U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8927 #define RCC_ICSCR_MSICAL_1 (0x02U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 8928 #define RCC_ICSCR_MSICAL_2 (0x04U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 8929 #define RCC_ICSCR_MSICAL_3 (0x08U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 8930 #define RCC_ICSCR_MSICAL_4 (0x10U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 8931 #define RCC_ICSCR_MSICAL_5 (0x20U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 8932 #define RCC_ICSCR_MSICAL_6 (0x40U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 8933 #define RCC_ICSCR_MSICAL_7 (0x80U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 8934
Kojto 122:f9eeca106725 8935 /*!< MSITRIM configuration */
Kojto 122:f9eeca106725 8936 #define RCC_ICSCR_MSITRIM_Pos (8U)
Kojto 122:f9eeca106725 8937 #define RCC_ICSCR_MSITRIM_Msk (0xFFU << RCC_ICSCR_MSITRIM_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 8938 #define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< MSITRIM[7:0] bits */
Kojto 122:f9eeca106725 8939 #define RCC_ICSCR_MSITRIM_0 (0x01U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 8940 #define RCC_ICSCR_MSITRIM_1 (0x02U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 8941 #define RCC_ICSCR_MSITRIM_2 (0x04U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 8942 #define RCC_ICSCR_MSITRIM_3 (0x08U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 8943 #define RCC_ICSCR_MSITRIM_4 (0x10U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 8944 #define RCC_ICSCR_MSITRIM_5 (0x20U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 8945 #define RCC_ICSCR_MSITRIM_6 (0x40U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 8946 #define RCC_ICSCR_MSITRIM_7 (0x80U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 8947
Kojto 122:f9eeca106725 8948 /*!< HSICAL configuration */
Kojto 122:f9eeca106725 8949 #define RCC_ICSCR_HSICAL_Pos (16U)
Kojto 122:f9eeca106725 8950 #define RCC_ICSCR_HSICAL_Msk (0xFFU << RCC_ICSCR_HSICAL_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 8951 #define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< HSICAL[7:0] bits */
Kojto 122:f9eeca106725 8952 #define RCC_ICSCR_HSICAL_0 (0x01U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 8953 #define RCC_ICSCR_HSICAL_1 (0x02U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 8954 #define RCC_ICSCR_HSICAL_2 (0x04U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 8955 #define RCC_ICSCR_HSICAL_3 (0x08U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 8956 #define RCC_ICSCR_HSICAL_4 (0x10U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 8957 #define RCC_ICSCR_HSICAL_5 (0x20U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 8958 #define RCC_ICSCR_HSICAL_6 (0x40U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 8959 #define RCC_ICSCR_HSICAL_7 (0x80U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 8960
Kojto 122:f9eeca106725 8961 /*!< HSITRIM configuration */
Kojto 122:f9eeca106725 8962 #define RCC_ICSCR_HSITRIM_Pos (24U)
Kojto 122:f9eeca106725 8963 #define RCC_ICSCR_HSITRIM_Msk (0x1FU << RCC_ICSCR_HSITRIM_Pos) /*!< 0x1F000000 */
Kojto 122:f9eeca106725 8964 #define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[4:0] bits */
Kojto 122:f9eeca106725 8965 #define RCC_ICSCR_HSITRIM_0 (0x01U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 8966 #define RCC_ICSCR_HSITRIM_1 (0x02U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 8967 #define RCC_ICSCR_HSITRIM_2 (0x04U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 8968 #define RCC_ICSCR_HSITRIM_3 (0x08U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 8969 #define RCC_ICSCR_HSITRIM_4 (0x10U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 8970
Kojto 122:f9eeca106725 8971 /******************** Bit definition for RCC_CFGR register ******************/
Kojto 122:f9eeca106725 8972 /*!< SW configuration */
Kojto 122:f9eeca106725 8973 #define RCC_CFGR_SW_Pos (0U)
Kojto 122:f9eeca106725 8974 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 8975 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
Kojto 122:f9eeca106725 8976 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 8977 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 8978
Kojto 122:f9eeca106725 8979 #define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI oscillator selection as system clock */
Kojto 122:f9eeca106725 8980 #define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI16 oscillator selection as system clock */
Kojto 122:f9eeca106725 8981 #define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE oscillator selection as system clock */
Kojto 122:f9eeca106725 8982 #define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selection as system clock */
Kojto 122:f9eeca106725 8983
Kojto 122:f9eeca106725 8984 /*!< SWS configuration */
Kojto 122:f9eeca106725 8985 #define RCC_CFGR_SWS_Pos (2U)
Kojto 122:f9eeca106725 8986 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
Kojto 122:f9eeca106725 8987 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
Kojto 122:f9eeca106725 8988 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 8989 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 8990
Kojto 122:f9eeca106725 8991 #define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */
Kojto 122:f9eeca106725 8992 #define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI16 oscillator used as system clock */
Kojto 122:f9eeca106725 8993 #define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */
Kojto 122:f9eeca106725 8994 #define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */
Kojto 122:f9eeca106725 8995
Kojto 122:f9eeca106725 8996 /*!< HPRE configuration */
Kojto 122:f9eeca106725 8997 #define RCC_CFGR_HPRE_Pos (4U)
Kojto 122:f9eeca106725 8998 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
Kojto 122:f9eeca106725 8999 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
Kojto 122:f9eeca106725 9000 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 9001 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 9002 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 9003 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 9004
Kojto 122:f9eeca106725 9005 #define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
Kojto 122:f9eeca106725 9006 #define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
Kojto 122:f9eeca106725 9007 #define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
Kojto 122:f9eeca106725 9008 #define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
Kojto 122:f9eeca106725 9009 #define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
Kojto 122:f9eeca106725 9010 #define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
Kojto 122:f9eeca106725 9011 #define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
Kojto 122:f9eeca106725 9012 #define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
Kojto 122:f9eeca106725 9013 #define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
Kojto 122:f9eeca106725 9014
Kojto 122:f9eeca106725 9015 /*!< PPRE1 configuration */
Kojto 122:f9eeca106725 9016 #define RCC_CFGR_PPRE1_Pos (8U)
Kojto 122:f9eeca106725 9017 #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
Kojto 122:f9eeca106725 9018 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB2 prescaler) */
Kojto 122:f9eeca106725 9019 #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 9020 #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 9021 #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 9022
Kojto 122:f9eeca106725 9023 #define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
Kojto 122:f9eeca106725 9024 #define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
Kojto 122:f9eeca106725 9025 #define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
Kojto 122:f9eeca106725 9026 #define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
Kojto 122:f9eeca106725 9027 #define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
Kojto 122:f9eeca106725 9028
Kojto 122:f9eeca106725 9029 /*!< PPRE2 configuration */
Kojto 122:f9eeca106725 9030 #define RCC_CFGR_PPRE2_Pos (11U)
Kojto 122:f9eeca106725 9031 #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
Kojto 122:f9eeca106725 9032 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
Kojto 122:f9eeca106725 9033 #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 9034 #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 9035 #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 9036
Kojto 122:f9eeca106725 9037 #define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
Kojto 122:f9eeca106725 9038 #define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
Kojto 122:f9eeca106725 9039 #define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
Kojto 122:f9eeca106725 9040 #define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
Kojto 122:f9eeca106725 9041 #define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
Kojto 122:f9eeca106725 9042
Kojto 122:f9eeca106725 9043 #define RCC_CFGR_STOPWUCK_Pos (15U)
Kojto 122:f9eeca106725 9044 #define RCC_CFGR_STOPWUCK_Msk (0x1U << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 9045 #define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from stop and CSS backup clock selection */
Kojto 122:f9eeca106725 9046
Kojto 122:f9eeca106725 9047 /*!< MCOSEL configuration */
Kojto 122:f9eeca106725 9048 #define RCC_CFGR_MCOSEL_Pos (24U)
Kojto 122:f9eeca106725 9049 #define RCC_CFGR_MCOSEL_Msk (0xFU << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */
Kojto 122:f9eeca106725 9050 #define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCOSEL [3:0] bits (Clock output selection) */
Kojto 122:f9eeca106725 9051 #define RCC_CFGR_MCOSEL_0 (0x1U << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 9052 #define RCC_CFGR_MCOSEL_1 (0x2U << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 9053 #define RCC_CFGR_MCOSEL_2 (0x4U << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 9054 #define RCC_CFGR_MCOSEL_3 (0x8U << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 9055
Kojto 122:f9eeca106725 9056 #define RCC_CFGR_MCOPRE_Pos (28U)
Kojto 122:f9eeca106725 9057 #define RCC_CFGR_MCOPRE_Msk (0x7U << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
Kojto 122:f9eeca106725 9058 #define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
Kojto 122:f9eeca106725 9059 #define RCC_CFGR_MCOPRE_0 (0x1U << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 9060 #define RCC_CFGR_MCOPRE_1 (0x2U << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 9061 #define RCC_CFGR_MCOPRE_2 (0x4U << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 9062
Kojto 122:f9eeca106725 9063 #define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
Kojto 122:f9eeca106725 9064 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
Kojto 122:f9eeca106725 9065 #define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
Kojto 122:f9eeca106725 9066 #define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
Kojto 122:f9eeca106725 9067 #define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
Kojto 122:f9eeca106725 9068
Kojto 122:f9eeca106725 9069 /* Legacy aliases */
Kojto 122:f9eeca106725 9070 #define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE
Kojto 122:f9eeca106725 9071 #define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1
Kojto 122:f9eeca106725 9072 #define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2
Kojto 122:f9eeca106725 9073 #define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4
Kojto 122:f9eeca106725 9074 #define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8
Kojto 122:f9eeca106725 9075 #define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16
Kojto 122:f9eeca106725 9076
Kojto 122:f9eeca106725 9077 /******************** Bit definition for RCC_PLLCFGR register ***************/
Kojto 122:f9eeca106725 9078 #define RCC_PLLCFGR_PLLSRC_Pos (0U)
Kojto 122:f9eeca106725 9079 #define RCC_PLLCFGR_PLLSRC_Msk (0x3U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 9080 #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
Kojto 122:f9eeca106725 9081
Kojto 122:f9eeca106725 9082 #define RCC_PLLCFGR_PLLSRC_MSI_Pos (0U)
Kojto 122:f9eeca106725 9083 #define RCC_PLLCFGR_PLLSRC_MSI_Msk (0x1U << RCC_PLLCFGR_PLLSRC_MSI_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9084 #define RCC_PLLCFGR_PLLSRC_MSI RCC_PLLCFGR_PLLSRC_MSI_Msk /*!< MSI oscillator source clock selected */
Kojto 122:f9eeca106725 9085 #define RCC_PLLCFGR_PLLSRC_HSI_Pos (1U)
Kojto 122:f9eeca106725 9086 #define RCC_PLLCFGR_PLLSRC_HSI_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSI_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9087 #define RCC_PLLCFGR_PLLSRC_HSI RCC_PLLCFGR_PLLSRC_HSI_Msk /*!< HSI16 oscillator source clock selected */
Kojto 122:f9eeca106725 9088 #define RCC_PLLCFGR_PLLSRC_HSE_Pos (0U)
Kojto 122:f9eeca106725 9089 #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x3U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 9090 #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk /*!< HSE oscillator source clock selected */
Kojto 122:f9eeca106725 9091
Kojto 122:f9eeca106725 9092 #define RCC_PLLCFGR_PLLM_Pos (4U)
Kojto 122:f9eeca106725 9093 #define RCC_PLLCFGR_PLLM_Msk (0x7U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000070 */
Kojto 122:f9eeca106725 9094 #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
Kojto 122:f9eeca106725 9095 #define RCC_PLLCFGR_PLLM_0 (0x1U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 9096 #define RCC_PLLCFGR_PLLM_1 (0x2U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 9097 #define RCC_PLLCFGR_PLLM_2 (0x4U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 9098
Kojto 122:f9eeca106725 9099 #define RCC_PLLCFGR_PLLN_Pos (8U)
Kojto 122:f9eeca106725 9100 #define RCC_PLLCFGR_PLLN_Msk (0x7FU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007F00 */
Kojto 122:f9eeca106725 9101 #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
Kojto 122:f9eeca106725 9102 #define RCC_PLLCFGR_PLLN_0 (0x01U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 9103 #define RCC_PLLCFGR_PLLN_1 (0x02U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 9104 #define RCC_PLLCFGR_PLLN_2 (0x04U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 9105 #define RCC_PLLCFGR_PLLN_3 (0x08U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 9106 #define RCC_PLLCFGR_PLLN_4 (0x10U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 9107 #define RCC_PLLCFGR_PLLN_5 (0x20U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 9108 #define RCC_PLLCFGR_PLLN_6 (0x40U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 9109
Kojto 122:f9eeca106725 9110 #define RCC_PLLCFGR_PLLPEN_Pos (16U)
Kojto 122:f9eeca106725 9111 #define RCC_PLLCFGR_PLLPEN_Msk (0x1U << RCC_PLLCFGR_PLLPEN_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 9112 #define RCC_PLLCFGR_PLLPEN RCC_PLLCFGR_PLLPEN_Msk
Kojto 122:f9eeca106725 9113 #define RCC_PLLCFGR_PLLP_Pos (17U)
Kojto 122:f9eeca106725 9114 #define RCC_PLLCFGR_PLLP_Msk (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 9115 #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
Kojto 122:f9eeca106725 9116 #define RCC_PLLCFGR_PLLQEN_Pos (20U)
Kojto 122:f9eeca106725 9117 #define RCC_PLLCFGR_PLLQEN_Msk (0x1U << RCC_PLLCFGR_PLLQEN_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 9118 #define RCC_PLLCFGR_PLLQEN RCC_PLLCFGR_PLLQEN_Msk
Kojto 122:f9eeca106725 9119
Kojto 122:f9eeca106725 9120 #define RCC_PLLCFGR_PLLQ_Pos (21U)
Kojto 122:f9eeca106725 9121 #define RCC_PLLCFGR_PLLQ_Msk (0x3U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00600000 */
Kojto 122:f9eeca106725 9122 #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
Kojto 122:f9eeca106725 9123 #define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 9124 #define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 9125
Kojto 122:f9eeca106725 9126 #define RCC_PLLCFGR_PLLREN_Pos (24U)
Kojto 122:f9eeca106725 9127 #define RCC_PLLCFGR_PLLREN_Msk (0x1U << RCC_PLLCFGR_PLLREN_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 9128 #define RCC_PLLCFGR_PLLREN RCC_PLLCFGR_PLLREN_Msk
Kojto 122:f9eeca106725 9129 #define RCC_PLLCFGR_PLLR_Pos (25U)
Kojto 122:f9eeca106725 9130 #define RCC_PLLCFGR_PLLR_Msk (0x3U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x06000000 */
Kojto 122:f9eeca106725 9131 #define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
Kojto 122:f9eeca106725 9132 #define RCC_PLLCFGR_PLLR_0 (0x1U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 9133 #define RCC_PLLCFGR_PLLR_1 (0x2U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 9134
Kojto 122:f9eeca106725 9135 #define RCC_PLLCFGR_PLLPDIV_Pos (27U)
Kojto 122:f9eeca106725 9136 #define RCC_PLLCFGR_PLLPDIV_Msk (0x1FU << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0xF8000000 */
Kojto 122:f9eeca106725 9137 #define RCC_PLLCFGR_PLLPDIV RCC_PLLCFGR_PLLPDIV_Msk
Kojto 122:f9eeca106725 9138 #define RCC_PLLCFGR_PLLPDIV_0 (0x01U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 9139 #define RCC_PLLCFGR_PLLPDIV_1 (0x02U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 9140 #define RCC_PLLCFGR_PLLPDIV_2 (0x04U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 9141 #define RCC_PLLCFGR_PLLPDIV_3 (0x08U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 9142 #define RCC_PLLCFGR_PLLPDIV_4 (0x10U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 9143
Kojto 122:f9eeca106725 9144 /******************** Bit definition for RCC_PLLSAI1CFGR register ************/
Kojto 122:f9eeca106725 9145 #define RCC_PLLSAI1CFGR_PLLSAI1N_Pos (8U)
Kojto 122:f9eeca106725 9146 #define RCC_PLLSAI1CFGR_PLLSAI1N_Msk (0x7FU << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00007F00 */
Kojto 122:f9eeca106725 9147 #define RCC_PLLSAI1CFGR_PLLSAI1N RCC_PLLSAI1CFGR_PLLSAI1N_Msk
Kojto 122:f9eeca106725 9148 #define RCC_PLLSAI1CFGR_PLLSAI1N_0 (0x01U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 9149 #define RCC_PLLSAI1CFGR_PLLSAI1N_1 (0x02U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 9150 #define RCC_PLLSAI1CFGR_PLLSAI1N_2 (0x04U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 9151 #define RCC_PLLSAI1CFGR_PLLSAI1N_3 (0x08U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 9152 #define RCC_PLLSAI1CFGR_PLLSAI1N_4 (0x10U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 9153 #define RCC_PLLSAI1CFGR_PLLSAI1N_5 (0x20U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 9154 #define RCC_PLLSAI1CFGR_PLLSAI1N_6 (0x40U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 9155
Kojto 122:f9eeca106725 9156 #define RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos (16U)
Kojto 122:f9eeca106725 9157 #define RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 9158 #define RCC_PLLSAI1CFGR_PLLSAI1PEN RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk
Kojto 122:f9eeca106725 9159 #define RCC_PLLSAI1CFGR_PLLSAI1P_Pos (17U)
Kojto 122:f9eeca106725 9160 #define RCC_PLLSAI1CFGR_PLLSAI1P_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 9161 #define RCC_PLLSAI1CFGR_PLLSAI1P RCC_PLLSAI1CFGR_PLLSAI1P_Msk
Kojto 122:f9eeca106725 9162
Kojto 122:f9eeca106725 9163 #define RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos (20U)
Kojto 122:f9eeca106725 9164 #define RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 9165 #define RCC_PLLSAI1CFGR_PLLSAI1QEN RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk
Kojto 122:f9eeca106725 9166 #define RCC_PLLSAI1CFGR_PLLSAI1Q_Pos (21U)
Kojto 122:f9eeca106725 9167 #define RCC_PLLSAI1CFGR_PLLSAI1Q_Msk (0x3U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00600000 */
Kojto 122:f9eeca106725 9168 #define RCC_PLLSAI1CFGR_PLLSAI1Q RCC_PLLSAI1CFGR_PLLSAI1Q_Msk
Kojto 122:f9eeca106725 9169 #define RCC_PLLSAI1CFGR_PLLSAI1Q_0 (0x1U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 9170 #define RCC_PLLSAI1CFGR_PLLSAI1Q_1 (0x2U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 9171
Kojto 122:f9eeca106725 9172 #define RCC_PLLSAI1CFGR_PLLSAI1REN_Pos (24U)
Kojto 122:f9eeca106725 9173 #define RCC_PLLSAI1CFGR_PLLSAI1REN_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1REN_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 9174 #define RCC_PLLSAI1CFGR_PLLSAI1REN RCC_PLLSAI1CFGR_PLLSAI1REN_Msk
Kojto 122:f9eeca106725 9175 #define RCC_PLLSAI1CFGR_PLLSAI1R_Pos (25U)
Kojto 122:f9eeca106725 9176 #define RCC_PLLSAI1CFGR_PLLSAI1R_Msk (0x3U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x06000000 */
Kojto 122:f9eeca106725 9177 #define RCC_PLLSAI1CFGR_PLLSAI1R RCC_PLLSAI1CFGR_PLLSAI1R_Msk
Kojto 122:f9eeca106725 9178 #define RCC_PLLSAI1CFGR_PLLSAI1R_0 (0x1U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 9179 #define RCC_PLLSAI1CFGR_PLLSAI1R_1 (0x2U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 9180
Kojto 122:f9eeca106725 9181 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos (27U)
Kojto 122:f9eeca106725 9182 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_Msk (0x1FU << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0xF8000000 */
Kojto 122:f9eeca106725 9183 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV RCC_PLLSAI1CFGR_PLLSAI1PDIV_Msk
Kojto 122:f9eeca106725 9184 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_0 (0x01U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 9185 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_1 (0x02U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 9186 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_2 (0x04U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 9187 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_3 (0x08U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 9188 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_4 (0x10U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 9189
Kojto 122:f9eeca106725 9190 /******************** Bit definition for RCC_CIER register ******************/
Kojto 122:f9eeca106725 9191 #define RCC_CIER_LSIRDYIE_Pos (0U)
Kojto 122:f9eeca106725 9192 #define RCC_CIER_LSIRDYIE_Msk (0x1U << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9193 #define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk
Kojto 122:f9eeca106725 9194 #define RCC_CIER_LSERDYIE_Pos (1U)
Kojto 122:f9eeca106725 9195 #define RCC_CIER_LSERDYIE_Msk (0x1U << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9196 #define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk
Kojto 122:f9eeca106725 9197 #define RCC_CIER_MSIRDYIE_Pos (2U)
Kojto 122:f9eeca106725 9198 #define RCC_CIER_MSIRDYIE_Msk (0x1U << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9199 #define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk
Kojto 122:f9eeca106725 9200 #define RCC_CIER_HSIRDYIE_Pos (3U)
Kojto 122:f9eeca106725 9201 #define RCC_CIER_HSIRDYIE_Msk (0x1U << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 9202 #define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk
Kojto 122:f9eeca106725 9203 #define RCC_CIER_HSERDYIE_Pos (4U)
Kojto 122:f9eeca106725 9204 #define RCC_CIER_HSERDYIE_Msk (0x1U << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 9205 #define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk
Kojto 122:f9eeca106725 9206 #define RCC_CIER_PLLRDYIE_Pos (5U)
Kojto 122:f9eeca106725 9207 #define RCC_CIER_PLLRDYIE_Msk (0x1U << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 9208 #define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk
Kojto 122:f9eeca106725 9209 #define RCC_CIER_PLLSAI1RDYIE_Pos (6U)
Kojto 122:f9eeca106725 9210 #define RCC_CIER_PLLSAI1RDYIE_Msk (0x1U << RCC_CIER_PLLSAI1RDYIE_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 9211 #define RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE_Msk
Kojto 122:f9eeca106725 9212 #define RCC_CIER_LSECSSIE_Pos (9U)
Kojto 122:f9eeca106725 9213 #define RCC_CIER_LSECSSIE_Msk (0x1U << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 9214 #define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk
Kojto 122:f9eeca106725 9215 #define RCC_CIER_HSI48RDYIE_Pos (10U)
Kojto 122:f9eeca106725 9216 #define RCC_CIER_HSI48RDYIE_Msk (0x1U << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 9217 #define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk
Kojto 122:f9eeca106725 9218
Kojto 122:f9eeca106725 9219 /******************** Bit definition for RCC_CIFR register ******************/
Kojto 122:f9eeca106725 9220 #define RCC_CIFR_LSIRDYF_Pos (0U)
Kojto 122:f9eeca106725 9221 #define RCC_CIFR_LSIRDYF_Msk (0x1U << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9222 #define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk
Kojto 122:f9eeca106725 9223 #define RCC_CIFR_LSERDYF_Pos (1U)
Kojto 122:f9eeca106725 9224 #define RCC_CIFR_LSERDYF_Msk (0x1U << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9225 #define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk
Kojto 122:f9eeca106725 9226 #define RCC_CIFR_MSIRDYF_Pos (2U)
Kojto 122:f9eeca106725 9227 #define RCC_CIFR_MSIRDYF_Msk (0x1U << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9228 #define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk
Kojto 122:f9eeca106725 9229 #define RCC_CIFR_HSIRDYF_Pos (3U)
Kojto 122:f9eeca106725 9230 #define RCC_CIFR_HSIRDYF_Msk (0x1U << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 9231 #define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk
Kojto 122:f9eeca106725 9232 #define RCC_CIFR_HSERDYF_Pos (4U)
Kojto 122:f9eeca106725 9233 #define RCC_CIFR_HSERDYF_Msk (0x1U << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 9234 #define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk
Kojto 122:f9eeca106725 9235 #define RCC_CIFR_PLLRDYF_Pos (5U)
Kojto 122:f9eeca106725 9236 #define RCC_CIFR_PLLRDYF_Msk (0x1U << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 9237 #define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk
Kojto 122:f9eeca106725 9238 #define RCC_CIFR_PLLSAI1RDYF_Pos (6U)
Kojto 122:f9eeca106725 9239 #define RCC_CIFR_PLLSAI1RDYF_Msk (0x1U << RCC_CIFR_PLLSAI1RDYF_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 9240 #define RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF_Msk
Kojto 122:f9eeca106725 9241 #define RCC_CIFR_CSSF_Pos (8U)
Kojto 122:f9eeca106725 9242 #define RCC_CIFR_CSSF_Msk (0x1U << RCC_CIFR_CSSF_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 9243 #define RCC_CIFR_CSSF RCC_CIFR_CSSF_Msk
Kojto 122:f9eeca106725 9244 #define RCC_CIFR_LSECSSF_Pos (9U)
Kojto 122:f9eeca106725 9245 #define RCC_CIFR_LSECSSF_Msk (0x1U << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 9246 #define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk
Kojto 122:f9eeca106725 9247 #define RCC_CIFR_HSI48RDYF_Pos (10U)
Kojto 122:f9eeca106725 9248 #define RCC_CIFR_HSI48RDYF_Msk (0x1U << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 9249 #define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk
Kojto 122:f9eeca106725 9250
Kojto 122:f9eeca106725 9251 /******************** Bit definition for RCC_CICR register ******************/
Kojto 122:f9eeca106725 9252 #define RCC_CICR_LSIRDYC_Pos (0U)
Kojto 122:f9eeca106725 9253 #define RCC_CICR_LSIRDYC_Msk (0x1U << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9254 #define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk
Kojto 122:f9eeca106725 9255 #define RCC_CICR_LSERDYC_Pos (1U)
Kojto 122:f9eeca106725 9256 #define RCC_CICR_LSERDYC_Msk (0x1U << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9257 #define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk
Kojto 122:f9eeca106725 9258 #define RCC_CICR_MSIRDYC_Pos (2U)
Kojto 122:f9eeca106725 9259 #define RCC_CICR_MSIRDYC_Msk (0x1U << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9260 #define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk
Kojto 122:f9eeca106725 9261 #define RCC_CICR_HSIRDYC_Pos (3U)
Kojto 122:f9eeca106725 9262 #define RCC_CICR_HSIRDYC_Msk (0x1U << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 9263 #define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk
Kojto 122:f9eeca106725 9264 #define RCC_CICR_HSERDYC_Pos (4U)
Kojto 122:f9eeca106725 9265 #define RCC_CICR_HSERDYC_Msk (0x1U << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 9266 #define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk
Kojto 122:f9eeca106725 9267 #define RCC_CICR_PLLRDYC_Pos (5U)
Kojto 122:f9eeca106725 9268 #define RCC_CICR_PLLRDYC_Msk (0x1U << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 9269 #define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk
Kojto 122:f9eeca106725 9270 #define RCC_CICR_PLLSAI1RDYC_Pos (6U)
Kojto 122:f9eeca106725 9271 #define RCC_CICR_PLLSAI1RDYC_Msk (0x1U << RCC_CICR_PLLSAI1RDYC_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 9272 #define RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC_Msk
Kojto 122:f9eeca106725 9273 #define RCC_CICR_CSSC_Pos (8U)
Kojto 122:f9eeca106725 9274 #define RCC_CICR_CSSC_Msk (0x1U << RCC_CICR_CSSC_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 9275 #define RCC_CICR_CSSC RCC_CICR_CSSC_Msk
Kojto 122:f9eeca106725 9276 #define RCC_CICR_LSECSSC_Pos (9U)
Kojto 122:f9eeca106725 9277 #define RCC_CICR_LSECSSC_Msk (0x1U << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 9278 #define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk
Kojto 122:f9eeca106725 9279 #define RCC_CICR_HSI48RDYC_Pos (10U)
Kojto 122:f9eeca106725 9280 #define RCC_CICR_HSI48RDYC_Msk (0x1U << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 9281 #define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk
Kojto 122:f9eeca106725 9282
Kojto 122:f9eeca106725 9283 /******************** Bit definition for RCC_AHB1RSTR register **************/
Kojto 122:f9eeca106725 9284 #define RCC_AHB1RSTR_DMA1RST_Pos (0U)
Kojto 122:f9eeca106725 9285 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9286 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
Kojto 122:f9eeca106725 9287 #define RCC_AHB1RSTR_DMA2RST_Pos (1U)
Kojto 122:f9eeca106725 9288 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9289 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
Kojto 122:f9eeca106725 9290 #define RCC_AHB1RSTR_FLASHRST_Pos (8U)
Kojto 122:f9eeca106725 9291 #define RCC_AHB1RSTR_FLASHRST_Msk (0x1U << RCC_AHB1RSTR_FLASHRST_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 9292 #define RCC_AHB1RSTR_FLASHRST RCC_AHB1RSTR_FLASHRST_Msk
Kojto 122:f9eeca106725 9293 #define RCC_AHB1RSTR_CRCRST_Pos (12U)
Kojto 122:f9eeca106725 9294 #define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 9295 #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
Kojto 122:f9eeca106725 9296 #define RCC_AHB1RSTR_TSCRST_Pos (16U)
Kojto 122:f9eeca106725 9297 #define RCC_AHB1RSTR_TSCRST_Msk (0x1U << RCC_AHB1RSTR_TSCRST_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 9298 #define RCC_AHB1RSTR_TSCRST RCC_AHB1RSTR_TSCRST_Msk
Kojto 122:f9eeca106725 9299
Kojto 122:f9eeca106725 9300 /******************** Bit definition for RCC_AHB2RSTR register **************/
Kojto 122:f9eeca106725 9301 #define RCC_AHB2RSTR_GPIOARST_Pos (0U)
Kojto 122:f9eeca106725 9302 #define RCC_AHB2RSTR_GPIOARST_Msk (0x1U << RCC_AHB2RSTR_GPIOARST_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9303 #define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk
Kojto 122:f9eeca106725 9304 #define RCC_AHB2RSTR_GPIOBRST_Pos (1U)
Kojto 122:f9eeca106725 9305 #define RCC_AHB2RSTR_GPIOBRST_Msk (0x1U << RCC_AHB2RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9306 #define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk
Kojto 122:f9eeca106725 9307 #define RCC_AHB2RSTR_GPIOCRST_Pos (2U)
Kojto 122:f9eeca106725 9308 #define RCC_AHB2RSTR_GPIOCRST_Msk (0x1U << RCC_AHB2RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9309 #define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk
Kojto 122:f9eeca106725 9310 #define RCC_AHB2RSTR_GPIOHRST_Pos (7U)
Kojto 122:f9eeca106725 9311 #define RCC_AHB2RSTR_GPIOHRST_Msk (0x1U << RCC_AHB2RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 9312 #define RCC_AHB2RSTR_GPIOHRST RCC_AHB2RSTR_GPIOHRST_Msk
Kojto 122:f9eeca106725 9313 #define RCC_AHB2RSTR_ADCRST_Pos (13U)
Kojto 122:f9eeca106725 9314 #define RCC_AHB2RSTR_ADCRST_Msk (0x1U << RCC_AHB2RSTR_ADCRST_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 9315 #define RCC_AHB2RSTR_ADCRST RCC_AHB2RSTR_ADCRST_Msk
Kojto 122:f9eeca106725 9316 #define RCC_AHB2RSTR_RNGRST_Pos (18U)
Kojto 122:f9eeca106725 9317 #define RCC_AHB2RSTR_RNGRST_Msk (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 9318 #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
Kojto 122:f9eeca106725 9319
Kojto 122:f9eeca106725 9320 /******************** Bit definition for RCC_AHB3RSTR register **************/
Kojto 122:f9eeca106725 9321 #define RCC_AHB3RSTR_QSPIRST_Pos (8U)
Kojto 122:f9eeca106725 9322 #define RCC_AHB3RSTR_QSPIRST_Msk (0x1U << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 9323 #define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
Kojto 122:f9eeca106725 9324
Kojto 122:f9eeca106725 9325 /******************** Bit definition for RCC_APB1RSTR1 register **************/
Kojto 122:f9eeca106725 9326 #define RCC_APB1RSTR1_TIM2RST_Pos (0U)
Kojto 122:f9eeca106725 9327 #define RCC_APB1RSTR1_TIM2RST_Msk (0x1U << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9328 #define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk
Kojto 122:f9eeca106725 9329 #define RCC_APB1RSTR1_TIM6RST_Pos (4U)
Kojto 122:f9eeca106725 9330 #define RCC_APB1RSTR1_TIM6RST_Msk (0x1U << RCC_APB1RSTR1_TIM6RST_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 9331 #define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk
Kojto 122:f9eeca106725 9332 #define RCC_APB1RSTR1_TIM7RST_Pos (5U)
Kojto 122:f9eeca106725 9333 #define RCC_APB1RSTR1_TIM7RST_Msk (0x1U << RCC_APB1RSTR1_TIM7RST_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 9334 #define RCC_APB1RSTR1_TIM7RST RCC_APB1RSTR1_TIM7RST_Msk
Kojto 122:f9eeca106725 9335 #define RCC_APB1RSTR1_SPI3RST_Pos (15U)
Kojto 122:f9eeca106725 9336 #define RCC_APB1RSTR1_SPI3RST_Msk (0x1U << RCC_APB1RSTR1_SPI3RST_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 9337 #define RCC_APB1RSTR1_SPI3RST RCC_APB1RSTR1_SPI3RST_Msk
Kojto 122:f9eeca106725 9338 #define RCC_APB1RSTR1_USART2RST_Pos (17U)
Kojto 122:f9eeca106725 9339 #define RCC_APB1RSTR1_USART2RST_Msk (0x1U << RCC_APB1RSTR1_USART2RST_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 9340 #define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk
Kojto 122:f9eeca106725 9341 #define RCC_APB1RSTR1_I2C1RST_Pos (21U)
Kojto 122:f9eeca106725 9342 #define RCC_APB1RSTR1_I2C1RST_Msk (0x1U << RCC_APB1RSTR1_I2C1RST_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 9343 #define RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk
Kojto 122:f9eeca106725 9344 #define RCC_APB1RSTR1_I2C3RST_Pos (23U)
Kojto 122:f9eeca106725 9345 #define RCC_APB1RSTR1_I2C3RST_Msk (0x1U << RCC_APB1RSTR1_I2C3RST_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 9346 #define RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk
Kojto 122:f9eeca106725 9347 #define RCC_APB1RSTR1_CRSRST_Pos (24U)
Kojto 122:f9eeca106725 9348 #define RCC_APB1RSTR1_CRSRST_Msk (0x1U << RCC_APB1RSTR1_CRSRST_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 9349 #define RCC_APB1RSTR1_CRSRST RCC_APB1RSTR1_CRSRST_Msk
Kojto 122:f9eeca106725 9350 #define RCC_APB1RSTR1_CAN1RST_Pos (25U)
Kojto 122:f9eeca106725 9351 #define RCC_APB1RSTR1_CAN1RST_Msk (0x1U << RCC_APB1RSTR1_CAN1RST_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 9352 #define RCC_APB1RSTR1_CAN1RST RCC_APB1RSTR1_CAN1RST_Msk
Kojto 122:f9eeca106725 9353 #define RCC_APB1RSTR1_USBFSRST_Pos (26U)
Kojto 122:f9eeca106725 9354 #define RCC_APB1RSTR1_USBFSRST_Msk (0x1U << RCC_APB1RSTR1_USBFSRST_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 9355 #define RCC_APB1RSTR1_USBFSRST RCC_APB1RSTR1_USBFSRST_Msk
Kojto 122:f9eeca106725 9356 #define RCC_APB1RSTR1_PWRRST_Pos (28U)
Kojto 122:f9eeca106725 9357 #define RCC_APB1RSTR1_PWRRST_Msk (0x1U << RCC_APB1RSTR1_PWRRST_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 9358 #define RCC_APB1RSTR1_PWRRST RCC_APB1RSTR1_PWRRST_Msk
Kojto 122:f9eeca106725 9359 #define RCC_APB1RSTR1_DAC1RST_Pos (29U)
Kojto 122:f9eeca106725 9360 #define RCC_APB1RSTR1_DAC1RST_Msk (0x1U << RCC_APB1RSTR1_DAC1RST_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 9361 #define RCC_APB1RSTR1_DAC1RST RCC_APB1RSTR1_DAC1RST_Msk
Kojto 122:f9eeca106725 9362 #define RCC_APB1RSTR1_OPAMPRST_Pos (30U)
Kojto 122:f9eeca106725 9363 #define RCC_APB1RSTR1_OPAMPRST_Msk (0x1U << RCC_APB1RSTR1_OPAMPRST_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 9364 #define RCC_APB1RSTR1_OPAMPRST RCC_APB1RSTR1_OPAMPRST_Msk
Kojto 122:f9eeca106725 9365 #define RCC_APB1RSTR1_LPTIM1RST_Pos (31U)
Kojto 122:f9eeca106725 9366 #define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1U << RCC_APB1RSTR1_LPTIM1RST_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 9367 #define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk
Kojto 122:f9eeca106725 9368
Kojto 122:f9eeca106725 9369 /******************** Bit definition for RCC_APB1RSTR2 register **************/
Kojto 122:f9eeca106725 9370 #define RCC_APB1RSTR2_LPUART1RST_Pos (0U)
Kojto 122:f9eeca106725 9371 #define RCC_APB1RSTR2_LPUART1RST_Msk (0x1U << RCC_APB1RSTR2_LPUART1RST_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9372 #define RCC_APB1RSTR2_LPUART1RST RCC_APB1RSTR2_LPUART1RST_Msk
Kojto 122:f9eeca106725 9373 #define RCC_APB1RSTR2_SWPMI1RST_Pos (2U)
Kojto 122:f9eeca106725 9374 #define RCC_APB1RSTR2_SWPMI1RST_Msk (0x1U << RCC_APB1RSTR2_SWPMI1RST_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9375 #define RCC_APB1RSTR2_SWPMI1RST RCC_APB1RSTR2_SWPMI1RST_Msk
Kojto 122:f9eeca106725 9376 #define RCC_APB1RSTR2_LPTIM2RST_Pos (5U)
Kojto 122:f9eeca106725 9377 #define RCC_APB1RSTR2_LPTIM2RST_Msk (0x1U << RCC_APB1RSTR2_LPTIM2RST_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 9378 #define RCC_APB1RSTR2_LPTIM2RST RCC_APB1RSTR2_LPTIM2RST_Msk
Kojto 122:f9eeca106725 9379
Kojto 122:f9eeca106725 9380 /******************** Bit definition for RCC_APB2RSTR register **************/
Kojto 122:f9eeca106725 9381 #define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
Kojto 122:f9eeca106725 9382 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9383 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
Kojto 122:f9eeca106725 9384 #define RCC_APB2RSTR_TIM1RST_Pos (11U)
Kojto 122:f9eeca106725 9385 #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 9386 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
Kojto 122:f9eeca106725 9387 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
Kojto 122:f9eeca106725 9388 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 9389 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
Kojto 122:f9eeca106725 9390 #define RCC_APB2RSTR_USART1RST_Pos (14U)
Kojto 122:f9eeca106725 9391 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 9392 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
Kojto 122:f9eeca106725 9393 #define RCC_APB2RSTR_TIM15RST_Pos (16U)
Kojto 122:f9eeca106725 9394 #define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 9395 #define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk
Kojto 122:f9eeca106725 9396 #define RCC_APB2RSTR_TIM16RST_Pos (17U)
Kojto 122:f9eeca106725 9397 #define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 9398 #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk
Kojto 122:f9eeca106725 9399 #define RCC_APB2RSTR_SAI1RST_Pos (21U)
Kojto 122:f9eeca106725 9400 #define RCC_APB2RSTR_SAI1RST_Msk (0x1U << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 9401 #define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
Kojto 122:f9eeca106725 9402
Kojto 122:f9eeca106725 9403 /******************** Bit definition for RCC_AHB1ENR register ***************/
Kojto 122:f9eeca106725 9404 #define RCC_AHB1ENR_DMA1EN_Pos (0U)
Kojto 122:f9eeca106725 9405 #define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9406 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
Kojto 122:f9eeca106725 9407 #define RCC_AHB1ENR_DMA2EN_Pos (1U)
Kojto 122:f9eeca106725 9408 #define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9409 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
Kojto 122:f9eeca106725 9410 #define RCC_AHB1ENR_FLASHEN_Pos (8U)
Kojto 122:f9eeca106725 9411 #define RCC_AHB1ENR_FLASHEN_Msk (0x1U << RCC_AHB1ENR_FLASHEN_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 9412 #define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk
Kojto 122:f9eeca106725 9413 #define RCC_AHB1ENR_CRCEN_Pos (12U)
Kojto 122:f9eeca106725 9414 #define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 9415 #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
Kojto 122:f9eeca106725 9416 #define RCC_AHB1ENR_TSCEN_Pos (16U)
Kojto 122:f9eeca106725 9417 #define RCC_AHB1ENR_TSCEN_Msk (0x1U << RCC_AHB1ENR_TSCEN_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 9418 #define RCC_AHB1ENR_TSCEN RCC_AHB1ENR_TSCEN_Msk
Kojto 122:f9eeca106725 9419
Kojto 122:f9eeca106725 9420 /******************** Bit definition for RCC_AHB2ENR register ***************/
Kojto 122:f9eeca106725 9421 #define RCC_AHB2ENR_GPIOAEN_Pos (0U)
Kojto 122:f9eeca106725 9422 #define RCC_AHB2ENR_GPIOAEN_Msk (0x1U << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9423 #define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk
Kojto 122:f9eeca106725 9424 #define RCC_AHB2ENR_GPIOBEN_Pos (1U)
Kojto 122:f9eeca106725 9425 #define RCC_AHB2ENR_GPIOBEN_Msk (0x1U << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9426 #define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk
Kojto 122:f9eeca106725 9427 #define RCC_AHB2ENR_GPIOCEN_Pos (2U)
Kojto 122:f9eeca106725 9428 #define RCC_AHB2ENR_GPIOCEN_Msk (0x1U << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9429 #define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk
Kojto 122:f9eeca106725 9430 #define RCC_AHB2ENR_GPIOHEN_Pos (7U)
Kojto 122:f9eeca106725 9431 #define RCC_AHB2ENR_GPIOHEN_Msk (0x1U << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 9432 #define RCC_AHB2ENR_GPIOHEN RCC_AHB2ENR_GPIOHEN_Msk
Kojto 122:f9eeca106725 9433 #define RCC_AHB2ENR_ADCEN_Pos (13U)
Kojto 122:f9eeca106725 9434 #define RCC_AHB2ENR_ADCEN_Msk (0x1U << RCC_AHB2ENR_ADCEN_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 9435 #define RCC_AHB2ENR_ADCEN RCC_AHB2ENR_ADCEN_Msk
Kojto 122:f9eeca106725 9436 #define RCC_AHB2ENR_RNGEN_Pos (18U)
Kojto 122:f9eeca106725 9437 #define RCC_AHB2ENR_RNGEN_Msk (0x1U << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 9438 #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
Kojto 122:f9eeca106725 9439
Kojto 122:f9eeca106725 9440 /******************** Bit definition for RCC_AHB3ENR register ***************/
Kojto 122:f9eeca106725 9441 #define RCC_AHB3ENR_QSPIEN_Pos (8U)
Kojto 122:f9eeca106725 9442 #define RCC_AHB3ENR_QSPIEN_Msk (0x1U << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 9443 #define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
Kojto 122:f9eeca106725 9444
Kojto 122:f9eeca106725 9445 /******************** Bit definition for RCC_APB1ENR1 register ***************/
Kojto 122:f9eeca106725 9446 #define RCC_APB1ENR1_TIM2EN_Pos (0U)
Kojto 122:f9eeca106725 9447 #define RCC_APB1ENR1_TIM2EN_Msk (0x1U << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9448 #define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk
Kojto 122:f9eeca106725 9449 #define RCC_APB1ENR1_TIM6EN_Pos (4U)
Kojto 122:f9eeca106725 9450 #define RCC_APB1ENR1_TIM6EN_Msk (0x1U << RCC_APB1ENR1_TIM6EN_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 9451 #define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk
Kojto 122:f9eeca106725 9452 #define RCC_APB1ENR1_TIM7EN_Pos (5U)
Kojto 122:f9eeca106725 9453 #define RCC_APB1ENR1_TIM7EN_Msk (0x1U << RCC_APB1ENR1_TIM7EN_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 9454 #define RCC_APB1ENR1_TIM7EN RCC_APB1ENR1_TIM7EN_Msk
Kojto 122:f9eeca106725 9455 #define RCC_APB1ENR1_RTCAPBEN_Pos (10U)
Kojto 122:f9eeca106725 9456 #define RCC_APB1ENR1_RTCAPBEN_Msk (0x1U << RCC_APB1ENR1_RTCAPBEN_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 9457 #define RCC_APB1ENR1_RTCAPBEN RCC_APB1ENR1_RTCAPBEN_Msk
Kojto 122:f9eeca106725 9458 #define RCC_APB1ENR1_WWDGEN_Pos (11U)
Kojto 122:f9eeca106725 9459 #define RCC_APB1ENR1_WWDGEN_Msk (0x1U << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 9460 #define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk
Kojto 122:f9eeca106725 9461 #define RCC_APB1ENR1_SPI3EN_Pos (15U)
Kojto 122:f9eeca106725 9462 #define RCC_APB1ENR1_SPI3EN_Msk (0x1U << RCC_APB1ENR1_SPI3EN_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 9463 #define RCC_APB1ENR1_SPI3EN RCC_APB1ENR1_SPI3EN_Msk
Kojto 122:f9eeca106725 9464 #define RCC_APB1ENR1_USART2EN_Pos (17U)
Kojto 122:f9eeca106725 9465 #define RCC_APB1ENR1_USART2EN_Msk (0x1U << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 9466 #define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk
Kojto 122:f9eeca106725 9467 #define RCC_APB1ENR1_I2C1EN_Pos (21U)
Kojto 122:f9eeca106725 9468 #define RCC_APB1ENR1_I2C1EN_Msk (0x1U << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 9469 #define RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk
Kojto 122:f9eeca106725 9470 #define RCC_APB1ENR1_I2C3EN_Pos (23U)
Kojto 122:f9eeca106725 9471 #define RCC_APB1ENR1_I2C3EN_Msk (0x1U << RCC_APB1ENR1_I2C3EN_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 9472 #define RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk
Kojto 122:f9eeca106725 9473 #define RCC_APB1ENR1_CRSEN_Pos (24U)
Kojto 122:f9eeca106725 9474 #define RCC_APB1ENR1_CRSEN_Msk (0x1U << RCC_APB1ENR1_CRSEN_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 9475 #define RCC_APB1ENR1_CRSEN RCC_APB1ENR1_CRSEN_Msk
Kojto 122:f9eeca106725 9476 #define RCC_APB1ENR1_CAN1EN_Pos (25U)
Kojto 122:f9eeca106725 9477 #define RCC_APB1ENR1_CAN1EN_Msk (0x1U << RCC_APB1ENR1_CAN1EN_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 9478 #define RCC_APB1ENR1_CAN1EN RCC_APB1ENR1_CAN1EN_Msk
Kojto 122:f9eeca106725 9479 #define RCC_APB1ENR1_USBFSEN_Pos (26U)
Kojto 122:f9eeca106725 9480 #define RCC_APB1ENR1_USBFSEN_Msk (0x1U << RCC_APB1ENR1_USBFSEN_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 9481 #define RCC_APB1ENR1_USBFSEN RCC_APB1ENR1_USBFSEN_Msk
Kojto 122:f9eeca106725 9482 #define RCC_APB1ENR1_PWREN_Pos (28U)
Kojto 122:f9eeca106725 9483 #define RCC_APB1ENR1_PWREN_Msk (0x1U << RCC_APB1ENR1_PWREN_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 9484 #define RCC_APB1ENR1_PWREN RCC_APB1ENR1_PWREN_Msk
Kojto 122:f9eeca106725 9485 #define RCC_APB1ENR1_DAC1EN_Pos (29U)
Kojto 122:f9eeca106725 9486 #define RCC_APB1ENR1_DAC1EN_Msk (0x1U << RCC_APB1ENR1_DAC1EN_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 9487 #define RCC_APB1ENR1_DAC1EN RCC_APB1ENR1_DAC1EN_Msk
Kojto 122:f9eeca106725 9488 #define RCC_APB1ENR1_OPAMPEN_Pos (30U)
Kojto 122:f9eeca106725 9489 #define RCC_APB1ENR1_OPAMPEN_Msk (0x1U << RCC_APB1ENR1_OPAMPEN_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 9490 #define RCC_APB1ENR1_OPAMPEN RCC_APB1ENR1_OPAMPEN_Msk
Kojto 122:f9eeca106725 9491 #define RCC_APB1ENR1_LPTIM1EN_Pos (31U)
Kojto 122:f9eeca106725 9492 #define RCC_APB1ENR1_LPTIM1EN_Msk (0x1U << RCC_APB1ENR1_LPTIM1EN_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 9493 #define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk
Kojto 122:f9eeca106725 9494
Kojto 122:f9eeca106725 9495 /******************** Bit definition for RCC_APB1RSTR2 register **************/
Kojto 122:f9eeca106725 9496 #define RCC_APB1ENR2_LPUART1EN_Pos (0U)
Kojto 122:f9eeca106725 9497 #define RCC_APB1ENR2_LPUART1EN_Msk (0x1U << RCC_APB1ENR2_LPUART1EN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9498 #define RCC_APB1ENR2_LPUART1EN RCC_APB1ENR2_LPUART1EN_Msk
Kojto 122:f9eeca106725 9499 #define RCC_APB1ENR2_SWPMI1EN_Pos (2U)
Kojto 122:f9eeca106725 9500 #define RCC_APB1ENR2_SWPMI1EN_Msk (0x1U << RCC_APB1ENR2_SWPMI1EN_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9501 #define RCC_APB1ENR2_SWPMI1EN RCC_APB1ENR2_SWPMI1EN_Msk
Kojto 122:f9eeca106725 9502 #define RCC_APB1ENR2_LPTIM2EN_Pos (5U)
Kojto 122:f9eeca106725 9503 #define RCC_APB1ENR2_LPTIM2EN_Msk (0x1U << RCC_APB1ENR2_LPTIM2EN_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 9504 #define RCC_APB1ENR2_LPTIM2EN RCC_APB1ENR2_LPTIM2EN_Msk
Kojto 122:f9eeca106725 9505
Kojto 122:f9eeca106725 9506 /******************** Bit definition for RCC_APB2ENR register ***************/
Kojto 122:f9eeca106725 9507 #define RCC_APB2ENR_SYSCFGEN_Pos (0U)
Kojto 122:f9eeca106725 9508 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9509 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
Kojto 122:f9eeca106725 9510 #define RCC_APB2ENR_FWEN_Pos (7U)
Kojto 122:f9eeca106725 9511 #define RCC_APB2ENR_FWEN_Msk (0x1U << RCC_APB2ENR_FWEN_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 9512 #define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk
Kojto 122:f9eeca106725 9513 #define RCC_APB2ENR_TIM1EN_Pos (11U)
Kojto 122:f9eeca106725 9514 #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 9515 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
Kojto 122:f9eeca106725 9516 #define RCC_APB2ENR_SPI1EN_Pos (12U)
Kojto 122:f9eeca106725 9517 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 9518 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
Kojto 122:f9eeca106725 9519 #define RCC_APB2ENR_USART1EN_Pos (14U)
Kojto 122:f9eeca106725 9520 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 9521 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
Kojto 122:f9eeca106725 9522 #define RCC_APB2ENR_TIM15EN_Pos (16U)
Kojto 122:f9eeca106725 9523 #define RCC_APB2ENR_TIM15EN_Msk (0x1U << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 9524 #define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk
Kojto 122:f9eeca106725 9525 #define RCC_APB2ENR_TIM16EN_Pos (17U)
Kojto 122:f9eeca106725 9526 #define RCC_APB2ENR_TIM16EN_Msk (0x1U << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 9527 #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk
Kojto 122:f9eeca106725 9528 #define RCC_APB2ENR_SAI1EN_Pos (21U)
Kojto 122:f9eeca106725 9529 #define RCC_APB2ENR_SAI1EN_Msk (0x1U << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 9530 #define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
Kojto 122:f9eeca106725 9531
Kojto 122:f9eeca106725 9532 /******************** Bit definition for RCC_AHB1SMENR register ***************/
Kojto 122:f9eeca106725 9533 #define RCC_AHB1SMENR_DMA1SMEN_Pos (0U)
Kojto 122:f9eeca106725 9534 #define RCC_AHB1SMENR_DMA1SMEN_Msk (0x1U << RCC_AHB1SMENR_DMA1SMEN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9535 #define RCC_AHB1SMENR_DMA1SMEN RCC_AHB1SMENR_DMA1SMEN_Msk
Kojto 122:f9eeca106725 9536 #define RCC_AHB1SMENR_DMA2SMEN_Pos (1U)
Kojto 122:f9eeca106725 9537 #define RCC_AHB1SMENR_DMA2SMEN_Msk (0x1U << RCC_AHB1SMENR_DMA2SMEN_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9538 #define RCC_AHB1SMENR_DMA2SMEN RCC_AHB1SMENR_DMA2SMEN_Msk
Kojto 122:f9eeca106725 9539 #define RCC_AHB1SMENR_FLASHSMEN_Pos (8U)
Kojto 122:f9eeca106725 9540 #define RCC_AHB1SMENR_FLASHSMEN_Msk (0x1U << RCC_AHB1SMENR_FLASHSMEN_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 9541 #define RCC_AHB1SMENR_FLASHSMEN RCC_AHB1SMENR_FLASHSMEN_Msk
Kojto 122:f9eeca106725 9542 #define RCC_AHB1SMENR_SRAM1SMEN_Pos (9U)
Kojto 122:f9eeca106725 9543 #define RCC_AHB1SMENR_SRAM1SMEN_Msk (0x1U << RCC_AHB1SMENR_SRAM1SMEN_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 9544 #define RCC_AHB1SMENR_SRAM1SMEN RCC_AHB1SMENR_SRAM1SMEN_Msk
Kojto 122:f9eeca106725 9545 #define RCC_AHB1SMENR_CRCSMEN_Pos (12U)
Kojto 122:f9eeca106725 9546 #define RCC_AHB1SMENR_CRCSMEN_Msk (0x1U << RCC_AHB1SMENR_CRCSMEN_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 9547 #define RCC_AHB1SMENR_CRCSMEN RCC_AHB1SMENR_CRCSMEN_Msk
Kojto 122:f9eeca106725 9548 #define RCC_AHB1SMENR_TSCSMEN_Pos (16U)
Kojto 122:f9eeca106725 9549 #define RCC_AHB1SMENR_TSCSMEN_Msk (0x1U << RCC_AHB1SMENR_TSCSMEN_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 9550 #define RCC_AHB1SMENR_TSCSMEN RCC_AHB1SMENR_TSCSMEN_Msk
Kojto 122:f9eeca106725 9551
Kojto 122:f9eeca106725 9552 /******************** Bit definition for RCC_AHB2SMENR register *************/
Kojto 122:f9eeca106725 9553 #define RCC_AHB2SMENR_GPIOASMEN_Pos (0U)
Kojto 122:f9eeca106725 9554 #define RCC_AHB2SMENR_GPIOASMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOASMEN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9555 #define RCC_AHB2SMENR_GPIOASMEN RCC_AHB2SMENR_GPIOASMEN_Msk
Kojto 122:f9eeca106725 9556 #define RCC_AHB2SMENR_GPIOBSMEN_Pos (1U)
Kojto 122:f9eeca106725 9557 #define RCC_AHB2SMENR_GPIOBSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOBSMEN_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9558 #define RCC_AHB2SMENR_GPIOBSMEN RCC_AHB2SMENR_GPIOBSMEN_Msk
Kojto 122:f9eeca106725 9559 #define RCC_AHB2SMENR_GPIOCSMEN_Pos (2U)
Kojto 122:f9eeca106725 9560 #define RCC_AHB2SMENR_GPIOCSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOCSMEN_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9561 #define RCC_AHB2SMENR_GPIOCSMEN RCC_AHB2SMENR_GPIOCSMEN_Msk
Kojto 122:f9eeca106725 9562 #define RCC_AHB2SMENR_GPIOHSMEN_Pos (7U)
Kojto 122:f9eeca106725 9563 #define RCC_AHB2SMENR_GPIOHSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOHSMEN_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 9564 #define RCC_AHB2SMENR_GPIOHSMEN RCC_AHB2SMENR_GPIOHSMEN_Msk
Kojto 122:f9eeca106725 9565 #define RCC_AHB2SMENR_SRAM2SMEN_Pos (9U)
Kojto 122:f9eeca106725 9566 #define RCC_AHB2SMENR_SRAM2SMEN_Msk (0x1U << RCC_AHB2SMENR_SRAM2SMEN_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 9567 #define RCC_AHB2SMENR_SRAM2SMEN RCC_AHB2SMENR_SRAM2SMEN_Msk
Kojto 122:f9eeca106725 9568 #define RCC_AHB2SMENR_ADCSMEN_Pos (13U)
Kojto 122:f9eeca106725 9569 #define RCC_AHB2SMENR_ADCSMEN_Msk (0x1U << RCC_AHB2SMENR_ADCSMEN_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 9570 #define RCC_AHB2SMENR_ADCSMEN RCC_AHB2SMENR_ADCSMEN_Msk
Kojto 122:f9eeca106725 9571 #define RCC_AHB2SMENR_RNGSMEN_Pos (18U)
Kojto 122:f9eeca106725 9572 #define RCC_AHB2SMENR_RNGSMEN_Msk (0x1U << RCC_AHB2SMENR_RNGSMEN_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 9573 #define RCC_AHB2SMENR_RNGSMEN RCC_AHB2SMENR_RNGSMEN_Msk
Kojto 122:f9eeca106725 9574
Kojto 122:f9eeca106725 9575 /******************** Bit definition for RCC_AHB3SMENR register *************/
Kojto 122:f9eeca106725 9576 #define RCC_AHB3SMENR_QSPISMEN_Pos (8U)
Kojto 122:f9eeca106725 9577 #define RCC_AHB3SMENR_QSPISMEN_Msk (0x1U << RCC_AHB3SMENR_QSPISMEN_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 9578 #define RCC_AHB3SMENR_QSPISMEN RCC_AHB3SMENR_QSPISMEN_Msk
Kojto 122:f9eeca106725 9579
Kojto 122:f9eeca106725 9580 /******************** Bit definition for RCC_APB1SMENR1 register *************/
Kojto 122:f9eeca106725 9581 #define RCC_APB1SMENR1_TIM2SMEN_Pos (0U)
Kojto 122:f9eeca106725 9582 #define RCC_APB1SMENR1_TIM2SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM2SMEN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9583 #define RCC_APB1SMENR1_TIM2SMEN RCC_APB1SMENR1_TIM2SMEN_Msk
Kojto 122:f9eeca106725 9584 #define RCC_APB1SMENR1_TIM6SMEN_Pos (4U)
Kojto 122:f9eeca106725 9585 #define RCC_APB1SMENR1_TIM6SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM6SMEN_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 9586 #define RCC_APB1SMENR1_TIM6SMEN RCC_APB1SMENR1_TIM6SMEN_Msk
Kojto 122:f9eeca106725 9587 #define RCC_APB1SMENR1_TIM7SMEN_Pos (5U)
Kojto 122:f9eeca106725 9588 #define RCC_APB1SMENR1_TIM7SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM7SMEN_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 9589 #define RCC_APB1SMENR1_TIM7SMEN RCC_APB1SMENR1_TIM7SMEN_Msk
Kojto 122:f9eeca106725 9590 #define RCC_APB1SMENR1_RTCAPBSMEN_Pos (10U)
Kojto 122:f9eeca106725 9591 #define RCC_APB1SMENR1_RTCAPBSMEN_Msk (0x1U << RCC_APB1SMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 9592 #define RCC_APB1SMENR1_RTCAPBSMEN RCC_APB1SMENR1_RTCAPBSMEN_Msk
Kojto 122:f9eeca106725 9593 #define RCC_APB1SMENR1_WWDGSMEN_Pos (11U)
Kojto 122:f9eeca106725 9594 #define RCC_APB1SMENR1_WWDGSMEN_Msk (0x1U << RCC_APB1SMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 9595 #define RCC_APB1SMENR1_WWDGSMEN RCC_APB1SMENR1_WWDGSMEN_Msk
Kojto 122:f9eeca106725 9596 #define RCC_APB1SMENR1_SPI3SMEN_Pos (15U)
Kojto 122:f9eeca106725 9597 #define RCC_APB1SMENR1_SPI3SMEN_Msk (0x1U << RCC_APB1SMENR1_SPI3SMEN_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 9598 #define RCC_APB1SMENR1_SPI3SMEN RCC_APB1SMENR1_SPI3SMEN_Msk
Kojto 122:f9eeca106725 9599 #define RCC_APB1SMENR1_USART2SMEN_Pos (17U)
Kojto 122:f9eeca106725 9600 #define RCC_APB1SMENR1_USART2SMEN_Msk (0x1U << RCC_APB1SMENR1_USART2SMEN_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 9601 #define RCC_APB1SMENR1_USART2SMEN RCC_APB1SMENR1_USART2SMEN_Msk
Kojto 122:f9eeca106725 9602 #define RCC_APB1SMENR1_I2C1SMEN_Pos (21U)
Kojto 122:f9eeca106725 9603 #define RCC_APB1SMENR1_I2C1SMEN_Msk (0x1U << RCC_APB1SMENR1_I2C1SMEN_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 9604 #define RCC_APB1SMENR1_I2C1SMEN RCC_APB1SMENR1_I2C1SMEN_Msk
Kojto 122:f9eeca106725 9605 #define RCC_APB1SMENR1_I2C3SMEN_Pos (23U)
Kojto 122:f9eeca106725 9606 #define RCC_APB1SMENR1_I2C3SMEN_Msk (0x1U << RCC_APB1SMENR1_I2C3SMEN_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 9607 #define RCC_APB1SMENR1_I2C3SMEN RCC_APB1SMENR1_I2C3SMEN_Msk
Kojto 122:f9eeca106725 9608 #define RCC_APB1SMENR1_CRSSMEN_Pos (24U)
Kojto 122:f9eeca106725 9609 #define RCC_APB1SMENR1_CRSSMEN_Msk (0x1U << RCC_APB1SMENR1_CRSSMEN_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 9610 #define RCC_APB1SMENR1_CRSSMEN RCC_APB1SMENR1_CRSSMEN_Msk
Kojto 122:f9eeca106725 9611 #define RCC_APB1SMENR1_CAN1SMEN_Pos (25U)
Kojto 122:f9eeca106725 9612 #define RCC_APB1SMENR1_CAN1SMEN_Msk (0x1U << RCC_APB1SMENR1_CAN1SMEN_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 9613 #define RCC_APB1SMENR1_CAN1SMEN RCC_APB1SMENR1_CAN1SMEN_Msk
Kojto 122:f9eeca106725 9614 #define RCC_APB1SMENR1_USBFSSMEN_Pos (26U)
Kojto 122:f9eeca106725 9615 #define RCC_APB1SMENR1_USBFSSMEN_Msk (0x1U << RCC_APB1SMENR1_USBFSSMEN_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 9616 #define RCC_APB1SMENR1_USBFSSMEN RCC_APB1SMENR1_USBFSSMEN_Msk
Kojto 122:f9eeca106725 9617 #define RCC_APB1SMENR1_PWRSMEN_Pos (28U)
Kojto 122:f9eeca106725 9618 #define RCC_APB1SMENR1_PWRSMEN_Msk (0x1U << RCC_APB1SMENR1_PWRSMEN_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 9619 #define RCC_APB1SMENR1_PWRSMEN RCC_APB1SMENR1_PWRSMEN_Msk
Kojto 122:f9eeca106725 9620 #define RCC_APB1SMENR1_DAC1SMEN_Pos (29U)
Kojto 122:f9eeca106725 9621 #define RCC_APB1SMENR1_DAC1SMEN_Msk (0x1U << RCC_APB1SMENR1_DAC1SMEN_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 9622 #define RCC_APB1SMENR1_DAC1SMEN RCC_APB1SMENR1_DAC1SMEN_Msk
Kojto 122:f9eeca106725 9623 #define RCC_APB1SMENR1_OPAMPSMEN_Pos (30U)
Kojto 122:f9eeca106725 9624 #define RCC_APB1SMENR1_OPAMPSMEN_Msk (0x1U << RCC_APB1SMENR1_OPAMPSMEN_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 9625 #define RCC_APB1SMENR1_OPAMPSMEN RCC_APB1SMENR1_OPAMPSMEN_Msk
Kojto 122:f9eeca106725 9626 #define RCC_APB1SMENR1_LPTIM1SMEN_Pos (31U)
Kojto 122:f9eeca106725 9627 #define RCC_APB1SMENR1_LPTIM1SMEN_Msk (0x1U << RCC_APB1SMENR1_LPTIM1SMEN_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 9628 #define RCC_APB1SMENR1_LPTIM1SMEN RCC_APB1SMENR1_LPTIM1SMEN_Msk
Kojto 122:f9eeca106725 9629
Kojto 122:f9eeca106725 9630 /******************** Bit definition for RCC_APB1SMENR2 register *************/
Kojto 122:f9eeca106725 9631 #define RCC_APB1SMENR2_LPUART1SMEN_Pos (0U)
Kojto 122:f9eeca106725 9632 #define RCC_APB1SMENR2_LPUART1SMEN_Msk (0x1U << RCC_APB1SMENR2_LPUART1SMEN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9633 #define RCC_APB1SMENR2_LPUART1SMEN RCC_APB1SMENR2_LPUART1SMEN_Msk
Kojto 122:f9eeca106725 9634 #define RCC_APB1SMENR2_SWPMI1SMEN_Pos (2U)
Kojto 122:f9eeca106725 9635 #define RCC_APB1SMENR2_SWPMI1SMEN_Msk (0x1U << RCC_APB1SMENR2_SWPMI1SMEN_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9636 #define RCC_APB1SMENR2_SWPMI1SMEN RCC_APB1SMENR2_SWPMI1SMEN_Msk
Kojto 122:f9eeca106725 9637 #define RCC_APB1SMENR2_LPTIM2SMEN_Pos (5U)
Kojto 122:f9eeca106725 9638 #define RCC_APB1SMENR2_LPTIM2SMEN_Msk (0x1U << RCC_APB1SMENR2_LPTIM2SMEN_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 9639 #define RCC_APB1SMENR2_LPTIM2SMEN RCC_APB1SMENR2_LPTIM2SMEN_Msk
Kojto 122:f9eeca106725 9640
Kojto 122:f9eeca106725 9641 /******************** Bit definition for RCC_APB2SMENR register *************/
Kojto 122:f9eeca106725 9642 #define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
Kojto 122:f9eeca106725 9643 #define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1U << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9644 #define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk
Kojto 122:f9eeca106725 9645 #define RCC_APB2SMENR_TIM1SMEN_Pos (11U)
Kojto 122:f9eeca106725 9646 #define RCC_APB2SMENR_TIM1SMEN_Msk (0x1U << RCC_APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 9647 #define RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk
Kojto 122:f9eeca106725 9648 #define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
Kojto 122:f9eeca106725 9649 #define RCC_APB2SMENR_SPI1SMEN_Msk (0x1U << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 9650 #define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk
Kojto 122:f9eeca106725 9651 #define RCC_APB2SMENR_USART1SMEN_Pos (14U)
Kojto 122:f9eeca106725 9652 #define RCC_APB2SMENR_USART1SMEN_Msk (0x1U << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 9653 #define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk
Kojto 122:f9eeca106725 9654 #define RCC_APB2SMENR_TIM15SMEN_Pos (16U)
Kojto 122:f9eeca106725 9655 #define RCC_APB2SMENR_TIM15SMEN_Msk (0x1U << RCC_APB2SMENR_TIM15SMEN_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 9656 #define RCC_APB2SMENR_TIM15SMEN RCC_APB2SMENR_TIM15SMEN_Msk
Kojto 122:f9eeca106725 9657 #define RCC_APB2SMENR_TIM16SMEN_Pos (17U)
Kojto 122:f9eeca106725 9658 #define RCC_APB2SMENR_TIM16SMEN_Msk (0x1U << RCC_APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 9659 #define RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk
Kojto 122:f9eeca106725 9660 #define RCC_APB2SMENR_SAI1SMEN_Pos (21U)
Kojto 122:f9eeca106725 9661 #define RCC_APB2SMENR_SAI1SMEN_Msk (0x1U << RCC_APB2SMENR_SAI1SMEN_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 9662 #define RCC_APB2SMENR_SAI1SMEN RCC_APB2SMENR_SAI1SMEN_Msk
Kojto 122:f9eeca106725 9663
Kojto 122:f9eeca106725 9664 /******************** Bit definition for RCC_CCIPR register ******************/
Kojto 122:f9eeca106725 9665 #define RCC_CCIPR_USART1SEL_Pos (0U)
Kojto 122:f9eeca106725 9666 #define RCC_CCIPR_USART1SEL_Msk (0x3U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 9667 #define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk
Kojto 122:f9eeca106725 9668 #define RCC_CCIPR_USART1SEL_0 (0x1U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9669 #define RCC_CCIPR_USART1SEL_1 (0x2U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9670
Kojto 122:f9eeca106725 9671 #define RCC_CCIPR_USART2SEL_Pos (2U)
Kojto 122:f9eeca106725 9672 #define RCC_CCIPR_USART2SEL_Msk (0x3U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
Kojto 122:f9eeca106725 9673 #define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk
Kojto 122:f9eeca106725 9674 #define RCC_CCIPR_USART2SEL_0 (0x1U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9675 #define RCC_CCIPR_USART2SEL_1 (0x2U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 9676
Kojto 122:f9eeca106725 9677 #define RCC_CCIPR_LPUART1SEL_Pos (10U)
Kojto 122:f9eeca106725 9678 #define RCC_CCIPR_LPUART1SEL_Msk (0x3U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
Kojto 122:f9eeca106725 9679 #define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk
Kojto 122:f9eeca106725 9680 #define RCC_CCIPR_LPUART1SEL_0 (0x1U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 9681 #define RCC_CCIPR_LPUART1SEL_1 (0x2U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 9682
Kojto 122:f9eeca106725 9683 #define RCC_CCIPR_I2C1SEL_Pos (12U)
Kojto 122:f9eeca106725 9684 #define RCC_CCIPR_I2C1SEL_Msk (0x3U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */
Kojto 122:f9eeca106725 9685 #define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk
Kojto 122:f9eeca106725 9686 #define RCC_CCIPR_I2C1SEL_0 (0x1U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 9687 #define RCC_CCIPR_I2C1SEL_1 (0x2U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 9688
Kojto 122:f9eeca106725 9689 #define RCC_CCIPR_I2C3SEL_Pos (16U)
Kojto 122:f9eeca106725 9690 #define RCC_CCIPR_I2C3SEL_Msk (0x3U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00030000 */
Kojto 122:f9eeca106725 9691 #define RCC_CCIPR_I2C3SEL RCC_CCIPR_I2C3SEL_Msk
Kojto 122:f9eeca106725 9692 #define RCC_CCIPR_I2C3SEL_0 (0x1U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 9693 #define RCC_CCIPR_I2C3SEL_1 (0x2U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 9694
Kojto 122:f9eeca106725 9695 #define RCC_CCIPR_LPTIM1SEL_Pos (18U)
Kojto 122:f9eeca106725 9696 #define RCC_CCIPR_LPTIM1SEL_Msk (0x3U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
Kojto 122:f9eeca106725 9697 #define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk
Kojto 122:f9eeca106725 9698 #define RCC_CCIPR_LPTIM1SEL_0 (0x1U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 9699 #define RCC_CCIPR_LPTIM1SEL_1 (0x2U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 9700
Kojto 122:f9eeca106725 9701 #define RCC_CCIPR_LPTIM2SEL_Pos (20U)
Kojto 122:f9eeca106725 9702 #define RCC_CCIPR_LPTIM2SEL_Msk (0x3U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00300000 */
Kojto 122:f9eeca106725 9703 #define RCC_CCIPR_LPTIM2SEL RCC_CCIPR_LPTIM2SEL_Msk
Kojto 122:f9eeca106725 9704 #define RCC_CCIPR_LPTIM2SEL_0 (0x1U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 9705 #define RCC_CCIPR_LPTIM2SEL_1 (0x2U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 9706
Kojto 122:f9eeca106725 9707 #define RCC_CCIPR_SAI1SEL_Pos (22U)
Kojto 122:f9eeca106725 9708 #define RCC_CCIPR_SAI1SEL_Msk (0x3U << RCC_CCIPR_SAI1SEL_Pos) /*!< 0x00C00000 */
Kojto 122:f9eeca106725 9709 #define RCC_CCIPR_SAI1SEL RCC_CCIPR_SAI1SEL_Msk
Kojto 122:f9eeca106725 9710 #define RCC_CCIPR_SAI1SEL_0 (0x1U << RCC_CCIPR_SAI1SEL_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 9711 #define RCC_CCIPR_SAI1SEL_1 (0x2U << RCC_CCIPR_SAI1SEL_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 9712
Kojto 122:f9eeca106725 9713 #define RCC_CCIPR_CLK48SEL_Pos (26U)
Kojto 122:f9eeca106725 9714 #define RCC_CCIPR_CLK48SEL_Msk (0x3U << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */
Kojto 122:f9eeca106725 9715 #define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
Kojto 122:f9eeca106725 9716 #define RCC_CCIPR_CLK48SEL_0 (0x1U << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 9717 #define RCC_CCIPR_CLK48SEL_1 (0x2U << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 9718
Kojto 122:f9eeca106725 9719 #define RCC_CCIPR_ADCSEL_Pos (28U)
Kojto 122:f9eeca106725 9720 #define RCC_CCIPR_ADCSEL_Msk (0x3U << RCC_CCIPR_ADCSEL_Pos) /*!< 0x30000000 */
Kojto 122:f9eeca106725 9721 #define RCC_CCIPR_ADCSEL RCC_CCIPR_ADCSEL_Msk
Kojto 122:f9eeca106725 9722 #define RCC_CCIPR_ADCSEL_0 (0x1U << RCC_CCIPR_ADCSEL_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 9723 #define RCC_CCIPR_ADCSEL_1 (0x2U << RCC_CCIPR_ADCSEL_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 9724
Kojto 122:f9eeca106725 9725 #define RCC_CCIPR_SWPMI1SEL_Pos (30U)
Kojto 122:f9eeca106725 9726 #define RCC_CCIPR_SWPMI1SEL_Msk (0x1U << RCC_CCIPR_SWPMI1SEL_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 9727 #define RCC_CCIPR_SWPMI1SEL RCC_CCIPR_SWPMI1SEL_Msk
Kojto 122:f9eeca106725 9728
Kojto 122:f9eeca106725 9729 /******************** Bit definition for RCC_BDCR register ******************/
Kojto 122:f9eeca106725 9730 #define RCC_BDCR_LSEON_Pos (0U)
Kojto 122:f9eeca106725 9731 #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9732 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
Kojto 122:f9eeca106725 9733 #define RCC_BDCR_LSERDY_Pos (1U)
Kojto 122:f9eeca106725 9734 #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9735 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
Kojto 122:f9eeca106725 9736 #define RCC_BDCR_LSEBYP_Pos (2U)
Kojto 122:f9eeca106725 9737 #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9738 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
Kojto 122:f9eeca106725 9739
Kojto 122:f9eeca106725 9740 #define RCC_BDCR_LSEDRV_Pos (3U)
Kojto 122:f9eeca106725 9741 #define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
Kojto 122:f9eeca106725 9742 #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
Kojto 122:f9eeca106725 9743 #define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 9744 #define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 9745
Kojto 122:f9eeca106725 9746 #define RCC_BDCR_LSECSSON_Pos (5U)
Kojto 122:f9eeca106725 9747 #define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 9748 #define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk
Kojto 122:f9eeca106725 9749 #define RCC_BDCR_LSECSSD_Pos (6U)
Kojto 122:f9eeca106725 9750 #define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 9751 #define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk
Kojto 122:f9eeca106725 9752
Kojto 122:f9eeca106725 9753 #define RCC_BDCR_RTCSEL_Pos (8U)
Kojto 122:f9eeca106725 9754 #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 9755 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
Kojto 122:f9eeca106725 9756 #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 9757 #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 9758
Kojto 122:f9eeca106725 9759 #define RCC_BDCR_RTCEN_Pos (15U)
Kojto 122:f9eeca106725 9760 #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 9761 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
Kojto 122:f9eeca106725 9762 #define RCC_BDCR_BDRST_Pos (16U)
Kojto 122:f9eeca106725 9763 #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 9764 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
Kojto 122:f9eeca106725 9765 #define RCC_BDCR_LSCOEN_Pos (24U)
Kojto 122:f9eeca106725 9766 #define RCC_BDCR_LSCOEN_Msk (0x1U << RCC_BDCR_LSCOEN_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 9767 #define RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk
Kojto 122:f9eeca106725 9768 #define RCC_BDCR_LSCOSEL_Pos (25U)
Kojto 122:f9eeca106725 9769 #define RCC_BDCR_LSCOSEL_Msk (0x1U << RCC_BDCR_LSCOSEL_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 9770 #define RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk
Kojto 122:f9eeca106725 9771
Kojto 122:f9eeca106725 9772 /******************** Bit definition for RCC_CSR register *******************/
Kojto 122:f9eeca106725 9773 #define RCC_CSR_LSION_Pos (0U)
Kojto 122:f9eeca106725 9774 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9775 #define RCC_CSR_LSION RCC_CSR_LSION_Msk
Kojto 122:f9eeca106725 9776 #define RCC_CSR_LSIRDY_Pos (1U)
Kojto 122:f9eeca106725 9777 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9778 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
Kojto 122:f9eeca106725 9779
Kojto 122:f9eeca106725 9780 #define RCC_CSR_MSISRANGE_Pos (8U)
Kojto 122:f9eeca106725 9781 #define RCC_CSR_MSISRANGE_Msk (0xFU << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 9782 #define RCC_CSR_MSISRANGE RCC_CSR_MSISRANGE_Msk
Kojto 122:f9eeca106725 9783 #define RCC_CSR_MSISRANGE_1 (0x4U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 9784 #define RCC_CSR_MSISRANGE_2 (0x5U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000500 */
Kojto 122:f9eeca106725 9785 #define RCC_CSR_MSISRANGE_4 (0x6U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000600 */
Kojto 122:f9eeca106725 9786 #define RCC_CSR_MSISRANGE_8 (0x7U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000700 */
Kojto 122:f9eeca106725 9787
Kojto 122:f9eeca106725 9788 #define RCC_CSR_RMVF_Pos (23U)
Kojto 122:f9eeca106725 9789 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 9790 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
Kojto 122:f9eeca106725 9791 #define RCC_CSR_FWRSTF_Pos (24U)
Kojto 122:f9eeca106725 9792 #define RCC_CSR_FWRSTF_Msk (0x1U << RCC_CSR_FWRSTF_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 9793 #define RCC_CSR_FWRSTF RCC_CSR_FWRSTF_Msk
Kojto 122:f9eeca106725 9794 #define RCC_CSR_OBLRSTF_Pos (25U)
Kojto 122:f9eeca106725 9795 #define RCC_CSR_OBLRSTF_Msk (0x1U << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 9796 #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk
Kojto 122:f9eeca106725 9797 #define RCC_CSR_PINRSTF_Pos (26U)
Kojto 122:f9eeca106725 9798 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 9799 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
Kojto 122:f9eeca106725 9800 #define RCC_CSR_BORRSTF_Pos (27U)
Kojto 122:f9eeca106725 9801 #define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 9802 #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
Kojto 122:f9eeca106725 9803 #define RCC_CSR_SFTRSTF_Pos (28U)
Kojto 122:f9eeca106725 9804 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 9805 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
Kojto 122:f9eeca106725 9806 #define RCC_CSR_IWDGRSTF_Pos (29U)
Kojto 122:f9eeca106725 9807 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 9808 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
Kojto 122:f9eeca106725 9809 #define RCC_CSR_WWDGRSTF_Pos (30U)
Kojto 122:f9eeca106725 9810 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 9811 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
Kojto 122:f9eeca106725 9812 #define RCC_CSR_LPWRRSTF_Pos (31U)
Kojto 122:f9eeca106725 9813 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 9814 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
Kojto 122:f9eeca106725 9815
Kojto 122:f9eeca106725 9816 /******************** Bit definition for RCC_CRRCR register *****************/
Kojto 122:f9eeca106725 9817 #define RCC_CRRCR_HSI48ON_Pos (0U)
Kojto 122:f9eeca106725 9818 #define RCC_CRRCR_HSI48ON_Msk (0x1U << RCC_CRRCR_HSI48ON_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9819 #define RCC_CRRCR_HSI48ON RCC_CRRCR_HSI48ON_Msk
Kojto 122:f9eeca106725 9820 #define RCC_CRRCR_HSI48RDY_Pos (1U)
Kojto 122:f9eeca106725 9821 #define RCC_CRRCR_HSI48RDY_Msk (0x1U << RCC_CRRCR_HSI48RDY_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9822 #define RCC_CRRCR_HSI48RDY RCC_CRRCR_HSI48RDY_Msk
Kojto 122:f9eeca106725 9823
Kojto 122:f9eeca106725 9824 /*!< HSI48CAL configuration */
Kojto 122:f9eeca106725 9825 #define RCC_CRRCR_HSI48CAL_Pos (15U)
Kojto 122:f9eeca106725 9826 #define RCC_CRRCR_HSI48CAL_Msk (0x1FFU << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00FF8000 */
Kojto 122:f9eeca106725 9827 #define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk /*!< HSI48CAL[8:0] bits */
Kojto 122:f9eeca106725 9828 #define RCC_CRRCR_HSI48CAL_0 (0x000U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 9829 #define RCC_CRRCR_HSI48CAL_1 (0x002U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 9830 #define RCC_CRRCR_HSI48CAL_2 (0x004U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 9831 #define RCC_CRRCR_HSI48CAL_3 (0x008U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 9832 #define RCC_CRRCR_HSI48CAL_4 (0x010U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 9833 #define RCC_CRRCR_HSI48CAL_5 (0x020U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 9834 #define RCC_CRRCR_HSI48CAL_6 (0x040U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 9835 #define RCC_CRRCR_HSI48CAL_7 (0x080U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 9836 #define RCC_CRRCR_HSI48CAL_8 (0x100U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 9837
Kojto 122:f9eeca106725 9838 /******************************************************************************/
Kojto 122:f9eeca106725 9839 /* */
Kojto 122:f9eeca106725 9840 /* RNG */
Kojto 122:f9eeca106725 9841 /* */
Kojto 122:f9eeca106725 9842 /******************************************************************************/
Kojto 122:f9eeca106725 9843 /******************** Bits definition for RNG_CR register *******************/
Kojto 122:f9eeca106725 9844 #define RNG_CR_RNGEN_Pos (2U)
Kojto 122:f9eeca106725 9845 #define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9846 #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
Kojto 122:f9eeca106725 9847 #define RNG_CR_IE_Pos (3U)
Kojto 122:f9eeca106725 9848 #define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 9849 #define RNG_CR_IE RNG_CR_IE_Msk
Kojto 122:f9eeca106725 9850
Kojto 122:f9eeca106725 9851 /******************** Bits definition for RNG_SR register *******************/
Kojto 122:f9eeca106725 9852 #define RNG_SR_DRDY_Pos (0U)
Kojto 122:f9eeca106725 9853 #define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9854 #define RNG_SR_DRDY RNG_SR_DRDY_Msk
Kojto 122:f9eeca106725 9855 #define RNG_SR_CECS_Pos (1U)
Kojto 122:f9eeca106725 9856 #define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9857 #define RNG_SR_CECS RNG_SR_CECS_Msk
Kojto 122:f9eeca106725 9858 #define RNG_SR_SECS_Pos (2U)
Kojto 122:f9eeca106725 9859 #define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9860 #define RNG_SR_SECS RNG_SR_SECS_Msk
Kojto 122:f9eeca106725 9861 #define RNG_SR_CEIS_Pos (5U)
Kojto 122:f9eeca106725 9862 #define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 9863 #define RNG_SR_CEIS RNG_SR_CEIS_Msk
Kojto 122:f9eeca106725 9864 #define RNG_SR_SEIS_Pos (6U)
Kojto 122:f9eeca106725 9865 #define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 9866 #define RNG_SR_SEIS RNG_SR_SEIS_Msk
Kojto 122:f9eeca106725 9867
Kojto 122:f9eeca106725 9868 /******************************************************************************/
Kojto 122:f9eeca106725 9869 /* */
Kojto 122:f9eeca106725 9870 /* Real-Time Clock (RTC) */
Kojto 122:f9eeca106725 9871 /* */
Kojto 122:f9eeca106725 9872 /******************************************************************************/
Kojto 122:f9eeca106725 9873 /*
Kojto 122:f9eeca106725 9874 * @brief Specific device feature definitions
Kojto 122:f9eeca106725 9875 */
Kojto 122:f9eeca106725 9876 #define RTC_TAMPER2_SUPPORT
Kojto 122:f9eeca106725 9877 #define RTC_WAKEUP_SUPPORT
Kojto 122:f9eeca106725 9878 #define RTC_BACKUP_SUPPORT
Kojto 122:f9eeca106725 9879
Kojto 122:f9eeca106725 9880 /******************** Bits definition for RTC_TR register *******************/
Kojto 122:f9eeca106725 9881 #define RTC_TR_PM_Pos (22U)
Kojto 122:f9eeca106725 9882 #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 9883 #define RTC_TR_PM RTC_TR_PM_Msk
Kojto 122:f9eeca106725 9884 #define RTC_TR_HT_Pos (20U)
Kojto 122:f9eeca106725 9885 #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
Kojto 122:f9eeca106725 9886 #define RTC_TR_HT RTC_TR_HT_Msk
Kojto 122:f9eeca106725 9887 #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 9888 #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 9889 #define RTC_TR_HU_Pos (16U)
Kojto 122:f9eeca106725 9890 #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
Kojto 122:f9eeca106725 9891 #define RTC_TR_HU RTC_TR_HU_Msk
Kojto 122:f9eeca106725 9892 #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 9893 #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 9894 #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 9895 #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 9896 #define RTC_TR_MNT_Pos (12U)
Kojto 122:f9eeca106725 9897 #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
Kojto 122:f9eeca106725 9898 #define RTC_TR_MNT RTC_TR_MNT_Msk
Kojto 122:f9eeca106725 9899 #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 9900 #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 9901 #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 9902 #define RTC_TR_MNU_Pos (8U)
Kojto 122:f9eeca106725 9903 #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 9904 #define RTC_TR_MNU RTC_TR_MNU_Msk
Kojto 122:f9eeca106725 9905 #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 9906 #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 9907 #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 9908 #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 9909 #define RTC_TR_ST_Pos (4U)
Kojto 122:f9eeca106725 9910 #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
Kojto 122:f9eeca106725 9911 #define RTC_TR_ST RTC_TR_ST_Msk
Kojto 122:f9eeca106725 9912 #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 9913 #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 9914 #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 9915 #define RTC_TR_SU_Pos (0U)
Kojto 122:f9eeca106725 9916 #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 9917 #define RTC_TR_SU RTC_TR_SU_Msk
Kojto 122:f9eeca106725 9918 #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9919 #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9920 #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9921 #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 9922
Kojto 122:f9eeca106725 9923 /******************** Bits definition for RTC_DR register *******************/
Kojto 122:f9eeca106725 9924 #define RTC_DR_YT_Pos (20U)
Kojto 122:f9eeca106725 9925 #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
Kojto 122:f9eeca106725 9926 #define RTC_DR_YT RTC_DR_YT_Msk
Kojto 122:f9eeca106725 9927 #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 9928 #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 9929 #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 9930 #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 9931 #define RTC_DR_YU_Pos (16U)
Kojto 122:f9eeca106725 9932 #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
Kojto 122:f9eeca106725 9933 #define RTC_DR_YU RTC_DR_YU_Msk
Kojto 122:f9eeca106725 9934 #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 9935 #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 9936 #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 9937 #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 9938 #define RTC_DR_WDU_Pos (13U)
Kojto 122:f9eeca106725 9939 #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
Kojto 122:f9eeca106725 9940 #define RTC_DR_WDU RTC_DR_WDU_Msk
Kojto 122:f9eeca106725 9941 #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 9942 #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 9943 #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 9944 #define RTC_DR_MT_Pos (12U)
Kojto 122:f9eeca106725 9945 #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 9946 #define RTC_DR_MT RTC_DR_MT_Msk
Kojto 122:f9eeca106725 9947 #define RTC_DR_MU_Pos (8U)
Kojto 122:f9eeca106725 9948 #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 9949 #define RTC_DR_MU RTC_DR_MU_Msk
Kojto 122:f9eeca106725 9950 #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 9951 #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 9952 #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 9953 #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 9954 #define RTC_DR_DT_Pos (4U)
Kojto 122:f9eeca106725 9955 #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
Kojto 122:f9eeca106725 9956 #define RTC_DR_DT RTC_DR_DT_Msk
Kojto 122:f9eeca106725 9957 #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 9958 #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 9959 #define RTC_DR_DU_Pos (0U)
Kojto 122:f9eeca106725 9960 #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 9961 #define RTC_DR_DU RTC_DR_DU_Msk
Kojto 122:f9eeca106725 9962 #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 9963 #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 9964 #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 9965 #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 9966
Kojto 122:f9eeca106725 9967 /******************** Bits definition for RTC_CR register *******************/
Kojto 122:f9eeca106725 9968 #define RTC_CR_ITSE_Pos (24U)
Kojto 122:f9eeca106725 9969 #define RTC_CR_ITSE_Msk (0x1U << RTC_CR_ITSE_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 9970 #define RTC_CR_ITSE RTC_CR_ITSE_Msk
Kojto 122:f9eeca106725 9971 #define RTC_CR_COE_Pos (23U)
Kojto 122:f9eeca106725 9972 #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 9973 #define RTC_CR_COE RTC_CR_COE_Msk
Kojto 122:f9eeca106725 9974 #define RTC_CR_OSEL_Pos (21U)
Kojto 122:f9eeca106725 9975 #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
Kojto 122:f9eeca106725 9976 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
Kojto 122:f9eeca106725 9977 #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 9978 #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 9979 #define RTC_CR_POL_Pos (20U)
Kojto 122:f9eeca106725 9980 #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 9981 #define RTC_CR_POL RTC_CR_POL_Msk
Kojto 122:f9eeca106725 9982 #define RTC_CR_COSEL_Pos (19U)
Kojto 122:f9eeca106725 9983 #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 9984 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
Kojto 122:f9eeca106725 9985 #define RTC_CR_BCK_Pos (18U)
Kojto 122:f9eeca106725 9986 #define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 9987 #define RTC_CR_BCK RTC_CR_BCK_Msk
Kojto 122:f9eeca106725 9988 #define RTC_CR_SUB1H_Pos (17U)
Kojto 122:f9eeca106725 9989 #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 9990 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
Kojto 122:f9eeca106725 9991 #define RTC_CR_ADD1H_Pos (16U)
Kojto 122:f9eeca106725 9992 #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 9993 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
Kojto 122:f9eeca106725 9994 #define RTC_CR_TSIE_Pos (15U)
Kojto 122:f9eeca106725 9995 #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 9996 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
Kojto 122:f9eeca106725 9997 #define RTC_CR_WUTIE_Pos (14U)
Kojto 122:f9eeca106725 9998 #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 9999 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
Kojto 122:f9eeca106725 10000 #define RTC_CR_ALRBIE_Pos (13U)
Kojto 122:f9eeca106725 10001 #define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 10002 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
Kojto 122:f9eeca106725 10003 #define RTC_CR_ALRAIE_Pos (12U)
Kojto 122:f9eeca106725 10004 #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 10005 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
Kojto 122:f9eeca106725 10006 #define RTC_CR_TSE_Pos (11U)
Kojto 122:f9eeca106725 10007 #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 10008 #define RTC_CR_TSE RTC_CR_TSE_Msk
Kojto 122:f9eeca106725 10009 #define RTC_CR_WUTE_Pos (10U)
Kojto 122:f9eeca106725 10010 #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 10011 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
Kojto 122:f9eeca106725 10012 #define RTC_CR_ALRBE_Pos (9U)
Kojto 122:f9eeca106725 10013 #define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 10014 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
Kojto 122:f9eeca106725 10015 #define RTC_CR_ALRAE_Pos (8U)
Kojto 122:f9eeca106725 10016 #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 10017 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
Kojto 122:f9eeca106725 10018 #define RTC_CR_FMT_Pos (6U)
Kojto 122:f9eeca106725 10019 #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 10020 #define RTC_CR_FMT RTC_CR_FMT_Msk
Kojto 122:f9eeca106725 10021 #define RTC_CR_BYPSHAD_Pos (5U)
Kojto 122:f9eeca106725 10022 #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 10023 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
Kojto 122:f9eeca106725 10024 #define RTC_CR_REFCKON_Pos (4U)
Kojto 122:f9eeca106725 10025 #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 10026 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
Kojto 122:f9eeca106725 10027 #define RTC_CR_TSEDGE_Pos (3U)
Kojto 122:f9eeca106725 10028 #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 10029 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
Kojto 122:f9eeca106725 10030 #define RTC_CR_WUCKSEL_Pos (0U)
Kojto 122:f9eeca106725 10031 #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
Kojto 122:f9eeca106725 10032 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
Kojto 122:f9eeca106725 10033 #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10034 #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10035 #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 10036
Kojto 122:f9eeca106725 10037 /******************** Bits definition for RTC_ISR register ******************/
Kojto 122:f9eeca106725 10038 #define RTC_ISR_ITSF_Pos (17U)
Kojto 122:f9eeca106725 10039 #define RTC_ISR_ITSF_Msk (0x1U << RTC_ISR_ITSF_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 10040 #define RTC_ISR_ITSF RTC_ISR_ITSF_Msk
Kojto 122:f9eeca106725 10041 #define RTC_ISR_RECALPF_Pos (16U)
Kojto 122:f9eeca106725 10042 #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 10043 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
Kojto 122:f9eeca106725 10044 #define RTC_ISR_TAMP2F_Pos (14U)
Kojto 122:f9eeca106725 10045 #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 10046 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
Kojto 122:f9eeca106725 10047 #define RTC_ISR_TSOVF_Pos (12U)
Kojto 122:f9eeca106725 10048 #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 10049 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
Kojto 122:f9eeca106725 10050 #define RTC_ISR_TSF_Pos (11U)
Kojto 122:f9eeca106725 10051 #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 10052 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
Kojto 122:f9eeca106725 10053 #define RTC_ISR_WUTF_Pos (10U)
Kojto 122:f9eeca106725 10054 #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 10055 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
Kojto 122:f9eeca106725 10056 #define RTC_ISR_ALRBF_Pos (9U)
Kojto 122:f9eeca106725 10057 #define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 10058 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
Kojto 122:f9eeca106725 10059 #define RTC_ISR_ALRAF_Pos (8U)
Kojto 122:f9eeca106725 10060 #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 10061 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
Kojto 122:f9eeca106725 10062 #define RTC_ISR_INIT_Pos (7U)
Kojto 122:f9eeca106725 10063 #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 10064 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
Kojto 122:f9eeca106725 10065 #define RTC_ISR_INITF_Pos (6U)
Kojto 122:f9eeca106725 10066 #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 10067 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
Kojto 122:f9eeca106725 10068 #define RTC_ISR_RSF_Pos (5U)
Kojto 122:f9eeca106725 10069 #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 10070 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
Kojto 122:f9eeca106725 10071 #define RTC_ISR_INITS_Pos (4U)
Kojto 122:f9eeca106725 10072 #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 10073 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
Kojto 122:f9eeca106725 10074 #define RTC_ISR_SHPF_Pos (3U)
Kojto 122:f9eeca106725 10075 #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 10076 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
Kojto 122:f9eeca106725 10077 #define RTC_ISR_WUTWF_Pos (2U)
Kojto 122:f9eeca106725 10078 #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 10079 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
Kojto 122:f9eeca106725 10080 #define RTC_ISR_ALRBWF_Pos (1U)
Kojto 122:f9eeca106725 10081 #define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10082 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
Kojto 122:f9eeca106725 10083 #define RTC_ISR_ALRAWF_Pos (0U)
Kojto 122:f9eeca106725 10084 #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10085 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
Kojto 122:f9eeca106725 10086
Kojto 122:f9eeca106725 10087 /******************** Bits definition for RTC_PRER register *****************/
Kojto 122:f9eeca106725 10088 #define RTC_PRER_PREDIV_A_Pos (16U)
Kojto 122:f9eeca106725 10089 #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
Kojto 122:f9eeca106725 10090 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
Kojto 122:f9eeca106725 10091 #define RTC_PRER_PREDIV_S_Pos (0U)
Kojto 122:f9eeca106725 10092 #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
Kojto 122:f9eeca106725 10093 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
Kojto 122:f9eeca106725 10094
Kojto 122:f9eeca106725 10095 /******************** Bits definition for RTC_WUTR register *****************/
Kojto 122:f9eeca106725 10096 #define RTC_WUTR_WUT_Pos (0U)
Kojto 122:f9eeca106725 10097 #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 10098 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
Kojto 122:f9eeca106725 10099
Kojto 122:f9eeca106725 10100 /******************** Bits definition for RTC_ALRMAR register ***************/
Kojto 122:f9eeca106725 10101 #define RTC_ALRMAR_MSK4_Pos (31U)
Kojto 122:f9eeca106725 10102 #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 10103 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
Kojto 122:f9eeca106725 10104 #define RTC_ALRMAR_WDSEL_Pos (30U)
Kojto 122:f9eeca106725 10105 #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 10106 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
Kojto 122:f9eeca106725 10107 #define RTC_ALRMAR_DT_Pos (28U)
Kojto 122:f9eeca106725 10108 #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
Kojto 122:f9eeca106725 10109 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
Kojto 122:f9eeca106725 10110 #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 10111 #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 10112 #define RTC_ALRMAR_DU_Pos (24U)
Kojto 122:f9eeca106725 10113 #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
Kojto 122:f9eeca106725 10114 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
Kojto 122:f9eeca106725 10115 #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 10116 #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 10117 #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 10118 #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 10119 #define RTC_ALRMAR_MSK3_Pos (23U)
Kojto 122:f9eeca106725 10120 #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 10121 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
Kojto 122:f9eeca106725 10122 #define RTC_ALRMAR_PM_Pos (22U)
Kojto 122:f9eeca106725 10123 #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 10124 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
Kojto 122:f9eeca106725 10125 #define RTC_ALRMAR_HT_Pos (20U)
Kojto 122:f9eeca106725 10126 #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
Kojto 122:f9eeca106725 10127 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
Kojto 122:f9eeca106725 10128 #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 10129 #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 10130 #define RTC_ALRMAR_HU_Pos (16U)
Kojto 122:f9eeca106725 10131 #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
Kojto 122:f9eeca106725 10132 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
Kojto 122:f9eeca106725 10133 #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 10134 #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 10135 #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 10136 #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 10137 #define RTC_ALRMAR_MSK2_Pos (15U)
Kojto 122:f9eeca106725 10138 #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 10139 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
Kojto 122:f9eeca106725 10140 #define RTC_ALRMAR_MNT_Pos (12U)
Kojto 122:f9eeca106725 10141 #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
Kojto 122:f9eeca106725 10142 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
Kojto 122:f9eeca106725 10143 #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 10144 #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 10145 #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 10146 #define RTC_ALRMAR_MNU_Pos (8U)
Kojto 122:f9eeca106725 10147 #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 10148 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
Kojto 122:f9eeca106725 10149 #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 10150 #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 10151 #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 10152 #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 10153 #define RTC_ALRMAR_MSK1_Pos (7U)
Kojto 122:f9eeca106725 10154 #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 10155 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
Kojto 122:f9eeca106725 10156 #define RTC_ALRMAR_ST_Pos (4U)
Kojto 122:f9eeca106725 10157 #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
Kojto 122:f9eeca106725 10158 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
Kojto 122:f9eeca106725 10159 #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 10160 #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 10161 #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 10162 #define RTC_ALRMAR_SU_Pos (0U)
Kojto 122:f9eeca106725 10163 #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 10164 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
Kojto 122:f9eeca106725 10165 #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10166 #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10167 #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 10168 #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 10169
Kojto 122:f9eeca106725 10170 /******************** Bits definition for RTC_ALRMBR register ***************/
Kojto 122:f9eeca106725 10171 #define RTC_ALRMBR_MSK4_Pos (31U)
Kojto 122:f9eeca106725 10172 #define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 10173 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
Kojto 122:f9eeca106725 10174 #define RTC_ALRMBR_WDSEL_Pos (30U)
Kojto 122:f9eeca106725 10175 #define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 10176 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
Kojto 122:f9eeca106725 10177 #define RTC_ALRMBR_DT_Pos (28U)
Kojto 122:f9eeca106725 10178 #define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
Kojto 122:f9eeca106725 10179 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
Kojto 122:f9eeca106725 10180 #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 10181 #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 10182 #define RTC_ALRMBR_DU_Pos (24U)
Kojto 122:f9eeca106725 10183 #define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
Kojto 122:f9eeca106725 10184 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
Kojto 122:f9eeca106725 10185 #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 10186 #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 10187 #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 10188 #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 10189 #define RTC_ALRMBR_MSK3_Pos (23U)
Kojto 122:f9eeca106725 10190 #define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 10191 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
Kojto 122:f9eeca106725 10192 #define RTC_ALRMBR_PM_Pos (22U)
Kojto 122:f9eeca106725 10193 #define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 10194 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
Kojto 122:f9eeca106725 10195 #define RTC_ALRMBR_HT_Pos (20U)
Kojto 122:f9eeca106725 10196 #define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
Kojto 122:f9eeca106725 10197 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
Kojto 122:f9eeca106725 10198 #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 10199 #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 10200 #define RTC_ALRMBR_HU_Pos (16U)
Kojto 122:f9eeca106725 10201 #define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
Kojto 122:f9eeca106725 10202 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
Kojto 122:f9eeca106725 10203 #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 10204 #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 10205 #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 10206 #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 10207 #define RTC_ALRMBR_MSK2_Pos (15U)
Kojto 122:f9eeca106725 10208 #define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 10209 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
Kojto 122:f9eeca106725 10210 #define RTC_ALRMBR_MNT_Pos (12U)
Kojto 122:f9eeca106725 10211 #define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
Kojto 122:f9eeca106725 10212 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
Kojto 122:f9eeca106725 10213 #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 10214 #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 10215 #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 10216 #define RTC_ALRMBR_MNU_Pos (8U)
Kojto 122:f9eeca106725 10217 #define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 10218 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
Kojto 122:f9eeca106725 10219 #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 10220 #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 10221 #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 10222 #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 10223 #define RTC_ALRMBR_MSK1_Pos (7U)
Kojto 122:f9eeca106725 10224 #define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 10225 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
Kojto 122:f9eeca106725 10226 #define RTC_ALRMBR_ST_Pos (4U)
Kojto 122:f9eeca106725 10227 #define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
Kojto 122:f9eeca106725 10228 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
Kojto 122:f9eeca106725 10229 #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 10230 #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 10231 #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 10232 #define RTC_ALRMBR_SU_Pos (0U)
Kojto 122:f9eeca106725 10233 #define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 10234 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
Kojto 122:f9eeca106725 10235 #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10236 #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10237 #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 10238 #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 10239
Kojto 122:f9eeca106725 10240 /******************** Bits definition for RTC_WPR register ******************/
Kojto 122:f9eeca106725 10241 #define RTC_WPR_KEY_Pos (0U)
Kojto 122:f9eeca106725 10242 #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 10243 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
Kojto 122:f9eeca106725 10244
Kojto 122:f9eeca106725 10245 /******************** Bits definition for RTC_SSR register ******************/
Kojto 122:f9eeca106725 10246 #define RTC_SSR_SS_Pos (0U)
Kojto 122:f9eeca106725 10247 #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 10248 #define RTC_SSR_SS RTC_SSR_SS_Msk
Kojto 122:f9eeca106725 10249
Kojto 122:f9eeca106725 10250 /******************** Bits definition for RTC_SHIFTR register ***************/
Kojto 122:f9eeca106725 10251 #define RTC_SHIFTR_SUBFS_Pos (0U)
Kojto 122:f9eeca106725 10252 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
Kojto 122:f9eeca106725 10253 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
Kojto 122:f9eeca106725 10254 #define RTC_SHIFTR_ADD1S_Pos (31U)
Kojto 122:f9eeca106725 10255 #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 10256 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
Kojto 122:f9eeca106725 10257
Kojto 122:f9eeca106725 10258 /******************** Bits definition for RTC_TSTR register *****************/
Kojto 122:f9eeca106725 10259 #define RTC_TSTR_PM_Pos (22U)
Kojto 122:f9eeca106725 10260 #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 10261 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
Kojto 122:f9eeca106725 10262 #define RTC_TSTR_HT_Pos (20U)
Kojto 122:f9eeca106725 10263 #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
Kojto 122:f9eeca106725 10264 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
Kojto 122:f9eeca106725 10265 #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 10266 #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 10267 #define RTC_TSTR_HU_Pos (16U)
Kojto 122:f9eeca106725 10268 #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
Kojto 122:f9eeca106725 10269 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
Kojto 122:f9eeca106725 10270 #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 10271 #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 10272 #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 10273 #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 10274 #define RTC_TSTR_MNT_Pos (12U)
Kojto 122:f9eeca106725 10275 #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
Kojto 122:f9eeca106725 10276 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
Kojto 122:f9eeca106725 10277 #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 10278 #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 10279 #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 10280 #define RTC_TSTR_MNU_Pos (8U)
Kojto 122:f9eeca106725 10281 #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 10282 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
Kojto 122:f9eeca106725 10283 #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 10284 #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 10285 #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 10286 #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 10287 #define RTC_TSTR_ST_Pos (4U)
Kojto 122:f9eeca106725 10288 #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
Kojto 122:f9eeca106725 10289 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
Kojto 122:f9eeca106725 10290 #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 10291 #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 10292 #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 10293 #define RTC_TSTR_SU_Pos (0U)
Kojto 122:f9eeca106725 10294 #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 10295 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
Kojto 122:f9eeca106725 10296 #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10297 #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10298 #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 10299 #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 10300
Kojto 122:f9eeca106725 10301 /******************** Bits definition for RTC_TSDR register *****************/
Kojto 122:f9eeca106725 10302 #define RTC_TSDR_WDU_Pos (13U)
Kojto 122:f9eeca106725 10303 #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
Kojto 122:f9eeca106725 10304 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
Kojto 122:f9eeca106725 10305 #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 10306 #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 10307 #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 10308 #define RTC_TSDR_MT_Pos (12U)
Kojto 122:f9eeca106725 10309 #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 10310 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
Kojto 122:f9eeca106725 10311 #define RTC_TSDR_MU_Pos (8U)
Kojto 122:f9eeca106725 10312 #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 10313 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
Kojto 122:f9eeca106725 10314 #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 10315 #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 10316 #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 10317 #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 10318 #define RTC_TSDR_DT_Pos (4U)
Kojto 122:f9eeca106725 10319 #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
Kojto 122:f9eeca106725 10320 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
Kojto 122:f9eeca106725 10321 #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 10322 #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 10323 #define RTC_TSDR_DU_Pos (0U)
Kojto 122:f9eeca106725 10324 #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 10325 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
Kojto 122:f9eeca106725 10326 #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10327 #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10328 #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 10329 #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 10330
Kojto 122:f9eeca106725 10331 /******************** Bits definition for RTC_TSSSR register ****************/
Kojto 122:f9eeca106725 10332 #define RTC_TSSSR_SS_Pos (0U)
Kojto 122:f9eeca106725 10333 #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 10334 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
Kojto 122:f9eeca106725 10335
Kojto 122:f9eeca106725 10336 /******************** Bits definition for RTC_CAL register *****************/
Kojto 122:f9eeca106725 10337 #define RTC_CALR_CALP_Pos (15U)
Kojto 122:f9eeca106725 10338 #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 10339 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
Kojto 122:f9eeca106725 10340 #define RTC_CALR_CALW8_Pos (14U)
Kojto 122:f9eeca106725 10341 #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 10342 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
Kojto 122:f9eeca106725 10343 #define RTC_CALR_CALW16_Pos (13U)
Kojto 122:f9eeca106725 10344 #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 10345 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
Kojto 122:f9eeca106725 10346 #define RTC_CALR_CALM_Pos (0U)
Kojto 122:f9eeca106725 10347 #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
Kojto 122:f9eeca106725 10348 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
Kojto 122:f9eeca106725 10349 #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10350 #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10351 #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 10352 #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 10353 #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 10354 #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 10355 #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 10356 #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 10357 #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 10358
Kojto 122:f9eeca106725 10359 /******************** Bits definition for RTC_TAMPCR register ***************/
Kojto 122:f9eeca106725 10360 #define RTC_TAMPCR_TAMP2MF_Pos (21U)
Kojto 122:f9eeca106725 10361 #define RTC_TAMPCR_TAMP2MF_Msk (0x1U << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 10362 #define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk
Kojto 122:f9eeca106725 10363 #define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
Kojto 122:f9eeca106725 10364 #define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 10365 #define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk
Kojto 122:f9eeca106725 10366 #define RTC_TAMPCR_TAMP2IE_Pos (19U)
Kojto 122:f9eeca106725 10367 #define RTC_TAMPCR_TAMP2IE_Msk (0x1U << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 10368 #define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk
Kojto 122:f9eeca106725 10369 #define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
Kojto 122:f9eeca106725 10370 #define RTC_TAMPCR_TAMPPUDIS_Msk (0x1U << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 10371 #define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk
Kojto 122:f9eeca106725 10372 #define RTC_TAMPCR_TAMPPRCH_Pos (13U)
Kojto 122:f9eeca106725 10373 #define RTC_TAMPCR_TAMPPRCH_Msk (0x3U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */
Kojto 122:f9eeca106725 10374 #define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk
Kojto 122:f9eeca106725 10375 #define RTC_TAMPCR_TAMPPRCH_0 (0x1U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 10376 #define RTC_TAMPCR_TAMPPRCH_1 (0x2U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 10377 #define RTC_TAMPCR_TAMPFLT_Pos (11U)
Kojto 122:f9eeca106725 10378 #define RTC_TAMPCR_TAMPFLT_Msk (0x3U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */
Kojto 122:f9eeca106725 10379 #define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk
Kojto 122:f9eeca106725 10380 #define RTC_TAMPCR_TAMPFLT_0 (0x1U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 10381 #define RTC_TAMPCR_TAMPFLT_1 (0x2U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 10382 #define RTC_TAMPCR_TAMPFREQ_Pos (8U)
Kojto 122:f9eeca106725 10383 #define RTC_TAMPCR_TAMPFREQ_Msk (0x7U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */
Kojto 122:f9eeca106725 10384 #define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk
Kojto 122:f9eeca106725 10385 #define RTC_TAMPCR_TAMPFREQ_0 (0x1U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 10386 #define RTC_TAMPCR_TAMPFREQ_1 (0x2U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 10387 #define RTC_TAMPCR_TAMPFREQ_2 (0x4U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 10388 #define RTC_TAMPCR_TAMPTS_Pos (7U)
Kojto 122:f9eeca106725 10389 #define RTC_TAMPCR_TAMPTS_Msk (0x1U << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 10390 #define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk
Kojto 122:f9eeca106725 10391 #define RTC_TAMPCR_TAMP2TRG_Pos (4U)
Kojto 122:f9eeca106725 10392 #define RTC_TAMPCR_TAMP2TRG_Msk (0x1U << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 10393 #define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk
Kojto 122:f9eeca106725 10394 #define RTC_TAMPCR_TAMP2E_Pos (3U)
Kojto 122:f9eeca106725 10395 #define RTC_TAMPCR_TAMP2E_Msk (0x1U << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 10396 #define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk
Kojto 122:f9eeca106725 10397 #define RTC_TAMPCR_TAMPIE_Pos (2U)
Kojto 122:f9eeca106725 10398 #define RTC_TAMPCR_TAMPIE_Msk (0x1U << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 10399 #define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk
Kojto 122:f9eeca106725 10400
Kojto 122:f9eeca106725 10401 /******************** Bits definition for RTC_ALRMASSR register *************/
Kojto 122:f9eeca106725 10402 #define RTC_ALRMASSR_MASKSS_Pos (24U)
Kojto 122:f9eeca106725 10403 #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
Kojto 122:f9eeca106725 10404 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
Kojto 122:f9eeca106725 10405 #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 10406 #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 10407 #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 10408 #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 10409 #define RTC_ALRMASSR_SS_Pos (0U)
Kojto 122:f9eeca106725 10410 #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
Kojto 122:f9eeca106725 10411 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
Kojto 122:f9eeca106725 10412
Kojto 122:f9eeca106725 10413 /******************** Bits definition for RTC_ALRMBSSR register *************/
Kojto 122:f9eeca106725 10414 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
Kojto 122:f9eeca106725 10415 #define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
Kojto 122:f9eeca106725 10416 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
Kojto 122:f9eeca106725 10417 #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 10418 #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 10419 #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 10420 #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 10421 #define RTC_ALRMBSSR_SS_Pos (0U)
Kojto 122:f9eeca106725 10422 #define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
Kojto 122:f9eeca106725 10423 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
Kojto 122:f9eeca106725 10424
Kojto 122:f9eeca106725 10425 /******************** Bits definition for RTC_0R register *******************/
Kojto 122:f9eeca106725 10426 #define RTC_OR_OUT_RMP_Pos (1U)
Kojto 122:f9eeca106725 10427 #define RTC_OR_OUT_RMP_Msk (0x1U << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10428 #define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk
Kojto 122:f9eeca106725 10429 #define RTC_OR_ALARMOUTTYPE_Pos (0U)
Kojto 122:f9eeca106725 10430 #define RTC_OR_ALARMOUTTYPE_Msk (0x1U << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10431 #define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk
Kojto 122:f9eeca106725 10432
Kojto 122:f9eeca106725 10433
Kojto 122:f9eeca106725 10434 /******************** Bits definition for RTC_BKP0R register ****************/
Kojto 122:f9eeca106725 10435 #define RTC_BKP0R_Pos (0U)
Kojto 122:f9eeca106725 10436 #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 10437 #define RTC_BKP0R RTC_BKP0R_Msk
Kojto 122:f9eeca106725 10438
Kojto 122:f9eeca106725 10439 /******************** Bits definition for RTC_BKP1R register ****************/
Kojto 122:f9eeca106725 10440 #define RTC_BKP1R_Pos (0U)
Kojto 122:f9eeca106725 10441 #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 10442 #define RTC_BKP1R RTC_BKP1R_Msk
Kojto 122:f9eeca106725 10443
Kojto 122:f9eeca106725 10444 /******************** Bits definition for RTC_BKP2R register ****************/
Kojto 122:f9eeca106725 10445 #define RTC_BKP2R_Pos (0U)
Kojto 122:f9eeca106725 10446 #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 10447 #define RTC_BKP2R RTC_BKP2R_Msk
Kojto 122:f9eeca106725 10448
Kojto 122:f9eeca106725 10449 /******************** Bits definition for RTC_BKP3R register ****************/
Kojto 122:f9eeca106725 10450 #define RTC_BKP3R_Pos (0U)
Kojto 122:f9eeca106725 10451 #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 10452 #define RTC_BKP3R RTC_BKP3R_Msk
Kojto 122:f9eeca106725 10453
Kojto 122:f9eeca106725 10454 /******************** Bits definition for RTC_BKP4R register ****************/
Kojto 122:f9eeca106725 10455 #define RTC_BKP4R_Pos (0U)
Kojto 122:f9eeca106725 10456 #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 10457 #define RTC_BKP4R RTC_BKP4R_Msk
Kojto 122:f9eeca106725 10458
Kojto 122:f9eeca106725 10459 /******************** Bits definition for RTC_BKP5R register ****************/
Kojto 122:f9eeca106725 10460 #define RTC_BKP5R_Pos (0U)
Kojto 122:f9eeca106725 10461 #define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 10462 #define RTC_BKP5R RTC_BKP5R_Msk
Kojto 122:f9eeca106725 10463
Kojto 122:f9eeca106725 10464 /******************** Bits definition for RTC_BKP6R register ****************/
Kojto 122:f9eeca106725 10465 #define RTC_BKP6R_Pos (0U)
Kojto 122:f9eeca106725 10466 #define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 10467 #define RTC_BKP6R RTC_BKP6R_Msk
Kojto 122:f9eeca106725 10468
Kojto 122:f9eeca106725 10469 /******************** Bits definition for RTC_BKP7R register ****************/
Kojto 122:f9eeca106725 10470 #define RTC_BKP7R_Pos (0U)
Kojto 122:f9eeca106725 10471 #define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 10472 #define RTC_BKP7R RTC_BKP7R_Msk
Kojto 122:f9eeca106725 10473
Kojto 122:f9eeca106725 10474 /******************** Bits definition for RTC_BKP8R register ****************/
Kojto 122:f9eeca106725 10475 #define RTC_BKP8R_Pos (0U)
Kojto 122:f9eeca106725 10476 #define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 10477 #define RTC_BKP8R RTC_BKP8R_Msk
Kojto 122:f9eeca106725 10478
Kojto 122:f9eeca106725 10479 /******************** Bits definition for RTC_BKP9R register ****************/
Kojto 122:f9eeca106725 10480 #define RTC_BKP9R_Pos (0U)
Kojto 122:f9eeca106725 10481 #define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 10482 #define RTC_BKP9R RTC_BKP9R_Msk
Kojto 122:f9eeca106725 10483
Kojto 122:f9eeca106725 10484 /******************** Bits definition for RTC_BKP10R register ***************/
Kojto 122:f9eeca106725 10485 #define RTC_BKP10R_Pos (0U)
Kojto 122:f9eeca106725 10486 #define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 10487 #define RTC_BKP10R RTC_BKP10R_Msk
Kojto 122:f9eeca106725 10488
Kojto 122:f9eeca106725 10489 /******************** Bits definition for RTC_BKP11R register ***************/
Kojto 122:f9eeca106725 10490 #define RTC_BKP11R_Pos (0U)
Kojto 122:f9eeca106725 10491 #define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 10492 #define RTC_BKP11R RTC_BKP11R_Msk
Kojto 122:f9eeca106725 10493
Kojto 122:f9eeca106725 10494 /******************** Bits definition for RTC_BKP12R register ***************/
Kojto 122:f9eeca106725 10495 #define RTC_BKP12R_Pos (0U)
Kojto 122:f9eeca106725 10496 #define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 10497 #define RTC_BKP12R RTC_BKP12R_Msk
Kojto 122:f9eeca106725 10498
Kojto 122:f9eeca106725 10499 /******************** Bits definition for RTC_BKP13R register ***************/
Kojto 122:f9eeca106725 10500 #define RTC_BKP13R_Pos (0U)
Kojto 122:f9eeca106725 10501 #define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 10502 #define RTC_BKP13R RTC_BKP13R_Msk
Kojto 122:f9eeca106725 10503
Kojto 122:f9eeca106725 10504 /******************** Bits definition for RTC_BKP14R register ***************/
Kojto 122:f9eeca106725 10505 #define RTC_BKP14R_Pos (0U)
Kojto 122:f9eeca106725 10506 #define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 10507 #define RTC_BKP14R RTC_BKP14R_Msk
Kojto 122:f9eeca106725 10508
Kojto 122:f9eeca106725 10509 /******************** Bits definition for RTC_BKP15R register ***************/
Kojto 122:f9eeca106725 10510 #define RTC_BKP15R_Pos (0U)
Kojto 122:f9eeca106725 10511 #define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 10512 #define RTC_BKP15R RTC_BKP15R_Msk
Kojto 122:f9eeca106725 10513
Kojto 122:f9eeca106725 10514 /******************** Bits definition for RTC_BKP16R register ***************/
Kojto 122:f9eeca106725 10515 #define RTC_BKP16R_Pos (0U)
Kojto 122:f9eeca106725 10516 #define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 10517 #define RTC_BKP16R RTC_BKP16R_Msk
Kojto 122:f9eeca106725 10518
Kojto 122:f9eeca106725 10519 /******************** Bits definition for RTC_BKP17R register ***************/
Kojto 122:f9eeca106725 10520 #define RTC_BKP17R_Pos (0U)
Kojto 122:f9eeca106725 10521 #define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 10522 #define RTC_BKP17R RTC_BKP17R_Msk
Kojto 122:f9eeca106725 10523
Kojto 122:f9eeca106725 10524 /******************** Bits definition for RTC_BKP18R register ***************/
Kojto 122:f9eeca106725 10525 #define RTC_BKP18R_Pos (0U)
Kojto 122:f9eeca106725 10526 #define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 10527 #define RTC_BKP18R RTC_BKP18R_Msk
Kojto 122:f9eeca106725 10528
Kojto 122:f9eeca106725 10529 /******************** Bits definition for RTC_BKP19R register ***************/
Kojto 122:f9eeca106725 10530 #define RTC_BKP19R_Pos (0U)
Kojto 122:f9eeca106725 10531 #define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 10532 #define RTC_BKP19R RTC_BKP19R_Msk
Kojto 122:f9eeca106725 10533
Kojto 122:f9eeca106725 10534 /******************** Bits definition for RTC_BKP20R register ***************/
Kojto 122:f9eeca106725 10535 #define RTC_BKP20R_Pos (0U)
Kojto 122:f9eeca106725 10536 #define RTC_BKP20R_Msk (0xFFFFFFFFU << RTC_BKP20R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 10537 #define RTC_BKP20R RTC_BKP20R_Msk
Kojto 122:f9eeca106725 10538
Kojto 122:f9eeca106725 10539 /******************** Bits definition for RTC_BKP21R register ***************/
Kojto 122:f9eeca106725 10540 #define RTC_BKP21R_Pos (0U)
Kojto 122:f9eeca106725 10541 #define RTC_BKP21R_Msk (0xFFFFFFFFU << RTC_BKP21R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 10542 #define RTC_BKP21R RTC_BKP21R_Msk
Kojto 122:f9eeca106725 10543
Kojto 122:f9eeca106725 10544 /******************** Bits definition for RTC_BKP22R register ***************/
Kojto 122:f9eeca106725 10545 #define RTC_BKP22R_Pos (0U)
Kojto 122:f9eeca106725 10546 #define RTC_BKP22R_Msk (0xFFFFFFFFU << RTC_BKP22R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 10547 #define RTC_BKP22R RTC_BKP22R_Msk
Kojto 122:f9eeca106725 10548
Kojto 122:f9eeca106725 10549 /******************** Bits definition for RTC_BKP23R register ***************/
Kojto 122:f9eeca106725 10550 #define RTC_BKP23R_Pos (0U)
Kojto 122:f9eeca106725 10551 #define RTC_BKP23R_Msk (0xFFFFFFFFU << RTC_BKP23R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 10552 #define RTC_BKP23R RTC_BKP23R_Msk
Kojto 122:f9eeca106725 10553
Kojto 122:f9eeca106725 10554 /******************** Bits definition for RTC_BKP24R register ***************/
Kojto 122:f9eeca106725 10555 #define RTC_BKP24R_Pos (0U)
Kojto 122:f9eeca106725 10556 #define RTC_BKP24R_Msk (0xFFFFFFFFU << RTC_BKP24R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 10557 #define RTC_BKP24R RTC_BKP24R_Msk
Kojto 122:f9eeca106725 10558
Kojto 122:f9eeca106725 10559 /******************** Bits definition for RTC_BKP25R register ***************/
Kojto 122:f9eeca106725 10560 #define RTC_BKP25R_Pos (0U)
Kojto 122:f9eeca106725 10561 #define RTC_BKP25R_Msk (0xFFFFFFFFU << RTC_BKP25R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 10562 #define RTC_BKP25R RTC_BKP25R_Msk
Kojto 122:f9eeca106725 10563
Kojto 122:f9eeca106725 10564 /******************** Bits definition for RTC_BKP26R register ***************/
Kojto 122:f9eeca106725 10565 #define RTC_BKP26R_Pos (0U)
Kojto 122:f9eeca106725 10566 #define RTC_BKP26R_Msk (0xFFFFFFFFU << RTC_BKP26R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 10567 #define RTC_BKP26R RTC_BKP26R_Msk
Kojto 122:f9eeca106725 10568
Kojto 122:f9eeca106725 10569 /******************** Bits definition for RTC_BKP27R register ***************/
Kojto 122:f9eeca106725 10570 #define RTC_BKP27R_Pos (0U)
Kojto 122:f9eeca106725 10571 #define RTC_BKP27R_Msk (0xFFFFFFFFU << RTC_BKP27R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 10572 #define RTC_BKP27R RTC_BKP27R_Msk
Kojto 122:f9eeca106725 10573
Kojto 122:f9eeca106725 10574 /******************** Bits definition for RTC_BKP28R register ***************/
Kojto 122:f9eeca106725 10575 #define RTC_BKP28R_Pos (0U)
Kojto 122:f9eeca106725 10576 #define RTC_BKP28R_Msk (0xFFFFFFFFU << RTC_BKP28R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 10577 #define RTC_BKP28R RTC_BKP28R_Msk
Kojto 122:f9eeca106725 10578
Kojto 122:f9eeca106725 10579 /******************** Bits definition for RTC_BKP29R register ***************/
Kojto 122:f9eeca106725 10580 #define RTC_BKP29R_Pos (0U)
Kojto 122:f9eeca106725 10581 #define RTC_BKP29R_Msk (0xFFFFFFFFU << RTC_BKP29R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 10582 #define RTC_BKP29R RTC_BKP29R_Msk
Kojto 122:f9eeca106725 10583
Kojto 122:f9eeca106725 10584 /******************** Bits definition for RTC_BKP30R register ***************/
Kojto 122:f9eeca106725 10585 #define RTC_BKP30R_Pos (0U)
Kojto 122:f9eeca106725 10586 #define RTC_BKP30R_Msk (0xFFFFFFFFU << RTC_BKP30R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 10587 #define RTC_BKP30R RTC_BKP30R_Msk
Kojto 122:f9eeca106725 10588
Kojto 122:f9eeca106725 10589 /******************** Bits definition for RTC_BKP31R register ***************/
Kojto 122:f9eeca106725 10590 #define RTC_BKP31R_Pos (0U)
Kojto 122:f9eeca106725 10591 #define RTC_BKP31R_Msk (0xFFFFFFFFU << RTC_BKP31R_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 10592 #define RTC_BKP31R RTC_BKP31R_Msk
Kojto 122:f9eeca106725 10593
Kojto 122:f9eeca106725 10594 /******************** Number of backup registers ******************************/
Kojto 122:f9eeca106725 10595 #define RTC_BKP_NUMBER 32U
Kojto 122:f9eeca106725 10596
Kojto 122:f9eeca106725 10597 /******************************************************************************/
Kojto 122:f9eeca106725 10598 /* */
Kojto 122:f9eeca106725 10599 /* Serial Audio Interface */
Kojto 122:f9eeca106725 10600 /* */
Kojto 122:f9eeca106725 10601 /******************************************************************************/
Kojto 122:f9eeca106725 10602 /******************** Bit definition for SAI_GCR register *******************/
Kojto 122:f9eeca106725 10603 #define SAI_GCR_SYNCIN_Pos (0U)
Kojto 122:f9eeca106725 10604 #define SAI_GCR_SYNCIN_Msk (0x3U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 10605 #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
Kojto 122:f9eeca106725 10606 #define SAI_GCR_SYNCIN_0 (0x1U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10607 #define SAI_GCR_SYNCIN_1 (0x2U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10608
Kojto 122:f9eeca106725 10609 #define SAI_GCR_SYNCOUT_Pos (4U)
Kojto 122:f9eeca106725 10610 #define SAI_GCR_SYNCOUT_Msk (0x3U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
Kojto 122:f9eeca106725 10611 #define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
Kojto 122:f9eeca106725 10612 #define SAI_GCR_SYNCOUT_0 (0x1U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 10613 #define SAI_GCR_SYNCOUT_1 (0x2U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 10614
Kojto 122:f9eeca106725 10615 /******************* Bit definition for SAI_xCR1 register *******************/
Kojto 122:f9eeca106725 10616 #define SAI_xCR1_MODE_Pos (0U)
Kojto 122:f9eeca106725 10617 #define SAI_xCR1_MODE_Msk (0x3U << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 10618 #define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
Kojto 122:f9eeca106725 10619 #define SAI_xCR1_MODE_0 (0x1U << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10620 #define SAI_xCR1_MODE_1 (0x2U << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10621
Kojto 122:f9eeca106725 10622 #define SAI_xCR1_PRTCFG_Pos (2U)
Kojto 122:f9eeca106725 10623 #define SAI_xCR1_PRTCFG_Msk (0x3U << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
Kojto 122:f9eeca106725 10624 #define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
Kojto 122:f9eeca106725 10625 #define SAI_xCR1_PRTCFG_0 (0x1U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 10626 #define SAI_xCR1_PRTCFG_1 (0x2U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 10627
Kojto 122:f9eeca106725 10628 #define SAI_xCR1_DS_Pos (5U)
Kojto 122:f9eeca106725 10629 #define SAI_xCR1_DS_Msk (0x7U << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
Kojto 122:f9eeca106725 10630 #define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
Kojto 122:f9eeca106725 10631 #define SAI_xCR1_DS_0 (0x1U << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 10632 #define SAI_xCR1_DS_1 (0x2U << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 10633 #define SAI_xCR1_DS_2 (0x4U << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 10634
Kojto 122:f9eeca106725 10635 #define SAI_xCR1_LSBFIRST_Pos (8U)
Kojto 122:f9eeca106725 10636 #define SAI_xCR1_LSBFIRST_Msk (0x1U << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 10637 #define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
Kojto 122:f9eeca106725 10638 #define SAI_xCR1_CKSTR_Pos (9U)
Kojto 122:f9eeca106725 10639 #define SAI_xCR1_CKSTR_Msk (0x1U << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 10640 #define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
Kojto 122:f9eeca106725 10641
Kojto 122:f9eeca106725 10642 #define SAI_xCR1_SYNCEN_Pos (10U)
Kojto 122:f9eeca106725 10643 #define SAI_xCR1_SYNCEN_Msk (0x3U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
Kojto 122:f9eeca106725 10644 #define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
Kojto 122:f9eeca106725 10645 #define SAI_xCR1_SYNCEN_0 (0x1U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 10646 #define SAI_xCR1_SYNCEN_1 (0x2U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 10647
Kojto 122:f9eeca106725 10648 #define SAI_xCR1_MONO_Pos (12U)
Kojto 122:f9eeca106725 10649 #define SAI_xCR1_MONO_Msk (0x1U << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 10650 #define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
Kojto 122:f9eeca106725 10651 #define SAI_xCR1_OUTDRIV_Pos (13U)
Kojto 122:f9eeca106725 10652 #define SAI_xCR1_OUTDRIV_Msk (0x1U << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 10653 #define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
Kojto 122:f9eeca106725 10654 #define SAI_xCR1_SAIEN_Pos (16U)
Kojto 122:f9eeca106725 10655 #define SAI_xCR1_SAIEN_Msk (0x1U << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 10656 #define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
Kojto 122:f9eeca106725 10657 #define SAI_xCR1_DMAEN_Pos (17U)
Kojto 122:f9eeca106725 10658 #define SAI_xCR1_DMAEN_Msk (0x1U << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 10659 #define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
Kojto 122:f9eeca106725 10660 #define SAI_xCR1_NODIV_Pos (19U)
Kojto 122:f9eeca106725 10661 #define SAI_xCR1_NODIV_Msk (0x1U << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 10662 #define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
Kojto 122:f9eeca106725 10663
Kojto 122:f9eeca106725 10664 #define SAI_xCR1_MCKDIV_Pos (20U)
Kojto 122:f9eeca106725 10665 #define SAI_xCR1_MCKDIV_Msk (0xFU << SAI_xCR1_MCKDIV_Pos) /*!< 0x00F00000 */
Kojto 122:f9eeca106725 10666 #define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[3:0] (Master ClocK Divider) */
Kojto 122:f9eeca106725 10667 #define SAI_xCR1_MCKDIV_0 (0x00100000U) /*!<Bit 0 */
Kojto 122:f9eeca106725 10668 #define SAI_xCR1_MCKDIV_1 (0x00200000U) /*!<Bit 1 */
Kojto 122:f9eeca106725 10669 #define SAI_xCR1_MCKDIV_2 (0x00400000U) /*!<Bit 2 */
Kojto 122:f9eeca106725 10670 #define SAI_xCR1_MCKDIV_3 (0x00800000U) /*!<Bit 3 */
Kojto 122:f9eeca106725 10671
Kojto 122:f9eeca106725 10672 /******************* Bit definition for SAI_xCR2 register *******************/
Kojto 122:f9eeca106725 10673 #define SAI_xCR2_FTH_Pos (0U)
Kojto 122:f9eeca106725 10674 #define SAI_xCR2_FTH_Msk (0x7U << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
Kojto 122:f9eeca106725 10675 #define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
Kojto 122:f9eeca106725 10676 #define SAI_xCR2_FTH_0 (0x1U << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10677 #define SAI_xCR2_FTH_1 (0x2U << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10678 #define SAI_xCR2_FTH_2 (0x4U << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 10679
Kojto 122:f9eeca106725 10680 #define SAI_xCR2_FFLUSH_Pos (3U)
Kojto 122:f9eeca106725 10681 #define SAI_xCR2_FFLUSH_Msk (0x1U << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 10682 #define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
Kojto 122:f9eeca106725 10683 #define SAI_xCR2_TRIS_Pos (4U)
Kojto 122:f9eeca106725 10684 #define SAI_xCR2_TRIS_Msk (0x1U << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 10685 #define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
Kojto 122:f9eeca106725 10686 #define SAI_xCR2_MUTE_Pos (5U)
Kojto 122:f9eeca106725 10687 #define SAI_xCR2_MUTE_Msk (0x1U << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 10688 #define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
Kojto 122:f9eeca106725 10689 #define SAI_xCR2_MUTEVAL_Pos (6U)
Kojto 122:f9eeca106725 10690 #define SAI_xCR2_MUTEVAL_Msk (0x1U << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 10691 #define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
Kojto 122:f9eeca106725 10692
Kojto 122:f9eeca106725 10693
Kojto 122:f9eeca106725 10694 #define SAI_xCR2_MUTECNT_Pos (7U)
Kojto 122:f9eeca106725 10695 #define SAI_xCR2_MUTECNT_Msk (0x3FU << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
Kojto 122:f9eeca106725 10696 #define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
Kojto 122:f9eeca106725 10697 #define SAI_xCR2_MUTECNT_0 (0x01U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 10698 #define SAI_xCR2_MUTECNT_1 (0x02U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 10699 #define SAI_xCR2_MUTECNT_2 (0x04U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 10700 #define SAI_xCR2_MUTECNT_3 (0x08U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 10701 #define SAI_xCR2_MUTECNT_4 (0x10U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 10702 #define SAI_xCR2_MUTECNT_5 (0x20U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 10703
Kojto 122:f9eeca106725 10704 #define SAI_xCR2_CPL_Pos (13U)
Kojto 122:f9eeca106725 10705 #define SAI_xCR2_CPL_Msk (0x1U << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 10706 #define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!<CPL mode */
Kojto 122:f9eeca106725 10707 #define SAI_xCR2_COMP_Pos (14U)
Kojto 122:f9eeca106725 10708 #define SAI_xCR2_COMP_Msk (0x3U << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
Kojto 122:f9eeca106725 10709 #define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
Kojto 122:f9eeca106725 10710 #define SAI_xCR2_COMP_0 (0x1U << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 10711 #define SAI_xCR2_COMP_1 (0x2U << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 10712
Kojto 122:f9eeca106725 10713
Kojto 122:f9eeca106725 10714 /****************** Bit definition for SAI_xFRCR register *******************/
Kojto 122:f9eeca106725 10715 #define SAI_xFRCR_FRL_Pos (0U)
Kojto 122:f9eeca106725 10716 #define SAI_xFRCR_FRL_Msk (0xFFU << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 10717 #define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[7:0](Frame length) */
Kojto 122:f9eeca106725 10718 #define SAI_xFRCR_FRL_0 (0x01U << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10719 #define SAI_xFRCR_FRL_1 (0x02U << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10720 #define SAI_xFRCR_FRL_2 (0x04U << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 10721 #define SAI_xFRCR_FRL_3 (0x08U << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 10722 #define SAI_xFRCR_FRL_4 (0x10U << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 10723 #define SAI_xFRCR_FRL_5 (0x20U << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 10724 #define SAI_xFRCR_FRL_6 (0x40U << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 10725 #define SAI_xFRCR_FRL_7 (0x80U << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 10726
Kojto 122:f9eeca106725 10727 #define SAI_xFRCR_FSALL_Pos (8U)
Kojto 122:f9eeca106725 10728 #define SAI_xFRCR_FSALL_Msk (0x7FU << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
Kojto 122:f9eeca106725 10729 #define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[6:0] (Frame synchronization active level length) */
Kojto 122:f9eeca106725 10730 #define SAI_xFRCR_FSALL_0 (0x01U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 10731 #define SAI_xFRCR_FSALL_1 (0x02U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 10732 #define SAI_xFRCR_FSALL_2 (0x04U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 10733 #define SAI_xFRCR_FSALL_3 (0x08U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 10734 #define SAI_xFRCR_FSALL_4 (0x10U << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 10735 #define SAI_xFRCR_FSALL_5 (0x20U << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 10736 #define SAI_xFRCR_FSALL_6 (0x40U << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 10737
Kojto 122:f9eeca106725 10738 #define SAI_xFRCR_FSDEF_Pos (16U)
Kojto 122:f9eeca106725 10739 #define SAI_xFRCR_FSDEF_Msk (0x1U << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 10740 #define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */
Kojto 122:f9eeca106725 10741 #define SAI_xFRCR_FSPOL_Pos (17U)
Kojto 122:f9eeca106725 10742 #define SAI_xFRCR_FSPOL_Msk (0x1U << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 10743 #define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
Kojto 122:f9eeca106725 10744 #define SAI_xFRCR_FSOFF_Pos (18U)
Kojto 122:f9eeca106725 10745 #define SAI_xFRCR_FSOFF_Msk (0x1U << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 10746 #define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
Kojto 122:f9eeca106725 10747
Kojto 122:f9eeca106725 10748 /****************** Bit definition for SAI_xSLOTR register *******************/
Kojto 122:f9eeca106725 10749 #define SAI_xSLOTR_FBOFF_Pos (0U)
Kojto 122:f9eeca106725 10750 #define SAI_xSLOTR_FBOFF_Msk (0x1FU << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
Kojto 122:f9eeca106725 10751 #define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
Kojto 122:f9eeca106725 10752 #define SAI_xSLOTR_FBOFF_0 (0x01U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10753 #define SAI_xSLOTR_FBOFF_1 (0x02U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10754 #define SAI_xSLOTR_FBOFF_2 (0x04U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 10755 #define SAI_xSLOTR_FBOFF_3 (0x08U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 10756 #define SAI_xSLOTR_FBOFF_4 (0x10U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 10757
Kojto 122:f9eeca106725 10758 #define SAI_xSLOTR_SLOTSZ_Pos (6U)
Kojto 122:f9eeca106725 10759 #define SAI_xSLOTR_SLOTSZ_Msk (0x3U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
Kojto 122:f9eeca106725 10760 #define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
Kojto 122:f9eeca106725 10761 #define SAI_xSLOTR_SLOTSZ_0 (0x1U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 10762 #define SAI_xSLOTR_SLOTSZ_1 (0x2U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 10763
Kojto 122:f9eeca106725 10764 #define SAI_xSLOTR_NBSLOT_Pos (8U)
Kojto 122:f9eeca106725 10765 #define SAI_xSLOTR_NBSLOT_Msk (0xFU << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 10766 #define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
Kojto 122:f9eeca106725 10767 #define SAI_xSLOTR_NBSLOT_0 (0x1U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 10768 #define SAI_xSLOTR_NBSLOT_1 (0x2U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 10769 #define SAI_xSLOTR_NBSLOT_2 (0x4U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 10770 #define SAI_xSLOTR_NBSLOT_3 (0x8U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 10771
Kojto 122:f9eeca106725 10772 #define SAI_xSLOTR_SLOTEN_Pos (16U)
Kojto 122:f9eeca106725 10773 #define SAI_xSLOTR_SLOTEN_Msk (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
Kojto 122:f9eeca106725 10774 #define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
Kojto 122:f9eeca106725 10775
Kojto 122:f9eeca106725 10776 /******************* Bit definition for SAI_xIMR register *******************/
Kojto 122:f9eeca106725 10777 #define SAI_xIMR_OVRUDRIE_Pos (0U)
Kojto 122:f9eeca106725 10778 #define SAI_xIMR_OVRUDRIE_Msk (0x1U << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10779 #define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
Kojto 122:f9eeca106725 10780 #define SAI_xIMR_MUTEDETIE_Pos (1U)
Kojto 122:f9eeca106725 10781 #define SAI_xIMR_MUTEDETIE_Msk (0x1U << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10782 #define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
Kojto 122:f9eeca106725 10783 #define SAI_xIMR_WCKCFGIE_Pos (2U)
Kojto 122:f9eeca106725 10784 #define SAI_xIMR_WCKCFGIE_Msk (0x1U << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 10785 #define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
Kojto 122:f9eeca106725 10786 #define SAI_xIMR_FREQIE_Pos (3U)
Kojto 122:f9eeca106725 10787 #define SAI_xIMR_FREQIE_Msk (0x1U << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 10788 #define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
Kojto 122:f9eeca106725 10789 #define SAI_xIMR_CNRDYIE_Pos (4U)
Kojto 122:f9eeca106725 10790 #define SAI_xIMR_CNRDYIE_Msk (0x1U << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 10791 #define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
Kojto 122:f9eeca106725 10792 #define SAI_xIMR_AFSDETIE_Pos (5U)
Kojto 122:f9eeca106725 10793 #define SAI_xIMR_AFSDETIE_Msk (0x1U << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 10794 #define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
Kojto 122:f9eeca106725 10795 #define SAI_xIMR_LFSDETIE_Pos (6U)
Kojto 122:f9eeca106725 10796 #define SAI_xIMR_LFSDETIE_Msk (0x1U << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 10797 #define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
Kojto 122:f9eeca106725 10798
Kojto 122:f9eeca106725 10799 /******************** Bit definition for SAI_xSR register *******************/
Kojto 122:f9eeca106725 10800 #define SAI_xSR_OVRUDR_Pos (0U)
Kojto 122:f9eeca106725 10801 #define SAI_xSR_OVRUDR_Msk (0x1U << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10802 #define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
Kojto 122:f9eeca106725 10803 #define SAI_xSR_MUTEDET_Pos (1U)
Kojto 122:f9eeca106725 10804 #define SAI_xSR_MUTEDET_Msk (0x1U << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10805 #define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
Kojto 122:f9eeca106725 10806 #define SAI_xSR_WCKCFG_Pos (2U)
Kojto 122:f9eeca106725 10807 #define SAI_xSR_WCKCFG_Msk (0x1U << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 10808 #define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
Kojto 122:f9eeca106725 10809 #define SAI_xSR_FREQ_Pos (3U)
Kojto 122:f9eeca106725 10810 #define SAI_xSR_FREQ_Msk (0x1U << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 10811 #define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
Kojto 122:f9eeca106725 10812 #define SAI_xSR_CNRDY_Pos (4U)
Kojto 122:f9eeca106725 10813 #define SAI_xSR_CNRDY_Msk (0x1U << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 10814 #define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
Kojto 122:f9eeca106725 10815 #define SAI_xSR_AFSDET_Pos (5U)
Kojto 122:f9eeca106725 10816 #define SAI_xSR_AFSDET_Msk (0x1U << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 10817 #define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
Kojto 122:f9eeca106725 10818 #define SAI_xSR_LFSDET_Pos (6U)
Kojto 122:f9eeca106725 10819 #define SAI_xSR_LFSDET_Msk (0x1U << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 10820 #define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
Kojto 122:f9eeca106725 10821
Kojto 122:f9eeca106725 10822 #define SAI_xSR_FLVL_Pos (16U)
Kojto 122:f9eeca106725 10823 #define SAI_xSR_FLVL_Msk (0x7U << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
Kojto 122:f9eeca106725 10824 #define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
Kojto 122:f9eeca106725 10825 #define SAI_xSR_FLVL_0 (0x1U << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 10826 #define SAI_xSR_FLVL_1 (0x2U << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 10827 #define SAI_xSR_FLVL_2 (0x4U << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 10828
Kojto 122:f9eeca106725 10829 /****************** Bit definition for SAI_xCLRFR register ******************/
Kojto 122:f9eeca106725 10830 #define SAI_xCLRFR_COVRUDR_Pos (0U)
Kojto 122:f9eeca106725 10831 #define SAI_xCLRFR_COVRUDR_Msk (0x1U << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10832 #define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
Kojto 122:f9eeca106725 10833 #define SAI_xCLRFR_CMUTEDET_Pos (1U)
Kojto 122:f9eeca106725 10834 #define SAI_xCLRFR_CMUTEDET_Msk (0x1U << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10835 #define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
Kojto 122:f9eeca106725 10836 #define SAI_xCLRFR_CWCKCFG_Pos (2U)
Kojto 122:f9eeca106725 10837 #define SAI_xCLRFR_CWCKCFG_Msk (0x1U << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 10838 #define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
Kojto 122:f9eeca106725 10839 #define SAI_xCLRFR_CFREQ_Pos (3U)
Kojto 122:f9eeca106725 10840 #define SAI_xCLRFR_CFREQ_Msk (0x1U << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 10841 #define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
Kojto 122:f9eeca106725 10842 #define SAI_xCLRFR_CCNRDY_Pos (4U)
Kojto 122:f9eeca106725 10843 #define SAI_xCLRFR_CCNRDY_Msk (0x1U << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 10844 #define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
Kojto 122:f9eeca106725 10845 #define SAI_xCLRFR_CAFSDET_Pos (5U)
Kojto 122:f9eeca106725 10846 #define SAI_xCLRFR_CAFSDET_Msk (0x1U << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 10847 #define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
Kojto 122:f9eeca106725 10848 #define SAI_xCLRFR_CLFSDET_Pos (6U)
Kojto 122:f9eeca106725 10849 #define SAI_xCLRFR_CLFSDET_Msk (0x1U << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 10850 #define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
Kojto 122:f9eeca106725 10851
Kojto 122:f9eeca106725 10852 /****************** Bit definition for SAI_xDR register ******************/
Kojto 122:f9eeca106725 10853 #define SAI_xDR_DATA_Pos (0U)
Kojto 122:f9eeca106725 10854 #define SAI_xDR_DATA_Msk (0xFFFFFFFFU << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 10855 #define SAI_xDR_DATA SAI_xDR_DATA_Msk
Kojto 122:f9eeca106725 10856
Kojto 122:f9eeca106725 10857 /******************************************************************************/
Kojto 122:f9eeca106725 10858 /* */
Kojto 122:f9eeca106725 10859 /* Serial Peripheral Interface (SPI) */
Kojto 122:f9eeca106725 10860 /* */
Kojto 122:f9eeca106725 10861 /******************************************************************************/
Kojto 122:f9eeca106725 10862 /******************* Bit definition for SPI_CR1 register ********************/
Kojto 122:f9eeca106725 10863 #define SPI_CR1_CPHA_Pos (0U)
Kojto 122:f9eeca106725 10864 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10865 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
Kojto 122:f9eeca106725 10866 #define SPI_CR1_CPOL_Pos (1U)
Kojto 122:f9eeca106725 10867 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10868 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
Kojto 122:f9eeca106725 10869 #define SPI_CR1_MSTR_Pos (2U)
Kojto 122:f9eeca106725 10870 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 10871 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
Kojto 122:f9eeca106725 10872
Kojto 122:f9eeca106725 10873 #define SPI_CR1_BR_Pos (3U)
Kojto 122:f9eeca106725 10874 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
Kojto 122:f9eeca106725 10875 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
Kojto 122:f9eeca106725 10876 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 10877 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 10878 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 10879
Kojto 122:f9eeca106725 10880 #define SPI_CR1_SPE_Pos (6U)
Kojto 122:f9eeca106725 10881 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 10882 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
Kojto 122:f9eeca106725 10883 #define SPI_CR1_LSBFIRST_Pos (7U)
Kojto 122:f9eeca106725 10884 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 10885 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
Kojto 122:f9eeca106725 10886 #define SPI_CR1_SSI_Pos (8U)
Kojto 122:f9eeca106725 10887 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 10888 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
Kojto 122:f9eeca106725 10889 #define SPI_CR1_SSM_Pos (9U)
Kojto 122:f9eeca106725 10890 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 10891 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
Kojto 122:f9eeca106725 10892 #define SPI_CR1_RXONLY_Pos (10U)
Kojto 122:f9eeca106725 10893 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 10894 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
Kojto 122:f9eeca106725 10895 #define SPI_CR1_CRCL_Pos (11U)
Kojto 122:f9eeca106725 10896 #define SPI_CR1_CRCL_Msk (0x1U << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 10897 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
Kojto 122:f9eeca106725 10898 #define SPI_CR1_CRCNEXT_Pos (12U)
Kojto 122:f9eeca106725 10899 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 10900 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
Kojto 122:f9eeca106725 10901 #define SPI_CR1_CRCEN_Pos (13U)
Kojto 122:f9eeca106725 10902 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 10903 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
Kojto 122:f9eeca106725 10904 #define SPI_CR1_BIDIOE_Pos (14U)
Kojto 122:f9eeca106725 10905 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 10906 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
Kojto 122:f9eeca106725 10907 #define SPI_CR1_BIDIMODE_Pos (15U)
Kojto 122:f9eeca106725 10908 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 10909 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
Kojto 122:f9eeca106725 10910
Kojto 122:f9eeca106725 10911 /******************* Bit definition for SPI_CR2 register ********************/
Kojto 122:f9eeca106725 10912 #define SPI_CR2_RXDMAEN_Pos (0U)
Kojto 122:f9eeca106725 10913 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10914 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
Kojto 122:f9eeca106725 10915 #define SPI_CR2_TXDMAEN_Pos (1U)
Kojto 122:f9eeca106725 10916 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10917 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
Kojto 122:f9eeca106725 10918 #define SPI_CR2_SSOE_Pos (2U)
Kojto 122:f9eeca106725 10919 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 10920 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
Kojto 122:f9eeca106725 10921 #define SPI_CR2_NSSP_Pos (3U)
Kojto 122:f9eeca106725 10922 #define SPI_CR2_NSSP_Msk (0x1U << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 10923 #define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */
Kojto 122:f9eeca106725 10924 #define SPI_CR2_FRF_Pos (4U)
Kojto 122:f9eeca106725 10925 #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 10926 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
Kojto 122:f9eeca106725 10927 #define SPI_CR2_ERRIE_Pos (5U)
Kojto 122:f9eeca106725 10928 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 10929 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
Kojto 122:f9eeca106725 10930 #define SPI_CR2_RXNEIE_Pos (6U)
Kojto 122:f9eeca106725 10931 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 10932 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
Kojto 122:f9eeca106725 10933 #define SPI_CR2_TXEIE_Pos (7U)
Kojto 122:f9eeca106725 10934 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 10935 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
Kojto 122:f9eeca106725 10936 #define SPI_CR2_DS_Pos (8U)
Kojto 122:f9eeca106725 10937 #define SPI_CR2_DS_Msk (0xFU << SPI_CR2_DS_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 10938 #define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */
Kojto 122:f9eeca106725 10939 #define SPI_CR2_DS_0 (0x1U << SPI_CR2_DS_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 10940 #define SPI_CR2_DS_1 (0x2U << SPI_CR2_DS_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 10941 #define SPI_CR2_DS_2 (0x4U << SPI_CR2_DS_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 10942 #define SPI_CR2_DS_3 (0x8U << SPI_CR2_DS_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 10943 #define SPI_CR2_FRXTH_Pos (12U)
Kojto 122:f9eeca106725 10944 #define SPI_CR2_FRXTH_Msk (0x1U << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 10945 #define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */
Kojto 122:f9eeca106725 10946 #define SPI_CR2_LDMARX_Pos (13U)
Kojto 122:f9eeca106725 10947 #define SPI_CR2_LDMARX_Msk (0x1U << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 10948 #define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */
Kojto 122:f9eeca106725 10949 #define SPI_CR2_LDMATX_Pos (14U)
Kojto 122:f9eeca106725 10950 #define SPI_CR2_LDMATX_Msk (0x1U << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 10951 #define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */
Kojto 122:f9eeca106725 10952
Kojto 122:f9eeca106725 10953 /******************** Bit definition for SPI_SR register ********************/
Kojto 122:f9eeca106725 10954 #define SPI_SR_RXNE_Pos (0U)
Kojto 122:f9eeca106725 10955 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 10956 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
Kojto 122:f9eeca106725 10957 #define SPI_SR_TXE_Pos (1U)
Kojto 122:f9eeca106725 10958 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 10959 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
Kojto 122:f9eeca106725 10960 #define SPI_SR_CHSIDE_Pos (2U)
Kojto 122:f9eeca106725 10961 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 10962 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
Kojto 122:f9eeca106725 10963 #define SPI_SR_UDR_Pos (3U)
Kojto 122:f9eeca106725 10964 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 10965 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
Kojto 122:f9eeca106725 10966 #define SPI_SR_CRCERR_Pos (4U)
Kojto 122:f9eeca106725 10967 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 10968 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
Kojto 122:f9eeca106725 10969 #define SPI_SR_MODF_Pos (5U)
Kojto 122:f9eeca106725 10970 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 10971 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
Kojto 122:f9eeca106725 10972 #define SPI_SR_OVR_Pos (6U)
Kojto 122:f9eeca106725 10973 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 10974 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
Kojto 122:f9eeca106725 10975 #define SPI_SR_BSY_Pos (7U)
Kojto 122:f9eeca106725 10976 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 10977 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
Kojto 122:f9eeca106725 10978 #define SPI_SR_FRE_Pos (8U)
Kojto 122:f9eeca106725 10979 #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 10980 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
Kojto 122:f9eeca106725 10981 #define SPI_SR_FRLVL_Pos (9U)
Kojto 122:f9eeca106725 10982 #define SPI_SR_FRLVL_Msk (0x3U << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */
Kojto 122:f9eeca106725 10983 #define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */
Kojto 122:f9eeca106725 10984 #define SPI_SR_FRLVL_0 (0x1U << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 10985 #define SPI_SR_FRLVL_1 (0x2U << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 10986 #define SPI_SR_FTLVL_Pos (11U)
Kojto 122:f9eeca106725 10987 #define SPI_SR_FTLVL_Msk (0x3U << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */
Kojto 122:f9eeca106725 10988 #define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */
Kojto 122:f9eeca106725 10989 #define SPI_SR_FTLVL_0 (0x1U << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 10990 #define SPI_SR_FTLVL_1 (0x2U << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 10991
Kojto 122:f9eeca106725 10992 /******************** Bit definition for SPI_DR register ********************/
Kojto 122:f9eeca106725 10993 #define SPI_DR_DR_Pos (0U)
Kojto 122:f9eeca106725 10994 #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 10995 #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
Kojto 122:f9eeca106725 10996
Kojto 122:f9eeca106725 10997 /******************* Bit definition for SPI_CRCPR register ******************/
Kojto 122:f9eeca106725 10998 #define SPI_CRCPR_CRCPOLY_Pos (0U)
Kojto 122:f9eeca106725 10999 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 11000 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
Kojto 122:f9eeca106725 11001
Kojto 122:f9eeca106725 11002 /****************** Bit definition for SPI_RXCRCR register ******************/
Kojto 122:f9eeca106725 11003 #define SPI_RXCRCR_RXCRC_Pos (0U)
Kojto 122:f9eeca106725 11004 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 11005 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
Kojto 122:f9eeca106725 11006
Kojto 122:f9eeca106725 11007 /****************** Bit definition for SPI_TXCRCR register ******************/
Kojto 122:f9eeca106725 11008 #define SPI_TXCRCR_TXCRC_Pos (0U)
Kojto 122:f9eeca106725 11009 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 11010 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
Kojto 122:f9eeca106725 11011
Kojto 122:f9eeca106725 11012 /******************************************************************************/
Kojto 122:f9eeca106725 11013 /* */
Kojto 122:f9eeca106725 11014 /* QUADSPI */
Kojto 122:f9eeca106725 11015 /* */
Kojto 122:f9eeca106725 11016 /******************************************************************************/
Kojto 122:f9eeca106725 11017 /***************** Bit definition for QUADSPI_CR register *******************/
Kojto 122:f9eeca106725 11018 #define QUADSPI_CR_EN_Pos (0U)
Kojto 122:f9eeca106725 11019 #define QUADSPI_CR_EN_Msk (0x1U << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 11020 #define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */
Kojto 122:f9eeca106725 11021 #define QUADSPI_CR_ABORT_Pos (1U)
Kojto 122:f9eeca106725 11022 #define QUADSPI_CR_ABORT_Msk (0x1U << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 11023 #define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
Kojto 122:f9eeca106725 11024 #define QUADSPI_CR_DMAEN_Pos (2U)
Kojto 122:f9eeca106725 11025 #define QUADSPI_CR_DMAEN_Msk (0x1U << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 11026 #define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
Kojto 122:f9eeca106725 11027 #define QUADSPI_CR_TCEN_Pos (3U)
Kojto 122:f9eeca106725 11028 #define QUADSPI_CR_TCEN_Msk (0x1U << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 11029 #define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
Kojto 122:f9eeca106725 11030 #define QUADSPI_CR_SSHIFT_Pos (4U)
Kojto 122:f9eeca106725 11031 #define QUADSPI_CR_SSHIFT_Msk (0x1U << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 11032 #define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< Sample Shift */
Kojto 122:f9eeca106725 11033 #define QUADSPI_CR_DFM_Pos (6U)
Kojto 122:f9eeca106725 11034 #define QUADSPI_CR_DFM_Msk (0x1U << QUADSPI_CR_DFM_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 11035 #define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk /*!< Dual-flash mode */
Kojto 122:f9eeca106725 11036 #define QUADSPI_CR_FSEL_Pos (7U)
Kojto 122:f9eeca106725 11037 #define QUADSPI_CR_FSEL_Msk (0x1U << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 11038 #define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash memory selection */
Kojto 122:f9eeca106725 11039 #define QUADSPI_CR_FTHRES_Pos (8U)
Kojto 122:f9eeca106725 11040 #define QUADSPI_CR_FTHRES_Msk (0xFU << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 11041 #define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
Kojto 122:f9eeca106725 11042 #define QUADSPI_CR_TEIE_Pos (16U)
Kojto 122:f9eeca106725 11043 #define QUADSPI_CR_TEIE_Msk (0x1U << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 11044 #define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
Kojto 122:f9eeca106725 11045 #define QUADSPI_CR_TCIE_Pos (17U)
Kojto 122:f9eeca106725 11046 #define QUADSPI_CR_TCIE_Msk (0x1U << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 11047 #define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
Kojto 122:f9eeca106725 11048 #define QUADSPI_CR_FTIE_Pos (18U)
Kojto 122:f9eeca106725 11049 #define QUADSPI_CR_FTIE_Msk (0x1U << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 11050 #define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
Kojto 122:f9eeca106725 11051 #define QUADSPI_CR_SMIE_Pos (19U)
Kojto 122:f9eeca106725 11052 #define QUADSPI_CR_SMIE_Msk (0x1U << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 11053 #define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
Kojto 122:f9eeca106725 11054 #define QUADSPI_CR_TOIE_Pos (20U)
Kojto 122:f9eeca106725 11055 #define QUADSPI_CR_TOIE_Msk (0x1U << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 11056 #define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
Kojto 122:f9eeca106725 11057 #define QUADSPI_CR_APMS_Pos (22U)
Kojto 122:f9eeca106725 11058 #define QUADSPI_CR_APMS_Msk (0x1U << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 11059 #define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Automatic Polling Mode Stop */
Kojto 122:f9eeca106725 11060 #define QUADSPI_CR_PMM_Pos (23U)
Kojto 122:f9eeca106725 11061 #define QUADSPI_CR_PMM_Msk (0x1U << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 11062 #define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */
Kojto 122:f9eeca106725 11063 #define QUADSPI_CR_PRESCALER_Pos (24U)
Kojto 122:f9eeca106725 11064 #define QUADSPI_CR_PRESCALER_Msk (0xFFU << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 11065 #define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */
Kojto 122:f9eeca106725 11066
Kojto 122:f9eeca106725 11067 /***************** Bit definition for QUADSPI_DCR register ******************/
Kojto 122:f9eeca106725 11068 #define QUADSPI_DCR_CKMODE_Pos (0U)
Kojto 122:f9eeca106725 11069 #define QUADSPI_DCR_CKMODE_Msk (0x1U << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 11070 #define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */
Kojto 122:f9eeca106725 11071 #define QUADSPI_DCR_CSHT_Pos (8U)
Kojto 122:f9eeca106725 11072 #define QUADSPI_DCR_CSHT_Msk (0x7U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */
Kojto 122:f9eeca106725 11073 #define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */
Kojto 122:f9eeca106725 11074 #define QUADSPI_DCR_CSHT_0 (0x1U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 11075 #define QUADSPI_DCR_CSHT_1 (0x2U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 11076 #define QUADSPI_DCR_CSHT_2 (0x4U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 11077 #define QUADSPI_DCR_FSIZE_Pos (16U)
Kojto 122:f9eeca106725 11078 #define QUADSPI_DCR_FSIZE_Msk (0x1FU << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */
Kojto 122:f9eeca106725 11079 #define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */
Kojto 122:f9eeca106725 11080
Kojto 122:f9eeca106725 11081 /****************** Bit definition for QUADSPI_SR register *******************/
Kojto 122:f9eeca106725 11082 #define QUADSPI_SR_TEF_Pos (0U)
Kojto 122:f9eeca106725 11083 #define QUADSPI_SR_TEF_Msk (0x1U << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 11084 #define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */
Kojto 122:f9eeca106725 11085 #define QUADSPI_SR_TCF_Pos (1U)
Kojto 122:f9eeca106725 11086 #define QUADSPI_SR_TCF_Msk (0x1U << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 11087 #define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
Kojto 122:f9eeca106725 11088 #define QUADSPI_SR_FTF_Pos (2U)
Kojto 122:f9eeca106725 11089 #define QUADSPI_SR_FTF_Msk (0x1U << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 11090 #define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */
Kojto 122:f9eeca106725 11091 #define QUADSPI_SR_SMF_Pos (3U)
Kojto 122:f9eeca106725 11092 #define QUADSPI_SR_SMF_Msk (0x1U << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 11093 #define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */
Kojto 122:f9eeca106725 11094 #define QUADSPI_SR_TOF_Pos (4U)
Kojto 122:f9eeca106725 11095 #define QUADSPI_SR_TOF_Msk (0x1U << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 11096 #define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */
Kojto 122:f9eeca106725 11097 #define QUADSPI_SR_BUSY_Pos (5U)
Kojto 122:f9eeca106725 11098 #define QUADSPI_SR_BUSY_Msk (0x1U << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 11099 #define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */
Kojto 122:f9eeca106725 11100 #define QUADSPI_SR_FLEVEL_Pos (8U)
Kojto 122:f9eeca106725 11101 #define QUADSPI_SR_FLEVEL_Msk (0x1FU << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001F00 */
Kojto 122:f9eeca106725 11102 #define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */
Kojto 122:f9eeca106725 11103
Kojto 122:f9eeca106725 11104 /****************** Bit definition for QUADSPI_FCR register ******************/
Kojto 122:f9eeca106725 11105 #define QUADSPI_FCR_CTEF_Pos (0U)
Kojto 122:f9eeca106725 11106 #define QUADSPI_FCR_CTEF_Msk (0x1U << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 11107 #define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
Kojto 122:f9eeca106725 11108 #define QUADSPI_FCR_CTCF_Pos (1U)
Kojto 122:f9eeca106725 11109 #define QUADSPI_FCR_CTCF_Msk (0x1U << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 11110 #define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
Kojto 122:f9eeca106725 11111 #define QUADSPI_FCR_CSMF_Pos (3U)
Kojto 122:f9eeca106725 11112 #define QUADSPI_FCR_CSMF_Msk (0x1U << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 11113 #define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
Kojto 122:f9eeca106725 11114 #define QUADSPI_FCR_CTOF_Pos (4U)
Kojto 122:f9eeca106725 11115 #define QUADSPI_FCR_CTOF_Msk (0x1U << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 11116 #define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
Kojto 122:f9eeca106725 11117
Kojto 122:f9eeca106725 11118 /****************** Bit definition for QUADSPI_DLR register ******************/
Kojto 122:f9eeca106725 11119 #define QUADSPI_DLR_DL_Pos (0U)
Kojto 122:f9eeca106725 11120 #define QUADSPI_DLR_DL_Msk (0xFFFFFFFFU << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 11121 #define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */
Kojto 122:f9eeca106725 11122
Kojto 122:f9eeca106725 11123 /****************** Bit definition for QUADSPI_CCR register ******************/
Kojto 122:f9eeca106725 11124 #define QUADSPI_CCR_INSTRUCTION_Pos (0U)
Kojto 122:f9eeca106725 11125 #define QUADSPI_CCR_INSTRUCTION_Msk (0xFFU << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 11126 #define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */
Kojto 122:f9eeca106725 11127 #define QUADSPI_CCR_IMODE_Pos (8U)
Kojto 122:f9eeca106725 11128 #define QUADSPI_CCR_IMODE_Msk (0x3U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 11129 #define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */
Kojto 122:f9eeca106725 11130 #define QUADSPI_CCR_IMODE_0 (0x1U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 11131 #define QUADSPI_CCR_IMODE_1 (0x2U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 11132 #define QUADSPI_CCR_ADMODE_Pos (10U)
Kojto 122:f9eeca106725 11133 #define QUADSPI_CCR_ADMODE_Msk (0x3U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */
Kojto 122:f9eeca106725 11134 #define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */
Kojto 122:f9eeca106725 11135 #define QUADSPI_CCR_ADMODE_0 (0x1U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 11136 #define QUADSPI_CCR_ADMODE_1 (0x2U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 11137 #define QUADSPI_CCR_ADSIZE_Pos (12U)
Kojto 122:f9eeca106725 11138 #define QUADSPI_CCR_ADSIZE_Msk (0x3U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
Kojto 122:f9eeca106725 11139 #define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */
Kojto 122:f9eeca106725 11140 #define QUADSPI_CCR_ADSIZE_0 (0x1U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 11141 #define QUADSPI_CCR_ADSIZE_1 (0x2U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 11142 #define QUADSPI_CCR_ABMODE_Pos (14U)
Kojto 122:f9eeca106725 11143 #define QUADSPI_CCR_ABMODE_Msk (0x3U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */
Kojto 122:f9eeca106725 11144 #define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */
Kojto 122:f9eeca106725 11145 #define QUADSPI_CCR_ABMODE_0 (0x1U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 11146 #define QUADSPI_CCR_ABMODE_1 (0x2U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 11147 #define QUADSPI_CCR_ABSIZE_Pos (16U)
Kojto 122:f9eeca106725 11148 #define QUADSPI_CCR_ABSIZE_Msk (0x3U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */
Kojto 122:f9eeca106725 11149 #define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */
Kojto 122:f9eeca106725 11150 #define QUADSPI_CCR_ABSIZE_0 (0x1U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 11151 #define QUADSPI_CCR_ABSIZE_1 (0x2U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 11152 #define QUADSPI_CCR_DCYC_Pos (18U)
Kojto 122:f9eeca106725 11153 #define QUADSPI_CCR_DCYC_Msk (0x1FU << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
Kojto 122:f9eeca106725 11154 #define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */
Kojto 122:f9eeca106725 11155 #define QUADSPI_CCR_DMODE_Pos (24U)
Kojto 122:f9eeca106725 11156 #define QUADSPI_CCR_DMODE_Msk (0x3U << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */
Kojto 122:f9eeca106725 11157 #define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */
Kojto 122:f9eeca106725 11158 #define QUADSPI_CCR_DMODE_0 (0x1U << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 11159 #define QUADSPI_CCR_DMODE_1 (0x2U << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 11160 #define QUADSPI_CCR_FMODE_Pos (26U)
Kojto 122:f9eeca106725 11161 #define QUADSPI_CCR_FMODE_Msk (0x3U << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */
Kojto 122:f9eeca106725 11162 #define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */
Kojto 122:f9eeca106725 11163 #define QUADSPI_CCR_FMODE_0 (0x1U << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 11164 #define QUADSPI_CCR_FMODE_1 (0x2U << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 11165 #define QUADSPI_CCR_SIOO_Pos (28U)
Kojto 122:f9eeca106725 11166 #define QUADSPI_CCR_SIOO_Msk (0x1U << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 11167 #define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */
Kojto 122:f9eeca106725 11168 #define QUADSPI_CCR_DHHC_Pos (30U)
Kojto 122:f9eeca106725 11169 #define QUADSPI_CCR_DHHC_Msk (0x1U << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 11170 #define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: DDR hold */
Kojto 122:f9eeca106725 11171 #define QUADSPI_CCR_DDRM_Pos (31U)
Kojto 122:f9eeca106725 11172 #define QUADSPI_CCR_DDRM_Msk (0x1U << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 11173 #define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */
Kojto 122:f9eeca106725 11174
Kojto 122:f9eeca106725 11175 /****************** Bit definition for QUADSPI_AR register *******************/
Kojto 122:f9eeca106725 11176 #define QUADSPI_AR_ADDRESS_Pos (0U)
Kojto 122:f9eeca106725 11177 #define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFU << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 11178 #define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */
Kojto 122:f9eeca106725 11179
Kojto 122:f9eeca106725 11180 /****************** Bit definition for QUADSPI_ABR register ******************/
Kojto 122:f9eeca106725 11181 #define QUADSPI_ABR_ALTERNATE_Pos (0U)
Kojto 122:f9eeca106725 11182 #define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFU << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 11183 #define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */
Kojto 122:f9eeca106725 11184
Kojto 122:f9eeca106725 11185 /****************** Bit definition for QUADSPI_DR register *******************/
Kojto 122:f9eeca106725 11186 #define QUADSPI_DR_DATA_Pos (0U)
Kojto 122:f9eeca106725 11187 #define QUADSPI_DR_DATA_Msk (0xFFFFFFFFU << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 11188 #define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */
Kojto 122:f9eeca106725 11189
Kojto 122:f9eeca106725 11190 /****************** Bit definition for QUADSPI_PSMKR register ****************/
Kojto 122:f9eeca106725 11191 #define QUADSPI_PSMKR_MASK_Pos (0U)
Kojto 122:f9eeca106725 11192 #define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFU << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 11193 #define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */
Kojto 122:f9eeca106725 11194
Kojto 122:f9eeca106725 11195 /****************** Bit definition for QUADSPI_PSMAR register ****************/
Kojto 122:f9eeca106725 11196 #define QUADSPI_PSMAR_MATCH_Pos (0U)
Kojto 122:f9eeca106725 11197 #define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFU << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 11198 #define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */
Kojto 122:f9eeca106725 11199
Kojto 122:f9eeca106725 11200 /****************** Bit definition for QUADSPI_PIR register *****************/
Kojto 122:f9eeca106725 11201 #define QUADSPI_PIR_INTERVAL_Pos (0U)
Kojto 122:f9eeca106725 11202 #define QUADSPI_PIR_INTERVAL_Msk (0xFFFFU << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 11203 #define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */
Kojto 122:f9eeca106725 11204
Kojto 122:f9eeca106725 11205 /****************** Bit definition for QUADSPI_LPTR register *****************/
Kojto 122:f9eeca106725 11206 #define QUADSPI_LPTR_TIMEOUT_Pos (0U)
Kojto 122:f9eeca106725 11207 #define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFU << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 11208 #define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */
Kojto 122:f9eeca106725 11209
Kojto 122:f9eeca106725 11210 /******************************************************************************/
Kojto 122:f9eeca106725 11211 /* */
Kojto 122:f9eeca106725 11212 /* SYSCFG */
Kojto 122:f9eeca106725 11213 /* */
Kojto 122:f9eeca106725 11214 /******************************************************************************/
Kojto 122:f9eeca106725 11215 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
Kojto 122:f9eeca106725 11216 #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
Kojto 122:f9eeca106725 11217 #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */
Kojto 122:f9eeca106725 11218 #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
Kojto 122:f9eeca106725 11219 #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 11220 #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 11221 #define SYSCFG_MEMRMP_MEM_MODE_2 (0x4U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 11222
Kojto 122:f9eeca106725 11223 /****************** Bit definition for SYSCFG_CFGR1 register ******************/
Kojto 122:f9eeca106725 11224 #define SYSCFG_CFGR1_FWDIS_Pos (0U)
Kojto 122:f9eeca106725 11225 #define SYSCFG_CFGR1_FWDIS_Msk (0x1U << SYSCFG_CFGR1_FWDIS_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 11226 #define SYSCFG_CFGR1_FWDIS SYSCFG_CFGR1_FWDIS_Msk /*!< FIREWALL access enable*/
Kojto 122:f9eeca106725 11227 #define SYSCFG_CFGR1_BOOSTEN_Pos (8U)
Kojto 122:f9eeca106725 11228 #define SYSCFG_CFGR1_BOOSTEN_Msk (0x1U << SYSCFG_CFGR1_BOOSTEN_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 11229 #define SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN_Msk /*!< I/O analog switch voltage booster enable */
Kojto 122:f9eeca106725 11230 #define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U)
Kojto 122:f9eeca106725 11231 #define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 11232 #define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
Kojto 122:f9eeca106725 11233 #define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U)
Kojto 122:f9eeca106725 11234 #define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB7_FMP_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 11235 #define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
Kojto 122:f9eeca106725 11236 #define SYSCFG_CFGR1_I2C1_FMP_Pos (20U)
Kojto 122:f9eeca106725 11237 #define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C1_FMP_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 11238 #define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
Kojto 122:f9eeca106725 11239 #define SYSCFG_CFGR1_I2C3_FMP_Pos (22U)
Kojto 122:f9eeca106725 11240 #define SYSCFG_CFGR1_I2C3_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C3_FMP_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 11241 #define SYSCFG_CFGR1_I2C3_FMP SYSCFG_CFGR1_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */
Kojto 122:f9eeca106725 11242 #define SYSCFG_CFGR1_FPU_IE_0 (0x04000000U) /*!< Invalid operation Interrupt enable */
Kojto 122:f9eeca106725 11243 #define SYSCFG_CFGR1_FPU_IE_1 (0x08000000U) /*!< Divide-by-zero Interrupt enable */
Kojto 122:f9eeca106725 11244 #define SYSCFG_CFGR1_FPU_IE_2 (0x10000000U) /*!< Underflow Interrupt enable */
Kojto 122:f9eeca106725 11245 #define SYSCFG_CFGR1_FPU_IE_3 (0x20000000U) /*!< Overflow Interrupt enable */
Kojto 122:f9eeca106725 11246 #define SYSCFG_CFGR1_FPU_IE_4 (0x40000000U) /*!< Input denormal Interrupt enable */
Kojto 122:f9eeca106725 11247 #define SYSCFG_CFGR1_FPU_IE_5 (0x80000000U) /*!< Inexact Interrupt enable (interrupt disabled at reset) */
Kojto 122:f9eeca106725 11248
Kojto 122:f9eeca106725 11249 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
Kojto 122:f9eeca106725 11250 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
Kojto 122:f9eeca106725 11251 #define SYSCFG_EXTICR1_EXTI0_Msk (0x7U << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x00000007 */
Kojto 122:f9eeca106725 11252 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
Kojto 122:f9eeca106725 11253 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
Kojto 122:f9eeca106725 11254 #define SYSCFG_EXTICR1_EXTI1_Msk (0x7U << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x00000070 */
Kojto 122:f9eeca106725 11255 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
Kojto 122:f9eeca106725 11256 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
Kojto 122:f9eeca106725 11257 #define SYSCFG_EXTICR1_EXTI2_Msk (0x7U << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000700 */
Kojto 122:f9eeca106725 11258 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
Kojto 122:f9eeca106725 11259 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
Kojto 122:f9eeca106725 11260 #define SYSCFG_EXTICR1_EXTI3_Msk (0x7U << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x00007000 */
Kojto 122:f9eeca106725 11261 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
Kojto 122:f9eeca106725 11262
Kojto 122:f9eeca106725 11263 /**
Kojto 122:f9eeca106725 11264 * @brief EXTI0 configuration
Kojto 122:f9eeca106725 11265 */
Kojto 122:f9eeca106725 11266 #define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!<PA[0] pin */
Kojto 122:f9eeca106725 11267 #define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
Kojto 122:f9eeca106725 11268 #define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */
Kojto 122:f9eeca106725 11269
Kojto 122:f9eeca106725 11270 /**
Kojto 122:f9eeca106725 11271 * @brief EXTI1 configuration
Kojto 122:f9eeca106725 11272 */
Kojto 122:f9eeca106725 11273 #define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!<PA[1] pin */
Kojto 122:f9eeca106725 11274 #define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
Kojto 122:f9eeca106725 11275 #define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */
Kojto 122:f9eeca106725 11276
Kojto 122:f9eeca106725 11277 /**
Kojto 122:f9eeca106725 11278 * @brief EXTI2 configuration
Kojto 122:f9eeca106725 11279 */
Kojto 122:f9eeca106725 11280 #define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!<PA[2] pin */
Kojto 122:f9eeca106725 11281
Kojto 122:f9eeca106725 11282 /**
Kojto 122:f9eeca106725 11283 * @brief EXTI3 configuration
Kojto 122:f9eeca106725 11284 */
Kojto 122:f9eeca106725 11285 #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!<PA[3] pin */
Kojto 122:f9eeca106725 11286 #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
Kojto 122:f9eeca106725 11287 #define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */
Kojto 122:f9eeca106725 11288
Kojto 122:f9eeca106725 11289 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
Kojto 122:f9eeca106725 11290 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
Kojto 122:f9eeca106725 11291 #define SYSCFG_EXTICR2_EXTI4_Msk (0x7U << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x00000007 */
Kojto 122:f9eeca106725 11292 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
Kojto 122:f9eeca106725 11293 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
Kojto 122:f9eeca106725 11294 #define SYSCFG_EXTICR2_EXTI5_Msk (0x7U << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x00000070 */
Kojto 122:f9eeca106725 11295 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
Kojto 122:f9eeca106725 11296 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
Kojto 122:f9eeca106725 11297 #define SYSCFG_EXTICR2_EXTI6_Msk (0x7U << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000700 */
Kojto 122:f9eeca106725 11298 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
Kojto 122:f9eeca106725 11299 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
Kojto 122:f9eeca106725 11300 #define SYSCFG_EXTICR2_EXTI7_Msk (0x7U << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x00007000 */
Kojto 122:f9eeca106725 11301 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
Kojto 122:f9eeca106725 11302 /**
Kojto 122:f9eeca106725 11303 * @brief EXTI4 configuration
Kojto 122:f9eeca106725 11304 */
Kojto 122:f9eeca106725 11305 #define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!<PA[4] pin */
Kojto 122:f9eeca106725 11306 #define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
Kojto 122:f9eeca106725 11307
Kojto 122:f9eeca106725 11308 /**
Kojto 122:f9eeca106725 11309 * @brief EXTI5 configuration
Kojto 122:f9eeca106725 11310 */
Kojto 122:f9eeca106725 11311 #define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!<PA[5] pin */
Kojto 122:f9eeca106725 11312 #define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
Kojto 122:f9eeca106725 11313
Kojto 122:f9eeca106725 11314 /**
Kojto 122:f9eeca106725 11315 * @brief EXTI6 configuration
Kojto 122:f9eeca106725 11316 */
Kojto 122:f9eeca106725 11317 #define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!<PA[6] pin */
Kojto 122:f9eeca106725 11318 #define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
Kojto 122:f9eeca106725 11319
Kojto 122:f9eeca106725 11320 /**
Kojto 122:f9eeca106725 11321 * @brief EXTI7 configuration
Kojto 122:f9eeca106725 11322 */
Kojto 122:f9eeca106725 11323 #define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!<PA[7] pin */
Kojto 122:f9eeca106725 11324 #define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
Kojto 122:f9eeca106725 11325
Kojto 122:f9eeca106725 11326 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
Kojto 122:f9eeca106725 11327 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
Kojto 122:f9eeca106725 11328 #define SYSCFG_EXTICR3_EXTI8_Msk (0x7U << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x00000007 */
Kojto 122:f9eeca106725 11329 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
Kojto 122:f9eeca106725 11330 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
Kojto 122:f9eeca106725 11331 #define SYSCFG_EXTICR3_EXTI9_Msk (0x7U << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x00000070 */
Kojto 122:f9eeca106725 11332 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
Kojto 122:f9eeca106725 11333 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
Kojto 122:f9eeca106725 11334 #define SYSCFG_EXTICR3_EXTI10_Msk (0x7U << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000700 */
Kojto 122:f9eeca106725 11335 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
Kojto 122:f9eeca106725 11336 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
Kojto 122:f9eeca106725 11337 #define SYSCFG_EXTICR3_EXTI11_Msk (0x7U << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x00007000 */
Kojto 122:f9eeca106725 11338 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
Kojto 122:f9eeca106725 11339
Kojto 122:f9eeca106725 11340 /**
Kojto 122:f9eeca106725 11341 * @brief EXTI8 configuration
Kojto 122:f9eeca106725 11342 */
Kojto 122:f9eeca106725 11343 #define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!<PA[8] pin */
Kojto 122:f9eeca106725 11344
Kojto 122:f9eeca106725 11345 /**
Kojto 122:f9eeca106725 11346 * @brief EXTI9 configuration
Kojto 122:f9eeca106725 11347 */
Kojto 122:f9eeca106725 11348 #define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!<PA[9] pin */
Kojto 122:f9eeca106725 11349
Kojto 122:f9eeca106725 11350 /**
Kojto 122:f9eeca106725 11351 * @brief EXTI10 configuration
Kojto 122:f9eeca106725 11352 */
Kojto 122:f9eeca106725 11353 #define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!<PA[10] pin */
Kojto 122:f9eeca106725 11354
Kojto 122:f9eeca106725 11355 /**
Kojto 122:f9eeca106725 11356 * @brief EXTI11 configuration
Kojto 122:f9eeca106725 11357 */
Kojto 122:f9eeca106725 11358 #define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!<PA[11] pin */
Kojto 122:f9eeca106725 11359
Kojto 122:f9eeca106725 11360 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
Kojto 122:f9eeca106725 11361 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
Kojto 122:f9eeca106725 11362 #define SYSCFG_EXTICR4_EXTI12_Msk (0x7U << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x00000007 */
Kojto 122:f9eeca106725 11363 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
Kojto 122:f9eeca106725 11364 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
Kojto 122:f9eeca106725 11365 #define SYSCFG_EXTICR4_EXTI13_Msk (0x7U << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x00000070 */
Kojto 122:f9eeca106725 11366 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
Kojto 122:f9eeca106725 11367 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
Kojto 122:f9eeca106725 11368 #define SYSCFG_EXTICR4_EXTI14_Msk (0x7U << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000700 */
Kojto 122:f9eeca106725 11369 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
Kojto 122:f9eeca106725 11370 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
Kojto 122:f9eeca106725 11371 #define SYSCFG_EXTICR4_EXTI15_Msk (0x7U << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x00007000 */
Kojto 122:f9eeca106725 11372 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
Kojto 122:f9eeca106725 11373
Kojto 122:f9eeca106725 11374 /**
Kojto 122:f9eeca106725 11375 * @brief EXTI12 configuration
Kojto 122:f9eeca106725 11376 */
Kojto 122:f9eeca106725 11377 #define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!<PA[12] pin */
Kojto 122:f9eeca106725 11378
Kojto 122:f9eeca106725 11379 /**
Kojto 122:f9eeca106725 11380 * @brief EXTI13 configuration
Kojto 122:f9eeca106725 11381 */
Kojto 122:f9eeca106725 11382 #define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!<PA[13] pin */
Kojto 122:f9eeca106725 11383
Kojto 122:f9eeca106725 11384 /**
Kojto 122:f9eeca106725 11385 * @brief EXTI14 configuration
Kojto 122:f9eeca106725 11386 */
Kojto 122:f9eeca106725 11387 #define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!<PA[14] pin */
Kojto 122:f9eeca106725 11388 #define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
Kojto 122:f9eeca106725 11389
Kojto 122:f9eeca106725 11390 /**
Kojto 122:f9eeca106725 11391 * @brief EXTI15 configuration
Kojto 122:f9eeca106725 11392 */
Kojto 122:f9eeca106725 11393 #define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!<PA[15] pin */
Kojto 122:f9eeca106725 11394 #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
Kojto 122:f9eeca106725 11395
Kojto 122:f9eeca106725 11396 /****************** Bit definition for SYSCFG_SCSR register ****************/
Kojto 122:f9eeca106725 11397 #define SYSCFG_SCSR_SRAM2ER_Pos (0U)
Kojto 122:f9eeca106725 11398 #define SYSCFG_SCSR_SRAM2ER_Msk (0x1U << SYSCFG_SCSR_SRAM2ER_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 11399 #define SYSCFG_SCSR_SRAM2ER SYSCFG_SCSR_SRAM2ER_Msk /*!< SRAM2 Erase Request */
Kojto 122:f9eeca106725 11400 #define SYSCFG_SCSR_SRAM2BSY_Pos (1U)
Kojto 122:f9eeca106725 11401 #define SYSCFG_SCSR_SRAM2BSY_Msk (0x1U << SYSCFG_SCSR_SRAM2BSY_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 11402 #define SYSCFG_SCSR_SRAM2BSY SYSCFG_SCSR_SRAM2BSY_Msk /*!< SRAM2 Erase Ongoing */
Kojto 122:f9eeca106725 11403
Kojto 122:f9eeca106725 11404 /****************** Bit definition for SYSCFG_CFGR2 register ****************/
Kojto 122:f9eeca106725 11405 #define SYSCFG_CFGR2_CLL_Pos (0U)
Kojto 122:f9eeca106725 11406 #define SYSCFG_CFGR2_CLL_Msk (0x1U << SYSCFG_CFGR2_CLL_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 11407 #define SYSCFG_CFGR2_CLL SYSCFG_CFGR2_CLL_Msk /*!< Core Lockup Lock */
Kojto 122:f9eeca106725 11408 #define SYSCFG_CFGR2_SPL_Pos (1U)
Kojto 122:f9eeca106725 11409 #define SYSCFG_CFGR2_SPL_Msk (0x1U << SYSCFG_CFGR2_SPL_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 11410 #define SYSCFG_CFGR2_SPL SYSCFG_CFGR2_SPL_Msk /*!< SRAM Parity Lock*/
Kojto 122:f9eeca106725 11411 #define SYSCFG_CFGR2_PVDL_Pos (2U)
Kojto 122:f9eeca106725 11412 #define SYSCFG_CFGR2_PVDL_Msk (0x1U << SYSCFG_CFGR2_PVDL_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 11413 #define SYSCFG_CFGR2_PVDL SYSCFG_CFGR2_PVDL_Msk /*!< PVD Lock */
Kojto 122:f9eeca106725 11414 #define SYSCFG_CFGR2_ECCL_Pos (3U)
Kojto 122:f9eeca106725 11415 #define SYSCFG_CFGR2_ECCL_Msk (0x1U << SYSCFG_CFGR2_ECCL_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 11416 #define SYSCFG_CFGR2_ECCL SYSCFG_CFGR2_ECCL_Msk /*!< ECC Lock*/
Kojto 122:f9eeca106725 11417 #define SYSCFG_CFGR2_SPF_Pos (8U)
Kojto 122:f9eeca106725 11418 #define SYSCFG_CFGR2_SPF_Msk (0x1U << SYSCFG_CFGR2_SPF_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 11419 #define SYSCFG_CFGR2_SPF SYSCFG_CFGR2_SPF_Msk /*!< SRAM Parity Flag */
Kojto 122:f9eeca106725 11420
Kojto 122:f9eeca106725 11421 /****************** Bit definition for SYSCFG_SWPR register ****************/
Kojto 122:f9eeca106725 11422 #define SYSCFG_SWPR_PAGE0_Pos (0U)
Kojto 122:f9eeca106725 11423 #define SYSCFG_SWPR_PAGE0_Msk (0x1U << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 11424 #define SYSCFG_SWPR_PAGE0 SYSCFG_SWPR_PAGE0_Msk /*!< SRAM2 Write protection page 0 */
Kojto 122:f9eeca106725 11425 #define SYSCFG_SWPR_PAGE1_Pos (1U)
Kojto 122:f9eeca106725 11426 #define SYSCFG_SWPR_PAGE1_Msk (0x1U << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 11427 #define SYSCFG_SWPR_PAGE1 SYSCFG_SWPR_PAGE1_Msk /*!< SRAM2 Write protection page 1 */
Kojto 122:f9eeca106725 11428 #define SYSCFG_SWPR_PAGE2_Pos (2U)
Kojto 122:f9eeca106725 11429 #define SYSCFG_SWPR_PAGE2_Msk (0x1U << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 11430 #define SYSCFG_SWPR_PAGE2 SYSCFG_SWPR_PAGE2_Msk /*!< SRAM2 Write protection page 2 */
Kojto 122:f9eeca106725 11431 #define SYSCFG_SWPR_PAGE3_Pos (3U)
Kojto 122:f9eeca106725 11432 #define SYSCFG_SWPR_PAGE3_Msk (0x1U << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 11433 #define SYSCFG_SWPR_PAGE3 SYSCFG_SWPR_PAGE3_Msk /*!< SRAM2 Write protection page 3 */
Kojto 122:f9eeca106725 11434 #define SYSCFG_SWPR_PAGE4_Pos (4U)
Kojto 122:f9eeca106725 11435 #define SYSCFG_SWPR_PAGE4_Msk (0x1U << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 11436 #define SYSCFG_SWPR_PAGE4 SYSCFG_SWPR_PAGE4_Msk /*!< SRAM2 Write protection page 4 */
Kojto 122:f9eeca106725 11437 #define SYSCFG_SWPR_PAGE5_Pos (5U)
Kojto 122:f9eeca106725 11438 #define SYSCFG_SWPR_PAGE5_Msk (0x1U << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 11439 #define SYSCFG_SWPR_PAGE5 SYSCFG_SWPR_PAGE5_Msk /*!< SRAM2 Write protection page 5 */
Kojto 122:f9eeca106725 11440 #define SYSCFG_SWPR_PAGE6_Pos (6U)
Kojto 122:f9eeca106725 11441 #define SYSCFG_SWPR_PAGE6_Msk (0x1U << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 11442 #define SYSCFG_SWPR_PAGE6 SYSCFG_SWPR_PAGE6_Msk /*!< SRAM2 Write protection page 6 */
Kojto 122:f9eeca106725 11443 #define SYSCFG_SWPR_PAGE7_Pos (7U)
Kojto 122:f9eeca106725 11444 #define SYSCFG_SWPR_PAGE7_Msk (0x1U << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 11445 #define SYSCFG_SWPR_PAGE7 SYSCFG_SWPR_PAGE7_Msk /*!< SRAM2 Write protection page 7 */
Kojto 122:f9eeca106725 11446 #define SYSCFG_SWPR_PAGE8_Pos (8U)
Kojto 122:f9eeca106725 11447 #define SYSCFG_SWPR_PAGE8_Msk (0x1U << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 11448 #define SYSCFG_SWPR_PAGE8 SYSCFG_SWPR_PAGE8_Msk /*!< SRAM2 Write protection page 8 */
Kojto 122:f9eeca106725 11449 #define SYSCFG_SWPR_PAGE9_Pos (9U)
Kojto 122:f9eeca106725 11450 #define SYSCFG_SWPR_PAGE9_Msk (0x1U << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 11451 #define SYSCFG_SWPR_PAGE9 SYSCFG_SWPR_PAGE9_Msk /*!< SRAM2 Write protection page 9 */
Kojto 122:f9eeca106725 11452 #define SYSCFG_SWPR_PAGE10_Pos (10U)
Kojto 122:f9eeca106725 11453 #define SYSCFG_SWPR_PAGE10_Msk (0x1U << SYSCFG_SWPR_PAGE10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 11454 #define SYSCFG_SWPR_PAGE10 SYSCFG_SWPR_PAGE10_Msk /*!< SRAM2 Write protection page 10*/
Kojto 122:f9eeca106725 11455 #define SYSCFG_SWPR_PAGE11_Pos (11U)
Kojto 122:f9eeca106725 11456 #define SYSCFG_SWPR_PAGE11_Msk (0x1U << SYSCFG_SWPR_PAGE11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 11457 #define SYSCFG_SWPR_PAGE11 SYSCFG_SWPR_PAGE11_Msk /*!< SRAM2 Write protection page 11*/
Kojto 122:f9eeca106725 11458 #define SYSCFG_SWPR_PAGE12_Pos (12U)
Kojto 122:f9eeca106725 11459 #define SYSCFG_SWPR_PAGE12_Msk (0x1U << SYSCFG_SWPR_PAGE12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 11460 #define SYSCFG_SWPR_PAGE12 SYSCFG_SWPR_PAGE12_Msk /*!< SRAM2 Write protection page 12*/
Kojto 122:f9eeca106725 11461 #define SYSCFG_SWPR_PAGE13_Pos (13U)
Kojto 122:f9eeca106725 11462 #define SYSCFG_SWPR_PAGE13_Msk (0x1U << SYSCFG_SWPR_PAGE13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 11463 #define SYSCFG_SWPR_PAGE13 SYSCFG_SWPR_PAGE13_Msk /*!< SRAM2 Write protection page 13*/
Kojto 122:f9eeca106725 11464 #define SYSCFG_SWPR_PAGE14_Pos (14U)
Kojto 122:f9eeca106725 11465 #define SYSCFG_SWPR_PAGE14_Msk (0x1U << SYSCFG_SWPR_PAGE14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 11466 #define SYSCFG_SWPR_PAGE14 SYSCFG_SWPR_PAGE14_Msk /*!< SRAM2 Write protection page 14*/
Kojto 122:f9eeca106725 11467 #define SYSCFG_SWPR_PAGE15_Pos (15U)
Kojto 122:f9eeca106725 11468 #define SYSCFG_SWPR_PAGE15_Msk (0x1U << SYSCFG_SWPR_PAGE15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 11469 #define SYSCFG_SWPR_PAGE15 SYSCFG_SWPR_PAGE15_Msk /*!< SRAM2 Write protection page 15*/
Kojto 122:f9eeca106725 11470
Kojto 122:f9eeca106725 11471 /****************** Bit definition for SYSCFG_SKR register ****************/
Kojto 122:f9eeca106725 11472 #define SYSCFG_SKR_KEY_Pos (0U)
Kojto 122:f9eeca106725 11473 #define SYSCFG_SKR_KEY_Msk (0xFFU << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 11474 #define SYSCFG_SKR_KEY SYSCFG_SKR_KEY_Msk /*!< SRAM2 write protection key for software erase */
Kojto 122:f9eeca106725 11475
Kojto 122:f9eeca106725 11476
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Kojto 122:f9eeca106725 11478
Kojto 122:f9eeca106725 11479 /******************************************************************************/
Kojto 122:f9eeca106725 11480 /* */
Kojto 122:f9eeca106725 11481 /* TIM */
Kojto 122:f9eeca106725 11482 /* */
Kojto 122:f9eeca106725 11483 /******************************************************************************/
Kojto 122:f9eeca106725 11484 /******************* Bit definition for TIM_CR1 register ********************/
Kojto 122:f9eeca106725 11485 #define TIM_CR1_CEN_Pos (0U)
Kojto 122:f9eeca106725 11486 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 11487 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
Kojto 122:f9eeca106725 11488 #define TIM_CR1_UDIS_Pos (1U)
Kojto 122:f9eeca106725 11489 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 11490 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
Kojto 122:f9eeca106725 11491 #define TIM_CR1_URS_Pos (2U)
Kojto 122:f9eeca106725 11492 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 11493 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
Kojto 122:f9eeca106725 11494 #define TIM_CR1_OPM_Pos (3U)
Kojto 122:f9eeca106725 11495 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 11496 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
Kojto 122:f9eeca106725 11497 #define TIM_CR1_DIR_Pos (4U)
Kojto 122:f9eeca106725 11498 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 11499 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
Kojto 122:f9eeca106725 11500
Kojto 122:f9eeca106725 11501 #define TIM_CR1_CMS_Pos (5U)
Kojto 122:f9eeca106725 11502 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
Kojto 122:f9eeca106725 11503 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
Kojto 122:f9eeca106725 11504 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 11505 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 11506
Kojto 122:f9eeca106725 11507 #define TIM_CR1_ARPE_Pos (7U)
Kojto 122:f9eeca106725 11508 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 11509 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
Kojto 122:f9eeca106725 11510
Kojto 122:f9eeca106725 11511 #define TIM_CR1_CKD_Pos (8U)
Kojto 122:f9eeca106725 11512 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 11513 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
Kojto 122:f9eeca106725 11514 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 11515 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 11516
Kojto 122:f9eeca106725 11517 #define TIM_CR1_UIFREMAP_Pos (11U)
Kojto 122:f9eeca106725 11518 #define TIM_CR1_UIFREMAP_Msk (0x1U << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 11519 #define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */
Kojto 122:f9eeca106725 11520
Kojto 122:f9eeca106725 11521 /******************* Bit definition for TIM_CR2 register ********************/
Kojto 122:f9eeca106725 11522 #define TIM_CR2_CCPC_Pos (0U)
Kojto 122:f9eeca106725 11523 #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 11524 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
Kojto 122:f9eeca106725 11525 #define TIM_CR2_CCUS_Pos (2U)
Kojto 122:f9eeca106725 11526 #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 11527 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
Kojto 122:f9eeca106725 11528 #define TIM_CR2_CCDS_Pos (3U)
Kojto 122:f9eeca106725 11529 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 11530 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
Kojto 122:f9eeca106725 11531
Kojto 122:f9eeca106725 11532 #define TIM_CR2_MMS_Pos (4U)
Kojto 122:f9eeca106725 11533 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
Kojto 122:f9eeca106725 11534 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
Kojto 122:f9eeca106725 11535 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 11536 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 11537 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 11538
Kojto 122:f9eeca106725 11539 #define TIM_CR2_TI1S_Pos (7U)
Kojto 122:f9eeca106725 11540 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 11541 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
Kojto 122:f9eeca106725 11542 #define TIM_CR2_OIS1_Pos (8U)
Kojto 122:f9eeca106725 11543 #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 11544 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
Kojto 122:f9eeca106725 11545 #define TIM_CR2_OIS1N_Pos (9U)
Kojto 122:f9eeca106725 11546 #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 11547 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
Kojto 122:f9eeca106725 11548 #define TIM_CR2_OIS2_Pos (10U)
Kojto 122:f9eeca106725 11549 #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 11550 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
Kojto 122:f9eeca106725 11551 #define TIM_CR2_OIS2N_Pos (11U)
Kojto 122:f9eeca106725 11552 #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 11553 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
Kojto 122:f9eeca106725 11554 #define TIM_CR2_OIS3_Pos (12U)
Kojto 122:f9eeca106725 11555 #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 11556 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
Kojto 122:f9eeca106725 11557 #define TIM_CR2_OIS3N_Pos (13U)
Kojto 122:f9eeca106725 11558 #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 11559 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
Kojto 122:f9eeca106725 11560 #define TIM_CR2_OIS4_Pos (14U)
Kojto 122:f9eeca106725 11561 #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 11562 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
Kojto 122:f9eeca106725 11563 #define TIM_CR2_OIS5_Pos (16U)
Kojto 122:f9eeca106725 11564 #define TIM_CR2_OIS5_Msk (0x1U << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 11565 #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 5 (OC5 output) */
Kojto 122:f9eeca106725 11566 #define TIM_CR2_OIS6_Pos (18U)
Kojto 122:f9eeca106725 11567 #define TIM_CR2_OIS6_Msk (0x1U << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 11568 #define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 6 (OC6 output) */
Kojto 122:f9eeca106725 11569
Kojto 122:f9eeca106725 11570 #define TIM_CR2_MMS2_Pos (20U)
Kojto 122:f9eeca106725 11571 #define TIM_CR2_MMS2_Msk (0xFU << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */
Kojto 122:f9eeca106725 11572 #define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
Kojto 122:f9eeca106725 11573 #define TIM_CR2_MMS2_0 (0x1U << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 11574 #define TIM_CR2_MMS2_1 (0x2U << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 11575 #define TIM_CR2_MMS2_2 (0x4U << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 11576 #define TIM_CR2_MMS2_3 (0x8U << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 11577
Kojto 122:f9eeca106725 11578 /******************* Bit definition for TIM_SMCR register *******************/
Kojto 122:f9eeca106725 11579 #define TIM_SMCR_SMS_Pos (0U)
Kojto 122:f9eeca106725 11580 #define TIM_SMCR_SMS_Msk (0x10007U << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */
Kojto 122:f9eeca106725 11581 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
Kojto 122:f9eeca106725 11582 #define TIM_SMCR_SMS_0 (0x00001U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 11583 #define TIM_SMCR_SMS_1 (0x00002U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 11584 #define TIM_SMCR_SMS_2 (0x00004U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 11585 #define TIM_SMCR_SMS_3 (0x10000U << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 11586
Kojto 122:f9eeca106725 11587 #define TIM_SMCR_OCCS_Pos (3U)
Kojto 122:f9eeca106725 11588 #define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 11589 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
Kojto 122:f9eeca106725 11590
Kojto 122:f9eeca106725 11591 #define TIM_SMCR_TS_Pos (4U)
Kojto 122:f9eeca106725 11592 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
Kojto 122:f9eeca106725 11593 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
Kojto 122:f9eeca106725 11594 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 11595 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 11596 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 11597
Kojto 122:f9eeca106725 11598 #define TIM_SMCR_MSM_Pos (7U)
Kojto 122:f9eeca106725 11599 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 11600 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
Kojto 122:f9eeca106725 11601
Kojto 122:f9eeca106725 11602 #define TIM_SMCR_ETF_Pos (8U)
Kojto 122:f9eeca106725 11603 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 11604 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
Kojto 122:f9eeca106725 11605 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 11606 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 11607 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 11608 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 11609
Kojto 122:f9eeca106725 11610 #define TIM_SMCR_ETPS_Pos (12U)
Kojto 122:f9eeca106725 11611 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
Kojto 122:f9eeca106725 11612 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
Kojto 122:f9eeca106725 11613 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 11614 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 11615
Kojto 122:f9eeca106725 11616 #define TIM_SMCR_ECE_Pos (14U)
Kojto 122:f9eeca106725 11617 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 11618 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
Kojto 122:f9eeca106725 11619 #define TIM_SMCR_ETP_Pos (15U)
Kojto 122:f9eeca106725 11620 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 11621 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
Kojto 122:f9eeca106725 11622
Kojto 122:f9eeca106725 11623 /******************* Bit definition for TIM_DIER register *******************/
Kojto 122:f9eeca106725 11624 #define TIM_DIER_UIE_Pos (0U)
Kojto 122:f9eeca106725 11625 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 11626 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
Kojto 122:f9eeca106725 11627 #define TIM_DIER_CC1IE_Pos (1U)
Kojto 122:f9eeca106725 11628 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 11629 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
Kojto 122:f9eeca106725 11630 #define TIM_DIER_CC2IE_Pos (2U)
Kojto 122:f9eeca106725 11631 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 11632 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
Kojto 122:f9eeca106725 11633 #define TIM_DIER_CC3IE_Pos (3U)
Kojto 122:f9eeca106725 11634 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 11635 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
Kojto 122:f9eeca106725 11636 #define TIM_DIER_CC4IE_Pos (4U)
Kojto 122:f9eeca106725 11637 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 11638 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
Kojto 122:f9eeca106725 11639 #define TIM_DIER_COMIE_Pos (5U)
Kojto 122:f9eeca106725 11640 #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 11641 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
Kojto 122:f9eeca106725 11642 #define TIM_DIER_TIE_Pos (6U)
Kojto 122:f9eeca106725 11643 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 11644 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
Kojto 122:f9eeca106725 11645 #define TIM_DIER_BIE_Pos (7U)
Kojto 122:f9eeca106725 11646 #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 11647 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
Kojto 122:f9eeca106725 11648 #define TIM_DIER_UDE_Pos (8U)
Kojto 122:f9eeca106725 11649 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 11650 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
Kojto 122:f9eeca106725 11651 #define TIM_DIER_CC1DE_Pos (9U)
Kojto 122:f9eeca106725 11652 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 11653 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
Kojto 122:f9eeca106725 11654 #define TIM_DIER_CC2DE_Pos (10U)
Kojto 122:f9eeca106725 11655 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 11656 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
Kojto 122:f9eeca106725 11657 #define TIM_DIER_CC3DE_Pos (11U)
Kojto 122:f9eeca106725 11658 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 11659 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
Kojto 122:f9eeca106725 11660 #define TIM_DIER_CC4DE_Pos (12U)
Kojto 122:f9eeca106725 11661 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 11662 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
Kojto 122:f9eeca106725 11663 #define TIM_DIER_COMDE_Pos (13U)
Kojto 122:f9eeca106725 11664 #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 11665 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
Kojto 122:f9eeca106725 11666 #define TIM_DIER_TDE_Pos (14U)
Kojto 122:f9eeca106725 11667 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 11668 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
Kojto 122:f9eeca106725 11669
Kojto 122:f9eeca106725 11670 /******************** Bit definition for TIM_SR register ********************/
Kojto 122:f9eeca106725 11671 #define TIM_SR_UIF_Pos (0U)
Kojto 122:f9eeca106725 11672 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 11673 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
Kojto 122:f9eeca106725 11674 #define TIM_SR_CC1IF_Pos (1U)
Kojto 122:f9eeca106725 11675 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 11676 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
Kojto 122:f9eeca106725 11677 #define TIM_SR_CC2IF_Pos (2U)
Kojto 122:f9eeca106725 11678 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 11679 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
Kojto 122:f9eeca106725 11680 #define TIM_SR_CC3IF_Pos (3U)
Kojto 122:f9eeca106725 11681 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 11682 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
Kojto 122:f9eeca106725 11683 #define TIM_SR_CC4IF_Pos (4U)
Kojto 122:f9eeca106725 11684 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 11685 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
Kojto 122:f9eeca106725 11686 #define TIM_SR_COMIF_Pos (5U)
Kojto 122:f9eeca106725 11687 #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 11688 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
Kojto 122:f9eeca106725 11689 #define TIM_SR_TIF_Pos (6U)
Kojto 122:f9eeca106725 11690 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 11691 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
Kojto 122:f9eeca106725 11692 #define TIM_SR_BIF_Pos (7U)
Kojto 122:f9eeca106725 11693 #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 11694 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
Kojto 122:f9eeca106725 11695 #define TIM_SR_B2IF_Pos (8U)
Kojto 122:f9eeca106725 11696 #define TIM_SR_B2IF_Msk (0x1U << TIM_SR_B2IF_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 11697 #define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break 2 interrupt Flag */
Kojto 122:f9eeca106725 11698 #define TIM_SR_CC1OF_Pos (9U)
Kojto 122:f9eeca106725 11699 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 11700 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
Kojto 122:f9eeca106725 11701 #define TIM_SR_CC2OF_Pos (10U)
Kojto 122:f9eeca106725 11702 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 11703 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
Kojto 122:f9eeca106725 11704 #define TIM_SR_CC3OF_Pos (11U)
Kojto 122:f9eeca106725 11705 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 11706 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
Kojto 122:f9eeca106725 11707 #define TIM_SR_CC4OF_Pos (12U)
Kojto 122:f9eeca106725 11708 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 11709 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
Kojto 122:f9eeca106725 11710 #define TIM_SR_SBIF_Pos (13U)
Kojto 122:f9eeca106725 11711 #define TIM_SR_SBIF_Msk (0x1U << TIM_SR_SBIF_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 11712 #define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!<System Break interrupt Flag */
Kojto 122:f9eeca106725 11713 #define TIM_SR_CC5IF_Pos (16U)
Kojto 122:f9eeca106725 11714 #define TIM_SR_CC5IF_Msk (0x1U << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 11715 #define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */
Kojto 122:f9eeca106725 11716 #define TIM_SR_CC6IF_Pos (17U)
Kojto 122:f9eeca106725 11717 #define TIM_SR_CC6IF_Msk (0x1U << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 11718 #define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */
Kojto 122:f9eeca106725 11719
Kojto 122:f9eeca106725 11720
Kojto 122:f9eeca106725 11721 /******************* Bit definition for TIM_EGR register ********************/
Kojto 122:f9eeca106725 11722 #define TIM_EGR_UG_Pos (0U)
Kojto 122:f9eeca106725 11723 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 11724 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
Kojto 122:f9eeca106725 11725 #define TIM_EGR_CC1G_Pos (1U)
Kojto 122:f9eeca106725 11726 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 11727 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
Kojto 122:f9eeca106725 11728 #define TIM_EGR_CC2G_Pos (2U)
Kojto 122:f9eeca106725 11729 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 11730 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
Kojto 122:f9eeca106725 11731 #define TIM_EGR_CC3G_Pos (3U)
Kojto 122:f9eeca106725 11732 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 11733 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
Kojto 122:f9eeca106725 11734 #define TIM_EGR_CC4G_Pos (4U)
Kojto 122:f9eeca106725 11735 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 11736 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
Kojto 122:f9eeca106725 11737 #define TIM_EGR_COMG_Pos (5U)
Kojto 122:f9eeca106725 11738 #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 11739 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
Kojto 122:f9eeca106725 11740 #define TIM_EGR_TG_Pos (6U)
Kojto 122:f9eeca106725 11741 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 11742 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
Kojto 122:f9eeca106725 11743 #define TIM_EGR_BG_Pos (7U)
Kojto 122:f9eeca106725 11744 #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 11745 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
Kojto 122:f9eeca106725 11746 #define TIM_EGR_B2G_Pos (8U)
Kojto 122:f9eeca106725 11747 #define TIM_EGR_B2G_Msk (0x1U << TIM_EGR_B2G_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 11748 #define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break 2 Generation */
Kojto 122:f9eeca106725 11749
Kojto 122:f9eeca106725 11750
Kojto 122:f9eeca106725 11751 /****************** Bit definition for TIM_CCMR1 register *******************/
Kojto 122:f9eeca106725 11752 #define TIM_CCMR1_CC1S_Pos (0U)
Kojto 122:f9eeca106725 11753 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 11754 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
Kojto 122:f9eeca106725 11755 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 11756 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 11757
Kojto 122:f9eeca106725 11758 #define TIM_CCMR1_OC1FE_Pos (2U)
Kojto 122:f9eeca106725 11759 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 11760 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
Kojto 122:f9eeca106725 11761 #define TIM_CCMR1_OC1PE_Pos (3U)
Kojto 122:f9eeca106725 11762 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 11763 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
Kojto 122:f9eeca106725 11764
Kojto 122:f9eeca106725 11765 #define TIM_CCMR1_OC1M_Pos (4U)
Kojto 122:f9eeca106725 11766 #define TIM_CCMR1_OC1M_Msk (0x1007U << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */
Kojto 122:f9eeca106725 11767 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
Kojto 122:f9eeca106725 11768 #define TIM_CCMR1_OC1M_0 (0x0001U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 11769 #define TIM_CCMR1_OC1M_1 (0x0002U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 11770 #define TIM_CCMR1_OC1M_2 (0x0004U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 11771 #define TIM_CCMR1_OC1M_3 (0x1000U << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 11772
Kojto 122:f9eeca106725 11773 #define TIM_CCMR1_OC1CE_Pos (7U)
Kojto 122:f9eeca106725 11774 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 11775 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1 Clear Enable */
Kojto 122:f9eeca106725 11776
Kojto 122:f9eeca106725 11777 #define TIM_CCMR1_CC2S_Pos (8U)
Kojto 122:f9eeca106725 11778 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 11779 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
Kojto 122:f9eeca106725 11780 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 11781 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 11782
Kojto 122:f9eeca106725 11783 #define TIM_CCMR1_OC2FE_Pos (10U)
Kojto 122:f9eeca106725 11784 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 11785 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
Kojto 122:f9eeca106725 11786 #define TIM_CCMR1_OC2PE_Pos (11U)
Kojto 122:f9eeca106725 11787 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 11788 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
Kojto 122:f9eeca106725 11789
Kojto 122:f9eeca106725 11790 #define TIM_CCMR1_OC2M_Pos (12U)
Kojto 122:f9eeca106725 11791 #define TIM_CCMR1_OC2M_Msk (0x1007U << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */
Kojto 122:f9eeca106725 11792 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
Kojto 122:f9eeca106725 11793 #define TIM_CCMR1_OC2M_0 (0x0001U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 11794 #define TIM_CCMR1_OC2M_1 (0x0002U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 11795 #define TIM_CCMR1_OC2M_2 (0x0004U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 11796 #define TIM_CCMR1_OC2M_3 (0x1000U << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 11797
Kojto 122:f9eeca106725 11798 #define TIM_CCMR1_OC2CE_Pos (15U)
Kojto 122:f9eeca106725 11799 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 11800 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
Kojto 122:f9eeca106725 11801
Kojto 122:f9eeca106725 11802 /*----------------------------------------------------------------------------*/
Kojto 122:f9eeca106725 11803 #define TIM_CCMR1_IC1PSC_Pos (2U)
Kojto 122:f9eeca106725 11804 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
Kojto 122:f9eeca106725 11805 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
Kojto 122:f9eeca106725 11806 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 11807 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 11808
Kojto 122:f9eeca106725 11809 #define TIM_CCMR1_IC1F_Pos (4U)
Kojto 122:f9eeca106725 11810 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
Kojto 122:f9eeca106725 11811 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
Kojto 122:f9eeca106725 11812 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 11813 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 11814 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 11815 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 11816
Kojto 122:f9eeca106725 11817 #define TIM_CCMR1_IC2PSC_Pos (10U)
Kojto 122:f9eeca106725 11818 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
Kojto 122:f9eeca106725 11819 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
Kojto 122:f9eeca106725 11820 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 11821 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 11822
Kojto 122:f9eeca106725 11823 #define TIM_CCMR1_IC2F_Pos (12U)
Kojto 122:f9eeca106725 11824 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
Kojto 122:f9eeca106725 11825 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
Kojto 122:f9eeca106725 11826 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 11827 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 11828 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 11829 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 11830
Kojto 122:f9eeca106725 11831 /****************** Bit definition for TIM_CCMR2 register *******************/
Kojto 122:f9eeca106725 11832 #define TIM_CCMR2_CC3S_Pos (0U)
Kojto 122:f9eeca106725 11833 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 11834 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
Kojto 122:f9eeca106725 11835 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 11836 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 11837
Kojto 122:f9eeca106725 11838 #define TIM_CCMR2_OC3FE_Pos (2U)
Kojto 122:f9eeca106725 11839 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 11840 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
Kojto 122:f9eeca106725 11841 #define TIM_CCMR2_OC3PE_Pos (3U)
Kojto 122:f9eeca106725 11842 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 11843 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
Kojto 122:f9eeca106725 11844
Kojto 122:f9eeca106725 11845 #define TIM_CCMR2_OC3M_Pos (4U)
Kojto 122:f9eeca106725 11846 #define TIM_CCMR2_OC3M_Msk (0x1007U << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
Kojto 122:f9eeca106725 11847 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
Kojto 122:f9eeca106725 11848 #define TIM_CCMR2_OC3M_0 (0x0001U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 11849 #define TIM_CCMR2_OC3M_1 (0x0002U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 11850 #define TIM_CCMR2_OC3M_2 (0x0004U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 11851 #define TIM_CCMR2_OC3M_3 (0x1000U << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 11852
Kojto 122:f9eeca106725 11853 #define TIM_CCMR2_OC3CE_Pos (7U)
Kojto 122:f9eeca106725 11854 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 11855 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
Kojto 122:f9eeca106725 11856
Kojto 122:f9eeca106725 11857 #define TIM_CCMR2_CC4S_Pos (8U)
Kojto 122:f9eeca106725 11858 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 11859 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
Kojto 122:f9eeca106725 11860 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 11861 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 11862
Kojto 122:f9eeca106725 11863 #define TIM_CCMR2_OC4FE_Pos (10U)
Kojto 122:f9eeca106725 11864 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 11865 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
Kojto 122:f9eeca106725 11866 #define TIM_CCMR2_OC4PE_Pos (11U)
Kojto 122:f9eeca106725 11867 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 11868 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
Kojto 122:f9eeca106725 11869
Kojto 122:f9eeca106725 11870 #define TIM_CCMR2_OC4M_Pos (12U)
Kojto 122:f9eeca106725 11871 #define TIM_CCMR2_OC4M_Msk (0x1007U << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
Kojto 122:f9eeca106725 11872 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
Kojto 122:f9eeca106725 11873 #define TIM_CCMR2_OC4M_0 (0x0001U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 11874 #define TIM_CCMR2_OC4M_1 (0x0002U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 11875 #define TIM_CCMR2_OC4M_2 (0x0004U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 11876 #define TIM_CCMR2_OC4M_3 (0x1000U << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 11877
Kojto 122:f9eeca106725 11878 #define TIM_CCMR2_OC4CE_Pos (15U)
Kojto 122:f9eeca106725 11879 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 11880 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
Kojto 122:f9eeca106725 11881
Kojto 122:f9eeca106725 11882 /*----------------------------------------------------------------------------*/
Kojto 122:f9eeca106725 11883 #define TIM_CCMR2_IC3PSC_Pos (2U)
Kojto 122:f9eeca106725 11884 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
Kojto 122:f9eeca106725 11885 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
Kojto 122:f9eeca106725 11886 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 11887 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 11888
Kojto 122:f9eeca106725 11889 #define TIM_CCMR2_IC3F_Pos (4U)
Kojto 122:f9eeca106725 11890 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
Kojto 122:f9eeca106725 11891 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
Kojto 122:f9eeca106725 11892 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 11893 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 11894 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 11895 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 11896
Kojto 122:f9eeca106725 11897 #define TIM_CCMR2_IC4PSC_Pos (10U)
Kojto 122:f9eeca106725 11898 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
Kojto 122:f9eeca106725 11899 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
Kojto 122:f9eeca106725 11900 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 11901 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 11902
Kojto 122:f9eeca106725 11903 #define TIM_CCMR2_IC4F_Pos (12U)
Kojto 122:f9eeca106725 11904 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
Kojto 122:f9eeca106725 11905 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
Kojto 122:f9eeca106725 11906 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 11907 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 11908 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 11909 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 11910
Kojto 122:f9eeca106725 11911 /****************** Bit definition for TIM_CCMR3 register *******************/
Kojto 122:f9eeca106725 11912 #define TIM_CCMR3_OC5FE_Pos (2U)
Kojto 122:f9eeca106725 11913 #define TIM_CCMR3_OC5FE_Msk (0x1U << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 11914 #define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
Kojto 122:f9eeca106725 11915 #define TIM_CCMR3_OC5PE_Pos (3U)
Kojto 122:f9eeca106725 11916 #define TIM_CCMR3_OC5PE_Msk (0x1U << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 11917 #define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
Kojto 122:f9eeca106725 11918
Kojto 122:f9eeca106725 11919 #define TIM_CCMR3_OC5M_Pos (4U)
Kojto 122:f9eeca106725 11920 #define TIM_CCMR3_OC5M_Msk (0x1007U << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
Kojto 122:f9eeca106725 11921 #define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
Kojto 122:f9eeca106725 11922 #define TIM_CCMR3_OC5M_0 (0x0001U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 11923 #define TIM_CCMR3_OC5M_1 (0x0002U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 11924 #define TIM_CCMR3_OC5M_2 (0x0004U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 11925 #define TIM_CCMR3_OC5M_3 (0x1000U << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 11926
Kojto 122:f9eeca106725 11927 #define TIM_CCMR3_OC5CE_Pos (7U)
Kojto 122:f9eeca106725 11928 #define TIM_CCMR3_OC5CE_Msk (0x1U << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 11929 #define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */
Kojto 122:f9eeca106725 11930
Kojto 122:f9eeca106725 11931 #define TIM_CCMR3_OC6FE_Pos (10U)
Kojto 122:f9eeca106725 11932 #define TIM_CCMR3_OC6FE_Msk (0x1U << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 11933 #define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */
Kojto 122:f9eeca106725 11934 #define TIM_CCMR3_OC6PE_Pos (11U)
Kojto 122:f9eeca106725 11935 #define TIM_CCMR3_OC6PE_Msk (0x1U << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 11936 #define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 6 Preload enable */
Kojto 122:f9eeca106725 11937
Kojto 122:f9eeca106725 11938 #define TIM_CCMR3_OC6M_Pos (12U)
Kojto 122:f9eeca106725 11939 #define TIM_CCMR3_OC6M_Msk (0x1007U << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
Kojto 122:f9eeca106725 11940 #define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
Kojto 122:f9eeca106725 11941 #define TIM_CCMR3_OC6M_0 (0x0001U << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 11942 #define TIM_CCMR3_OC6M_1 (0x0002U << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 11943 #define TIM_CCMR3_OC6M_2 (0x0004U << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 11944 #define TIM_CCMR3_OC6M_3 (0x1000U << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 11945
Kojto 122:f9eeca106725 11946 #define TIM_CCMR3_OC6CE_Pos (15U)
Kojto 122:f9eeca106725 11947 #define TIM_CCMR3_OC6CE_Msk (0x1U << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 11948 #define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 6 Clear Enable */
Kojto 122:f9eeca106725 11949
Kojto 122:f9eeca106725 11950 /******************* Bit definition for TIM_CCER register *******************/
Kojto 122:f9eeca106725 11951 #define TIM_CCER_CC1E_Pos (0U)
Kojto 122:f9eeca106725 11952 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 11953 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
Kojto 122:f9eeca106725 11954 #define TIM_CCER_CC1P_Pos (1U)
Kojto 122:f9eeca106725 11955 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 11956 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
Kojto 122:f9eeca106725 11957 #define TIM_CCER_CC1NE_Pos (2U)
Kojto 122:f9eeca106725 11958 #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 11959 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
Kojto 122:f9eeca106725 11960 #define TIM_CCER_CC1NP_Pos (3U)
Kojto 122:f9eeca106725 11961 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 11962 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
Kojto 122:f9eeca106725 11963 #define TIM_CCER_CC2E_Pos (4U)
Kojto 122:f9eeca106725 11964 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 11965 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
Kojto 122:f9eeca106725 11966 #define TIM_CCER_CC2P_Pos (5U)
Kojto 122:f9eeca106725 11967 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 11968 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
Kojto 122:f9eeca106725 11969 #define TIM_CCER_CC2NE_Pos (6U)
Kojto 122:f9eeca106725 11970 #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 11971 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
Kojto 122:f9eeca106725 11972 #define TIM_CCER_CC2NP_Pos (7U)
Kojto 122:f9eeca106725 11973 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 11974 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
Kojto 122:f9eeca106725 11975 #define TIM_CCER_CC3E_Pos (8U)
Kojto 122:f9eeca106725 11976 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 11977 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
Kojto 122:f9eeca106725 11978 #define TIM_CCER_CC3P_Pos (9U)
Kojto 122:f9eeca106725 11979 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 11980 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
Kojto 122:f9eeca106725 11981 #define TIM_CCER_CC3NE_Pos (10U)
Kojto 122:f9eeca106725 11982 #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 11983 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
Kojto 122:f9eeca106725 11984 #define TIM_CCER_CC3NP_Pos (11U)
Kojto 122:f9eeca106725 11985 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 11986 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
Kojto 122:f9eeca106725 11987 #define TIM_CCER_CC4E_Pos (12U)
Kojto 122:f9eeca106725 11988 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 11989 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
Kojto 122:f9eeca106725 11990 #define TIM_CCER_CC4P_Pos (13U)
Kojto 122:f9eeca106725 11991 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 11992 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
Kojto 122:f9eeca106725 11993 #define TIM_CCER_CC4NP_Pos (15U)
Kojto 122:f9eeca106725 11994 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 11995 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
Kojto 122:f9eeca106725 11996 #define TIM_CCER_CC5E_Pos (16U)
Kojto 122:f9eeca106725 11997 #define TIM_CCER_CC5E_Msk (0x1U << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 11998 #define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */
Kojto 122:f9eeca106725 11999 #define TIM_CCER_CC5P_Pos (17U)
Kojto 122:f9eeca106725 12000 #define TIM_CCER_CC5P_Msk (0x1U << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 12001 #define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */
Kojto 122:f9eeca106725 12002 #define TIM_CCER_CC6E_Pos (20U)
Kojto 122:f9eeca106725 12003 #define TIM_CCER_CC6E_Msk (0x1U << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 12004 #define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */
Kojto 122:f9eeca106725 12005 #define TIM_CCER_CC6P_Pos (21U)
Kojto 122:f9eeca106725 12006 #define TIM_CCER_CC6P_Msk (0x1U << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 12007 #define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */
Kojto 122:f9eeca106725 12008
Kojto 122:f9eeca106725 12009 /******************* Bit definition for TIM_CNT register ********************/
Kojto 122:f9eeca106725 12010 #define TIM_CNT_CNT_Pos (0U)
Kojto 122:f9eeca106725 12011 #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 12012 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
Kojto 122:f9eeca106725 12013 #define TIM_CNT_UIFCPY_Pos (31U)
Kojto 122:f9eeca106725 12014 #define TIM_CNT_UIFCPY_Msk (0x1U << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 12015 #define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy (if UIFREMAP=1) */
Kojto 122:f9eeca106725 12016
Kojto 122:f9eeca106725 12017 /******************* Bit definition for TIM_PSC register ********************/
Kojto 122:f9eeca106725 12018 #define TIM_PSC_PSC_Pos (0U)
Kojto 122:f9eeca106725 12019 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 12020 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
Kojto 122:f9eeca106725 12021
Kojto 122:f9eeca106725 12022 /******************* Bit definition for TIM_ARR register ********************/
Kojto 122:f9eeca106725 12023 #define TIM_ARR_ARR_Pos (0U)
Kojto 122:f9eeca106725 12024 #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 12025 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<Actual auto-reload Value */
Kojto 122:f9eeca106725 12026
Kojto 122:f9eeca106725 12027 /******************* Bit definition for TIM_RCR register ********************/
Kojto 122:f9eeca106725 12028 #define TIM_RCR_REP_Pos (0U)
Kojto 122:f9eeca106725 12029 #define TIM_RCR_REP_Msk (0xFFFFU << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 12030 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
Kojto 122:f9eeca106725 12031
Kojto 122:f9eeca106725 12032 /******************* Bit definition for TIM_CCR1 register *******************/
Kojto 122:f9eeca106725 12033 #define TIM_CCR1_CCR1_Pos (0U)
Kojto 122:f9eeca106725 12034 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 12035 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
Kojto 122:f9eeca106725 12036
Kojto 122:f9eeca106725 12037 /******************* Bit definition for TIM_CCR2 register *******************/
Kojto 122:f9eeca106725 12038 #define TIM_CCR2_CCR2_Pos (0U)
Kojto 122:f9eeca106725 12039 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 12040 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
Kojto 122:f9eeca106725 12041
Kojto 122:f9eeca106725 12042 /******************* Bit definition for TIM_CCR3 register *******************/
Kojto 122:f9eeca106725 12043 #define TIM_CCR3_CCR3_Pos (0U)
Kojto 122:f9eeca106725 12044 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 12045 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
Kojto 122:f9eeca106725 12046
Kojto 122:f9eeca106725 12047 /******************* Bit definition for TIM_CCR4 register *******************/
Kojto 122:f9eeca106725 12048 #define TIM_CCR4_CCR4_Pos (0U)
Kojto 122:f9eeca106725 12049 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 12050 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
Kojto 122:f9eeca106725 12051
Kojto 122:f9eeca106725 12052 /******************* Bit definition for TIM_CCR5 register *******************/
Kojto 122:f9eeca106725 12053 #define TIM_CCR5_CCR5_Pos (0U)
Kojto 122:f9eeca106725 12054 #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFU << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 12055 #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
Kojto 122:f9eeca106725 12056 #define TIM_CCR5_GC5C1_Pos (29U)
Kojto 122:f9eeca106725 12057 #define TIM_CCR5_GC5C1_Msk (0x1U << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 12058 #define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */
Kojto 122:f9eeca106725 12059 #define TIM_CCR5_GC5C2_Pos (30U)
Kojto 122:f9eeca106725 12060 #define TIM_CCR5_GC5C2_Msk (0x1U << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 12061 #define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */
Kojto 122:f9eeca106725 12062 #define TIM_CCR5_GC5C3_Pos (31U)
Kojto 122:f9eeca106725 12063 #define TIM_CCR5_GC5C3_Msk (0x1U << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 12064 #define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */
Kojto 122:f9eeca106725 12065
Kojto 122:f9eeca106725 12066 /******************* Bit definition for TIM_CCR6 register *******************/
Kojto 122:f9eeca106725 12067 #define TIM_CCR6_CCR6_Pos (0U)
Kojto 122:f9eeca106725 12068 #define TIM_CCR6_CCR6_Msk (0xFFFFU << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 12069 #define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */
Kojto 122:f9eeca106725 12070
Kojto 122:f9eeca106725 12071 /******************* Bit definition for TIM_BDTR register *******************/
Kojto 122:f9eeca106725 12072 #define TIM_BDTR_DTG_Pos (0U)
Kojto 122:f9eeca106725 12073 #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 12074 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
Kojto 122:f9eeca106725 12075 #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 12076 #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 12077 #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 12078 #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 12079 #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 12080 #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 12081 #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 12082 #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 12083
Kojto 122:f9eeca106725 12084 #define TIM_BDTR_LOCK_Pos (8U)
Kojto 122:f9eeca106725 12085 #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 12086 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
Kojto 122:f9eeca106725 12087 #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 12088 #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 12089
Kojto 122:f9eeca106725 12090 #define TIM_BDTR_OSSI_Pos (10U)
Kojto 122:f9eeca106725 12091 #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 12092 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
Kojto 122:f9eeca106725 12093 #define TIM_BDTR_OSSR_Pos (11U)
Kojto 122:f9eeca106725 12094 #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 12095 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
Kojto 122:f9eeca106725 12096 #define TIM_BDTR_BKE_Pos (12U)
Kojto 122:f9eeca106725 12097 #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 12098 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break 1 */
Kojto 122:f9eeca106725 12099 #define TIM_BDTR_BKP_Pos (13U)
Kojto 122:f9eeca106725 12100 #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 12101 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break 1 */
Kojto 122:f9eeca106725 12102 #define TIM_BDTR_AOE_Pos (14U)
Kojto 122:f9eeca106725 12103 #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 12104 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
Kojto 122:f9eeca106725 12105 #define TIM_BDTR_MOE_Pos (15U)
Kojto 122:f9eeca106725 12106 #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 12107 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
Kojto 122:f9eeca106725 12108
Kojto 122:f9eeca106725 12109 #define TIM_BDTR_BKF_Pos (16U)
Kojto 122:f9eeca106725 12110 #define TIM_BDTR_BKF_Msk (0xFU << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */
Kojto 122:f9eeca106725 12111 #define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break 1 */
Kojto 122:f9eeca106725 12112 #define TIM_BDTR_BK2F_Pos (20U)
Kojto 122:f9eeca106725 12113 #define TIM_BDTR_BK2F_Msk (0xFU << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */
Kojto 122:f9eeca106725 12114 #define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break 2 */
Kojto 122:f9eeca106725 12115
Kojto 122:f9eeca106725 12116 #define TIM_BDTR_BK2E_Pos (24U)
Kojto 122:f9eeca106725 12117 #define TIM_BDTR_BK2E_Msk (0x1U << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 12118 #define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break 2 */
Kojto 122:f9eeca106725 12119 #define TIM_BDTR_BK2P_Pos (25U)
Kojto 122:f9eeca106725 12120 #define TIM_BDTR_BK2P_Msk (0x1U << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 12121 #define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break 2 */
Kojto 122:f9eeca106725 12122
Kojto 122:f9eeca106725 12123 /******************* Bit definition for TIM_DCR register ********************/
Kojto 122:f9eeca106725 12124 #define TIM_DCR_DBA_Pos (0U)
Kojto 122:f9eeca106725 12125 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
Kojto 122:f9eeca106725 12126 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
Kojto 122:f9eeca106725 12127 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 12128 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 12129 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 12130 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 12131 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 12132
Kojto 122:f9eeca106725 12133 #define TIM_DCR_DBL_Pos (8U)
Kojto 122:f9eeca106725 12134 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
Kojto 122:f9eeca106725 12135 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
Kojto 122:f9eeca106725 12136 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 12137 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 12138 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 12139 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 12140 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 12141
Kojto 122:f9eeca106725 12142 /******************* Bit definition for TIM_DMAR register *******************/
Kojto 122:f9eeca106725 12143 #define TIM_DMAR_DMAB_Pos (0U)
Kojto 122:f9eeca106725 12144 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 12145 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
Kojto 122:f9eeca106725 12146
Kojto 122:f9eeca106725 12147 /******************* Bit definition for TIM1_OR1 register *******************/
Kojto 122:f9eeca106725 12148 #define TIM1_OR1_ETR_ADC1_RMP_Pos (0U)
Kojto 122:f9eeca106725 12149 #define TIM1_OR1_ETR_ADC1_RMP_Msk (0x3U << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 12150 #define TIM1_OR1_ETR_ADC1_RMP TIM1_OR1_ETR_ADC1_RMP_Msk /*!<ETR_ADC1_RMP[1:0] bits (TIM1 ETR remap on ADC1) */
Kojto 122:f9eeca106725 12151 #define TIM1_OR1_ETR_ADC1_RMP_0 (0x1U << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 12152 #define TIM1_OR1_ETR_ADC1_RMP_1 (0x2U << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 12153
Kojto 122:f9eeca106725 12154 #define TIM1_OR1_TI1_RMP_Pos (4U)
Kojto 122:f9eeca106725 12155 #define TIM1_OR1_TI1_RMP_Msk (0x1U << TIM1_OR1_TI1_RMP_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 12156 #define TIM1_OR1_TI1_RMP TIM1_OR1_TI1_RMP_Msk /*!<TIM1 Input Capture 1 remap */
Kojto 122:f9eeca106725 12157
Kojto 122:f9eeca106725 12158 /******************* Bit definition for TIM1_OR2 register *******************/
Kojto 122:f9eeca106725 12159 #define TIM1_OR2_BKINE_Pos (0U)
Kojto 122:f9eeca106725 12160 #define TIM1_OR2_BKINE_Msk (0x1U << TIM1_OR2_BKINE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 12161 #define TIM1_OR2_BKINE TIM1_OR2_BKINE_Msk /*!<BRK BKIN input enable */
Kojto 122:f9eeca106725 12162 #define TIM1_OR2_BKCMP1E_Pos (1U)
Kojto 122:f9eeca106725 12163 #define TIM1_OR2_BKCMP1E_Msk (0x1U << TIM1_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 12164 #define TIM1_OR2_BKCMP1E TIM1_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
Kojto 122:f9eeca106725 12165 #define TIM1_OR2_BKCMP2E_Pos (2U)
Kojto 122:f9eeca106725 12166 #define TIM1_OR2_BKCMP2E_Msk (0x1U << TIM1_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 12167 #define TIM1_OR2_BKCMP2E TIM1_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
Kojto 122:f9eeca106725 12168 #define TIM1_OR2_BKINP_Pos (9U)
Kojto 122:f9eeca106725 12169 #define TIM1_OR2_BKINP_Msk (0x1U << TIM1_OR2_BKINP_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 12170 #define TIM1_OR2_BKINP TIM1_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
Kojto 122:f9eeca106725 12171 #define TIM1_OR2_BKCMP1P_Pos (10U)
Kojto 122:f9eeca106725 12172 #define TIM1_OR2_BKCMP1P_Msk (0x1U << TIM1_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 12173 #define TIM1_OR2_BKCMP1P TIM1_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
Kojto 122:f9eeca106725 12174 #define TIM1_OR2_BKCMP2P_Pos (11U)
Kojto 122:f9eeca106725 12175 #define TIM1_OR2_BKCMP2P_Msk (0x1U << TIM1_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 12176 #define TIM1_OR2_BKCMP2P TIM1_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
Kojto 122:f9eeca106725 12177
Kojto 122:f9eeca106725 12178 #define TIM1_OR2_ETRSEL_Pos (14U)
Kojto 122:f9eeca106725 12179 #define TIM1_OR2_ETRSEL_Msk (0x7U << TIM1_OR2_ETRSEL_Pos) /*!< 0x0001C000 */
Kojto 122:f9eeca106725 12180 #define TIM1_OR2_ETRSEL TIM1_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM1 ETR source selection) */
Kojto 122:f9eeca106725 12181 #define TIM1_OR2_ETRSEL_0 (0x1U << TIM1_OR2_ETRSEL_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 12182 #define TIM1_OR2_ETRSEL_1 (0x2U << TIM1_OR2_ETRSEL_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 12183 #define TIM1_OR2_ETRSEL_2 (0x4U << TIM1_OR2_ETRSEL_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 12184
Kojto 122:f9eeca106725 12185 /******************* Bit definition for TIM1_OR3 register *******************/
Kojto 122:f9eeca106725 12186 #define TIM1_OR3_BK2INE_Pos (0U)
Kojto 122:f9eeca106725 12187 #define TIM1_OR3_BK2INE_Msk (0x1U << TIM1_OR3_BK2INE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 12188 #define TIM1_OR3_BK2INE TIM1_OR3_BK2INE_Msk /*!<BRK2 BKIN2 input enable */
Kojto 122:f9eeca106725 12189 #define TIM1_OR3_BK2CMP1E_Pos (1U)
Kojto 122:f9eeca106725 12190 #define TIM1_OR3_BK2CMP1E_Msk (0x1U << TIM1_OR3_BK2CMP1E_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 12191 #define TIM1_OR3_BK2CMP1E TIM1_OR3_BK2CMP1E_Msk /*!<BRK2 COMP1 enable */
Kojto 122:f9eeca106725 12192 #define TIM1_OR3_BK2CMP2E_Pos (2U)
Kojto 122:f9eeca106725 12193 #define TIM1_OR3_BK2CMP2E_Msk (0x1U << TIM1_OR3_BK2CMP2E_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 12194 #define TIM1_OR3_BK2CMP2E TIM1_OR3_BK2CMP2E_Msk /*!<BRK2 COMP2 enable */
Kojto 122:f9eeca106725 12195 #define TIM1_OR3_BK2INP_Pos (9U)
Kojto 122:f9eeca106725 12196 #define TIM1_OR3_BK2INP_Msk (0x1U << TIM1_OR3_BK2INP_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 12197 #define TIM1_OR3_BK2INP TIM1_OR3_BK2INP_Msk /*!<BRK2 BKIN2 input polarity */
Kojto 122:f9eeca106725 12198 #define TIM1_OR3_BK2CMP1P_Pos (10U)
Kojto 122:f9eeca106725 12199 #define TIM1_OR3_BK2CMP1P_Msk (0x1U << TIM1_OR3_BK2CMP1P_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 12200 #define TIM1_OR3_BK2CMP1P TIM1_OR3_BK2CMP1P_Msk /*!<BRK2 COMP1 input polarity */
Kojto 122:f9eeca106725 12201 #define TIM1_OR3_BK2CMP2P_Pos (11U)
Kojto 122:f9eeca106725 12202 #define TIM1_OR3_BK2CMP2P_Msk (0x1U << TIM1_OR3_BK2CMP2P_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 12203 #define TIM1_OR3_BK2CMP2P TIM1_OR3_BK2CMP2P_Msk /*!<BRK2 COMP2 input polarity */
Kojto 122:f9eeca106725 12204
Kojto 122:f9eeca106725 12205
Kojto 122:f9eeca106725 12206 /******************* Bit definition for TIM2_OR1 register *******************/
Kojto 122:f9eeca106725 12207 #define TIM2_OR1_ITR1_RMP_Pos (0U)
Kojto 122:f9eeca106725 12208 #define TIM2_OR1_ITR1_RMP_Msk (0x1U << TIM2_OR1_ITR1_RMP_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 12209 #define TIM2_OR1_ITR1_RMP TIM2_OR1_ITR1_RMP_Msk /*!<TIM2 Internal trigger 1 remap */
Kojto 122:f9eeca106725 12210 #define TIM2_OR1_ETR1_RMP_Pos (1U)
Kojto 122:f9eeca106725 12211 #define TIM2_OR1_ETR1_RMP_Msk (0x1U << TIM2_OR1_ETR1_RMP_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 12212 #define TIM2_OR1_ETR1_RMP TIM2_OR1_ETR1_RMP_Msk /*!<TIM2 External trigger 1 remap */
Kojto 122:f9eeca106725 12213
Kojto 122:f9eeca106725 12214 #define TIM2_OR1_TI4_RMP_Pos (2U)
Kojto 122:f9eeca106725 12215 #define TIM2_OR1_TI4_RMP_Msk (0x3U << TIM2_OR1_TI4_RMP_Pos) /*!< 0x0000000C */
Kojto 122:f9eeca106725 12216 #define TIM2_OR1_TI4_RMP TIM2_OR1_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM2 Input Capture 4 remap) */
Kojto 122:f9eeca106725 12217 #define TIM2_OR1_TI4_RMP_0 (0x1U << TIM2_OR1_TI4_RMP_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 12218 #define TIM2_OR1_TI4_RMP_1 (0x2U << TIM2_OR1_TI4_RMP_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 12219
Kojto 122:f9eeca106725 12220 /******************* Bit definition for TIM2_OR2 register *******************/
Kojto 122:f9eeca106725 12221 #define TIM2_OR2_ETRSEL_Pos (14U)
Kojto 122:f9eeca106725 12222 #define TIM2_OR2_ETRSEL_Msk (0x7U << TIM2_OR2_ETRSEL_Pos) /*!< 0x0001C000 */
Kojto 122:f9eeca106725 12223 #define TIM2_OR2_ETRSEL TIM2_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM2 ETR source selection) */
Kojto 122:f9eeca106725 12224 #define TIM2_OR2_ETRSEL_0 (0x1U << TIM2_OR2_ETRSEL_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 12225 #define TIM2_OR2_ETRSEL_1 (0x2U << TIM2_OR2_ETRSEL_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 12226 #define TIM2_OR2_ETRSEL_2 (0x4U << TIM2_OR2_ETRSEL_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 12227
Kojto 122:f9eeca106725 12228
Kojto 122:f9eeca106725 12229 /******************* Bit definition for TIM15_OR1 register ******************/
Kojto 122:f9eeca106725 12230 #define TIM15_OR1_TI1_RMP_Pos (0U)
Kojto 122:f9eeca106725 12231 #define TIM15_OR1_TI1_RMP_Msk (0x1U << TIM15_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 12232 #define TIM15_OR1_TI1_RMP TIM15_OR1_TI1_RMP_Msk /*!<TIM15 Input Capture 1 remap */
Kojto 122:f9eeca106725 12233
Kojto 122:f9eeca106725 12234 #define TIM15_OR1_ENCODER_MODE_Pos (1U)
Kojto 122:f9eeca106725 12235 #define TIM15_OR1_ENCODER_MODE_Msk (0x3U << TIM15_OR1_ENCODER_MODE_Pos) /*!< 0x00000006 */
Kojto 122:f9eeca106725 12236 #define TIM15_OR1_ENCODER_MODE TIM15_OR1_ENCODER_MODE_Msk /*!<ENCODER_MODE[1:0] bits (TIM15 Encoder mode) */
Kojto 122:f9eeca106725 12237 #define TIM15_OR1_ENCODER_MODE_0 (0x1U << TIM15_OR1_ENCODER_MODE_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 12238 #define TIM15_OR1_ENCODER_MODE_1 (0x2U << TIM15_OR1_ENCODER_MODE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 12239
Kojto 122:f9eeca106725 12240 /******************* Bit definition for TIM15_OR2 register ******************/
Kojto 122:f9eeca106725 12241 #define TIM15_OR2_BKINE_Pos (0U)
Kojto 122:f9eeca106725 12242 #define TIM15_OR2_BKINE_Msk (0x1U << TIM15_OR2_BKINE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 12243 #define TIM15_OR2_BKINE TIM15_OR2_BKINE_Msk /*!<BRK BKIN input enable */
Kojto 122:f9eeca106725 12244 #define TIM15_OR2_BKCMP1E_Pos (1U)
Kojto 122:f9eeca106725 12245 #define TIM15_OR2_BKCMP1E_Msk (0x1U << TIM15_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 12246 #define TIM15_OR2_BKCMP1E TIM15_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
Kojto 122:f9eeca106725 12247 #define TIM15_OR2_BKCMP2E_Pos (2U)
Kojto 122:f9eeca106725 12248 #define TIM15_OR2_BKCMP2E_Msk (0x1U << TIM15_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 12249 #define TIM15_OR2_BKCMP2E TIM15_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
Kojto 122:f9eeca106725 12250 #define TIM15_OR2_BKINP_Pos (9U)
Kojto 122:f9eeca106725 12251 #define TIM15_OR2_BKINP_Msk (0x1U << TIM15_OR2_BKINP_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 12252 #define TIM15_OR2_BKINP TIM15_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
Kojto 122:f9eeca106725 12253 #define TIM15_OR2_BKCMP1P_Pos (10U)
Kojto 122:f9eeca106725 12254 #define TIM15_OR2_BKCMP1P_Msk (0x1U << TIM15_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 12255 #define TIM15_OR2_BKCMP1P TIM15_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
Kojto 122:f9eeca106725 12256 #define TIM15_OR2_BKCMP2P_Pos (11U)
Kojto 122:f9eeca106725 12257 #define TIM15_OR2_BKCMP2P_Msk (0x1U << TIM15_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 12258 #define TIM15_OR2_BKCMP2P TIM15_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
Kojto 122:f9eeca106725 12259
Kojto 122:f9eeca106725 12260 /******************* Bit definition for TIM16_OR1 register ******************/
Kojto 122:f9eeca106725 12261 #define TIM16_OR1_TI1_RMP_Pos (0U)
Kojto 122:f9eeca106725 12262 #define TIM16_OR1_TI1_RMP_Msk (0x7U << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000007 */
Kojto 122:f9eeca106725 12263 #define TIM16_OR1_TI1_RMP TIM16_OR1_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM16 Input Capture 1 remap) */
Kojto 122:f9eeca106725 12264 #define TIM16_OR1_TI1_RMP_0 (0x1U << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 12265 #define TIM16_OR1_TI1_RMP_1 (0x2U << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 12266 #define TIM16_OR1_TI1_RMP_2 (0x4U << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 12267
Kojto 122:f9eeca106725 12268 /******************* Bit definition for TIM16_OR2 register ******************/
Kojto 122:f9eeca106725 12269 #define TIM16_OR2_BKINE_Pos (0U)
Kojto 122:f9eeca106725 12270 #define TIM16_OR2_BKINE_Msk (0x1U << TIM16_OR2_BKINE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 12271 #define TIM16_OR2_BKINE TIM16_OR2_BKINE_Msk /*!<BRK BKIN input enable */
Kojto 122:f9eeca106725 12272 #define TIM16_OR2_BKCMP1E_Pos (1U)
Kojto 122:f9eeca106725 12273 #define TIM16_OR2_BKCMP1E_Msk (0x1U << TIM16_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 12274 #define TIM16_OR2_BKCMP1E TIM16_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
Kojto 122:f9eeca106725 12275 #define TIM16_OR2_BKCMP2E_Pos (2U)
Kojto 122:f9eeca106725 12276 #define TIM16_OR2_BKCMP2E_Msk (0x1U << TIM16_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 12277 #define TIM16_OR2_BKCMP2E TIM16_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
Kojto 122:f9eeca106725 12278 #define TIM16_OR2_BKINP_Pos (9U)
Kojto 122:f9eeca106725 12279 #define TIM16_OR2_BKINP_Msk (0x1U << TIM16_OR2_BKINP_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 12280 #define TIM16_OR2_BKINP TIM16_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
Kojto 122:f9eeca106725 12281 #define TIM16_OR2_BKCMP1P_Pos (10U)
Kojto 122:f9eeca106725 12282 #define TIM16_OR2_BKCMP1P_Msk (0x1U << TIM16_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 12283 #define TIM16_OR2_BKCMP1P TIM16_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
Kojto 122:f9eeca106725 12284 #define TIM16_OR2_BKCMP2P_Pos (11U)
Kojto 122:f9eeca106725 12285 #define TIM16_OR2_BKCMP2P_Msk (0x1U << TIM16_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 12286 #define TIM16_OR2_BKCMP2P TIM16_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
Kojto 122:f9eeca106725 12287
Kojto 122:f9eeca106725 12288
Kojto 122:f9eeca106725 12289 /******************************************************************************/
Kojto 122:f9eeca106725 12290 /* */
Kojto 122:f9eeca106725 12291 /* Low Power Timer (LPTTIM) */
Kojto 122:f9eeca106725 12292 /* */
Kojto 122:f9eeca106725 12293 /******************************************************************************/
Kojto 122:f9eeca106725 12294 /****************** Bit definition for LPTIM_ISR register *******************/
Kojto 122:f9eeca106725 12295 #define LPTIM_ISR_CMPM_Pos (0U)
Kojto 122:f9eeca106725 12296 #define LPTIM_ISR_CMPM_Msk (0x1U << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 12297 #define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
Kojto 122:f9eeca106725 12298 #define LPTIM_ISR_ARRM_Pos (1U)
Kojto 122:f9eeca106725 12299 #define LPTIM_ISR_ARRM_Msk (0x1U << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 12300 #define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
Kojto 122:f9eeca106725 12301 #define LPTIM_ISR_EXTTRIG_Pos (2U)
Kojto 122:f9eeca106725 12302 #define LPTIM_ISR_EXTTRIG_Msk (0x1U << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 12303 #define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
Kojto 122:f9eeca106725 12304 #define LPTIM_ISR_CMPOK_Pos (3U)
Kojto 122:f9eeca106725 12305 #define LPTIM_ISR_CMPOK_Msk (0x1U << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 12306 #define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
Kojto 122:f9eeca106725 12307 #define LPTIM_ISR_ARROK_Pos (4U)
Kojto 122:f9eeca106725 12308 #define LPTIM_ISR_ARROK_Msk (0x1U << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 12309 #define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
Kojto 122:f9eeca106725 12310 #define LPTIM_ISR_UP_Pos (5U)
Kojto 122:f9eeca106725 12311 #define LPTIM_ISR_UP_Msk (0x1U << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 12312 #define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
Kojto 122:f9eeca106725 12313 #define LPTIM_ISR_DOWN_Pos (6U)
Kojto 122:f9eeca106725 12314 #define LPTIM_ISR_DOWN_Msk (0x1U << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 12315 #define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
Kojto 122:f9eeca106725 12316
Kojto 122:f9eeca106725 12317 /****************** Bit definition for LPTIM_ICR register *******************/
Kojto 122:f9eeca106725 12318 #define LPTIM_ICR_CMPMCF_Pos (0U)
Kojto 122:f9eeca106725 12319 #define LPTIM_ICR_CMPMCF_Msk (0x1U << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 12320 #define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
Kojto 122:f9eeca106725 12321 #define LPTIM_ICR_ARRMCF_Pos (1U)
Kojto 122:f9eeca106725 12322 #define LPTIM_ICR_ARRMCF_Msk (0x1U << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 12323 #define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
Kojto 122:f9eeca106725 12324 #define LPTIM_ICR_EXTTRIGCF_Pos (2U)
Kojto 122:f9eeca106725 12325 #define LPTIM_ICR_EXTTRIGCF_Msk (0x1U << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 12326 #define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
Kojto 122:f9eeca106725 12327 #define LPTIM_ICR_CMPOKCF_Pos (3U)
Kojto 122:f9eeca106725 12328 #define LPTIM_ICR_CMPOKCF_Msk (0x1U << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 12329 #define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
Kojto 122:f9eeca106725 12330 #define LPTIM_ICR_ARROKCF_Pos (4U)
Kojto 122:f9eeca106725 12331 #define LPTIM_ICR_ARROKCF_Msk (0x1U << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 12332 #define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
Kojto 122:f9eeca106725 12333 #define LPTIM_ICR_UPCF_Pos (5U)
Kojto 122:f9eeca106725 12334 #define LPTIM_ICR_UPCF_Msk (0x1U << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 12335 #define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
Kojto 122:f9eeca106725 12336 #define LPTIM_ICR_DOWNCF_Pos (6U)
Kojto 122:f9eeca106725 12337 #define LPTIM_ICR_DOWNCF_Msk (0x1U << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 12338 #define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
Kojto 122:f9eeca106725 12339
Kojto 122:f9eeca106725 12340 /****************** Bit definition for LPTIM_IER register ********************/
Kojto 122:f9eeca106725 12341 #define LPTIM_IER_CMPMIE_Pos (0U)
Kojto 122:f9eeca106725 12342 #define LPTIM_IER_CMPMIE_Msk (0x1U << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 12343 #define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
Kojto 122:f9eeca106725 12344 #define LPTIM_IER_ARRMIE_Pos (1U)
Kojto 122:f9eeca106725 12345 #define LPTIM_IER_ARRMIE_Msk (0x1U << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 12346 #define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
Kojto 122:f9eeca106725 12347 #define LPTIM_IER_EXTTRIGIE_Pos (2U)
Kojto 122:f9eeca106725 12348 #define LPTIM_IER_EXTTRIGIE_Msk (0x1U << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 12349 #define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
Kojto 122:f9eeca106725 12350 #define LPTIM_IER_CMPOKIE_Pos (3U)
Kojto 122:f9eeca106725 12351 #define LPTIM_IER_CMPOKIE_Msk (0x1U << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 12352 #define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
Kojto 122:f9eeca106725 12353 #define LPTIM_IER_ARROKIE_Pos (4U)
Kojto 122:f9eeca106725 12354 #define LPTIM_IER_ARROKIE_Msk (0x1U << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 12355 #define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
Kojto 122:f9eeca106725 12356 #define LPTIM_IER_UPIE_Pos (5U)
Kojto 122:f9eeca106725 12357 #define LPTIM_IER_UPIE_Msk (0x1U << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 12358 #define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
Kojto 122:f9eeca106725 12359 #define LPTIM_IER_DOWNIE_Pos (6U)
Kojto 122:f9eeca106725 12360 #define LPTIM_IER_DOWNIE_Msk (0x1U << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 12361 #define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
Kojto 122:f9eeca106725 12362
Kojto 122:f9eeca106725 12363 /****************** Bit definition for LPTIM_CFGR register *******************/
Kojto 122:f9eeca106725 12364 #define LPTIM_CFGR_CKSEL_Pos (0U)
Kojto 122:f9eeca106725 12365 #define LPTIM_CFGR_CKSEL_Msk (0x1U << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 12366 #define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
Kojto 122:f9eeca106725 12367
Kojto 122:f9eeca106725 12368 #define LPTIM_CFGR_CKPOL_Pos (1U)
Kojto 122:f9eeca106725 12369 #define LPTIM_CFGR_CKPOL_Msk (0x3U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
Kojto 122:f9eeca106725 12370 #define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
Kojto 122:f9eeca106725 12371 #define LPTIM_CFGR_CKPOL_0 (0x1U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 12372 #define LPTIM_CFGR_CKPOL_1 (0x2U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 12373
Kojto 122:f9eeca106725 12374 #define LPTIM_CFGR_CKFLT_Pos (3U)
Kojto 122:f9eeca106725 12375 #define LPTIM_CFGR_CKFLT_Msk (0x3U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
Kojto 122:f9eeca106725 12376 #define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
Kojto 122:f9eeca106725 12377 #define LPTIM_CFGR_CKFLT_0 (0x1U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 12378 #define LPTIM_CFGR_CKFLT_1 (0x2U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 12379
Kojto 122:f9eeca106725 12380 #define LPTIM_CFGR_TRGFLT_Pos (6U)
Kojto 122:f9eeca106725 12381 #define LPTIM_CFGR_TRGFLT_Msk (0x3U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
Kojto 122:f9eeca106725 12382 #define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
Kojto 122:f9eeca106725 12383 #define LPTIM_CFGR_TRGFLT_0 (0x1U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 12384 #define LPTIM_CFGR_TRGFLT_1 (0x2U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 12385
Kojto 122:f9eeca106725 12386 #define LPTIM_CFGR_PRESC_Pos (9U)
Kojto 122:f9eeca106725 12387 #define LPTIM_CFGR_PRESC_Msk (0x7U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
Kojto 122:f9eeca106725 12388 #define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
Kojto 122:f9eeca106725 12389 #define LPTIM_CFGR_PRESC_0 (0x1U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 12390 #define LPTIM_CFGR_PRESC_1 (0x2U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 12391 #define LPTIM_CFGR_PRESC_2 (0x4U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 12392
Kojto 122:f9eeca106725 12393 #define LPTIM_CFGR_TRIGSEL_Pos (13U)
Kojto 122:f9eeca106725 12394 #define LPTIM_CFGR_TRIGSEL_Msk (0x7U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
Kojto 122:f9eeca106725 12395 #define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
Kojto 122:f9eeca106725 12396 #define LPTIM_CFGR_TRIGSEL_0 (0x1U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 12397 #define LPTIM_CFGR_TRIGSEL_1 (0x2U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 12398 #define LPTIM_CFGR_TRIGSEL_2 (0x4U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 12399
Kojto 122:f9eeca106725 12400 #define LPTIM_CFGR_TRIGEN_Pos (17U)
Kojto 122:f9eeca106725 12401 #define LPTIM_CFGR_TRIGEN_Msk (0x3U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
Kojto 122:f9eeca106725 12402 #define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
Kojto 122:f9eeca106725 12403 #define LPTIM_CFGR_TRIGEN_0 (0x1U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 12404 #define LPTIM_CFGR_TRIGEN_1 (0x2U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 12405
Kojto 122:f9eeca106725 12406 #define LPTIM_CFGR_TIMOUT_Pos (19U)
Kojto 122:f9eeca106725 12407 #define LPTIM_CFGR_TIMOUT_Msk (0x1U << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 12408 #define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
Kojto 122:f9eeca106725 12409 #define LPTIM_CFGR_WAVE_Pos (20U)
Kojto 122:f9eeca106725 12410 #define LPTIM_CFGR_WAVE_Msk (0x1U << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 12411 #define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
Kojto 122:f9eeca106725 12412 #define LPTIM_CFGR_WAVPOL_Pos (21U)
Kojto 122:f9eeca106725 12413 #define LPTIM_CFGR_WAVPOL_Msk (0x1U << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 12414 #define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
Kojto 122:f9eeca106725 12415 #define LPTIM_CFGR_PRELOAD_Pos (22U)
Kojto 122:f9eeca106725 12416 #define LPTIM_CFGR_PRELOAD_Msk (0x1U << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 12417 #define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
Kojto 122:f9eeca106725 12418 #define LPTIM_CFGR_COUNTMODE_Pos (23U)
Kojto 122:f9eeca106725 12419 #define LPTIM_CFGR_COUNTMODE_Msk (0x1U << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 12420 #define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
Kojto 122:f9eeca106725 12421 #define LPTIM_CFGR_ENC_Pos (24U)
Kojto 122:f9eeca106725 12422 #define LPTIM_CFGR_ENC_Msk (0x1U << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 12423 #define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
Kojto 122:f9eeca106725 12424
Kojto 122:f9eeca106725 12425 /****************** Bit definition for LPTIM_CR register ********************/
Kojto 122:f9eeca106725 12426 #define LPTIM_CR_ENABLE_Pos (0U)
Kojto 122:f9eeca106725 12427 #define LPTIM_CR_ENABLE_Msk (0x1U << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 12428 #define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
Kojto 122:f9eeca106725 12429 #define LPTIM_CR_SNGSTRT_Pos (1U)
Kojto 122:f9eeca106725 12430 #define LPTIM_CR_SNGSTRT_Msk (0x1U << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 12431 #define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
Kojto 122:f9eeca106725 12432 #define LPTIM_CR_CNTSTRT_Pos (2U)
Kojto 122:f9eeca106725 12433 #define LPTIM_CR_CNTSTRT_Msk (0x1U << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 12434 #define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
Kojto 122:f9eeca106725 12435
Kojto 122:f9eeca106725 12436 /****************** Bit definition for LPTIM_CMP register *******************/
Kojto 122:f9eeca106725 12437 #define LPTIM_CMP_CMP_Pos (0U)
Kojto 122:f9eeca106725 12438 #define LPTIM_CMP_CMP_Msk (0xFFFFU << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 12439 #define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
Kojto 122:f9eeca106725 12440
Kojto 122:f9eeca106725 12441 /****************** Bit definition for LPTIM_ARR register *******************/
Kojto 122:f9eeca106725 12442 #define LPTIM_ARR_ARR_Pos (0U)
Kojto 122:f9eeca106725 12443 #define LPTIM_ARR_ARR_Msk (0xFFFFU << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 12444 #define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
Kojto 122:f9eeca106725 12445
Kojto 122:f9eeca106725 12446 /****************** Bit definition for LPTIM_CNT register *******************/
Kojto 122:f9eeca106725 12447 #define LPTIM_CNT_CNT_Pos (0U)
Kojto 122:f9eeca106725 12448 #define LPTIM_CNT_CNT_Msk (0xFFFFU << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 12449 #define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
Kojto 122:f9eeca106725 12450
Kojto 122:f9eeca106725 12451 /****************** Bit definition for LPTIM_OR register *******************/
Kojto 122:f9eeca106725 12452 #define LPTIM_OR_OR_Pos (0U)
Kojto 122:f9eeca106725 12453 #define LPTIM_OR_OR_Msk (0x3U << LPTIM_OR_OR_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 12454 #define LPTIM_OR_OR LPTIM_OR_OR_Msk /*!< LPTIMER[1:0] bits (Remap selection) */
Kojto 122:f9eeca106725 12455 #define LPTIM_OR_OR_0 (0x1U << LPTIM_OR_OR_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 12456 #define LPTIM_OR_OR_1 (0x2U << LPTIM_OR_OR_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 12457
Kojto 122:f9eeca106725 12458 /******************************************************************************/
Kojto 122:f9eeca106725 12459 /* */
Kojto 122:f9eeca106725 12460 /* Analog Comparators (COMP) */
Kojto 122:f9eeca106725 12461 /* */
Kojto 122:f9eeca106725 12462 /******************************************************************************/
Kojto 122:f9eeca106725 12463 /********************** Bit definition for COMP_CSR register ****************/
Kojto 122:f9eeca106725 12464 #define COMP_CSR_EN_Pos (0U)
Kojto 122:f9eeca106725 12465 #define COMP_CSR_EN_Msk (0x1U << COMP_CSR_EN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 12466 #define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */
Kojto 122:f9eeca106725 12467
Kojto 122:f9eeca106725 12468 #define COMP_CSR_PWRMODE_Pos (2U)
Kojto 122:f9eeca106725 12469 #define COMP_CSR_PWRMODE_Msk (0x3U << COMP_CSR_PWRMODE_Pos) /*!< 0x0000000C */
Kojto 122:f9eeca106725 12470 #define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk /*!< Comparator power mode */
Kojto 122:f9eeca106725 12471 #define COMP_CSR_PWRMODE_0 (0x1U << COMP_CSR_PWRMODE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 12472 #define COMP_CSR_PWRMODE_1 (0x2U << COMP_CSR_PWRMODE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 12473
Kojto 122:f9eeca106725 12474 #define COMP_CSR_INMSEL_Pos (4U)
Kojto 122:f9eeca106725 12475 #define COMP_CSR_INMSEL_Msk (0x7U << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */
Kojto 122:f9eeca106725 12476 #define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */
Kojto 122:f9eeca106725 12477 #define COMP_CSR_INMSEL_0 (0x1U << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 12478 #define COMP_CSR_INMSEL_1 (0x2U << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 12479 #define COMP_CSR_INMSEL_2 (0x4U << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 12480
Kojto 122:f9eeca106725 12481 #define COMP_CSR_INPSEL_Pos (7U)
Kojto 122:f9eeca106725 12482 #define COMP_CSR_INPSEL_Msk (0x3U << COMP_CSR_INPSEL_Pos) /*!< 0x00000180 */
Kojto 122:f9eeca106725 12483 #define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */
Kojto 122:f9eeca106725 12484 #define COMP_CSR_INPSEL_0 (0x1U << COMP_CSR_INPSEL_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 12485 #define COMP_CSR_INPSEL_1 (0x2U << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 12486
Kojto 122:f9eeca106725 12487 #define COMP_CSR_WINMODE_Pos (9U)
Kojto 122:f9eeca106725 12488 #define COMP_CSR_WINMODE_Msk (0x1U << COMP_CSR_WINMODE_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 12489 #define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
Kojto 122:f9eeca106725 12490
Kojto 122:f9eeca106725 12491 #define COMP_CSR_POLARITY_Pos (15U)
Kojto 122:f9eeca106725 12492 #define COMP_CSR_POLARITY_Msk (0x1U << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 12493 #define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */
Kojto 122:f9eeca106725 12494
Kojto 122:f9eeca106725 12495 #define COMP_CSR_HYST_Pos (16U)
Kojto 122:f9eeca106725 12496 #define COMP_CSR_HYST_Msk (0x3U << COMP_CSR_HYST_Pos) /*!< 0x00030000 */
Kojto 122:f9eeca106725 12497 #define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */
Kojto 122:f9eeca106725 12498 #define COMP_CSR_HYST_0 (0x1U << COMP_CSR_HYST_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 12499 #define COMP_CSR_HYST_1 (0x2U << COMP_CSR_HYST_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 12500
Kojto 122:f9eeca106725 12501 #define COMP_CSR_BLANKING_Pos (18U)
Kojto 122:f9eeca106725 12502 #define COMP_CSR_BLANKING_Msk (0x7U << COMP_CSR_BLANKING_Pos) /*!< 0x001C0000 */
Kojto 122:f9eeca106725 12503 #define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */
Kojto 122:f9eeca106725 12504 #define COMP_CSR_BLANKING_0 (0x1U << COMP_CSR_BLANKING_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 12505 #define COMP_CSR_BLANKING_1 (0x2U << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 12506 #define COMP_CSR_BLANKING_2 (0x4U << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 12507
Kojto 122:f9eeca106725 12508 #define COMP_CSR_BRGEN_Pos (22U)
Kojto 122:f9eeca106725 12509 #define COMP_CSR_BRGEN_Msk (0x1U << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 12510 #define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator voltage scaler enable */
Kojto 122:f9eeca106725 12511 #define COMP_CSR_SCALEN_Pos (23U)
Kojto 122:f9eeca106725 12512 #define COMP_CSR_SCALEN_Msk (0x1U << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 12513 #define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator scaler bridge enable */
Kojto 122:f9eeca106725 12514
Kojto 122:f9eeca106725 12515 #define COMP_CSR_INMESEL_Pos (25U)
Kojto 122:f9eeca106725 12516 #define COMP_CSR_INMESEL_Msk (0x3U << COMP_CSR_INMESEL_Pos) /*!< 0x06000000 */
Kojto 122:f9eeca106725 12517 #define COMP_CSR_INMESEL COMP_CSR_INMESEL_Msk /*!< Comparator inverting input (minus) extended selection */
Kojto 122:f9eeca106725 12518 #define COMP_CSR_INMESEL_0 (0x1U << COMP_CSR_INMESEL_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 12519 #define COMP_CSR_INMESEL_1 (0x2U << COMP_CSR_INMESEL_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 12520
Kojto 122:f9eeca106725 12521 #define COMP_CSR_VALUE_Pos (30U)
Kojto 122:f9eeca106725 12522 #define COMP_CSR_VALUE_Msk (0x1U << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 12523 #define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */
Kojto 122:f9eeca106725 12524
Kojto 122:f9eeca106725 12525 #define COMP_CSR_LOCK_Pos (31U)
Kojto 122:f9eeca106725 12526 #define COMP_CSR_LOCK_Msk (0x1U << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 12527 #define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */
Kojto 122:f9eeca106725 12528
Kojto 122:f9eeca106725 12529 /******************************************************************************/
Kojto 122:f9eeca106725 12530 /* */
Kojto 122:f9eeca106725 12531 /* Operational Amplifier (OPAMP) */
Kojto 122:f9eeca106725 12532 /* */
Kojto 122:f9eeca106725 12533 /******************************************************************************/
Kojto 122:f9eeca106725 12534 /********************* Bit definition for OPAMPx_CSR register ***************/
Kojto 122:f9eeca106725 12535 #define OPAMP_CSR_OPAMPxEN_Pos (0U)
Kojto 122:f9eeca106725 12536 #define OPAMP_CSR_OPAMPxEN_Msk (0x1U << OPAMP_CSR_OPAMPxEN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 12537 #define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk /*!< OPAMP enable */
Kojto 122:f9eeca106725 12538 #define OPAMP_CSR_OPALPM_Pos (1U)
Kojto 122:f9eeca106725 12539 #define OPAMP_CSR_OPALPM_Msk (0x1U << OPAMP_CSR_OPALPM_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 12540 #define OPAMP_CSR_OPALPM OPAMP_CSR_OPALPM_Msk /*!< Operational amplifier Low Power Mode */
Kojto 122:f9eeca106725 12541
Kojto 122:f9eeca106725 12542 #define OPAMP_CSR_OPAMODE_Pos (2U)
Kojto 122:f9eeca106725 12543 #define OPAMP_CSR_OPAMODE_Msk (0x3U << OPAMP_CSR_OPAMODE_Pos) /*!< 0x0000000C */
Kojto 122:f9eeca106725 12544 #define OPAMP_CSR_OPAMODE OPAMP_CSR_OPAMODE_Msk /*!< Operational amplifier PGA mode */
Kojto 122:f9eeca106725 12545 #define OPAMP_CSR_OPAMODE_0 (0x1U << OPAMP_CSR_OPAMODE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 12546 #define OPAMP_CSR_OPAMODE_1 (0x2U << OPAMP_CSR_OPAMODE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 12547
Kojto 122:f9eeca106725 12548 #define OPAMP_CSR_PGGAIN_Pos (4U)
Kojto 122:f9eeca106725 12549 #define OPAMP_CSR_PGGAIN_Msk (0x3U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00000030 */
Kojto 122:f9eeca106725 12550 #define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk /*!< Operational amplifier Programmable amplifier gain value */
Kojto 122:f9eeca106725 12551 #define OPAMP_CSR_PGGAIN_0 (0x1U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 12552 #define OPAMP_CSR_PGGAIN_1 (0x2U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 12553
Kojto 122:f9eeca106725 12554 #define OPAMP_CSR_VMSEL_Pos (8U)
Kojto 122:f9eeca106725 12555 #define OPAMP_CSR_VMSEL_Msk (0x3U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 12556 #define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk /*!< Inverting input selection */
Kojto 122:f9eeca106725 12557 #define OPAMP_CSR_VMSEL_0 (0x1U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 12558 #define OPAMP_CSR_VMSEL_1 (0x2U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 12559
Kojto 122:f9eeca106725 12560 #define OPAMP_CSR_VPSEL_Pos (10U)
Kojto 122:f9eeca106725 12561 #define OPAMP_CSR_VPSEL_Msk (0x1U << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 12562 #define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk /*!< Non inverted input selection */
Kojto 122:f9eeca106725 12563 #define OPAMP_CSR_CALON_Pos (12U)
Kojto 122:f9eeca106725 12564 #define OPAMP_CSR_CALON_Msk (0x1U << OPAMP_CSR_CALON_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 12565 #define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */
Kojto 122:f9eeca106725 12566 #define OPAMP_CSR_CALSEL_Pos (13U)
Kojto 122:f9eeca106725 12567 #define OPAMP_CSR_CALSEL_Msk (0x1U << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 12568 #define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */
Kojto 122:f9eeca106725 12569 #define OPAMP_CSR_USERTRIM_Pos (14U)
Kojto 122:f9eeca106725 12570 #define OPAMP_CSR_USERTRIM_Msk (0x1U << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 12571 #define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */
Kojto 122:f9eeca106725 12572 #define OPAMP_CSR_CALOUT_Pos (15U)
Kojto 122:f9eeca106725 12573 #define OPAMP_CSR_CALOUT_Msk (0x1U << OPAMP_CSR_CALOUT_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 12574 #define OPAMP_CSR_CALOUT OPAMP_CSR_CALOUT_Msk /*!< Operational amplifier1 calibration output */
Kojto 122:f9eeca106725 12575
Kojto 122:f9eeca106725 12576 /********************* Bit definition for OPAMP1_CSR register ***************/
Kojto 122:f9eeca106725 12577 #define OPAMP1_CSR_OPAEN_Pos (0U)
Kojto 122:f9eeca106725 12578 #define OPAMP1_CSR_OPAEN_Msk (0x1U << OPAMP1_CSR_OPAEN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 12579 #define OPAMP1_CSR_OPAEN OPAMP1_CSR_OPAEN_Msk /*!< Operational amplifier1 Enable */
Kojto 122:f9eeca106725 12580 #define OPAMP1_CSR_OPALPM_Pos (1U)
Kojto 122:f9eeca106725 12581 #define OPAMP1_CSR_OPALPM_Msk (0x1U << OPAMP1_CSR_OPALPM_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 12582 #define OPAMP1_CSR_OPALPM OPAMP1_CSR_OPALPM_Msk /*!< Operational amplifier1 Low Power Mode */
Kojto 122:f9eeca106725 12583
Kojto 122:f9eeca106725 12584 #define OPAMP1_CSR_OPAMODE_Pos (2U)
Kojto 122:f9eeca106725 12585 #define OPAMP1_CSR_OPAMODE_Msk (0x3U << OPAMP1_CSR_OPAMODE_Pos) /*!< 0x0000000C */
Kojto 122:f9eeca106725 12586 #define OPAMP1_CSR_OPAMODE OPAMP1_CSR_OPAMODE_Msk /*!< Operational amplifier1 PGA mode */
Kojto 122:f9eeca106725 12587 #define OPAMP1_CSR_OPAMODE_0 (0x1U << OPAMP1_CSR_OPAMODE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 12588 #define OPAMP1_CSR_OPAMODE_1 (0x2U << OPAMP1_CSR_OPAMODE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 12589
Kojto 122:f9eeca106725 12590 #define OPAMP1_CSR_PGAGAIN_Pos (4U)
Kojto 122:f9eeca106725 12591 #define OPAMP1_CSR_PGAGAIN_Msk (0x3U << OPAMP1_CSR_PGAGAIN_Pos) /*!< 0x00000030 */
Kojto 122:f9eeca106725 12592 #define OPAMP1_CSR_PGAGAIN OPAMP1_CSR_PGAGAIN_Msk /*!< Operational amplifier1 Programmable amplifier gain value */
Kojto 122:f9eeca106725 12593 #define OPAMP1_CSR_PGAGAIN_0 (0x1U << OPAMP1_CSR_PGAGAIN_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 12594 #define OPAMP1_CSR_PGAGAIN_1 (0x2U << OPAMP1_CSR_PGAGAIN_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 12595
Kojto 122:f9eeca106725 12596 #define OPAMP1_CSR_VMSEL_Pos (8U)
Kojto 122:f9eeca106725 12597 #define OPAMP1_CSR_VMSEL_Msk (0x3U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 12598 #define OPAMP1_CSR_VMSEL OPAMP1_CSR_VMSEL_Msk /*!< Inverting input selection */
Kojto 122:f9eeca106725 12599 #define OPAMP1_CSR_VMSEL_0 (0x1U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 12600 #define OPAMP1_CSR_VMSEL_1 (0x2U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 12601
Kojto 122:f9eeca106725 12602 #define OPAMP1_CSR_VPSEL_Pos (10U)
Kojto 122:f9eeca106725 12603 #define OPAMP1_CSR_VPSEL_Msk (0x1U << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 12604 #define OPAMP1_CSR_VPSEL OPAMP1_CSR_VPSEL_Msk /*!< Non inverted input selection */
Kojto 122:f9eeca106725 12605 #define OPAMP1_CSR_CALON_Pos (12U)
Kojto 122:f9eeca106725 12606 #define OPAMP1_CSR_CALON_Msk (0x1U << OPAMP1_CSR_CALON_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 12607 #define OPAMP1_CSR_CALON OPAMP1_CSR_CALON_Msk /*!< Calibration mode enable */
Kojto 122:f9eeca106725 12608 #define OPAMP1_CSR_CALSEL_Pos (13U)
Kojto 122:f9eeca106725 12609 #define OPAMP1_CSR_CALSEL_Msk (0x1U << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 12610 #define OPAMP1_CSR_CALSEL OPAMP1_CSR_CALSEL_Msk /*!< Calibration selection */
Kojto 122:f9eeca106725 12611 #define OPAMP1_CSR_USERTRIM_Pos (14U)
Kojto 122:f9eeca106725 12612 #define OPAMP1_CSR_USERTRIM_Msk (0x1U << OPAMP1_CSR_USERTRIM_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 12613 #define OPAMP1_CSR_USERTRIM OPAMP1_CSR_USERTRIM_Msk /*!< User trimming enable */
Kojto 122:f9eeca106725 12614 #define OPAMP1_CSR_CALOUT_Pos (15U)
Kojto 122:f9eeca106725 12615 #define OPAMP1_CSR_CALOUT_Msk (0x1U << OPAMP1_CSR_CALOUT_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 12616 #define OPAMP1_CSR_CALOUT OPAMP1_CSR_CALOUT_Msk /*!< Operational amplifier1 calibration output */
Kojto 122:f9eeca106725 12617
Kojto 122:f9eeca106725 12618 #define OPAMP1_CSR_OPARANGE_Pos (31U)
Kojto 122:f9eeca106725 12619 #define OPAMP1_CSR_OPARANGE_Msk (0x1U << OPAMP1_CSR_OPARANGE_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 12620 #define OPAMP1_CSR_OPARANGE OPAMP1_CSR_OPARANGE_Msk /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */
Kojto 122:f9eeca106725 12621
Kojto 122:f9eeca106725 12622 /******************* Bit definition for OPAMP_OTR register ******************/
Kojto 122:f9eeca106725 12623 #define OPAMP_OTR_TRIMOFFSETN_Pos (0U)
Kojto 122:f9eeca106725 12624 #define OPAMP_OTR_TRIMOFFSETN_Msk (0x1FU << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
Kojto 122:f9eeca106725 12625 #define OPAMP_OTR_TRIMOFFSETN OPAMP_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
Kojto 122:f9eeca106725 12626 #define OPAMP_OTR_TRIMOFFSETP_Pos (8U)
Kojto 122:f9eeca106725 12627 #define OPAMP_OTR_TRIMOFFSETP_Msk (0x1FU << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
Kojto 122:f9eeca106725 12628 #define OPAMP_OTR_TRIMOFFSETP OPAMP_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
Kojto 122:f9eeca106725 12629
Kojto 122:f9eeca106725 12630 /******************* Bit definition for OPAMP1_OTR register ******************/
Kojto 122:f9eeca106725 12631 #define OPAMP1_OTR_TRIMOFFSETN_Pos (0U)
Kojto 122:f9eeca106725 12632 #define OPAMP1_OTR_TRIMOFFSETN_Msk (0x1FU << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
Kojto 122:f9eeca106725 12633 #define OPAMP1_OTR_TRIMOFFSETN OPAMP1_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
Kojto 122:f9eeca106725 12634 #define OPAMP1_OTR_TRIMOFFSETP_Pos (8U)
Kojto 122:f9eeca106725 12635 #define OPAMP1_OTR_TRIMOFFSETP_Msk (0x1FU << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
Kojto 122:f9eeca106725 12636 #define OPAMP1_OTR_TRIMOFFSETP OPAMP1_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
Kojto 122:f9eeca106725 12637
Kojto 122:f9eeca106725 12638 /******************* Bit definition for OPAMP_LPOTR register ****************/
Kojto 122:f9eeca106725 12639 #define OPAMP_LPOTR_TRIMLPOFFSETN_Pos (0U)
Kojto 122:f9eeca106725 12640 #define OPAMP_LPOTR_TRIMLPOFFSETN_Msk (0x1FU << OPAMP_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
Kojto 122:f9eeca106725 12641 #define OPAMP_LPOTR_TRIMLPOFFSETN OPAMP_LPOTR_TRIMLPOFFSETN_Msk /*!< Trim for NMOS differential pairs */
Kojto 122:f9eeca106725 12642 #define OPAMP_LPOTR_TRIMLPOFFSETP_Pos (8U)
Kojto 122:f9eeca106725 12643 #define OPAMP_LPOTR_TRIMLPOFFSETP_Msk (0x1FU << OPAMP_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
Kojto 122:f9eeca106725 12644 #define OPAMP_LPOTR_TRIMLPOFFSETP OPAMP_LPOTR_TRIMLPOFFSETP_Msk /*!< Trim for PMOS differential pairs */
Kojto 122:f9eeca106725 12645
Kojto 122:f9eeca106725 12646 /******************* Bit definition for OPAMP1_LPOTR register ****************/
Kojto 122:f9eeca106725 12647 #define OPAMP1_LPOTR_TRIMLPOFFSETN_Pos (0U)
Kojto 122:f9eeca106725 12648 #define OPAMP1_LPOTR_TRIMLPOFFSETN_Msk (0x1FU << OPAMP1_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
Kojto 122:f9eeca106725 12649 #define OPAMP1_LPOTR_TRIMLPOFFSETN OPAMP1_LPOTR_TRIMLPOFFSETN_Msk /*!< Trim for NMOS differential pairs */
Kojto 122:f9eeca106725 12650 #define OPAMP1_LPOTR_TRIMLPOFFSETP_Pos (8U)
Kojto 122:f9eeca106725 12651 #define OPAMP1_LPOTR_TRIMLPOFFSETP_Msk (0x1FU << OPAMP1_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
Kojto 122:f9eeca106725 12652 #define OPAMP1_LPOTR_TRIMLPOFFSETP OPAMP1_LPOTR_TRIMLPOFFSETP_Msk /*!< Trim for PMOS differential pairs */
Kojto 122:f9eeca106725 12653
Kojto 122:f9eeca106725 12654 /******************************************************************************/
Kojto 122:f9eeca106725 12655 /* */
Kojto 122:f9eeca106725 12656 /* Touch Sensing Controller (TSC) */
Kojto 122:f9eeca106725 12657 /* */
Kojto 122:f9eeca106725 12658 /******************************************************************************/
Kojto 122:f9eeca106725 12659 /******************* Bit definition for TSC_CR register *********************/
Kojto 122:f9eeca106725 12660 #define TSC_CR_TSCE_Pos (0U)
Kojto 122:f9eeca106725 12661 #define TSC_CR_TSCE_Msk (0x1U << TSC_CR_TSCE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 12662 #define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!<Touch sensing controller enable */
Kojto 122:f9eeca106725 12663 #define TSC_CR_START_Pos (1U)
Kojto 122:f9eeca106725 12664 #define TSC_CR_START_Msk (0x1U << TSC_CR_START_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 12665 #define TSC_CR_START TSC_CR_START_Msk /*!<Start acquisition */
Kojto 122:f9eeca106725 12666 #define TSC_CR_AM_Pos (2U)
Kojto 122:f9eeca106725 12667 #define TSC_CR_AM_Msk (0x1U << TSC_CR_AM_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 12668 #define TSC_CR_AM TSC_CR_AM_Msk /*!<Acquisition mode */
Kojto 122:f9eeca106725 12669 #define TSC_CR_SYNCPOL_Pos (3U)
Kojto 122:f9eeca106725 12670 #define TSC_CR_SYNCPOL_Msk (0x1U << TSC_CR_SYNCPOL_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 12671 #define TSC_CR_SYNCPOL TSC_CR_SYNCPOL_Msk /*!<Synchronization pin polarity */
Kojto 122:f9eeca106725 12672 #define TSC_CR_IODEF_Pos (4U)
Kojto 122:f9eeca106725 12673 #define TSC_CR_IODEF_Msk (0x1U << TSC_CR_IODEF_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 12674 #define TSC_CR_IODEF TSC_CR_IODEF_Msk /*!<IO default mode */
Kojto 122:f9eeca106725 12675
Kojto 122:f9eeca106725 12676 #define TSC_CR_MCV_Pos (5U)
Kojto 122:f9eeca106725 12677 #define TSC_CR_MCV_Msk (0x7U << TSC_CR_MCV_Pos) /*!< 0x000000E0 */
Kojto 122:f9eeca106725 12678 #define TSC_CR_MCV TSC_CR_MCV_Msk /*!<MCV[2:0] bits (Max Count Value) */
Kojto 122:f9eeca106725 12679 #define TSC_CR_MCV_0 (0x1U << TSC_CR_MCV_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 12680 #define TSC_CR_MCV_1 (0x2U << TSC_CR_MCV_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 12681 #define TSC_CR_MCV_2 (0x4U << TSC_CR_MCV_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 12682
Kojto 122:f9eeca106725 12683 #define TSC_CR_PGPSC_Pos (12U)
Kojto 122:f9eeca106725 12684 #define TSC_CR_PGPSC_Msk (0x7U << TSC_CR_PGPSC_Pos) /*!< 0x00007000 */
Kojto 122:f9eeca106725 12685 #define TSC_CR_PGPSC TSC_CR_PGPSC_Msk /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
Kojto 122:f9eeca106725 12686 #define TSC_CR_PGPSC_0 (0x1U << TSC_CR_PGPSC_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 12687 #define TSC_CR_PGPSC_1 (0x2U << TSC_CR_PGPSC_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 12688 #define TSC_CR_PGPSC_2 (0x4U << TSC_CR_PGPSC_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 12689
Kojto 122:f9eeca106725 12690 #define TSC_CR_SSPSC_Pos (15U)
Kojto 122:f9eeca106725 12691 #define TSC_CR_SSPSC_Msk (0x1U << TSC_CR_SSPSC_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 12692 #define TSC_CR_SSPSC TSC_CR_SSPSC_Msk /*!<Spread Spectrum Prescaler */
Kojto 122:f9eeca106725 12693 #define TSC_CR_SSE_Pos (16U)
Kojto 122:f9eeca106725 12694 #define TSC_CR_SSE_Msk (0x1U << TSC_CR_SSE_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 12695 #define TSC_CR_SSE TSC_CR_SSE_Msk /*!<Spread Spectrum Enable */
Kojto 122:f9eeca106725 12696
Kojto 122:f9eeca106725 12697 #define TSC_CR_SSD_Pos (17U)
Kojto 122:f9eeca106725 12698 #define TSC_CR_SSD_Msk (0x7FU << TSC_CR_SSD_Pos) /*!< 0x00FE0000 */
Kojto 122:f9eeca106725 12699 #define TSC_CR_SSD TSC_CR_SSD_Msk /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
Kojto 122:f9eeca106725 12700 #define TSC_CR_SSD_0 (0x01U << TSC_CR_SSD_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 12701 #define TSC_CR_SSD_1 (0x02U << TSC_CR_SSD_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 12702 #define TSC_CR_SSD_2 (0x04U << TSC_CR_SSD_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 12703 #define TSC_CR_SSD_3 (0x08U << TSC_CR_SSD_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 12704 #define TSC_CR_SSD_4 (0x10U << TSC_CR_SSD_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 12705 #define TSC_CR_SSD_5 (0x20U << TSC_CR_SSD_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 12706 #define TSC_CR_SSD_6 (0x40U << TSC_CR_SSD_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 12707
Kojto 122:f9eeca106725 12708 #define TSC_CR_CTPL_Pos (24U)
Kojto 122:f9eeca106725 12709 #define TSC_CR_CTPL_Msk (0xFU << TSC_CR_CTPL_Pos) /*!< 0x0F000000 */
Kojto 122:f9eeca106725 12710 #define TSC_CR_CTPL TSC_CR_CTPL_Msk /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
Kojto 122:f9eeca106725 12711 #define TSC_CR_CTPL_0 (0x1U << TSC_CR_CTPL_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 12712 #define TSC_CR_CTPL_1 (0x2U << TSC_CR_CTPL_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 12713 #define TSC_CR_CTPL_2 (0x4U << TSC_CR_CTPL_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 12714 #define TSC_CR_CTPL_3 (0x8U << TSC_CR_CTPL_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 12715
Kojto 122:f9eeca106725 12716 #define TSC_CR_CTPH_Pos (28U)
Kojto 122:f9eeca106725 12717 #define TSC_CR_CTPH_Msk (0xFU << TSC_CR_CTPH_Pos) /*!< 0xF0000000 */
Kojto 122:f9eeca106725 12718 #define TSC_CR_CTPH TSC_CR_CTPH_Msk /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
Kojto 122:f9eeca106725 12719 #define TSC_CR_CTPH_0 (0x1U << TSC_CR_CTPH_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 12720 #define TSC_CR_CTPH_1 (0x2U << TSC_CR_CTPH_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 12721 #define TSC_CR_CTPH_2 (0x4U << TSC_CR_CTPH_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 12722 #define TSC_CR_CTPH_3 (0x8U << TSC_CR_CTPH_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 12723
Kojto 122:f9eeca106725 12724 /******************* Bit definition for TSC_IER register ********************/
Kojto 122:f9eeca106725 12725 #define TSC_IER_EOAIE_Pos (0U)
Kojto 122:f9eeca106725 12726 #define TSC_IER_EOAIE_Msk (0x1U << TSC_IER_EOAIE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 12727 #define TSC_IER_EOAIE TSC_IER_EOAIE_Msk /*!<End of acquisition interrupt enable */
Kojto 122:f9eeca106725 12728 #define TSC_IER_MCEIE_Pos (1U)
Kojto 122:f9eeca106725 12729 #define TSC_IER_MCEIE_Msk (0x1U << TSC_IER_MCEIE_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 12730 #define TSC_IER_MCEIE TSC_IER_MCEIE_Msk /*!<Max count error interrupt enable */
Kojto 122:f9eeca106725 12731
Kojto 122:f9eeca106725 12732 /******************* Bit definition for TSC_ICR register ********************/
Kojto 122:f9eeca106725 12733 #define TSC_ICR_EOAIC_Pos (0U)
Kojto 122:f9eeca106725 12734 #define TSC_ICR_EOAIC_Msk (0x1U << TSC_ICR_EOAIC_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 12735 #define TSC_ICR_EOAIC TSC_ICR_EOAIC_Msk /*!<End of acquisition interrupt clear */
Kojto 122:f9eeca106725 12736 #define TSC_ICR_MCEIC_Pos (1U)
Kojto 122:f9eeca106725 12737 #define TSC_ICR_MCEIC_Msk (0x1U << TSC_ICR_MCEIC_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 12738 #define TSC_ICR_MCEIC TSC_ICR_MCEIC_Msk /*!<Max count error interrupt clear */
Kojto 122:f9eeca106725 12739
Kojto 122:f9eeca106725 12740 /******************* Bit definition for TSC_ISR register ********************/
Kojto 122:f9eeca106725 12741 #define TSC_ISR_EOAF_Pos (0U)
Kojto 122:f9eeca106725 12742 #define TSC_ISR_EOAF_Msk (0x1U << TSC_ISR_EOAF_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 12743 #define TSC_ISR_EOAF TSC_ISR_EOAF_Msk /*!<End of acquisition flag */
Kojto 122:f9eeca106725 12744 #define TSC_ISR_MCEF_Pos (1U)
Kojto 122:f9eeca106725 12745 #define TSC_ISR_MCEF_Msk (0x1U << TSC_ISR_MCEF_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 12746 #define TSC_ISR_MCEF TSC_ISR_MCEF_Msk /*!<Max count error flag */
Kojto 122:f9eeca106725 12747
Kojto 122:f9eeca106725 12748 /******************* Bit definition for TSC_IOHCR register ******************/
Kojto 122:f9eeca106725 12749 #define TSC_IOHCR_G1_IO1_Pos (0U)
Kojto 122:f9eeca106725 12750 #define TSC_IOHCR_G1_IO1_Msk (0x1U << TSC_IOHCR_G1_IO1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 12751 #define TSC_IOHCR_G1_IO1 TSC_IOHCR_G1_IO1_Msk /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 12752 #define TSC_IOHCR_G1_IO2_Pos (1U)
Kojto 122:f9eeca106725 12753 #define TSC_IOHCR_G1_IO2_Msk (0x1U << TSC_IOHCR_G1_IO2_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 12754 #define TSC_IOHCR_G1_IO2 TSC_IOHCR_G1_IO2_Msk /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 12755 #define TSC_IOHCR_G1_IO3_Pos (2U)
Kojto 122:f9eeca106725 12756 #define TSC_IOHCR_G1_IO3_Msk (0x1U << TSC_IOHCR_G1_IO3_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 12757 #define TSC_IOHCR_G1_IO3 TSC_IOHCR_G1_IO3_Msk /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 12758 #define TSC_IOHCR_G1_IO4_Pos (3U)
Kojto 122:f9eeca106725 12759 #define TSC_IOHCR_G1_IO4_Msk (0x1U << TSC_IOHCR_G1_IO4_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 12760 #define TSC_IOHCR_G1_IO4 TSC_IOHCR_G1_IO4_Msk /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 12761 #define TSC_IOHCR_G2_IO1_Pos (4U)
Kojto 122:f9eeca106725 12762 #define TSC_IOHCR_G2_IO1_Msk (0x1U << TSC_IOHCR_G2_IO1_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 12763 #define TSC_IOHCR_G2_IO1 TSC_IOHCR_G2_IO1_Msk /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 12764 #define TSC_IOHCR_G2_IO2_Pos (5U)
Kojto 122:f9eeca106725 12765 #define TSC_IOHCR_G2_IO2_Msk (0x1U << TSC_IOHCR_G2_IO2_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 12766 #define TSC_IOHCR_G2_IO2 TSC_IOHCR_G2_IO2_Msk /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 12767 #define TSC_IOHCR_G2_IO3_Pos (6U)
Kojto 122:f9eeca106725 12768 #define TSC_IOHCR_G2_IO3_Msk (0x1U << TSC_IOHCR_G2_IO3_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 12769 #define TSC_IOHCR_G2_IO3 TSC_IOHCR_G2_IO3_Msk /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 12770 #define TSC_IOHCR_G2_IO4_Pos (7U)
Kojto 122:f9eeca106725 12771 #define TSC_IOHCR_G2_IO4_Msk (0x1U << TSC_IOHCR_G2_IO4_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 12772 #define TSC_IOHCR_G2_IO4 TSC_IOHCR_G2_IO4_Msk /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 12773 #define TSC_IOHCR_G3_IO1_Pos (8U)
Kojto 122:f9eeca106725 12774 #define TSC_IOHCR_G3_IO1_Msk (0x1U << TSC_IOHCR_G3_IO1_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 12775 #define TSC_IOHCR_G3_IO1 TSC_IOHCR_G3_IO1_Msk /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 12776 #define TSC_IOHCR_G3_IO2_Pos (9U)
Kojto 122:f9eeca106725 12777 #define TSC_IOHCR_G3_IO2_Msk (0x1U << TSC_IOHCR_G3_IO2_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 12778 #define TSC_IOHCR_G3_IO2 TSC_IOHCR_G3_IO2_Msk /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 12779 #define TSC_IOHCR_G3_IO3_Pos (10U)
Kojto 122:f9eeca106725 12780 #define TSC_IOHCR_G3_IO3_Msk (0x1U << TSC_IOHCR_G3_IO3_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 12781 #define TSC_IOHCR_G3_IO3 TSC_IOHCR_G3_IO3_Msk /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 12782 #define TSC_IOHCR_G3_IO4_Pos (11U)
Kojto 122:f9eeca106725 12783 #define TSC_IOHCR_G3_IO4_Msk (0x1U << TSC_IOHCR_G3_IO4_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 12784 #define TSC_IOHCR_G3_IO4 TSC_IOHCR_G3_IO4_Msk /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 12785 #define TSC_IOHCR_G4_IO1_Pos (12U)
Kojto 122:f9eeca106725 12786 #define TSC_IOHCR_G4_IO1_Msk (0x1U << TSC_IOHCR_G4_IO1_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 12787 #define TSC_IOHCR_G4_IO1 TSC_IOHCR_G4_IO1_Msk /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 12788 #define TSC_IOHCR_G4_IO2_Pos (13U)
Kojto 122:f9eeca106725 12789 #define TSC_IOHCR_G4_IO2_Msk (0x1U << TSC_IOHCR_G4_IO2_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 12790 #define TSC_IOHCR_G4_IO2 TSC_IOHCR_G4_IO2_Msk /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 12791 #define TSC_IOHCR_G4_IO3_Pos (14U)
Kojto 122:f9eeca106725 12792 #define TSC_IOHCR_G4_IO3_Msk (0x1U << TSC_IOHCR_G4_IO3_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 12793 #define TSC_IOHCR_G4_IO3 TSC_IOHCR_G4_IO3_Msk /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 12794 #define TSC_IOHCR_G4_IO4_Pos (15U)
Kojto 122:f9eeca106725 12795 #define TSC_IOHCR_G4_IO4_Msk (0x1U << TSC_IOHCR_G4_IO4_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 12796 #define TSC_IOHCR_G4_IO4 TSC_IOHCR_G4_IO4_Msk /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 12797 #define TSC_IOHCR_G5_IO1_Pos (16U)
Kojto 122:f9eeca106725 12798 #define TSC_IOHCR_G5_IO1_Msk (0x1U << TSC_IOHCR_G5_IO1_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 12799 #define TSC_IOHCR_G5_IO1 TSC_IOHCR_G5_IO1_Msk /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 12800 #define TSC_IOHCR_G5_IO2_Pos (17U)
Kojto 122:f9eeca106725 12801 #define TSC_IOHCR_G5_IO2_Msk (0x1U << TSC_IOHCR_G5_IO2_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 12802 #define TSC_IOHCR_G5_IO2 TSC_IOHCR_G5_IO2_Msk /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 12803 #define TSC_IOHCR_G5_IO3_Pos (18U)
Kojto 122:f9eeca106725 12804 #define TSC_IOHCR_G5_IO3_Msk (0x1U << TSC_IOHCR_G5_IO3_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 12805 #define TSC_IOHCR_G5_IO3 TSC_IOHCR_G5_IO3_Msk /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 12806 #define TSC_IOHCR_G5_IO4_Pos (19U)
Kojto 122:f9eeca106725 12807 #define TSC_IOHCR_G5_IO4_Msk (0x1U << TSC_IOHCR_G5_IO4_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 12808 #define TSC_IOHCR_G5_IO4 TSC_IOHCR_G5_IO4_Msk /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 12809 #define TSC_IOHCR_G6_IO1_Pos (20U)
Kojto 122:f9eeca106725 12810 #define TSC_IOHCR_G6_IO1_Msk (0x1U << TSC_IOHCR_G6_IO1_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 12811 #define TSC_IOHCR_G6_IO1 TSC_IOHCR_G6_IO1_Msk /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 12812 #define TSC_IOHCR_G6_IO2_Pos (21U)
Kojto 122:f9eeca106725 12813 #define TSC_IOHCR_G6_IO2_Msk (0x1U << TSC_IOHCR_G6_IO2_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 12814 #define TSC_IOHCR_G6_IO2 TSC_IOHCR_G6_IO2_Msk /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 12815 #define TSC_IOHCR_G6_IO3_Pos (22U)
Kojto 122:f9eeca106725 12816 #define TSC_IOHCR_G6_IO3_Msk (0x1U << TSC_IOHCR_G6_IO3_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 12817 #define TSC_IOHCR_G6_IO3 TSC_IOHCR_G6_IO3_Msk /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 12818 #define TSC_IOHCR_G6_IO4_Pos (23U)
Kojto 122:f9eeca106725 12819 #define TSC_IOHCR_G6_IO4_Msk (0x1U << TSC_IOHCR_G6_IO4_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 12820 #define TSC_IOHCR_G6_IO4 TSC_IOHCR_G6_IO4_Msk /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 12821 #define TSC_IOHCR_G7_IO1_Pos (24U)
Kojto 122:f9eeca106725 12822 #define TSC_IOHCR_G7_IO1_Msk (0x1U << TSC_IOHCR_G7_IO1_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 12823 #define TSC_IOHCR_G7_IO1 TSC_IOHCR_G7_IO1_Msk /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 12824 #define TSC_IOHCR_G7_IO2_Pos (25U)
Kojto 122:f9eeca106725 12825 #define TSC_IOHCR_G7_IO2_Msk (0x1U << TSC_IOHCR_G7_IO2_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 12826 #define TSC_IOHCR_G7_IO2 TSC_IOHCR_G7_IO2_Msk /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 12827 #define TSC_IOHCR_G7_IO3_Pos (26U)
Kojto 122:f9eeca106725 12828 #define TSC_IOHCR_G7_IO3_Msk (0x1U << TSC_IOHCR_G7_IO3_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 12829 #define TSC_IOHCR_G7_IO3 TSC_IOHCR_G7_IO3_Msk /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 12830 #define TSC_IOHCR_G7_IO4_Pos (27U)
Kojto 122:f9eeca106725 12831 #define TSC_IOHCR_G7_IO4_Msk (0x1U << TSC_IOHCR_G7_IO4_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 12832 #define TSC_IOHCR_G7_IO4 TSC_IOHCR_G7_IO4_Msk /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
Kojto 122:f9eeca106725 12833
Kojto 122:f9eeca106725 12834 /******************* Bit definition for TSC_IOASCR register *****************/
Kojto 122:f9eeca106725 12835 #define TSC_IOASCR_G1_IO1_Pos (0U)
Kojto 122:f9eeca106725 12836 #define TSC_IOASCR_G1_IO1_Msk (0x1U << TSC_IOASCR_G1_IO1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 12837 #define TSC_IOASCR_G1_IO1 TSC_IOASCR_G1_IO1_Msk /*!<GROUP1_IO1 analog switch enable */
Kojto 122:f9eeca106725 12838 #define TSC_IOASCR_G1_IO2_Pos (1U)
Kojto 122:f9eeca106725 12839 #define TSC_IOASCR_G1_IO2_Msk (0x1U << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 12840 #define TSC_IOASCR_G1_IO2 TSC_IOASCR_G1_IO2_Msk /*!<GROUP1_IO2 analog switch enable */
Kojto 122:f9eeca106725 12841 #define TSC_IOASCR_G1_IO3_Pos (2U)
Kojto 122:f9eeca106725 12842 #define TSC_IOASCR_G1_IO3_Msk (0x1U << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 12843 #define TSC_IOASCR_G1_IO3 TSC_IOASCR_G1_IO3_Msk /*!<GROUP1_IO3 analog switch enable */
Kojto 122:f9eeca106725 12844 #define TSC_IOASCR_G1_IO4_Pos (3U)
Kojto 122:f9eeca106725 12845 #define TSC_IOASCR_G1_IO4_Msk (0x1U << TSC_IOASCR_G1_IO4_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 12846 #define TSC_IOASCR_G1_IO4 TSC_IOASCR_G1_IO4_Msk /*!<GROUP1_IO4 analog switch enable */
Kojto 122:f9eeca106725 12847 #define TSC_IOASCR_G2_IO1_Pos (4U)
Kojto 122:f9eeca106725 12848 #define TSC_IOASCR_G2_IO1_Msk (0x1U << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 12849 #define TSC_IOASCR_G2_IO1 TSC_IOASCR_G2_IO1_Msk /*!<GROUP2_IO1 analog switch enable */
Kojto 122:f9eeca106725 12850 #define TSC_IOASCR_G2_IO2_Pos (5U)
Kojto 122:f9eeca106725 12851 #define TSC_IOASCR_G2_IO2_Msk (0x1U << TSC_IOASCR_G2_IO2_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 12852 #define TSC_IOASCR_G2_IO2 TSC_IOASCR_G2_IO2_Msk /*!<GROUP2_IO2 analog switch enable */
Kojto 122:f9eeca106725 12853 #define TSC_IOASCR_G2_IO3_Pos (6U)
Kojto 122:f9eeca106725 12854 #define TSC_IOASCR_G2_IO3_Msk (0x1U << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 12855 #define TSC_IOASCR_G2_IO3 TSC_IOASCR_G2_IO3_Msk /*!<GROUP2_IO3 analog switch enable */
Kojto 122:f9eeca106725 12856 #define TSC_IOASCR_G2_IO4_Pos (7U)
Kojto 122:f9eeca106725 12857 #define TSC_IOASCR_G2_IO4_Msk (0x1U << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 12858 #define TSC_IOASCR_G2_IO4 TSC_IOASCR_G2_IO4_Msk /*!<GROUP2_IO4 analog switch enable */
Kojto 122:f9eeca106725 12859 #define TSC_IOASCR_G3_IO1_Pos (8U)
Kojto 122:f9eeca106725 12860 #define TSC_IOASCR_G3_IO1_Msk (0x1U << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 12861 #define TSC_IOASCR_G3_IO1 TSC_IOASCR_G3_IO1_Msk /*!<GROUP3_IO1 analog switch enable */
Kojto 122:f9eeca106725 12862 #define TSC_IOASCR_G3_IO2_Pos (9U)
Kojto 122:f9eeca106725 12863 #define TSC_IOASCR_G3_IO2_Msk (0x1U << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 12864 #define TSC_IOASCR_G3_IO2 TSC_IOASCR_G3_IO2_Msk /*!<GROUP3_IO2 analog switch enable */
Kojto 122:f9eeca106725 12865 #define TSC_IOASCR_G3_IO3_Pos (10U)
Kojto 122:f9eeca106725 12866 #define TSC_IOASCR_G3_IO3_Msk (0x1U << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 12867 #define TSC_IOASCR_G3_IO3 TSC_IOASCR_G3_IO3_Msk /*!<GROUP3_IO3 analog switch enable */
Kojto 122:f9eeca106725 12868 #define TSC_IOASCR_G3_IO4_Pos (11U)
Kojto 122:f9eeca106725 12869 #define TSC_IOASCR_G3_IO4_Msk (0x1U << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 12870 #define TSC_IOASCR_G3_IO4 TSC_IOASCR_G3_IO4_Msk /*!<GROUP3_IO4 analog switch enable */
Kojto 122:f9eeca106725 12871 #define TSC_IOASCR_G4_IO1_Pos (12U)
Kojto 122:f9eeca106725 12872 #define TSC_IOASCR_G4_IO1_Msk (0x1U << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 12873 #define TSC_IOASCR_G4_IO1 TSC_IOASCR_G4_IO1_Msk /*!<GROUP4_IO1 analog switch enable */
Kojto 122:f9eeca106725 12874 #define TSC_IOASCR_G4_IO2_Pos (13U)
Kojto 122:f9eeca106725 12875 #define TSC_IOASCR_G4_IO2_Msk (0x1U << TSC_IOASCR_G4_IO2_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 12876 #define TSC_IOASCR_G4_IO2 TSC_IOASCR_G4_IO2_Msk /*!<GROUP4_IO2 analog switch enable */
Kojto 122:f9eeca106725 12877 #define TSC_IOASCR_G4_IO3_Pos (14U)
Kojto 122:f9eeca106725 12878 #define TSC_IOASCR_G4_IO3_Msk (0x1U << TSC_IOASCR_G4_IO3_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 12879 #define TSC_IOASCR_G4_IO3 TSC_IOASCR_G4_IO3_Msk /*!<GROUP4_IO3 analog switch enable */
Kojto 122:f9eeca106725 12880 #define TSC_IOASCR_G4_IO4_Pos (15U)
Kojto 122:f9eeca106725 12881 #define TSC_IOASCR_G4_IO4_Msk (0x1U << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 12882 #define TSC_IOASCR_G4_IO4 TSC_IOASCR_G4_IO4_Msk /*!<GROUP4_IO4 analog switch enable */
Kojto 122:f9eeca106725 12883 #define TSC_IOASCR_G5_IO1_Pos (16U)
Kojto 122:f9eeca106725 12884 #define TSC_IOASCR_G5_IO1_Msk (0x1U << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 12885 #define TSC_IOASCR_G5_IO1 TSC_IOASCR_G5_IO1_Msk /*!<GROUP5_IO1 analog switch enable */
Kojto 122:f9eeca106725 12886 #define TSC_IOASCR_G5_IO2_Pos (17U)
Kojto 122:f9eeca106725 12887 #define TSC_IOASCR_G5_IO2_Msk (0x1U << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 12888 #define TSC_IOASCR_G5_IO2 TSC_IOASCR_G5_IO2_Msk /*!<GROUP5_IO2 analog switch enable */
Kojto 122:f9eeca106725 12889 #define TSC_IOASCR_G5_IO3_Pos (18U)
Kojto 122:f9eeca106725 12890 #define TSC_IOASCR_G5_IO3_Msk (0x1U << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 12891 #define TSC_IOASCR_G5_IO3 TSC_IOASCR_G5_IO3_Msk /*!<GROUP5_IO3 analog switch enable */
Kojto 122:f9eeca106725 12892 #define TSC_IOASCR_G5_IO4_Pos (19U)
Kojto 122:f9eeca106725 12893 #define TSC_IOASCR_G5_IO4_Msk (0x1U << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 12894 #define TSC_IOASCR_G5_IO4 TSC_IOASCR_G5_IO4_Msk /*!<GROUP5_IO4 analog switch enable */
Kojto 122:f9eeca106725 12895 #define TSC_IOASCR_G6_IO1_Pos (20U)
Kojto 122:f9eeca106725 12896 #define TSC_IOASCR_G6_IO1_Msk (0x1U << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 12897 #define TSC_IOASCR_G6_IO1 TSC_IOASCR_G6_IO1_Msk /*!<GROUP6_IO1 analog switch enable */
Kojto 122:f9eeca106725 12898 #define TSC_IOASCR_G6_IO2_Pos (21U)
Kojto 122:f9eeca106725 12899 #define TSC_IOASCR_G6_IO2_Msk (0x1U << TSC_IOASCR_G6_IO2_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 12900 #define TSC_IOASCR_G6_IO2 TSC_IOASCR_G6_IO2_Msk /*!<GROUP6_IO2 analog switch enable */
Kojto 122:f9eeca106725 12901 #define TSC_IOASCR_G6_IO3_Pos (22U)
Kojto 122:f9eeca106725 12902 #define TSC_IOASCR_G6_IO3_Msk (0x1U << TSC_IOASCR_G6_IO3_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 12903 #define TSC_IOASCR_G6_IO3 TSC_IOASCR_G6_IO3_Msk /*!<GROUP6_IO3 analog switch enable */
Kojto 122:f9eeca106725 12904 #define TSC_IOASCR_G6_IO4_Pos (23U)
Kojto 122:f9eeca106725 12905 #define TSC_IOASCR_G6_IO4_Msk (0x1U << TSC_IOASCR_G6_IO4_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 12906 #define TSC_IOASCR_G6_IO4 TSC_IOASCR_G6_IO4_Msk /*!<GROUP6_IO4 analog switch enable */
Kojto 122:f9eeca106725 12907 #define TSC_IOASCR_G7_IO1_Pos (24U)
Kojto 122:f9eeca106725 12908 #define TSC_IOASCR_G7_IO1_Msk (0x1U << TSC_IOASCR_G7_IO1_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 12909 #define TSC_IOASCR_G7_IO1 TSC_IOASCR_G7_IO1_Msk /*!<GROUP7_IO1 analog switch enable */
Kojto 122:f9eeca106725 12910 #define TSC_IOASCR_G7_IO2_Pos (25U)
Kojto 122:f9eeca106725 12911 #define TSC_IOASCR_G7_IO2_Msk (0x1U << TSC_IOASCR_G7_IO2_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 12912 #define TSC_IOASCR_G7_IO2 TSC_IOASCR_G7_IO2_Msk /*!<GROUP7_IO2 analog switch enable */
Kojto 122:f9eeca106725 12913 #define TSC_IOASCR_G7_IO3_Pos (26U)
Kojto 122:f9eeca106725 12914 #define TSC_IOASCR_G7_IO3_Msk (0x1U << TSC_IOASCR_G7_IO3_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 12915 #define TSC_IOASCR_G7_IO3 TSC_IOASCR_G7_IO3_Msk /*!<GROUP7_IO3 analog switch enable */
Kojto 122:f9eeca106725 12916 #define TSC_IOASCR_G7_IO4_Pos (27U)
Kojto 122:f9eeca106725 12917 #define TSC_IOASCR_G7_IO4_Msk (0x1U << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 12918 #define TSC_IOASCR_G7_IO4 TSC_IOASCR_G7_IO4_Msk /*!<GROUP7_IO4 analog switch enable */
Kojto 122:f9eeca106725 12919
Kojto 122:f9eeca106725 12920 /******************* Bit definition for TSC_IOSCR register ******************/
Kojto 122:f9eeca106725 12921 #define TSC_IOSCR_G1_IO1_Pos (0U)
Kojto 122:f9eeca106725 12922 #define TSC_IOSCR_G1_IO1_Msk (0x1U << TSC_IOSCR_G1_IO1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 12923 #define TSC_IOSCR_G1_IO1 TSC_IOSCR_G1_IO1_Msk /*!<GROUP1_IO1 sampling mode */
Kojto 122:f9eeca106725 12924 #define TSC_IOSCR_G1_IO2_Pos (1U)
Kojto 122:f9eeca106725 12925 #define TSC_IOSCR_G1_IO2_Msk (0x1U << TSC_IOSCR_G1_IO2_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 12926 #define TSC_IOSCR_G1_IO2 TSC_IOSCR_G1_IO2_Msk /*!<GROUP1_IO2 sampling mode */
Kojto 122:f9eeca106725 12927 #define TSC_IOSCR_G1_IO3_Pos (2U)
Kojto 122:f9eeca106725 12928 #define TSC_IOSCR_G1_IO3_Msk (0x1U << TSC_IOSCR_G1_IO3_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 12929 #define TSC_IOSCR_G1_IO3 TSC_IOSCR_G1_IO3_Msk /*!<GROUP1_IO3 sampling mode */
Kojto 122:f9eeca106725 12930 #define TSC_IOSCR_G1_IO4_Pos (3U)
Kojto 122:f9eeca106725 12931 #define TSC_IOSCR_G1_IO4_Msk (0x1U << TSC_IOSCR_G1_IO4_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 12932 #define TSC_IOSCR_G1_IO4 TSC_IOSCR_G1_IO4_Msk /*!<GROUP1_IO4 sampling mode */
Kojto 122:f9eeca106725 12933 #define TSC_IOSCR_G2_IO1_Pos (4U)
Kojto 122:f9eeca106725 12934 #define TSC_IOSCR_G2_IO1_Msk (0x1U << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 12935 #define TSC_IOSCR_G2_IO1 TSC_IOSCR_G2_IO1_Msk /*!<GROUP2_IO1 sampling mode */
Kojto 122:f9eeca106725 12936 #define TSC_IOSCR_G2_IO2_Pos (5U)
Kojto 122:f9eeca106725 12937 #define TSC_IOSCR_G2_IO2_Msk (0x1U << TSC_IOSCR_G2_IO2_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 12938 #define TSC_IOSCR_G2_IO2 TSC_IOSCR_G2_IO2_Msk /*!<GROUP2_IO2 sampling mode */
Kojto 122:f9eeca106725 12939 #define TSC_IOSCR_G2_IO3_Pos (6U)
Kojto 122:f9eeca106725 12940 #define TSC_IOSCR_G2_IO3_Msk (0x1U << TSC_IOSCR_G2_IO3_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 12941 #define TSC_IOSCR_G2_IO3 TSC_IOSCR_G2_IO3_Msk /*!<GROUP2_IO3 sampling mode */
Kojto 122:f9eeca106725 12942 #define TSC_IOSCR_G2_IO4_Pos (7U)
Kojto 122:f9eeca106725 12943 #define TSC_IOSCR_G2_IO4_Msk (0x1U << TSC_IOSCR_G2_IO4_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 12944 #define TSC_IOSCR_G2_IO4 TSC_IOSCR_G2_IO4_Msk /*!<GROUP2_IO4 sampling mode */
Kojto 122:f9eeca106725 12945 #define TSC_IOSCR_G3_IO1_Pos (8U)
Kojto 122:f9eeca106725 12946 #define TSC_IOSCR_G3_IO1_Msk (0x1U << TSC_IOSCR_G3_IO1_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 12947 #define TSC_IOSCR_G3_IO1 TSC_IOSCR_G3_IO1_Msk /*!<GROUP3_IO1 sampling mode */
Kojto 122:f9eeca106725 12948 #define TSC_IOSCR_G3_IO2_Pos (9U)
Kojto 122:f9eeca106725 12949 #define TSC_IOSCR_G3_IO2_Msk (0x1U << TSC_IOSCR_G3_IO2_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 12950 #define TSC_IOSCR_G3_IO2 TSC_IOSCR_G3_IO2_Msk /*!<GROUP3_IO2 sampling mode */
Kojto 122:f9eeca106725 12951 #define TSC_IOSCR_G3_IO3_Pos (10U)
Kojto 122:f9eeca106725 12952 #define TSC_IOSCR_G3_IO3_Msk (0x1U << TSC_IOSCR_G3_IO3_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 12953 #define TSC_IOSCR_G3_IO3 TSC_IOSCR_G3_IO3_Msk /*!<GROUP3_IO3 sampling mode */
Kojto 122:f9eeca106725 12954 #define TSC_IOSCR_G3_IO4_Pos (11U)
Kojto 122:f9eeca106725 12955 #define TSC_IOSCR_G3_IO4_Msk (0x1U << TSC_IOSCR_G3_IO4_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 12956 #define TSC_IOSCR_G3_IO4 TSC_IOSCR_G3_IO4_Msk /*!<GROUP3_IO4 sampling mode */
Kojto 122:f9eeca106725 12957 #define TSC_IOSCR_G4_IO1_Pos (12U)
Kojto 122:f9eeca106725 12958 #define TSC_IOSCR_G4_IO1_Msk (0x1U << TSC_IOSCR_G4_IO1_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 12959 #define TSC_IOSCR_G4_IO1 TSC_IOSCR_G4_IO1_Msk /*!<GROUP4_IO1 sampling mode */
Kojto 122:f9eeca106725 12960 #define TSC_IOSCR_G4_IO2_Pos (13U)
Kojto 122:f9eeca106725 12961 #define TSC_IOSCR_G4_IO2_Msk (0x1U << TSC_IOSCR_G4_IO2_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 12962 #define TSC_IOSCR_G4_IO2 TSC_IOSCR_G4_IO2_Msk /*!<GROUP4_IO2 sampling mode */
Kojto 122:f9eeca106725 12963 #define TSC_IOSCR_G4_IO3_Pos (14U)
Kojto 122:f9eeca106725 12964 #define TSC_IOSCR_G4_IO3_Msk (0x1U << TSC_IOSCR_G4_IO3_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 12965 #define TSC_IOSCR_G4_IO3 TSC_IOSCR_G4_IO3_Msk /*!<GROUP4_IO3 sampling mode */
Kojto 122:f9eeca106725 12966 #define TSC_IOSCR_G4_IO4_Pos (15U)
Kojto 122:f9eeca106725 12967 #define TSC_IOSCR_G4_IO4_Msk (0x1U << TSC_IOSCR_G4_IO4_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 12968 #define TSC_IOSCR_G4_IO4 TSC_IOSCR_G4_IO4_Msk /*!<GROUP4_IO4 sampling mode */
Kojto 122:f9eeca106725 12969 #define TSC_IOSCR_G5_IO1_Pos (16U)
Kojto 122:f9eeca106725 12970 #define TSC_IOSCR_G5_IO1_Msk (0x1U << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 12971 #define TSC_IOSCR_G5_IO1 TSC_IOSCR_G5_IO1_Msk /*!<GROUP5_IO1 sampling mode */
Kojto 122:f9eeca106725 12972 #define TSC_IOSCR_G5_IO2_Pos (17U)
Kojto 122:f9eeca106725 12973 #define TSC_IOSCR_G5_IO2_Msk (0x1U << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 12974 #define TSC_IOSCR_G5_IO2 TSC_IOSCR_G5_IO2_Msk /*!<GROUP5_IO2 sampling mode */
Kojto 122:f9eeca106725 12975 #define TSC_IOSCR_G5_IO3_Pos (18U)
Kojto 122:f9eeca106725 12976 #define TSC_IOSCR_G5_IO3_Msk (0x1U << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 12977 #define TSC_IOSCR_G5_IO3 TSC_IOSCR_G5_IO3_Msk /*!<GROUP5_IO3 sampling mode */
Kojto 122:f9eeca106725 12978 #define TSC_IOSCR_G5_IO4_Pos (19U)
Kojto 122:f9eeca106725 12979 #define TSC_IOSCR_G5_IO4_Msk (0x1U << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 12980 #define TSC_IOSCR_G5_IO4 TSC_IOSCR_G5_IO4_Msk /*!<GROUP5_IO4 sampling mode */
Kojto 122:f9eeca106725 12981 #define TSC_IOSCR_G6_IO1_Pos (20U)
Kojto 122:f9eeca106725 12982 #define TSC_IOSCR_G6_IO1_Msk (0x1U << TSC_IOSCR_G6_IO1_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 12983 #define TSC_IOSCR_G6_IO1 TSC_IOSCR_G6_IO1_Msk /*!<GROUP6_IO1 sampling mode */
Kojto 122:f9eeca106725 12984 #define TSC_IOSCR_G6_IO2_Pos (21U)
Kojto 122:f9eeca106725 12985 #define TSC_IOSCR_G6_IO2_Msk (0x1U << TSC_IOSCR_G6_IO2_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 12986 #define TSC_IOSCR_G6_IO2 TSC_IOSCR_G6_IO2_Msk /*!<GROUP6_IO2 sampling mode */
Kojto 122:f9eeca106725 12987 #define TSC_IOSCR_G6_IO3_Pos (22U)
Kojto 122:f9eeca106725 12988 #define TSC_IOSCR_G6_IO3_Msk (0x1U << TSC_IOSCR_G6_IO3_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 12989 #define TSC_IOSCR_G6_IO3 TSC_IOSCR_G6_IO3_Msk /*!<GROUP6_IO3 sampling mode */
Kojto 122:f9eeca106725 12990 #define TSC_IOSCR_G6_IO4_Pos (23U)
Kojto 122:f9eeca106725 12991 #define TSC_IOSCR_G6_IO4_Msk (0x1U << TSC_IOSCR_G6_IO4_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 12992 #define TSC_IOSCR_G6_IO4 TSC_IOSCR_G6_IO4_Msk /*!<GROUP6_IO4 sampling mode */
Kojto 122:f9eeca106725 12993 #define TSC_IOSCR_G7_IO1_Pos (24U)
Kojto 122:f9eeca106725 12994 #define TSC_IOSCR_G7_IO1_Msk (0x1U << TSC_IOSCR_G7_IO1_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 12995 #define TSC_IOSCR_G7_IO1 TSC_IOSCR_G7_IO1_Msk /*!<GROUP7_IO1 sampling mode */
Kojto 122:f9eeca106725 12996 #define TSC_IOSCR_G7_IO2_Pos (25U)
Kojto 122:f9eeca106725 12997 #define TSC_IOSCR_G7_IO2_Msk (0x1U << TSC_IOSCR_G7_IO2_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 12998 #define TSC_IOSCR_G7_IO2 TSC_IOSCR_G7_IO2_Msk /*!<GROUP7_IO2 sampling mode */
Kojto 122:f9eeca106725 12999 #define TSC_IOSCR_G7_IO3_Pos (26U)
Kojto 122:f9eeca106725 13000 #define TSC_IOSCR_G7_IO3_Msk (0x1U << TSC_IOSCR_G7_IO3_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 13001 #define TSC_IOSCR_G7_IO3 TSC_IOSCR_G7_IO3_Msk /*!<GROUP7_IO3 sampling mode */
Kojto 122:f9eeca106725 13002 #define TSC_IOSCR_G7_IO4_Pos (27U)
Kojto 122:f9eeca106725 13003 #define TSC_IOSCR_G7_IO4_Msk (0x1U << TSC_IOSCR_G7_IO4_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 13004 #define TSC_IOSCR_G7_IO4 TSC_IOSCR_G7_IO4_Msk /*!<GROUP7_IO4 sampling mode */
Kojto 122:f9eeca106725 13005
Kojto 122:f9eeca106725 13006 /******************* Bit definition for TSC_IOCCR register ******************/
Kojto 122:f9eeca106725 13007 #define TSC_IOCCR_G1_IO1_Pos (0U)
Kojto 122:f9eeca106725 13008 #define TSC_IOCCR_G1_IO1_Msk (0x1U << TSC_IOCCR_G1_IO1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 13009 #define TSC_IOCCR_G1_IO1 TSC_IOCCR_G1_IO1_Msk /*!<GROUP1_IO1 channel mode */
Kojto 122:f9eeca106725 13010 #define TSC_IOCCR_G1_IO2_Pos (1U)
Kojto 122:f9eeca106725 13011 #define TSC_IOCCR_G1_IO2_Msk (0x1U << TSC_IOCCR_G1_IO2_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 13012 #define TSC_IOCCR_G1_IO2 TSC_IOCCR_G1_IO2_Msk /*!<GROUP1_IO2 channel mode */
Kojto 122:f9eeca106725 13013 #define TSC_IOCCR_G1_IO3_Pos (2U)
Kojto 122:f9eeca106725 13014 #define TSC_IOCCR_G1_IO3_Msk (0x1U << TSC_IOCCR_G1_IO3_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 13015 #define TSC_IOCCR_G1_IO3 TSC_IOCCR_G1_IO3_Msk /*!<GROUP1_IO3 channel mode */
Kojto 122:f9eeca106725 13016 #define TSC_IOCCR_G1_IO4_Pos (3U)
Kojto 122:f9eeca106725 13017 #define TSC_IOCCR_G1_IO4_Msk (0x1U << TSC_IOCCR_G1_IO4_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 13018 #define TSC_IOCCR_G1_IO4 TSC_IOCCR_G1_IO4_Msk /*!<GROUP1_IO4 channel mode */
Kojto 122:f9eeca106725 13019 #define TSC_IOCCR_G2_IO1_Pos (4U)
Kojto 122:f9eeca106725 13020 #define TSC_IOCCR_G2_IO1_Msk (0x1U << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 13021 #define TSC_IOCCR_G2_IO1 TSC_IOCCR_G2_IO1_Msk /*!<GROUP2_IO1 channel mode */
Kojto 122:f9eeca106725 13022 #define TSC_IOCCR_G2_IO2_Pos (5U)
Kojto 122:f9eeca106725 13023 #define TSC_IOCCR_G2_IO2_Msk (0x1U << TSC_IOCCR_G2_IO2_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 13024 #define TSC_IOCCR_G2_IO2 TSC_IOCCR_G2_IO2_Msk /*!<GROUP2_IO2 channel mode */
Kojto 122:f9eeca106725 13025 #define TSC_IOCCR_G2_IO3_Pos (6U)
Kojto 122:f9eeca106725 13026 #define TSC_IOCCR_G2_IO3_Msk (0x1U << TSC_IOCCR_G2_IO3_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 13027 #define TSC_IOCCR_G2_IO3 TSC_IOCCR_G2_IO3_Msk /*!<GROUP2_IO3 channel mode */
Kojto 122:f9eeca106725 13028 #define TSC_IOCCR_G2_IO4_Pos (7U)
Kojto 122:f9eeca106725 13029 #define TSC_IOCCR_G2_IO4_Msk (0x1U << TSC_IOCCR_G2_IO4_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 13030 #define TSC_IOCCR_G2_IO4 TSC_IOCCR_G2_IO4_Msk /*!<GROUP2_IO4 channel mode */
Kojto 122:f9eeca106725 13031 #define TSC_IOCCR_G3_IO1_Pos (8U)
Kojto 122:f9eeca106725 13032 #define TSC_IOCCR_G3_IO1_Msk (0x1U << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 13033 #define TSC_IOCCR_G3_IO1 TSC_IOCCR_G3_IO1_Msk /*!<GROUP3_IO1 channel mode */
Kojto 122:f9eeca106725 13034 #define TSC_IOCCR_G3_IO2_Pos (9U)
Kojto 122:f9eeca106725 13035 #define TSC_IOCCR_G3_IO2_Msk (0x1U << TSC_IOCCR_G3_IO2_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 13036 #define TSC_IOCCR_G3_IO2 TSC_IOCCR_G3_IO2_Msk /*!<GROUP3_IO2 channel mode */
Kojto 122:f9eeca106725 13037 #define TSC_IOCCR_G3_IO3_Pos (10U)
Kojto 122:f9eeca106725 13038 #define TSC_IOCCR_G3_IO3_Msk (0x1U << TSC_IOCCR_G3_IO3_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 13039 #define TSC_IOCCR_G3_IO3 TSC_IOCCR_G3_IO3_Msk /*!<GROUP3_IO3 channel mode */
Kojto 122:f9eeca106725 13040 #define TSC_IOCCR_G3_IO4_Pos (11U)
Kojto 122:f9eeca106725 13041 #define TSC_IOCCR_G3_IO4_Msk (0x1U << TSC_IOCCR_G3_IO4_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 13042 #define TSC_IOCCR_G3_IO4 TSC_IOCCR_G3_IO4_Msk /*!<GROUP3_IO4 channel mode */
Kojto 122:f9eeca106725 13043 #define TSC_IOCCR_G4_IO1_Pos (12U)
Kojto 122:f9eeca106725 13044 #define TSC_IOCCR_G4_IO1_Msk (0x1U << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 13045 #define TSC_IOCCR_G4_IO1 TSC_IOCCR_G4_IO1_Msk /*!<GROUP4_IO1 channel mode */
Kojto 122:f9eeca106725 13046 #define TSC_IOCCR_G4_IO2_Pos (13U)
Kojto 122:f9eeca106725 13047 #define TSC_IOCCR_G4_IO2_Msk (0x1U << TSC_IOCCR_G4_IO2_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 13048 #define TSC_IOCCR_G4_IO2 TSC_IOCCR_G4_IO2_Msk /*!<GROUP4_IO2 channel mode */
Kojto 122:f9eeca106725 13049 #define TSC_IOCCR_G4_IO3_Pos (14U)
Kojto 122:f9eeca106725 13050 #define TSC_IOCCR_G4_IO3_Msk (0x1U << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 13051 #define TSC_IOCCR_G4_IO3 TSC_IOCCR_G4_IO3_Msk /*!<GROUP4_IO3 channel mode */
Kojto 122:f9eeca106725 13052 #define TSC_IOCCR_G4_IO4_Pos (15U)
Kojto 122:f9eeca106725 13053 #define TSC_IOCCR_G4_IO4_Msk (0x1U << TSC_IOCCR_G4_IO4_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 13054 #define TSC_IOCCR_G4_IO4 TSC_IOCCR_G4_IO4_Msk /*!<GROUP4_IO4 channel mode */
Kojto 122:f9eeca106725 13055 #define TSC_IOCCR_G5_IO1_Pos (16U)
Kojto 122:f9eeca106725 13056 #define TSC_IOCCR_G5_IO1_Msk (0x1U << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 13057 #define TSC_IOCCR_G5_IO1 TSC_IOCCR_G5_IO1_Msk /*!<GROUP5_IO1 channel mode */
Kojto 122:f9eeca106725 13058 #define TSC_IOCCR_G5_IO2_Pos (17U)
Kojto 122:f9eeca106725 13059 #define TSC_IOCCR_G5_IO2_Msk (0x1U << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 13060 #define TSC_IOCCR_G5_IO2 TSC_IOCCR_G5_IO2_Msk /*!<GROUP5_IO2 channel mode */
Kojto 122:f9eeca106725 13061 #define TSC_IOCCR_G5_IO3_Pos (18U)
Kojto 122:f9eeca106725 13062 #define TSC_IOCCR_G5_IO3_Msk (0x1U << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 13063 #define TSC_IOCCR_G5_IO3 TSC_IOCCR_G5_IO3_Msk /*!<GROUP5_IO3 channel mode */
Kojto 122:f9eeca106725 13064 #define TSC_IOCCR_G5_IO4_Pos (19U)
Kojto 122:f9eeca106725 13065 #define TSC_IOCCR_G5_IO4_Msk (0x1U << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 13066 #define TSC_IOCCR_G5_IO4 TSC_IOCCR_G5_IO4_Msk /*!<GROUP5_IO4 channel mode */
Kojto 122:f9eeca106725 13067 #define TSC_IOCCR_G6_IO1_Pos (20U)
Kojto 122:f9eeca106725 13068 #define TSC_IOCCR_G6_IO1_Msk (0x1U << TSC_IOCCR_G6_IO1_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 13069 #define TSC_IOCCR_G6_IO1 TSC_IOCCR_G6_IO1_Msk /*!<GROUP6_IO1 channel mode */
Kojto 122:f9eeca106725 13070 #define TSC_IOCCR_G6_IO2_Pos (21U)
Kojto 122:f9eeca106725 13071 #define TSC_IOCCR_G6_IO2_Msk (0x1U << TSC_IOCCR_G6_IO2_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 13072 #define TSC_IOCCR_G6_IO2 TSC_IOCCR_G6_IO2_Msk /*!<GROUP6_IO2 channel mode */
Kojto 122:f9eeca106725 13073 #define TSC_IOCCR_G6_IO3_Pos (22U)
Kojto 122:f9eeca106725 13074 #define TSC_IOCCR_G6_IO3_Msk (0x1U << TSC_IOCCR_G6_IO3_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 13075 #define TSC_IOCCR_G6_IO3 TSC_IOCCR_G6_IO3_Msk /*!<GROUP6_IO3 channel mode */
Kojto 122:f9eeca106725 13076 #define TSC_IOCCR_G6_IO4_Pos (23U)
Kojto 122:f9eeca106725 13077 #define TSC_IOCCR_G6_IO4_Msk (0x1U << TSC_IOCCR_G6_IO4_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 13078 #define TSC_IOCCR_G6_IO4 TSC_IOCCR_G6_IO4_Msk /*!<GROUP6_IO4 channel mode */
Kojto 122:f9eeca106725 13079 #define TSC_IOCCR_G7_IO1_Pos (24U)
Kojto 122:f9eeca106725 13080 #define TSC_IOCCR_G7_IO1_Msk (0x1U << TSC_IOCCR_G7_IO1_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 13081 #define TSC_IOCCR_G7_IO1 TSC_IOCCR_G7_IO1_Msk /*!<GROUP7_IO1 channel mode */
Kojto 122:f9eeca106725 13082 #define TSC_IOCCR_G7_IO2_Pos (25U)
Kojto 122:f9eeca106725 13083 #define TSC_IOCCR_G7_IO2_Msk (0x1U << TSC_IOCCR_G7_IO2_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 13084 #define TSC_IOCCR_G7_IO2 TSC_IOCCR_G7_IO2_Msk /*!<GROUP7_IO2 channel mode */
Kojto 122:f9eeca106725 13085 #define TSC_IOCCR_G7_IO3_Pos (26U)
Kojto 122:f9eeca106725 13086 #define TSC_IOCCR_G7_IO3_Msk (0x1U << TSC_IOCCR_G7_IO3_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 13087 #define TSC_IOCCR_G7_IO3 TSC_IOCCR_G7_IO3_Msk /*!<GROUP7_IO3 channel mode */
Kojto 122:f9eeca106725 13088 #define TSC_IOCCR_G7_IO4_Pos (27U)
Kojto 122:f9eeca106725 13089 #define TSC_IOCCR_G7_IO4_Msk (0x1U << TSC_IOCCR_G7_IO4_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 13090 #define TSC_IOCCR_G7_IO4 TSC_IOCCR_G7_IO4_Msk /*!<GROUP7_IO4 channel mode */
Kojto 122:f9eeca106725 13091
Kojto 122:f9eeca106725 13092 /******************* Bit definition for TSC_IOGCSR register *****************/
Kojto 122:f9eeca106725 13093 #define TSC_IOGCSR_G1E_Pos (0U)
Kojto 122:f9eeca106725 13094 #define TSC_IOGCSR_G1E_Msk (0x1U << TSC_IOGCSR_G1E_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 13095 #define TSC_IOGCSR_G1E TSC_IOGCSR_G1E_Msk /*!<Analog IO GROUP1 enable */
Kojto 122:f9eeca106725 13096 #define TSC_IOGCSR_G2E_Pos (1U)
Kojto 122:f9eeca106725 13097 #define TSC_IOGCSR_G2E_Msk (0x1U << TSC_IOGCSR_G2E_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 13098 #define TSC_IOGCSR_G2E TSC_IOGCSR_G2E_Msk /*!<Analog IO GROUP2 enable */
Kojto 122:f9eeca106725 13099 #define TSC_IOGCSR_G3E_Pos (2U)
Kojto 122:f9eeca106725 13100 #define TSC_IOGCSR_G3E_Msk (0x1U << TSC_IOGCSR_G3E_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 13101 #define TSC_IOGCSR_G3E TSC_IOGCSR_G3E_Msk /*!<Analog IO GROUP3 enable */
Kojto 122:f9eeca106725 13102 #define TSC_IOGCSR_G4E_Pos (3U)
Kojto 122:f9eeca106725 13103 #define TSC_IOGCSR_G4E_Msk (0x1U << TSC_IOGCSR_G4E_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 13104 #define TSC_IOGCSR_G4E TSC_IOGCSR_G4E_Msk /*!<Analog IO GROUP4 enable */
Kojto 122:f9eeca106725 13105 #define TSC_IOGCSR_G5E_Pos (4U)
Kojto 122:f9eeca106725 13106 #define TSC_IOGCSR_G5E_Msk (0x1U << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 13107 #define TSC_IOGCSR_G5E TSC_IOGCSR_G5E_Msk /*!<Analog IO GROUP5 enable */
Kojto 122:f9eeca106725 13108 #define TSC_IOGCSR_G6E_Pos (5U)
Kojto 122:f9eeca106725 13109 #define TSC_IOGCSR_G6E_Msk (0x1U << TSC_IOGCSR_G6E_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 13110 #define TSC_IOGCSR_G6E TSC_IOGCSR_G6E_Msk /*!<Analog IO GROUP6 enable */
Kojto 122:f9eeca106725 13111 #define TSC_IOGCSR_G7E_Pos (6U)
Kojto 122:f9eeca106725 13112 #define TSC_IOGCSR_G7E_Msk (0x1U << TSC_IOGCSR_G7E_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 13113 #define TSC_IOGCSR_G7E TSC_IOGCSR_G7E_Msk /*!<Analog IO GROUP7 enable */
Kojto 122:f9eeca106725 13114 #define TSC_IOGCSR_G1S_Pos (16U)
Kojto 122:f9eeca106725 13115 #define TSC_IOGCSR_G1S_Msk (0x1U << TSC_IOGCSR_G1S_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 13116 #define TSC_IOGCSR_G1S TSC_IOGCSR_G1S_Msk /*!<Analog IO GROUP1 status */
Kojto 122:f9eeca106725 13117 #define TSC_IOGCSR_G2S_Pos (17U)
Kojto 122:f9eeca106725 13118 #define TSC_IOGCSR_G2S_Msk (0x1U << TSC_IOGCSR_G2S_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 13119 #define TSC_IOGCSR_G2S TSC_IOGCSR_G2S_Msk /*!<Analog IO GROUP2 status */
Kojto 122:f9eeca106725 13120 #define TSC_IOGCSR_G3S_Pos (18U)
Kojto 122:f9eeca106725 13121 #define TSC_IOGCSR_G3S_Msk (0x1U << TSC_IOGCSR_G3S_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 13122 #define TSC_IOGCSR_G3S TSC_IOGCSR_G3S_Msk /*!<Analog IO GROUP3 status */
Kojto 122:f9eeca106725 13123 #define TSC_IOGCSR_G4S_Pos (19U)
Kojto 122:f9eeca106725 13124 #define TSC_IOGCSR_G4S_Msk (0x1U << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 13125 #define TSC_IOGCSR_G4S TSC_IOGCSR_G4S_Msk /*!<Analog IO GROUP4 status */
Kojto 122:f9eeca106725 13126 #define TSC_IOGCSR_G5S_Pos (20U)
Kojto 122:f9eeca106725 13127 #define TSC_IOGCSR_G5S_Msk (0x1U << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 13128 #define TSC_IOGCSR_G5S TSC_IOGCSR_G5S_Msk /*!<Analog IO GROUP5 status */
Kojto 122:f9eeca106725 13129 #define TSC_IOGCSR_G6S_Pos (21U)
Kojto 122:f9eeca106725 13130 #define TSC_IOGCSR_G6S_Msk (0x1U << TSC_IOGCSR_G6S_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 13131 #define TSC_IOGCSR_G6S TSC_IOGCSR_G6S_Msk /*!<Analog IO GROUP6 status */
Kojto 122:f9eeca106725 13132 #define TSC_IOGCSR_G7S_Pos (22U)
Kojto 122:f9eeca106725 13133 #define TSC_IOGCSR_G7S_Msk (0x1U << TSC_IOGCSR_G7S_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 13134 #define TSC_IOGCSR_G7S TSC_IOGCSR_G7S_Msk /*!<Analog IO GROUP7 status */
Kojto 122:f9eeca106725 13135
Kojto 122:f9eeca106725 13136 /******************* Bit definition for TSC_IOGXCR register *****************/
Kojto 122:f9eeca106725 13137 #define TSC_IOGXCR_CNT_Pos (0U)
Kojto 122:f9eeca106725 13138 #define TSC_IOGXCR_CNT_Msk (0x3FFFU << TSC_IOGXCR_CNT_Pos) /*!< 0x00003FFF */
Kojto 122:f9eeca106725 13139 #define TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk /*!<CNT[13:0] bits (Counter value) */
Kojto 122:f9eeca106725 13140
Kojto 122:f9eeca106725 13141 /******************************************************************************/
Kojto 122:f9eeca106725 13142 /* */
Kojto 122:f9eeca106725 13143 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
Kojto 122:f9eeca106725 13144 /* */
Kojto 122:f9eeca106725 13145 /******************************************************************************/
Kojto 122:f9eeca106725 13146
Kojto 122:f9eeca106725 13147 /*
Kojto 122:f9eeca106725 13148 * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
Kojto 122:f9eeca106725 13149 */
Kojto 122:f9eeca106725 13150
Kojto 122:f9eeca106725 13151 /* Support of TCBGT feature : Supported from USART IP version c7amba_sci3 v1.3 */
Kojto 122:f9eeca106725 13152 #define USART_TCBGT_SUPPORT
Kojto 122:f9eeca106725 13153
Kojto 122:f9eeca106725 13154 /****************** Bit definition for USART_CR1 register *******************/
Kojto 122:f9eeca106725 13155 #define USART_CR1_UE_Pos (0U)
Kojto 122:f9eeca106725 13156 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 13157 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
Kojto 122:f9eeca106725 13158 #define USART_CR1_UESM_Pos (1U)
Kojto 122:f9eeca106725 13159 #define USART_CR1_UESM_Msk (0x1U << USART_CR1_UESM_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 13160 #define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
Kojto 122:f9eeca106725 13161 #define USART_CR1_RE_Pos (2U)
Kojto 122:f9eeca106725 13162 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 13163 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
Kojto 122:f9eeca106725 13164 #define USART_CR1_TE_Pos (3U)
Kojto 122:f9eeca106725 13165 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 13166 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
Kojto 122:f9eeca106725 13167 #define USART_CR1_IDLEIE_Pos (4U)
Kojto 122:f9eeca106725 13168 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 13169 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
Kojto 122:f9eeca106725 13170 #define USART_CR1_RXNEIE_Pos (5U)
Kojto 122:f9eeca106725 13171 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 13172 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
Kojto 122:f9eeca106725 13173 #define USART_CR1_TCIE_Pos (6U)
Kojto 122:f9eeca106725 13174 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 13175 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
Kojto 122:f9eeca106725 13176 #define USART_CR1_TXEIE_Pos (7U)
Kojto 122:f9eeca106725 13177 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 13178 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
Kojto 122:f9eeca106725 13179 #define USART_CR1_PEIE_Pos (8U)
Kojto 122:f9eeca106725 13180 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 13181 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
Kojto 122:f9eeca106725 13182 #define USART_CR1_PS_Pos (9U)
Kojto 122:f9eeca106725 13183 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 13184 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
Kojto 122:f9eeca106725 13185 #define USART_CR1_PCE_Pos (10U)
Kojto 122:f9eeca106725 13186 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 13187 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
Kojto 122:f9eeca106725 13188 #define USART_CR1_WAKE_Pos (11U)
Kojto 122:f9eeca106725 13189 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 13190 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
Kojto 122:f9eeca106725 13191 #define USART_CR1_M_Pos (12U)
Kojto 122:f9eeca106725 13192 #define USART_CR1_M_Msk (0x10001U << USART_CR1_M_Pos) /*!< 0x10001000 */
Kojto 122:f9eeca106725 13193 #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
Kojto 122:f9eeca106725 13194 #define USART_CR1_M0_Pos (12U)
Kojto 122:f9eeca106725 13195 #define USART_CR1_M0_Msk (0x1U << USART_CR1_M0_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 13196 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
Kojto 122:f9eeca106725 13197 #define USART_CR1_MME_Pos (13U)
Kojto 122:f9eeca106725 13198 #define USART_CR1_MME_Msk (0x1U << USART_CR1_MME_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 13199 #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
Kojto 122:f9eeca106725 13200 #define USART_CR1_CMIE_Pos (14U)
Kojto 122:f9eeca106725 13201 #define USART_CR1_CMIE_Msk (0x1U << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 13202 #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
Kojto 122:f9eeca106725 13203 #define USART_CR1_OVER8_Pos (15U)
Kojto 122:f9eeca106725 13204 #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 13205 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
Kojto 122:f9eeca106725 13206 #define USART_CR1_DEDT_Pos (16U)
Kojto 122:f9eeca106725 13207 #define USART_CR1_DEDT_Msk (0x1FU << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
Kojto 122:f9eeca106725 13208 #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
Kojto 122:f9eeca106725 13209 #define USART_CR1_DEDT_0 (0x01U << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 13210 #define USART_CR1_DEDT_1 (0x02U << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 13211 #define USART_CR1_DEDT_2 (0x04U << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 13212 #define USART_CR1_DEDT_3 (0x08U << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 13213 #define USART_CR1_DEDT_4 (0x10U << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 13214 #define USART_CR1_DEAT_Pos (21U)
Kojto 122:f9eeca106725 13215 #define USART_CR1_DEAT_Msk (0x1FU << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
Kojto 122:f9eeca106725 13216 #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
Kojto 122:f9eeca106725 13217 #define USART_CR1_DEAT_0 (0x01U << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 13218 #define USART_CR1_DEAT_1 (0x02U << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 13219 #define USART_CR1_DEAT_2 (0x04U << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 13220 #define USART_CR1_DEAT_3 (0x08U << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 13221 #define USART_CR1_DEAT_4 (0x10U << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 13222 #define USART_CR1_RTOIE_Pos (26U)
Kojto 122:f9eeca106725 13223 #define USART_CR1_RTOIE_Msk (0x1U << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 13224 #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
Kojto 122:f9eeca106725 13225 #define USART_CR1_EOBIE_Pos (27U)
Kojto 122:f9eeca106725 13226 #define USART_CR1_EOBIE_Msk (0x1U << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 13227 #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
Kojto 122:f9eeca106725 13228 #define USART_CR1_M1_Pos (28U)
Kojto 122:f9eeca106725 13229 #define USART_CR1_M1_Msk (0x1U << USART_CR1_M1_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 13230 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
Kojto 122:f9eeca106725 13231
Kojto 122:f9eeca106725 13232 /****************** Bit definition for USART_CR2 register *******************/
Kojto 122:f9eeca106725 13233 #define USART_CR2_ADDM7_Pos (4U)
Kojto 122:f9eeca106725 13234 #define USART_CR2_ADDM7_Msk (0x1U << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 13235 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
Kojto 122:f9eeca106725 13236 #define USART_CR2_LBDL_Pos (5U)
Kojto 122:f9eeca106725 13237 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 13238 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
Kojto 122:f9eeca106725 13239 #define USART_CR2_LBDIE_Pos (6U)
Kojto 122:f9eeca106725 13240 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 13241 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
Kojto 122:f9eeca106725 13242 #define USART_CR2_LBCL_Pos (8U)
Kojto 122:f9eeca106725 13243 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 13244 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
Kojto 122:f9eeca106725 13245 #define USART_CR2_CPHA_Pos (9U)
Kojto 122:f9eeca106725 13246 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 13247 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
Kojto 122:f9eeca106725 13248 #define USART_CR2_CPOL_Pos (10U)
Kojto 122:f9eeca106725 13249 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 13250 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
Kojto 122:f9eeca106725 13251 #define USART_CR2_CLKEN_Pos (11U)
Kojto 122:f9eeca106725 13252 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 13253 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
Kojto 122:f9eeca106725 13254 #define USART_CR2_STOP_Pos (12U)
Kojto 122:f9eeca106725 13255 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
Kojto 122:f9eeca106725 13256 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
Kojto 122:f9eeca106725 13257 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 13258 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 13259 #define USART_CR2_LINEN_Pos (14U)
Kojto 122:f9eeca106725 13260 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 13261 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
Kojto 122:f9eeca106725 13262 #define USART_CR2_SWAP_Pos (15U)
Kojto 122:f9eeca106725 13263 #define USART_CR2_SWAP_Msk (0x1U << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 13264 #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
Kojto 122:f9eeca106725 13265 #define USART_CR2_RXINV_Pos (16U)
Kojto 122:f9eeca106725 13266 #define USART_CR2_RXINV_Msk (0x1U << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 13267 #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
Kojto 122:f9eeca106725 13268 #define USART_CR2_TXINV_Pos (17U)
Kojto 122:f9eeca106725 13269 #define USART_CR2_TXINV_Msk (0x1U << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 13270 #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
Kojto 122:f9eeca106725 13271 #define USART_CR2_DATAINV_Pos (18U)
Kojto 122:f9eeca106725 13272 #define USART_CR2_DATAINV_Msk (0x1U << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 13273 #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
Kojto 122:f9eeca106725 13274 #define USART_CR2_MSBFIRST_Pos (19U)
Kojto 122:f9eeca106725 13275 #define USART_CR2_MSBFIRST_Msk (0x1U << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 13276 #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
Kojto 122:f9eeca106725 13277 #define USART_CR2_ABREN_Pos (20U)
Kojto 122:f9eeca106725 13278 #define USART_CR2_ABREN_Msk (0x1U << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 13279 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
Kojto 122:f9eeca106725 13280 #define USART_CR2_ABRMODE_Pos (21U)
Kojto 122:f9eeca106725 13281 #define USART_CR2_ABRMODE_Msk (0x3U << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
Kojto 122:f9eeca106725 13282 #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
Kojto 122:f9eeca106725 13283 #define USART_CR2_ABRMODE_0 (0x1U << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 13284 #define USART_CR2_ABRMODE_1 (0x2U << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 13285 #define USART_CR2_RTOEN_Pos (23U)
Kojto 122:f9eeca106725 13286 #define USART_CR2_RTOEN_Msk (0x1U << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 13287 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
Kojto 122:f9eeca106725 13288 #define USART_CR2_ADD_Pos (24U)
Kojto 122:f9eeca106725 13289 #define USART_CR2_ADD_Msk (0xFFU << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 13290 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
Kojto 122:f9eeca106725 13291
Kojto 122:f9eeca106725 13292 /****************** Bit definition for USART_CR3 register *******************/
Kojto 122:f9eeca106725 13293 #define USART_CR3_EIE_Pos (0U)
Kojto 122:f9eeca106725 13294 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 13295 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
Kojto 122:f9eeca106725 13296 #define USART_CR3_IREN_Pos (1U)
Kojto 122:f9eeca106725 13297 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 13298 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
Kojto 122:f9eeca106725 13299 #define USART_CR3_IRLP_Pos (2U)
Kojto 122:f9eeca106725 13300 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 13301 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
Kojto 122:f9eeca106725 13302 #define USART_CR3_HDSEL_Pos (3U)
Kojto 122:f9eeca106725 13303 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 13304 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
Kojto 122:f9eeca106725 13305 #define USART_CR3_NACK_Pos (4U)
Kojto 122:f9eeca106725 13306 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 13307 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
Kojto 122:f9eeca106725 13308 #define USART_CR3_SCEN_Pos (5U)
Kojto 122:f9eeca106725 13309 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 13310 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
Kojto 122:f9eeca106725 13311 #define USART_CR3_DMAR_Pos (6U)
Kojto 122:f9eeca106725 13312 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 13313 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
Kojto 122:f9eeca106725 13314 #define USART_CR3_DMAT_Pos (7U)
Kojto 122:f9eeca106725 13315 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 13316 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
Kojto 122:f9eeca106725 13317 #define USART_CR3_RTSE_Pos (8U)
Kojto 122:f9eeca106725 13318 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 13319 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
Kojto 122:f9eeca106725 13320 #define USART_CR3_CTSE_Pos (9U)
Kojto 122:f9eeca106725 13321 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 13322 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
Kojto 122:f9eeca106725 13323 #define USART_CR3_CTSIE_Pos (10U)
Kojto 122:f9eeca106725 13324 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 13325 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
Kojto 122:f9eeca106725 13326 #define USART_CR3_ONEBIT_Pos (11U)
Kojto 122:f9eeca106725 13327 #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 13328 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
Kojto 122:f9eeca106725 13329 #define USART_CR3_OVRDIS_Pos (12U)
Kojto 122:f9eeca106725 13330 #define USART_CR3_OVRDIS_Msk (0x1U << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 13331 #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
Kojto 122:f9eeca106725 13332 #define USART_CR3_DDRE_Pos (13U)
Kojto 122:f9eeca106725 13333 #define USART_CR3_DDRE_Msk (0x1U << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 13334 #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
Kojto 122:f9eeca106725 13335 #define USART_CR3_DEM_Pos (14U)
Kojto 122:f9eeca106725 13336 #define USART_CR3_DEM_Msk (0x1U << USART_CR3_DEM_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 13337 #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
Kojto 122:f9eeca106725 13338 #define USART_CR3_DEP_Pos (15U)
Kojto 122:f9eeca106725 13339 #define USART_CR3_DEP_Msk (0x1U << USART_CR3_DEP_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 13340 #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
Kojto 122:f9eeca106725 13341 #define USART_CR3_SCARCNT_Pos (17U)
Kojto 122:f9eeca106725 13342 #define USART_CR3_SCARCNT_Msk (0x7U << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
Kojto 122:f9eeca106725 13343 #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
Kojto 122:f9eeca106725 13344 #define USART_CR3_SCARCNT_0 (0x1U << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 13345 #define USART_CR3_SCARCNT_1 (0x2U << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 13346 #define USART_CR3_SCARCNT_2 (0x4U << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 13347 #define USART_CR3_WUS_Pos (20U)
Kojto 122:f9eeca106725 13348 #define USART_CR3_WUS_Msk (0x3U << USART_CR3_WUS_Pos) /*!< 0x00300000 */
Kojto 122:f9eeca106725 13349 #define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
Kojto 122:f9eeca106725 13350 #define USART_CR3_WUS_0 (0x1U << USART_CR3_WUS_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 13351 #define USART_CR3_WUS_1 (0x2U << USART_CR3_WUS_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 13352 #define USART_CR3_WUFIE_Pos (22U)
Kojto 122:f9eeca106725 13353 #define USART_CR3_WUFIE_Msk (0x1U << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 13354 #define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
Kojto 122:f9eeca106725 13355 #define USART_CR3_TCBGTIE_Pos (24U)
Kojto 122:f9eeca106725 13356 #define USART_CR3_TCBGTIE_Msk (0x1U << USART_CR3_TCBGTIE_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 13357 #define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk /*!< Transmission Complete Before Guard Time Interrupt Enable */
Kojto 122:f9eeca106725 13358
Kojto 122:f9eeca106725 13359 /****************** Bit definition for USART_BRR register *******************/
Kojto 122:f9eeca106725 13360 #define USART_BRR_DIV_FRACTION_Pos (0U)
Kojto 122:f9eeca106725 13361 #define USART_BRR_DIV_FRACTION_Msk (0xFU << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 13362 #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
Kojto 122:f9eeca106725 13363 #define USART_BRR_DIV_MANTISSA_Pos (4U)
Kojto 122:f9eeca106725 13364 #define USART_BRR_DIV_MANTISSA_Msk (0xFFFU << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
Kojto 122:f9eeca106725 13365 #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
Kojto 122:f9eeca106725 13366
Kojto 122:f9eeca106725 13367 /****************** Bit definition for USART_GTPR register ******************/
Kojto 122:f9eeca106725 13368 #define USART_GTPR_PSC_Pos (0U)
Kojto 122:f9eeca106725 13369 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 13370 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
Kojto 122:f9eeca106725 13371 #define USART_GTPR_GT_Pos (8U)
Kojto 122:f9eeca106725 13372 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 13373 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
Kojto 122:f9eeca106725 13374
Kojto 122:f9eeca106725 13375
Kojto 122:f9eeca106725 13376 /******************* Bit definition for USART_RTOR register *****************/
Kojto 122:f9eeca106725 13377 #define USART_RTOR_RTO_Pos (0U)
Kojto 122:f9eeca106725 13378 #define USART_RTOR_RTO_Msk (0xFFFFFFU << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
Kojto 122:f9eeca106725 13379 #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
Kojto 122:f9eeca106725 13380 #define USART_RTOR_BLEN_Pos (24U)
Kojto 122:f9eeca106725 13381 #define USART_RTOR_BLEN_Msk (0xFFU << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 13382 #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
Kojto 122:f9eeca106725 13383
Kojto 122:f9eeca106725 13384 /******************* Bit definition for USART_RQR register ******************/
Kojto 122:f9eeca106725 13385 #define USART_RQR_ABRRQ_Pos (0U)
Kojto 122:f9eeca106725 13386 #define USART_RQR_ABRRQ_Msk (0x1U << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 13387 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
Kojto 122:f9eeca106725 13388 #define USART_RQR_SBKRQ_Pos (1U)
Kojto 122:f9eeca106725 13389 #define USART_RQR_SBKRQ_Msk (0x1U << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 13390 #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
Kojto 122:f9eeca106725 13391 #define USART_RQR_MMRQ_Pos (2U)
Kojto 122:f9eeca106725 13392 #define USART_RQR_MMRQ_Msk (0x1U << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 13393 #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
Kojto 122:f9eeca106725 13394 #define USART_RQR_RXFRQ_Pos (3U)
Kojto 122:f9eeca106725 13395 #define USART_RQR_RXFRQ_Msk (0x1U << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 13396 #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
Kojto 122:f9eeca106725 13397 #define USART_RQR_TXFRQ_Pos (4U)
Kojto 122:f9eeca106725 13398 #define USART_RQR_TXFRQ_Msk (0x1U << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 13399 #define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
Kojto 122:f9eeca106725 13400
Kojto 122:f9eeca106725 13401 /******************* Bit definition for USART_ISR register ******************/
Kojto 122:f9eeca106725 13402 #define USART_ISR_PE_Pos (0U)
Kojto 122:f9eeca106725 13403 #define USART_ISR_PE_Msk (0x1U << USART_ISR_PE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 13404 #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
Kojto 122:f9eeca106725 13405 #define USART_ISR_FE_Pos (1U)
Kojto 122:f9eeca106725 13406 #define USART_ISR_FE_Msk (0x1U << USART_ISR_FE_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 13407 #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
Kojto 122:f9eeca106725 13408 #define USART_ISR_NE_Pos (2U)
Kojto 122:f9eeca106725 13409 #define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 13410 #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
Kojto 122:f9eeca106725 13411 #define USART_ISR_ORE_Pos (3U)
Kojto 122:f9eeca106725 13412 #define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 13413 #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
Kojto 122:f9eeca106725 13414 #define USART_ISR_IDLE_Pos (4U)
Kojto 122:f9eeca106725 13415 #define USART_ISR_IDLE_Msk (0x1U << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 13416 #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
Kojto 122:f9eeca106725 13417 #define USART_ISR_RXNE_Pos (5U)
Kojto 122:f9eeca106725 13418 #define USART_ISR_RXNE_Msk (0x1U << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 13419 #define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
Kojto 122:f9eeca106725 13420 #define USART_ISR_TC_Pos (6U)
Kojto 122:f9eeca106725 13421 #define USART_ISR_TC_Msk (0x1U << USART_ISR_TC_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 13422 #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
Kojto 122:f9eeca106725 13423 #define USART_ISR_TXE_Pos (7U)
Kojto 122:f9eeca106725 13424 #define USART_ISR_TXE_Msk (0x1U << USART_ISR_TXE_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 13425 #define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
Kojto 122:f9eeca106725 13426 #define USART_ISR_LBDF_Pos (8U)
Kojto 122:f9eeca106725 13427 #define USART_ISR_LBDF_Msk (0x1U << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 13428 #define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
Kojto 122:f9eeca106725 13429 #define USART_ISR_CTSIF_Pos (9U)
Kojto 122:f9eeca106725 13430 #define USART_ISR_CTSIF_Msk (0x1U << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 13431 #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
Kojto 122:f9eeca106725 13432 #define USART_ISR_CTS_Pos (10U)
Kojto 122:f9eeca106725 13433 #define USART_ISR_CTS_Msk (0x1U << USART_ISR_CTS_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 13434 #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
Kojto 122:f9eeca106725 13435 #define USART_ISR_RTOF_Pos (11U)
Kojto 122:f9eeca106725 13436 #define USART_ISR_RTOF_Msk (0x1U << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 13437 #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
Kojto 122:f9eeca106725 13438 #define USART_ISR_EOBF_Pos (12U)
Kojto 122:f9eeca106725 13439 #define USART_ISR_EOBF_Msk (0x1U << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 13440 #define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
Kojto 122:f9eeca106725 13441 #define USART_ISR_ABRE_Pos (14U)
Kojto 122:f9eeca106725 13442 #define USART_ISR_ABRE_Msk (0x1U << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 13443 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
Kojto 122:f9eeca106725 13444 #define USART_ISR_ABRF_Pos (15U)
Kojto 122:f9eeca106725 13445 #define USART_ISR_ABRF_Msk (0x1U << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 13446 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
Kojto 122:f9eeca106725 13447 #define USART_ISR_BUSY_Pos (16U)
Kojto 122:f9eeca106725 13448 #define USART_ISR_BUSY_Msk (0x1U << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 13449 #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
Kojto 122:f9eeca106725 13450 #define USART_ISR_CMF_Pos (17U)
Kojto 122:f9eeca106725 13451 #define USART_ISR_CMF_Msk (0x1U << USART_ISR_CMF_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 13452 #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
Kojto 122:f9eeca106725 13453 #define USART_ISR_SBKF_Pos (18U)
Kojto 122:f9eeca106725 13454 #define USART_ISR_SBKF_Msk (0x1U << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 13455 #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
Kojto 122:f9eeca106725 13456 #define USART_ISR_RWU_Pos (19U)
Kojto 122:f9eeca106725 13457 #define USART_ISR_RWU_Msk (0x1U << USART_ISR_RWU_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 13458 #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
Kojto 122:f9eeca106725 13459 #define USART_ISR_WUF_Pos (20U)
Kojto 122:f9eeca106725 13460 #define USART_ISR_WUF_Msk (0x1U << USART_ISR_WUF_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 13461 #define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
Kojto 122:f9eeca106725 13462 #define USART_ISR_TEACK_Pos (21U)
Kojto 122:f9eeca106725 13463 #define USART_ISR_TEACK_Msk (0x1U << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 13464 #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
Kojto 122:f9eeca106725 13465 #define USART_ISR_REACK_Pos (22U)
Kojto 122:f9eeca106725 13466 #define USART_ISR_REACK_Msk (0x1U << USART_ISR_REACK_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 13467 #define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
Kojto 122:f9eeca106725 13468 #define USART_ISR_TCBGT_Pos (25U)
Kojto 122:f9eeca106725 13469 #define USART_ISR_TCBGT_Msk (0x1U << USART_ISR_TCBGT_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 13470 #define USART_ISR_TCBGT USART_ISR_TCBGT_Msk /*!< Transmission Complete Before Guard Time Completion Flag */
Kojto 122:f9eeca106725 13471
Kojto 122:f9eeca106725 13472 /******************* Bit definition for USART_ICR register ******************/
Kojto 122:f9eeca106725 13473 #define USART_ICR_PECF_Pos (0U)
Kojto 122:f9eeca106725 13474 #define USART_ICR_PECF_Msk (0x1U << USART_ICR_PECF_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 13475 #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
Kojto 122:f9eeca106725 13476 #define USART_ICR_FECF_Pos (1U)
Kojto 122:f9eeca106725 13477 #define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 13478 #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
Kojto 122:f9eeca106725 13479 #define USART_ICR_NCF_Pos (2U)
Kojto 122:f9eeca106725 13480 #define USART_ICR_NCF_Msk (0x1U << USART_ICR_NCF_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 13481 #define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
Kojto 122:f9eeca106725 13482 #define USART_ICR_ORECF_Pos (3U)
Kojto 122:f9eeca106725 13483 #define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 13484 #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
Kojto 122:f9eeca106725 13485 #define USART_ICR_IDLECF_Pos (4U)
Kojto 122:f9eeca106725 13486 #define USART_ICR_IDLECF_Msk (0x1U << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 13487 #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
Kojto 122:f9eeca106725 13488 #define USART_ICR_TCCF_Pos (6U)
Kojto 122:f9eeca106725 13489 #define USART_ICR_TCCF_Msk (0x1U << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 13490 #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
Kojto 122:f9eeca106725 13491 #define USART_ICR_TCBGTCF_Pos (7U)
Kojto 122:f9eeca106725 13492 #define USART_ICR_TCBGTCF_Msk (0x1U << USART_ICR_TCBGTCF_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 13493 #define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk /*!< Transmission Complete Before Guard Time Clear Flag */
Kojto 122:f9eeca106725 13494 #define USART_ICR_LBDCF_Pos (8U)
Kojto 122:f9eeca106725 13495 #define USART_ICR_LBDCF_Msk (0x1U << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 13496 #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
Kojto 122:f9eeca106725 13497 #define USART_ICR_CTSCF_Pos (9U)
Kojto 122:f9eeca106725 13498 #define USART_ICR_CTSCF_Msk (0x1U << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 13499 #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
Kojto 122:f9eeca106725 13500 #define USART_ICR_RTOCF_Pos (11U)
Kojto 122:f9eeca106725 13501 #define USART_ICR_RTOCF_Msk (0x1U << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 13502 #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
Kojto 122:f9eeca106725 13503 #define USART_ICR_EOBCF_Pos (12U)
Kojto 122:f9eeca106725 13504 #define USART_ICR_EOBCF_Msk (0x1U << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 13505 #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
Kojto 122:f9eeca106725 13506 #define USART_ICR_CMCF_Pos (17U)
Kojto 122:f9eeca106725 13507 #define USART_ICR_CMCF_Msk (0x1U << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 13508 #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
Kojto 122:f9eeca106725 13509 #define USART_ICR_WUCF_Pos (20U)
Kojto 122:f9eeca106725 13510 #define USART_ICR_WUCF_Msk (0x1U << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 13511 #define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
Kojto 122:f9eeca106725 13512
Kojto 122:f9eeca106725 13513 /******************* Bit definition for USART_RDR register ******************/
Kojto 122:f9eeca106725 13514 #define USART_RDR_RDR_Pos (0U)
Kojto 122:f9eeca106725 13515 #define USART_RDR_RDR_Msk (0x1FFU << USART_RDR_RDR_Pos) /*!< 0x000001FF */
Kojto 122:f9eeca106725 13516 #define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
Kojto 122:f9eeca106725 13517
Kojto 122:f9eeca106725 13518 /******************* Bit definition for USART_TDR register ******************/
Kojto 122:f9eeca106725 13519 #define USART_TDR_TDR_Pos (0U)
Kojto 122:f9eeca106725 13520 #define USART_TDR_TDR_Msk (0x1FFU << USART_TDR_TDR_Pos) /*!< 0x000001FF */
Kojto 122:f9eeca106725 13521 #define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
Kojto 122:f9eeca106725 13522
Kojto 122:f9eeca106725 13523 /******************************************************************************/
Kojto 122:f9eeca106725 13524 /* */
Kojto 122:f9eeca106725 13525 /* Single Wire Protocol Master Interface (SWPMI) */
Kojto 122:f9eeca106725 13526 /* */
Kojto 122:f9eeca106725 13527 /******************************************************************************/
Kojto 122:f9eeca106725 13528
Kojto 122:f9eeca106725 13529 /******************* Bit definition for SWPMI_CR register ********************/
Kojto 122:f9eeca106725 13530 #define SWPMI_CR_RXDMA_Pos (0U)
Kojto 122:f9eeca106725 13531 #define SWPMI_CR_RXDMA_Msk (0x1U << SWPMI_CR_RXDMA_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 13532 #define SWPMI_CR_RXDMA SWPMI_CR_RXDMA_Msk /*!<Reception DMA enable */
Kojto 122:f9eeca106725 13533 #define SWPMI_CR_TXDMA_Pos (1U)
Kojto 122:f9eeca106725 13534 #define SWPMI_CR_TXDMA_Msk (0x1U << SWPMI_CR_TXDMA_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 13535 #define SWPMI_CR_TXDMA SWPMI_CR_TXDMA_Msk /*!<Transmission DMA enable */
Kojto 122:f9eeca106725 13536 #define SWPMI_CR_RXMODE_Pos (2U)
Kojto 122:f9eeca106725 13537 #define SWPMI_CR_RXMODE_Msk (0x1U << SWPMI_CR_RXMODE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 13538 #define SWPMI_CR_RXMODE SWPMI_CR_RXMODE_Msk /*!<Reception buffering mode */
Kojto 122:f9eeca106725 13539 #define SWPMI_CR_TXMODE_Pos (3U)
Kojto 122:f9eeca106725 13540 #define SWPMI_CR_TXMODE_Msk (0x1U << SWPMI_CR_TXMODE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 13541 #define SWPMI_CR_TXMODE SWPMI_CR_TXMODE_Msk /*!<Transmission buffering mode */
Kojto 122:f9eeca106725 13542 #define SWPMI_CR_LPBK_Pos (4U)
Kojto 122:f9eeca106725 13543 #define SWPMI_CR_LPBK_Msk (0x1U << SWPMI_CR_LPBK_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 13544 #define SWPMI_CR_LPBK SWPMI_CR_LPBK_Msk /*!<Loopback mode enable */
Kojto 122:f9eeca106725 13545 #define SWPMI_CR_SWPACT_Pos (5U)
Kojto 122:f9eeca106725 13546 #define SWPMI_CR_SWPACT_Msk (0x1U << SWPMI_CR_SWPACT_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 13547 #define SWPMI_CR_SWPACT SWPMI_CR_SWPACT_Msk /*!<Single wire protocol master interface activate */
Kojto 122:f9eeca106725 13548 #define SWPMI_CR_DEACT_Pos (10U)
Kojto 122:f9eeca106725 13549 #define SWPMI_CR_DEACT_Msk (0x1U << SWPMI_CR_DEACT_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 13550 #define SWPMI_CR_DEACT SWPMI_CR_DEACT_Msk /*!<Single wire protocol master interface deactivate */
Kojto 122:f9eeca106725 13551
Kojto 122:f9eeca106725 13552 /******************* Bit definition for SWPMI_BRR register ********************/
Kojto 122:f9eeca106725 13553 #define SWPMI_BRR_BR_Pos (0U)
Kojto 122:f9eeca106725 13554 #define SWPMI_BRR_BR_Msk (0x3FU << SWPMI_BRR_BR_Pos) /*!< 0x0000003F */
Kojto 122:f9eeca106725 13555 #define SWPMI_BRR_BR SWPMI_BRR_BR_Msk /*!<BR[5:0] bits (Bitrate prescaler) */
Kojto 122:f9eeca106725 13556
Kojto 122:f9eeca106725 13557 /******************* Bit definition for SWPMI_ISR register ********************/
Kojto 122:f9eeca106725 13558 #define SWPMI_ISR_RXBFF_Pos (0U)
Kojto 122:f9eeca106725 13559 #define SWPMI_ISR_RXBFF_Msk (0x1U << SWPMI_ISR_RXBFF_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 13560 #define SWPMI_ISR_RXBFF SWPMI_ISR_RXBFF_Msk /*!<Receive buffer full flag */
Kojto 122:f9eeca106725 13561 #define SWPMI_ISR_TXBEF_Pos (1U)
Kojto 122:f9eeca106725 13562 #define SWPMI_ISR_TXBEF_Msk (0x1U << SWPMI_ISR_TXBEF_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 13563 #define SWPMI_ISR_TXBEF SWPMI_ISR_TXBEF_Msk /*!<Transmit buffer empty flag */
Kojto 122:f9eeca106725 13564 #define SWPMI_ISR_RXBERF_Pos (2U)
Kojto 122:f9eeca106725 13565 #define SWPMI_ISR_RXBERF_Msk (0x1U << SWPMI_ISR_RXBERF_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 13566 #define SWPMI_ISR_RXBERF SWPMI_ISR_RXBERF_Msk /*!<Receive CRC error flag */
Kojto 122:f9eeca106725 13567 #define SWPMI_ISR_RXOVRF_Pos (3U)
Kojto 122:f9eeca106725 13568 #define SWPMI_ISR_RXOVRF_Msk (0x1U << SWPMI_ISR_RXOVRF_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 13569 #define SWPMI_ISR_RXOVRF SWPMI_ISR_RXOVRF_Msk /*!<Receive overrun error flag */
Kojto 122:f9eeca106725 13570 #define SWPMI_ISR_TXUNRF_Pos (4U)
Kojto 122:f9eeca106725 13571 #define SWPMI_ISR_TXUNRF_Msk (0x1U << SWPMI_ISR_TXUNRF_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 13572 #define SWPMI_ISR_TXUNRF SWPMI_ISR_TXUNRF_Msk /*!<Transmit underrun error flag */
Kojto 122:f9eeca106725 13573 #define SWPMI_ISR_RXNE_Pos (5U)
Kojto 122:f9eeca106725 13574 #define SWPMI_ISR_RXNE_Msk (0x1U << SWPMI_ISR_RXNE_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 13575 #define SWPMI_ISR_RXNE SWPMI_ISR_RXNE_Msk /*!<Receive data register not empty */
Kojto 122:f9eeca106725 13576 #define SWPMI_ISR_TXE_Pos (6U)
Kojto 122:f9eeca106725 13577 #define SWPMI_ISR_TXE_Msk (0x1U << SWPMI_ISR_TXE_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 13578 #define SWPMI_ISR_TXE SWPMI_ISR_TXE_Msk /*!<Transmit data register empty */
Kojto 122:f9eeca106725 13579 #define SWPMI_ISR_TCF_Pos (7U)
Kojto 122:f9eeca106725 13580 #define SWPMI_ISR_TCF_Msk (0x1U << SWPMI_ISR_TCF_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 13581 #define SWPMI_ISR_TCF SWPMI_ISR_TCF_Msk /*!<Transfer complete flag */
Kojto 122:f9eeca106725 13582 #define SWPMI_ISR_SRF_Pos (8U)
Kojto 122:f9eeca106725 13583 #define SWPMI_ISR_SRF_Msk (0x1U << SWPMI_ISR_SRF_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 13584 #define SWPMI_ISR_SRF SWPMI_ISR_SRF_Msk /*!<Slave resume flag */
Kojto 122:f9eeca106725 13585 #define SWPMI_ISR_SUSP_Pos (9U)
Kojto 122:f9eeca106725 13586 #define SWPMI_ISR_SUSP_Msk (0x1U << SWPMI_ISR_SUSP_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 13587 #define SWPMI_ISR_SUSP SWPMI_ISR_SUSP_Msk /*!<SUSPEND flag */
Kojto 122:f9eeca106725 13588 #define SWPMI_ISR_DEACTF_Pos (10U)
Kojto 122:f9eeca106725 13589 #define SWPMI_ISR_DEACTF_Msk (0x1U << SWPMI_ISR_DEACTF_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 13590 #define SWPMI_ISR_DEACTF SWPMI_ISR_DEACTF_Msk /*!<DEACTIVATED flag */
Kojto 122:f9eeca106725 13591
Kojto 122:f9eeca106725 13592 /******************* Bit definition for SWPMI_ICR register ********************/
Kojto 122:f9eeca106725 13593 #define SWPMI_ICR_CRXBFF_Pos (0U)
Kojto 122:f9eeca106725 13594 #define SWPMI_ICR_CRXBFF_Msk (0x1U << SWPMI_ICR_CRXBFF_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 13595 #define SWPMI_ICR_CRXBFF SWPMI_ICR_CRXBFF_Msk /*!<Clear receive buffer full flag */
Kojto 122:f9eeca106725 13596 #define SWPMI_ICR_CTXBEF_Pos (1U)
Kojto 122:f9eeca106725 13597 #define SWPMI_ICR_CTXBEF_Msk (0x1U << SWPMI_ICR_CTXBEF_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 13598 #define SWPMI_ICR_CTXBEF SWPMI_ICR_CTXBEF_Msk /*!<Clear transmit buffer empty flag */
Kojto 122:f9eeca106725 13599 #define SWPMI_ICR_CRXBERF_Pos (2U)
Kojto 122:f9eeca106725 13600 #define SWPMI_ICR_CRXBERF_Msk (0x1U << SWPMI_ICR_CRXBERF_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 13601 #define SWPMI_ICR_CRXBERF SWPMI_ICR_CRXBERF_Msk /*!<Clear receive CRC error flag */
Kojto 122:f9eeca106725 13602 #define SWPMI_ICR_CRXOVRF_Pos (3U)
Kojto 122:f9eeca106725 13603 #define SWPMI_ICR_CRXOVRF_Msk (0x1U << SWPMI_ICR_CRXOVRF_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 13604 #define SWPMI_ICR_CRXOVRF SWPMI_ICR_CRXOVRF_Msk /*!<Clear receive overrun error flag */
Kojto 122:f9eeca106725 13605 #define SWPMI_ICR_CTXUNRF_Pos (4U)
Kojto 122:f9eeca106725 13606 #define SWPMI_ICR_CTXUNRF_Msk (0x1U << SWPMI_ICR_CTXUNRF_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 13607 #define SWPMI_ICR_CTXUNRF SWPMI_ICR_CTXUNRF_Msk /*!<Clear transmit underrun error flag */
Kojto 122:f9eeca106725 13608 #define SWPMI_ICR_CTCF_Pos (7U)
Kojto 122:f9eeca106725 13609 #define SWPMI_ICR_CTCF_Msk (0x1U << SWPMI_ICR_CTCF_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 13610 #define SWPMI_ICR_CTCF SWPMI_ICR_CTCF_Msk /*!<Clear transfer complete flag */
Kojto 122:f9eeca106725 13611 #define SWPMI_ICR_CSRF_Pos (8U)
Kojto 122:f9eeca106725 13612 #define SWPMI_ICR_CSRF_Msk (0x1U << SWPMI_ICR_CSRF_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 13613 #define SWPMI_ICR_CSRF SWPMI_ICR_CSRF_Msk /*!<Clear slave resume flag */
Kojto 122:f9eeca106725 13614
Kojto 122:f9eeca106725 13615 /******************* Bit definition for SWPMI_IER register ********************/
Kojto 122:f9eeca106725 13616 #define SWPMI_IER_SRIE_Pos (8U)
Kojto 122:f9eeca106725 13617 #define SWPMI_IER_SRIE_Msk (0x1U << SWPMI_IER_SRIE_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 13618 #define SWPMI_IER_SRIE SWPMI_IER_SRIE_Msk /*!<Slave resume interrupt enable */
Kojto 122:f9eeca106725 13619 #define SWPMI_IER_TCIE_Pos (7U)
Kojto 122:f9eeca106725 13620 #define SWPMI_IER_TCIE_Msk (0x1U << SWPMI_IER_TCIE_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 13621 #define SWPMI_IER_TCIE SWPMI_IER_TCIE_Msk /*!<Transmit complete interrupt enable */
Kojto 122:f9eeca106725 13622 #define SWPMI_IER_TIE_Pos (6U)
Kojto 122:f9eeca106725 13623 #define SWPMI_IER_TIE_Msk (0x1U << SWPMI_IER_TIE_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 13624 #define SWPMI_IER_TIE SWPMI_IER_TIE_Msk /*!<Transmit interrupt enable */
Kojto 122:f9eeca106725 13625 #define SWPMI_IER_RIE_Pos (5U)
Kojto 122:f9eeca106725 13626 #define SWPMI_IER_RIE_Msk (0x1U << SWPMI_IER_RIE_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 13627 #define SWPMI_IER_RIE SWPMI_IER_RIE_Msk /*!<Receive interrupt enable */
Kojto 122:f9eeca106725 13628 #define SWPMI_IER_TXUNRIE_Pos (4U)
Kojto 122:f9eeca106725 13629 #define SWPMI_IER_TXUNRIE_Msk (0x1U << SWPMI_IER_TXUNRIE_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 13630 #define SWPMI_IER_TXUNRIE SWPMI_IER_TXUNRIE_Msk /*!<Transmit underrun error interrupt enable */
Kojto 122:f9eeca106725 13631 #define SWPMI_IER_RXOVRIE_Pos (3U)
Kojto 122:f9eeca106725 13632 #define SWPMI_IER_RXOVRIE_Msk (0x1U << SWPMI_IER_RXOVRIE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 13633 #define SWPMI_IER_RXOVRIE SWPMI_IER_RXOVRIE_Msk /*!<Receive overrun error interrupt enable */
Kojto 122:f9eeca106725 13634 #define SWPMI_IER_RXBERIE_Pos (2U)
Kojto 122:f9eeca106725 13635 #define SWPMI_IER_RXBERIE_Msk (0x1U << SWPMI_IER_RXBERIE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 13636 #define SWPMI_IER_RXBERIE SWPMI_IER_RXBERIE_Msk /*!<Receive CRC error interrupt enable */
Kojto 122:f9eeca106725 13637 #define SWPMI_IER_TXBEIE_Pos (1U)
Kojto 122:f9eeca106725 13638 #define SWPMI_IER_TXBEIE_Msk (0x1U << SWPMI_IER_TXBEIE_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 13639 #define SWPMI_IER_TXBEIE SWPMI_IER_TXBEIE_Msk /*!<Transmit buffer empty interrupt enable */
Kojto 122:f9eeca106725 13640 #define SWPMI_IER_RXBFIE_Pos (0U)
Kojto 122:f9eeca106725 13641 #define SWPMI_IER_RXBFIE_Msk (0x1U << SWPMI_IER_RXBFIE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 13642 #define SWPMI_IER_RXBFIE SWPMI_IER_RXBFIE_Msk /*!<Receive buffer full interrupt enable */
Kojto 122:f9eeca106725 13643
Kojto 122:f9eeca106725 13644 /******************* Bit definition for SWPMI_RFL register ********************/
Kojto 122:f9eeca106725 13645 #define SWPMI_RFL_RFL_Pos (0U)
Kojto 122:f9eeca106725 13646 #define SWPMI_RFL_RFL_Msk (0x1FU << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */
Kojto 122:f9eeca106725 13647 #define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */
Kojto 122:f9eeca106725 13648 #define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
Kojto 122:f9eeca106725 13649
Kojto 122:f9eeca106725 13650 /******************* Bit definition for SWPMI_TDR register ********************/
Kojto 122:f9eeca106725 13651 #define SWPMI_TDR_TD_Pos (0U)
Kojto 122:f9eeca106725 13652 #define SWPMI_TDR_TD_Msk (0xFFFFFFFFU << SWPMI_TDR_TD_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 13653 #define SWPMI_TDR_TD SWPMI_TDR_TD_Msk /*!<Transmit Data Register */
Kojto 122:f9eeca106725 13654
Kojto 122:f9eeca106725 13655 /******************* Bit definition for SWPMI_RDR register ********************/
Kojto 122:f9eeca106725 13656 #define SWPMI_RDR_RD_Pos (0U)
Kojto 122:f9eeca106725 13657 #define SWPMI_RDR_RD_Msk (0xFFFFFFFFU << SWPMI_RDR_RD_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 13658 #define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Receive Data Register */
Kojto 122:f9eeca106725 13659
Kojto 122:f9eeca106725 13660 /******************* Bit definition for SWPMI_OR register ********************/
Kojto 122:f9eeca106725 13661 #define SWPMI_OR_TBYP_Pos (0U)
Kojto 122:f9eeca106725 13662 #define SWPMI_OR_TBYP_Msk (0x1U << SWPMI_OR_TBYP_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 13663 #define SWPMI_OR_TBYP SWPMI_OR_TBYP_Msk /*!<SWP Transceiver Bypass */
Kojto 122:f9eeca106725 13664 #define SWPMI_OR_CLASS_Pos (1U)
Kojto 122:f9eeca106725 13665 #define SWPMI_OR_CLASS_Msk (0x1U << SWPMI_OR_CLASS_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 13666 #define SWPMI_OR_CLASS SWPMI_OR_CLASS_Msk /*!<SWP Voltage Class selection */
Kojto 122:f9eeca106725 13667
Kojto 122:f9eeca106725 13668
Kojto 122:f9eeca106725 13669 /******************************************************************************/
Kojto 122:f9eeca106725 13670 /* */
Kojto 122:f9eeca106725 13671 /* Window WATCHDOG */
Kojto 122:f9eeca106725 13672 /* */
Kojto 122:f9eeca106725 13673 /******************************************************************************/
Kojto 122:f9eeca106725 13674 /******************* Bit definition for WWDG_CR register ********************/
Kojto 122:f9eeca106725 13675 #define WWDG_CR_T_Pos (0U)
Kojto 122:f9eeca106725 13676 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
Kojto 122:f9eeca106725 13677 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
Kojto 122:f9eeca106725 13678 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 13679 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 13680 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 13681 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 13682 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 13683 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 13684 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 13685
Kojto 122:f9eeca106725 13686 #define WWDG_CR_WDGA_Pos (7U)
Kojto 122:f9eeca106725 13687 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 13688 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
Kojto 122:f9eeca106725 13689
Kojto 122:f9eeca106725 13690 /******************* Bit definition for WWDG_CFR register *******************/
Kojto 122:f9eeca106725 13691 #define WWDG_CFR_W_Pos (0U)
Kojto 122:f9eeca106725 13692 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
Kojto 122:f9eeca106725 13693 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
Kojto 122:f9eeca106725 13694 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 13695 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 13696 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 13697 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 13698 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 13699 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 13700 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 13701
Kojto 122:f9eeca106725 13702 #define WWDG_CFR_WDGTB_Pos (7U)
Kojto 122:f9eeca106725 13703 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
Kojto 122:f9eeca106725 13704 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
Kojto 122:f9eeca106725 13705 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 13706 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 13707
Kojto 122:f9eeca106725 13708 #define WWDG_CFR_EWI_Pos (9U)
Kojto 122:f9eeca106725 13709 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 13710 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
Kojto 122:f9eeca106725 13711
Kojto 122:f9eeca106725 13712 /******************* Bit definition for WWDG_SR register ********************/
Kojto 122:f9eeca106725 13713 #define WWDG_SR_EWIF_Pos (0U)
Kojto 122:f9eeca106725 13714 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 13715 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
Kojto 122:f9eeca106725 13716
Kojto 122:f9eeca106725 13717
Kojto 122:f9eeca106725 13718 /******************************************************************************/
Kojto 122:f9eeca106725 13719 /* */
Kojto 122:f9eeca106725 13720 /* Debug MCU */
Kojto 122:f9eeca106725 13721 /* */
Kojto 122:f9eeca106725 13722 /******************************************************************************/
Kojto 122:f9eeca106725 13723 /******************** Bit definition for DBGMCU_IDCODE register *************/
Kojto 122:f9eeca106725 13724 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
Kojto 122:f9eeca106725 13725 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
Kojto 122:f9eeca106725 13726 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
Kojto 122:f9eeca106725 13727 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
Kojto 122:f9eeca106725 13728 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
Kojto 122:f9eeca106725 13729 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
Kojto 122:f9eeca106725 13730
Kojto 122:f9eeca106725 13731 /******************** Bit definition for DBGMCU_CR register *****************/
Kojto 122:f9eeca106725 13732 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
Kojto 122:f9eeca106725 13733 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 13734 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
Kojto 122:f9eeca106725 13735 #define DBGMCU_CR_DBG_STOP_Pos (1U)
Kojto 122:f9eeca106725 13736 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 13737 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
Kojto 122:f9eeca106725 13738 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
Kojto 122:f9eeca106725 13739 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 13740 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
Kojto 122:f9eeca106725 13741 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
Kojto 122:f9eeca106725 13742 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 13743 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
Kojto 122:f9eeca106725 13744
Kojto 122:f9eeca106725 13745 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
Kojto 122:f9eeca106725 13746 #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
Kojto 122:f9eeca106725 13747 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
Kojto 122:f9eeca106725 13748 #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 13749 #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 13750
Kojto 122:f9eeca106725 13751 /******************** Bit definition for DBGMCU_APB1FZR1 register ***********/
Kojto 122:f9eeca106725 13752 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U)
Kojto 122:f9eeca106725 13753 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 13754 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk
Kojto 122:f9eeca106725 13755 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos (4U)
Kojto 122:f9eeca106725 13756 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 13757 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk
Kojto 122:f9eeca106725 13758 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos (5U)
Kojto 122:f9eeca106725 13759 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 13760 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk
Kojto 122:f9eeca106725 13761 #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos (10U)
Kojto 122:f9eeca106725 13762 #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 13763 #define DBGMCU_APB1FZR1_DBG_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk
Kojto 122:f9eeca106725 13764 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos (11U)
Kojto 122:f9eeca106725 13765 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 13766 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk
Kojto 122:f9eeca106725 13767 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos (12U)
Kojto 122:f9eeca106725 13768 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 13769 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk
Kojto 122:f9eeca106725 13770 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos (21U)
Kojto 122:f9eeca106725 13771 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 13772 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk
Kojto 122:f9eeca106725 13773 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos (23U)
Kojto 122:f9eeca106725 13774 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 13775 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk
Kojto 122:f9eeca106725 13776 #define DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos (25U)
Kojto 122:f9eeca106725 13777 #define DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 13778 #define DBGMCU_APB1FZR1_DBG_CAN_STOP DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk
Kojto 122:f9eeca106725 13779 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos (31U)
Kojto 122:f9eeca106725 13780 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 13781 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk
Kojto 122:f9eeca106725 13782
Kojto 122:f9eeca106725 13783 /******************** Bit definition for DBGMCU_APB1FZR2 register **********/
Kojto 122:f9eeca106725 13784 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos (5U)
Kojto 122:f9eeca106725 13785 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk (0x1U << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 13786 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk
Kojto 122:f9eeca106725 13787
Kojto 122:f9eeca106725 13788 /******************** Bit definition for DBGMCU_APB2FZ register ************/
Kojto 122:f9eeca106725 13789 #define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos (11U)
Kojto 122:f9eeca106725 13790 #define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 13791 #define DBGMCU_APB2FZ_DBG_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk
Kojto 122:f9eeca106725 13792 #define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos (16U)
Kojto 122:f9eeca106725 13793 #define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 13794 #define DBGMCU_APB2FZ_DBG_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk
Kojto 122:f9eeca106725 13795 #define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos (17U)
Kojto 122:f9eeca106725 13796 #define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 13797 #define DBGMCU_APB2FZ_DBG_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk
Kojto 122:f9eeca106725 13798
Kojto 122:f9eeca106725 13799 /******************************************************************************/
Kojto 122:f9eeca106725 13800 /* */
Kojto 122:f9eeca106725 13801 /* USB Device FS Endpoint registers */
Kojto 122:f9eeca106725 13802 /* */
Kojto 122:f9eeca106725 13803 /******************************************************************************/
Kojto 122:f9eeca106725 13804 #define USB_EP0R USB_BASE /*!< endpoint 0 register address */
Kojto 122:f9eeca106725 13805 #define USB_EP1R (USB_BASE + 0x0x00000004) /*!< endpoint 1 register address */
Kojto 122:f9eeca106725 13806 #define USB_EP2R (USB_BASE + 0x0x00000008) /*!< endpoint 2 register address */
Kojto 122:f9eeca106725 13807 #define USB_EP3R (USB_BASE + 0x0x0000000C) /*!< endpoint 3 register address */
Kojto 122:f9eeca106725 13808 #define USB_EP4R (USB_BASE + 0x0x00000010) /*!< endpoint 4 register address */
Kojto 122:f9eeca106725 13809 #define USB_EP5R (USB_BASE + 0x0x00000014) /*!< endpoint 5 register address */
Kojto 122:f9eeca106725 13810 #define USB_EP6R (USB_BASE + 0x0x00000018) /*!< endpoint 6 register address */
Kojto 122:f9eeca106725 13811 #define USB_EP7R (USB_BASE + 0x0x0000001C) /*!< endpoint 7 register address */
Kojto 122:f9eeca106725 13812
Kojto 122:f9eeca106725 13813 /* bit positions */
Kojto 122:f9eeca106725 13814 #define USB_EP_CTR_RX ((uint16_t)0x8000U) /*!< EndPoint Correct TRansfer RX */
Kojto 122:f9eeca106725 13815 #define USB_EP_DTOG_RX ((uint16_t)0x4000U) /*!< EndPoint Data TOGGLE RX */
Kojto 122:f9eeca106725 13816 #define USB_EPRX_STAT ((uint16_t)0x3000U) /*!< EndPoint RX STATus bit field */
Kojto 122:f9eeca106725 13817 #define USB_EP_SETUP ((uint16_t)0x0800U) /*!< EndPoint SETUP */
Kojto 122:f9eeca106725 13818 #define USB_EP_T_FIELD ((uint16_t)0x0600U) /*!< EndPoint TYPE */
Kojto 122:f9eeca106725 13819 #define USB_EP_KIND ((uint16_t)0x0100U) /*!< EndPoint KIND */
Kojto 122:f9eeca106725 13820 #define USB_EP_CTR_TX ((uint16_t)0x0080U) /*!< EndPoint Correct TRansfer TX */
Kojto 122:f9eeca106725 13821 #define USB_EP_DTOG_TX ((uint16_t)0x0040U) /*!< EndPoint Data TOGGLE TX */
Kojto 122:f9eeca106725 13822 #define USB_EPTX_STAT ((uint16_t)0x0030U) /*!< EndPoint TX STATus bit field */
Kojto 122:f9eeca106725 13823 #define USB_EPADDR_FIELD ((uint16_t)0x000FU) /*!< EndPoint ADDRess FIELD */
Kojto 122:f9eeca106725 13824
Kojto 122:f9eeca106725 13825 /* EndPoint REGister MASK (no toggle fields) */
Kojto 122:f9eeca106725 13826 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
Kojto 122:f9eeca106725 13827 /*!< EP_TYPE[1:0] EndPoint TYPE */
Kojto 122:f9eeca106725 13828 #define USB_EP_TYPE_MASK ((uint16_t)0x0600U) /*!< EndPoint TYPE Mask */
Kojto 122:f9eeca106725 13829 #define USB_EP_BULK ((uint16_t)0x0000U) /*!< EndPoint BULK */
Kojto 122:f9eeca106725 13830 #define USB_EP_CONTROL ((uint16_t)0x0200U) /*!< EndPoint CONTROL */
Kojto 122:f9eeca106725 13831 #define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /*!< EndPoint ISOCHRONOUS */
Kojto 122:f9eeca106725 13832 #define USB_EP_INTERRUPT ((uint16_t)0x0600U) /*!< EndPoint INTERRUPT */
Kojto 122:f9eeca106725 13833 #define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
Kojto 122:f9eeca106725 13834
Kojto 122:f9eeca106725 13835 #define USB_EPKIND_MASK ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
Kojto 122:f9eeca106725 13836 /*!< STAT_TX[1:0] STATus for TX transfer */
Kojto 122:f9eeca106725 13837 #define USB_EP_TX_DIS ((uint16_t)0x0000U) /*!< EndPoint TX DISabled */
Kojto 122:f9eeca106725 13838 #define USB_EP_TX_STALL ((uint16_t)0x0010U) /*!< EndPoint TX STALLed */
Kojto 122:f9eeca106725 13839 #define USB_EP_TX_NAK ((uint16_t)0x0020U) /*!< EndPoint TX NAKed */
Kojto 122:f9eeca106725 13840 #define USB_EP_TX_VALID ((uint16_t)0x0030U) /*!< EndPoint TX VALID */
Kojto 122:f9eeca106725 13841 #define USB_EPTX_DTOG1 ((uint16_t)0x0010U) /*!< EndPoint TX Data TOGgle bit1 */
Kojto 122:f9eeca106725 13842 #define USB_EPTX_DTOG2 ((uint16_t)0x0020U) /*!< EndPoint TX Data TOGgle bit2 */
Kojto 122:f9eeca106725 13843 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
Kojto 122:f9eeca106725 13844 /*!< STAT_RX[1:0] STATus for RX transfer */
Kojto 122:f9eeca106725 13845 #define USB_EP_RX_DIS ((uint16_t)0x0000U) /*!< EndPoint RX DISabled */
Kojto 122:f9eeca106725 13846 #define USB_EP_RX_STALL ((uint16_t)0x1000U) /*!< EndPoint RX STALLed */
Kojto 122:f9eeca106725 13847 #define USB_EP_RX_NAK ((uint16_t)0x2000U) /*!< EndPoint RX NAKed */
Kojto 122:f9eeca106725 13848 #define USB_EP_RX_VALID ((uint16_t)0x3000U) /*!< EndPoint RX VALID */
Kojto 122:f9eeca106725 13849 #define USB_EPRX_DTOG1 ((uint16_t)0x1000U) /*!< EndPoint RX Data TOGgle bit1 */
Kojto 122:f9eeca106725 13850 #define USB_EPRX_DTOG2 ((uint16_t)0x2000U) /*!< EndPoint RX Data TOGgle bit1 */
Kojto 122:f9eeca106725 13851 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
Kojto 122:f9eeca106725 13852
Kojto 122:f9eeca106725 13853 /******************************************************************************/
Kojto 122:f9eeca106725 13854 /* */
Kojto 122:f9eeca106725 13855 /* USB Device FS General registers */
Kojto 122:f9eeca106725 13856 /* */
Kojto 122:f9eeca106725 13857 /******************************************************************************/
Kojto 122:f9eeca106725 13858 #define USB_CNTR (USB_BASE + 0x00000040U) /*!< Control register */
Kojto 122:f9eeca106725 13859 #define USB_ISTR (USB_BASE + 0x00000044U) /*!< Interrupt status register */
Kojto 122:f9eeca106725 13860 #define USB_FNR (USB_BASE + 0x00000048U) /*!< Frame number register */
Kojto 122:f9eeca106725 13861 #define USB_DADDR (USB_BASE + 0x0000004CU) /*!< Device address register */
Kojto 122:f9eeca106725 13862 #define USB_BTABLE (USB_BASE + 0x00000050U) /*!< Buffer Table address register */
Kojto 122:f9eeca106725 13863 #define USB_LPMCSR (USB_BASE + 0x00000054U) /*!< LPM Control and Status register */
Kojto 122:f9eeca106725 13864 #define USB_BCDR (USB_BASE + 0x00000058U) /*!< Battery Charging detector register*/
Kojto 122:f9eeca106725 13865
Kojto 122:f9eeca106725 13866 /****************** Bits definition for USB_CNTR register *******************/
Kojto 122:f9eeca106725 13867 #define USB_CNTR_CTRM ((uint16_t)0x8000U) /*!< Correct TRansfer Mask */
Kojto 122:f9eeca106725 13868 #define USB_CNTR_PMAOVRM ((uint16_t)0x4000U) /*!< DMA OVeR/underrun Mask */
Kojto 122:f9eeca106725 13869 #define USB_CNTR_ERRM ((uint16_t)0x2000U) /*!< ERRor Mask */
Kojto 122:f9eeca106725 13870 #define USB_CNTR_WKUPM ((uint16_t)0x1000U) /*!< WaKe UP Mask */
Kojto 122:f9eeca106725 13871 #define USB_CNTR_SUSPM ((uint16_t)0x0800U) /*!< SUSPend Mask */
Kojto 122:f9eeca106725 13872 #define USB_CNTR_RESETM ((uint16_t)0x0400U) /*!< RESET Mask */
Kojto 122:f9eeca106725 13873 #define USB_CNTR_SOFM ((uint16_t)0x0200U) /*!< Start Of Frame Mask */
Kojto 122:f9eeca106725 13874 #define USB_CNTR_ESOFM ((uint16_t)0x0100U) /*!< Expected Start Of Frame Mask */
Kojto 122:f9eeca106725 13875 #define USB_CNTR_L1REQM ((uint16_t)0x0080U) /*!< LPM L1 state request interrupt mask */
Kojto 122:f9eeca106725 13876 #define USB_CNTR_L1RESUME ((uint16_t)0x0020U) /*!< LPM L1 Resume request */
Kojto 122:f9eeca106725 13877 #define USB_CNTR_RESUME ((uint16_t)0x0010U) /*!< RESUME request */
Kojto 122:f9eeca106725 13878 #define USB_CNTR_FSUSP ((uint16_t)0x0008U) /*!< Force SUSPend */
Kojto 122:f9eeca106725 13879 #define USB_CNTR_LPMODE ((uint16_t)0x0004U) /*!< Low-power MODE */
Kojto 122:f9eeca106725 13880 #define USB_CNTR_PDWN ((uint16_t)0x0002U) /*!< Power DoWN */
Kojto 122:f9eeca106725 13881 #define USB_CNTR_FRES ((uint16_t)0x0001U) /*!< Force USB RESet */
Kojto 122:f9eeca106725 13882
Kojto 122:f9eeca106725 13883 /****************** Bits definition for USB_ISTR register *******************/
Kojto 122:f9eeca106725 13884 #define USB_ISTR_EP_ID ((uint16_t)0x000FU) /*!< EndPoint IDentifier (read-only bit) */
Kojto 122:f9eeca106725 13885 #define USB_ISTR_DIR ((uint16_t)0x0010U) /*!< DIRection of transaction (read-only bit) */
Kojto 122:f9eeca106725 13886 #define USB_ISTR_L1REQ ((uint16_t)0x0080U) /*!< LPM L1 state request */
Kojto 122:f9eeca106725 13887 #define USB_ISTR_ESOF ((uint16_t)0x0100U) /*!< Expected Start Of Frame (clear-only bit) */
Kojto 122:f9eeca106725 13888 #define USB_ISTR_SOF ((uint16_t)0x0200U) /*!< Start Of Frame (clear-only bit) */
Kojto 122:f9eeca106725 13889 #define USB_ISTR_RESET ((uint16_t)0x0400U) /*!< RESET (clear-only bit) */
Kojto 122:f9eeca106725 13890 #define USB_ISTR_SUSP ((uint16_t)0x0800U) /*!< SUSPend (clear-only bit) */
Kojto 122:f9eeca106725 13891 #define USB_ISTR_WKUP ((uint16_t)0x1000U) /*!< WaKe UP (clear-only bit) */
Kojto 122:f9eeca106725 13892 #define USB_ISTR_ERR ((uint16_t)0x2000U) /*!< ERRor (clear-only bit) */
Kojto 122:f9eeca106725 13893 #define USB_ISTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun (clear-only bit) */
Kojto 122:f9eeca106725 13894 #define USB_ISTR_CTR ((uint16_t)0x8000U) /*!< Correct TRansfer (clear-only bit) */
Kojto 122:f9eeca106725 13895
Kojto 122:f9eeca106725 13896 #define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
Kojto 122:f9eeca106725 13897 #define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
Kojto 122:f9eeca106725 13898 #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
Kojto 122:f9eeca106725 13899 #define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
Kojto 122:f9eeca106725 13900 #define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
Kojto 122:f9eeca106725 13901 #define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
Kojto 122:f9eeca106725 13902 #define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
Kojto 122:f9eeca106725 13903 #define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
Kojto 122:f9eeca106725 13904 #define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
Kojto 122:f9eeca106725 13905
Kojto 122:f9eeca106725 13906 /****************** Bits definition for USB_FNR register ********************/
Kojto 122:f9eeca106725 13907 #define USB_FNR_FN ((uint16_t)0x07FFU) /*!< Frame Number */
Kojto 122:f9eeca106725 13908 #define USB_FNR_LSOF ((uint16_t)0x1800U) /*!< Lost SOF */
Kojto 122:f9eeca106725 13909 #define USB_FNR_LCK ((uint16_t)0x2000U) /*!< LoCKed */
Kojto 122:f9eeca106725 13910 #define USB_FNR_RXDM ((uint16_t)0x4000U) /*!< status of D- data line */
Kojto 122:f9eeca106725 13911 #define USB_FNR_RXDP ((uint16_t)0x8000U) /*!< status of D+ data line */
Kojto 122:f9eeca106725 13912
Kojto 122:f9eeca106725 13913 /****************** Bits definition for USB_DADDR register ****************/
Kojto 122:f9eeca106725 13914 #define USB_DADDR_ADD ((uint8_t)0x7FU) /*!< ADD[6:0] bits (Device Address) */
Kojto 122:f9eeca106725 13915 #define USB_DADDR_ADD0 ((uint8_t)0x01U) /*!< Bit 0 */
Kojto 122:f9eeca106725 13916 #define USB_DADDR_ADD1 ((uint8_t)0x02U) /*!< Bit 1 */
Kojto 122:f9eeca106725 13917 #define USB_DADDR_ADD2 ((uint8_t)0x04U) /*!< Bit 2 */
Kojto 122:f9eeca106725 13918 #define USB_DADDR_ADD3 ((uint8_t)0x08U) /*!< Bit 3 */
Kojto 122:f9eeca106725 13919 #define USB_DADDR_ADD4 ((uint8_t)0x10U) /*!< Bit 4 */
Kojto 122:f9eeca106725 13920 #define USB_DADDR_ADD5 ((uint8_t)0x20U) /*!< Bit 5 */
Kojto 122:f9eeca106725 13921 #define USB_DADDR_ADD6 ((uint8_t)0x40U) /*!< Bit 6 */
Kojto 122:f9eeca106725 13922
Kojto 122:f9eeca106725 13923 #define USB_DADDR_EF ((uint8_t)0x80U) /*!< Enable Function */
Kojto 122:f9eeca106725 13924
Kojto 122:f9eeca106725 13925 /****************** Bit definition for USB_BTABLE register ******************/
Kojto 122:f9eeca106725 13926 #define USB_BTABLE_BTABLE ((uint16_t)0xFFF8U) /*!< Buffer Table */
Kojto 122:f9eeca106725 13927
Kojto 122:f9eeca106725 13928 /****************** Bits definition for USB_BCDR register *******************/
Kojto 122:f9eeca106725 13929 #define USB_BCDR_BCDEN ((uint16_t)0x0001U) /*!< Battery charging detector (BCD) enable */
Kojto 122:f9eeca106725 13930 #define USB_BCDR_DCDEN ((uint16_t)0x0002U) /*!< Data contact detection (DCD) mode enable */
Kojto 122:f9eeca106725 13931 #define USB_BCDR_PDEN ((uint16_t)0x0004U) /*!< Primary detection (PD) mode enable */
Kojto 122:f9eeca106725 13932 #define USB_BCDR_SDEN ((uint16_t)0x0008U) /*!< Secondary detection (SD) mode enable */
Kojto 122:f9eeca106725 13933 #define USB_BCDR_DCDET ((uint16_t)0x0010U) /*!< Data contact detection (DCD) status */
Kojto 122:f9eeca106725 13934 #define USB_BCDR_PDET ((uint16_t)0x0020U) /*!< Primary detection (PD) status */
Kojto 122:f9eeca106725 13935 #define USB_BCDR_SDET ((uint16_t)0x0040U) /*!< Secondary detection (SD) status */
Kojto 122:f9eeca106725 13936 #define USB_BCDR_PS2DET ((uint16_t)0x0080U) /*!< PS2 port or proprietary charger detected */
Kojto 122:f9eeca106725 13937 #define USB_BCDR_DPPU ((uint16_t)0x8000U) /*!< DP Pull-up Enable */
Kojto 122:f9eeca106725 13938
Kojto 122:f9eeca106725 13939 /******************* Bit definition for LPMCSR register *********************/
Kojto 122:f9eeca106725 13940 #define USB_LPMCSR_LMPEN ((uint16_t)0x0001U) /*!< LPM support enable */
Kojto 122:f9eeca106725 13941 #define USB_LPMCSR_LPMACK ((uint16_t)0x0002U) /*!< LPM Token acknowledge enable*/
Kojto 122:f9eeca106725 13942 #define USB_LPMCSR_REMWAKE ((uint16_t)0x0008U) /*!< bRemoteWake value received with last ACKed LPM Token */
Kojto 122:f9eeca106725 13943 #define USB_LPMCSR_BESL ((uint16_t)0x00F0U) /*!< BESL value received with last ACKed LPM Token */
Kojto 122:f9eeca106725 13944
Kojto 122:f9eeca106725 13945 /*!< Buffer descriptor table */
Kojto 122:f9eeca106725 13946 /***************** Bit definition for USB_ADDR0_TX register *****************/
Kojto 122:f9eeca106725 13947 #define USB_ADDR0_TX_ADDR0_TX_Pos (1U)
Kojto 122:f9eeca106725 13948 #define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFU << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
Kojto 122:f9eeca106725 13949 #define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /*!< Transmission Buffer Address 0 */
Kojto 122:f9eeca106725 13950
Kojto 122:f9eeca106725 13951 /***************** Bit definition for USB_ADDR1_TX register *****************/
Kojto 122:f9eeca106725 13952 #define USB_ADDR1_TX_ADDR1_TX_Pos (1U)
Kojto 122:f9eeca106725 13953 #define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFU << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
Kojto 122:f9eeca106725 13954 #define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /*!< Transmission Buffer Address 1 */
Kojto 122:f9eeca106725 13955
Kojto 122:f9eeca106725 13956 /***************** Bit definition for USB_ADDR2_TX register *****************/
Kojto 122:f9eeca106725 13957 #define USB_ADDR2_TX_ADDR2_TX_Pos (1U)
Kojto 122:f9eeca106725 13958 #define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFU << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
Kojto 122:f9eeca106725 13959 #define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /*!< Transmission Buffer Address 2 */
Kojto 122:f9eeca106725 13960
Kojto 122:f9eeca106725 13961 /***************** Bit definition for USB_ADDR3_TX register *****************/
Kojto 122:f9eeca106725 13962 #define USB_ADDR3_TX_ADDR3_TX_Pos (1U)
Kojto 122:f9eeca106725 13963 #define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFU << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
Kojto 122:f9eeca106725 13964 #define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /*!< Transmission Buffer Address 3 */
Kojto 122:f9eeca106725 13965
Kojto 122:f9eeca106725 13966 /***************** Bit definition for USB_ADDR4_TX register *****************/
Kojto 122:f9eeca106725 13967 #define USB_ADDR4_TX_ADDR4_TX_Pos (1U)
Kojto 122:f9eeca106725 13968 #define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFU << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
Kojto 122:f9eeca106725 13969 #define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /*!< Transmission Buffer Address 4 */
Kojto 122:f9eeca106725 13970
Kojto 122:f9eeca106725 13971 /***************** Bit definition for USB_ADDR5_TX register *****************/
Kojto 122:f9eeca106725 13972 #define USB_ADDR5_TX_ADDR5_TX_Pos (1U)
Kojto 122:f9eeca106725 13973 #define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFU << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
Kojto 122:f9eeca106725 13974 #define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /*!< Transmission Buffer Address 5 */
Kojto 122:f9eeca106725 13975
Kojto 122:f9eeca106725 13976 /***************** Bit definition for USB_ADDR6_TX register *****************/
Kojto 122:f9eeca106725 13977 #define USB_ADDR6_TX_ADDR6_TX_Pos (1U)
Kojto 122:f9eeca106725 13978 #define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFU << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
Kojto 122:f9eeca106725 13979 #define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /*!< Transmission Buffer Address 6 */
Kojto 122:f9eeca106725 13980
Kojto 122:f9eeca106725 13981 /***************** Bit definition for USB_ADDR7_TX register *****************/
Kojto 122:f9eeca106725 13982 #define USB_ADDR7_TX_ADDR7_TX_Pos (1U)
Kojto 122:f9eeca106725 13983 #define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFU << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
Kojto 122:f9eeca106725 13984 #define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /*!< Transmission Buffer Address 7 */
Kojto 122:f9eeca106725 13985
Kojto 122:f9eeca106725 13986 /*----------------------------------------------------------------------------*/
Kojto 122:f9eeca106725 13987
Kojto 122:f9eeca106725 13988 /***************** Bit definition for USB_COUNT0_TX register ****************/
Kojto 122:f9eeca106725 13989 #define USB_COUNT0_TX_COUNT0_TX_Pos (0U)
Kojto 122:f9eeca106725 13990 #define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFU << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
Kojto 122:f9eeca106725 13991 #define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /*!< Transmission Byte Count 0 */
Kojto 122:f9eeca106725 13992
Kojto 122:f9eeca106725 13993 /***************** Bit definition for USB_COUNT1_TX register ****************/
Kojto 122:f9eeca106725 13994 #define USB_COUNT1_TX_COUNT1_TX_Pos (0U)
Kojto 122:f9eeca106725 13995 #define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFU << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
Kojto 122:f9eeca106725 13996 #define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /*!< Transmission Byte Count 1 */
Kojto 122:f9eeca106725 13997
Kojto 122:f9eeca106725 13998 /***************** Bit definition for USB_COUNT2_TX register ****************/
Kojto 122:f9eeca106725 13999 #define USB_COUNT2_TX_COUNT2_TX_Pos (0U)
Kojto 122:f9eeca106725 14000 #define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFU << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
Kojto 122:f9eeca106725 14001 #define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /*!< Transmission Byte Count 2 */
Kojto 122:f9eeca106725 14002
Kojto 122:f9eeca106725 14003 /***************** Bit definition for USB_COUNT3_TX register ****************/
Kojto 122:f9eeca106725 14004 #define USB_COUNT3_TX_COUNT3_TX_Pos (0U)
Kojto 122:f9eeca106725 14005 #define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFU << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
Kojto 122:f9eeca106725 14006 #define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /*!< Transmission Byte Count 3 */
Kojto 122:f9eeca106725 14007
Kojto 122:f9eeca106725 14008 /***************** Bit definition for USB_COUNT4_TX register ****************/
Kojto 122:f9eeca106725 14009 #define USB_COUNT4_TX_COUNT4_TX_Pos (0U)
Kojto 122:f9eeca106725 14010 #define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFU << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
Kojto 122:f9eeca106725 14011 #define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /*!< Transmission Byte Count 4 */
Kojto 122:f9eeca106725 14012
Kojto 122:f9eeca106725 14013 /***************** Bit definition for USB_COUNT5_TX register ****************/
Kojto 122:f9eeca106725 14014 #define USB_COUNT5_TX_COUNT5_TX_Pos (0U)
Kojto 122:f9eeca106725 14015 #define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFU << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
Kojto 122:f9eeca106725 14016 #define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /*!< Transmission Byte Count 5 */
Kojto 122:f9eeca106725 14017
Kojto 122:f9eeca106725 14018 /***************** Bit definition for USB_COUNT6_TX register ****************/
Kojto 122:f9eeca106725 14019 #define USB_COUNT6_TX_COUNT6_TX_Pos (0U)
Kojto 122:f9eeca106725 14020 #define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFU << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
Kojto 122:f9eeca106725 14021 #define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /*!< Transmission Byte Count 6 */
Kojto 122:f9eeca106725 14022
Kojto 122:f9eeca106725 14023 /***************** Bit definition for USB_COUNT7_TX register ****************/
Kojto 122:f9eeca106725 14024 #define USB_COUNT7_TX_COUNT7_TX_Pos (0U)
Kojto 122:f9eeca106725 14025 #define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFU << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
Kojto 122:f9eeca106725 14026 #define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /*!< Transmission Byte Count 7 */
Kojto 122:f9eeca106725 14027
Kojto 122:f9eeca106725 14028 /*----------------------------------------------------------------------------*/
Kojto 122:f9eeca106725 14029
Kojto 122:f9eeca106725 14030 /**************** Bit definition for USB_COUNT0_TX_0 register ***************/
Kojto 122:f9eeca106725 14031 #define USB_COUNT0_TX_0_COUNT0_TX_0 (0x000003FFU) /*!< Transmission Byte Count 0 (low) */
Kojto 122:f9eeca106725 14032
Kojto 122:f9eeca106725 14033 /**************** Bit definition for USB_COUNT0_TX_1 register ***************/
Kojto 122:f9eeca106725 14034 #define USB_COUNT0_TX_1_COUNT0_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 0 (high) */
Kojto 122:f9eeca106725 14035
Kojto 122:f9eeca106725 14036 /**************** Bit definition for USB_COUNT1_TX_0 register ***************/
Kojto 122:f9eeca106725 14037 #define USB_COUNT1_TX_0_COUNT1_TX_0 (0x000003FFU) /*!< Transmission Byte Count 1 (low) */
Kojto 122:f9eeca106725 14038
Kojto 122:f9eeca106725 14039 /**************** Bit definition for USB_COUNT1_TX_1 register ***************/
Kojto 122:f9eeca106725 14040 #define USB_COUNT1_TX_1_COUNT1_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 1 (high) */
Kojto 122:f9eeca106725 14041
Kojto 122:f9eeca106725 14042 /**************** Bit definition for USB_COUNT2_TX_0 register ***************/
Kojto 122:f9eeca106725 14043 #define USB_COUNT2_TX_0_COUNT2_TX_0 (0x000003FFU) /*!< Transmission Byte Count 2 (low) */
Kojto 122:f9eeca106725 14044
Kojto 122:f9eeca106725 14045 /**************** Bit definition for USB_COUNT2_TX_1 register ***************/
Kojto 122:f9eeca106725 14046 #define USB_COUNT2_TX_1_COUNT2_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 2 (high) */
Kojto 122:f9eeca106725 14047
Kojto 122:f9eeca106725 14048 /**************** Bit definition for USB_COUNT3_TX_0 register ***************/
Kojto 122:f9eeca106725 14049 #define USB_COUNT3_TX_0_COUNT3_TX_0 (0x000003FFU) /*!< Transmission Byte Count 3 (low) */
Kojto 122:f9eeca106725 14050
Kojto 122:f9eeca106725 14051 /**************** Bit definition for USB_COUNT3_TX_1 register ***************/
Kojto 122:f9eeca106725 14052 #define USB_COUNT3_TX_1_COUNT3_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 3 (high) */
Kojto 122:f9eeca106725 14053
Kojto 122:f9eeca106725 14054 /**************** Bit definition for USB_COUNT4_TX_0 register ***************/
Kojto 122:f9eeca106725 14055 #define USB_COUNT4_TX_0_COUNT4_TX_0 (0x000003FFU) /*!< Transmission Byte Count 4 (low) */
Kojto 122:f9eeca106725 14056
Kojto 122:f9eeca106725 14057 /**************** Bit definition for USB_COUNT4_TX_1 register ***************/
Kojto 122:f9eeca106725 14058 #define USB_COUNT4_TX_1_COUNT4_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 4 (high) */
Kojto 122:f9eeca106725 14059
Kojto 122:f9eeca106725 14060 /**************** Bit definition for USB_COUNT5_TX_0 register ***************/
Kojto 122:f9eeca106725 14061 #define USB_COUNT5_TX_0_COUNT5_TX_0 (0x000003FFU) /*!< Transmission Byte Count 5 (low) */
Kojto 122:f9eeca106725 14062
Kojto 122:f9eeca106725 14063 /**************** Bit definition for USB_COUNT5_TX_1 register ***************/
Kojto 122:f9eeca106725 14064 #define USB_COUNT5_TX_1_COUNT5_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 5 (high) */
Kojto 122:f9eeca106725 14065
Kojto 122:f9eeca106725 14066 /**************** Bit definition for USB_COUNT6_TX_0 register ***************/
Kojto 122:f9eeca106725 14067 #define USB_COUNT6_TX_0_COUNT6_TX_0 (0x000003FFU) /*!< Transmission Byte Count 6 (low) */
Kojto 122:f9eeca106725 14068
Kojto 122:f9eeca106725 14069 /**************** Bit definition for USB_COUNT6_TX_1 register ***************/
Kojto 122:f9eeca106725 14070 #define USB_COUNT6_TX_1_COUNT6_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 6 (high) */
Kojto 122:f9eeca106725 14071
Kojto 122:f9eeca106725 14072 /**************** Bit definition for USB_COUNT7_TX_0 register ***************/
Kojto 122:f9eeca106725 14073 #define USB_COUNT7_TX_0_COUNT7_TX_0 (0x000003FFU) /*!< Transmission Byte Count 7 (low) */
Kojto 122:f9eeca106725 14074
Kojto 122:f9eeca106725 14075 /**************** Bit definition for USB_COUNT7_TX_1 register ***************/
Kojto 122:f9eeca106725 14076 #define USB_COUNT7_TX_1_COUNT7_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 7 (high) */
Kojto 122:f9eeca106725 14077
Kojto 122:f9eeca106725 14078 /*----------------------------------------------------------------------------*/
Kojto 122:f9eeca106725 14079
Kojto 122:f9eeca106725 14080 /***************** Bit definition for USB_ADDR0_RX register *****************/
Kojto 122:f9eeca106725 14081 #define USB_ADDR0_RX_ADDR0_RX_Pos (1U)
Kojto 122:f9eeca106725 14082 #define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFU << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
Kojto 122:f9eeca106725 14083 #define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /*!< Reception Buffer Address 0 */
Kojto 122:f9eeca106725 14084
Kojto 122:f9eeca106725 14085 /***************** Bit definition for USB_ADDR1_RX register *****************/
Kojto 122:f9eeca106725 14086 #define USB_ADDR1_RX_ADDR1_RX_Pos (1U)
Kojto 122:f9eeca106725 14087 #define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFU << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
Kojto 122:f9eeca106725 14088 #define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /*!< Reception Buffer Address 1 */
Kojto 122:f9eeca106725 14089
Kojto 122:f9eeca106725 14090 /***************** Bit definition for USB_ADDR2_RX register *****************/
Kojto 122:f9eeca106725 14091 #define USB_ADDR2_RX_ADDR2_RX_Pos (1U)
Kojto 122:f9eeca106725 14092 #define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFU << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
Kojto 122:f9eeca106725 14093 #define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /*!< Reception Buffer Address 2 */
Kojto 122:f9eeca106725 14094
Kojto 122:f9eeca106725 14095 /***************** Bit definition for USB_ADDR3_RX register *****************/
Kojto 122:f9eeca106725 14096 #define USB_ADDR3_RX_ADDR3_RX_Pos (1U)
Kojto 122:f9eeca106725 14097 #define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFU << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
Kojto 122:f9eeca106725 14098 #define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /*!< Reception Buffer Address 3 */
Kojto 122:f9eeca106725 14099
Kojto 122:f9eeca106725 14100 /***************** Bit definition for USB_ADDR4_RX register *****************/
Kojto 122:f9eeca106725 14101 #define USB_ADDR4_RX_ADDR4_RX_Pos (1U)
Kojto 122:f9eeca106725 14102 #define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFU << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
Kojto 122:f9eeca106725 14103 #define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /*!< Reception Buffer Address 4 */
Kojto 122:f9eeca106725 14104
Kojto 122:f9eeca106725 14105 /***************** Bit definition for USB_ADDR5_RX register *****************/
Kojto 122:f9eeca106725 14106 #define USB_ADDR5_RX_ADDR5_RX_Pos (1U)
Kojto 122:f9eeca106725 14107 #define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFU << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
Kojto 122:f9eeca106725 14108 #define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /*!< Reception Buffer Address 5 */
Kojto 122:f9eeca106725 14109
Kojto 122:f9eeca106725 14110 /***************** Bit definition for USB_ADDR6_RX register *****************/
Kojto 122:f9eeca106725 14111 #define USB_ADDR6_RX_ADDR6_RX_Pos (1U)
Kojto 122:f9eeca106725 14112 #define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFU << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
Kojto 122:f9eeca106725 14113 #define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /*!< Reception Buffer Address 6 */
Kojto 122:f9eeca106725 14114
Kojto 122:f9eeca106725 14115 /***************** Bit definition for USB_ADDR7_RX register *****************/
Kojto 122:f9eeca106725 14116 #define USB_ADDR7_RX_ADDR7_RX_Pos (1U)
Kojto 122:f9eeca106725 14117 #define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFU << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
Kojto 122:f9eeca106725 14118 #define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /*!< Reception Buffer Address 7 */
Kojto 122:f9eeca106725 14119
Kojto 122:f9eeca106725 14120 /*----------------------------------------------------------------------------*/
Kojto 122:f9eeca106725 14121
Kojto 122:f9eeca106725 14122 /***************** Bit definition for USB_COUNT0_RX register ****************/
Kojto 122:f9eeca106725 14123 #define USB_COUNT0_RX_COUNT0_RX_Pos (0U)
Kojto 122:f9eeca106725 14124 #define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFU << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
Kojto 122:f9eeca106725 14125 #define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /*!< Reception Byte Count */
Kojto 122:f9eeca106725 14126
Kojto 122:f9eeca106725 14127 #define USB_COUNT0_RX_NUM_BLOCK_Pos (10U)
Kojto 122:f9eeca106725 14128 #define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
Kojto 122:f9eeca106725 14129 #define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
Kojto 122:f9eeca106725 14130 #define USB_COUNT0_RX_NUM_BLOCK_0 (0x01U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 14131 #define USB_COUNT0_RX_NUM_BLOCK_1 (0x02U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 14132 #define USB_COUNT0_RX_NUM_BLOCK_2 (0x04U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 14133 #define USB_COUNT0_RX_NUM_BLOCK_3 (0x08U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 14134 #define USB_COUNT0_RX_NUM_BLOCK_4 (0x10U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 14135
Kojto 122:f9eeca106725 14136 #define USB_COUNT0_RX_BLSIZE_Pos (15U)
Kojto 122:f9eeca106725 14137 #define USB_COUNT0_RX_BLSIZE_Msk (0x1U << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 14138 #define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /*!< BLock SIZE */
Kojto 122:f9eeca106725 14139
Kojto 122:f9eeca106725 14140 /***************** Bit definition for USB_COUNT1_RX register ****************/
Kojto 122:f9eeca106725 14141 #define USB_COUNT1_RX_COUNT1_RX_Pos (0U)
Kojto 122:f9eeca106725 14142 #define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFU << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
Kojto 122:f9eeca106725 14143 #define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /*!< Reception Byte Count */
Kojto 122:f9eeca106725 14144
Kojto 122:f9eeca106725 14145 #define USB_COUNT1_RX_NUM_BLOCK_Pos (10U)
Kojto 122:f9eeca106725 14146 #define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
Kojto 122:f9eeca106725 14147 #define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
Kojto 122:f9eeca106725 14148 #define USB_COUNT1_RX_NUM_BLOCK_0 (0x01U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 14149 #define USB_COUNT1_RX_NUM_BLOCK_1 (0x02U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 14150 #define USB_COUNT1_RX_NUM_BLOCK_2 (0x04U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 14151 #define USB_COUNT1_RX_NUM_BLOCK_3 (0x08U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 14152 #define USB_COUNT1_RX_NUM_BLOCK_4 (0x10U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 14153
Kojto 122:f9eeca106725 14154 #define USB_COUNT1_RX_BLSIZE_Pos (15U)
Kojto 122:f9eeca106725 14155 #define USB_COUNT1_RX_BLSIZE_Msk (0x1U << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 14156 #define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /*!< BLock SIZE */
Kojto 122:f9eeca106725 14157
Kojto 122:f9eeca106725 14158 /***************** Bit definition for USB_COUNT2_RX register ****************/
Kojto 122:f9eeca106725 14159 #define USB_COUNT2_RX_COUNT2_RX_Pos (0U)
Kojto 122:f9eeca106725 14160 #define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFU << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
Kojto 122:f9eeca106725 14161 #define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /*!< Reception Byte Count */
Kojto 122:f9eeca106725 14162
Kojto 122:f9eeca106725 14163 #define USB_COUNT2_RX_NUM_BLOCK_Pos (10U)
Kojto 122:f9eeca106725 14164 #define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
Kojto 122:f9eeca106725 14165 #define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
Kojto 122:f9eeca106725 14166 #define USB_COUNT2_RX_NUM_BLOCK_0 (0x01U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 14167 #define USB_COUNT2_RX_NUM_BLOCK_1 (0x02U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 14168 #define USB_COUNT2_RX_NUM_BLOCK_2 (0x04U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 14169 #define USB_COUNT2_RX_NUM_BLOCK_3 (0x08U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 14170 #define USB_COUNT2_RX_NUM_BLOCK_4 (0x10U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 14171
Kojto 122:f9eeca106725 14172 #define USB_COUNT2_RX_BLSIZE_Pos (15U)
Kojto 122:f9eeca106725 14173 #define USB_COUNT2_RX_BLSIZE_Msk (0x1U << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 14174 #define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /*!< BLock SIZE */
Kojto 122:f9eeca106725 14175
Kojto 122:f9eeca106725 14176 /***************** Bit definition for USB_COUNT3_RX register ****************/
Kojto 122:f9eeca106725 14177 #define USB_COUNT3_RX_COUNT3_RX_Pos (0U)
Kojto 122:f9eeca106725 14178 #define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFU << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
Kojto 122:f9eeca106725 14179 #define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /*!< Reception Byte Count */
Kojto 122:f9eeca106725 14180
Kojto 122:f9eeca106725 14181 #define USB_COUNT3_RX_NUM_BLOCK_Pos (10U)
Kojto 122:f9eeca106725 14182 #define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
Kojto 122:f9eeca106725 14183 #define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
Kojto 122:f9eeca106725 14184 #define USB_COUNT3_RX_NUM_BLOCK_0 (0x01U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 14185 #define USB_COUNT3_RX_NUM_BLOCK_1 (0x02U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 14186 #define USB_COUNT3_RX_NUM_BLOCK_2 (0x04U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 14187 #define USB_COUNT3_RX_NUM_BLOCK_3 (0x08U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 14188 #define USB_COUNT3_RX_NUM_BLOCK_4 (0x10U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 14189
Kojto 122:f9eeca106725 14190 #define USB_COUNT3_RX_BLSIZE_Pos (15U)
Kojto 122:f9eeca106725 14191 #define USB_COUNT3_RX_BLSIZE_Msk (0x1U << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 14192 #define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /*!< BLock SIZE */
Kojto 122:f9eeca106725 14193
Kojto 122:f9eeca106725 14194 /***************** Bit definition for USB_COUNT4_RX register ****************/
Kojto 122:f9eeca106725 14195 #define USB_COUNT4_RX_COUNT4_RX_Pos (0U)
Kojto 122:f9eeca106725 14196 #define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFU << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
Kojto 122:f9eeca106725 14197 #define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /*!< Reception Byte Count */
Kojto 122:f9eeca106725 14198
Kojto 122:f9eeca106725 14199 #define USB_COUNT4_RX_NUM_BLOCK_Pos (10U)
Kojto 122:f9eeca106725 14200 #define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
Kojto 122:f9eeca106725 14201 #define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
Kojto 122:f9eeca106725 14202 #define USB_COUNT4_RX_NUM_BLOCK_0 (0x01U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 14203 #define USB_COUNT4_RX_NUM_BLOCK_1 (0x02U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 14204 #define USB_COUNT4_RX_NUM_BLOCK_2 (0x04U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 14205 #define USB_COUNT4_RX_NUM_BLOCK_3 (0x08U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 14206 #define USB_COUNT4_RX_NUM_BLOCK_4 (0x10U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 14207
Kojto 122:f9eeca106725 14208 #define USB_COUNT4_RX_BLSIZE_Pos (15U)
Kojto 122:f9eeca106725 14209 #define USB_COUNT4_RX_BLSIZE_Msk (0x1U << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 14210 #define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /*!< BLock SIZE */
Kojto 122:f9eeca106725 14211
Kojto 122:f9eeca106725 14212 /***************** Bit definition for USB_COUNT5_RX register ****************/
Kojto 122:f9eeca106725 14213 #define USB_COUNT5_RX_COUNT5_RX_Pos (0U)
Kojto 122:f9eeca106725 14214 #define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFU << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
Kojto 122:f9eeca106725 14215 #define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /*!< Reception Byte Count */
Kojto 122:f9eeca106725 14216
Kojto 122:f9eeca106725 14217 #define USB_COUNT5_RX_NUM_BLOCK_Pos (10U)
Kojto 122:f9eeca106725 14218 #define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
Kojto 122:f9eeca106725 14219 #define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
Kojto 122:f9eeca106725 14220 #define USB_COUNT5_RX_NUM_BLOCK_0 (0x01U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 14221 #define USB_COUNT5_RX_NUM_BLOCK_1 (0x02U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 14222 #define USB_COUNT5_RX_NUM_BLOCK_2 (0x04U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 14223 #define USB_COUNT5_RX_NUM_BLOCK_3 (0x08U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 14224 #define USB_COUNT5_RX_NUM_BLOCK_4 (0x10U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 14225
Kojto 122:f9eeca106725 14226 #define USB_COUNT5_RX_BLSIZE_Pos (15U)
Kojto 122:f9eeca106725 14227 #define USB_COUNT5_RX_BLSIZE_Msk (0x1U << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 14228 #define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /*!< BLock SIZE */
Kojto 122:f9eeca106725 14229
Kojto 122:f9eeca106725 14230 /***************** Bit definition for USB_COUNT6_RX register ****************/
Kojto 122:f9eeca106725 14231 #define USB_COUNT6_RX_COUNT6_RX_Pos (0U)
Kojto 122:f9eeca106725 14232 #define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFU << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
Kojto 122:f9eeca106725 14233 #define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /*!< Reception Byte Count */
Kojto 122:f9eeca106725 14234
Kojto 122:f9eeca106725 14235 #define USB_COUNT6_RX_NUM_BLOCK_Pos (10U)
Kojto 122:f9eeca106725 14236 #define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
Kojto 122:f9eeca106725 14237 #define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
Kojto 122:f9eeca106725 14238 #define USB_COUNT6_RX_NUM_BLOCK_0 (0x01U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 14239 #define USB_COUNT6_RX_NUM_BLOCK_1 (0x02U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 14240 #define USB_COUNT6_RX_NUM_BLOCK_2 (0x04U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 14241 #define USB_COUNT6_RX_NUM_BLOCK_3 (0x08U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 14242 #define USB_COUNT6_RX_NUM_BLOCK_4 (0x10U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 14243
Kojto 122:f9eeca106725 14244 #define USB_COUNT6_RX_BLSIZE_Pos (15U)
Kojto 122:f9eeca106725 14245 #define USB_COUNT6_RX_BLSIZE_Msk (0x1U << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 14246 #define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /*!< BLock SIZE */
Kojto 122:f9eeca106725 14247
Kojto 122:f9eeca106725 14248 /***************** Bit definition for USB_COUNT7_RX register ****************/
Kojto 122:f9eeca106725 14249 #define USB_COUNT7_RX_COUNT7_RX_Pos (0U)
Kojto 122:f9eeca106725 14250 #define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFU << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
Kojto 122:f9eeca106725 14251 #define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /*!< Reception Byte Count */
Kojto 122:f9eeca106725 14252
Kojto 122:f9eeca106725 14253 #define USB_COUNT7_RX_NUM_BLOCK_Pos (10U)
Kojto 122:f9eeca106725 14254 #define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
Kojto 122:f9eeca106725 14255 #define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
Kojto 122:f9eeca106725 14256 #define USB_COUNT7_RX_NUM_BLOCK_0 (0x01U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 14257 #define USB_COUNT7_RX_NUM_BLOCK_1 (0x02U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 14258 #define USB_COUNT7_RX_NUM_BLOCK_2 (0x04U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 14259 #define USB_COUNT7_RX_NUM_BLOCK_3 (0x08U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 14260 #define USB_COUNT7_RX_NUM_BLOCK_4 (0x10U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 14261
Kojto 122:f9eeca106725 14262 #define USB_COUNT7_RX_BLSIZE_Pos (15U)
Kojto 122:f9eeca106725 14263 #define USB_COUNT7_RX_BLSIZE_Msk (0x1U << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 14264 #define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /*!< BLock SIZE */
Kojto 122:f9eeca106725 14265
Kojto 122:f9eeca106725 14266 /*----------------------------------------------------------------------------*/
Kojto 122:f9eeca106725 14267
Kojto 122:f9eeca106725 14268 /**************** Bit definition for USB_COUNT0_RX_0 register ***************/
Kojto 122:f9eeca106725 14269 #define USB_COUNT0_RX_0_COUNT0_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
Kojto 122:f9eeca106725 14270
Kojto 122:f9eeca106725 14271 #define USB_COUNT0_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
Kojto 122:f9eeca106725 14272 #define USB_COUNT0_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
Kojto 122:f9eeca106725 14273 #define USB_COUNT0_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
Kojto 122:f9eeca106725 14274 #define USB_COUNT0_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 14275 #define USB_COUNT0_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 14276 #define USB_COUNT0_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 14277
Kojto 122:f9eeca106725 14278 #define USB_COUNT0_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
Kojto 122:f9eeca106725 14279
Kojto 122:f9eeca106725 14280 /**************** Bit definition for USB_COUNT0_RX_1 register ***************/
Kojto 122:f9eeca106725 14281 #define USB_COUNT0_RX_1_COUNT0_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
Kojto 122:f9eeca106725 14282
Kojto 122:f9eeca106725 14283 #define USB_COUNT0_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
Kojto 122:f9eeca106725 14284 #define USB_COUNT0_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 14285 #define USB_COUNT0_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 14286 #define USB_COUNT0_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 14287 #define USB_COUNT0_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 14288 #define USB_COUNT0_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 14289
Kojto 122:f9eeca106725 14290 #define USB_COUNT0_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
Kojto 122:f9eeca106725 14291
Kojto 122:f9eeca106725 14292 /**************** Bit definition for USB_COUNT1_RX_0 register ***************/
Kojto 122:f9eeca106725 14293 #define USB_COUNT1_RX_0_COUNT1_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
Kojto 122:f9eeca106725 14294
Kojto 122:f9eeca106725 14295 #define USB_COUNT1_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
Kojto 122:f9eeca106725 14296 #define USB_COUNT1_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
Kojto 122:f9eeca106725 14297 #define USB_COUNT1_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
Kojto 122:f9eeca106725 14298 #define USB_COUNT1_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 14299 #define USB_COUNT1_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 14300 #define USB_COUNT1_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 14301
Kojto 122:f9eeca106725 14302 #define USB_COUNT1_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
Kojto 122:f9eeca106725 14303
Kojto 122:f9eeca106725 14304 /**************** Bit definition for USB_COUNT1_RX_1 register ***************/
Kojto 122:f9eeca106725 14305 #define USB_COUNT1_RX_1_COUNT1_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
Kojto 122:f9eeca106725 14306
Kojto 122:f9eeca106725 14307 #define USB_COUNT1_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
Kojto 122:f9eeca106725 14308 #define USB_COUNT1_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 14309 #define USB_COUNT1_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 14310 #define USB_COUNT1_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 14311 #define USB_COUNT1_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 14312 #define USB_COUNT1_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 14313
Kojto 122:f9eeca106725 14314 #define USB_COUNT1_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
Kojto 122:f9eeca106725 14315
Kojto 122:f9eeca106725 14316 /**************** Bit definition for USB_COUNT2_RX_0 register ***************/
Kojto 122:f9eeca106725 14317 #define USB_COUNT2_RX_0_COUNT2_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
Kojto 122:f9eeca106725 14318
Kojto 122:f9eeca106725 14319 #define USB_COUNT2_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
Kojto 122:f9eeca106725 14320 #define USB_COUNT2_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
Kojto 122:f9eeca106725 14321 #define USB_COUNT2_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
Kojto 122:f9eeca106725 14322 #define USB_COUNT2_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 14323 #define USB_COUNT2_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 14324 #define USB_COUNT2_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 14325
Kojto 122:f9eeca106725 14326 #define USB_COUNT2_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
Kojto 122:f9eeca106725 14327
Kojto 122:f9eeca106725 14328 /**************** Bit definition for USB_COUNT2_RX_1 register ***************/
Kojto 122:f9eeca106725 14329 #define USB_COUNT2_RX_1_COUNT2_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
Kojto 122:f9eeca106725 14330
Kojto 122:f9eeca106725 14331 #define USB_COUNT2_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
Kojto 122:f9eeca106725 14332 #define USB_COUNT2_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 14333 #define USB_COUNT2_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 14334 #define USB_COUNT2_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 14335 #define USB_COUNT2_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 14336 #define USB_COUNT2_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 14337
Kojto 122:f9eeca106725 14338 #define USB_COUNT2_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
Kojto 122:f9eeca106725 14339
Kojto 122:f9eeca106725 14340 /**************** Bit definition for USB_COUNT3_RX_0 register ***************/
Kojto 122:f9eeca106725 14341 #define USB_COUNT3_RX_0_COUNT3_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
Kojto 122:f9eeca106725 14342
Kojto 122:f9eeca106725 14343 #define USB_COUNT3_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
Kojto 122:f9eeca106725 14344 #define USB_COUNT3_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
Kojto 122:f9eeca106725 14345 #define USB_COUNT3_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
Kojto 122:f9eeca106725 14346 #define USB_COUNT3_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 14347 #define USB_COUNT3_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 14348 #define USB_COUNT3_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 14349
Kojto 122:f9eeca106725 14350 #define USB_COUNT3_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
Kojto 122:f9eeca106725 14351
Kojto 122:f9eeca106725 14352 /**************** Bit definition for USB_COUNT3_RX_1 register ***************/
Kojto 122:f9eeca106725 14353 #define USB_COUNT3_RX_1_COUNT3_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
Kojto 122:f9eeca106725 14354
Kojto 122:f9eeca106725 14355 #define USB_COUNT3_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
Kojto 122:f9eeca106725 14356 #define USB_COUNT3_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 14357 #define USB_COUNT3_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 14358 #define USB_COUNT3_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 14359 #define USB_COUNT3_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 14360 #define USB_COUNT3_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 14361
Kojto 122:f9eeca106725 14362 #define USB_COUNT3_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
Kojto 122:f9eeca106725 14363
Kojto 122:f9eeca106725 14364 /**************** Bit definition for USB_COUNT4_RX_0 register ***************/
Kojto 122:f9eeca106725 14365 #define USB_COUNT4_RX_0_COUNT4_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
Kojto 122:f9eeca106725 14366
Kojto 122:f9eeca106725 14367 #define USB_COUNT4_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
Kojto 122:f9eeca106725 14368 #define USB_COUNT4_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
Kojto 122:f9eeca106725 14369 #define USB_COUNT4_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
Kojto 122:f9eeca106725 14370 #define USB_COUNT4_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 14371 #define USB_COUNT4_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 14372 #define USB_COUNT4_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 14373
Kojto 122:f9eeca106725 14374 #define USB_COUNT4_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
Kojto 122:f9eeca106725 14375
Kojto 122:f9eeca106725 14376 /**************** Bit definition for USB_COUNT4_RX_1 register ***************/
Kojto 122:f9eeca106725 14377 #define USB_COUNT4_RX_1_COUNT4_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
Kojto 122:f9eeca106725 14378
Kojto 122:f9eeca106725 14379 #define USB_COUNT4_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
Kojto 122:f9eeca106725 14380 #define USB_COUNT4_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 14381 #define USB_COUNT4_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 14382 #define USB_COUNT4_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 14383 #define USB_COUNT4_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 14384 #define USB_COUNT4_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 14385
Kojto 122:f9eeca106725 14386 #define USB_COUNT4_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
Kojto 122:f9eeca106725 14387
Kojto 122:f9eeca106725 14388 /**************** Bit definition for USB_COUNT5_RX_0 register ***************/
Kojto 122:f9eeca106725 14389 #define USB_COUNT5_RX_0_COUNT5_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
Kojto 122:f9eeca106725 14390
Kojto 122:f9eeca106725 14391 #define USB_COUNT5_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
Kojto 122:f9eeca106725 14392 #define USB_COUNT5_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
Kojto 122:f9eeca106725 14393 #define USB_COUNT5_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
Kojto 122:f9eeca106725 14394 #define USB_COUNT5_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 14395 #define USB_COUNT5_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 14396 #define USB_COUNT5_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 14397
Kojto 122:f9eeca106725 14398 #define USB_COUNT5_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
Kojto 122:f9eeca106725 14399
Kojto 122:f9eeca106725 14400 /**************** Bit definition for USB_COUNT5_RX_1 register ***************/
Kojto 122:f9eeca106725 14401 #define USB_COUNT5_RX_1_COUNT5_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
Kojto 122:f9eeca106725 14402
Kojto 122:f9eeca106725 14403 #define USB_COUNT5_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
Kojto 122:f9eeca106725 14404 #define USB_COUNT5_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 14405 #define USB_COUNT5_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 14406 #define USB_COUNT5_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 14407 #define USB_COUNT5_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 14408 #define USB_COUNT5_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 14409
Kojto 122:f9eeca106725 14410 #define USB_COUNT5_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
Kojto 122:f9eeca106725 14411
Kojto 122:f9eeca106725 14412 /*************** Bit definition for USB_COUNT6_RX_0 register ***************/
Kojto 122:f9eeca106725 14413 #define USB_COUNT6_RX_0_COUNT6_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
Kojto 122:f9eeca106725 14414
Kojto 122:f9eeca106725 14415 #define USB_COUNT6_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
Kojto 122:f9eeca106725 14416 #define USB_COUNT6_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
Kojto 122:f9eeca106725 14417 #define USB_COUNT6_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
Kojto 122:f9eeca106725 14418 #define USB_COUNT6_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 14419 #define USB_COUNT6_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 14420 #define USB_COUNT6_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 14421
Kojto 122:f9eeca106725 14422 #define USB_COUNT6_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
Kojto 122:f9eeca106725 14423
Kojto 122:f9eeca106725 14424 /**************** Bit definition for USB_COUNT6_RX_1 register ***************/
Kojto 122:f9eeca106725 14425 #define USB_COUNT6_RX_1_COUNT6_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
Kojto 122:f9eeca106725 14426
Kojto 122:f9eeca106725 14427 #define USB_COUNT6_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
Kojto 122:f9eeca106725 14428 #define USB_COUNT6_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 14429 #define USB_COUNT6_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 14430 #define USB_COUNT6_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 14431 #define USB_COUNT6_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 14432 #define USB_COUNT6_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 14433
Kojto 122:f9eeca106725 14434 #define USB_COUNT6_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
Kojto 122:f9eeca106725 14435
Kojto 122:f9eeca106725 14436 /*************** Bit definition for USB_COUNT7_RX_0 register ****************/
Kojto 122:f9eeca106725 14437 #define USB_COUNT7_RX_0_COUNT7_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
Kojto 122:f9eeca106725 14438
Kojto 122:f9eeca106725 14439 #define USB_COUNT7_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
Kojto 122:f9eeca106725 14440 #define USB_COUNT7_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
Kojto 122:f9eeca106725 14441 #define USB_COUNT7_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
Kojto 122:f9eeca106725 14442 #define USB_COUNT7_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 14443 #define USB_COUNT7_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 14444 #define USB_COUNT7_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 14445
Kojto 122:f9eeca106725 14446 #define USB_COUNT7_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
Kojto 122:f9eeca106725 14447
Kojto 122:f9eeca106725 14448 /*************** Bit definition for USB_COUNT7_RX_1 register ****************/
Kojto 122:f9eeca106725 14449 #define USB_COUNT7_RX_1_COUNT7_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
Kojto 122:f9eeca106725 14450
Kojto 122:f9eeca106725 14451 #define USB_COUNT7_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
Kojto 122:f9eeca106725 14452 #define USB_COUNT7_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 14453 #define USB_COUNT7_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 14454 #define USB_COUNT7_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 14455 #define USB_COUNT7_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 14456 #define USB_COUNT7_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 14457
Kojto 122:f9eeca106725 14458 #define USB_COUNT7_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
Kojto 122:f9eeca106725 14459
Kojto 122:f9eeca106725 14460
Kojto 122:f9eeca106725 14461 /**
Kojto 122:f9eeca106725 14462 * @}
Kojto 122:f9eeca106725 14463 */
Kojto 122:f9eeca106725 14464
Kojto 122:f9eeca106725 14465 /**
Kojto 122:f9eeca106725 14466 * @}
Kojto 122:f9eeca106725 14467 */
Kojto 122:f9eeca106725 14468
Kojto 122:f9eeca106725 14469 /** @addtogroup Exported_macros
Kojto 122:f9eeca106725 14470 * @{
Kojto 122:f9eeca106725 14471 */
Kojto 122:f9eeca106725 14472
Kojto 122:f9eeca106725 14473 /******************************* ADC Instances ********************************/
Kojto 122:f9eeca106725 14474 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
Kojto 122:f9eeca106725 14475
Kojto 122:f9eeca106725 14476 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
Kojto 122:f9eeca106725 14477
Kojto 122:f9eeca106725 14478 /******************************** CAN Instances ******************************/
Kojto 122:f9eeca106725 14479 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
Kojto 122:f9eeca106725 14480
Kojto 122:f9eeca106725 14481 /******************************** COMP Instances ******************************/
Kojto 122:f9eeca106725 14482 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
Kojto 122:f9eeca106725 14483 ((INSTANCE) == COMP2))
Kojto 122:f9eeca106725 14484
Kojto 122:f9eeca106725 14485 #define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
Kojto 122:f9eeca106725 14486
Kojto 122:f9eeca106725 14487 /******************** COMP Instances with window mode capability **************/
Kojto 122:f9eeca106725 14488 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
Kojto 122:f9eeca106725 14489
Kojto 122:f9eeca106725 14490 /******************************* CRC Instances ********************************/
Kojto 122:f9eeca106725 14491 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
Kojto 122:f9eeca106725 14492
Kojto 122:f9eeca106725 14493 /******************************* DAC Instances ********************************/
Kojto 122:f9eeca106725 14494 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
Kojto 122:f9eeca106725 14495
Kojto 122:f9eeca106725 14496 /******************************** DMA Instances *******************************/
Kojto 122:f9eeca106725 14497 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
Kojto 122:f9eeca106725 14498 ((INSTANCE) == DMA1_Channel2) || \
Kojto 122:f9eeca106725 14499 ((INSTANCE) == DMA1_Channel3) || \
Kojto 122:f9eeca106725 14500 ((INSTANCE) == DMA1_Channel4) || \
Kojto 122:f9eeca106725 14501 ((INSTANCE) == DMA1_Channel5) || \
Kojto 122:f9eeca106725 14502 ((INSTANCE) == DMA1_Channel6) || \
Kojto 122:f9eeca106725 14503 ((INSTANCE) == DMA1_Channel7) || \
Kojto 122:f9eeca106725 14504 ((INSTANCE) == DMA2_Channel1) || \
Kojto 122:f9eeca106725 14505 ((INSTANCE) == DMA2_Channel2) || \
Kojto 122:f9eeca106725 14506 ((INSTANCE) == DMA2_Channel3) || \
Kojto 122:f9eeca106725 14507 ((INSTANCE) == DMA2_Channel4) || \
Kojto 122:f9eeca106725 14508 ((INSTANCE) == DMA2_Channel5) || \
Kojto 122:f9eeca106725 14509 ((INSTANCE) == DMA2_Channel6) || \
Kojto 122:f9eeca106725 14510 ((INSTANCE) == DMA2_Channel7))
Kojto 122:f9eeca106725 14511
Kojto 122:f9eeca106725 14512 /******************************* GPIO Instances *******************************/
Kojto 122:f9eeca106725 14513 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
Kojto 122:f9eeca106725 14514 ((INSTANCE) == GPIOB) || \
Kojto 122:f9eeca106725 14515 ((INSTANCE) == GPIOC) || \
Kojto 122:f9eeca106725 14516 ((INSTANCE) == GPIOH))
Kojto 122:f9eeca106725 14517
Kojto 122:f9eeca106725 14518 /******************************* GPIO AF Instances ****************************/
Kojto 122:f9eeca106725 14519 /* On L4, all GPIO Bank support AF */
Kojto 122:f9eeca106725 14520 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
Kojto 122:f9eeca106725 14521
Kojto 122:f9eeca106725 14522 /**************************** GPIO Lock Instances *****************************/
Kojto 122:f9eeca106725 14523 /* On L4, all GPIO Bank support the Lock mechanism */
Kojto 122:f9eeca106725 14524 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
Kojto 122:f9eeca106725 14525
Kojto 122:f9eeca106725 14526 /******************************** I2C Instances *******************************/
Kojto 122:f9eeca106725 14527 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
Kojto 122:f9eeca106725 14528 ((INSTANCE) == I2C3))
Kojto 122:f9eeca106725 14529
Kojto 122:f9eeca106725 14530 /****************** I2C Instances : wakeup capability from stop modes *********/
Kojto 122:f9eeca106725 14531 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
Kojto 122:f9eeca106725 14532
Kojto 122:f9eeca106725 14533 /****************************** OPAMP Instances *******************************/
Kojto 122:f9eeca106725 14534 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == OPAMP1)
Kojto 122:f9eeca106725 14535
Kojto 122:f9eeca106725 14536 #define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP1_COMMON)
Kojto 122:f9eeca106725 14537
Kojto 122:f9eeca106725 14538 /******************************* QSPI Instances *******************************/
Kojto 122:f9eeca106725 14539 #define IS_QSPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == QUADSPI)
Kojto 122:f9eeca106725 14540
Kojto 122:f9eeca106725 14541 /******************************* RNG Instances ********************************/
Kojto 122:f9eeca106725 14542 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
Kojto 122:f9eeca106725 14543
Kojto 122:f9eeca106725 14544 /****************************** RTC Instances *********************************/
Kojto 122:f9eeca106725 14545 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
Kojto 122:f9eeca106725 14546
Kojto 122:f9eeca106725 14547 /******************************** SAI Instances *******************************/
Kojto 122:f9eeca106725 14548 #define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
Kojto 122:f9eeca106725 14549 ((INSTANCE) == SAI1_Block_B))
Kojto 122:f9eeca106725 14550
Kojto 122:f9eeca106725 14551 /****************************** SMBUS Instances *******************************/
Kojto 122:f9eeca106725 14552 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
Kojto 122:f9eeca106725 14553 ((INSTANCE) == I2C3))
Kojto 122:f9eeca106725 14554
Kojto 122:f9eeca106725 14555 /******************************** SPI Instances *******************************/
Kojto 122:f9eeca106725 14556 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
Kojto 122:f9eeca106725 14557 ((INSTANCE) == SPI3))
Kojto 122:f9eeca106725 14558
Kojto 122:f9eeca106725 14559 /******************************** SWPMI Instances *****************************/
Kojto 122:f9eeca106725 14560 #define IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1)
Kojto 122:f9eeca106725 14561
Kojto 122:f9eeca106725 14562 /****************** LPTIM Instances : All supported instances *****************/
Kojto 122:f9eeca106725 14563 #define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
Kojto 122:f9eeca106725 14564 ((INSTANCE) == LPTIM2))
Kojto 122:f9eeca106725 14565
Kojto 122:f9eeca106725 14566 /****************** TIM Instances : All supported instances *******************/
Kojto 122:f9eeca106725 14567 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 122:f9eeca106725 14568 ((INSTANCE) == TIM2) || \
Kojto 122:f9eeca106725 14569 ((INSTANCE) == TIM6) || \
Kojto 122:f9eeca106725 14570 ((INSTANCE) == TIM7) || \
Kojto 122:f9eeca106725 14571 ((INSTANCE) == TIM15) || \
Kojto 122:f9eeca106725 14572 ((INSTANCE) == TIM16))
Kojto 122:f9eeca106725 14573
Kojto 122:f9eeca106725 14574 /****************** TIM Instances : supporting 32 bits counter ****************/
Kojto 122:f9eeca106725 14575 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
Kojto 122:f9eeca106725 14576
Kojto 122:f9eeca106725 14577 /****************** TIM Instances : supporting the break function *************/
Kojto 122:f9eeca106725 14578 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 122:f9eeca106725 14579 ((INSTANCE) == TIM15) || \
Kojto 122:f9eeca106725 14580 ((INSTANCE) == TIM16))
Kojto 122:f9eeca106725 14581
Kojto 122:f9eeca106725 14582 /************** TIM Instances : supporting Break source selection *************/
Kojto 122:f9eeca106725 14583 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 122:f9eeca106725 14584 ((INSTANCE) == TIM15) || \
Kojto 122:f9eeca106725 14585 ((INSTANCE) == TIM16))
Kojto 122:f9eeca106725 14586
Kojto 122:f9eeca106725 14587 /****************** TIM Instances : supporting 2 break inputs *****************/
Kojto 122:f9eeca106725 14588 #define IS_TIM_BKIN2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
Kojto 122:f9eeca106725 14589
Kojto 122:f9eeca106725 14590 /************* TIM Instances : at least 1 capture/compare channel *************/
Kojto 122:f9eeca106725 14591 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 122:f9eeca106725 14592 ((INSTANCE) == TIM2) || \
Kojto 122:f9eeca106725 14593 ((INSTANCE) == TIM15) || \
Kojto 122:f9eeca106725 14594 ((INSTANCE) == TIM16))
Kojto 122:f9eeca106725 14595
Kojto 122:f9eeca106725 14596 /************ TIM Instances : at least 2 capture/compare channels *************/
Kojto 122:f9eeca106725 14597 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 122:f9eeca106725 14598 ((INSTANCE) == TIM2) || \
Kojto 122:f9eeca106725 14599 ((INSTANCE) == TIM15))
Kojto 122:f9eeca106725 14600
Kojto 122:f9eeca106725 14601 /************ TIM Instances : at least 3 capture/compare channels *************/
Kojto 122:f9eeca106725 14602 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 122:f9eeca106725 14603 ((INSTANCE) == TIM2))
Kojto 122:f9eeca106725 14604
Kojto 122:f9eeca106725 14605 /************ TIM Instances : at least 4 capture/compare channels *************/
Kojto 122:f9eeca106725 14606 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 122:f9eeca106725 14607 ((INSTANCE) == TIM2))
Kojto 122:f9eeca106725 14608
Kojto 122:f9eeca106725 14609 /****************** TIM Instances : at least 5 capture/compare channels *******/
Kojto 122:f9eeca106725 14610 #define IS_TIM_CC5_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
Kojto 122:f9eeca106725 14611
Kojto 122:f9eeca106725 14612 /****************** TIM Instances : at least 6 capture/compare channels *******/
Kojto 122:f9eeca106725 14613 #define IS_TIM_CC6_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
Kojto 122:f9eeca106725 14614
Kojto 122:f9eeca106725 14615 /************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
Kojto 122:f9eeca106725 14616 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 122:f9eeca106725 14617 ((INSTANCE) == TIM15) || \
Kojto 122:f9eeca106725 14618 ((INSTANCE) == TIM16))
Kojto 122:f9eeca106725 14619
Kojto 122:f9eeca106725 14620 /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
Kojto 122:f9eeca106725 14621 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 122:f9eeca106725 14622 ((INSTANCE) == TIM2) || \
Kojto 122:f9eeca106725 14623 ((INSTANCE) == TIM6) || \
Kojto 122:f9eeca106725 14624 ((INSTANCE) == TIM7) || \
Kojto 122:f9eeca106725 14625 ((INSTANCE) == TIM15) || \
Kojto 122:f9eeca106725 14626 ((INSTANCE) == TIM16))
Kojto 122:f9eeca106725 14627
Kojto 122:f9eeca106725 14628 /************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
Kojto 122:f9eeca106725 14629 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 122:f9eeca106725 14630 ((INSTANCE) == TIM2) || \
Kojto 122:f9eeca106725 14631 ((INSTANCE) == TIM15) || \
Kojto 122:f9eeca106725 14632 ((INSTANCE) == TIM16))
Kojto 122:f9eeca106725 14633
Kojto 122:f9eeca106725 14634 /******************** TIM Instances : DMA burst feature ***********************/
Kojto 122:f9eeca106725 14635 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 122:f9eeca106725 14636 ((INSTANCE) == TIM2) || \
Kojto 122:f9eeca106725 14637 ((INSTANCE) == TIM15) || \
Kojto 122:f9eeca106725 14638 ((INSTANCE) == TIM16))
Kojto 122:f9eeca106725 14639
Kojto 122:f9eeca106725 14640 /******************* TIM Instances : output(s) available **********************/
Kojto 122:f9eeca106725 14641 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
Kojto 122:f9eeca106725 14642 ((((INSTANCE) == TIM1) && \
Kojto 122:f9eeca106725 14643 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 122:f9eeca106725 14644 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 122:f9eeca106725 14645 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 122:f9eeca106725 14646 ((CHANNEL) == TIM_CHANNEL_4) || \
Kojto 122:f9eeca106725 14647 ((CHANNEL) == TIM_CHANNEL_5) || \
Kojto 122:f9eeca106725 14648 ((CHANNEL) == TIM_CHANNEL_6))) \
Kojto 122:f9eeca106725 14649 || \
Kojto 122:f9eeca106725 14650 (((INSTANCE) == TIM2) && \
Kojto 122:f9eeca106725 14651 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 122:f9eeca106725 14652 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 122:f9eeca106725 14653 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 122:f9eeca106725 14654 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 122:f9eeca106725 14655 || \
Kojto 122:f9eeca106725 14656 (((INSTANCE) == TIM15) && \
Kojto 122:f9eeca106725 14657 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 122:f9eeca106725 14658 ((CHANNEL) == TIM_CHANNEL_2))) \
Kojto 122:f9eeca106725 14659 || \
Kojto 122:f9eeca106725 14660 (((INSTANCE) == TIM16) && \
Kojto 122:f9eeca106725 14661 (((CHANNEL) == TIM_CHANNEL_1))))
Kojto 122:f9eeca106725 14662
Kojto 122:f9eeca106725 14663 /****************** TIM Instances : supporting complementary output(s) ********/
Kojto 122:f9eeca106725 14664 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
Kojto 122:f9eeca106725 14665 ((((INSTANCE) == TIM1) && \
Kojto 122:f9eeca106725 14666 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 122:f9eeca106725 14667 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 122:f9eeca106725 14668 ((CHANNEL) == TIM_CHANNEL_3))) \
Kojto 122:f9eeca106725 14669 || \
Kojto 122:f9eeca106725 14670 (((INSTANCE) == TIM15) && \
Kojto 122:f9eeca106725 14671 ((CHANNEL) == TIM_CHANNEL_1)) \
Kojto 122:f9eeca106725 14672 || \
Kojto 122:f9eeca106725 14673 (((INSTANCE) == TIM16) && \
Kojto 122:f9eeca106725 14674 ((CHANNEL) == TIM_CHANNEL_1)))
Kojto 122:f9eeca106725 14675
Kojto 122:f9eeca106725 14676 /****************** TIM Instances : supporting clock division *****************/
Kojto 122:f9eeca106725 14677 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 122:f9eeca106725 14678 ((INSTANCE) == TIM2) || \
Kojto 122:f9eeca106725 14679 ((INSTANCE) == TIM15) || \
Kojto 122:f9eeca106725 14680 ((INSTANCE) == TIM16))
Kojto 122:f9eeca106725 14681
Kojto 122:f9eeca106725 14682 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
Kojto 122:f9eeca106725 14683 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 122:f9eeca106725 14684 ((INSTANCE) == TIM2) || \
Kojto 122:f9eeca106725 14685 ((INSTANCE) == TIM15))
Kojto 122:f9eeca106725 14686
Kojto 122:f9eeca106725 14687 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
Kojto 122:f9eeca106725 14688 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 122:f9eeca106725 14689 ((INSTANCE) == TIM2))
Kojto 122:f9eeca106725 14690
Kojto 122:f9eeca106725 14691 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
Kojto 122:f9eeca106725 14692 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 122:f9eeca106725 14693 ((INSTANCE) == TIM2) || \
Kojto 122:f9eeca106725 14694 ((INSTANCE) == TIM15))
Kojto 122:f9eeca106725 14695
Kojto 122:f9eeca106725 14696 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
Kojto 122:f9eeca106725 14697 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 122:f9eeca106725 14698 ((INSTANCE) == TIM2) || \
Kojto 122:f9eeca106725 14699 ((INSTANCE) == TIM15))
Kojto 122:f9eeca106725 14700
Kojto 122:f9eeca106725 14701 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
Kojto 122:f9eeca106725 14702 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
Kojto 122:f9eeca106725 14703
Kojto 122:f9eeca106725 14704 /****************** TIM Instances : supporting commutation event generation ***/
Kojto 122:f9eeca106725 14705 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 122:f9eeca106725 14706 ((INSTANCE) == TIM15) || \
Kojto 122:f9eeca106725 14707 ((INSTANCE) == TIM16))
Kojto 122:f9eeca106725 14708
Kojto 122:f9eeca106725 14709 /****************** TIM Instances : supporting counting mode selection ********/
Kojto 122:f9eeca106725 14710 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 122:f9eeca106725 14711 ((INSTANCE) == TIM2))
Kojto 122:f9eeca106725 14712
Kojto 122:f9eeca106725 14713 /****************** TIM Instances : supporting encoder interface **************/
Kojto 122:f9eeca106725 14714 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 122:f9eeca106725 14715 ((INSTANCE) == TIM2))
Kojto 122:f9eeca106725 14716
Kojto 122:f9eeca106725 14717 /****************** TIM Instances : supporting Hall sensor interface **********/
Kojto 122:f9eeca106725 14718 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 122:f9eeca106725 14719 ((INSTANCE) == TIM2))
Kojto 122:f9eeca106725 14720
Kojto 122:f9eeca106725 14721 /**************** TIM Instances : external trigger input available ************/
Kojto 122:f9eeca106725 14722 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 122:f9eeca106725 14723 ((INSTANCE) == TIM2))
Kojto 122:f9eeca106725 14724
Kojto 122:f9eeca106725 14725 /************* TIM Instances : supporting ETR source selection ***************/
Kojto 122:f9eeca106725 14726 #define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 122:f9eeca106725 14727 ((INSTANCE) == TIM2))
Kojto 122:f9eeca106725 14728
Kojto 122:f9eeca106725 14729 /****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
Kojto 122:f9eeca106725 14730 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 122:f9eeca106725 14731 ((INSTANCE) == TIM2) || \
Kojto 122:f9eeca106725 14732 ((INSTANCE) == TIM6) || \
Kojto 122:f9eeca106725 14733 ((INSTANCE) == TIM7) || \
Kojto 122:f9eeca106725 14734 ((INSTANCE) == TIM15))
Kojto 122:f9eeca106725 14735
Kojto 122:f9eeca106725 14736 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
Kojto 122:f9eeca106725 14737 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 122:f9eeca106725 14738 ((INSTANCE) == TIM2) || \
Kojto 122:f9eeca106725 14739 ((INSTANCE) == TIM15))
Kojto 122:f9eeca106725 14740
Kojto 122:f9eeca106725 14741 /****************** TIM Instances : supporting OCxREF clear *******************/
Kojto 122:f9eeca106725 14742 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 122:f9eeca106725 14743 ((INSTANCE) == TIM2))
Kojto 122:f9eeca106725 14744
Kojto 122:f9eeca106725 14745 /****************** TIM Instances : remapping capability **********************/
Kojto 122:f9eeca106725 14746 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 122:f9eeca106725 14747 ((INSTANCE) == TIM2) || \
Kojto 122:f9eeca106725 14748 ((INSTANCE) == TIM15) || \
Kojto 122:f9eeca106725 14749 ((INSTANCE) == TIM16))
Kojto 122:f9eeca106725 14750
Kojto 122:f9eeca106725 14751 /****************** TIM Instances : supporting repetition counter *************/
Kojto 122:f9eeca106725 14752 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 122:f9eeca106725 14753 ((INSTANCE) == TIM15) || \
Kojto 122:f9eeca106725 14754 ((INSTANCE) == TIM16))
Kojto 122:f9eeca106725 14755
Kojto 122:f9eeca106725 14756 /****************** TIM Instances : supporting synchronization ****************/
Kojto 122:f9eeca106725 14757 #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
Kojto 122:f9eeca106725 14758
Kojto 122:f9eeca106725 14759 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
Kojto 122:f9eeca106725 14760 #define IS_TIM_TRGO2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
Kojto 122:f9eeca106725 14761
Kojto 122:f9eeca106725 14762 /******************* TIM Instances : Timer input XOR function *****************/
Kojto 122:f9eeca106725 14763 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 122:f9eeca106725 14764 ((INSTANCE) == TIM2) || \
Kojto 122:f9eeca106725 14765 ((INSTANCE) == TIM15))
Kojto 122:f9eeca106725 14766
Kojto 122:f9eeca106725 14767 /****************************** TSC Instances *********************************/
Kojto 122:f9eeca106725 14768 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
Kojto 122:f9eeca106725 14769
Kojto 122:f9eeca106725 14770 /******************** USART Instances : Synchronous mode **********************/
Kojto 122:f9eeca106725 14771 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 122:f9eeca106725 14772 ((INSTANCE) == USART2))
Kojto 122:f9eeca106725 14773
Kojto 122:f9eeca106725 14774 /******************** UART Instances : Asynchronous mode **********************/
Kojto 122:f9eeca106725 14775 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 122:f9eeca106725 14776 ((INSTANCE) == USART2))
Kojto 122:f9eeca106725 14777
Kojto 122:f9eeca106725 14778 /****************** UART Instances : Auto Baud Rate detection ****************/
Kojto 122:f9eeca106725 14779 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 122:f9eeca106725 14780 ((INSTANCE) == USART2))
Kojto 122:f9eeca106725 14781
Kojto 122:f9eeca106725 14782 /****************** UART Instances : Driver Enable *****************/
Kojto 122:f9eeca106725 14783 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 122:f9eeca106725 14784 ((INSTANCE) == USART2) || \
Kojto 122:f9eeca106725 14785 ((INSTANCE) == LPUART1))
Kojto 122:f9eeca106725 14786
Kojto 122:f9eeca106725 14787 /******************** UART Instances : Half-Duplex mode **********************/
Kojto 122:f9eeca106725 14788 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 122:f9eeca106725 14789 ((INSTANCE) == USART2) || \
Kojto 122:f9eeca106725 14790 ((INSTANCE) == LPUART1))
Kojto 122:f9eeca106725 14791
Kojto 122:f9eeca106725 14792 /****************** UART Instances : Hardware Flow control ********************/
Kojto 122:f9eeca106725 14793 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 122:f9eeca106725 14794 ((INSTANCE) == USART2) || \
Kojto 122:f9eeca106725 14795 ((INSTANCE) == LPUART1))
Kojto 122:f9eeca106725 14796
Kojto 122:f9eeca106725 14797 /******************** UART Instances : LIN mode **********************/
Kojto 122:f9eeca106725 14798 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 122:f9eeca106725 14799 ((INSTANCE) == USART2))
Kojto 122:f9eeca106725 14800
Kojto 122:f9eeca106725 14801 /******************** UART Instances : Wake-up from Stop mode **********************/
Kojto 122:f9eeca106725 14802 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 122:f9eeca106725 14803 ((INSTANCE) == USART2) || \
Kojto 122:f9eeca106725 14804 ((INSTANCE) == LPUART1))
Kojto 122:f9eeca106725 14805
Kojto 122:f9eeca106725 14806 /*********************** UART Instances : IRDA mode ***************************/
Kojto 122:f9eeca106725 14807 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 122:f9eeca106725 14808 ((INSTANCE) == USART2))
Kojto 122:f9eeca106725 14809
Kojto 122:f9eeca106725 14810 /********************* USART Instances : Smard card mode ***********************/
Kojto 122:f9eeca106725 14811 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 122:f9eeca106725 14812 ((INSTANCE) == USART2))
Kojto 122:f9eeca106725 14813
Kojto 122:f9eeca106725 14814 /******************** LPUART Instance *****************************************/
Kojto 122:f9eeca106725 14815 #define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
Kojto 122:f9eeca106725 14816
Kojto 122:f9eeca106725 14817 /****************************** IWDG Instances ********************************/
Kojto 122:f9eeca106725 14818 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
Kojto 122:f9eeca106725 14819
Kojto 122:f9eeca106725 14820 /****************************** WWDG Instances ********************************/
Kojto 122:f9eeca106725 14821 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
Kojto 122:f9eeca106725 14822
Kojto 122:f9eeca106725 14823 /******************************* USB Instances *******************************/
Kojto 122:f9eeca106725 14824 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
Kojto 122:f9eeca106725 14825
Kojto 122:f9eeca106725 14826 /**
Kojto 122:f9eeca106725 14827 * @}
Kojto 122:f9eeca106725 14828 */
Kojto 122:f9eeca106725 14829
Kojto 122:f9eeca106725 14830
Kojto 122:f9eeca106725 14831 /******************************************************************************/
Kojto 122:f9eeca106725 14832 /* For a painless codes migration between the STM32L4xx device product */
Kojto 122:f9eeca106725 14833 /* lines, the aliases defined below are put in place to overcome the */
Kojto 122:f9eeca106725 14834 /* differences in the interrupt handlers and IRQn definitions. */
Kojto 122:f9eeca106725 14835 /* No need to update developed interrupt code when moving across */
Kojto 122:f9eeca106725 14836 /* product lines within the same STM32L4 Family */
Kojto 122:f9eeca106725 14837 /******************************************************************************/
Kojto 122:f9eeca106725 14838
Kojto 122:f9eeca106725 14839 /* Aliases for __IRQn */
Kojto 122:f9eeca106725 14840 #define ADC1_2_IRQn ADC1_IRQn
Kojto 122:f9eeca106725 14841 #define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
Kojto 122:f9eeca106725 14842 #define USB_FS_IRQn USB_IRQn
Kojto 122:f9eeca106725 14843
Kojto 122:f9eeca106725 14844 /* Aliases for __IRQHandler */
Kojto 122:f9eeca106725 14845 #define ADC1_2_IRQHandler ADC1_IRQHandler
Kojto 122:f9eeca106725 14846 #define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
Kojto 122:f9eeca106725 14847 #define USB_FS_IRQHandler USB_IRQHandler
Kojto 122:f9eeca106725 14848
Kojto 122:f9eeca106725 14849 #ifdef __cplusplus
Kojto 122:f9eeca106725 14850 }
Kojto 122:f9eeca106725 14851 #endif /* __cplusplus */
Kojto 122:f9eeca106725 14852
Kojto 122:f9eeca106725 14853 #endif /* __STM32L432xx_H */
Kojto 122:f9eeca106725 14854
Kojto 122:f9eeca106725 14855 /**
Kojto 122:f9eeca106725 14856 * @}
Kojto 122:f9eeca106725 14857 */
Kojto 122:f9eeca106725 14858
Kojto 122:f9eeca106725 14859 /**
Kojto 122:f9eeca106725 14860 * @}
Kojto 122:f9eeca106725 14861 */
Kojto 122:f9eeca106725 14862
Kojto 122:f9eeca106725 14863 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/