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Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more
TARGET_MAX32620HSP/TARGET_Maxim/TARGET_MAX32620/device/gpio_regs.h@129:0ab6a29f35bf, 2016-11-08 (annotated)
- Committer:
- <>
- Date:
- Tue Nov 08 17:28:34 2016 +0000
- Revision:
- 129:0ab6a29f35bf
- Parent:
- 128:9bcdf88f62b0
Release 129 of the mbed library
Ports for Upcoming Targets
3011: Add u-blox Sara-N target. https://github.com/ARMmbed/mbed-os/pull/3011
3099: MAX32625 https://github.com/ARMmbed/mbed-os/pull/3099
3151: Add support for FRDM-K82F https://github.com/ARMmbed/mbed-os/pull/3151
3177: New mcu k22512 fixing pr 3136 https://github.com/ARMmbed/mbed-os/pull/3177
Fixes and Changes
3008: NUCLEO_F072RB: Fix wrong timer channel number on pwm PB_5 pin https://github.com/ARMmbed/mbed-os/pull/3008
3013: STM32xx - Change how the ADC internal pins are checked before pinmap_ https://github.com/ARMmbed/mbed-os/pull/3013
3041: [nRF5] - added implementation of API of serial port flow control configuration. https://github.com/ARMmbed/mbed-os/pull/3041
3084: [nrf5] fix in Digital I/O : a gpioe pin was uninitialized badly https://github.com/ARMmbed/mbed-os/pull/3084
3009: TRNG enabled. TRNG APIs implemented. REV A/B/C/D flags removed. Warnings removed https://github.com/ARMmbed/mbed-os/pull/3009
3074: Target stm init gcc alignement https://github.com/ARMmbed/mbed-os/pull/3074
2988: Update of can_api.c fixing #2987 https://github.com/ARMmbed/mbed-os/pull/2988
3173: [Exporters] Add a device_name to microbit entry in targets.json https://github.com/ARMmbed/mbed-os/pull/3173
2969: [nRF52] - switch irq priorities of driver handlers to the lowest level https://github.com/ARMmbed/mbed-os/pull/2969
3184: #3183 Compiler warning in trng_api.c with K64F https://github.com/ARMmbed/mbed-os/pull/3184
3104: [NuMaker] Support CAN and fix PWM CLK error https://github.com/ARMmbed/mbed-os/pull/3104
3186: MultiTech mDot - add back SPI3 pins https://github.com/ARMmbed/mbed-os/pull/3186
3075: nsapi - Add standardized return types for size and errors https://github.com/ARMmbed/mbed-os/pull/3075
3221: u-blox odin w2 drivers update https://github.com/ARMmbed/mbed-os/pull/3221
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 125:2e9cc70d1897 | 1 | /******************************************************************************* |
| AnnaBridge | 125:2e9cc70d1897 | 2 | * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. |
| AnnaBridge | 125:2e9cc70d1897 | 3 | * |
| AnnaBridge | 125:2e9cc70d1897 | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| AnnaBridge | 125:2e9cc70d1897 | 5 | * copy of this software and associated documentation files (the "Software"), |
| AnnaBridge | 125:2e9cc70d1897 | 6 | * to deal in the Software without restriction, including without limitation |
| AnnaBridge | 125:2e9cc70d1897 | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| AnnaBridge | 125:2e9cc70d1897 | 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| AnnaBridge | 125:2e9cc70d1897 | 9 | * Software is furnished to do so, subject to the following conditions: |
| AnnaBridge | 125:2e9cc70d1897 | 10 | * |
| AnnaBridge | 125:2e9cc70d1897 | 11 | * The above copyright notice and this permission notice shall be included |
| AnnaBridge | 125:2e9cc70d1897 | 12 | * in all copies or substantial portions of the Software. |
| AnnaBridge | 125:2e9cc70d1897 | 13 | * |
| AnnaBridge | 125:2e9cc70d1897 | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| AnnaBridge | 125:2e9cc70d1897 | 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| AnnaBridge | 125:2e9cc70d1897 | 16 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| AnnaBridge | 125:2e9cc70d1897 | 17 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
| AnnaBridge | 125:2e9cc70d1897 | 18 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| AnnaBridge | 125:2e9cc70d1897 | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| AnnaBridge | 125:2e9cc70d1897 | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| AnnaBridge | 125:2e9cc70d1897 | 21 | * |
| AnnaBridge | 125:2e9cc70d1897 | 22 | * Except as contained in this notice, the name of Maxim Integrated |
| AnnaBridge | 125:2e9cc70d1897 | 23 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
| AnnaBridge | 125:2e9cc70d1897 | 24 | * Products, Inc. Branding Policy. |
| AnnaBridge | 125:2e9cc70d1897 | 25 | * |
| AnnaBridge | 125:2e9cc70d1897 | 26 | * The mere transfer of this software does not imply any licenses |
| AnnaBridge | 125:2e9cc70d1897 | 27 | * of trade secrets, proprietary technology, copyrights, patents, |
| AnnaBridge | 125:2e9cc70d1897 | 28 | * trademarks, maskwork rights, or any other form of intellectual |
| AnnaBridge | 125:2e9cc70d1897 | 29 | * property whatsoever. Maxim Integrated Products, Inc. retains all |
| AnnaBridge | 125:2e9cc70d1897 | 30 | * ownership rights. |
| AnnaBridge | 125:2e9cc70d1897 | 31 | ******************************************************************************* |
| AnnaBridge | 125:2e9cc70d1897 | 32 | */ |
| AnnaBridge | 125:2e9cc70d1897 | 33 | |
| AnnaBridge | 125:2e9cc70d1897 | 34 | #ifndef _MXC_GPIO_REGS_H_ |
| AnnaBridge | 125:2e9cc70d1897 | 35 | #define _MXC_GPIO_REGS_H_ |
| AnnaBridge | 125:2e9cc70d1897 | 36 | |
| AnnaBridge | 125:2e9cc70d1897 | 37 | #ifdef __cplusplus |
| AnnaBridge | 125:2e9cc70d1897 | 38 | extern "C" { |
| AnnaBridge | 125:2e9cc70d1897 | 39 | #endif |
| AnnaBridge | 125:2e9cc70d1897 | 40 | |
| AnnaBridge | 125:2e9cc70d1897 | 41 | #include <stdint.h> |
| AnnaBridge | 125:2e9cc70d1897 | 42 | |
| AnnaBridge | 125:2e9cc70d1897 | 43 | /* |
| AnnaBridge | 125:2e9cc70d1897 | 44 | If types are not defined elsewhere (CMSIS) define them here |
| AnnaBridge | 125:2e9cc70d1897 | 45 | */ |
| AnnaBridge | 125:2e9cc70d1897 | 46 | #ifndef __IO |
| AnnaBridge | 125:2e9cc70d1897 | 47 | #define __IO volatile |
| AnnaBridge | 125:2e9cc70d1897 | 48 | #endif |
| AnnaBridge | 125:2e9cc70d1897 | 49 | #ifndef __I |
| AnnaBridge | 125:2e9cc70d1897 | 50 | #define __I volatile const |
| AnnaBridge | 125:2e9cc70d1897 | 51 | #endif |
| AnnaBridge | 125:2e9cc70d1897 | 52 | #ifndef __O |
| AnnaBridge | 125:2e9cc70d1897 | 53 | #define __O volatile |
| AnnaBridge | 125:2e9cc70d1897 | 54 | #endif |
| AnnaBridge | 125:2e9cc70d1897 | 55 | |
| AnnaBridge | 125:2e9cc70d1897 | 56 | |
| AnnaBridge | 125:2e9cc70d1897 | 57 | /* |
| AnnaBridge | 125:2e9cc70d1897 | 58 | Typedefed structure(s) for module registers (per instance or section) with direct 32-bit |
| AnnaBridge | 125:2e9cc70d1897 | 59 | access to each register in module. |
| AnnaBridge | 125:2e9cc70d1897 | 60 | */ |
| AnnaBridge | 125:2e9cc70d1897 | 61 | |
| AnnaBridge | 125:2e9cc70d1897 | 62 | /* Offset Register Description |
| AnnaBridge | 125:2e9cc70d1897 | 63 | ============= ============================================================================ */ |
| AnnaBridge | 125:2e9cc70d1897 | 64 | typedef struct { |
| AnnaBridge | 125:2e9cc70d1897 | 65 | __IO uint32_t rst_mode[7]; /* 0x0000-0x0018 Port P[0..6] Default (Power-On Reset) Output Drive Mode */ |
| AnnaBridge | 125:2e9cc70d1897 | 66 | __I uint32_t rsv01C[9]; /* 0x001C-0x003C */ |
| AnnaBridge | 125:2e9cc70d1897 | 67 | __IO uint32_t free[7]; /* 0x0040-0x0058 Port P[0..6] Free for GPIO Operation Flags */ |
| AnnaBridge | 125:2e9cc70d1897 | 68 | __I uint32_t rsv05C[9]; /* 0x005C-0x007C */ |
| AnnaBridge | 125:2e9cc70d1897 | 69 | __IO uint32_t out_mode[7]; /* 0x0080-0x0098 Port P[0..6] Output Drive Mode */ |
| AnnaBridge | 125:2e9cc70d1897 | 70 | __I uint32_t rsv09C[9]; /* 0x009C-0x00BC */ |
| AnnaBridge | 125:2e9cc70d1897 | 71 | __IO uint32_t out_val[7]; /* 0x00C0-0x00D8 Port P[0..6] GPIO Output Value */ |
| AnnaBridge | 125:2e9cc70d1897 | 72 | __I uint32_t rsv0DC[9]; /* 0x00DC-0x00FC */ |
| AnnaBridge | 125:2e9cc70d1897 | 73 | __IO uint32_t func_sel[7]; /* 0x0100-0x0118 Port P[0..6] GPIO Function Select */ |
| AnnaBridge | 125:2e9cc70d1897 | 74 | __I uint32_t rsv11C[9]; /* 0x011C-0x013C */ |
| AnnaBridge | 125:2e9cc70d1897 | 75 | __IO uint32_t in_mode[7]; /* 0x0140-0x0158 Port P[0..6] GPIO Input Monitoring Mode */ |
| AnnaBridge | 125:2e9cc70d1897 | 76 | __I uint32_t rsv15C[9]; /* 0x015C-0x017C */ |
| AnnaBridge | 125:2e9cc70d1897 | 77 | __IO uint32_t in_val[7]; /* 0x0180-0x0198 Port P[0..6] GPIO Input Value */ |
| AnnaBridge | 125:2e9cc70d1897 | 78 | __I uint32_t rsv19C[9]; /* 0x019C-0x01BC */ |
| AnnaBridge | 125:2e9cc70d1897 | 79 | __IO uint32_t int_mode[7]; /* 0x01C0-0x01D8 Port P[0..6] Interrupt Detection Mode */ |
| AnnaBridge | 125:2e9cc70d1897 | 80 | __I uint32_t rsv1DC[9]; /* 0x01DC-0x01FC */ |
| AnnaBridge | 125:2e9cc70d1897 | 81 | __IO uint32_t intfl[7]; /* 0x0200-0x0218 Port P[0..6] Interrupt Flags */ |
| AnnaBridge | 125:2e9cc70d1897 | 82 | __I uint32_t rsv21C[9]; /* 0x021C-0x023C */ |
| AnnaBridge | 125:2e9cc70d1897 | 83 | __IO uint32_t inten[7]; /* 0x0240-0x0258 Port P[0..6] Interrupt Enables */ |
| AnnaBridge | 125:2e9cc70d1897 | 84 | } mxc_gpio_regs_t; |
| AnnaBridge | 125:2e9cc70d1897 | 85 | |
| AnnaBridge | 125:2e9cc70d1897 | 86 | |
| AnnaBridge | 125:2e9cc70d1897 | 87 | /* |
| AnnaBridge | 125:2e9cc70d1897 | 88 | Register offsets for module GPIO. |
| AnnaBridge | 125:2e9cc70d1897 | 89 | */ |
| AnnaBridge | 125:2e9cc70d1897 | 90 | |
| AnnaBridge | 125:2e9cc70d1897 | 91 | #define MXC_R_GPIO_OFFS_RST_MODE_P0 ((uint32_t)0x00000000UL) |
| AnnaBridge | 125:2e9cc70d1897 | 92 | #define MXC_R_GPIO_OFFS_RST_MODE_P1 ((uint32_t)0x00000004UL) |
| AnnaBridge | 125:2e9cc70d1897 | 93 | #define MXC_R_GPIO_OFFS_RST_MODE_P2 ((uint32_t)0x00000008UL) |
| AnnaBridge | 125:2e9cc70d1897 | 94 | #define MXC_R_GPIO_OFFS_RST_MODE_P3 ((uint32_t)0x0000000CUL) |
| AnnaBridge | 125:2e9cc70d1897 | 95 | #define MXC_R_GPIO_OFFS_RST_MODE_P4 ((uint32_t)0x00000010UL) |
| AnnaBridge | 125:2e9cc70d1897 | 96 | #define MXC_R_GPIO_OFFS_RST_MODE_P5 ((uint32_t)0x00000014UL) |
| AnnaBridge | 125:2e9cc70d1897 | 97 | #define MXC_R_GPIO_OFFS_RST_MODE_P6 ((uint32_t)0x00000018UL) |
| AnnaBridge | 125:2e9cc70d1897 | 98 | #define MXC_R_GPIO_OFFS_FREE_P0 ((uint32_t)0x00000040UL) |
| AnnaBridge | 125:2e9cc70d1897 | 99 | #define MXC_R_GPIO_OFFS_FREE_P1 ((uint32_t)0x00000044UL) |
| AnnaBridge | 125:2e9cc70d1897 | 100 | #define MXC_R_GPIO_OFFS_FREE_P2 ((uint32_t)0x00000048UL) |
| AnnaBridge | 125:2e9cc70d1897 | 101 | #define MXC_R_GPIO_OFFS_FREE_P3 ((uint32_t)0x0000004CUL) |
| AnnaBridge | 125:2e9cc70d1897 | 102 | #define MXC_R_GPIO_OFFS_FREE_P4 ((uint32_t)0x00000050UL) |
| AnnaBridge | 125:2e9cc70d1897 | 103 | #define MXC_R_GPIO_OFFS_FREE_P5 ((uint32_t)0x00000054UL) |
| AnnaBridge | 125:2e9cc70d1897 | 104 | #define MXC_R_GPIO_OFFS_FREE_P6 ((uint32_t)0x00000058UL) |
| AnnaBridge | 125:2e9cc70d1897 | 105 | #define MXC_R_GPIO_OFFS_OUT_MODE_P0 ((uint32_t)0x00000080UL) |
| AnnaBridge | 125:2e9cc70d1897 | 106 | #define MXC_R_GPIO_OFFS_OUT_MODE_P1 ((uint32_t)0x00000084UL) |
| AnnaBridge | 125:2e9cc70d1897 | 107 | #define MXC_R_GPIO_OFFS_OUT_MODE_P2 ((uint32_t)0x00000088UL) |
| AnnaBridge | 125:2e9cc70d1897 | 108 | #define MXC_R_GPIO_OFFS_OUT_MODE_P3 ((uint32_t)0x0000008CUL) |
| AnnaBridge | 125:2e9cc70d1897 | 109 | #define MXC_R_GPIO_OFFS_OUT_MODE_P4 ((uint32_t)0x00000090UL) |
| AnnaBridge | 125:2e9cc70d1897 | 110 | #define MXC_R_GPIO_OFFS_OUT_MODE_P5 ((uint32_t)0x00000094UL) |
| AnnaBridge | 125:2e9cc70d1897 | 111 | #define MXC_R_GPIO_OFFS_OUT_MODE_P6 ((uint32_t)0x00000098UL) |
| AnnaBridge | 125:2e9cc70d1897 | 112 | #define MXC_R_GPIO_OFFS_OUT_VAL_P0 ((uint32_t)0x000000C0UL) |
| AnnaBridge | 125:2e9cc70d1897 | 113 | #define MXC_R_GPIO_OFFS_OUT_VAL_P1 ((uint32_t)0x000000C4UL) |
| AnnaBridge | 125:2e9cc70d1897 | 114 | #define MXC_R_GPIO_OFFS_OUT_VAL_P2 ((uint32_t)0x000000C8UL) |
| AnnaBridge | 125:2e9cc70d1897 | 115 | #define MXC_R_GPIO_OFFS_OUT_VAL_P3 ((uint32_t)0x000000CCUL) |
| AnnaBridge | 125:2e9cc70d1897 | 116 | #define MXC_R_GPIO_OFFS_OUT_VAL_P4 ((uint32_t)0x000000D0UL) |
| AnnaBridge | 125:2e9cc70d1897 | 117 | #define MXC_R_GPIO_OFFS_OUT_VAL_P5 ((uint32_t)0x000000D4UL) |
| AnnaBridge | 125:2e9cc70d1897 | 118 | #define MXC_R_GPIO_OFFS_OUT_VAL_P6 ((uint32_t)0x000000D8UL) |
| AnnaBridge | 125:2e9cc70d1897 | 119 | #define MXC_R_GPIO_OFFS_FUNC_SEL_P0 ((uint32_t)0x00000100UL) |
| AnnaBridge | 125:2e9cc70d1897 | 120 | #define MXC_R_GPIO_OFFS_FUNC_SEL_P1 ((uint32_t)0x00000104UL) |
| AnnaBridge | 125:2e9cc70d1897 | 121 | #define MXC_R_GPIO_OFFS_FUNC_SEL_P2 ((uint32_t)0x00000108UL) |
| AnnaBridge | 125:2e9cc70d1897 | 122 | #define MXC_R_GPIO_OFFS_FUNC_SEL_P3 ((uint32_t)0x0000010CUL) |
| AnnaBridge | 125:2e9cc70d1897 | 123 | #define MXC_R_GPIO_OFFS_FUNC_SEL_P4 ((uint32_t)0x00000110UL) |
| AnnaBridge | 125:2e9cc70d1897 | 124 | #define MXC_R_GPIO_OFFS_FUNC_SEL_P5 ((uint32_t)0x00000114UL) |
| AnnaBridge | 125:2e9cc70d1897 | 125 | #define MXC_R_GPIO_OFFS_FUNC_SEL_P6 ((uint32_t)0x00000118UL) |
| AnnaBridge | 125:2e9cc70d1897 | 126 | #define MXC_R_GPIO_OFFS_IN_MODE_P0 ((uint32_t)0x00000140UL) |
| AnnaBridge | 125:2e9cc70d1897 | 127 | #define MXC_R_GPIO_OFFS_IN_MODE_P1 ((uint32_t)0x00000144UL) |
| AnnaBridge | 125:2e9cc70d1897 | 128 | #define MXC_R_GPIO_OFFS_IN_MODE_P2 ((uint32_t)0x00000148UL) |
| AnnaBridge | 125:2e9cc70d1897 | 129 | #define MXC_R_GPIO_OFFS_IN_MODE_P3 ((uint32_t)0x0000014CUL) |
| AnnaBridge | 125:2e9cc70d1897 | 130 | #define MXC_R_GPIO_OFFS_IN_MODE_P4 ((uint32_t)0x00000150UL) |
| AnnaBridge | 125:2e9cc70d1897 | 131 | #define MXC_R_GPIO_OFFS_IN_MODE_P5 ((uint32_t)0x00000154UL) |
| AnnaBridge | 125:2e9cc70d1897 | 132 | #define MXC_R_GPIO_OFFS_IN_MODE_P6 ((uint32_t)0x00000158UL) |
| AnnaBridge | 125:2e9cc70d1897 | 133 | #define MXC_R_GPIO_OFFS_IN_VAL_P0 ((uint32_t)0x00000180UL) |
| AnnaBridge | 125:2e9cc70d1897 | 134 | #define MXC_R_GPIO_OFFS_IN_VAL_P1 ((uint32_t)0x00000184UL) |
| AnnaBridge | 125:2e9cc70d1897 | 135 | #define MXC_R_GPIO_OFFS_IN_VAL_P2 ((uint32_t)0x00000188UL) |
| AnnaBridge | 125:2e9cc70d1897 | 136 | #define MXC_R_GPIO_OFFS_IN_VAL_P3 ((uint32_t)0x0000018CUL) |
| AnnaBridge | 125:2e9cc70d1897 | 137 | #define MXC_R_GPIO_OFFS_IN_VAL_P4 ((uint32_t)0x00000190UL) |
| AnnaBridge | 125:2e9cc70d1897 | 138 | #define MXC_R_GPIO_OFFS_IN_VAL_P5 ((uint32_t)0x00000194UL) |
| AnnaBridge | 125:2e9cc70d1897 | 139 | #define MXC_R_GPIO_OFFS_IN_VAL_P6 ((uint32_t)0x00000198UL) |
| AnnaBridge | 125:2e9cc70d1897 | 140 | #define MXC_R_GPIO_OFFS_INT_MODE_P0 ((uint32_t)0x000001C0UL) |
| AnnaBridge | 125:2e9cc70d1897 | 141 | #define MXC_R_GPIO_OFFS_INT_MODE_P1 ((uint32_t)0x000001C4UL) |
| AnnaBridge | 125:2e9cc70d1897 | 142 | #define MXC_R_GPIO_OFFS_INT_MODE_P2 ((uint32_t)0x000001C8UL) |
| AnnaBridge | 125:2e9cc70d1897 | 143 | #define MXC_R_GPIO_OFFS_INT_MODE_P3 ((uint32_t)0x000001CCUL) |
| AnnaBridge | 125:2e9cc70d1897 | 144 | #define MXC_R_GPIO_OFFS_INT_MODE_P4 ((uint32_t)0x000001D0UL) |
| AnnaBridge | 125:2e9cc70d1897 | 145 | #define MXC_R_GPIO_OFFS_INT_MODE_P5 ((uint32_t)0x000001D4UL) |
| AnnaBridge | 125:2e9cc70d1897 | 146 | #define MXC_R_GPIO_OFFS_INT_MODE_P6 ((uint32_t)0x000001D8UL) |
| AnnaBridge | 125:2e9cc70d1897 | 147 | #define MXC_R_GPIO_OFFS_INTFL_P0 ((uint32_t)0x00000200UL) |
| AnnaBridge | 125:2e9cc70d1897 | 148 | #define MXC_R_GPIO_OFFS_INTFL_P1 ((uint32_t)0x00000204UL) |
| AnnaBridge | 125:2e9cc70d1897 | 149 | #define MXC_R_GPIO_OFFS_INTFL_P2 ((uint32_t)0x00000208UL) |
| AnnaBridge | 125:2e9cc70d1897 | 150 | #define MXC_R_GPIO_OFFS_INTFL_P3 ((uint32_t)0x0000020CUL) |
| AnnaBridge | 125:2e9cc70d1897 | 151 | #define MXC_R_GPIO_OFFS_INTFL_P4 ((uint32_t)0x00000210UL) |
| AnnaBridge | 125:2e9cc70d1897 | 152 | #define MXC_R_GPIO_OFFS_INTFL_P5 ((uint32_t)0x00000214UL) |
| AnnaBridge | 125:2e9cc70d1897 | 153 | #define MXC_R_GPIO_OFFS_INTFL_P6 ((uint32_t)0x00000218UL) |
| AnnaBridge | 125:2e9cc70d1897 | 154 | #define MXC_R_GPIO_OFFS_INTEN_P0 ((uint32_t)0x00000240UL) |
| AnnaBridge | 125:2e9cc70d1897 | 155 | #define MXC_R_GPIO_OFFS_INTEN_P1 ((uint32_t)0x00000244UL) |
| AnnaBridge | 125:2e9cc70d1897 | 156 | #define MXC_R_GPIO_OFFS_INTEN_P2 ((uint32_t)0x00000248UL) |
| AnnaBridge | 125:2e9cc70d1897 | 157 | #define MXC_R_GPIO_OFFS_INTEN_P3 ((uint32_t)0x0000024CUL) |
| AnnaBridge | 125:2e9cc70d1897 | 158 | #define MXC_R_GPIO_OFFS_INTEN_P4 ((uint32_t)0x00000250UL) |
| AnnaBridge | 125:2e9cc70d1897 | 159 | #define MXC_R_GPIO_OFFS_INTEN_P5 ((uint32_t)0x00000254UL) |
| AnnaBridge | 125:2e9cc70d1897 | 160 | #define MXC_R_GPIO_OFFS_INTEN_P6 ((uint32_t)0x00000258UL) |
| AnnaBridge | 125:2e9cc70d1897 | 161 | |
| AnnaBridge | 125:2e9cc70d1897 | 162 | |
| AnnaBridge | 125:2e9cc70d1897 | 163 | /* |
| AnnaBridge | 125:2e9cc70d1897 | 164 | Field positions and masks for module GPIO. |
| AnnaBridge | 125:2e9cc70d1897 | 165 | */ |
| AnnaBridge | 125:2e9cc70d1897 | 166 | |
| AnnaBridge | 125:2e9cc70d1897 | 167 | #define MXC_F_GPIO_RST_MODE_PIN0_POS 0 |
| AnnaBridge | 125:2e9cc70d1897 | 168 | #define MXC_F_GPIO_RST_MODE_PIN0 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN0_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 169 | #define MXC_F_GPIO_RST_MODE_PIN1_POS 4 |
| AnnaBridge | 125:2e9cc70d1897 | 170 | #define MXC_F_GPIO_RST_MODE_PIN1 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN1_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 171 | #define MXC_F_GPIO_RST_MODE_PIN2_POS 8 |
| AnnaBridge | 125:2e9cc70d1897 | 172 | #define MXC_F_GPIO_RST_MODE_PIN2 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN2_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 173 | #define MXC_F_GPIO_RST_MODE_PIN3_POS 12 |
| AnnaBridge | 125:2e9cc70d1897 | 174 | #define MXC_F_GPIO_RST_MODE_PIN3 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN3_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 175 | #define MXC_F_GPIO_RST_MODE_PIN4_POS 16 |
| AnnaBridge | 125:2e9cc70d1897 | 176 | #define MXC_F_GPIO_RST_MODE_PIN4 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN4_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 177 | #define MXC_F_GPIO_RST_MODE_PIN5_POS 20 |
| AnnaBridge | 125:2e9cc70d1897 | 178 | #define MXC_F_GPIO_RST_MODE_PIN5 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN5_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 179 | #define MXC_F_GPIO_RST_MODE_PIN6_POS 24 |
| AnnaBridge | 125:2e9cc70d1897 | 180 | #define MXC_F_GPIO_RST_MODE_PIN6 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN6_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 181 | #define MXC_F_GPIO_RST_MODE_PIN7_POS 28 |
| AnnaBridge | 125:2e9cc70d1897 | 182 | #define MXC_F_GPIO_RST_MODE_PIN7 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN7_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 183 | |
| AnnaBridge | 125:2e9cc70d1897 | 184 | #define MXC_F_GPIO_FREE_PIN0_POS 0 |
| AnnaBridge | 125:2e9cc70d1897 | 185 | #define MXC_F_GPIO_FREE_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN0_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 186 | #define MXC_F_GPIO_FREE_PIN1_POS 1 |
| AnnaBridge | 125:2e9cc70d1897 | 187 | #define MXC_F_GPIO_FREE_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN1_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 188 | #define MXC_F_GPIO_FREE_PIN2_POS 2 |
| AnnaBridge | 125:2e9cc70d1897 | 189 | #define MXC_F_GPIO_FREE_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN2_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 190 | #define MXC_F_GPIO_FREE_PIN3_POS 3 |
| AnnaBridge | 125:2e9cc70d1897 | 191 | #define MXC_F_GPIO_FREE_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN3_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 192 | #define MXC_F_GPIO_FREE_PIN4_POS 4 |
| AnnaBridge | 125:2e9cc70d1897 | 193 | #define MXC_F_GPIO_FREE_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN4_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 194 | #define MXC_F_GPIO_FREE_PIN5_POS 5 |
| AnnaBridge | 125:2e9cc70d1897 | 195 | #define MXC_F_GPIO_FREE_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN5_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 196 | #define MXC_F_GPIO_FREE_PIN6_POS 6 |
| AnnaBridge | 125:2e9cc70d1897 | 197 | #define MXC_F_GPIO_FREE_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN6_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 198 | #define MXC_F_GPIO_FREE_PIN7_POS 7 |
| AnnaBridge | 125:2e9cc70d1897 | 199 | #define MXC_F_GPIO_FREE_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN7_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 200 | |
| AnnaBridge | 125:2e9cc70d1897 | 201 | #define MXC_F_GPIO_OUT_MODE_PIN0_POS 0 |
| AnnaBridge | 125:2e9cc70d1897 | 202 | #define MXC_F_GPIO_OUT_MODE_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN0_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 203 | #define MXC_F_GPIO_OUT_MODE_PIN1_POS 4 |
| AnnaBridge | 125:2e9cc70d1897 | 204 | #define MXC_F_GPIO_OUT_MODE_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN1_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 205 | #define MXC_F_GPIO_OUT_MODE_PIN2_POS 8 |
| AnnaBridge | 125:2e9cc70d1897 | 206 | #define MXC_F_GPIO_OUT_MODE_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN2_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 207 | #define MXC_F_GPIO_OUT_MODE_PIN3_POS 12 |
| AnnaBridge | 125:2e9cc70d1897 | 208 | #define MXC_F_GPIO_OUT_MODE_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN3_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 209 | #define MXC_F_GPIO_OUT_MODE_PIN4_POS 16 |
| AnnaBridge | 125:2e9cc70d1897 | 210 | #define MXC_F_GPIO_OUT_MODE_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN4_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 211 | #define MXC_F_GPIO_OUT_MODE_PIN5_POS 20 |
| AnnaBridge | 125:2e9cc70d1897 | 212 | #define MXC_F_GPIO_OUT_MODE_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN5_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 213 | #define MXC_F_GPIO_OUT_MODE_PIN6_POS 24 |
| AnnaBridge | 125:2e9cc70d1897 | 214 | #define MXC_F_GPIO_OUT_MODE_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN6_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 215 | #define MXC_F_GPIO_OUT_MODE_PIN7_POS 28 |
| AnnaBridge | 125:2e9cc70d1897 | 216 | #define MXC_F_GPIO_OUT_MODE_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN7_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 217 | |
| AnnaBridge | 125:2e9cc70d1897 | 218 | #define MXC_F_GPIO_OUT_VAL_PIN0_POS 0 |
| AnnaBridge | 125:2e9cc70d1897 | 219 | #define MXC_F_GPIO_OUT_VAL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN0_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 220 | #define MXC_F_GPIO_OUT_VAL_PIN1_POS 1 |
| AnnaBridge | 125:2e9cc70d1897 | 221 | #define MXC_F_GPIO_OUT_VAL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN1_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 222 | #define MXC_F_GPIO_OUT_VAL_PIN2_POS 2 |
| AnnaBridge | 125:2e9cc70d1897 | 223 | #define MXC_F_GPIO_OUT_VAL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN2_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 224 | #define MXC_F_GPIO_OUT_VAL_PIN3_POS 3 |
| AnnaBridge | 125:2e9cc70d1897 | 225 | #define MXC_F_GPIO_OUT_VAL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN3_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 226 | #define MXC_F_GPIO_OUT_VAL_PIN4_POS 4 |
| AnnaBridge | 125:2e9cc70d1897 | 227 | #define MXC_F_GPIO_OUT_VAL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN4_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 228 | #define MXC_F_GPIO_OUT_VAL_PIN5_POS 5 |
| AnnaBridge | 125:2e9cc70d1897 | 229 | #define MXC_F_GPIO_OUT_VAL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN5_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 230 | #define MXC_F_GPIO_OUT_VAL_PIN6_POS 6 |
| AnnaBridge | 125:2e9cc70d1897 | 231 | #define MXC_F_GPIO_OUT_VAL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN6_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 232 | #define MXC_F_GPIO_OUT_VAL_PIN7_POS 7 |
| AnnaBridge | 125:2e9cc70d1897 | 233 | #define MXC_F_GPIO_OUT_VAL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN7_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 234 | |
| AnnaBridge | 125:2e9cc70d1897 | 235 | #define MXC_F_GPIO_FUNC_SEL_P0_PIN0_POS 0 |
| AnnaBridge | 125:2e9cc70d1897 | 236 | #define MXC_F_GPIO_FUNC_SEL_P0_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P0_PIN0_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 237 | #define MXC_F_GPIO_FUNC_SEL_P0_PIN1_POS 4 |
| AnnaBridge | 125:2e9cc70d1897 | 238 | #define MXC_F_GPIO_FUNC_SEL_P0_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P0_PIN1_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 239 | #define MXC_F_GPIO_FUNC_SEL_P0_PIN2_POS 8 |
| AnnaBridge | 125:2e9cc70d1897 | 240 | #define MXC_F_GPIO_FUNC_SEL_P0_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P0_PIN2_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 241 | #define MXC_F_GPIO_FUNC_SEL_P0_PIN3_POS 12 |
| AnnaBridge | 125:2e9cc70d1897 | 242 | #define MXC_F_GPIO_FUNC_SEL_P0_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P0_PIN3_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 243 | #define MXC_F_GPIO_FUNC_SEL_P0_PIN4_POS 16 |
| AnnaBridge | 125:2e9cc70d1897 | 244 | #define MXC_F_GPIO_FUNC_SEL_P0_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P0_PIN4_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 245 | #define MXC_F_GPIO_FUNC_SEL_P0_PIN5_POS 20 |
| AnnaBridge | 125:2e9cc70d1897 | 246 | #define MXC_F_GPIO_FUNC_SEL_P0_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P0_PIN5_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 247 | #define MXC_F_GPIO_FUNC_SEL_P0_PIN6_POS 24 |
| AnnaBridge | 125:2e9cc70d1897 | 248 | #define MXC_F_GPIO_FUNC_SEL_P0_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P0_PIN6_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 249 | #define MXC_F_GPIO_FUNC_SEL_P0_PIN7_POS 28 |
| AnnaBridge | 125:2e9cc70d1897 | 250 | #define MXC_F_GPIO_FUNC_SEL_P0_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P0_PIN7_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 251 | |
| AnnaBridge | 125:2e9cc70d1897 | 252 | #define MXC_F_GPIO_FUNC_SEL_P1_PIN0_POS 0 |
| AnnaBridge | 125:2e9cc70d1897 | 253 | #define MXC_F_GPIO_FUNC_SEL_P1_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P1_PIN0_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 254 | #define MXC_F_GPIO_FUNC_SEL_P1_PIN1_POS 4 |
| AnnaBridge | 125:2e9cc70d1897 | 255 | #define MXC_F_GPIO_FUNC_SEL_P1_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P1_PIN1_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 256 | #define MXC_F_GPIO_FUNC_SEL_P1_PIN2_POS 8 |
| AnnaBridge | 125:2e9cc70d1897 | 257 | #define MXC_F_GPIO_FUNC_SEL_P1_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P1_PIN2_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 258 | #define MXC_F_GPIO_FUNC_SEL_P1_PIN3_POS 12 |
| AnnaBridge | 125:2e9cc70d1897 | 259 | #define MXC_F_GPIO_FUNC_SEL_P1_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P1_PIN3_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 260 | #define MXC_F_GPIO_FUNC_SEL_P1_PIN4_POS 16 |
| AnnaBridge | 125:2e9cc70d1897 | 261 | #define MXC_F_GPIO_FUNC_SEL_P1_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P1_PIN4_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 262 | #define MXC_F_GPIO_FUNC_SEL_P1_PIN5_POS 20 |
| AnnaBridge | 125:2e9cc70d1897 | 263 | #define MXC_F_GPIO_FUNC_SEL_P1_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P1_PIN5_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 264 | #define MXC_F_GPIO_FUNC_SEL_P1_PIN6_POS 24 |
| AnnaBridge | 125:2e9cc70d1897 | 265 | #define MXC_F_GPIO_FUNC_SEL_P1_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P1_PIN6_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 266 | #define MXC_F_GPIO_FUNC_SEL_P1_PIN7_POS 28 |
| AnnaBridge | 125:2e9cc70d1897 | 267 | #define MXC_F_GPIO_FUNC_SEL_P1_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P1_PIN7_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 268 | |
| AnnaBridge | 125:2e9cc70d1897 | 269 | #define MXC_F_GPIO_FUNC_SEL_P2_PIN0_POS 0 |
| AnnaBridge | 125:2e9cc70d1897 | 270 | #define MXC_F_GPIO_FUNC_SEL_P2_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P2_PIN0_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 271 | #define MXC_F_GPIO_FUNC_SEL_P2_PIN1_POS 4 |
| AnnaBridge | 125:2e9cc70d1897 | 272 | #define MXC_F_GPIO_FUNC_SEL_P2_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P2_PIN1_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 273 | #define MXC_F_GPIO_FUNC_SEL_P2_PIN2_POS 8 |
| AnnaBridge | 125:2e9cc70d1897 | 274 | #define MXC_F_GPIO_FUNC_SEL_P2_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P2_PIN2_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 275 | #define MXC_F_GPIO_FUNC_SEL_P2_PIN3_POS 12 |
| AnnaBridge | 125:2e9cc70d1897 | 276 | #define MXC_F_GPIO_FUNC_SEL_P2_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P2_PIN3_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 277 | #define MXC_F_GPIO_FUNC_SEL_P2_PIN4_POS 16 |
| AnnaBridge | 125:2e9cc70d1897 | 278 | #define MXC_F_GPIO_FUNC_SEL_P2_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P2_PIN4_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 279 | #define MXC_F_GPIO_FUNC_SEL_P2_PIN5_POS 20 |
| AnnaBridge | 125:2e9cc70d1897 | 280 | #define MXC_F_GPIO_FUNC_SEL_P2_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P2_PIN5_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 281 | #define MXC_F_GPIO_FUNC_SEL_P2_PIN6_POS 24 |
| AnnaBridge | 125:2e9cc70d1897 | 282 | #define MXC_F_GPIO_FUNC_SEL_P2_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P2_PIN6_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 283 | #define MXC_F_GPIO_FUNC_SEL_P2_PIN7_POS 28 |
| AnnaBridge | 125:2e9cc70d1897 | 284 | #define MXC_F_GPIO_FUNC_SEL_P2_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P2_PIN7_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 285 | |
| AnnaBridge | 125:2e9cc70d1897 | 286 | #define MXC_F_GPIO_FUNC_SEL_P3_PIN0_POS 0 |
| AnnaBridge | 125:2e9cc70d1897 | 287 | #define MXC_F_GPIO_FUNC_SEL_P3_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P3_PIN0_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 288 | #define MXC_F_GPIO_FUNC_SEL_P3_PIN1_POS 4 |
| AnnaBridge | 125:2e9cc70d1897 | 289 | #define MXC_F_GPIO_FUNC_SEL_P3_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P3_PIN1_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 290 | #define MXC_F_GPIO_FUNC_SEL_P3_PIN2_POS 8 |
| AnnaBridge | 125:2e9cc70d1897 | 291 | #define MXC_F_GPIO_FUNC_SEL_P3_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P3_PIN2_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 292 | #define MXC_F_GPIO_FUNC_SEL_P3_PIN3_POS 12 |
| AnnaBridge | 125:2e9cc70d1897 | 293 | #define MXC_F_GPIO_FUNC_SEL_P3_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P3_PIN3_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 294 | #define MXC_F_GPIO_FUNC_SEL_P3_PIN4_POS 16 |
| AnnaBridge | 125:2e9cc70d1897 | 295 | #define MXC_F_GPIO_FUNC_SEL_P3_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P3_PIN4_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 296 | #define MXC_F_GPIO_FUNC_SEL_P3_PIN5_POS 20 |
| AnnaBridge | 125:2e9cc70d1897 | 297 | #define MXC_F_GPIO_FUNC_SEL_P3_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P3_PIN5_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 298 | #define MXC_F_GPIO_FUNC_SEL_P3_PIN6_POS 24 |
| AnnaBridge | 125:2e9cc70d1897 | 299 | #define MXC_F_GPIO_FUNC_SEL_P3_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P3_PIN6_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 300 | #define MXC_F_GPIO_FUNC_SEL_P3_PIN7_POS 28 |
| AnnaBridge | 125:2e9cc70d1897 | 301 | #define MXC_F_GPIO_FUNC_SEL_P3_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P3_PIN7_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 302 | |
| AnnaBridge | 125:2e9cc70d1897 | 303 | #define MXC_F_GPIO_FUNC_SEL_P4_PIN0_POS 0 |
| AnnaBridge | 125:2e9cc70d1897 | 304 | #define MXC_F_GPIO_FUNC_SEL_P4_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P4_PIN0_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 305 | #define MXC_F_GPIO_FUNC_SEL_P4_PIN1_POS 4 |
| AnnaBridge | 125:2e9cc70d1897 | 306 | #define MXC_F_GPIO_FUNC_SEL_P4_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P4_PIN1_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 307 | #define MXC_F_GPIO_FUNC_SEL_P4_PIN2_POS 8 |
| AnnaBridge | 125:2e9cc70d1897 | 308 | #define MXC_F_GPIO_FUNC_SEL_P4_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P4_PIN2_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 309 | #define MXC_F_GPIO_FUNC_SEL_P4_PIN3_POS 12 |
| AnnaBridge | 125:2e9cc70d1897 | 310 | #define MXC_F_GPIO_FUNC_SEL_P4_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P4_PIN3_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 311 | #define MXC_F_GPIO_FUNC_SEL_P4_PIN4_POS 16 |
| AnnaBridge | 125:2e9cc70d1897 | 312 | #define MXC_F_GPIO_FUNC_SEL_P4_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P4_PIN4_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 313 | #define MXC_F_GPIO_FUNC_SEL_P4_PIN5_POS 20 |
| AnnaBridge | 125:2e9cc70d1897 | 314 | #define MXC_F_GPIO_FUNC_SEL_P4_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P4_PIN5_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 315 | #define MXC_F_GPIO_FUNC_SEL_P4_PIN6_POS 24 |
| AnnaBridge | 125:2e9cc70d1897 | 316 | #define MXC_F_GPIO_FUNC_SEL_P4_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P4_PIN6_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 317 | #define MXC_F_GPIO_FUNC_SEL_P4_PIN7_POS 28 |
| AnnaBridge | 125:2e9cc70d1897 | 318 | #define MXC_F_GPIO_FUNC_SEL_P4_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P4_PIN7_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 319 | |
| AnnaBridge | 125:2e9cc70d1897 | 320 | #define MXC_F_GPIO_FUNC_SEL_P5_PIN0_POS 0 |
| AnnaBridge | 125:2e9cc70d1897 | 321 | #define MXC_F_GPIO_FUNC_SEL_P5_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P5_PIN0_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 322 | #define MXC_F_GPIO_FUNC_SEL_P5_PIN1_POS 4 |
| AnnaBridge | 125:2e9cc70d1897 | 323 | #define MXC_F_GPIO_FUNC_SEL_P5_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P5_PIN1_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 324 | #define MXC_F_GPIO_FUNC_SEL_P5_PIN2_POS 8 |
| AnnaBridge | 125:2e9cc70d1897 | 325 | #define MXC_F_GPIO_FUNC_SEL_P5_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P5_PIN2_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 326 | #define MXC_F_GPIO_FUNC_SEL_P5_PIN3_POS 12 |
| AnnaBridge | 125:2e9cc70d1897 | 327 | #define MXC_F_GPIO_FUNC_SEL_P5_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P5_PIN3_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 328 | #define MXC_F_GPIO_FUNC_SEL_P5_PIN4_POS 16 |
| AnnaBridge | 125:2e9cc70d1897 | 329 | #define MXC_F_GPIO_FUNC_SEL_P5_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P5_PIN4_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 330 | #define MXC_F_GPIO_FUNC_SEL_P5_PIN5_POS 20 |
| AnnaBridge | 125:2e9cc70d1897 | 331 | #define MXC_F_GPIO_FUNC_SEL_P5_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P5_PIN5_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 332 | #define MXC_F_GPIO_FUNC_SEL_P5_PIN6_POS 24 |
| AnnaBridge | 125:2e9cc70d1897 | 333 | #define MXC_F_GPIO_FUNC_SEL_P5_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P5_PIN6_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 334 | #define MXC_F_GPIO_FUNC_SEL_P5_PIN7_POS 28 |
| AnnaBridge | 125:2e9cc70d1897 | 335 | #define MXC_F_GPIO_FUNC_SEL_P5_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P5_PIN7_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 336 | |
| AnnaBridge | 125:2e9cc70d1897 | 337 | #define MXC_F_GPIO_FUNC_SEL_P6_PIN0_POS 0 |
| AnnaBridge | 125:2e9cc70d1897 | 338 | #define MXC_F_GPIO_FUNC_SEL_P6_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P6_PIN0_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 339 | |
| AnnaBridge | 125:2e9cc70d1897 | 340 | #define MXC_F_GPIO_IN_MODE_PIN0_POS 0 |
| AnnaBridge | 125:2e9cc70d1897 | 341 | #define MXC_F_GPIO_IN_MODE_PIN0 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN0_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 342 | #define MXC_F_GPIO_IN_MODE_PIN1_POS 4 |
| AnnaBridge | 125:2e9cc70d1897 | 343 | #define MXC_F_GPIO_IN_MODE_PIN1 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN1_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 344 | #define MXC_F_GPIO_IN_MODE_PIN2_POS 8 |
| AnnaBridge | 125:2e9cc70d1897 | 345 | #define MXC_F_GPIO_IN_MODE_PIN2 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN2_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 346 | #define MXC_F_GPIO_IN_MODE_PIN3_POS 12 |
| AnnaBridge | 125:2e9cc70d1897 | 347 | #define MXC_F_GPIO_IN_MODE_PIN3 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN3_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 348 | #define MXC_F_GPIO_IN_MODE_PIN4_POS 16 |
| AnnaBridge | 125:2e9cc70d1897 | 349 | #define MXC_F_GPIO_IN_MODE_PIN4 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN4_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 350 | #define MXC_F_GPIO_IN_MODE_PIN5_POS 20 |
| AnnaBridge | 125:2e9cc70d1897 | 351 | #define MXC_F_GPIO_IN_MODE_PIN5 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN5_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 352 | #define MXC_F_GPIO_IN_MODE_PIN6_POS 24 |
| AnnaBridge | 125:2e9cc70d1897 | 353 | #define MXC_F_GPIO_IN_MODE_PIN6 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN6_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 354 | #define MXC_F_GPIO_IN_MODE_PIN7_POS 28 |
| AnnaBridge | 125:2e9cc70d1897 | 355 | #define MXC_F_GPIO_IN_MODE_PIN7 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN7_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 356 | |
| AnnaBridge | 125:2e9cc70d1897 | 357 | #define MXC_F_GPIO_IN_VAL_PIN0_POS 0 |
| AnnaBridge | 125:2e9cc70d1897 | 358 | #define MXC_F_GPIO_IN_VAL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN0_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 359 | #define MXC_F_GPIO_IN_VAL_PIN1_POS 1 |
| AnnaBridge | 125:2e9cc70d1897 | 360 | #define MXC_F_GPIO_IN_VAL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN1_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 361 | #define MXC_F_GPIO_IN_VAL_PIN2_POS 2 |
| AnnaBridge | 125:2e9cc70d1897 | 362 | #define MXC_F_GPIO_IN_VAL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN2_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 363 | #define MXC_F_GPIO_IN_VAL_PIN3_POS 3 |
| AnnaBridge | 125:2e9cc70d1897 | 364 | #define MXC_F_GPIO_IN_VAL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN3_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 365 | #define MXC_F_GPIO_IN_VAL_PIN4_POS 4 |
| AnnaBridge | 125:2e9cc70d1897 | 366 | #define MXC_F_GPIO_IN_VAL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN4_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 367 | #define MXC_F_GPIO_IN_VAL_PIN5_POS 5 |
| AnnaBridge | 125:2e9cc70d1897 | 368 | #define MXC_F_GPIO_IN_VAL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN5_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 369 | #define MXC_F_GPIO_IN_VAL_PIN6_POS 6 |
| AnnaBridge | 125:2e9cc70d1897 | 370 | #define MXC_F_GPIO_IN_VAL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN6_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 371 | #define MXC_F_GPIO_IN_VAL_PIN7_POS 7 |
| AnnaBridge | 125:2e9cc70d1897 | 372 | #define MXC_F_GPIO_IN_VAL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN7_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 373 | |
| AnnaBridge | 125:2e9cc70d1897 | 374 | #define MXC_F_GPIO_INT_MODE_PIN0_POS 0 |
| AnnaBridge | 125:2e9cc70d1897 | 375 | #define MXC_F_GPIO_INT_MODE_PIN0 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN0_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 376 | #define MXC_F_GPIO_INT_MODE_PIN1_POS 4 |
| AnnaBridge | 125:2e9cc70d1897 | 377 | #define MXC_F_GPIO_INT_MODE_PIN1 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN1_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 378 | #define MXC_F_GPIO_INT_MODE_PIN2_POS 8 |
| AnnaBridge | 125:2e9cc70d1897 | 379 | #define MXC_F_GPIO_INT_MODE_PIN2 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN2_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 380 | #define MXC_F_GPIO_INT_MODE_PIN3_POS 12 |
| AnnaBridge | 125:2e9cc70d1897 | 381 | #define MXC_F_GPIO_INT_MODE_PIN3 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN3_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 382 | #define MXC_F_GPIO_INT_MODE_PIN4_POS 16 |
| AnnaBridge | 125:2e9cc70d1897 | 383 | #define MXC_F_GPIO_INT_MODE_PIN4 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN4_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 384 | #define MXC_F_GPIO_INT_MODE_PIN5_POS 20 |
| AnnaBridge | 125:2e9cc70d1897 | 385 | #define MXC_F_GPIO_INT_MODE_PIN5 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN5_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 386 | #define MXC_F_GPIO_INT_MODE_PIN6_POS 24 |
| AnnaBridge | 125:2e9cc70d1897 | 387 | #define MXC_F_GPIO_INT_MODE_PIN6 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN6_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 388 | #define MXC_F_GPIO_INT_MODE_PIN7_POS 28 |
| AnnaBridge | 125:2e9cc70d1897 | 389 | #define MXC_F_GPIO_INT_MODE_PIN7 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN7_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 390 | |
| AnnaBridge | 125:2e9cc70d1897 | 391 | #define MXC_F_GPIO_INTFL_PIN0_POS 0 |
| AnnaBridge | 125:2e9cc70d1897 | 392 | #define MXC_F_GPIO_INTFL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN0_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 393 | #define MXC_F_GPIO_INTFL_PIN1_POS 1 |
| AnnaBridge | 125:2e9cc70d1897 | 394 | #define MXC_F_GPIO_INTFL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN1_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 395 | #define MXC_F_GPIO_INTFL_PIN2_POS 2 |
| AnnaBridge | 125:2e9cc70d1897 | 396 | #define MXC_F_GPIO_INTFL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN2_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 397 | #define MXC_F_GPIO_INTFL_PIN3_POS 3 |
| AnnaBridge | 125:2e9cc70d1897 | 398 | #define MXC_F_GPIO_INTFL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN3_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 399 | #define MXC_F_GPIO_INTFL_PIN4_POS 4 |
| AnnaBridge | 125:2e9cc70d1897 | 400 | #define MXC_F_GPIO_INTFL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN4_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 401 | #define MXC_F_GPIO_INTFL_PIN5_POS 5 |
| AnnaBridge | 125:2e9cc70d1897 | 402 | #define MXC_F_GPIO_INTFL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN5_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 403 | #define MXC_F_GPIO_INTFL_PIN6_POS 6 |
| AnnaBridge | 125:2e9cc70d1897 | 404 | #define MXC_F_GPIO_INTFL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN6_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 405 | #define MXC_F_GPIO_INTFL_PIN7_POS 7 |
| AnnaBridge | 125:2e9cc70d1897 | 406 | #define MXC_F_GPIO_INTFL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN7_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 407 | |
| AnnaBridge | 125:2e9cc70d1897 | 408 | #define MXC_F_GPIO_INTEN_PIN0_POS 0 |
| AnnaBridge | 125:2e9cc70d1897 | 409 | #define MXC_F_GPIO_INTEN_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN0_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 410 | #define MXC_F_GPIO_INTEN_PIN1_POS 1 |
| AnnaBridge | 125:2e9cc70d1897 | 411 | #define MXC_F_GPIO_INTEN_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN1_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 412 | #define MXC_F_GPIO_INTEN_PIN2_POS 2 |
| AnnaBridge | 125:2e9cc70d1897 | 413 | #define MXC_F_GPIO_INTEN_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN2_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 414 | #define MXC_F_GPIO_INTEN_PIN3_POS 3 |
| AnnaBridge | 125:2e9cc70d1897 | 415 | #define MXC_F_GPIO_INTEN_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN3_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 416 | #define MXC_F_GPIO_INTEN_PIN4_POS 4 |
| AnnaBridge | 125:2e9cc70d1897 | 417 | #define MXC_F_GPIO_INTEN_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN4_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 418 | #define MXC_F_GPIO_INTEN_PIN5_POS 5 |
| AnnaBridge | 125:2e9cc70d1897 | 419 | #define MXC_F_GPIO_INTEN_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN5_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 420 | #define MXC_F_GPIO_INTEN_PIN6_POS 6 |
| AnnaBridge | 125:2e9cc70d1897 | 421 | #define MXC_F_GPIO_INTEN_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN6_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 422 | #define MXC_F_GPIO_INTEN_PIN7_POS 7 |
| AnnaBridge | 125:2e9cc70d1897 | 423 | #define MXC_F_GPIO_INTEN_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN7_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 424 | |
| AnnaBridge | 125:2e9cc70d1897 | 425 | |
| AnnaBridge | 125:2e9cc70d1897 | 426 | |
| AnnaBridge | 125:2e9cc70d1897 | 427 | /* |
| AnnaBridge | 125:2e9cc70d1897 | 428 | Field values and shifted values for module GPIO. |
| AnnaBridge | 125:2e9cc70d1897 | 429 | */ |
| AnnaBridge | 125:2e9cc70d1897 | 430 | |
| AnnaBridge | 125:2e9cc70d1897 | 431 | #define MXC_V_GPIO_RST_MODE_DRIVE_0 ((uint32_t)(0x00000000UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 432 | #define MXC_V_GPIO_RST_MODE_WEAK_PULLDOWN ((uint32_t)(0x00000001UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 433 | #define MXC_V_GPIO_RST_MODE_WEAK_PULLUP ((uint32_t)(0x00000002UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 434 | #define MXC_V_GPIO_RST_MODE_DRIVE_1 ((uint32_t)(0x00000003UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 435 | #define MXC_V_GPIO_RST_MODE_HIGH_Z ((uint32_t)(0x00000004UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 436 | |
| AnnaBridge | 125:2e9cc70d1897 | 437 | #define MXC_V_GPIO_FREE_PIN0_NOT_AVAILABLE ((uint32_t)(0x00000000UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 438 | #define MXC_V_GPIO_FREE_PIN0_AVAILABLE ((uint32_t)(0x00000001UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 439 | |
| AnnaBridge | 125:2e9cc70d1897 | 440 | #define MXC_S_GPIO_FREE_PIN0_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN0_AVAILABLE << MXC_F_GPIO_FREE_PIN0_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 441 | |
| AnnaBridge | 125:2e9cc70d1897 | 442 | #define MXC_V_GPIO_FREE_PIN1_NOT_AVAILABLE ((uint32_t)(0x00000000UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 443 | #define MXC_V_GPIO_FREE_PIN1_AVAILABLE ((uint32_t)(0x00000001UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 444 | |
| AnnaBridge | 125:2e9cc70d1897 | 445 | #define MXC_S_GPIO_FREE_PIN1_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN1_AVAILABLE << MXC_F_GPIO_FREE_PIN1_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 446 | |
| AnnaBridge | 125:2e9cc70d1897 | 447 | #define MXC_V_GPIO_FREE_PIN2_NOT_AVAILABLE ((uint32_t)(0x00000000UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 448 | #define MXC_V_GPIO_FREE_PIN2_AVAILABLE ((uint32_t)(0x00000001UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 449 | |
| AnnaBridge | 125:2e9cc70d1897 | 450 | #define MXC_S_GPIO_FREE_PIN2_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN2_AVAILABLE << MXC_F_GPIO_FREE_PIN2_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 451 | |
| AnnaBridge | 125:2e9cc70d1897 | 452 | #define MXC_V_GPIO_FREE_PIN3_NOT_AVAILABLE ((uint32_t)(0x00000000UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 453 | #define MXC_V_GPIO_FREE_PIN3_AVAILABLE ((uint32_t)(0x00000001UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 454 | |
| AnnaBridge | 125:2e9cc70d1897 | 455 | #define MXC_S_GPIO_FREE_PIN3_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN3_AVAILABLE << MXC_F_GPIO_FREE_PIN3_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 456 | |
| AnnaBridge | 125:2e9cc70d1897 | 457 | #define MXC_V_GPIO_FREE_PIN4_NOT_AVAILABLE ((uint32_t)(0x00000000UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 458 | #define MXC_V_GPIO_FREE_PIN4_AVAILABLE ((uint32_t)(0x00000001UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 459 | |
| AnnaBridge | 125:2e9cc70d1897 | 460 | #define MXC_S_GPIO_FREE_PIN4_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN4_AVAILABLE << MXC_F_GPIO_FREE_PIN4_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 461 | |
| AnnaBridge | 125:2e9cc70d1897 | 462 | #define MXC_V_GPIO_FREE_PIN5_NOT_AVAILABLE ((uint32_t)(0x00000000UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 463 | #define MXC_V_GPIO_FREE_PIN5_AVAILABLE ((uint32_t)(0x00000001UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 464 | |
| AnnaBridge | 125:2e9cc70d1897 | 465 | #define MXC_S_GPIO_FREE_PIN5_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN5_AVAILABLE << MXC_F_GPIO_FREE_PIN5_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 466 | |
| AnnaBridge | 125:2e9cc70d1897 | 467 | #define MXC_V_GPIO_FREE_PIN6_NOT_AVAILABLE ((uint32_t)(0x00000000UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 468 | #define MXC_V_GPIO_FREE_PIN6_AVAILABLE ((uint32_t)(0x00000001UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 469 | |
| AnnaBridge | 125:2e9cc70d1897 | 470 | #define MXC_S_GPIO_FREE_PIN6_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN6_AVAILABLE << MXC_F_GPIO_FREE_PIN6_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 471 | |
| AnnaBridge | 125:2e9cc70d1897 | 472 | #define MXC_V_GPIO_FREE_PIN7_NOT_AVAILABLE ((uint32_t)(0x00000000UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 473 | #define MXC_V_GPIO_FREE_PIN7_AVAILABLE ((uint32_t)(0x00000001UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 474 | |
| AnnaBridge | 125:2e9cc70d1897 | 475 | #define MXC_S_GPIO_FREE_PIN7_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN7_AVAILABLE << MXC_F_GPIO_FREE_PIN7_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 476 | |
| AnnaBridge | 125:2e9cc70d1897 | 477 | #define MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP ((uint32_t)(0x00000000UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 478 | #define MXC_V_GPIO_OUT_MODE_OPEN_DRAIN ((uint32_t)(0x00000001UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 479 | #define MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(0x00000002UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 480 | #define MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z ((uint32_t)(0x00000004UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 481 | #define MXC_V_GPIO_OUT_MODE_NORMAL ((uint32_t)(0x00000005UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 482 | #define MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z ((uint32_t)(0x00000006UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 483 | #define MXC_V_GPIO_OUT_MODE_SLOW_DRIVE ((uint32_t)(0x00000007UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 484 | #define MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z ((uint32_t)(0x00000008UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 485 | #define MXC_V_GPIO_OUT_MODE_FAST_DRIVE ((uint32_t)(0x00000009UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 486 | #define MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLDOWN ((uint32_t)(0x0000000AUL)) |
| AnnaBridge | 125:2e9cc70d1897 | 487 | #define MXC_V_GPIO_OUT_MODE_OPEN_SOURCE ((uint32_t)(0x0000000BUL)) |
| AnnaBridge | 125:2e9cc70d1897 | 488 | #define MXC_V_GPIO_OUT_MODE_OPEN_SOURCE_WEAK_PULLDOWN ((uint32_t)(0x0000000CUL)) |
| AnnaBridge | 125:2e9cc70d1897 | 489 | #define MXC_V_GPIO_OUT_MODE_HIGH_Z_INPUT_DISABLED ((uint32_t)(0x0000000FUL)) |
| AnnaBridge | 125:2e9cc70d1897 | 490 | |
| AnnaBridge | 125:2e9cc70d1897 | 491 | #define MXC_V_GPIO_IN_MODE_NORMAL ((uint32_t)(0x00000000UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 492 | #define MXC_V_GPIO_IN_MODE_INVERTED ((uint32_t)(0x00000001UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 493 | #define MXC_V_GPIO_IN_MODE_ALWAYS_ZERO ((uint32_t)(0x00000002UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 494 | #define MXC_V_GPIO_IN_MODE_ALWAYS_ONE ((uint32_t)(0x00000003UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 495 | |
| AnnaBridge | 125:2e9cc70d1897 | 496 | #define MXC_V_GPIO_IN_MODE_PIN0_NORMAL ((uint32_t)(0x00000000UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 497 | #define MXC_V_GPIO_IN_MODE_PIN0_INVERTED ((uint32_t)(0x00000001UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 498 | #define MXC_V_GPIO_IN_MODE_PIN0_ALWAYS_ZERO ((uint32_t)(0x00000002UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 499 | #define MXC_V_GPIO_IN_MODE_PIN0_ALWAYS_ONE ((uint32_t)(0x00000003UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 500 | |
| AnnaBridge | 125:2e9cc70d1897 | 501 | #define MXC_S_GPIO_IN_MODE_PIN0_ALWAYS_ONE ((uint32_t)(MXC_V_GPIO_IN_MODE_PIN0_ALWAYS_ONE << MXC_F_GPIO_IN_MODE_PIN0_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 502 | |
| AnnaBridge | 125:2e9cc70d1897 | 503 | #define MXC_V_GPIO_IN_MODE_PIN1_NORMAL ((uint32_t)(0x00000000UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 504 | #define MXC_V_GPIO_IN_MODE_PIN1_INVERTED ((uint32_t)(0x00000001UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 505 | #define MXC_V_GPIO_IN_MODE_PIN1_ALWAYS_ZERO ((uint32_t)(0x00000002UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 506 | #define MXC_V_GPIO_IN_MODE_PIN1_ALWAYS_ONE ((uint32_t)(0x00000003UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 507 | |
| AnnaBridge | 125:2e9cc70d1897 | 508 | #define MXC_S_GPIO_IN_MODE_PIN1_ALWAYS_ONE ((uint32_t)(MXC_V_GPIO_IN_MODE_PIN1_ALWAYS_ONE << MXC_F_GPIO_IN_MODE_PIN1_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 509 | |
| AnnaBridge | 125:2e9cc70d1897 | 510 | #define MXC_V_GPIO_IN_MODE_PIN2_NORMAL ((uint32_t)(0x00000000UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 511 | #define MXC_V_GPIO_IN_MODE_PIN2_INVERTED ((uint32_t)(0x00000001UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 512 | #define MXC_V_GPIO_IN_MODE_PIN2_ALWAYS_ZERO ((uint32_t)(0x00000002UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 513 | #define MXC_V_GPIO_IN_MODE_PIN2_ALWAYS_ONE ((uint32_t)(0x00000003UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 514 | |
| AnnaBridge | 125:2e9cc70d1897 | 515 | #define MXC_S_GPIO_IN_MODE_PIN2_ALWAYS_ONE ((uint32_t)(MXC_V_GPIO_IN_MODE_PIN2_ALWAYS_ONE << MXC_F_GPIO_IN_MODE_PIN2_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 516 | |
| AnnaBridge | 125:2e9cc70d1897 | 517 | #define MXC_V_GPIO_IN_MODE_PIN3_NORMAL ((uint32_t)(0x00000000UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 518 | #define MXC_V_GPIO_IN_MODE_PIN3_INVERTED ((uint32_t)(0x00000001UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 519 | #define MXC_V_GPIO_IN_MODE_PIN3_ALWAYS_ZERO ((uint32_t)(0x00000002UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 520 | #define MXC_V_GPIO_IN_MODE_PIN3_ALWAYS_ONE ((uint32_t)(0x00000003UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 521 | |
| AnnaBridge | 125:2e9cc70d1897 | 522 | #define MXC_S_GPIO_IN_MODE_PIN3_ALWAYS_ONE ((uint32_t)(MXC_V_GPIO_IN_MODE_PIN3_ALWAYS_ONE << MXC_F_GPIO_IN_MODE_PIN3_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 523 | |
| AnnaBridge | 125:2e9cc70d1897 | 524 | #define MXC_V_GPIO_IN_MODE_PIN4_NORMAL ((uint32_t)(0x00000000UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 525 | #define MXC_V_GPIO_IN_MODE_PIN4_INVERTED ((uint32_t)(0x00000001UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 526 | #define MXC_V_GPIO_IN_MODE_PIN4_ALWAYS_ZERO ((uint32_t)(0x00000002UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 527 | #define MXC_V_GPIO_IN_MODE_PIN4_ALWAYS_ONE ((uint32_t)(0x00000003UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 528 | |
| AnnaBridge | 125:2e9cc70d1897 | 529 | #define MXC_S_GPIO_IN_MODE_PIN4_ALWAYS_ONE ((uint32_t)(MXC_V_GPIO_IN_MODE_PIN4_ALWAYS_ONE << MXC_F_GPIO_IN_MODE_PIN4_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 530 | |
| AnnaBridge | 125:2e9cc70d1897 | 531 | #define MXC_V_GPIO_IN_MODE_PIN5_NORMAL ((uint32_t)(0x00000000UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 532 | #define MXC_V_GPIO_IN_MODE_PIN5_INVERTED ((uint32_t)(0x00000001UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 533 | #define MXC_V_GPIO_IN_MODE_PIN5_ALWAYS_ZERO ((uint32_t)(0x00000002UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 534 | #define MXC_V_GPIO_IN_MODE_PIN5_ALWAYS_ONE ((uint32_t)(0x00000003UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 535 | |
| AnnaBridge | 125:2e9cc70d1897 | 536 | #define MXC_S_GPIO_IN_MODE_PIN5_ALWAYS_ONE ((uint32_t)(MXC_V_GPIO_IN_MODE_PIN5_ALWAYS_ONE << MXC_F_GPIO_IN_MODE_PIN5_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 537 | |
| AnnaBridge | 125:2e9cc70d1897 | 538 | #define MXC_V_GPIO_IN_MODE_PIN6_NORMAL ((uint32_t)(0x00000000UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 539 | #define MXC_V_GPIO_IN_MODE_PIN6_INVERTED ((uint32_t)(0x00000001UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 540 | #define MXC_V_GPIO_IN_MODE_PIN6_ALWAYS_ZERO ((uint32_t)(0x00000002UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 541 | #define MXC_V_GPIO_IN_MODE_PIN6_ALWAYS_ONE ((uint32_t)(0x00000003UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 542 | |
| AnnaBridge | 125:2e9cc70d1897 | 543 | #define MXC_S_GPIO_IN_MODE_PIN6_ALWAYS_ONE ((uint32_t)(MXC_V_GPIO_IN_MODE_PIN6_ALWAYS_ONE << MXC_F_GPIO_IN_MODE_PIN6_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 544 | |
| AnnaBridge | 125:2e9cc70d1897 | 545 | #define MXC_V_GPIO_IN_MODE_PIN7_NORMAL ((uint32_t)(0x00000000UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 546 | #define MXC_V_GPIO_IN_MODE_PIN7_INVERTED ((uint32_t)(0x00000001UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 547 | #define MXC_V_GPIO_IN_MODE_PIN7_ALWAYS_ZERO ((uint32_t)(0x00000002UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 548 | #define MXC_V_GPIO_IN_MODE_PIN7_ALWAYS_ONE ((uint32_t)(0x00000003UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 549 | |
| AnnaBridge | 125:2e9cc70d1897 | 550 | #define MXC_S_GPIO_IN_MODE_PIN7_ALWAYS_ONE ((uint32_t)(MXC_V_GPIO_IN_MODE_PIN7_ALWAYS_ONE << MXC_F_GPIO_IN_MODE_PIN7_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 551 | |
| AnnaBridge | 125:2e9cc70d1897 | 552 | #define MXC_V_GPIO_INT_MODE_DISABLE ((uint32_t)(0x00000000UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 553 | #define MXC_V_GPIO_INT_MODE_FALLING_EDGE ((uint32_t)(0x00000001UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 554 | #define MXC_V_GPIO_INT_MODE_RISING_EDGE ((uint32_t)(0x00000002UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 555 | #define MXC_V_GPIO_INT_MODE_ANY_EDGE ((uint32_t)(0x00000003UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 556 | #define MXC_V_GPIO_INT_MODE_LOW_LVL ((uint32_t)(0x00000004UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 557 | #define MXC_V_GPIO_INT_MODE_HIGH_LVL ((uint32_t)(0x00000005UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 558 | |
| AnnaBridge | 125:2e9cc70d1897 | 559 | #define MXC_V_GPIO_INT_MODE_PIN0_DISABLE ((uint32_t)(0x00000000UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 560 | #define MXC_V_GPIO_INT_MODE_PIN0_FALLING_EDGE ((uint32_t)(0x00000001UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 561 | #define MXC_V_GPIO_INT_MODE_PIN0_RISING_EDGE ((uint32_t)(0x00000002UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 562 | #define MXC_V_GPIO_INT_MODE_PIN0_ANY_EDGE ((uint32_t)(0x00000003UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 563 | #define MXC_V_GPIO_INT_MODE_PIN0_LOW_LVL ((uint32_t)(0x00000004UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 564 | #define MXC_V_GPIO_INT_MODE_PIN0_HIGH_LVL ((uint32_t)(0x00000005UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 565 | |
| AnnaBridge | 125:2e9cc70d1897 | 566 | #define MXC_S_GPIO_INT_MODE_PIN0_HIGH_LVL ((uint32_t)(MXC_V_GPIO_INT_MODE_PIN0_HIGH_LVL << MXC_F_GPIO_INT_MODE_PIN0_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 567 | |
| AnnaBridge | 125:2e9cc70d1897 | 568 | #define MXC_V_GPIO_INT_MODE_PIN1_DISABLE ((uint32_t)(0x00000000UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 569 | #define MXC_V_GPIO_INT_MODE_PIN1_FALLING_EDGE ((uint32_t)(0x00000001UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 570 | #define MXC_V_GPIO_INT_MODE_PIN1_RISING_EDGE ((uint32_t)(0x00000002UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 571 | #define MXC_V_GPIO_INT_MODE_PIN1_ANY_EDGE ((uint32_t)(0x00000003UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 572 | #define MXC_V_GPIO_INT_MODE_PIN1_LOW_LVL ((uint32_t)(0x00000004UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 573 | #define MXC_V_GPIO_INT_MODE_PIN1_HIGH_LVL ((uint32_t)(0x00000005UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 574 | |
| AnnaBridge | 125:2e9cc70d1897 | 575 | #define MXC_S_GPIO_INT_MODE_PIN1_HIGH_LVL ((uint32_t)(MXC_V_GPIO_INT_MODE_PIN1_HIGH_LVL << MXC_F_GPIO_INT_MODE_PIN1_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 576 | |
| AnnaBridge | 125:2e9cc70d1897 | 577 | #define MXC_V_GPIO_INT_MODE_PIN2_DISABLE ((uint32_t)(0x00000000UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 578 | #define MXC_V_GPIO_INT_MODE_PIN2_FALLING_EDGE ((uint32_t)(0x00000001UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 579 | #define MXC_V_GPIO_INT_MODE_PIN2_RISING_EDGE ((uint32_t)(0x00000002UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 580 | #define MXC_V_GPIO_INT_MODE_PIN2_ANY_EDGE ((uint32_t)(0x00000003UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 581 | #define MXC_V_GPIO_INT_MODE_PIN2_LOW_LVL ((uint32_t)(0x00000004UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 582 | #define MXC_V_GPIO_INT_MODE_PIN2_HIGH_LVL ((uint32_t)(0x00000005UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 583 | |
| AnnaBridge | 125:2e9cc70d1897 | 584 | #define MXC_S_GPIO_INT_MODE_PIN2_HIGH_LVL ((uint32_t)(MXC_V_GPIO_INT_MODE_PIN2_HIGH_LVL << MXC_F_GPIO_INT_MODE_PIN2_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 585 | |
| AnnaBridge | 125:2e9cc70d1897 | 586 | #define MXC_V_GPIO_INT_MODE_PIN3_DISABLE ((uint32_t)(0x00000000UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 587 | #define MXC_V_GPIO_INT_MODE_PIN3_FALLING_EDGE ((uint32_t)(0x00000001UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 588 | #define MXC_V_GPIO_INT_MODE_PIN3_RISING_EDGE ((uint32_t)(0x00000002UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 589 | #define MXC_V_GPIO_INT_MODE_PIN3_ANY_EDGE ((uint32_t)(0x00000003UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 590 | #define MXC_V_GPIO_INT_MODE_PIN3_LOW_LVL ((uint32_t)(0x00000004UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 591 | #define MXC_V_GPIO_INT_MODE_PIN3_HIGH_LVL ((uint32_t)(0x00000005UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 592 | |
| AnnaBridge | 125:2e9cc70d1897 | 593 | #define MXC_S_GPIO_INT_MODE_PIN3_HIGH_LVL ((uint32_t)(MXC_V_GPIO_INT_MODE_PIN3_HIGH_LVL << MXC_F_GPIO_INT_MODE_PIN3_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 594 | |
| AnnaBridge | 125:2e9cc70d1897 | 595 | #define MXC_V_GPIO_INT_MODE_PIN4_DISABLE ((uint32_t)(0x00000000UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 596 | #define MXC_V_GPIO_INT_MODE_PIN4_FALLING_EDGE ((uint32_t)(0x00000001UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 597 | #define MXC_V_GPIO_INT_MODE_PIN4_RISING_EDGE ((uint32_t)(0x00000002UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 598 | #define MXC_V_GPIO_INT_MODE_PIN4_ANY_EDGE ((uint32_t)(0x00000003UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 599 | #define MXC_V_GPIO_INT_MODE_PIN4_LOW_LVL ((uint32_t)(0x00000004UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 600 | #define MXC_V_GPIO_INT_MODE_PIN4_HIGH_LVL ((uint32_t)(0x00000005UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 601 | |
| AnnaBridge | 125:2e9cc70d1897 | 602 | #define MXC_S_GPIO_INT_MODE_PIN4_HIGH_LVL ((uint32_t)(MXC_V_GPIO_INT_MODE_PIN4_HIGH_LVL << MXC_F_GPIO_INT_MODE_PIN4_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 603 | |
| AnnaBridge | 125:2e9cc70d1897 | 604 | #define MXC_V_GPIO_INT_MODE_PIN5_DISABLE ((uint32_t)(0x00000000UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 605 | #define MXC_V_GPIO_INT_MODE_PIN5_FALLING_EDGE ((uint32_t)(0x00000001UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 606 | #define MXC_V_GPIO_INT_MODE_PIN5_RISING_EDGE ((uint32_t)(0x00000002UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 607 | #define MXC_V_GPIO_INT_MODE_PIN5_ANY_EDGE ((uint32_t)(0x00000003UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 608 | #define MXC_V_GPIO_INT_MODE_PIN5_LOW_LVL ((uint32_t)(0x00000004UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 609 | #define MXC_V_GPIO_INT_MODE_PIN5_HIGH_LVL ((uint32_t)(0x00000005UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 610 | |
| AnnaBridge | 125:2e9cc70d1897 | 611 | #define MXC_S_GPIO_INT_MODE_PIN5_HIGH_LVL ((uint32_t)(MXC_V_GPIO_INT_MODE_PIN5_HIGH_LVL << MXC_F_GPIO_INT_MODE_PIN5_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 612 | |
| AnnaBridge | 125:2e9cc70d1897 | 613 | #define MXC_V_GPIO_INT_MODE_PIN6_DISABLE ((uint32_t)(0x00000000UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 614 | #define MXC_V_GPIO_INT_MODE_PIN6_FALLING_EDGE ((uint32_t)(0x00000001UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 615 | #define MXC_V_GPIO_INT_MODE_PIN6_RISING_EDGE ((uint32_t)(0x00000002UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 616 | #define MXC_V_GPIO_INT_MODE_PIN6_ANY_EDGE ((uint32_t)(0x00000003UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 617 | #define MXC_V_GPIO_INT_MODE_PIN6_LOW_LVL ((uint32_t)(0x00000004UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 618 | #define MXC_V_GPIO_INT_MODE_PIN6_HIGH_LVL ((uint32_t)(0x00000005UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 619 | |
| AnnaBridge | 125:2e9cc70d1897 | 620 | #define MXC_S_GPIO_INT_MODE_PIN6_HIGH_LVL ((uint32_t)(MXC_V_GPIO_INT_MODE_PIN6_HIGH_LVL << MXC_F_GPIO_INT_MODE_PIN6_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 621 | |
| AnnaBridge | 125:2e9cc70d1897 | 622 | #define MXC_V_GPIO_INT_MODE_PIN7_DISABLE ((uint32_t)(0x00000000UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 623 | #define MXC_V_GPIO_INT_MODE_PIN7_FALLING_EDGE ((uint32_t)(0x00000001UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 624 | #define MXC_V_GPIO_INT_MODE_PIN7_RISING_EDGE ((uint32_t)(0x00000002UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 625 | #define MXC_V_GPIO_INT_MODE_PIN7_ANY_EDGE ((uint32_t)(0x00000003UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 626 | #define MXC_V_GPIO_INT_MODE_PIN7_LOW_LVL ((uint32_t)(0x00000004UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 627 | #define MXC_V_GPIO_INT_MODE_PIN7_HIGH_LVL ((uint32_t)(0x00000005UL)) |
| AnnaBridge | 125:2e9cc70d1897 | 628 | |
| AnnaBridge | 125:2e9cc70d1897 | 629 | #define MXC_S_GPIO_INT_MODE_PIN7_HIGH_LVL ((uint32_t)(MXC_V_GPIO_INT_MODE_PIN7_HIGH_LVL << MXC_F_GPIO_INT_MODE_PIN7_POS)) |
| AnnaBridge | 125:2e9cc70d1897 | 630 | |
| AnnaBridge | 125:2e9cc70d1897 | 631 | |
| AnnaBridge | 125:2e9cc70d1897 | 632 | |
| AnnaBridge | 125:2e9cc70d1897 | 633 | #ifdef __cplusplus |
| AnnaBridge | 125:2e9cc70d1897 | 634 | } |
| AnnaBridge | 125:2e9cc70d1897 | 635 | #endif |
| AnnaBridge | 125:2e9cc70d1897 | 636 | |
| AnnaBridge | 125:2e9cc70d1897 | 637 | #endif /* _MXC_GPIO_REGS_H_ */ |
| AnnaBridge | 125:2e9cc70d1897 | 638 |
