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TARGET_DELTA_DFBM_NQ620/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf51.h@129:0ab6a29f35bf, 2016-11-08 (annotated)

Committer:: <>
Date:: Tue Nov 08 17:28:34 2016 +0000
Revision:: 129:0ab6a29f35bf
Parent:: 128:9bcdf88f62b0

Release 129 of the mbed library

Ports for Upcoming Targets

3011: Add u-blox Sara-N target. https://github.com/ARMmbed/mbed-os/pull/3011

3099: MAX32625 https://github.com/ARMmbed/mbed-os/pull/3099

3151: Add support for FRDM-K82F https://github.com/ARMmbed/mbed-os/pull/3151

3177: New mcu k22512 fixing pr 3136 https://github.com/ARMmbed/mbed-os/pull/3177

Fixes and Changes

3008: NUCLEO_F072RB: Fix wrong timer channel number on pwm PB_5 pin https://github.com/ARMmbed/mbed-os/pull/3008

3013: STM32xx - Change how the ADC internal pins are checked before pinmap_ https://github.com/ARMmbed/mbed-os/pull/3013

3041: [nRF5] - added implementation of API of serial port flow control configuration. https://github.com/ARMmbed/mbed-os/pull/3041

3084: [nrf5] fix in Digital I/O : a gpioe pin was uninitialized badly https://github.com/ARMmbed/mbed-os/pull/3084

3009: TRNG enabled. TRNG APIs implemented. REV A/B/C/D flags removed. Warnings removed https://github.com/ARMmbed/mbed-os/pull/3009

3074: Target stm init gcc alignement https://github.com/ARMmbed/mbed-os/pull/3074

2988: Update of can_api.c fixing #2987 https://github.com/ARMmbed/mbed-os/pull/2988

3173: [Exporters] Add a device_name to microbit entry in targets.json https://github.com/ARMmbed/mbed-os/pull/3173

2969: [nRF52] - switch irq priorities of driver handlers to the lowest level https://github.com/ARMmbed/mbed-os/pull/2969

3184: #3183 Compiler warning in trng_api.c with K64F https://github.com/ARMmbed/mbed-os/pull/3184

3104: [NuMaker] Support CAN and fix PWM CLK error https://github.com/ARMmbed/mbed-os/pull/3104

3186: MultiTech mDot - add back SPI3 pins https://github.com/ARMmbed/mbed-os/pull/3186

3075: nsapi - Add standardized return types for size and errors https://github.com/ARMmbed/mbed-os/pull/3075

3221: u-blox odin w2 drivers update https://github.com/ARMmbed/mbed-os/pull/3221

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	123:b0220dba8be7	1
Kojto	123:b0220dba8be7	2	/**************************************************************************************************//
Kojto	123:b0220dba8be7	3	* @file nrf51.h
Kojto	123:b0220dba8be7	4	*
Kojto	123:b0220dba8be7	5	* @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for
Kojto	123:b0220dba8be7	6	* nrf51 from Nordic Semiconductor.
Kojto	123:b0220dba8be7	7	*
Kojto	123:b0220dba8be7	8	* @version V522
Kojto	123:b0220dba8be7	9	* @date 23. February 2016
Kojto	123:b0220dba8be7	10	*
Kojto	123:b0220dba8be7	11	* @note Generated with SVDConv V2.81d
Kojto	123:b0220dba8be7	12	* from CMSIS SVD File 'nrf51.svd' Version 522,
Kojto	123:b0220dba8be7	13	*
Kojto	123:b0220dba8be7	14	* @par Copyright (c) 2013, Nordic Semiconductor ASA
Kojto	123:b0220dba8be7	15	* All rights reserved.
Kojto	123:b0220dba8be7	16	*
Kojto	123:b0220dba8be7	17	* Redistribution and use in source and binary forms, with or without
Kojto	123:b0220dba8be7	18	* modification, are permitted provided that the following conditions are met:
Kojto	123:b0220dba8be7	19	*
Kojto	123:b0220dba8be7	20	* * Redistributions of source code must retain the above copyright notice, this
Kojto	123:b0220dba8be7	21	* list of conditions and the following disclaimer.
Kojto	123:b0220dba8be7	22	*
Kojto	123:b0220dba8be7	23	* * Redistributions in binary form must reproduce the above copyright notice,
Kojto	123:b0220dba8be7	24	* this list of conditions and the following disclaimer in the documentation
Kojto	123:b0220dba8be7	25	* and/or other materials provided with the distribution.
Kojto	123:b0220dba8be7	26	*
Kojto	123:b0220dba8be7	27	* * Neither the name of Nordic Semiconductor ASA nor the names of its
Kojto	123:b0220dba8be7	28	* contributors may be used to endorse or promote products derived from
Kojto	123:b0220dba8be7	29	* this software without specific prior written permission.
Kojto	123:b0220dba8be7	30	*
Kojto	123:b0220dba8be7	31	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	123:b0220dba8be7	32	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	123:b0220dba8be7	33	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	123:b0220dba8be7	34	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	123:b0220dba8be7	35	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	123:b0220dba8be7	36	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	123:b0220dba8be7	37	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	123:b0220dba8be7	38	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	123:b0220dba8be7	39	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	123:b0220dba8be7	40	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	123:b0220dba8be7	41	*
Kojto	123:b0220dba8be7	42	*
Kojto	123:b0220dba8be7	43	*******************************************************************************************************/
Kojto	123:b0220dba8be7	44
Kojto	123:b0220dba8be7	45
Kojto	123:b0220dba8be7	46
Kojto	123:b0220dba8be7	47	/** @addtogroup Nordic Semiconductor
Kojto	123:b0220dba8be7	48	* @{
Kojto	123:b0220dba8be7	49	*/
Kojto	123:b0220dba8be7	50
Kojto	123:b0220dba8be7	51	/** @addtogroup nrf51
Kojto	123:b0220dba8be7	52	* @{
Kojto	123:b0220dba8be7	53	*/
Kojto	123:b0220dba8be7	54
Kojto	123:b0220dba8be7	55	#ifndef NRF51_H
Kojto	123:b0220dba8be7	56	#define NRF51_H
Kojto	123:b0220dba8be7	57
Kojto	123:b0220dba8be7	58	#ifdef __cplusplus
Kojto	123:b0220dba8be7	59	extern "C" {
Kojto	123:b0220dba8be7	60	#endif
Kojto	123:b0220dba8be7	61
Kojto	123:b0220dba8be7	62
Kojto	123:b0220dba8be7	63	/* ------------------------- Interrupt Number Definition ------------------------ */
Kojto	123:b0220dba8be7	64
Kojto	123:b0220dba8be7	65	typedef enum {
Kojto	123:b0220dba8be7	66	/* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
Kojto	123:b0220dba8be7	67	Reset_IRQn = -15, /!< 1 Reset Vector, invoked on Power up and warm reset /
Kojto	123:b0220dba8be7	68	NonMaskableInt_IRQn = -14, /!< 2 Non maskable Interrupt, cannot be stopped or preempted /
Kojto	123:b0220dba8be7	69	HardFault_IRQn = -13, /!< 3 Hard Fault, all classes of Fault /
Kojto	123:b0220dba8be7	70	SVCall_IRQn = -5, /!< 11 System Service Call via SVC instruction /
Kojto	123:b0220dba8be7	71	DebugMonitor_IRQn = -4, /!< 12 Debug Monitor /
Kojto	123:b0220dba8be7	72	PendSV_IRQn = -2, /!< 14 Pendable request for system service /
Kojto	123:b0220dba8be7	73	SysTick_IRQn = -1, /!< 15 System Tick Timer /
Kojto	123:b0220dba8be7	74	/* ---------------------- nrf51 Specific Interrupt Numbers ---------------------- */
Kojto	123:b0220dba8be7	75	POWER_CLOCK_IRQn = 0, /!< 0 POWER_CLOCK /
Kojto	123:b0220dba8be7	76	RADIO_IRQn = 1, /!< 1 RADIO /
Kojto	123:b0220dba8be7	77	UART0_IRQn = 2, /!< 2 UART0 /
Kojto	123:b0220dba8be7	78	SPI0_TWI0_IRQn = 3, /!< 3 SPI0_TWI0 /
Kojto	123:b0220dba8be7	79	SPI1_TWI1_IRQn = 4, /!< 4 SPI1_TWI1 /
Kojto	123:b0220dba8be7	80	GPIOTE_IRQn = 6, /!< 6 GPIOTE /
Kojto	123:b0220dba8be7	81	ADC_IRQn = 7, /!< 7 ADC /
Kojto	123:b0220dba8be7	82	TIMER0_IRQn = 8, /!< 8 TIMER0 /
Kojto	123:b0220dba8be7	83	TIMER1_IRQn = 9, /!< 9 TIMER1 /
Kojto	123:b0220dba8be7	84	TIMER2_IRQn = 10, /!< 10 TIMER2 /
Kojto	123:b0220dba8be7	85	RTC0_IRQn = 11, /!< 11 RTC0 /
Kojto	123:b0220dba8be7	86	TEMP_IRQn = 12, /!< 12 TEMP /
Kojto	123:b0220dba8be7	87	RNG_IRQn = 13, /!< 13 RNG /
Kojto	123:b0220dba8be7	88	ECB_IRQn = 14, /!< 14 ECB /
Kojto	123:b0220dba8be7	89	CCM_AAR_IRQn = 15, /!< 15 CCM_AAR /
Kojto	123:b0220dba8be7	90	WDT_IRQn = 16, /!< 16 WDT /
Kojto	123:b0220dba8be7	91	RTC1_IRQn = 17, /!< 17 RTC1 /
Kojto	123:b0220dba8be7	92	QDEC_IRQn = 18, /!< 18 QDEC /
Kojto	123:b0220dba8be7	93	LPCOMP_IRQn = 19, /!< 19 LPCOMP /
Kojto	123:b0220dba8be7	94	SWI0_IRQn = 20, /!< 20 SWI0 /
Kojto	123:b0220dba8be7	95	SWI1_IRQn = 21, /!< 21 SWI1 /
Kojto	123:b0220dba8be7	96	SWI2_IRQn = 22, /!< 22 SWI2 /
Kojto	123:b0220dba8be7	97	SWI3_IRQn = 23, /!< 23 SWI3 /
Kojto	123:b0220dba8be7	98	SWI4_IRQn = 24, /!< 24 SWI4 /
Kojto	123:b0220dba8be7	99	SWI5_IRQn = 25 /!< 25 SWI5 /
Kojto	123:b0220dba8be7	100	} IRQn_Type;
Kojto	123:b0220dba8be7	101
Kojto	123:b0220dba8be7	102
Kojto	123:b0220dba8be7	103	/** @addtogroup Configuration_of_CMSIS
Kojto	123:b0220dba8be7	104	* @{
Kojto	123:b0220dba8be7	105	*/
Kojto	123:b0220dba8be7	106
Kojto	123:b0220dba8be7	107
Kojto	123:b0220dba8be7	108	/* ================================================================================ */
Kojto	123:b0220dba8be7	109	/* ================ Processor and Core Peripheral Section ================ */
Kojto	123:b0220dba8be7	110	/* ================================================================================ */
Kojto	123:b0220dba8be7	111
Kojto	123:b0220dba8be7	112	/* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */
Kojto	123:b0220dba8be7	113	#define __CM0_REV 0x0301 /!< Cortex-M0 Core Revision /
Kojto	123:b0220dba8be7	114	#define __MPU_PRESENT 0 /!< MPU present or not /
Kojto	123:b0220dba8be7	115	#define __NVIC_PRIO_BITS 2 /!< Number of Bits used for Priority Levels /
Kojto	123:b0220dba8be7	116	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
Kojto	123:b0220dba8be7	117	/** @} / / End of group Configuration_of_CMSIS */
Kojto	123:b0220dba8be7	118
Kojto	123:b0220dba8be7	119	#include "core_cm0.h" /!< Cortex-M0 processor and core peripherals /
Kojto	123:b0220dba8be7	120	#include "system_nrf51.h" /!< nrf51 System /
Kojto	123:b0220dba8be7	121
Kojto	123:b0220dba8be7	122
Kojto	123:b0220dba8be7	123	/* ================================================================================ */
Kojto	123:b0220dba8be7	124	/* ================ Device Specific Peripheral Section ================ */
Kojto	123:b0220dba8be7	125	/* ================================================================================ */
Kojto	123:b0220dba8be7	126
Kojto	123:b0220dba8be7	127
Kojto	123:b0220dba8be7	128	/** @addtogroup Device_Peripheral_Registers
Kojto	123:b0220dba8be7	129	* @{
Kojto	123:b0220dba8be7	130	*/
Kojto	123:b0220dba8be7	131
Kojto	123:b0220dba8be7	132
Kojto	123:b0220dba8be7	133	/* ------------------- Start of section using anonymous unions ------------------ */
Kojto	123:b0220dba8be7	134	#if defined(__CC_ARM)
Kojto	123:b0220dba8be7	135	#pragma push
Kojto	123:b0220dba8be7	136	#pragma anon_unions
Kojto	123:b0220dba8be7	137	#elif defined(__ICCARM__)
Kojto	123:b0220dba8be7	138	#pragma language=extended
Kojto	123:b0220dba8be7	139	#elif defined(__GNUC__)
Kojto	123:b0220dba8be7	140	/* anonymous unions are enabled by default */
Kojto	123:b0220dba8be7	141	#elif defined(__TMS470__)
Kojto	123:b0220dba8be7	142	/* anonymous unions are enabled by default */
Kojto	123:b0220dba8be7	143	#elif defined(__TASKING__)
Kojto	123:b0220dba8be7	144	#pragma warning 586
Kojto	123:b0220dba8be7	145	#else
Kojto	123:b0220dba8be7	146	#warning Not supported compiler type
Kojto	123:b0220dba8be7	147	#endif
Kojto	123:b0220dba8be7	148
Kojto	123:b0220dba8be7	149
Kojto	123:b0220dba8be7	150	typedef struct {
Kojto	123:b0220dba8be7	151	__IO uint32_t CPU0; /!< Configurable priority configuration register for CPU0. /
Kojto	123:b0220dba8be7	152	__IO uint32_t SPIS1; /!< Configurable priority configuration register for SPIS1. /
Kojto	123:b0220dba8be7	153	__IO uint32_t RADIO; /!< Configurable priority configuration register for RADIO. /
Kojto	123:b0220dba8be7	154	__IO uint32_t ECB; /!< Configurable priority configuration register for ECB. /
Kojto	123:b0220dba8be7	155	__IO uint32_t CCM; /!< Configurable priority configuration register for CCM. /
Kojto	123:b0220dba8be7	156	__IO uint32_t AAR; /!< Configurable priority configuration register for AAR. /
Kojto	123:b0220dba8be7	157	} AMLI_RAMPRI_Type;
Kojto	123:b0220dba8be7	158
Kojto	123:b0220dba8be7	159	typedef struct {
Kojto	123:b0220dba8be7	160	__IO uint32_t SCK; /!< Pin select for SCK. /
Kojto	123:b0220dba8be7	161	__IO uint32_t MOSI; /!< Pin select for MOSI. /
Kojto	123:b0220dba8be7	162	__IO uint32_t MISO; /!< Pin select for MISO. /
Kojto	123:b0220dba8be7	163	} SPIM_PSEL_Type;
Kojto	123:b0220dba8be7	164
Kojto	123:b0220dba8be7	165	typedef struct {
Kojto	123:b0220dba8be7	166	__IO uint32_t PTR; /!< Data pointer. /
Kojto	123:b0220dba8be7	167	__IO uint32_t MAXCNT; /!< Maximum number of buffer bytes to receive. /
Kojto	123:b0220dba8be7	168	__I uint32_t AMOUNT; /!< Number of bytes received in the last transaction. /
Kojto	123:b0220dba8be7	169	} SPIM_RXD_Type;
Kojto	123:b0220dba8be7	170
Kojto	123:b0220dba8be7	171	typedef struct {
Kojto	123:b0220dba8be7	172	__IO uint32_t PTR; /!< Data pointer. /
Kojto	123:b0220dba8be7	173	__IO uint32_t MAXCNT; /!< Maximum number of buffer bytes to send. /
Kojto	123:b0220dba8be7	174	__I uint32_t AMOUNT; /!< Number of bytes sent in the last transaction. /
Kojto	123:b0220dba8be7	175	} SPIM_TXD_Type;
Kojto	123:b0220dba8be7	176
Kojto	123:b0220dba8be7	177	typedef struct {
Kojto	123:b0220dba8be7	178	__O uint32_t EN; /!< Enable channel group. /
Kojto	123:b0220dba8be7	179	__O uint32_t DIS; /!< Disable channel group. /
Kojto	123:b0220dba8be7	180	} PPI_TASKS_CHG_Type;
Kojto	123:b0220dba8be7	181
Kojto	123:b0220dba8be7	182	typedef struct {
Kojto	123:b0220dba8be7	183	__IO uint32_t EEP; /!< Channel event end-point. /
Kojto	123:b0220dba8be7	184	__IO uint32_t TEP; /!< Channel task end-point. /
Kojto	123:b0220dba8be7	185	} PPI_CH_Type;
Kojto	123:b0220dba8be7	186
Kojto	123:b0220dba8be7	187
Kojto	123:b0220dba8be7	188	/* ================================================================================ */
Kojto	123:b0220dba8be7	189	/* ================ POWER ================ */
Kojto	123:b0220dba8be7	190	/* ================================================================================ */
Kojto	123:b0220dba8be7	191
Kojto	123:b0220dba8be7	192
Kojto	123:b0220dba8be7	193	/**
Kojto	123:b0220dba8be7	194	* @brief Power Control. (POWER)
Kojto	123:b0220dba8be7	195	*/
Kojto	123:b0220dba8be7	196
Kojto	123:b0220dba8be7	197	typedef struct { /!< POWER Structure /
Kojto	123:b0220dba8be7	198	__I uint32_t RESERVED0[30];
Kojto	123:b0220dba8be7	199	__O uint32_t TASKS_CONSTLAT; /!< Enable constant latency mode. /
Kojto	123:b0220dba8be7	200	__O uint32_t TASKS_LOWPWR; /!< Enable low power mode (variable latency). /
Kojto	123:b0220dba8be7	201	__I uint32_t RESERVED1[34];
Kojto	123:b0220dba8be7	202	__IO uint32_t EVENTS_POFWARN; /!< Power failure warning. /
Kojto	123:b0220dba8be7	203	__I uint32_t RESERVED2[126];
Kojto	123:b0220dba8be7	204	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
Kojto	123:b0220dba8be7	205	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
Kojto	123:b0220dba8be7	206	__I uint32_t RESERVED3[61];
Kojto	123:b0220dba8be7	207	__IO uint32_t RESETREAS; /!< Reset reason. /
Kojto	123:b0220dba8be7	208	__I uint32_t RESERVED4[9];
Kojto	123:b0220dba8be7	209	__I uint32_t RAMSTATUS; /!< Ram status register. /
Kojto	123:b0220dba8be7	210	__I uint32_t RESERVED5[53];
Kojto	123:b0220dba8be7	211	__O uint32_t SYSTEMOFF; /!< System off register. /
Kojto	123:b0220dba8be7	212	__I uint32_t RESERVED6[3];
Kojto	123:b0220dba8be7	213	__IO uint32_t POFCON; /!< Power failure configuration. /
Kojto	123:b0220dba8be7	214	__I uint32_t RESERVED7[2];
Kojto	123:b0220dba8be7	215	__IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained
Kojto	123:b0220dba8be7	216	register. */
Kojto	123:b0220dba8be7	217	__I uint32_t RESERVED8;
Kojto	123:b0220dba8be7	218	__IO uint32_t RAMON; /!< Ram on/off. /
Kojto	123:b0220dba8be7	219	__I uint32_t RESERVED9[7];
Kojto	123:b0220dba8be7	220	__IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register
Kojto	123:b0220dba8be7	221	is a retained register. */
Kojto	123:b0220dba8be7	222	__I uint32_t RESERVED10[3];
Kojto	123:b0220dba8be7	223	__IO uint32_t RAMONB; /!< Ram on/off. /
Kojto	123:b0220dba8be7	224	__I uint32_t RESERVED11[8];
Kojto	123:b0220dba8be7	225	__IO uint32_t DCDCEN; /!< DCDC converter enable configuration register. /
Kojto	123:b0220dba8be7	226	__I uint32_t RESERVED12[291];
Kojto	123:b0220dba8be7	227	__IO uint32_t DCDCFORCE; /!< DCDC power-up force register. /
Kojto	123:b0220dba8be7	228	} NRF_POWER_Type;
Kojto	123:b0220dba8be7	229
Kojto	123:b0220dba8be7	230
Kojto	123:b0220dba8be7	231	/* ================================================================================ */
Kojto	123:b0220dba8be7	232	/* ================ CLOCK ================ */
Kojto	123:b0220dba8be7	233	/* ================================================================================ */
Kojto	123:b0220dba8be7	234
Kojto	123:b0220dba8be7	235
Kojto	123:b0220dba8be7	236	/**
Kojto	123:b0220dba8be7	237	* @brief Clock control. (CLOCK)
Kojto	123:b0220dba8be7	238	*/
Kojto	123:b0220dba8be7	239
Kojto	123:b0220dba8be7	240	typedef struct { /!< CLOCK Structure /
Kojto	123:b0220dba8be7	241	__O uint32_t TASKS_HFCLKSTART; /!< Start HFCLK clock source. /
Kojto	123:b0220dba8be7	242	__O uint32_t TASKS_HFCLKSTOP; /!< Stop HFCLK clock source. /
Kojto	123:b0220dba8be7	243	__O uint32_t TASKS_LFCLKSTART; /!< Start LFCLK clock source. /
Kojto	123:b0220dba8be7	244	__O uint32_t TASKS_LFCLKSTOP; /!< Stop LFCLK clock source. /
Kojto	123:b0220dba8be7	245	__O uint32_t TASKS_CAL; /!< Start calibration of LFCLK RC oscillator. /
Kojto	123:b0220dba8be7	246	__O uint32_t TASKS_CTSTART; /!< Start calibration timer. /
Kojto	123:b0220dba8be7	247	__O uint32_t TASKS_CTSTOP; /!< Stop calibration timer. /
Kojto	123:b0220dba8be7	248	__I uint32_t RESERVED0[57];
Kojto	123:b0220dba8be7	249	__IO uint32_t EVENTS_HFCLKSTARTED; /!< HFCLK oscillator started. /
Kojto	123:b0220dba8be7	250	__IO uint32_t EVENTS_LFCLKSTARTED; /!< LFCLK oscillator started. /
Kojto	123:b0220dba8be7	251	__I uint32_t RESERVED1;
Kojto	123:b0220dba8be7	252	__IO uint32_t EVENTS_DONE; /!< Calibration of LFCLK RC oscillator completed. /
Kojto	123:b0220dba8be7	253	__IO uint32_t EVENTS_CTTO; /!< Calibration timer timeout. /
Kojto	123:b0220dba8be7	254	__I uint32_t RESERVED2[124];
Kojto	123:b0220dba8be7	255	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
Kojto	123:b0220dba8be7	256	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
Kojto	123:b0220dba8be7	257	__I uint32_t RESERVED3[63];
Kojto	123:b0220dba8be7	258	__I uint32_t HFCLKRUN; /!< Task HFCLKSTART trigger status. /
Kojto	123:b0220dba8be7	259	__I uint32_t HFCLKSTAT; /!< High frequency clock status. /
Kojto	123:b0220dba8be7	260	__I uint32_t RESERVED4;
Kojto	123:b0220dba8be7	261	__I uint32_t LFCLKRUN; /!< Task LFCLKSTART triggered status. /
Kojto	123:b0220dba8be7	262	__I uint32_t LFCLKSTAT; /!< Low frequency clock status. /
Kojto	123:b0220dba8be7	263	__I uint32_t LFCLKSRCCOPY; /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is
Kojto	123:b0220dba8be7	264	triggered. */
Kojto	123:b0220dba8be7	265	__I uint32_t RESERVED5[62];
Kojto	123:b0220dba8be7	266	__IO uint32_t LFCLKSRC; /!< Clock source for the LFCLK clock. /
Kojto	123:b0220dba8be7	267	__I uint32_t RESERVED6[7];
Kojto	123:b0220dba8be7	268	__IO uint32_t CTIV; /!< Calibration timer interval. /
Kojto	123:b0220dba8be7	269	__I uint32_t RESERVED7[5];
Kojto	123:b0220dba8be7	270	__IO uint32_t XTALFREQ; /!< Crystal frequency. /
Kojto	123:b0220dba8be7	271	} NRF_CLOCK_Type;
Kojto	123:b0220dba8be7	272
Kojto	123:b0220dba8be7	273
Kojto	123:b0220dba8be7	274	/* ================================================================================ */
Kojto	123:b0220dba8be7	275	/* ================ MPU ================ */
Kojto	123:b0220dba8be7	276	/* ================================================================================ */
Kojto	123:b0220dba8be7	277
Kojto	123:b0220dba8be7	278
Kojto	123:b0220dba8be7	279	/**
Kojto	123:b0220dba8be7	280	* @brief Memory Protection Unit. (MPU)
Kojto	123:b0220dba8be7	281	*/
Kojto	123:b0220dba8be7	282
Kojto	123:b0220dba8be7	283	typedef struct { /!< MPU Structure /
Kojto	123:b0220dba8be7	284	__I uint32_t RESERVED0[330];
Kojto	123:b0220dba8be7	285	__IO uint32_t PERR0; /!< Configuration of peripherals in mpu regions. /
Kojto	123:b0220dba8be7	286	__IO uint32_t RLENR0; /!< Length of RAM region 0. /
Kojto	123:b0220dba8be7	287	__I uint32_t RESERVED1[52];
Kojto	123:b0220dba8be7	288	__IO uint32_t PROTENSET0; /!< Erase and write protection bit enable set register. /
Kojto	123:b0220dba8be7	289	__IO uint32_t PROTENSET1; /!< Erase and write protection bit enable set register. /
Kojto	123:b0220dba8be7	290	__IO uint32_t DISABLEINDEBUG; /!< Disable erase and write protection mechanism in debug mode. /
Kojto	123:b0220dba8be7	291	__IO uint32_t PROTBLOCKSIZE; /!< Erase and write protection block size. /
Kojto	123:b0220dba8be7	292	} NRF_MPU_Type;
Kojto	123:b0220dba8be7	293
Kojto	123:b0220dba8be7	294
Kojto	123:b0220dba8be7	295	/* ================================================================================ */
Kojto	123:b0220dba8be7	296	/* ================ AMLI ================ */
Kojto	123:b0220dba8be7	297	/* ================================================================================ */
Kojto	123:b0220dba8be7	298
Kojto	123:b0220dba8be7	299
Kojto	123:b0220dba8be7	300	/**
Kojto	123:b0220dba8be7	301	* @brief AHB Multi-Layer Interface. (AMLI)
Kojto	123:b0220dba8be7	302	*/
Kojto	123:b0220dba8be7	303
Kojto	123:b0220dba8be7	304	typedef struct { /!< AMLI Structure /
Kojto	123:b0220dba8be7	305	__I uint32_t RESERVED0[896];
Kojto	123:b0220dba8be7	306	AMLI_RAMPRI_Type RAMPRI; /!< RAM configurable priority configuration structure. /
Kojto	123:b0220dba8be7	307	} NRF_AMLI_Type;
Kojto	123:b0220dba8be7	308
Kojto	123:b0220dba8be7	309
Kojto	123:b0220dba8be7	310	/* ================================================================================ */
Kojto	123:b0220dba8be7	311	/* ================ RADIO ================ */
Kojto	123:b0220dba8be7	312	/* ================================================================================ */
Kojto	123:b0220dba8be7	313
Kojto	123:b0220dba8be7	314
Kojto	123:b0220dba8be7	315	/**
Kojto	123:b0220dba8be7	316	* @brief The radio. (RADIO)
Kojto	123:b0220dba8be7	317	*/
Kojto	123:b0220dba8be7	318
Kojto	123:b0220dba8be7	319	typedef struct { /!< RADIO Structure /
Kojto	123:b0220dba8be7	320	__O uint32_t TASKS_TXEN; /!< Enable radio in TX mode. /
Kojto	123:b0220dba8be7	321	__O uint32_t TASKS_RXEN; /!< Enable radio in RX mode. /
Kojto	123:b0220dba8be7	322	__O uint32_t TASKS_START; /!< Start radio. /
Kojto	123:b0220dba8be7	323	__O uint32_t TASKS_STOP; /!< Stop radio. /
Kojto	123:b0220dba8be7	324	__O uint32_t TASKS_DISABLE; /!< Disable radio. /
Kojto	123:b0220dba8be7	325	__O uint32_t TASKS_RSSISTART; /!< Start the RSSI and take one sample of the receive signal strength. /
Kojto	123:b0220dba8be7	326	__O uint32_t TASKS_RSSISTOP; /!< Stop the RSSI measurement. /
Kojto	123:b0220dba8be7	327	__O uint32_t TASKS_BCSTART; /!< Start the bit counter. /
Kojto	123:b0220dba8be7	328	__O uint32_t TASKS_BCSTOP; /!< Stop the bit counter. /
Kojto	123:b0220dba8be7	329	__I uint32_t RESERVED0[55];
Kojto	123:b0220dba8be7	330	__IO uint32_t EVENTS_READY; /!< Ready event. /
Kojto	123:b0220dba8be7	331	__IO uint32_t EVENTS_ADDRESS; /!< Address event. /
Kojto	123:b0220dba8be7	332	__IO uint32_t EVENTS_PAYLOAD; /!< Payload event. /
Kojto	123:b0220dba8be7	333	__IO uint32_t EVENTS_END; /!< End event. /
Kojto	123:b0220dba8be7	334	__IO uint32_t EVENTS_DISABLED; /!< Disable event. /
Kojto	123:b0220dba8be7	335	__IO uint32_t EVENTS_DEVMATCH; /!< A device address match occurred on the last received packet. /
Kojto	123:b0220dba8be7	336	__IO uint32_t EVENTS_DEVMISS; /!< No device address match occurred on the last received packet. /
Kojto	123:b0220dba8be7	337	__IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI
Kojto	123:b0220dba8be7	338	sample is ready for readout at the RSSISAMPLE register. */
Kojto	123:b0220dba8be7	339	__I uint32_t RESERVED1[2];
Kojto	123:b0220dba8be7	340	__IO uint32_t EVENTS_BCMATCH; /!< Bit counter reached bit count value specified in BCC register. /
Kojto	123:b0220dba8be7	341	__I uint32_t RESERVED2[53];
Kojto	123:b0220dba8be7	342	__IO uint32_t SHORTS; /!< Shortcuts for the radio. /
Kojto	123:b0220dba8be7	343	__I uint32_t RESERVED3[64];
Kojto	123:b0220dba8be7	344	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
Kojto	123:b0220dba8be7	345	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
Kojto	123:b0220dba8be7	346	__I uint32_t RESERVED4[61];
Kojto	123:b0220dba8be7	347	__I uint32_t CRCSTATUS; /!< CRC status of received packet. /
Kojto	123:b0220dba8be7	348	__I uint32_t RESERVED5;
Kojto	123:b0220dba8be7	349	__I uint32_t RXMATCH; /!< Received address. /
Kojto	123:b0220dba8be7	350	__I uint32_t RXCRC; /!< Received CRC. /
Kojto	123:b0220dba8be7	351	__I uint32_t DAI; /!< Device address match index. /
Kojto	123:b0220dba8be7	352	__I uint32_t RESERVED6[60];
Kojto	123:b0220dba8be7	353	__IO uint32_t PACKETPTR; /!< Packet pointer. Decision point: START task. /
Kojto	123:b0220dba8be7	354	__IO uint32_t FREQUENCY; /!< Frequency. /
Kojto	123:b0220dba8be7	355	__IO uint32_t TXPOWER; /!< Output power. /
Kojto	123:b0220dba8be7	356	__IO uint32_t MODE; /!< Data rate and modulation. /
Kojto	123:b0220dba8be7	357	__IO uint32_t PCNF0; /!< Packet configuration 0. /
Kojto	123:b0220dba8be7	358	__IO uint32_t PCNF1; /!< Packet configuration 1. /
Kojto	123:b0220dba8be7	359	__IO uint32_t BASE0; /!< Radio base address 0. Decision point: START task. /
Kojto	123:b0220dba8be7	360	__IO uint32_t BASE1; /!< Radio base address 1. Decision point: START task. /
Kojto	123:b0220dba8be7	361	__IO uint32_t PREFIX0; /!< Prefixes bytes for logical addresses 0 to 3. /
Kojto	123:b0220dba8be7	362	__IO uint32_t PREFIX1; /!< Prefixes bytes for logical addresses 4 to 7. /
Kojto	123:b0220dba8be7	363	__IO uint32_t TXADDRESS; /!< Transmit address select. /
Kojto	123:b0220dba8be7	364	__IO uint32_t RXADDRESSES; /!< Receive address select. /
Kojto	123:b0220dba8be7	365	__IO uint32_t CRCCNF; /!< CRC configuration. /
Kojto	123:b0220dba8be7	366	__IO uint32_t CRCPOLY; /!< CRC polynomial. /
Kojto	123:b0220dba8be7	367	__IO uint32_t CRCINIT; /!< CRC initial value. /
Kojto	123:b0220dba8be7	368	__IO uint32_t TEST; /!< Test features enable register. /
Kojto	123:b0220dba8be7	369	__IO uint32_t TIFS; /!< Inter Frame Spacing in microseconds. /
Kojto	123:b0220dba8be7	370	__I uint32_t RSSISAMPLE; /!< RSSI sample. /
Kojto	123:b0220dba8be7	371	__I uint32_t RESERVED7;
Kojto	123:b0220dba8be7	372	__I uint32_t STATE; /!< Current radio state. /
Kojto	123:b0220dba8be7	373	__IO uint32_t DATAWHITEIV; /!< Data whitening initial value. /
Kojto	123:b0220dba8be7	374	__I uint32_t RESERVED8[2];
Kojto	123:b0220dba8be7	375	__IO uint32_t BCC; /!< Bit counter compare. /
Kojto	123:b0220dba8be7	376	__I uint32_t RESERVED9[39];
Kojto	123:b0220dba8be7	377	__IO uint32_t DAB[8]; /!< Device address base segment. /
Kojto	123:b0220dba8be7	378	__IO uint32_t DAP[8]; /!< Device address prefix. /
Kojto	123:b0220dba8be7	379	__IO uint32_t DACNF; /!< Device address match configuration. /
Kojto	123:b0220dba8be7	380	__I uint32_t RESERVED10[56];
Kojto	123:b0220dba8be7	381	__IO uint32_t OVERRIDE0; /!< Trim value override register 0. /
Kojto	123:b0220dba8be7	382	__IO uint32_t OVERRIDE1; /!< Trim value override register 1. /
Kojto	123:b0220dba8be7	383	__IO uint32_t OVERRIDE2; /!< Trim value override register 2. /
Kojto	123:b0220dba8be7	384	__IO uint32_t OVERRIDE3; /!< Trim value override register 3. /
Kojto	123:b0220dba8be7	385	__IO uint32_t OVERRIDE4; /!< Trim value override register 4. /
Kojto	123:b0220dba8be7	386	__I uint32_t RESERVED11[561];
Kojto	123:b0220dba8be7	387	__IO uint32_t POWER; /!< Peripheral power control. /
Kojto	123:b0220dba8be7	388	} NRF_RADIO_Type;
Kojto	123:b0220dba8be7	389
Kojto	123:b0220dba8be7	390
Kojto	123:b0220dba8be7	391	/* ================================================================================ */
Kojto	123:b0220dba8be7	392	/* ================ UART ================ */
Kojto	123:b0220dba8be7	393	/* ================================================================================ */
Kojto	123:b0220dba8be7	394
Kojto	123:b0220dba8be7	395
Kojto	123:b0220dba8be7	396	/**
Kojto	123:b0220dba8be7	397	* @brief Universal Asynchronous Receiver/Transmitter. (UART)
Kojto	123:b0220dba8be7	398	*/
Kojto	123:b0220dba8be7	399
Kojto	123:b0220dba8be7	400	typedef struct { /!< UART Structure /
Kojto	123:b0220dba8be7	401	__O uint32_t TASKS_STARTRX; /!< Start UART receiver. /
Kojto	123:b0220dba8be7	402	__O uint32_t TASKS_STOPRX; /!< Stop UART receiver. /
Kojto	123:b0220dba8be7	403	__O uint32_t TASKS_STARTTX; /!< Start UART transmitter. /
Kojto	123:b0220dba8be7	404	__O uint32_t TASKS_STOPTX; /!< Stop UART transmitter. /
Kojto	123:b0220dba8be7	405	__I uint32_t RESERVED0[3];
Kojto	123:b0220dba8be7	406	__O uint32_t TASKS_SUSPEND; /!< Suspend UART. /
Kojto	123:b0220dba8be7	407	__I uint32_t RESERVED1[56];
Kojto	123:b0220dba8be7	408	__IO uint32_t EVENTS_CTS; /!< CTS activated. /
Kojto	123:b0220dba8be7	409	__IO uint32_t EVENTS_NCTS; /!< CTS deactivated. /
Kojto	123:b0220dba8be7	410	__IO uint32_t EVENTS_RXDRDY; /!< Data received in RXD. /
Kojto	123:b0220dba8be7	411	__I uint32_t RESERVED2[4];
Kojto	123:b0220dba8be7	412	__IO uint32_t EVENTS_TXDRDY; /!< Data sent from TXD. /
Kojto	123:b0220dba8be7	413	__I uint32_t RESERVED3;
Kojto	123:b0220dba8be7	414	__IO uint32_t EVENTS_ERROR; /!< Error detected. /
Kojto	123:b0220dba8be7	415	__I uint32_t RESERVED4[7];
Kojto	123:b0220dba8be7	416	__IO uint32_t EVENTS_RXTO; /!< Receiver timeout. /
Kojto	123:b0220dba8be7	417	__I uint32_t RESERVED5[46];
Kojto	123:b0220dba8be7	418	__IO uint32_t SHORTS; /!< Shortcuts for UART. /
Kojto	123:b0220dba8be7	419	__I uint32_t RESERVED6[64];
Kojto	123:b0220dba8be7	420	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
Kojto	123:b0220dba8be7	421	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
Kojto	123:b0220dba8be7	422	__I uint32_t RESERVED7[93];
Kojto	123:b0220dba8be7	423	__IO uint32_t ERRORSRC; /!< Error source. Write error field to 1 to clear error. /
Kojto	123:b0220dba8be7	424	__I uint32_t RESERVED8[31];
Kojto	123:b0220dba8be7	425	__IO uint32_t ENABLE; /!< Enable UART and acquire IOs. /
Kojto	123:b0220dba8be7	426	__I uint32_t RESERVED9;
Kojto	123:b0220dba8be7	427	__IO uint32_t PSELRTS; /!< Pin select for RTS. /
Kojto	123:b0220dba8be7	428	__IO uint32_t PSELTXD; /!< Pin select for TXD. /
Kojto	123:b0220dba8be7	429	__IO uint32_t PSELCTS; /!< Pin select for CTS. /
Kojto	123:b0220dba8be7	430	__IO uint32_t PSELRXD; /!< Pin select for RXD. /
Kojto	123:b0220dba8be7	431	__I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced.
Kojto	123:b0220dba8be7	432	Once read the character is consumed. If read when no character
Kojto	123:b0220dba8be7	433	available, the UART will stop working. */
Kojto	123:b0220dba8be7	434	__O uint32_t TXD; /!< TXD register. /
Kojto	123:b0220dba8be7	435	__I uint32_t RESERVED10;
Kojto	123:b0220dba8be7	436	__IO uint32_t BAUDRATE; /!< UART Baudrate. /
Kojto	123:b0220dba8be7	437	__I uint32_t RESERVED11[17];
Kojto	123:b0220dba8be7	438	__IO uint32_t CONFIG; /!< Configuration of parity and hardware flow control register. /
Kojto	123:b0220dba8be7	439	__I uint32_t RESERVED12[675];
Kojto	123:b0220dba8be7	440	__IO uint32_t POWER; /!< Peripheral power control. /
Kojto	123:b0220dba8be7	441	} NRF_UART_Type;
Kojto	123:b0220dba8be7	442
Kojto	123:b0220dba8be7	443
Kojto	123:b0220dba8be7	444	/* ================================================================================ */
Kojto	123:b0220dba8be7	445	/* ================ SPI ================ */
Kojto	123:b0220dba8be7	446	/* ================================================================================ */
Kojto	123:b0220dba8be7	447
Kojto	123:b0220dba8be7	448
Kojto	123:b0220dba8be7	449	/**
Kojto	123:b0220dba8be7	450	* @brief SPI master 0. (SPI)
Kojto	123:b0220dba8be7	451	*/
Kojto	123:b0220dba8be7	452
Kojto	123:b0220dba8be7	453	typedef struct { /!< SPI Structure /
Kojto	123:b0220dba8be7	454	__I uint32_t RESERVED0[66];
Kojto	123:b0220dba8be7	455	__IO uint32_t EVENTS_READY; /!< TXD byte sent and RXD byte received. /
Kojto	123:b0220dba8be7	456	__I uint32_t RESERVED1[126];
Kojto	123:b0220dba8be7	457	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
Kojto	123:b0220dba8be7	458	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
Kojto	123:b0220dba8be7	459	__I uint32_t RESERVED2[125];
Kojto	123:b0220dba8be7	460	__IO uint32_t ENABLE; /!< Enable SPI. /
Kojto	123:b0220dba8be7	461	__I uint32_t RESERVED3;
Kojto	123:b0220dba8be7	462	__IO uint32_t PSELSCK; /!< Pin select for SCK. /
Kojto	123:b0220dba8be7	463	__IO uint32_t PSELMOSI; /!< Pin select for MOSI. /
Kojto	123:b0220dba8be7	464	__IO uint32_t PSELMISO; /!< Pin select for MISO. /
Kojto	123:b0220dba8be7	465	__I uint32_t RESERVED4;
Kojto	123:b0220dba8be7	466	__I uint32_t RXD; /!< RX data. /
Kojto	123:b0220dba8be7	467	__IO uint32_t TXD; /!< TX data. /
Kojto	123:b0220dba8be7	468	__I uint32_t RESERVED5;
Kojto	123:b0220dba8be7	469	__IO uint32_t FREQUENCY; /!< SPI frequency /
Kojto	123:b0220dba8be7	470	__I uint32_t RESERVED6[11];
Kojto	123:b0220dba8be7	471	__IO uint32_t CONFIG; /!< Configuration register. /
Kojto	123:b0220dba8be7	472	__I uint32_t RESERVED7[681];
Kojto	123:b0220dba8be7	473	__IO uint32_t POWER; /!< Peripheral power control. /
Kojto	123:b0220dba8be7	474	} NRF_SPI_Type;
Kojto	123:b0220dba8be7	475
Kojto	123:b0220dba8be7	476
Kojto	123:b0220dba8be7	477	/* ================================================================================ */
Kojto	123:b0220dba8be7	478	/* ================ TWI ================ */
Kojto	123:b0220dba8be7	479	/* ================================================================================ */
Kojto	123:b0220dba8be7	480
Kojto	123:b0220dba8be7	481
Kojto	123:b0220dba8be7	482	/**
Kojto	123:b0220dba8be7	483	* @brief Two-wire interface master 0. (TWI)
Kojto	123:b0220dba8be7	484	*/
Kojto	123:b0220dba8be7	485
Kojto	123:b0220dba8be7	486	typedef struct { /!< TWI Structure /
Kojto	123:b0220dba8be7	487	__O uint32_t TASKS_STARTRX; /!< Start 2-Wire master receive sequence. /
Kojto	123:b0220dba8be7	488	__I uint32_t RESERVED0;
Kojto	123:b0220dba8be7	489	__O uint32_t TASKS_STARTTX; /!< Start 2-Wire master transmit sequence. /
Kojto	123:b0220dba8be7	490	__I uint32_t RESERVED1[2];
Kojto	123:b0220dba8be7	491	__O uint32_t TASKS_STOP; /!< Stop 2-Wire transaction. /
Kojto	123:b0220dba8be7	492	__I uint32_t RESERVED2;
Kojto	123:b0220dba8be7	493	__O uint32_t TASKS_SUSPEND; /!< Suspend 2-Wire transaction. /
Kojto	123:b0220dba8be7	494	__O uint32_t TASKS_RESUME; /!< Resume 2-Wire transaction. /
Kojto	123:b0220dba8be7	495	__I uint32_t RESERVED3[56];
Kojto	123:b0220dba8be7	496	__IO uint32_t EVENTS_STOPPED; /!< Two-wire stopped. /
Kojto	123:b0220dba8be7	497	__IO uint32_t EVENTS_RXDREADY; /!< Two-wire ready to deliver new RXD byte received. /
Kojto	123:b0220dba8be7	498	__I uint32_t RESERVED4[4];
Kojto	123:b0220dba8be7	499	__IO uint32_t EVENTS_TXDSENT; /!< Two-wire finished sending last TXD byte. /
Kojto	123:b0220dba8be7	500	__I uint32_t RESERVED5;
Kojto	123:b0220dba8be7	501	__IO uint32_t EVENTS_ERROR; /!< Two-wire error detected. /
Kojto	123:b0220dba8be7	502	__I uint32_t RESERVED6[4];
Kojto	123:b0220dba8be7	503	__IO uint32_t EVENTS_BB; /!< Two-wire byte boundary. /
Kojto	123:b0220dba8be7	504	__I uint32_t RESERVED7[3];
Kojto	123:b0220dba8be7	505	__IO uint32_t EVENTS_SUSPENDED; /!< Two-wire suspended. /
Kojto	123:b0220dba8be7	506	__I uint32_t RESERVED8[45];
Kojto	123:b0220dba8be7	507	__IO uint32_t SHORTS; /!< Shortcuts for TWI. /
Kojto	123:b0220dba8be7	508	__I uint32_t RESERVED9[64];
Kojto	123:b0220dba8be7	509	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
Kojto	123:b0220dba8be7	510	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
Kojto	123:b0220dba8be7	511	__I uint32_t RESERVED10[110];
Kojto	123:b0220dba8be7	512	__IO uint32_t ERRORSRC; /!< Two-wire error source. Write error field to 1 to clear error. /
Kojto	123:b0220dba8be7	513	__I uint32_t RESERVED11[14];
Kojto	123:b0220dba8be7	514	__IO uint32_t ENABLE; /!< Enable two-wire master. /
Kojto	123:b0220dba8be7	515	__I uint32_t RESERVED12;
Kojto	123:b0220dba8be7	516	__IO uint32_t PSELSCL; /!< Pin select for SCL. /
Kojto	123:b0220dba8be7	517	__IO uint32_t PSELSDA; /!< Pin select for SDA. /
Kojto	123:b0220dba8be7	518	__I uint32_t RESERVED13[2];
Kojto	123:b0220dba8be7	519	__I uint32_t RXD; /!< RX data register. /
Kojto	123:b0220dba8be7	520	__IO uint32_t TXD; /!< TX data register. /
Kojto	123:b0220dba8be7	521	__I uint32_t RESERVED14;
Kojto	123:b0220dba8be7	522	__IO uint32_t FREQUENCY; /!< Two-wire frequency. /
Kojto	123:b0220dba8be7	523	__I uint32_t RESERVED15[24];
Kojto	123:b0220dba8be7	524	__IO uint32_t ADDRESS; /!< Address used in the two-wire transfer. /
Kojto	123:b0220dba8be7	525	__I uint32_t RESERVED16[668];
Kojto	123:b0220dba8be7	526	__IO uint32_t POWER; /!< Peripheral power control. /
Kojto	123:b0220dba8be7	527	} NRF_TWI_Type;
Kojto	123:b0220dba8be7	528
Kojto	123:b0220dba8be7	529
Kojto	123:b0220dba8be7	530	/* ================================================================================ */
Kojto	123:b0220dba8be7	531	/* ================ SPIS ================ */
Kojto	123:b0220dba8be7	532	/* ================================================================================ */
Kojto	123:b0220dba8be7	533
Kojto	123:b0220dba8be7	534
Kojto	123:b0220dba8be7	535	/**
Kojto	123:b0220dba8be7	536	* @brief SPI slave 1. (SPIS)
Kojto	123:b0220dba8be7	537	*/
Kojto	123:b0220dba8be7	538
Kojto	123:b0220dba8be7	539	typedef struct { /!< SPIS Structure /
Kojto	123:b0220dba8be7	540	__I uint32_t RESERVED0[9];
Kojto	123:b0220dba8be7	541	__O uint32_t TASKS_ACQUIRE; /!< Acquire SPI semaphore. /
Kojto	123:b0220dba8be7	542	__O uint32_t TASKS_RELEASE; /!< Release SPI semaphore. /
Kojto	123:b0220dba8be7	543	__I uint32_t RESERVED1[54];
Kojto	123:b0220dba8be7	544	__IO uint32_t EVENTS_END; /!< Granted transaction completed. /
Kojto	123:b0220dba8be7	545	__I uint32_t RESERVED2[2];
Kojto	123:b0220dba8be7	546	__IO uint32_t EVENTS_ENDRX; /!< End of RXD buffer reached /
Kojto	123:b0220dba8be7	547	__I uint32_t RESERVED3[5];
Kojto	123:b0220dba8be7	548	__IO uint32_t EVENTS_ACQUIRED; /!< Semaphore acquired. /
Kojto	123:b0220dba8be7	549	__I uint32_t RESERVED4[53];
Kojto	123:b0220dba8be7	550	__IO uint32_t SHORTS; /!< Shortcuts for SPIS. /
Kojto	123:b0220dba8be7	551	__I uint32_t RESERVED5[64];
Kojto	123:b0220dba8be7	552	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
Kojto	123:b0220dba8be7	553	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
Kojto	123:b0220dba8be7	554	__I uint32_t RESERVED6[61];
Kojto	123:b0220dba8be7	555	__I uint32_t SEMSTAT; /!< Semaphore status. /
Kojto	123:b0220dba8be7	556	__I uint32_t RESERVED7[15];
Kojto	123:b0220dba8be7	557	__IO uint32_t STATUS; /!< Status from last transaction. /
Kojto	123:b0220dba8be7	558	__I uint32_t RESERVED8[47];
Kojto	123:b0220dba8be7	559	__IO uint32_t ENABLE; /!< Enable SPIS. /
Kojto	123:b0220dba8be7	560	__I uint32_t RESERVED9;
Kojto	123:b0220dba8be7	561	__IO uint32_t PSELSCK; /!< Pin select for SCK. /
Kojto	123:b0220dba8be7	562	__IO uint32_t PSELMISO; /!< Pin select for MISO. /
Kojto	123:b0220dba8be7	563	__IO uint32_t PSELMOSI; /!< Pin select for MOSI. /
Kojto	123:b0220dba8be7	564	__IO uint32_t PSELCSN; /!< Pin select for CSN. /
Kojto	123:b0220dba8be7	565	__I uint32_t RESERVED10[7];
Kojto	123:b0220dba8be7	566	__IO uint32_t RXDPTR; /!< RX data pointer. /
Kojto	123:b0220dba8be7	567	__IO uint32_t MAXRX; /!< Maximum number of bytes in the receive buffer. /
Kojto	123:b0220dba8be7	568	__I uint32_t AMOUNTRX; /!< Number of bytes received in last granted transaction. /
Kojto	123:b0220dba8be7	569	__I uint32_t RESERVED11;
Kojto	123:b0220dba8be7	570	__IO uint32_t TXDPTR; /!< TX data pointer. /
Kojto	123:b0220dba8be7	571	__IO uint32_t MAXTX; /!< Maximum number of bytes in the transmit buffer. /
Kojto	123:b0220dba8be7	572	__I uint32_t AMOUNTTX; /!< Number of bytes transmitted in last granted transaction. /
Kojto	123:b0220dba8be7	573	__I uint32_t RESERVED12;
Kojto	123:b0220dba8be7	574	__IO uint32_t CONFIG; /!< Configuration register. /
Kojto	123:b0220dba8be7	575	__I uint32_t RESERVED13;
Kojto	123:b0220dba8be7	576	__IO uint32_t DEF; /!< Default character. /
Kojto	123:b0220dba8be7	577	__I uint32_t RESERVED14[24];
Kojto	123:b0220dba8be7	578	__IO uint32_t ORC; /!< Over-read character. /
Kojto	123:b0220dba8be7	579	__I uint32_t RESERVED15[654];
Kojto	123:b0220dba8be7	580	__IO uint32_t POWER; /!< Peripheral power control. /
Kojto	123:b0220dba8be7	581	} NRF_SPIS_Type;
Kojto	123:b0220dba8be7	582
Kojto	123:b0220dba8be7	583
Kojto	123:b0220dba8be7	584	/* ================================================================================ */
Kojto	123:b0220dba8be7	585	/* ================ SPIM ================ */
Kojto	123:b0220dba8be7	586	/* ================================================================================ */
Kojto	123:b0220dba8be7	587
Kojto	123:b0220dba8be7	588
Kojto	123:b0220dba8be7	589	/**
Kojto	123:b0220dba8be7	590	* @brief SPI master with easyDMA 1. (SPIM)
Kojto	123:b0220dba8be7	591	*/
Kojto	123:b0220dba8be7	592
Kojto	123:b0220dba8be7	593	typedef struct { /!< SPIM Structure /
Kojto	123:b0220dba8be7	594	__I uint32_t RESERVED0[4];
Kojto	123:b0220dba8be7	595	__O uint32_t TASKS_START; /!< Start SPI transaction. /
Kojto	123:b0220dba8be7	596	__O uint32_t TASKS_STOP; /!< Stop SPI transaction. /
Kojto	123:b0220dba8be7	597	__I uint32_t RESERVED1;
Kojto	123:b0220dba8be7	598	__O uint32_t TASKS_SUSPEND; /!< Suspend SPI transaction. /
Kojto	123:b0220dba8be7	599	__O uint32_t TASKS_RESUME; /!< Resume SPI transaction. /
Kojto	123:b0220dba8be7	600	__I uint32_t RESERVED2[56];
Kojto	123:b0220dba8be7	601	__IO uint32_t EVENTS_STOPPED; /!< SPI transaction has stopped. /
Kojto	123:b0220dba8be7	602	__I uint32_t RESERVED3[2];
Kojto	123:b0220dba8be7	603	__IO uint32_t EVENTS_ENDRX; /!< End of RXD buffer reached. /
Kojto	123:b0220dba8be7	604	__I uint32_t RESERVED4[3];
Kojto	123:b0220dba8be7	605	__IO uint32_t EVENTS_ENDTX; /!< End of TXD buffer reached. /
Kojto	123:b0220dba8be7	606	__I uint32_t RESERVED5[10];
Kojto	123:b0220dba8be7	607	__IO uint32_t EVENTS_STARTED; /!< Transaction started. /
Kojto	123:b0220dba8be7	608	__I uint32_t RESERVED6[109];
Kojto	123:b0220dba8be7	609	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
Kojto	123:b0220dba8be7	610	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
Kojto	123:b0220dba8be7	611	__I uint32_t RESERVED7[125];
Kojto	123:b0220dba8be7	612	__IO uint32_t ENABLE; /!< Enable SPIM. /
Kojto	123:b0220dba8be7	613	__I uint32_t RESERVED8;
Kojto	123:b0220dba8be7	614	SPIM_PSEL_Type PSEL; /!< Pin select configuration. /
Kojto	123:b0220dba8be7	615	__I uint32_t RESERVED9[4];
Kojto	123:b0220dba8be7	616	__IO uint32_t FREQUENCY; /!< SPI frequency. /
Kojto	123:b0220dba8be7	617	__I uint32_t RESERVED10[3];
Kojto	123:b0220dba8be7	618	SPIM_RXD_Type RXD; /!< RXD EasyDMA configuration and status. /
Kojto	123:b0220dba8be7	619	__I uint32_t RESERVED11;
Kojto	123:b0220dba8be7	620	SPIM_TXD_Type TXD; /!< TXD EasyDMA configuration and status. /
Kojto	123:b0220dba8be7	621	__I uint32_t RESERVED12;
Kojto	123:b0220dba8be7	622	__IO uint32_t CONFIG; /!< Configuration register. /
Kojto	123:b0220dba8be7	623	__I uint32_t RESERVED13[26];
Kojto	123:b0220dba8be7	624	__IO uint32_t ORC; /!< Over-read character. /
Kojto	123:b0220dba8be7	625	__I uint32_t RESERVED14[654];
Kojto	123:b0220dba8be7	626	__IO uint32_t POWER; /!< Peripheral power control. /
Kojto	123:b0220dba8be7	627	} NRF_SPIM_Type;
Kojto	123:b0220dba8be7	628
Kojto	123:b0220dba8be7	629
Kojto	123:b0220dba8be7	630	/* ================================================================================ */
Kojto	123:b0220dba8be7	631	/* ================ GPIOTE ================ */
Kojto	123:b0220dba8be7	632	/* ================================================================================ */
Kojto	123:b0220dba8be7	633
Kojto	123:b0220dba8be7	634
Kojto	123:b0220dba8be7	635	/**
Kojto	123:b0220dba8be7	636	* @brief GPIO tasks and events. (GPIOTE)
Kojto	123:b0220dba8be7	637	*/
Kojto	123:b0220dba8be7	638
Kojto	123:b0220dba8be7	639	typedef struct { /!< GPIOTE Structure /
Kojto	123:b0220dba8be7	640	__O uint32_t TASKS_OUT[4]; /!< Tasks asssociated with GPIOTE channels. /
Kojto	123:b0220dba8be7	641	__I uint32_t RESERVED0[60];
Kojto	123:b0220dba8be7	642	__IO uint32_t EVENTS_IN[4]; /!< Tasks asssociated with GPIOTE channels. /
Kojto	123:b0220dba8be7	643	__I uint32_t RESERVED1[27];
Kojto	123:b0220dba8be7	644	__IO uint32_t EVENTS_PORT; /!< Event generated from multiple pins. /
Kojto	123:b0220dba8be7	645	__I uint32_t RESERVED2[97];
Kojto	123:b0220dba8be7	646	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
Kojto	123:b0220dba8be7	647	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
Kojto	123:b0220dba8be7	648	__I uint32_t RESERVED3[129];
Kojto	123:b0220dba8be7	649	__IO uint32_t CONFIG[4]; /!< Channel configuration registers. /
Kojto	123:b0220dba8be7	650	__I uint32_t RESERVED4[695];
Kojto	123:b0220dba8be7	651	__IO uint32_t POWER; /!< Peripheral power control. /
Kojto	123:b0220dba8be7	652	} NRF_GPIOTE_Type;
Kojto	123:b0220dba8be7	653
Kojto	123:b0220dba8be7	654
Kojto	123:b0220dba8be7	655	/* ================================================================================ */
Kojto	123:b0220dba8be7	656	/* ================ ADC ================ */
Kojto	123:b0220dba8be7	657	/* ================================================================================ */
Kojto	123:b0220dba8be7	658
Kojto	123:b0220dba8be7	659
Kojto	123:b0220dba8be7	660	/**
Kojto	123:b0220dba8be7	661	* @brief Analog to digital converter. (ADC)
Kojto	123:b0220dba8be7	662	*/
Kojto	123:b0220dba8be7	663
Kojto	123:b0220dba8be7	664	typedef struct { /!< ADC Structure /
Kojto	123:b0220dba8be7	665	__O uint32_t TASKS_START; /!< Start an ADC conversion. /
Kojto	123:b0220dba8be7	666	__O uint32_t TASKS_STOP; /!< Stop ADC. /
Kojto	123:b0220dba8be7	667	__I uint32_t RESERVED0[62];
Kojto	123:b0220dba8be7	668	__IO uint32_t EVENTS_END; /!< ADC conversion complete. /
Kojto	123:b0220dba8be7	669	__I uint32_t RESERVED1[128];
Kojto	123:b0220dba8be7	670	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
Kojto	123:b0220dba8be7	671	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
Kojto	123:b0220dba8be7	672	__I uint32_t RESERVED2[61];
Kojto	123:b0220dba8be7	673	__I uint32_t BUSY; /!< ADC busy register. /
Kojto	123:b0220dba8be7	674	__I uint32_t RESERVED3[63];
Kojto	123:b0220dba8be7	675	__IO uint32_t ENABLE; /!< ADC enable. /
Kojto	123:b0220dba8be7	676	__IO uint32_t CONFIG; /!< ADC configuration register. /
Kojto	123:b0220dba8be7	677	__I uint32_t RESULT; /!< Result of ADC conversion. /
Kojto	123:b0220dba8be7	678	__I uint32_t RESERVED4[700];
Kojto	123:b0220dba8be7	679	__IO uint32_t POWER; /!< Peripheral power control. /
Kojto	123:b0220dba8be7	680	} NRF_ADC_Type;
Kojto	123:b0220dba8be7	681
Kojto	123:b0220dba8be7	682
Kojto	123:b0220dba8be7	683	/* ================================================================================ */
Kojto	123:b0220dba8be7	684	/* ================ TIMER ================ */
Kojto	123:b0220dba8be7	685	/* ================================================================================ */
Kojto	123:b0220dba8be7	686
Kojto	123:b0220dba8be7	687
Kojto	123:b0220dba8be7	688	/**
Kojto	123:b0220dba8be7	689	* @brief Timer 0. (TIMER)
Kojto	123:b0220dba8be7	690	*/
Kojto	123:b0220dba8be7	691
Kojto	123:b0220dba8be7	692	typedef struct { /!< TIMER Structure /
Kojto	123:b0220dba8be7	693	__O uint32_t TASKS_START; /!< Start Timer. /
Kojto	123:b0220dba8be7	694	__O uint32_t TASKS_STOP; /!< Stop Timer. /
Kojto	123:b0220dba8be7	695	__O uint32_t TASKS_COUNT; /!< Increment Timer (In counter mode). /
Kojto	123:b0220dba8be7	696	__O uint32_t TASKS_CLEAR; /!< Clear timer. /
Kojto	123:b0220dba8be7	697	__O uint32_t TASKS_SHUTDOWN; /!< Shutdown timer. /
Kojto	123:b0220dba8be7	698	__I uint32_t RESERVED0[11];
Kojto	123:b0220dba8be7	699	__O uint32_t TASKS_CAPTURE[4]; /!< Capture Timer value to CC[n] registers. /
Kojto	123:b0220dba8be7	700	__I uint32_t RESERVED1[60];
Kojto	123:b0220dba8be7	701	__IO uint32_t EVENTS_COMPARE[4]; /!< Compare event on CC[n] match. /
Kojto	123:b0220dba8be7	702	__I uint32_t RESERVED2[44];
Kojto	123:b0220dba8be7	703	__IO uint32_t SHORTS; /!< Shortcuts for Timer. /
Kojto	123:b0220dba8be7	704	__I uint32_t RESERVED3[64];
Kojto	123:b0220dba8be7	705	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
Kojto	123:b0220dba8be7	706	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
Kojto	123:b0220dba8be7	707	__I uint32_t RESERVED4[126];
Kojto	123:b0220dba8be7	708	__IO uint32_t MODE; /!< Timer Mode selection. /
Kojto	123:b0220dba8be7	709	__IO uint32_t BITMODE; /!< Sets timer behaviour. /
Kojto	123:b0220dba8be7	710	__I uint32_t RESERVED5;
Kojto	123:b0220dba8be7	711	__IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source
Kojto	123:b0220dba8be7	712	clock frequency is divided by 2^SCALE. */
Kojto	123:b0220dba8be7	713	__I uint32_t RESERVED6[11];
Kojto	123:b0220dba8be7	714	__IO uint32_t CC[4]; /!< Capture/compare registers. /
Kojto	123:b0220dba8be7	715	__I uint32_t RESERVED7[683];
Kojto	123:b0220dba8be7	716	__IO uint32_t POWER; /!< Peripheral power control. /
Kojto	123:b0220dba8be7	717	} NRF_TIMER_Type;
Kojto	123:b0220dba8be7	718
Kojto	123:b0220dba8be7	719
Kojto	123:b0220dba8be7	720	/* ================================================================================ */
Kojto	123:b0220dba8be7	721	/* ================ RTC ================ */
Kojto	123:b0220dba8be7	722	/* ================================================================================ */
Kojto	123:b0220dba8be7	723
Kojto	123:b0220dba8be7	724
Kojto	123:b0220dba8be7	725	/**
Kojto	123:b0220dba8be7	726	* @brief Real time counter 0. (RTC)
Kojto	123:b0220dba8be7	727	*/
Kojto	123:b0220dba8be7	728
Kojto	123:b0220dba8be7	729	typedef struct { /!< RTC Structure /
Kojto	123:b0220dba8be7	730	__O uint32_t TASKS_START; /!< Start RTC Counter. /
Kojto	123:b0220dba8be7	731	__O uint32_t TASKS_STOP; /!< Stop RTC Counter. /
Kojto	123:b0220dba8be7	732	__O uint32_t TASKS_CLEAR; /!< Clear RTC Counter. /
Kojto	123:b0220dba8be7	733	__O uint32_t TASKS_TRIGOVRFLW; /!< Set COUNTER to 0xFFFFFFF0. /
Kojto	123:b0220dba8be7	734	__I uint32_t RESERVED0[60];
Kojto	123:b0220dba8be7	735	__IO uint32_t EVENTS_TICK; /!< Event on COUNTER increment. /
Kojto	123:b0220dba8be7	736	__IO uint32_t EVENTS_OVRFLW; /!< Event on COUNTER overflow. /
Kojto	123:b0220dba8be7	737	__I uint32_t RESERVED1[14];
Kojto	123:b0220dba8be7	738	__IO uint32_t EVENTS_COMPARE[4]; /!< Compare event on CC[n] match. /
Kojto	123:b0220dba8be7	739	__I uint32_t RESERVED2[109];
Kojto	123:b0220dba8be7	740	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
Kojto	123:b0220dba8be7	741	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
Kojto	123:b0220dba8be7	742	__I uint32_t RESERVED3[13];
Kojto	123:b0220dba8be7	743	__IO uint32_t EVTEN; /!< Configures event enable routing to PPI for each RTC event. /
Kojto	123:b0220dba8be7	744	__IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives
Kojto	123:b0220dba8be7	745	the value of EVTEN. */
Kojto	123:b0220dba8be7	746	__IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register
Kojto	123:b0220dba8be7	747	gives the value of EVTEN. */
Kojto	123:b0220dba8be7	748	__I uint32_t RESERVED4[110];
Kojto	123:b0220dba8be7	749	__I uint32_t COUNTER; /!< Current COUNTER value. /
Kojto	123:b0220dba8be7	750	__IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
Kojto	123:b0220dba8be7	751	Must be written when RTC is STOPed. */
Kojto	123:b0220dba8be7	752	__I uint32_t RESERVED5[13];
Kojto	123:b0220dba8be7	753	__IO uint32_t CC[4]; /!< Capture/compare registers. /
Kojto	123:b0220dba8be7	754	__I uint32_t RESERVED6[683];
Kojto	123:b0220dba8be7	755	__IO uint32_t POWER; /!< Peripheral power control. /
Kojto	123:b0220dba8be7	756	} NRF_RTC_Type;
Kojto	123:b0220dba8be7	757
Kojto	123:b0220dba8be7	758
Kojto	123:b0220dba8be7	759	/* ================================================================================ */
Kojto	123:b0220dba8be7	760	/* ================ TEMP ================ */
Kojto	123:b0220dba8be7	761	/* ================================================================================ */
Kojto	123:b0220dba8be7	762
Kojto	123:b0220dba8be7	763
Kojto	123:b0220dba8be7	764	/**
Kojto	123:b0220dba8be7	765	* @brief Temperature Sensor. (TEMP)
Kojto	123:b0220dba8be7	766	*/
Kojto	123:b0220dba8be7	767
Kojto	123:b0220dba8be7	768	typedef struct { /!< TEMP Structure /
Kojto	123:b0220dba8be7	769	__O uint32_t TASKS_START; /!< Start temperature measurement. /
Kojto	123:b0220dba8be7	770	__O uint32_t TASKS_STOP; /!< Stop temperature measurement. /
Kojto	123:b0220dba8be7	771	__I uint32_t RESERVED0[62];
Kojto	123:b0220dba8be7	772	__IO uint32_t EVENTS_DATARDY; /!< Temperature measurement complete, data ready event. /
Kojto	123:b0220dba8be7	773	__I uint32_t RESERVED1[128];
Kojto	123:b0220dba8be7	774	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
Kojto	123:b0220dba8be7	775	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
Kojto	123:b0220dba8be7	776	__I uint32_t RESERVED2[127];
Kojto	123:b0220dba8be7	777	__I int32_t TEMP; /!< Die temperature in degC, 2's complement format, 0.25 degC pecision. /
Kojto	123:b0220dba8be7	778	__I uint32_t RESERVED3[700];
Kojto	123:b0220dba8be7	779	__IO uint32_t POWER; /!< Peripheral power control. /
Kojto	123:b0220dba8be7	780	} NRF_TEMP_Type;
Kojto	123:b0220dba8be7	781
Kojto	123:b0220dba8be7	782
Kojto	123:b0220dba8be7	783	/* ================================================================================ */
Kojto	123:b0220dba8be7	784	/* ================ RNG ================ */
Kojto	123:b0220dba8be7	785	/* ================================================================================ */
Kojto	123:b0220dba8be7	786
Kojto	123:b0220dba8be7	787
Kojto	123:b0220dba8be7	788	/**
Kojto	123:b0220dba8be7	789	* @brief Random Number Generator. (RNG)
Kojto	123:b0220dba8be7	790	*/
Kojto	123:b0220dba8be7	791
Kojto	123:b0220dba8be7	792	typedef struct { /!< RNG Structure /
Kojto	123:b0220dba8be7	793	__O uint32_t TASKS_START; /!< Start the random number generator. /
Kojto	123:b0220dba8be7	794	__O uint32_t TASKS_STOP; /!< Stop the random number generator. /
Kojto	123:b0220dba8be7	795	__I uint32_t RESERVED0[62];
Kojto	123:b0220dba8be7	796	__IO uint32_t EVENTS_VALRDY; /!< New random number generated and written to VALUE register. /
Kojto	123:b0220dba8be7	797	__I uint32_t RESERVED1[63];
Kojto	123:b0220dba8be7	798	__IO uint32_t SHORTS; /!< Shortcuts for the RNG. /
Kojto	123:b0220dba8be7	799	__I uint32_t RESERVED2[64];
Kojto	123:b0220dba8be7	800	__IO uint32_t INTENSET; /!< Interrupt enable set register /
Kojto	123:b0220dba8be7	801	__IO uint32_t INTENCLR; /!< Interrupt enable clear register /
Kojto	123:b0220dba8be7	802	__I uint32_t RESERVED3[126];
Kojto	123:b0220dba8be7	803	__IO uint32_t CONFIG; /!< Configuration register. /
Kojto	123:b0220dba8be7	804	__I uint32_t VALUE; /!< RNG random number. /
Kojto	123:b0220dba8be7	805	__I uint32_t RESERVED4[700];
Kojto	123:b0220dba8be7	806	__IO uint32_t POWER; /!< Peripheral power control. /
Kojto	123:b0220dba8be7	807	} NRF_RNG_Type;
Kojto	123:b0220dba8be7	808
Kojto	123:b0220dba8be7	809
Kojto	123:b0220dba8be7	810	/* ================================================================================ */
Kojto	123:b0220dba8be7	811	/* ================ ECB ================ */
Kojto	123:b0220dba8be7	812	/* ================================================================================ */
Kojto	123:b0220dba8be7	813
Kojto	123:b0220dba8be7	814
Kojto	123:b0220dba8be7	815	/**
Kojto	123:b0220dba8be7	816	* @brief AES ECB Mode Encryption. (ECB)
Kojto	123:b0220dba8be7	817	*/
Kojto	123:b0220dba8be7	818
Kojto	123:b0220dba8be7	819	typedef struct { /!< ECB Structure /
Kojto	123:b0220dba8be7	820	__O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this
Kojto	123:b0220dba8be7	821	will not initiate a new encryption and the ERRORECB event will
Kojto	123:b0220dba8be7	822	be triggered. */
Kojto	123:b0220dba8be7	823	__O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running,
Kojto	123:b0220dba8be7	824	this will will trigger the ERRORECB event. */
Kojto	123:b0220dba8be7	825	__I uint32_t RESERVED0[62];
Kojto	123:b0220dba8be7	826	__IO uint32_t EVENTS_ENDECB; /!< ECB block encrypt complete. /
Kojto	123:b0220dba8be7	827	__IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an
Kojto	123:b0220dba8be7	828	error. */
Kojto	123:b0220dba8be7	829	__I uint32_t RESERVED1[127];
Kojto	123:b0220dba8be7	830	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
Kojto	123:b0220dba8be7	831	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
Kojto	123:b0220dba8be7	832	__I uint32_t RESERVED2[126];
Kojto	123:b0220dba8be7	833	__IO uint32_t ECBDATAPTR; /!< ECB block encrypt memory pointer. /
Kojto	123:b0220dba8be7	834	__I uint32_t RESERVED3[701];
Kojto	123:b0220dba8be7	835	__IO uint32_t POWER; /!< Peripheral power control. /
Kojto	123:b0220dba8be7	836	} NRF_ECB_Type;
Kojto	123:b0220dba8be7	837
Kojto	123:b0220dba8be7	838
Kojto	123:b0220dba8be7	839	/* ================================================================================ */
Kojto	123:b0220dba8be7	840	/* ================ AAR ================ */
Kojto	123:b0220dba8be7	841	/* ================================================================================ */
Kojto	123:b0220dba8be7	842
Kojto	123:b0220dba8be7	843
Kojto	123:b0220dba8be7	844	/**
Kojto	123:b0220dba8be7	845	* @brief Accelerated Address Resolver. (AAR)
Kojto	123:b0220dba8be7	846	*/
Kojto	123:b0220dba8be7	847
Kojto	123:b0220dba8be7	848	typedef struct { /!< AAR Structure /
Kojto	123:b0220dba8be7	849	__O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK
Kojto	123:b0220dba8be7	850	data structure. */
Kojto	123:b0220dba8be7	851	__I uint32_t RESERVED0;
Kojto	123:b0220dba8be7	852	__O uint32_t TASKS_STOP; /!< Stop resolving addresses. /
Kojto	123:b0220dba8be7	853	__I uint32_t RESERVED1[61];
Kojto	123:b0220dba8be7	854	__IO uint32_t EVENTS_END; /!< Address resolution procedure completed. /
Kojto	123:b0220dba8be7	855	__IO uint32_t EVENTS_RESOLVED; /!< Address resolved. /
Kojto	123:b0220dba8be7	856	__IO uint32_t EVENTS_NOTRESOLVED; /!< Address not resolved. /
Kojto	123:b0220dba8be7	857	__I uint32_t RESERVED2[126];
Kojto	123:b0220dba8be7	858	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
Kojto	123:b0220dba8be7	859	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
Kojto	123:b0220dba8be7	860	__I uint32_t RESERVED3[61];
Kojto	123:b0220dba8be7	861	__I uint32_t STATUS; /!< Resolution status. /
Kojto	123:b0220dba8be7	862	__I uint32_t RESERVED4[63];
Kojto	123:b0220dba8be7	863	__IO uint32_t ENABLE; /!< Enable AAR. /
Kojto	123:b0220dba8be7	864	__IO uint32_t NIRK; /!< Number of Identity root Keys in the IRK data structure. /
Kojto	123:b0220dba8be7	865	__IO uint32_t IRKPTR; /!< Pointer to the IRK data structure. /
Kojto	123:b0220dba8be7	866	__I uint32_t RESERVED5;
Kojto	123:b0220dba8be7	867	__IO uint32_t ADDRPTR; /!< Pointer to the resolvable address (6 bytes). /
Kojto	123:b0220dba8be7	868	__IO uint32_t SCRATCHPTR; /*!< Pointer to a scratch data area used for temporary storage during
Kojto	123:b0220dba8be7	869	resolution. A minimum of 3 bytes must be reserved. */
Kojto	123:b0220dba8be7	870	__I uint32_t RESERVED6[697];
Kojto	123:b0220dba8be7	871	__IO uint32_t POWER; /!< Peripheral power control. /
Kojto	123:b0220dba8be7	872	} NRF_AAR_Type;
Kojto	123:b0220dba8be7	873
Kojto	123:b0220dba8be7	874
Kojto	123:b0220dba8be7	875	/* ================================================================================ */
Kojto	123:b0220dba8be7	876	/* ================ CCM ================ */
Kojto	123:b0220dba8be7	877	/* ================================================================================ */
Kojto	123:b0220dba8be7	878
Kojto	123:b0220dba8be7	879
Kojto	123:b0220dba8be7	880	/**
Kojto	123:b0220dba8be7	881	* @brief AES CCM Mode Encryption. (CCM)
Kojto	123:b0220dba8be7	882	*/
Kojto	123:b0220dba8be7	883
Kojto	123:b0220dba8be7	884	typedef struct { /!< CCM Structure /
Kojto	123:b0220dba8be7	885	__O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by
Kojto	123:b0220dba8be7	886	itself when completed. */
Kojto	123:b0220dba8be7	887	__O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when
Kojto	123:b0220dba8be7	888	completed. */
Kojto	123:b0220dba8be7	889	__O uint32_t TASKS_STOP; /!< Stop encrypt/decrypt. /
Kojto	123:b0220dba8be7	890	__I uint32_t RESERVED0[61];
Kojto	123:b0220dba8be7	891	__IO uint32_t EVENTS_ENDKSGEN; /!< Keystream generation completed. /
Kojto	123:b0220dba8be7	892	__IO uint32_t EVENTS_ENDCRYPT; /!< Encrypt/decrypt completed. /
Kojto	123:b0220dba8be7	893	__IO uint32_t EVENTS_ERROR; /!< Error happened. /
Kojto	123:b0220dba8be7	894	__I uint32_t RESERVED1[61];
Kojto	123:b0220dba8be7	895	__IO uint32_t SHORTS; /!< Shortcuts for the CCM. /
Kojto	123:b0220dba8be7	896	__I uint32_t RESERVED2[64];
Kojto	123:b0220dba8be7	897	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
Kojto	123:b0220dba8be7	898	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
Kojto	123:b0220dba8be7	899	__I uint32_t RESERVED3[61];
Kojto	123:b0220dba8be7	900	__I uint32_t MICSTATUS; /!< CCM RX MIC check result. /
Kojto	123:b0220dba8be7	901	__I uint32_t RESERVED4[63];
Kojto	123:b0220dba8be7	902	__IO uint32_t ENABLE; /!< CCM enable. /
Kojto	123:b0220dba8be7	903	__IO uint32_t MODE; /!< Operation mode. /
Kojto	123:b0220dba8be7	904	__IO uint32_t CNFPTR; /!< Pointer to a data structure holding AES key and NONCE vector. /
Kojto	123:b0220dba8be7	905	__IO uint32_t INPTR; /!< Pointer to the input packet. /
Kojto	123:b0220dba8be7	906	__IO uint32_t OUTPTR; /!< Pointer to the output packet. /
Kojto	123:b0220dba8be7	907	__IO uint32_t SCRATCHPTR; /*!< Pointer to a scratch data area used for temporary storage during
Kojto	123:b0220dba8be7	908	resolution. A minimum of 43 bytes must be reserved. */
Kojto	123:b0220dba8be7	909	__I uint32_t RESERVED5[697];
Kojto	123:b0220dba8be7	910	__IO uint32_t POWER; /!< Peripheral power control. /
Kojto	123:b0220dba8be7	911	} NRF_CCM_Type;
Kojto	123:b0220dba8be7	912
Kojto	123:b0220dba8be7	913
Kojto	123:b0220dba8be7	914	/* ================================================================================ */
Kojto	123:b0220dba8be7	915	/* ================ WDT ================ */
Kojto	123:b0220dba8be7	916	/* ================================================================================ */
Kojto	123:b0220dba8be7	917
Kojto	123:b0220dba8be7	918
Kojto	123:b0220dba8be7	919	/**
Kojto	123:b0220dba8be7	920	* @brief Watchdog Timer. (WDT)
Kojto	123:b0220dba8be7	921	*/
Kojto	123:b0220dba8be7	922
Kojto	123:b0220dba8be7	923	typedef struct { /!< WDT Structure /
Kojto	123:b0220dba8be7	924	__O uint32_t TASKS_START; /!< Start the watchdog. /
Kojto	123:b0220dba8be7	925	__I uint32_t RESERVED0[63];
Kojto	123:b0220dba8be7	926	__IO uint32_t EVENTS_TIMEOUT; /!< Watchdog timeout. /
Kojto	123:b0220dba8be7	927	__I uint32_t RESERVED1[128];
Kojto	123:b0220dba8be7	928	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
Kojto	123:b0220dba8be7	929	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
Kojto	123:b0220dba8be7	930	__I uint32_t RESERVED2[61];
Kojto	123:b0220dba8be7	931	__I uint32_t RUNSTATUS; /!< Watchdog running status. /
Kojto	123:b0220dba8be7	932	__I uint32_t REQSTATUS; /!< Request status. /
Kojto	123:b0220dba8be7	933	__I uint32_t RESERVED3[63];
Kojto	123:b0220dba8be7	934	__IO uint32_t CRV; /!< Counter reload value in number of 32kiHz clock cycles. /
Kojto	123:b0220dba8be7	935	__IO uint32_t RREN; /!< Reload request enable. /
Kojto	123:b0220dba8be7	936	__IO uint32_t CONFIG; /!< Configuration register. /
Kojto	123:b0220dba8be7	937	__I uint32_t RESERVED4[60];
Kojto	123:b0220dba8be7	938	__O uint32_t RR[8]; /!< Reload requests registers. /
Kojto	123:b0220dba8be7	939	__I uint32_t RESERVED5[631];
Kojto	123:b0220dba8be7	940	__IO uint32_t POWER; /!< Peripheral power control. /
Kojto	123:b0220dba8be7	941	} NRF_WDT_Type;
Kojto	123:b0220dba8be7	942
Kojto	123:b0220dba8be7	943
Kojto	123:b0220dba8be7	944	/* ================================================================================ */
Kojto	123:b0220dba8be7	945	/* ================ QDEC ================ */
Kojto	123:b0220dba8be7	946	/* ================================================================================ */
Kojto	123:b0220dba8be7	947
Kojto	123:b0220dba8be7	948
Kojto	123:b0220dba8be7	949	/**
Kojto	123:b0220dba8be7	950	* @brief Rotary decoder. (QDEC)
Kojto	123:b0220dba8be7	951	*/
Kojto	123:b0220dba8be7	952
Kojto	123:b0220dba8be7	953	typedef struct { /!< QDEC Structure /
Kojto	123:b0220dba8be7	954	__O uint32_t TASKS_START; /!< Start the quadrature decoder. /
Kojto	123:b0220dba8be7	955	__O uint32_t TASKS_STOP; /!< Stop the quadrature decoder. /
Kojto	123:b0220dba8be7	956	__O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers,
Kojto	123:b0220dba8be7	957	and clears the ACC registers. */
Kojto	123:b0220dba8be7	958	__I uint32_t RESERVED0[61];
Kojto	123:b0220dba8be7	959	__IO uint32_t EVENTS_SAMPLERDY; /!< A new sample is written to the sample register. /
Kojto	123:b0220dba8be7	960	__IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and
Kojto	123:b0220dba8be7	961	ACC register different than zero. */
Kojto	123:b0220dba8be7	962	__IO uint32_t EVENTS_ACCOF; /!< ACC or ACCDBL register overflow. /
Kojto	123:b0220dba8be7	963	__I uint32_t RESERVED1[61];
Kojto	123:b0220dba8be7	964	__IO uint32_t SHORTS; /!< Shortcuts for the QDEC. /
Kojto	123:b0220dba8be7	965	__I uint32_t RESERVED2[64];
Kojto	123:b0220dba8be7	966	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
Kojto	123:b0220dba8be7	967	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
Kojto	123:b0220dba8be7	968	__I uint32_t RESERVED3[125];
Kojto	123:b0220dba8be7	969	__IO uint32_t ENABLE; /!< Enable the QDEC. /
Kojto	123:b0220dba8be7	970	__IO uint32_t LEDPOL; /!< LED output pin polarity. /
Kojto	123:b0220dba8be7	971	__IO uint32_t SAMPLEPER; /!< Sample period. /
Kojto	123:b0220dba8be7	972	__I int32_t SAMPLE; /!< Motion sample value. /
Kojto	123:b0220dba8be7	973	__IO uint32_t REPORTPER; /!< Number of samples to generate an EVENT_REPORTRDY. /
Kojto	123:b0220dba8be7	974	__I int32_t ACC; /!< Accumulated valid transitions register. /
Kojto	123:b0220dba8be7	975	__I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
Kojto	123:b0220dba8be7	976	task. */
Kojto	123:b0220dba8be7	977	__IO uint32_t PSELLED; /!< Pin select for LED output. /
Kojto	123:b0220dba8be7	978	__IO uint32_t PSELA; /!< Pin select for phase A input. /
Kojto	123:b0220dba8be7	979	__IO uint32_t PSELB; /!< Pin select for phase B input. /
Kojto	123:b0220dba8be7	980	__IO uint32_t DBFEN; /!< Enable debouncer input filters. /
Kojto	123:b0220dba8be7	981	__I uint32_t RESERVED4[5];
Kojto	123:b0220dba8be7	982	__IO uint32_t LEDPRE; /!< Time LED is switched ON before the sample. /
Kojto	123:b0220dba8be7	983	__I uint32_t ACCDBL; /!< Accumulated double (error) transitions register. /
Kojto	123:b0220dba8be7	984	__I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
Kojto	123:b0220dba8be7	985	task. */
Kojto	123:b0220dba8be7	986	__I uint32_t RESERVED5[684];
Kojto	123:b0220dba8be7	987	__IO uint32_t POWER; /!< Peripheral power control. /
Kojto	123:b0220dba8be7	988	} NRF_QDEC_Type;
Kojto	123:b0220dba8be7	989
Kojto	123:b0220dba8be7	990
Kojto	123:b0220dba8be7	991	/* ================================================================================ */
Kojto	123:b0220dba8be7	992	/* ================ LPCOMP ================ */
Kojto	123:b0220dba8be7	993	/* ================================================================================ */
Kojto	123:b0220dba8be7	994
Kojto	123:b0220dba8be7	995
Kojto	123:b0220dba8be7	996	/**
Kojto	123:b0220dba8be7	997	* @brief Low power comparator. (LPCOMP)
Kojto	123:b0220dba8be7	998	*/
Kojto	123:b0220dba8be7	999
Kojto	123:b0220dba8be7	1000	typedef struct { /!< LPCOMP Structure /
Kojto	123:b0220dba8be7	1001	__O uint32_t TASKS_START; /!< Start the comparator. /
Kojto	123:b0220dba8be7	1002	__O uint32_t TASKS_STOP; /!< Stop the comparator. /
Kojto	123:b0220dba8be7	1003	__O uint32_t TASKS_SAMPLE; /!< Sample comparator value. /
Kojto	123:b0220dba8be7	1004	__I uint32_t RESERVED0[61];
Kojto	123:b0220dba8be7	1005	__IO uint32_t EVENTS_READY; /!< LPCOMP is ready and output is valid. /
Kojto	123:b0220dba8be7	1006	__IO uint32_t EVENTS_DOWN; /!< Input voltage crossed the threshold going down. /
Kojto	123:b0220dba8be7	1007	__IO uint32_t EVENTS_UP; /!< Input voltage crossed the threshold going up. /
Kojto	123:b0220dba8be7	1008	__IO uint32_t EVENTS_CROSS; /!< Input voltage crossed the threshold in any direction. /
Kojto	123:b0220dba8be7	1009	__I uint32_t RESERVED1[60];
Kojto	123:b0220dba8be7	1010	__IO uint32_t SHORTS; /!< Shortcuts for the LPCOMP. /
Kojto	123:b0220dba8be7	1011	__I uint32_t RESERVED2[64];
Kojto	123:b0220dba8be7	1012	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
Kojto	123:b0220dba8be7	1013	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
Kojto	123:b0220dba8be7	1014	__I uint32_t RESERVED3[61];
Kojto	123:b0220dba8be7	1015	__I uint32_t RESULT; /!< Result of last compare. /
Kojto	123:b0220dba8be7	1016	__I uint32_t RESERVED4[63];
Kojto	123:b0220dba8be7	1017	__IO uint32_t ENABLE; /!< Enable the LPCOMP. /
Kojto	123:b0220dba8be7	1018	__IO uint32_t PSEL; /!< Input pin select. /
Kojto	123:b0220dba8be7	1019	__IO uint32_t REFSEL; /!< Reference select. /
Kojto	123:b0220dba8be7	1020	__IO uint32_t EXTREFSEL; /!< External reference select. /
Kojto	123:b0220dba8be7	1021	__I uint32_t RESERVED5[4];
Kojto	123:b0220dba8be7	1022	__IO uint32_t ANADETECT; /!< Analog detect configuration. /
Kojto	123:b0220dba8be7	1023	__I uint32_t RESERVED6[694];
Kojto	123:b0220dba8be7	1024	__IO uint32_t POWER; /!< Peripheral power control. /
Kojto	123:b0220dba8be7	1025	} NRF_LPCOMP_Type;
Kojto	123:b0220dba8be7	1026
Kojto	123:b0220dba8be7	1027
Kojto	123:b0220dba8be7	1028	/* ================================================================================ */
Kojto	123:b0220dba8be7	1029	/* ================ SWI ================ */
Kojto	123:b0220dba8be7	1030	/* ================================================================================ */
Kojto	123:b0220dba8be7	1031
Kojto	123:b0220dba8be7	1032
Kojto	123:b0220dba8be7	1033	/**
Kojto	123:b0220dba8be7	1034	* @brief SW Interrupts. (SWI)
Kojto	123:b0220dba8be7	1035	*/
Kojto	123:b0220dba8be7	1036
Kojto	123:b0220dba8be7	1037	typedef struct { /!< SWI Structure /
Kojto	123:b0220dba8be7	1038	__I uint32_t UNUSED; /!< Unused. /
Kojto	123:b0220dba8be7	1039	} NRF_SWI_Type;
Kojto	123:b0220dba8be7	1040
Kojto	123:b0220dba8be7	1041
Kojto	123:b0220dba8be7	1042	/* ================================================================================ */
Kojto	123:b0220dba8be7	1043	/* ================ NVMC ================ */
Kojto	123:b0220dba8be7	1044	/* ================================================================================ */
Kojto	123:b0220dba8be7	1045
Kojto	123:b0220dba8be7	1046
Kojto	123:b0220dba8be7	1047	/**
Kojto	123:b0220dba8be7	1048	* @brief Non Volatile Memory Controller. (NVMC)
Kojto	123:b0220dba8be7	1049	*/
Kojto	123:b0220dba8be7	1050
Kojto	123:b0220dba8be7	1051	typedef struct { /!< NVMC Structure /
Kojto	123:b0220dba8be7	1052	__I uint32_t RESERVED0[256];
Kojto	123:b0220dba8be7	1053	__I uint32_t READY; /!< Ready flag. /
Kojto	123:b0220dba8be7	1054	__I uint32_t RESERVED1[64];
Kojto	123:b0220dba8be7	1055	__IO uint32_t CONFIG; /!< Configuration register. /
Kojto	123:b0220dba8be7	1056
Kojto	123:b0220dba8be7	1057	union {
Kojto	123:b0220dba8be7	1058	__IO uint32_t ERASEPCR1; /!< Register for erasing a non-protected non-volatile memory page. /
Kojto	123:b0220dba8be7	1059	__IO uint32_t ERASEPAGE; /!< Register for erasing a non-protected non-volatile memory page. /
Kojto	123:b0220dba8be7	1060	};
Kojto	123:b0220dba8be7	1061	__IO uint32_t ERASEALL; /!< Register for erasing all non-volatile user memory. /
Kojto	123:b0220dba8be7	1062	__IO uint32_t ERASEPCR0; /!< Register for erasing a protected non-volatile memory page. /
Kojto	123:b0220dba8be7	1063	__IO uint32_t ERASEUICR; /!< Register for start erasing User Information Congfiguration Registers. /
Kojto	123:b0220dba8be7	1064	} NRF_NVMC_Type;
Kojto	123:b0220dba8be7	1065
Kojto	123:b0220dba8be7	1066
Kojto	123:b0220dba8be7	1067	/* ================================================================================ */
Kojto	123:b0220dba8be7	1068	/* ================ PPI ================ */
Kojto	123:b0220dba8be7	1069	/* ================================================================================ */
Kojto	123:b0220dba8be7	1070
Kojto	123:b0220dba8be7	1071
Kojto	123:b0220dba8be7	1072	/**
Kojto	123:b0220dba8be7	1073	* @brief PPI controller. (PPI)
Kojto	123:b0220dba8be7	1074	*/
Kojto	123:b0220dba8be7	1075
Kojto	123:b0220dba8be7	1076	typedef struct { /!< PPI Structure /
Kojto	123:b0220dba8be7	1077	PPI_TASKS_CHG_Type TASKS_CHG[4]; /!< Channel group tasks. /
Kojto	123:b0220dba8be7	1078	__I uint32_t RESERVED0[312];
Kojto	123:b0220dba8be7	1079	__IO uint32_t CHEN; /!< Channel enable. /
Kojto	123:b0220dba8be7	1080	__IO uint32_t CHENSET; /!< Channel enable set. /
Kojto	123:b0220dba8be7	1081	__IO uint32_t CHENCLR; /!< Channel enable clear. /
Kojto	123:b0220dba8be7	1082	__I uint32_t RESERVED1;
Kojto	123:b0220dba8be7	1083	PPI_CH_Type CH[16]; /!< PPI Channel. /
Kojto	123:b0220dba8be7	1084	__I uint32_t RESERVED2[156];
Kojto	123:b0220dba8be7	1085	__IO uint32_t CHG[4]; /!< Channel group configuration. /
Kojto	123:b0220dba8be7	1086	} NRF_PPI_Type;
Kojto	123:b0220dba8be7	1087
Kojto	123:b0220dba8be7	1088
Kojto	123:b0220dba8be7	1089	/* ================================================================================ */
Kojto	123:b0220dba8be7	1090	/* ================ FICR ================ */
Kojto	123:b0220dba8be7	1091	/* ================================================================================ */
Kojto	123:b0220dba8be7	1092
Kojto	123:b0220dba8be7	1093
Kojto	123:b0220dba8be7	1094	/**
Kojto	123:b0220dba8be7	1095	* @brief Factory Information Configuration. (FICR)
Kojto	123:b0220dba8be7	1096	*/
Kojto	123:b0220dba8be7	1097
Kojto	123:b0220dba8be7	1098	typedef struct { /!< FICR Structure /
Kojto	123:b0220dba8be7	1099	__I uint32_t RESERVED0[4];
Kojto	123:b0220dba8be7	1100	__I uint32_t CODEPAGESIZE; /!< Code memory page size in bytes. /
Kojto	123:b0220dba8be7	1101	__I uint32_t CODESIZE; /!< Code memory size in pages. /
Kojto	123:b0220dba8be7	1102	__I uint32_t RESERVED1[4];
Kojto	123:b0220dba8be7	1103	__I uint32_t CLENR0; /!< Length of code region 0 in bytes. /
Kojto	123:b0220dba8be7	1104	__I uint32_t PPFC; /!< Pre-programmed factory code present. /
Kojto	123:b0220dba8be7	1105	__I uint32_t RESERVED2;
Kojto	123:b0220dba8be7	1106	__I uint32_t NUMRAMBLOCK; /!< Number of individualy controllable RAM blocks. /
Kojto	123:b0220dba8be7	1107
Kojto	123:b0220dba8be7	1108	union {
Kojto	123:b0220dba8be7	1109	__I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is
Kojto	123:b0220dba8be7	1110	kept for backward compatinility purposes. Use SIZERAMBLOCKS
Kojto	123:b0220dba8be7	1111	instead. */
Kojto	123:b0220dba8be7	1112	__I uint32_t SIZERAMBLOCKS; /!< Size of RAM blocks in bytes. /
Kojto	123:b0220dba8be7	1113	};
Kojto	123:b0220dba8be7	1114	__I uint32_t RESERVED3[5];
Kojto	123:b0220dba8be7	1115	__I uint32_t CONFIGID; /!< Configuration identifier. /
Kojto	123:b0220dba8be7	1116	__I uint32_t DEVICEID[2]; /!< Device identifier. /
Kojto	123:b0220dba8be7	1117	__I uint32_t RESERVED4[6];
Kojto	123:b0220dba8be7	1118	__I uint32_t ER[4]; /!< Encryption root. /
Kojto	123:b0220dba8be7	1119	__I uint32_t IR[4]; /!< Identity root. /
Kojto	123:b0220dba8be7	1120	__I uint32_t DEVICEADDRTYPE; /!< Device address type. /
Kojto	123:b0220dba8be7	1121	__I uint32_t DEVICEADDR[2]; /!< Device address. /
Kojto	123:b0220dba8be7	1122	__I uint32_t OVERRIDEEN; /!< Radio calibration override enable. /
Kojto	123:b0220dba8be7	1123	__I uint32_t NRF_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit
Kojto	123:b0220dba8be7	1124	mode. */
Kojto	123:b0220dba8be7	1125	__I uint32_t RESERVED5[10];
Kojto	123:b0220dba8be7	1126	__I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
Kojto	123:b0220dba8be7	1127	mode. */
Kojto	123:b0220dba8be7	1128	} NRF_FICR_Type;
Kojto	123:b0220dba8be7	1129
Kojto	123:b0220dba8be7	1130
Kojto	123:b0220dba8be7	1131	/* ================================================================================ */
Kojto	123:b0220dba8be7	1132	/* ================ UICR ================ */
Kojto	123:b0220dba8be7	1133	/* ================================================================================ */
Kojto	123:b0220dba8be7	1134
Kojto	123:b0220dba8be7	1135
Kojto	123:b0220dba8be7	1136	/**
Kojto	123:b0220dba8be7	1137	* @brief User Information Configuration. (UICR)
Kojto	123:b0220dba8be7	1138	*/
Kojto	123:b0220dba8be7	1139
Kojto	123:b0220dba8be7	1140	typedef struct { /!< UICR Structure /
Kojto	123:b0220dba8be7	1141	__IO uint32_t CLENR0; /!< Length of code region 0. /
Kojto	123:b0220dba8be7	1142	__IO uint32_t RBPCONF; /!< Readback protection configuration. /
Kojto	123:b0220dba8be7	1143	__IO uint32_t XTALFREQ; /!< Reset value for CLOCK XTALFREQ register. /
Kojto	123:b0220dba8be7	1144	__I uint32_t RESERVED0;
Kojto	123:b0220dba8be7	1145	__I uint32_t FWID; /!< Firmware ID. /
Kojto	123:b0220dba8be7	1146
Kojto	123:b0220dba8be7	1147	union {
Kojto	123:b0220dba8be7	1148	__IO uint32_t NRFFW[15]; /!< Reserved for Nordic firmware design. /
Kojto	123:b0220dba8be7	1149	__IO uint32_t BOOTLOADERADDR; /!< Bootloader start address. /
Kojto	123:b0220dba8be7	1150	};
Kojto	123:b0220dba8be7	1151	__IO uint32_t NRFHW[12]; /!< Reserved for Nordic hardware design. /
Kojto	123:b0220dba8be7	1152	__IO uint32_t CUSTOMER[32]; /!< Reserved for customer. /
Kojto	123:b0220dba8be7	1153	} NRF_UICR_Type;
Kojto	123:b0220dba8be7	1154
Kojto	123:b0220dba8be7	1155
Kojto	123:b0220dba8be7	1156	/* ================================================================================ */
Kojto	123:b0220dba8be7	1157	/* ================ GPIO ================ */
Kojto	123:b0220dba8be7	1158	/* ================================================================================ */
Kojto	123:b0220dba8be7	1159
Kojto	123:b0220dba8be7	1160
Kojto	123:b0220dba8be7	1161	/**
Kojto	123:b0220dba8be7	1162	* @brief General purpose input and output. (GPIO)
Kojto	123:b0220dba8be7	1163	*/
Kojto	123:b0220dba8be7	1164
Kojto	123:b0220dba8be7	1165	typedef struct { /!< GPIO Structure /
Kojto	123:b0220dba8be7	1166	__I uint32_t RESERVED0[321];
Kojto	123:b0220dba8be7	1167	__IO uint32_t OUT; /!< Write GPIO port. /
Kojto	123:b0220dba8be7	1168	__IO uint32_t OUTSET; /!< Set individual bits in GPIO port. /
Kojto	123:b0220dba8be7	1169	__IO uint32_t OUTCLR; /!< Clear individual bits in GPIO port. /
Kojto	123:b0220dba8be7	1170	__I uint32_t IN; /!< Read GPIO port. /
Kojto	123:b0220dba8be7	1171	__IO uint32_t DIR; /!< Direction of GPIO pins. /
Kojto	123:b0220dba8be7	1172	__IO uint32_t DIRSET; /!< DIR set register. /
Kojto	123:b0220dba8be7	1173	__IO uint32_t DIRCLR; /!< DIR clear register. /
Kojto	123:b0220dba8be7	1174	__I uint32_t RESERVED1[120];
Kojto	123:b0220dba8be7	1175	__IO uint32_t PIN_CNF[32]; /!< Configuration of GPIO pins. /
Kojto	123:b0220dba8be7	1176	} NRF_GPIO_Type;
Kojto	123:b0220dba8be7	1177
Kojto	123:b0220dba8be7	1178
Kojto	123:b0220dba8be7	1179	/* -------------------- End of section using anonymous unions ------------------- */
Kojto	123:b0220dba8be7	1180	#if defined(__CC_ARM)
Kojto	123:b0220dba8be7	1181	#pragma pop
Kojto	123:b0220dba8be7	1182	#elif defined(__ICCARM__)
Kojto	123:b0220dba8be7	1183	/* leave anonymous unions enabled */
Kojto	123:b0220dba8be7	1184	#elif defined(__GNUC__)
Kojto	123:b0220dba8be7	1185	/* anonymous unions are enabled by default */
Kojto	123:b0220dba8be7	1186	#elif defined(__TMS470__)
Kojto	123:b0220dba8be7	1187	/* anonymous unions are enabled by default */
Kojto	123:b0220dba8be7	1188	#elif defined(__TASKING__)
Kojto	123:b0220dba8be7	1189	#pragma warning restore
Kojto	123:b0220dba8be7	1190	#else
Kojto	123:b0220dba8be7	1191	#warning Not supported compiler type
Kojto	123:b0220dba8be7	1192	#endif
Kojto	123:b0220dba8be7	1193
Kojto	123:b0220dba8be7	1194
Kojto	123:b0220dba8be7	1195
Kojto	123:b0220dba8be7	1196
Kojto	123:b0220dba8be7	1197	/* ================================================================================ */
Kojto	123:b0220dba8be7	1198	/* ================ Peripheral memory map ================ */
Kojto	123:b0220dba8be7	1199	/* ================================================================================ */
Kojto	123:b0220dba8be7	1200
Kojto	123:b0220dba8be7	1201	#define NRF_POWER_BASE 0x40000000UL
Kojto	123:b0220dba8be7	1202	#define NRF_CLOCK_BASE 0x40000000UL
Kojto	123:b0220dba8be7	1203	#define NRF_MPU_BASE 0x40000000UL
Kojto	123:b0220dba8be7	1204	#define NRF_AMLI_BASE 0x40000000UL
Kojto	123:b0220dba8be7	1205	#define NRF_RADIO_BASE 0x40001000UL
Kojto	123:b0220dba8be7	1206	#define NRF_UART0_BASE 0x40002000UL
Kojto	123:b0220dba8be7	1207	#define NRF_SPI0_BASE 0x40003000UL
Kojto	123:b0220dba8be7	1208	#define NRF_TWI0_BASE 0x40003000UL
Kojto	123:b0220dba8be7	1209	#define NRF_SPI1_BASE 0x40004000UL
Kojto	123:b0220dba8be7	1210	#define NRF_TWI1_BASE 0x40004000UL
Kojto	123:b0220dba8be7	1211	#define NRF_SPIS1_BASE 0x40004000UL
Kojto	123:b0220dba8be7	1212	#define NRF_SPIM1_BASE 0x40004000UL
Kojto	123:b0220dba8be7	1213	#define NRF_GPIOTE_BASE 0x40006000UL
Kojto	123:b0220dba8be7	1214	#define NRF_ADC_BASE 0x40007000UL
Kojto	123:b0220dba8be7	1215	#define NRF_TIMER0_BASE 0x40008000UL
Kojto	123:b0220dba8be7	1216	#define NRF_TIMER1_BASE 0x40009000UL
Kojto	123:b0220dba8be7	1217	#define NRF_TIMER2_BASE 0x4000A000UL
Kojto	123:b0220dba8be7	1218	#define NRF_RTC0_BASE 0x4000B000UL
Kojto	123:b0220dba8be7	1219	#define NRF_TEMP_BASE 0x4000C000UL
Kojto	123:b0220dba8be7	1220	#define NRF_RNG_BASE 0x4000D000UL
Kojto	123:b0220dba8be7	1221	#define NRF_ECB_BASE 0x4000E000UL
Kojto	123:b0220dba8be7	1222	#define NRF_AAR_BASE 0x4000F000UL
Kojto	123:b0220dba8be7	1223	#define NRF_CCM_BASE 0x4000F000UL
Kojto	123:b0220dba8be7	1224	#define NRF_WDT_BASE 0x40010000UL
Kojto	123:b0220dba8be7	1225	#define NRF_RTC1_BASE 0x40011000UL
Kojto	123:b0220dba8be7	1226	#define NRF_QDEC_BASE 0x40012000UL
Kojto	123:b0220dba8be7	1227	#define NRF_LPCOMP_BASE 0x40013000UL
Kojto	123:b0220dba8be7	1228	#define NRF_SWI_BASE 0x40014000UL
Kojto	123:b0220dba8be7	1229	#define NRF_NVMC_BASE 0x4001E000UL
Kojto	123:b0220dba8be7	1230	#define NRF_PPI_BASE 0x4001F000UL
Kojto	123:b0220dba8be7	1231	#define NRF_FICR_BASE 0x10000000UL
Kojto	123:b0220dba8be7	1232	#define NRF_UICR_BASE 0x10001000UL
Kojto	123:b0220dba8be7	1233	#define NRF_GPIO_BASE 0x50000000UL
Kojto	123:b0220dba8be7	1234
Kojto	123:b0220dba8be7	1235
Kojto	123:b0220dba8be7	1236	/* ================================================================================ */
Kojto	123:b0220dba8be7	1237	/* ================ Peripheral declaration ================ */
Kojto	123:b0220dba8be7	1238	/* ================================================================================ */
Kojto	123:b0220dba8be7	1239
Kojto	123:b0220dba8be7	1240	#define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
Kojto	123:b0220dba8be7	1241	#define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
Kojto	123:b0220dba8be7	1242	#define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
Kojto	123:b0220dba8be7	1243	#define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
Kojto	123:b0220dba8be7	1244	#define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
Kojto	123:b0220dba8be7	1245	#define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
Kojto	123:b0220dba8be7	1246	#define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
Kojto	123:b0220dba8be7	1247	#define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE)
Kojto	123:b0220dba8be7	1248	#define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
Kojto	123:b0220dba8be7	1249	#define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
Kojto	123:b0220dba8be7	1250	#define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
Kojto	123:b0220dba8be7	1251	#define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE)
Kojto	123:b0220dba8be7	1252	#define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
Kojto	123:b0220dba8be7	1253	#define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE)
Kojto	123:b0220dba8be7	1254	#define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
Kojto	123:b0220dba8be7	1255	#define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE)
Kojto	123:b0220dba8be7	1256	#define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE)
Kojto	123:b0220dba8be7	1257	#define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE)
Kojto	123:b0220dba8be7	1258	#define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE)
Kojto	123:b0220dba8be7	1259	#define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE)
Kojto	123:b0220dba8be7	1260	#define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE)
Kojto	123:b0220dba8be7	1261	#define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE)
Kojto	123:b0220dba8be7	1262	#define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE)
Kojto	123:b0220dba8be7	1263	#define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE)
Kojto	123:b0220dba8be7	1264	#define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
Kojto	123:b0220dba8be7	1265	#define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
Kojto	123:b0220dba8be7	1266	#define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
Kojto	123:b0220dba8be7	1267	#define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE)
Kojto	123:b0220dba8be7	1268	#define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
Kojto	123:b0220dba8be7	1269	#define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
Kojto	123:b0220dba8be7	1270	#define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE)
Kojto	123:b0220dba8be7	1271	#define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE)
Kojto	123:b0220dba8be7	1272	#define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE)
Kojto	123:b0220dba8be7	1273
Kojto	123:b0220dba8be7	1274
Kojto	123:b0220dba8be7	1275	/** @} / / End of group Device_Peripheral_Registers */
Kojto	123:b0220dba8be7	1276	/** @} / / End of group nrf51 */
Kojto	123:b0220dba8be7	1277	/** @} / / End of group Nordic Semiconductor */
Kojto	123:b0220dba8be7	1278
Kojto	123:b0220dba8be7	1279	#ifdef __cplusplus
Kojto	123:b0220dba8be7	1280	}
Kojto	123:b0220dba8be7	1281	#endif
Kojto	123:b0220dba8be7	1282
Kojto	123:b0220dba8be7	1283
Kojto	123:b0220dba8be7	1284	#endif /* nrf51_H */
Kojto	123:b0220dba8be7	1285