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TARGET_NUCLEO_L053R8/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_ll_cortex.h@138:093f2bd7b9eb, 2017-03-14 (annotated)

Committer:
<>
Date:
Tue Mar 14 16:20:51 2017 +0000
Revision:
138:093f2bd7b9eb
Parent:
136:ef9c61f8c49f
Child:
167:84c0a372a020
Release 138 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3716: fix for issue #3715: correction in startup files for ARM and IAR, alignment of system_stm32f429xx.c files https://github.com/ARMmbed/mbed-os/pull/3716

3741: STM32 remove warning in hal_tick_32b.c file https://github.com/ARMmbed/mbed-os/pull/3741

3780: STM32L4 : Fix GPIO G port compatibility https://github.com/ARMmbed/mbed-os/pull/3780

3831: NCS36510: SPISLAVE enabled (Conflict resolved) https://github.com/ARMmbed/mbed-os/pull/3831

3836: Allow to redefine nRF's PSTORAGE_NUM_OF_PAGES outside of the mbed-os https://github.com/ARMmbed/mbed-os/pull/3836

3840: STM32: gpio SPEED - always set High Speed by default https://github.com/ARMmbed/mbed-os/pull/3840

3844: STM32 GPIO: Typo correction. Update comment (GPIO_IP_WITHOUT_BRR) https://github.com/ARMmbed/mbed-os/pull/3844

3850: STM32: change spi error to debug warning https://github.com/ARMmbed/mbed-os/pull/3850

3860: Define GPIO_IP_WITHOUT_BRR for xDot platform https://github.com/ARMmbed/mbed-os/pull/3860

3880: DISCO_F469NI: allow the use of CAN2 instance when CAN1 is not activated https://github.com/ARMmbed/mbed-os/pull/3880

3795: Fix pwm period calc https://github.com/ARMmbed/mbed-os/pull/3795

3828: STM32 CAN API: correct format and type https://github.com/ARMmbed/mbed-os/pull/3828

3842: TARGET_NRF: corrected spi_init() to properly handle re-initialization https://github.com/ARMmbed/mbed-os/pull/3842

3843: STM32L476xG: set APB2 clock to 80MHz (instead of 40MHz) https://github.com/ARMmbed/mbed-os/pull/3843

3879: NUCLEO_F446ZE: Add missing AnalogIn pins on PF_3, PF_5 and PF_10. https://github.com/ARMmbed/mbed-os/pull/3879

3902: Fix heap and stack size for NUCLEO_F746ZG https://github.com/ARMmbed/mbed-os/pull/3902

3829: can_write(): return error code when no tx mailboxes are available https://github.com/ARMmbed/mbed-os/pull/3829

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 136:ef9c61f8c49f 1 /**
Kojto 136:ef9c61f8c49f 2 ******************************************************************************
Kojto 136:ef9c61f8c49f 3 * @file stm32l0xx_ll_cortex.h
Kojto 136:ef9c61f8c49f 4 * @author MCD Application Team
Kojto 136:ef9c61f8c49f 5 * @version V1.7.0
Kojto 136:ef9c61f8c49f 6 * @date 31-May-2016
Kojto 136:ef9c61f8c49f 7 * @brief Header file of CORTEX LL module.
Kojto 136:ef9c61f8c49f 8 @verbatim
Kojto 136:ef9c61f8c49f 9 ==============================================================================
Kojto 136:ef9c61f8c49f 10 ##### How to use this driver #####
Kojto 136:ef9c61f8c49f 11 ==============================================================================
Kojto 136:ef9c61f8c49f 12 [..]
Kojto 136:ef9c61f8c49f 13 The LL CORTEX driver contains a set of generic APIs that can be
Kojto 136:ef9c61f8c49f 14 used by user:
Kojto 136:ef9c61f8c49f 15 (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
Kojto 136:ef9c61f8c49f 16 functions
Kojto 136:ef9c61f8c49f 17 (+) Low power mode configuration (SCB register of Cortex-MCU)
Kojto 136:ef9c61f8c49f 18 (+) MPU API to configure and enable regions
Kojto 136:ef9c61f8c49f 19 (+) API to access to MCU info (CPUID register)
Kojto 136:ef9c61f8c49f 20
Kojto 136:ef9c61f8c49f 21 @endverbatim
Kojto 136:ef9c61f8c49f 22 ******************************************************************************
Kojto 136:ef9c61f8c49f 23 * @attention
Kojto 136:ef9c61f8c49f 24 *
Kojto 136:ef9c61f8c49f 25 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
Kojto 136:ef9c61f8c49f 26 *
Kojto 136:ef9c61f8c49f 27 * Redistribution and use in source and binary forms, with or without modification,
Kojto 136:ef9c61f8c49f 28 * are permitted provided that the following conditions are met:
Kojto 136:ef9c61f8c49f 29 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 136:ef9c61f8c49f 30 * this list of conditions and the following disclaimer.
Kojto 136:ef9c61f8c49f 31 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 136:ef9c61f8c49f 32 * this list of conditions and the following disclaimer in the documentation
Kojto 136:ef9c61f8c49f 33 * and/or other materials provided with the distribution.
Kojto 136:ef9c61f8c49f 34 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 136:ef9c61f8c49f 35 * may be used to endorse or promote products derived from this software
Kojto 136:ef9c61f8c49f 36 * without specific prior written permission.
Kojto 136:ef9c61f8c49f 37 *
Kojto 136:ef9c61f8c49f 38 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 136:ef9c61f8c49f 39 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 136:ef9c61f8c49f 40 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 136:ef9c61f8c49f 41 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 136:ef9c61f8c49f 42 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 136:ef9c61f8c49f 43 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 136:ef9c61f8c49f 44 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 136:ef9c61f8c49f 45 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 136:ef9c61f8c49f 46 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 136:ef9c61f8c49f 47 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 136:ef9c61f8c49f 48 *
Kojto 136:ef9c61f8c49f 49 ******************************************************************************
Kojto 136:ef9c61f8c49f 50 */
Kojto 136:ef9c61f8c49f 51
Kojto 136:ef9c61f8c49f 52 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 136:ef9c61f8c49f 53 #ifndef __STM32L0xx_LL_CORTEX_H
Kojto 136:ef9c61f8c49f 54 #define __STM32L0xx_LL_CORTEX_H
Kojto 136:ef9c61f8c49f 55
Kojto 136:ef9c61f8c49f 56 #ifdef __cplusplus
Kojto 136:ef9c61f8c49f 57 extern "C" {
Kojto 136:ef9c61f8c49f 58 #endif
Kojto 136:ef9c61f8c49f 59
Kojto 136:ef9c61f8c49f 60 /* Includes ------------------------------------------------------------------*/
Kojto 136:ef9c61f8c49f 61 #include "stm32l0xx.h"
Kojto 136:ef9c61f8c49f 62
Kojto 136:ef9c61f8c49f 63 /** @addtogroup STM32L0xx_LL_Driver
Kojto 136:ef9c61f8c49f 64 * @{
Kojto 136:ef9c61f8c49f 65 */
Kojto 136:ef9c61f8c49f 66
Kojto 136:ef9c61f8c49f 67 /** @defgroup CORTEX_LL CORTEX
Kojto 136:ef9c61f8c49f 68 * @{
Kojto 136:ef9c61f8c49f 69 */
Kojto 136:ef9c61f8c49f 70
Kojto 136:ef9c61f8c49f 71 /* Private types -------------------------------------------------------------*/
Kojto 136:ef9c61f8c49f 72 /* Private variables ---------------------------------------------------------*/
Kojto 136:ef9c61f8c49f 73
Kojto 136:ef9c61f8c49f 74 /* Private constants ---------------------------------------------------------*/
Kojto 136:ef9c61f8c49f 75
Kojto 136:ef9c61f8c49f 76 /* Private macros ------------------------------------------------------------*/
Kojto 136:ef9c61f8c49f 77
Kojto 136:ef9c61f8c49f 78 /* Exported types ------------------------------------------------------------*/
Kojto 136:ef9c61f8c49f 79 /* Exported constants --------------------------------------------------------*/
Kojto 136:ef9c61f8c49f 80 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
Kojto 136:ef9c61f8c49f 81 * @{
Kojto 136:ef9c61f8c49f 82 */
Kojto 136:ef9c61f8c49f 83
Kojto 136:ef9c61f8c49f 84 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
Kojto 136:ef9c61f8c49f 85 * @{
Kojto 136:ef9c61f8c49f 86 */
Kojto 136:ef9c61f8c49f 87 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U) /*!< AHB clock divided by 8 selected as SysTick clock source.*/
Kojto 136:ef9c61f8c49f 88 #define LL_SYSTICK_CLKSOURCE_HCLK ((uint32_t)SysTick_CTRL_CLKSOURCE_Msk) /*!< AHB clock selected as SysTick clock source. */
Kojto 136:ef9c61f8c49f 89 /**
Kojto 136:ef9c61f8c49f 90 * @}
Kojto 136:ef9c61f8c49f 91 */
Kojto 136:ef9c61f8c49f 92
Kojto 136:ef9c61f8c49f 93 #if __MPU_PRESENT
Kojto 136:ef9c61f8c49f 94
Kojto 136:ef9c61f8c49f 95 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
Kojto 136:ef9c61f8c49f 96 * @{
Kojto 136:ef9c61f8c49f 97 */
Kojto 136:ef9c61f8c49f 98 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U) /*!< Disable NMI and privileged SW access */
Kojto 136:ef9c61f8c49f 99 #define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
Kojto 136:ef9c61f8c49f 100 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
Kojto 136:ef9c61f8c49f 101 #define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
Kojto 136:ef9c61f8c49f 102 /**
Kojto 136:ef9c61f8c49f 103 * @}
Kojto 136:ef9c61f8c49f 104 */
Kojto 136:ef9c61f8c49f 105
Kojto 136:ef9c61f8c49f 106 /** @defgroup CORTEX_LL_EC_REGION MPU Region Number
Kojto 136:ef9c61f8c49f 107 * @{
Kojto 136:ef9c61f8c49f 108 */
Kojto 136:ef9c61f8c49f 109 #define LL_MPU_REGION_NUMBER0 ((uint32_t)0x00U) /*!< REGION Number 0 */
Kojto 136:ef9c61f8c49f 110 #define LL_MPU_REGION_NUMBER1 ((uint32_t)0x01U) /*!< REGION Number 1 */
Kojto 136:ef9c61f8c49f 111 #define LL_MPU_REGION_NUMBER2 ((uint32_t)0x02U) /*!< REGION Number 2 */
Kojto 136:ef9c61f8c49f 112 #define LL_MPU_REGION_NUMBER3 ((uint32_t)0x03U) /*!< REGION Number 3 */
Kojto 136:ef9c61f8c49f 113 #define LL_MPU_REGION_NUMBER4 ((uint32_t)0x04U) /*!< REGION Number 4 */
Kojto 136:ef9c61f8c49f 114 #define LL_MPU_REGION_NUMBER5 ((uint32_t)0x05U) /*!< REGION Number 5 */
Kojto 136:ef9c61f8c49f 115 #define LL_MPU_REGION_NUMBER6 ((uint32_t)0x06U) /*!< REGION Number 6 */
Kojto 136:ef9c61f8c49f 116 #define LL_MPU_REGION_NUMBER7 ((uint32_t)0x07U) /*!< REGION Number 7 */
Kojto 136:ef9c61f8c49f 117 /**
Kojto 136:ef9c61f8c49f 118 * @}
Kojto 136:ef9c61f8c49f 119 */
Kojto 136:ef9c61f8c49f 120
Kojto 136:ef9c61f8c49f 121 /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
Kojto 136:ef9c61f8c49f 122 * @{
Kojto 136:ef9c61f8c49f 123 */
Kojto 136:ef9c61f8c49f 124 #define LL_MPU_REGION_SIZE_32B ((uint32_t)(0x04U << MPU_RASR_SIZE_Pos)) /*!< 32B Size of the MPU protection region */
Kojto 136:ef9c61f8c49f 125 #define LL_MPU_REGION_SIZE_64B ((uint32_t)(0x05U << MPU_RASR_SIZE_Pos)) /*!< 64B Size of the MPU protection region */
Kojto 136:ef9c61f8c49f 126 #define LL_MPU_REGION_SIZE_128B ((uint32_t)(0x06U << MPU_RASR_SIZE_Pos)) /*!< 128B Size of the MPU protection region */
Kojto 136:ef9c61f8c49f 127 #define LL_MPU_REGION_SIZE_256B ((uint32_t)(0x07U << MPU_RASR_SIZE_Pos)) /*!< 256B Size of the MPU protection region */
Kojto 136:ef9c61f8c49f 128 #define LL_MPU_REGION_SIZE_512B ((uint32_t)(0x08U << MPU_RASR_SIZE_Pos)) /*!< 512B Size of the MPU protection region */
Kojto 136:ef9c61f8c49f 129 #define LL_MPU_REGION_SIZE_1KB ((uint32_t)(0x09U << MPU_RASR_SIZE_Pos)) /*!< 1KB Size of the MPU protection region */
Kojto 136:ef9c61f8c49f 130 #define LL_MPU_REGION_SIZE_2KB ((uint32_t)(0x0AU << MPU_RASR_SIZE_Pos)) /*!< 2KB Size of the MPU protection region */
Kojto 136:ef9c61f8c49f 131 #define LL_MPU_REGION_SIZE_4KB ((uint32_t)(0x0BU << MPU_RASR_SIZE_Pos)) /*!< 4KB Size of the MPU protection region */
Kojto 136:ef9c61f8c49f 132 #define LL_MPU_REGION_SIZE_8KB ((uint32_t)(0x0CU << MPU_RASR_SIZE_Pos)) /*!< 8KB Size of the MPU protection region */
Kojto 136:ef9c61f8c49f 133 #define LL_MPU_REGION_SIZE_16KB ((uint32_t)(0x0DU << MPU_RASR_SIZE_Pos)) /*!< 16KB Size of the MPU protection region */
Kojto 136:ef9c61f8c49f 134 #define LL_MPU_REGION_SIZE_32KB ((uint32_t)(0x0EU << MPU_RASR_SIZE_Pos)) /*!< 32KB Size of the MPU protection region */
Kojto 136:ef9c61f8c49f 135 #define LL_MPU_REGION_SIZE_64KB ((uint32_t)(0x0FU << MPU_RASR_SIZE_Pos)) /*!< 64KB Size of the MPU protection region */
Kojto 136:ef9c61f8c49f 136 #define LL_MPU_REGION_SIZE_128KB ((uint32_t)(0x10U << MPU_RASR_SIZE_Pos)) /*!< 128KB Size of the MPU protection region */
Kojto 136:ef9c61f8c49f 137 #define LL_MPU_REGION_SIZE_256KB ((uint32_t)(0x11U << MPU_RASR_SIZE_Pos)) /*!< 256KB Size of the MPU protection region */
Kojto 136:ef9c61f8c49f 138 #define LL_MPU_REGION_SIZE_512KB ((uint32_t)(0x12U << MPU_RASR_SIZE_Pos)) /*!< 512KB Size of the MPU protection region */
Kojto 136:ef9c61f8c49f 139 #define LL_MPU_REGION_SIZE_1MB ((uint32_t)(0x13U << MPU_RASR_SIZE_Pos)) /*!< 1MB Size of the MPU protection region */
Kojto 136:ef9c61f8c49f 140 #define LL_MPU_REGION_SIZE_2MB ((uint32_t)(0x14U << MPU_RASR_SIZE_Pos)) /*!< 2MB Size of the MPU protection region */
Kojto 136:ef9c61f8c49f 141 #define LL_MPU_REGION_SIZE_4MB ((uint32_t)(0x15U << MPU_RASR_SIZE_Pos)) /*!< 4MB Size of the MPU protection region */
Kojto 136:ef9c61f8c49f 142 #define LL_MPU_REGION_SIZE_8MB ((uint32_t)(0x16U << MPU_RASR_SIZE_Pos)) /*!< 8MB Size of the MPU protection region */
Kojto 136:ef9c61f8c49f 143 #define LL_MPU_REGION_SIZE_16MB ((uint32_t)(0x17U << MPU_RASR_SIZE_Pos)) /*!< 16MB Size of the MPU protection region */
Kojto 136:ef9c61f8c49f 144 #define LL_MPU_REGION_SIZE_32MB ((uint32_t)(0x18U << MPU_RASR_SIZE_Pos)) /*!< 32MB Size of the MPU protection region */
Kojto 136:ef9c61f8c49f 145 #define LL_MPU_REGION_SIZE_64MB ((uint32_t)(0x19U << MPU_RASR_SIZE_Pos)) /*!< 64MB Size of the MPU protection region */
Kojto 136:ef9c61f8c49f 146 #define LL_MPU_REGION_SIZE_128MB ((uint32_t)(0x1AU << MPU_RASR_SIZE_Pos)) /*!< 128MB Size of the MPU protection region */
Kojto 136:ef9c61f8c49f 147 #define LL_MPU_REGION_SIZE_256MB ((uint32_t)(0x1BU << MPU_RASR_SIZE_Pos)) /*!< 256MB Size of the MPU protection region */
Kojto 136:ef9c61f8c49f 148 #define LL_MPU_REGION_SIZE_512MB ((uint32_t)(0x1CU << MPU_RASR_SIZE_Pos)) /*!< 512MB Size of the MPU protection region */
Kojto 136:ef9c61f8c49f 149 #define LL_MPU_REGION_SIZE_1GB ((uint32_t)(0x1DU << MPU_RASR_SIZE_Pos)) /*!< 1GB Size of the MPU protection region */
Kojto 136:ef9c61f8c49f 150 #define LL_MPU_REGION_SIZE_2GB ((uint32_t)(0x1EU << MPU_RASR_SIZE_Pos)) /*!< 2GB Size of the MPU protection region */
Kojto 136:ef9c61f8c49f 151 #define LL_MPU_REGION_SIZE_4GB ((uint32_t)(0x1FU << MPU_RASR_SIZE_Pos)) /*!< 4GB Size of the MPU protection region */
Kojto 136:ef9c61f8c49f 152 /**
Kojto 136:ef9c61f8c49f 153 * @}
Kojto 136:ef9c61f8c49f 154 */
Kojto 136:ef9c61f8c49f 155
Kojto 136:ef9c61f8c49f 156 /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
Kojto 136:ef9c61f8c49f 157 * @{
Kojto 136:ef9c61f8c49f 158 */
Kojto 136:ef9c61f8c49f 159 #define LL_MPU_REGION_NO_ACCESS ((uint32_t)(0x00U << MPU_RASR_AP_Pos)) /*!< No access*/
Kojto 136:ef9c61f8c49f 160 #define LL_MPU_REGION_PRIV_RW ((uint32_t)(0x01U << MPU_RASR_AP_Pos)) /*!< RW privileged (privileged access only)*/
Kojto 136:ef9c61f8c49f 161 #define LL_MPU_REGION_PRIV_RW_URO ((uint32_t)(0x02U << MPU_RASR_AP_Pos)) /*!< RW privileged - RO user (Write in a user program generates a fault) */
Kojto 136:ef9c61f8c49f 162 #define LL_MPU_REGION_FULL_ACCESS ((uint32_t)(0x03U << MPU_RASR_AP_Pos)) /*!< RW privileged & user (Full access) */
Kojto 136:ef9c61f8c49f 163 #define LL_MPU_REGION_PRIV_RO ((uint32_t)(0x05U << MPU_RASR_AP_Pos)) /*!< RO privileged (privileged read only)*/
Kojto 136:ef9c61f8c49f 164 #define LL_MPU_REGION_PRIV_RO_URO ((uint32_t)(0x06U << MPU_RASR_AP_Pos)) /*!< RO privileged & user (read only) */
Kojto 136:ef9c61f8c49f 165 /**
Kojto 136:ef9c61f8c49f 166 * @}
Kojto 136:ef9c61f8c49f 167 */
Kojto 136:ef9c61f8c49f 168
Kojto 136:ef9c61f8c49f 169 /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
Kojto 136:ef9c61f8c49f 170 * @{
Kojto 136:ef9c61f8c49f 171 */
Kojto 136:ef9c61f8c49f 172 #define LL_MPU_TEX_LEVEL0 ((uint32_t)(0x00U << MPU_RASR_TEX_Pos)) /*!< b000 for TEX bits */
Kojto 136:ef9c61f8c49f 173 #define LL_MPU_TEX_LEVEL1 ((uint32_t)(0x01U << MPU_RASR_TEX_Pos)) /*!< b001 for TEX bits */
Kojto 136:ef9c61f8c49f 174 #define LL_MPU_TEX_LEVEL2 ((uint32_t)(0x02U << MPU_RASR_TEX_Pos)) /*!< b010 for TEX bits */
Kojto 136:ef9c61f8c49f 175 #define LL_MPU_TEX_LEVEL4 ((uint32_t)(0x04U << MPU_RASR_TEX_Pos)) /*!< b100 for TEX bits */
Kojto 136:ef9c61f8c49f 176 /**
Kojto 136:ef9c61f8c49f 177 * @}
Kojto 136:ef9c61f8c49f 178 */
Kojto 136:ef9c61f8c49f 179
Kojto 136:ef9c61f8c49f 180 /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
Kojto 136:ef9c61f8c49f 181 * @{
Kojto 136:ef9c61f8c49f 182 */
Kojto 136:ef9c61f8c49f 183 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE ((uint32_t)0x00U) /*!< Instruction fetches enabled */
Kojto 136:ef9c61f8c49f 184 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
Kojto 136:ef9c61f8c49f 185 /**
Kojto 136:ef9c61f8c49f 186 * @}
Kojto 136:ef9c61f8c49f 187 */
Kojto 136:ef9c61f8c49f 188
Kojto 136:ef9c61f8c49f 189 /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
Kojto 136:ef9c61f8c49f 190 * @{
Kojto 136:ef9c61f8c49f 191 */
Kojto 136:ef9c61f8c49f 192 #define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
Kojto 136:ef9c61f8c49f 193 #define LL_MPU_ACCESS_NOT_SHAREABLE ((uint32_t)0x00U) /*!< Not Shareable memory attribute */
Kojto 136:ef9c61f8c49f 194 /**
Kojto 136:ef9c61f8c49f 195 * @}
Kojto 136:ef9c61f8c49f 196 */
Kojto 136:ef9c61f8c49f 197
Kojto 136:ef9c61f8c49f 198 /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
Kojto 136:ef9c61f8c49f 199 * @{
Kojto 136:ef9c61f8c49f 200 */
Kojto 136:ef9c61f8c49f 201 #define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
Kojto 136:ef9c61f8c49f 202 #define LL_MPU_ACCESS_NOT_CACHEABLE ((uint32_t)0x00U) /*!< Not Cacheable memory attribute */
Kojto 136:ef9c61f8c49f 203 /**
Kojto 136:ef9c61f8c49f 204 * @}
Kojto 136:ef9c61f8c49f 205 */
Kojto 136:ef9c61f8c49f 206
Kojto 136:ef9c61f8c49f 207 /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
Kojto 136:ef9c61f8c49f 208 * @{
Kojto 136:ef9c61f8c49f 209 */
Kojto 136:ef9c61f8c49f 210 #define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
Kojto 136:ef9c61f8c49f 211 #define LL_MPU_ACCESS_NOT_BUFFERABLE ((uint32_t)0x00U) /*!< Not Bufferable memory attribute */
Kojto 136:ef9c61f8c49f 212 /**
Kojto 136:ef9c61f8c49f 213 * @}
Kojto 136:ef9c61f8c49f 214 */
Kojto 136:ef9c61f8c49f 215 #endif /* __MPU_PRESENT */
Kojto 136:ef9c61f8c49f 216 /**
Kojto 136:ef9c61f8c49f 217 * @}
Kojto 136:ef9c61f8c49f 218 */
Kojto 136:ef9c61f8c49f 219
Kojto 136:ef9c61f8c49f 220 /* Exported macro ------------------------------------------------------------*/
Kojto 136:ef9c61f8c49f 221
Kojto 136:ef9c61f8c49f 222 /* Exported functions --------------------------------------------------------*/
Kojto 136:ef9c61f8c49f 223 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
Kojto 136:ef9c61f8c49f 224 * @{
Kojto 136:ef9c61f8c49f 225 */
Kojto 136:ef9c61f8c49f 226
Kojto 136:ef9c61f8c49f 227 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
Kojto 136:ef9c61f8c49f 228 * @{
Kojto 136:ef9c61f8c49f 229 */
Kojto 136:ef9c61f8c49f 230
Kojto 136:ef9c61f8c49f 231 /**
Kojto 136:ef9c61f8c49f 232 * @brief This function checks if the Systick counter flag is active or not.
Kojto 136:ef9c61f8c49f 233 * @note It can be used in timeout function on application side.
Kojto 136:ef9c61f8c49f 234 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
Kojto 136:ef9c61f8c49f 235 * @retval State of bit (1 or 0).
Kojto 136:ef9c61f8c49f 236 */
Kojto 136:ef9c61f8c49f 237 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
Kojto 136:ef9c61f8c49f 238 {
Kojto 136:ef9c61f8c49f 239 return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
Kojto 136:ef9c61f8c49f 240 }
Kojto 136:ef9c61f8c49f 241
Kojto 136:ef9c61f8c49f 242 /**
Kojto 136:ef9c61f8c49f 243 * @brief Configures the SysTick clock source
Kojto 136:ef9c61f8c49f 244 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
Kojto 136:ef9c61f8c49f 245 * @param Source This parameter can be one of the following values:
Kojto 136:ef9c61f8c49f 246 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
Kojto 136:ef9c61f8c49f 247 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
Kojto 136:ef9c61f8c49f 248 * @retval None
Kojto 136:ef9c61f8c49f 249 */
Kojto 136:ef9c61f8c49f 250 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
Kojto 136:ef9c61f8c49f 251 {
Kojto 136:ef9c61f8c49f 252 if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
Kojto 136:ef9c61f8c49f 253 {
Kojto 136:ef9c61f8c49f 254 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
Kojto 136:ef9c61f8c49f 255 }
Kojto 136:ef9c61f8c49f 256 else
Kojto 136:ef9c61f8c49f 257 {
Kojto 136:ef9c61f8c49f 258 CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
Kojto 136:ef9c61f8c49f 259 }
Kojto 136:ef9c61f8c49f 260 }
Kojto 136:ef9c61f8c49f 261
Kojto 136:ef9c61f8c49f 262 /**
Kojto 136:ef9c61f8c49f 263 * @brief Get the SysTick clock source
Kojto 136:ef9c61f8c49f 264 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
Kojto 136:ef9c61f8c49f 265 * @retval Returned value can be one of the following values:
Kojto 136:ef9c61f8c49f 266 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
Kojto 136:ef9c61f8c49f 267 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
Kojto 136:ef9c61f8c49f 268 */
Kojto 136:ef9c61f8c49f 269 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
Kojto 136:ef9c61f8c49f 270 {
Kojto 136:ef9c61f8c49f 271 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
Kojto 136:ef9c61f8c49f 272 }
Kojto 136:ef9c61f8c49f 273
Kojto 136:ef9c61f8c49f 274 /**
Kojto 136:ef9c61f8c49f 275 * @brief Enable SysTick exception request
Kojto 136:ef9c61f8c49f 276 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
Kojto 136:ef9c61f8c49f 277 * @retval None
Kojto 136:ef9c61f8c49f 278 */
Kojto 136:ef9c61f8c49f 279 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
Kojto 136:ef9c61f8c49f 280 {
Kojto 136:ef9c61f8c49f 281 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
Kojto 136:ef9c61f8c49f 282 }
Kojto 136:ef9c61f8c49f 283
Kojto 136:ef9c61f8c49f 284 /**
Kojto 136:ef9c61f8c49f 285 * @brief Disable SysTick exception request
Kojto 136:ef9c61f8c49f 286 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
Kojto 136:ef9c61f8c49f 287 * @retval None
Kojto 136:ef9c61f8c49f 288 */
Kojto 136:ef9c61f8c49f 289 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
Kojto 136:ef9c61f8c49f 290 {
Kojto 136:ef9c61f8c49f 291 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
Kojto 136:ef9c61f8c49f 292 }
Kojto 136:ef9c61f8c49f 293
Kojto 136:ef9c61f8c49f 294 /**
Kojto 136:ef9c61f8c49f 295 * @brief Checks if the SYSTICK interrupt is enabled or disabled.
Kojto 136:ef9c61f8c49f 296 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
Kojto 136:ef9c61f8c49f 297 * @retval State of bit (1 or 0).
Kojto 136:ef9c61f8c49f 298 */
Kojto 136:ef9c61f8c49f 299 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
Kojto 136:ef9c61f8c49f 300 {
Kojto 136:ef9c61f8c49f 301 return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
Kojto 136:ef9c61f8c49f 302 }
Kojto 136:ef9c61f8c49f 303
Kojto 136:ef9c61f8c49f 304 /**
Kojto 136:ef9c61f8c49f 305 * @}
Kojto 136:ef9c61f8c49f 306 */
Kojto 136:ef9c61f8c49f 307
Kojto 136:ef9c61f8c49f 308 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
Kojto 136:ef9c61f8c49f 309 * @{
Kojto 136:ef9c61f8c49f 310 */
Kojto 136:ef9c61f8c49f 311
Kojto 136:ef9c61f8c49f 312 /**
Kojto 136:ef9c61f8c49f 313 * @brief Processor uses sleep as its low power mode
Kojto 136:ef9c61f8c49f 314 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
Kojto 136:ef9c61f8c49f 315 * @retval None
Kojto 136:ef9c61f8c49f 316 */
Kojto 136:ef9c61f8c49f 317 __STATIC_INLINE void LL_LPM_EnableSleep(void)
Kojto 136:ef9c61f8c49f 318 {
Kojto 136:ef9c61f8c49f 319 /* Clear SLEEPDEEP bit of Cortex System Control Register */
Kojto 136:ef9c61f8c49f 320 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
Kojto 136:ef9c61f8c49f 321 }
Kojto 136:ef9c61f8c49f 322
Kojto 136:ef9c61f8c49f 323 /**
Kojto 136:ef9c61f8c49f 324 * @brief Processor uses deep sleep as its low power mode
Kojto 136:ef9c61f8c49f 325 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
Kojto 136:ef9c61f8c49f 326 * @retval None
Kojto 136:ef9c61f8c49f 327 */
Kojto 136:ef9c61f8c49f 328 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
Kojto 136:ef9c61f8c49f 329 {
Kojto 136:ef9c61f8c49f 330 /* Set SLEEPDEEP bit of Cortex System Control Register */
Kojto 136:ef9c61f8c49f 331 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
Kojto 136:ef9c61f8c49f 332 }
Kojto 136:ef9c61f8c49f 333
Kojto 136:ef9c61f8c49f 334 /**
Kojto 136:ef9c61f8c49f 335 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
Kojto 136:ef9c61f8c49f 336 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
Kojto 136:ef9c61f8c49f 337 * empty main application.
Kojto 136:ef9c61f8c49f 338 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
Kojto 136:ef9c61f8c49f 339 * @retval None
Kojto 136:ef9c61f8c49f 340 */
Kojto 136:ef9c61f8c49f 341 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
Kojto 136:ef9c61f8c49f 342 {
Kojto 136:ef9c61f8c49f 343 /* Set SLEEPONEXIT bit of Cortex System Control Register */
Kojto 136:ef9c61f8c49f 344 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
Kojto 136:ef9c61f8c49f 345 }
Kojto 136:ef9c61f8c49f 346
Kojto 136:ef9c61f8c49f 347 /**
Kojto 136:ef9c61f8c49f 348 * @brief Do not sleep when returning to Thread mode.
Kojto 136:ef9c61f8c49f 349 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
Kojto 136:ef9c61f8c49f 350 * @retval None
Kojto 136:ef9c61f8c49f 351 */
Kojto 136:ef9c61f8c49f 352 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
Kojto 136:ef9c61f8c49f 353 {
Kojto 136:ef9c61f8c49f 354 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
Kojto 136:ef9c61f8c49f 355 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
Kojto 136:ef9c61f8c49f 356 }
Kojto 136:ef9c61f8c49f 357
Kojto 136:ef9c61f8c49f 358 /**
Kojto 136:ef9c61f8c49f 359 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
Kojto 136:ef9c61f8c49f 360 * processor.
Kojto 136:ef9c61f8c49f 361 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
Kojto 136:ef9c61f8c49f 362 * @retval None
Kojto 136:ef9c61f8c49f 363 */
Kojto 136:ef9c61f8c49f 364 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
Kojto 136:ef9c61f8c49f 365 {
Kojto 136:ef9c61f8c49f 366 /* Set SEVEONPEND bit of Cortex System Control Register */
Kojto 136:ef9c61f8c49f 367 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
Kojto 136:ef9c61f8c49f 368 }
Kojto 136:ef9c61f8c49f 369
Kojto 136:ef9c61f8c49f 370 /**
Kojto 136:ef9c61f8c49f 371 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
Kojto 136:ef9c61f8c49f 372 * excluded
Kojto 136:ef9c61f8c49f 373 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
Kojto 136:ef9c61f8c49f 374 * @retval None
Kojto 136:ef9c61f8c49f 375 */
Kojto 136:ef9c61f8c49f 376 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
Kojto 136:ef9c61f8c49f 377 {
Kojto 136:ef9c61f8c49f 378 /* Clear SEVEONPEND bit of Cortex System Control Register */
Kojto 136:ef9c61f8c49f 379 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
Kojto 136:ef9c61f8c49f 380 }
Kojto 136:ef9c61f8c49f 381
Kojto 136:ef9c61f8c49f 382 /**
Kojto 136:ef9c61f8c49f 383 * @}
Kojto 136:ef9c61f8c49f 384 */
Kojto 136:ef9c61f8c49f 385
Kojto 136:ef9c61f8c49f 386 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
Kojto 136:ef9c61f8c49f 387 * @{
Kojto 136:ef9c61f8c49f 388 */
Kojto 136:ef9c61f8c49f 389
Kojto 136:ef9c61f8c49f 390 /**
Kojto 136:ef9c61f8c49f 391 * @brief Get Implementer code
Kojto 136:ef9c61f8c49f 392 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
Kojto 136:ef9c61f8c49f 393 * @retval Value should be equal to 0x41 for ARM
Kojto 136:ef9c61f8c49f 394 */
Kojto 136:ef9c61f8c49f 395 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
Kojto 136:ef9c61f8c49f 396 {
Kojto 136:ef9c61f8c49f 397 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
Kojto 136:ef9c61f8c49f 398 }
Kojto 136:ef9c61f8c49f 399
Kojto 136:ef9c61f8c49f 400 /**
Kojto 136:ef9c61f8c49f 401 * @brief Get Variant number (The r value in the rnpn product revision identifier)
Kojto 136:ef9c61f8c49f 402 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
Kojto 136:ef9c61f8c49f 403 * @retval Value between 0 and 255 (0x0: revision 0)
Kojto 136:ef9c61f8c49f 404 */
Kojto 136:ef9c61f8c49f 405 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
Kojto 136:ef9c61f8c49f 406 {
Kojto 136:ef9c61f8c49f 407 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
Kojto 136:ef9c61f8c49f 408 }
Kojto 136:ef9c61f8c49f 409
Kojto 136:ef9c61f8c49f 410 /**
Kojto 136:ef9c61f8c49f 411 * @brief Get Architecture number
Kojto 136:ef9c61f8c49f 412 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture
Kojto 136:ef9c61f8c49f 413 * @retval Value should be equal to 0xC for Cortex-M0+ devices
Kojto 136:ef9c61f8c49f 414 */
Kojto 136:ef9c61f8c49f 415 __STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void)
Kojto 136:ef9c61f8c49f 416 {
Kojto 136:ef9c61f8c49f 417 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
Kojto 136:ef9c61f8c49f 418 }
Kojto 136:ef9c61f8c49f 419
Kojto 136:ef9c61f8c49f 420 /**
Kojto 136:ef9c61f8c49f 421 * @brief Get Part number
Kojto 136:ef9c61f8c49f 422 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
Kojto 136:ef9c61f8c49f 423 * @retval Value should be equal to 0xC60 for Cortex-M0+
Kojto 136:ef9c61f8c49f 424 */
Kojto 136:ef9c61f8c49f 425 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
Kojto 136:ef9c61f8c49f 426 {
Kojto 136:ef9c61f8c49f 427 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
Kojto 136:ef9c61f8c49f 428 }
Kojto 136:ef9c61f8c49f 429
Kojto 136:ef9c61f8c49f 430 /**
Kojto 136:ef9c61f8c49f 431 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
Kojto 136:ef9c61f8c49f 432 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
Kojto 136:ef9c61f8c49f 433 * @retval Value between 0 and 255 (0x1: patch 1)
Kojto 136:ef9c61f8c49f 434 */
Kojto 136:ef9c61f8c49f 435 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
Kojto 136:ef9c61f8c49f 436 {
Kojto 136:ef9c61f8c49f 437 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
Kojto 136:ef9c61f8c49f 438 }
Kojto 136:ef9c61f8c49f 439
Kojto 136:ef9c61f8c49f 440 /**
Kojto 136:ef9c61f8c49f 441 * @}
Kojto 136:ef9c61f8c49f 442 */
Kojto 136:ef9c61f8c49f 443
Kojto 136:ef9c61f8c49f 444 #if __MPU_PRESENT
Kojto 136:ef9c61f8c49f 445 /** @defgroup CORTEX_LL_EF_MPU MPU
Kojto 136:ef9c61f8c49f 446 * @{
Kojto 136:ef9c61f8c49f 447 */
Kojto 136:ef9c61f8c49f 448
Kojto 136:ef9c61f8c49f 449 /**
Kojto 136:ef9c61f8c49f 450 * @brief Enable MPU with input options
Kojto 136:ef9c61f8c49f 451 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
Kojto 136:ef9c61f8c49f 452 * @param Options This parameter can be one of the following values:
Kojto 136:ef9c61f8c49f 453 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
Kojto 136:ef9c61f8c49f 454 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
Kojto 136:ef9c61f8c49f 455 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
Kojto 136:ef9c61f8c49f 456 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
Kojto 136:ef9c61f8c49f 457 * @retval None
Kojto 136:ef9c61f8c49f 458 */
Kojto 136:ef9c61f8c49f 459 __STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
Kojto 136:ef9c61f8c49f 460 {
Kojto 136:ef9c61f8c49f 461 /* Enable the MPU*/
Kojto 136:ef9c61f8c49f 462 WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
Kojto 136:ef9c61f8c49f 463 /* Ensure MPU settings take effects */
Kojto 136:ef9c61f8c49f 464 __DSB();
Kojto 136:ef9c61f8c49f 465 /* Sequence instruction fetches using update settings */
Kojto 136:ef9c61f8c49f 466 __ISB();
Kojto 136:ef9c61f8c49f 467 }
Kojto 136:ef9c61f8c49f 468
Kojto 136:ef9c61f8c49f 469 /**
Kojto 136:ef9c61f8c49f 470 * @brief Disable MPU
Kojto 136:ef9c61f8c49f 471 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
Kojto 136:ef9c61f8c49f 472 * @retval None
Kojto 136:ef9c61f8c49f 473 */
Kojto 136:ef9c61f8c49f 474 __STATIC_INLINE void LL_MPU_Disable(void)
Kojto 136:ef9c61f8c49f 475 {
Kojto 136:ef9c61f8c49f 476 /* Make sure outstanding transfers are done */
Kojto 136:ef9c61f8c49f 477 __DMB();
Kojto 136:ef9c61f8c49f 478 /* Disable MPU*/
Kojto 136:ef9c61f8c49f 479 WRITE_REG(MPU->CTRL, 0U);
Kojto 136:ef9c61f8c49f 480 }
Kojto 136:ef9c61f8c49f 481
Kojto 136:ef9c61f8c49f 482 /**
Kojto 136:ef9c61f8c49f 483 * @brief Check if MPU is enabled or not
Kojto 136:ef9c61f8c49f 484 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
Kojto 136:ef9c61f8c49f 485 * @retval State of bit (1 or 0).
Kojto 136:ef9c61f8c49f 486 */
Kojto 136:ef9c61f8c49f 487 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
Kojto 136:ef9c61f8c49f 488 {
Kojto 136:ef9c61f8c49f 489 return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
Kojto 136:ef9c61f8c49f 490 }
Kojto 136:ef9c61f8c49f 491
Kojto 136:ef9c61f8c49f 492 /**
Kojto 136:ef9c61f8c49f 493 * @brief Enable a MPU region
Kojto 136:ef9c61f8c49f 494 * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
Kojto 136:ef9c61f8c49f 495 * @param Region This parameter can be one of the following values:
Kojto 136:ef9c61f8c49f 496 * @arg @ref LL_MPU_REGION_NUMBER0
Kojto 136:ef9c61f8c49f 497 * @arg @ref LL_MPU_REGION_NUMBER1
Kojto 136:ef9c61f8c49f 498 * @arg @ref LL_MPU_REGION_NUMBER2
Kojto 136:ef9c61f8c49f 499 * @arg @ref LL_MPU_REGION_NUMBER3
Kojto 136:ef9c61f8c49f 500 * @arg @ref LL_MPU_REGION_NUMBER4
Kojto 136:ef9c61f8c49f 501 * @arg @ref LL_MPU_REGION_NUMBER5
Kojto 136:ef9c61f8c49f 502 * @arg @ref LL_MPU_REGION_NUMBER6
Kojto 136:ef9c61f8c49f 503 * @arg @ref LL_MPU_REGION_NUMBER7
Kojto 136:ef9c61f8c49f 504 * @retval None
Kojto 136:ef9c61f8c49f 505 */
Kojto 136:ef9c61f8c49f 506 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
Kojto 136:ef9c61f8c49f 507 {
Kojto 136:ef9c61f8c49f 508 /* Set Region number */
Kojto 136:ef9c61f8c49f 509 WRITE_REG(MPU->RNR, Region);
Kojto 136:ef9c61f8c49f 510 /* Enable the MPU region */
Kojto 136:ef9c61f8c49f 511 SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
Kojto 136:ef9c61f8c49f 512 }
Kojto 136:ef9c61f8c49f 513
Kojto 136:ef9c61f8c49f 514 /**
Kojto 136:ef9c61f8c49f 515 * @brief Configure and enable a region
Kojto 136:ef9c61f8c49f 516 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
Kojto 136:ef9c61f8c49f 517 * MPU_RBAR REGION LL_MPU_ConfigRegion\n
Kojto 136:ef9c61f8c49f 518 * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
Kojto 136:ef9c61f8c49f 519 * MPU_RASR XN LL_MPU_ConfigRegion\n
Kojto 136:ef9c61f8c49f 520 * MPU_RASR AP LL_MPU_ConfigRegion\n
Kojto 136:ef9c61f8c49f 521 * MPU_RASR S LL_MPU_ConfigRegion\n
Kojto 136:ef9c61f8c49f 522 * MPU_RASR C LL_MPU_ConfigRegion\n
Kojto 136:ef9c61f8c49f 523 * MPU_RASR B LL_MPU_ConfigRegion\n
Kojto 136:ef9c61f8c49f 524 * MPU_RASR SIZE LL_MPU_ConfigRegion
Kojto 136:ef9c61f8c49f 525 * @param Region This parameter can be one of the following values:
Kojto 136:ef9c61f8c49f 526 * @arg @ref LL_MPU_REGION_NUMBER0
Kojto 136:ef9c61f8c49f 527 * @arg @ref LL_MPU_REGION_NUMBER1
Kojto 136:ef9c61f8c49f 528 * @arg @ref LL_MPU_REGION_NUMBER2
Kojto 136:ef9c61f8c49f 529 * @arg @ref LL_MPU_REGION_NUMBER3
Kojto 136:ef9c61f8c49f 530 * @arg @ref LL_MPU_REGION_NUMBER4
Kojto 136:ef9c61f8c49f 531 * @arg @ref LL_MPU_REGION_NUMBER5
Kojto 136:ef9c61f8c49f 532 * @arg @ref LL_MPU_REGION_NUMBER6
Kojto 136:ef9c61f8c49f 533 * @arg @ref LL_MPU_REGION_NUMBER7
Kojto 136:ef9c61f8c49f 534 * @param Address Value of region base address
Kojto 136:ef9c61f8c49f 535 * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
Kojto 136:ef9c61f8c49f 536 * @param Attributes This parameter can be a combination of the following values:
Kojto 136:ef9c61f8c49f 537 * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
Kojto 136:ef9c61f8c49f 538 * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
Kojto 136:ef9c61f8c49f 539 * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
Kojto 136:ef9c61f8c49f 540 * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
Kojto 136:ef9c61f8c49f 541 * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
Kojto 136:ef9c61f8c49f 542 * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
Kojto 136:ef9c61f8c49f 543 * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
Kojto 136:ef9c61f8c49f 544 * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
Kojto 136:ef9c61f8c49f 545 * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
Kojto 136:ef9c61f8c49f 546 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
Kojto 136:ef9c61f8c49f 547 * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
Kojto 136:ef9c61f8c49f 548 * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
Kojto 136:ef9c61f8c49f 549 * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
Kojto 136:ef9c61f8c49f 550 * @retval None
Kojto 136:ef9c61f8c49f 551 */
Kojto 136:ef9c61f8c49f 552 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
Kojto 136:ef9c61f8c49f 553 {
Kojto 136:ef9c61f8c49f 554 /* Set Region number */
Kojto 136:ef9c61f8c49f 555 WRITE_REG(MPU->RNR, Region);
Kojto 136:ef9c61f8c49f 556 /* Set base address */
Kojto 136:ef9c61f8c49f 557 WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
Kojto 136:ef9c61f8c49f 558 /* Configure MPU */
Kojto 136:ef9c61f8c49f 559 WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
Kojto 136:ef9c61f8c49f 560 }
Kojto 136:ef9c61f8c49f 561
Kojto 136:ef9c61f8c49f 562 /**
Kojto 136:ef9c61f8c49f 563 * @brief Disable a region
Kojto 136:ef9c61f8c49f 564 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
Kojto 136:ef9c61f8c49f 565 * MPU_RASR ENABLE LL_MPU_DisableRegion
Kojto 136:ef9c61f8c49f 566 * @param Region This parameter can be one of the following values:
Kojto 136:ef9c61f8c49f 567 * @arg @ref LL_MPU_REGION_NUMBER0
Kojto 136:ef9c61f8c49f 568 * @arg @ref LL_MPU_REGION_NUMBER1
Kojto 136:ef9c61f8c49f 569 * @arg @ref LL_MPU_REGION_NUMBER2
Kojto 136:ef9c61f8c49f 570 * @arg @ref LL_MPU_REGION_NUMBER3
Kojto 136:ef9c61f8c49f 571 * @arg @ref LL_MPU_REGION_NUMBER4
Kojto 136:ef9c61f8c49f 572 * @arg @ref LL_MPU_REGION_NUMBER5
Kojto 136:ef9c61f8c49f 573 * @arg @ref LL_MPU_REGION_NUMBER6
Kojto 136:ef9c61f8c49f 574 * @arg @ref LL_MPU_REGION_NUMBER7
Kojto 136:ef9c61f8c49f 575 * @retval None
Kojto 136:ef9c61f8c49f 576 */
Kojto 136:ef9c61f8c49f 577 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
Kojto 136:ef9c61f8c49f 578 {
Kojto 136:ef9c61f8c49f 579 /* Set Region number */
Kojto 136:ef9c61f8c49f 580 WRITE_REG(MPU->RNR, Region);
Kojto 136:ef9c61f8c49f 581 /* Disable the MPU region */
Kojto 136:ef9c61f8c49f 582 CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
Kojto 136:ef9c61f8c49f 583 }
Kojto 136:ef9c61f8c49f 584
Kojto 136:ef9c61f8c49f 585 /**
Kojto 136:ef9c61f8c49f 586 * @}
Kojto 136:ef9c61f8c49f 587 */
Kojto 136:ef9c61f8c49f 588
Kojto 136:ef9c61f8c49f 589 #endif /* __MPU_PRESENT */
Kojto 136:ef9c61f8c49f 590 /**
Kojto 136:ef9c61f8c49f 591 * @}
Kojto 136:ef9c61f8c49f 592 */
Kojto 136:ef9c61f8c49f 593
Kojto 136:ef9c61f8c49f 594 /**
Kojto 136:ef9c61f8c49f 595 * @}
Kojto 136:ef9c61f8c49f 596 */
Kojto 136:ef9c61f8c49f 597
Kojto 136:ef9c61f8c49f 598 /**
Kojto 136:ef9c61f8c49f 599 * @}
Kojto 136:ef9c61f8c49f 600 */
Kojto 136:ef9c61f8c49f 601
Kojto 136:ef9c61f8c49f 602 #ifdef __cplusplus
Kojto 136:ef9c61f8c49f 603 }
Kojto 136:ef9c61f8c49f 604 #endif
Kojto 136:ef9c61f8c49f 605
Kojto 136:ef9c61f8c49f 606 #endif /* __STM32L0xx_LL_CORTEX_H */
Kojto 136:ef9c61f8c49f 607
Kojto 136:ef9c61f8c49f 608 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/