mbed official / mbed

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

TARGET_NUCLEO_F091RC/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_rcc.h@138:093f2bd7b9eb, 2017-03-14 (annotated)

Committer:
<>
Date:
Tue Mar 14 16:20:51 2017 +0000
Revision:
138:093f2bd7b9eb
Parent:
134:ad3be0349dc5
Child:
160:5571c4ff569f
Release 138 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3716: fix for issue #3715: correction in startup files for ARM and IAR, alignment of system_stm32f429xx.c files https://github.com/ARMmbed/mbed-os/pull/3716

3741: STM32 remove warning in hal_tick_32b.c file https://github.com/ARMmbed/mbed-os/pull/3741

3780: STM32L4 : Fix GPIO G port compatibility https://github.com/ARMmbed/mbed-os/pull/3780

3831: NCS36510: SPISLAVE enabled (Conflict resolved) https://github.com/ARMmbed/mbed-os/pull/3831

3836: Allow to redefine nRF's PSTORAGE_NUM_OF_PAGES outside of the mbed-os https://github.com/ARMmbed/mbed-os/pull/3836

3840: STM32: gpio SPEED - always set High Speed by default https://github.com/ARMmbed/mbed-os/pull/3840

3844: STM32 GPIO: Typo correction. Update comment (GPIO_IP_WITHOUT_BRR) https://github.com/ARMmbed/mbed-os/pull/3844

3850: STM32: change spi error to debug warning https://github.com/ARMmbed/mbed-os/pull/3850

3860: Define GPIO_IP_WITHOUT_BRR for xDot platform https://github.com/ARMmbed/mbed-os/pull/3860

3880: DISCO_F469NI: allow the use of CAN2 instance when CAN1 is not activated https://github.com/ARMmbed/mbed-os/pull/3880

3795: Fix pwm period calc https://github.com/ARMmbed/mbed-os/pull/3795

3828: STM32 CAN API: correct format and type https://github.com/ARMmbed/mbed-os/pull/3828

3842: TARGET_NRF: corrected spi_init() to properly handle re-initialization https://github.com/ARMmbed/mbed-os/pull/3842

3843: STM32L476xG: set APB2 clock to 80MHz (instead of 40MHz) https://github.com/ARMmbed/mbed-os/pull/3843

3879: NUCLEO_F446ZE: Add missing AnalogIn pins on PF_3, PF_5 and PF_10. https://github.com/ARMmbed/mbed-os/pull/3879

3902: Fix heap and stack size for NUCLEO_F746ZG https://github.com/ARMmbed/mbed-os/pull/3902

3829: can_write(): return error code when no tx mailboxes are available https://github.com/ARMmbed/mbed-os/pull/3829

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 134:ad3be0349dc5 1 /**
<> 134:ad3be0349dc5 2 ******************************************************************************
<> 134:ad3be0349dc5 3 * @file stm32f0xx_ll_rcc.h
<> 134:ad3be0349dc5 4 * @author MCD Application Team
<> 134:ad3be0349dc5 5 * @version V1.4.0
<> 134:ad3be0349dc5 6 * @date 27-May-2016
<> 134:ad3be0349dc5 7 * @brief Header file of RCC LL module.
<> 134:ad3be0349dc5 8 ******************************************************************************
<> 134:ad3be0349dc5 9 * @attention
<> 134:ad3be0349dc5 10 *
<> 134:ad3be0349dc5 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 134:ad3be0349dc5 12 *
<> 134:ad3be0349dc5 13 * Redistribution and use in source and binary forms, with or without modification,
<> 134:ad3be0349dc5 14 * are permitted provided that the following conditions are met:
<> 134:ad3be0349dc5 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 134:ad3be0349dc5 16 * this list of conditions and the following disclaimer.
<> 134:ad3be0349dc5 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 134:ad3be0349dc5 18 * this list of conditions and the following disclaimer in the documentation
<> 134:ad3be0349dc5 19 * and/or other materials provided with the distribution.
<> 134:ad3be0349dc5 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 134:ad3be0349dc5 21 * may be used to endorse or promote products derived from this software
<> 134:ad3be0349dc5 22 * without specific prior written permission.
<> 134:ad3be0349dc5 23 *
<> 134:ad3be0349dc5 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 134:ad3be0349dc5 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 134:ad3be0349dc5 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 134:ad3be0349dc5 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 134:ad3be0349dc5 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 134:ad3be0349dc5 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 134:ad3be0349dc5 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 134:ad3be0349dc5 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 134:ad3be0349dc5 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 134:ad3be0349dc5 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 134:ad3be0349dc5 34 *
<> 134:ad3be0349dc5 35 ******************************************************************************
<> 134:ad3be0349dc5 36 */
<> 134:ad3be0349dc5 37
<> 134:ad3be0349dc5 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 134:ad3be0349dc5 39 #ifndef __STM32F0xx_LL_RCC_H
<> 134:ad3be0349dc5 40 #define __STM32F0xx_LL_RCC_H
<> 134:ad3be0349dc5 41
<> 134:ad3be0349dc5 42 #ifdef __cplusplus
<> 134:ad3be0349dc5 43 extern "C" {
<> 134:ad3be0349dc5 44 #endif
<> 134:ad3be0349dc5 45
<> 134:ad3be0349dc5 46 /* Includes ------------------------------------------------------------------*/
<> 134:ad3be0349dc5 47 #include "stm32f0xx.h"
<> 134:ad3be0349dc5 48
<> 134:ad3be0349dc5 49 /** @addtogroup STM32F0xx_LL_Driver
<> 134:ad3be0349dc5 50 * @{
<> 134:ad3be0349dc5 51 */
<> 134:ad3be0349dc5 52
<> 134:ad3be0349dc5 53 #if defined(RCC)
<> 134:ad3be0349dc5 54
<> 134:ad3be0349dc5 55 /** @defgroup RCC_LL RCC
<> 134:ad3be0349dc5 56 * @{
<> 134:ad3be0349dc5 57 */
<> 134:ad3be0349dc5 58
<> 134:ad3be0349dc5 59 /* Private types -------------------------------------------------------------*/
<> 134:ad3be0349dc5 60 /* Private variables ---------------------------------------------------------*/
<> 134:ad3be0349dc5 61 /** @defgroup RCC_LL_Private_Variables RCC Private Variables
<> 134:ad3be0349dc5 62 * @{
<> 134:ad3be0349dc5 63 */
<> 134:ad3be0349dc5 64
<> 134:ad3be0349dc5 65 /**
<> 134:ad3be0349dc5 66 * @}
<> 134:ad3be0349dc5 67 */
<> 134:ad3be0349dc5 68
<> 134:ad3be0349dc5 69 /* Private constants ---------------------------------------------------------*/
<> 134:ad3be0349dc5 70 /** @defgroup RCC_LL_Private_Constants RCC Private Constants
<> 134:ad3be0349dc5 71 * @{
<> 134:ad3be0349dc5 72 */
<> 134:ad3be0349dc5 73 /* Defines used for the bit position in the register and perform offsets*/
<> 134:ad3be0349dc5 74 #define RCC_POSITION_HPRE (uint32_t)4U /*!< field position in register RCC_CFGR */
<> 134:ad3be0349dc5 75 #define RCC_POSITION_PPRE1 (uint32_t)8U /*!< field position in register RCC_CFGR */
<> 134:ad3be0349dc5 76 #define RCC_POSITION_PLLMUL (uint32_t)18U /*!< field position in register RCC_CFGR */
<> 134:ad3be0349dc5 77 #define RCC_POSITION_HSICAL (uint32_t)8U /*!< field position in register RCC_CR */
<> 134:ad3be0349dc5 78 #define RCC_POSITION_HSITRIM (uint32_t)3U /*!< field position in register RCC_CR */
<> 134:ad3be0349dc5 79 #define RCC_POSITION_HSI14TRIM (uint32_t)3U /*!< field position in register RCC_CR2 */
<> 134:ad3be0349dc5 80 #define RCC_POSITION_HSI14CAL (uint32_t)8U /*!< field position in register RCC_CR2 */
<> 134:ad3be0349dc5 81 #if defined(RCC_HSI48_SUPPORT)
<> 134:ad3be0349dc5 82 #define RCC_POSITION_HSI48CAL (uint32_t)24U /*!< field position in register RCC_CR2 */
<> 134:ad3be0349dc5 83 #endif /* RCC_HSI48_SUPPORT */
<> 134:ad3be0349dc5 84 #define RCC_POSITION_USART1SW (uint32_t)0U /*!< field position in register RCC_CFGR3 */
<> 134:ad3be0349dc5 85 #define RCC_POSITION_USART2SW (uint32_t)16U /*!< field position in register RCC_CFGR3 */
<> 134:ad3be0349dc5 86 #define RCC_POSITION_USART3SW (uint32_t)18U /*!< field position in register RCC_CFGR3 */
<> 134:ad3be0349dc5 87
<> 134:ad3be0349dc5 88 /**
<> 134:ad3be0349dc5 89 * @}
<> 134:ad3be0349dc5 90 */
<> 134:ad3be0349dc5 91
<> 134:ad3be0349dc5 92 /* Private macros ------------------------------------------------------------*/
<> 134:ad3be0349dc5 93 #if defined(USE_FULL_LL_DRIVER)
<> 134:ad3be0349dc5 94 /** @defgroup RCC_LL_Private_Macros RCC Private Macros
<> 134:ad3be0349dc5 95 * @{
<> 134:ad3be0349dc5 96 */
<> 134:ad3be0349dc5 97 /**
<> 134:ad3be0349dc5 98 * @}
<> 134:ad3be0349dc5 99 */
<> 134:ad3be0349dc5 100 #endif /*USE_FULL_LL_DRIVER*/
<> 134:ad3be0349dc5 101 /* Exported types ------------------------------------------------------------*/
<> 134:ad3be0349dc5 102 #if defined(USE_FULL_LL_DRIVER)
<> 134:ad3be0349dc5 103 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
<> 134:ad3be0349dc5 104 * @{
<> 134:ad3be0349dc5 105 */
<> 134:ad3be0349dc5 106
<> 134:ad3be0349dc5 107 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
<> 134:ad3be0349dc5 108 * @{
<> 134:ad3be0349dc5 109 */
<> 134:ad3be0349dc5 110
<> 134:ad3be0349dc5 111 /**
<> 134:ad3be0349dc5 112 * @brief RCC Clocks Frequency Structure
<> 134:ad3be0349dc5 113 */
<> 134:ad3be0349dc5 114 typedef struct
<> 134:ad3be0349dc5 115 {
<> 134:ad3be0349dc5 116 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
<> 134:ad3be0349dc5 117 uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
<> 134:ad3be0349dc5 118 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
<> 134:ad3be0349dc5 119 } LL_RCC_ClocksTypeDef;
<> 134:ad3be0349dc5 120
<> 134:ad3be0349dc5 121 /**
<> 134:ad3be0349dc5 122 * @}
<> 134:ad3be0349dc5 123 */
<> 134:ad3be0349dc5 124
<> 134:ad3be0349dc5 125 /**
<> 134:ad3be0349dc5 126 * @}
<> 134:ad3be0349dc5 127 */
<> 134:ad3be0349dc5 128 #endif /* USE_FULL_LL_DRIVER */
<> 134:ad3be0349dc5 129
<> 134:ad3be0349dc5 130 /* Exported constants --------------------------------------------------------*/
<> 134:ad3be0349dc5 131 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
<> 134:ad3be0349dc5 132 * @{
<> 134:ad3be0349dc5 133 */
<> 134:ad3be0349dc5 134
<> 134:ad3be0349dc5 135 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
<> 134:ad3be0349dc5 136 * @brief Defines used to adapt values of different oscillators
<> 134:ad3be0349dc5 137 * @note These values could be modified in the user environment according to
<> 134:ad3be0349dc5 138 * HW set-up.
<> 134:ad3be0349dc5 139 * @{
<> 134:ad3be0349dc5 140 */
<> 134:ad3be0349dc5 141 #if !defined (HSE_VALUE)
<> 134:ad3be0349dc5 142 #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the HSE oscillator in Hz */
<> 134:ad3be0349dc5 143 #endif /* HSE_VALUE */
<> 134:ad3be0349dc5 144
<> 134:ad3be0349dc5 145 #if !defined (HSI_VALUE)
<> 134:ad3be0349dc5 146 #define HSI_VALUE ((uint32_t)8000000U) /*!< Value of the HSI oscillator in Hz */
<> 134:ad3be0349dc5 147 #endif /* HSI_VALUE */
<> 134:ad3be0349dc5 148
<> 134:ad3be0349dc5 149 #if !defined (LSE_VALUE)
<> 134:ad3be0349dc5 150 #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the LSE oscillator in Hz */
<> 134:ad3be0349dc5 151 #endif /* LSE_VALUE */
<> 134:ad3be0349dc5 152
<> 134:ad3be0349dc5 153 #if !defined (LSI_VALUE)
<> 134:ad3be0349dc5 154 #define LSI_VALUE ((uint32_t)32000U) /*!< Value of the LSI oscillator in Hz */
<> 134:ad3be0349dc5 155 #endif /* LSI_VALUE */
<> 134:ad3be0349dc5 156 #if defined(RCC_HSI48_SUPPORT)
<> 134:ad3be0349dc5 157
<> 134:ad3be0349dc5 158 #if !defined (HSI48_VALUE)
<> 134:ad3be0349dc5 159 #define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the HSI48 oscillator in Hz */
<> 134:ad3be0349dc5 160 #endif /* HSI48_VALUE */
<> 134:ad3be0349dc5 161 #endif /* RCC_HSI48_SUPPORT */
<> 134:ad3be0349dc5 162 /**
<> 134:ad3be0349dc5 163 * @}
<> 134:ad3be0349dc5 164 */
<> 134:ad3be0349dc5 165
<> 134:ad3be0349dc5 166 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
<> 134:ad3be0349dc5 167 * @brief Flags defines which can be used with LL_RCC_WriteReg function
<> 134:ad3be0349dc5 168 * @{
<> 134:ad3be0349dc5 169 */
<> 134:ad3be0349dc5 170 #define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */
<> 134:ad3be0349dc5 171 #define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */
<> 134:ad3be0349dc5 172 #define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */
<> 134:ad3be0349dc5 173 #define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */
<> 134:ad3be0349dc5 174 #define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */
<> 134:ad3be0349dc5 175 #define LL_RCC_CIR_HSI14RDYC RCC_CIR_HSI14RDYC /*!< HSI14 Ready Interrupt Clear */
<> 134:ad3be0349dc5 176 #if defined(RCC_HSI48_SUPPORT)
<> 134:ad3be0349dc5 177 #define LL_RCC_CIR_HSI48RDYC RCC_CIR_HSI48RDYC /*!< HSI48 Ready Interrupt Clear */
<> 134:ad3be0349dc5 178 #endif /* RCC_HSI48_SUPPORT */
<> 134:ad3be0349dc5 179 #define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */
<> 134:ad3be0349dc5 180 /**
<> 134:ad3be0349dc5 181 * @}
<> 134:ad3be0349dc5 182 */
<> 134:ad3be0349dc5 183
<> 134:ad3be0349dc5 184 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
<> 134:ad3be0349dc5 185 * @brief Flags defines which can be used with LL_RCC_ReadReg function
<> 134:ad3be0349dc5 186 * @{
<> 134:ad3be0349dc5 187 */
<> 134:ad3be0349dc5 188 #define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */
<> 134:ad3be0349dc5 189 #define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */
<> 134:ad3be0349dc5 190 #define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */
<> 134:ad3be0349dc5 191 #define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */
<> 134:ad3be0349dc5 192 #define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */
<> 134:ad3be0349dc5 193 #define LL_RCC_CIR_HSI14RDYF RCC_CIR_HSI14RDYF /*!< HSI14 Ready Interrupt flag */
<> 134:ad3be0349dc5 194 #if defined(RCC_HSI48_SUPPORT)
<> 134:ad3be0349dc5 195 #define LL_RCC_CIR_HSI48RDYF RCC_CIR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */
<> 134:ad3be0349dc5 196 #endif /* RCC_HSI48_SUPPORT */
<> 134:ad3be0349dc5 197 #define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */
<> 134:ad3be0349dc5 198 #define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */
<> 134:ad3be0349dc5 199 #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
<> 134:ad3be0349dc5 200 #define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */
<> 134:ad3be0349dc5 201 #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
<> 134:ad3be0349dc5 202 #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
<> 134:ad3be0349dc5 203 #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
<> 134:ad3be0349dc5 204 #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
<> 134:ad3be0349dc5 205 #if defined(RCC_CSR_V18PWRRSTF)
<> 134:ad3be0349dc5 206 #define LL_RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF /*!< Reset flag of the 1.8 V domain. */
<> 134:ad3be0349dc5 207 #endif /* RCC_CSR_V18PWRRSTF */
<> 134:ad3be0349dc5 208 /**
<> 134:ad3be0349dc5 209 * @}
<> 134:ad3be0349dc5 210 */
<> 134:ad3be0349dc5 211
<> 134:ad3be0349dc5 212 /** @defgroup RCC_LL_EC_IT IT Defines
<> 134:ad3be0349dc5 213 * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
<> 134:ad3be0349dc5 214 * @{
<> 134:ad3be0349dc5 215 */
<> 134:ad3be0349dc5 216 #define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */
<> 134:ad3be0349dc5 217 #define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */
<> 134:ad3be0349dc5 218 #define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */
<> 134:ad3be0349dc5 219 #define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */
<> 134:ad3be0349dc5 220 #define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */
<> 134:ad3be0349dc5 221 #define LL_RCC_CIR_HSI14RDYIE RCC_CIR_HSI14RDYIE /*!< HSI14 Ready Interrupt Enable */
<> 134:ad3be0349dc5 222 #if defined(RCC_HSI48_SUPPORT)
<> 134:ad3be0349dc5 223 #define LL_RCC_CIR_HSI48RDYIE RCC_CIR_HSI48RDYIE /*!< HSI48 Ready Interrupt Enable */
<> 134:ad3be0349dc5 224 #endif /* RCC_HSI48_SUPPORT */
<> 134:ad3be0349dc5 225 /**
<> 134:ad3be0349dc5 226 * @}
<> 134:ad3be0349dc5 227 */
<> 134:ad3be0349dc5 228
<> 134:ad3be0349dc5 229 /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
<> 134:ad3be0349dc5 230 * @{
<> 134:ad3be0349dc5 231 */
<> 134:ad3be0349dc5 232 #define LL_RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) /*!< Xtal mode lower driving capability */
<> 134:ad3be0349dc5 233 #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low driving capability */
<> 134:ad3be0349dc5 234 #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high driving capability */
<> 134:ad3be0349dc5 235 #define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */
<> 134:ad3be0349dc5 236 /**
<> 134:ad3be0349dc5 237 * @}
<> 134:ad3be0349dc5 238 */
<> 134:ad3be0349dc5 239
<> 134:ad3be0349dc5 240 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
<> 134:ad3be0349dc5 241 * @{
<> 134:ad3be0349dc5 242 */
<> 134:ad3be0349dc5 243 #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
<> 134:ad3be0349dc5 244 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
<> 134:ad3be0349dc5 245 #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
<> 134:ad3be0349dc5 246 #if defined(RCC_CFGR_SW_HSI48)
<> 134:ad3be0349dc5 247 #define LL_RCC_SYS_CLKSOURCE_HSI48 RCC_CFGR_SW_HSI48 /*!< HSI48 selection as system clock */
<> 134:ad3be0349dc5 248 #endif /* RCC_CFGR_SW_HSI48 */
<> 134:ad3be0349dc5 249 /**
<> 134:ad3be0349dc5 250 * @}
<> 134:ad3be0349dc5 251 */
<> 134:ad3be0349dc5 252
<> 134:ad3be0349dc5 253 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
<> 134:ad3be0349dc5 254 * @{
<> 134:ad3be0349dc5 255 */
<> 134:ad3be0349dc5 256 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
<> 134:ad3be0349dc5 257 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
<> 134:ad3be0349dc5 258 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
<> 134:ad3be0349dc5 259 #if defined(RCC_CFGR_SWS_HSI48)
<> 134:ad3be0349dc5 260 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48 /*!< HSI48 used as system clock */
<> 134:ad3be0349dc5 261 #endif /* RCC_CFGR_SWS_HSI48 */
<> 134:ad3be0349dc5 262 /**
<> 134:ad3be0349dc5 263 * @}
<> 134:ad3be0349dc5 264 */
<> 134:ad3be0349dc5 265
<> 134:ad3be0349dc5 266 /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
<> 134:ad3be0349dc5 267 * @{
<> 134:ad3be0349dc5 268 */
<> 134:ad3be0349dc5 269 #define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
<> 134:ad3be0349dc5 270 #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
<> 134:ad3be0349dc5 271 #define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
<> 134:ad3be0349dc5 272 #define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
<> 134:ad3be0349dc5 273 #define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
<> 134:ad3be0349dc5 274 #define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
<> 134:ad3be0349dc5 275 #define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
<> 134:ad3be0349dc5 276 #define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
<> 134:ad3be0349dc5 277 #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
<> 134:ad3be0349dc5 278 /**
<> 134:ad3be0349dc5 279 * @}
<> 134:ad3be0349dc5 280 */
<> 134:ad3be0349dc5 281
<> 134:ad3be0349dc5 282 /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
<> 134:ad3be0349dc5 283 * @{
<> 134:ad3be0349dc5 284 */
<> 134:ad3be0349dc5 285 #define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE_DIV1 /*!< HCLK not divided */
<> 134:ad3be0349dc5 286 #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE_DIV2 /*!< HCLK divided by 2 */
<> 134:ad3be0349dc5 287 #define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE_DIV4 /*!< HCLK divided by 4 */
<> 134:ad3be0349dc5 288 #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE_DIV8 /*!< HCLK divided by 8 */
<> 134:ad3be0349dc5 289 #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE_DIV16 /*!< HCLK divided by 16 */
<> 134:ad3be0349dc5 290 /**
<> 134:ad3be0349dc5 291 * @}
<> 134:ad3be0349dc5 292 */
<> 134:ad3be0349dc5 293
<> 134:ad3be0349dc5 294 /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
<> 134:ad3be0349dc5 295 * @{
<> 134:ad3be0349dc5 296 */
<> 134:ad3be0349dc5 297 #define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK /*!< MCO output disabled, no clock on MCO */
<> 134:ad3be0349dc5 298 #define LL_RCC_MCO1SOURCE_HSI14 RCC_CFGR_MCOSEL_HSI14 /*!< HSI14 oscillator clock selected */
<> 134:ad3be0349dc5 299 #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK /*!< SYSCLK selection as MCO source */
<> 134:ad3be0349dc5 300 #define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI /*!< HSI selection as MCO source */
<> 134:ad3be0349dc5 301 #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE /*!< HSE selection as MCO source */
<> 134:ad3be0349dc5 302 #define LL_RCC_MCO1SOURCE_LSI RCC_CFGR_MCOSEL_LSI /*!< LSI selection as MCO source */
<> 134:ad3be0349dc5 303 #define LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_LSE /*!< LSE selection as MCO source */
<> 134:ad3be0349dc5 304 #if defined(RCC_CFGR_MCOSEL_HSI48)
<> 134:ad3be0349dc5 305 #define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_HSI48 /*!< HSI48 selection as MCO source */
<> 134:ad3be0349dc5 306 #endif /* RCC_CFGR_MCOSEL_HSI48 */
<> 134:ad3be0349dc5 307 #define LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 RCC_CFGR_MCOSEL_PLL_DIV2 /*!< PLL clock divided by 2*/
<> 134:ad3be0349dc5 308 #if defined(RCC_CFGR_PLLNODIV)
<> 134:ad3be0349dc5 309 #define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_PLL_DIV2 | RCC_CFGR_PLLNODIV) /*!< PLL clock selected*/
<> 134:ad3be0349dc5 310 #endif /* RCC_CFGR_PLLNODIV */
<> 134:ad3be0349dc5 311 /**
<> 134:ad3be0349dc5 312 * @}
<> 134:ad3be0349dc5 313 */
<> 134:ad3be0349dc5 314
<> 134:ad3be0349dc5 315 /** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler
<> 134:ad3be0349dc5 316 * @{
<> 134:ad3be0349dc5 317 */
<> 134:ad3be0349dc5 318 #define LL_RCC_MCO1_DIV_1 ((uint32_t)0x00000000U)/*!< MCO Clock divided by 1 */
<> 134:ad3be0349dc5 319 #if defined(RCC_CFGR_MCOPRE)
<> 134:ad3be0349dc5 320 #define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO Clock divided by 2 */
<> 134:ad3be0349dc5 321 #define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO Clock divided by 4 */
<> 134:ad3be0349dc5 322 #define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO Clock divided by 8 */
<> 134:ad3be0349dc5 323 #define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO Clock divided by 16 */
<> 134:ad3be0349dc5 324 #define LL_RCC_MCO1_DIV_32 RCC_CFGR_MCOPRE_DIV32 /*!< MCO Clock divided by 32 */
<> 134:ad3be0349dc5 325 #define LL_RCC_MCO1_DIV_64 RCC_CFGR_MCOPRE_DIV64 /*!< MCO Clock divided by 64 */
<> 134:ad3be0349dc5 326 #define LL_RCC_MCO1_DIV_128 RCC_CFGR_MCOPRE_DIV128 /*!< MCO Clock divided by 128 */
<> 134:ad3be0349dc5 327 #endif /* RCC_CFGR_MCOPRE */
<> 134:ad3be0349dc5 328 /**
<> 134:ad3be0349dc5 329 * @}
<> 134:ad3be0349dc5 330 */
<> 134:ad3be0349dc5 331
<> 134:ad3be0349dc5 332 #if defined(USE_FULL_LL_DRIVER)
<> 134:ad3be0349dc5 333 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
<> 134:ad3be0349dc5 334 * @{
<> 134:ad3be0349dc5 335 */
<> 134:ad3be0349dc5 336 #define LL_RCC_PERIPH_FREQUENCY_NO (uint32_t)0x00000000U /*!< No clock enabled for the peripheral */
<> 134:ad3be0349dc5 337 #define LL_RCC_PERIPH_FREQUENCY_NA (uint32_t)0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
<> 134:ad3be0349dc5 338 /**
<> 134:ad3be0349dc5 339 * @}
<> 134:ad3be0349dc5 340 */
<> 134:ad3be0349dc5 341 #endif /* USE_FULL_LL_DRIVER */
<> 134:ad3be0349dc5 342
<> 134:ad3be0349dc5 343 /** @defgroup RCC_LL_EC_USART1_CLKSOURCE Peripheral USART clock source selection
<> 134:ad3be0349dc5 344 * @{
<> 134:ad3be0349dc5 345 */
<> 134:ad3be0349dc5 346 #define LL_RCC_USART1_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART1SW << 24) | RCC_CFGR3_USART1SW_PCLK) /*!< PCLK1 clock used as USART1 clock source */
<> 134:ad3be0349dc5 347 #define LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART1SW << 24) | RCC_CFGR3_USART1SW_SYSCLK) /*!< System clock selected as USART1 clock source */
<> 134:ad3be0349dc5 348 #define LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART1SW << 24) | RCC_CFGR3_USART1SW_LSE) /*!< LSE oscillator clock used as USART1 clock source */
<> 134:ad3be0349dc5 349 #define LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART1SW << 24) | RCC_CFGR3_USART1SW_HSI) /*!< HSI oscillator clock used as USART1 clock source */
<> 134:ad3be0349dc5 350 #if defined(RCC_CFGR3_USART2SW)
<> 134:ad3be0349dc5 351 #define LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART2SW << 24) | RCC_CFGR3_USART2SW_PCLK) /*!< PCLK1 clock used as USART2 clock source */
<> 134:ad3be0349dc5 352 #define LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART2SW << 24) | RCC_CFGR3_USART2SW_SYSCLK) /*!< System clock selected as USART2 clock source */
<> 134:ad3be0349dc5 353 #define LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART2SW << 24) | RCC_CFGR3_USART2SW_LSE) /*!< LSE oscillator clock used as USART2 clock source */
<> 134:ad3be0349dc5 354 #define LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART2SW << 24) | RCC_CFGR3_USART2SW_HSI) /*!< HSI oscillator clock used as USART2 clock source */
<> 134:ad3be0349dc5 355 #endif /* RCC_CFGR3_USART2SW */
<> 134:ad3be0349dc5 356 #if defined(RCC_CFGR3_USART3SW)
<> 134:ad3be0349dc5 357 #define LL_RCC_USART3_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART3SW << 24) | RCC_CFGR3_USART3SW_PCLK) /*!< PCLK1 clock used as USART3 clock source */
<> 134:ad3be0349dc5 358 #define LL_RCC_USART3_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART3SW << 24) | RCC_CFGR3_USART3SW_SYSCLK) /*!< System clock selected as USART3 clock source */
<> 134:ad3be0349dc5 359 #define LL_RCC_USART3_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART3SW << 24) | RCC_CFGR3_USART3SW_LSE) /*!< LSE oscillator clock used as USART3 clock source */
<> 134:ad3be0349dc5 360 #define LL_RCC_USART3_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART3SW << 24) | RCC_CFGR3_USART3SW_HSI) /*!< HSI oscillator clock used as USART3 clock source */
<> 134:ad3be0349dc5 361 #endif /* RCC_CFGR3_USART3SW */
<> 134:ad3be0349dc5 362 /**
<> 134:ad3be0349dc5 363 * @}
<> 134:ad3be0349dc5 364 */
<> 134:ad3be0349dc5 365
<> 134:ad3be0349dc5 366 /** @defgroup RCC_LL_EC_I2C1_CLKSOURCE Peripheral I2C clock source selection
<> 134:ad3be0349dc5 367 * @{
<> 134:ad3be0349dc5 368 */
<> 134:ad3be0349dc5 369 #define LL_RCC_I2C1_CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI /*!< HSI oscillator clock used as I2C1 clock source */
<> 134:ad3be0349dc5 370 #define LL_RCC_I2C1_CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK /*!< System clock selected as I2C1 clock source */
<> 134:ad3be0349dc5 371 /**
<> 134:ad3be0349dc5 372 * @}
<> 134:ad3be0349dc5 373 */
<> 134:ad3be0349dc5 374
<> 134:ad3be0349dc5 375 #if defined(CEC)
<> 134:ad3be0349dc5 376 /** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection
<> 134:ad3be0349dc5 377 * @{
<> 134:ad3be0349dc5 378 */
<> 134:ad3be0349dc5 379 #define LL_RCC_CEC_CLKSOURCE_HSI_DIV244 RCC_CFGR3_CECSW_HSI_DIV244 /*!< HSI clock divided by 244 selected as HDMI CEC entry clock source */
<> 134:ad3be0349dc5 380 #define LL_RCC_CEC_CLKSOURCE_LSE RCC_CFGR3_CECSW_LSE /*!< LSE clock selected as HDMI CEC entry clock source */
<> 134:ad3be0349dc5 381 /**
<> 134:ad3be0349dc5 382 * @}
<> 134:ad3be0349dc5 383 */
<> 134:ad3be0349dc5 384
<> 134:ad3be0349dc5 385 #endif /* CEC */
<> 134:ad3be0349dc5 386
<> 134:ad3be0349dc5 387 #if defined(USB)
<> 134:ad3be0349dc5 388 /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
<> 134:ad3be0349dc5 389 * @{
<> 134:ad3be0349dc5 390 */
<> 134:ad3be0349dc5 391 #if defined(RCC_CFGR3_USBSW_HSI48)
<> 134:ad3be0349dc5 392 #define LL_RCC_USB_CLKSOURCE_HSI48 RCC_CFGR3_USBSW_HSI48 /*!< HSI48 oscillator clock used as USB clock source */
<> 134:ad3be0349dc5 393 #else
<> 134:ad3be0349dc5 394 #define LL_RCC_USB_CLKSOURCE_NONE ((uint32_t)0x00000000) /*!< USB Clock disabled */
<> 134:ad3be0349dc5 395 #endif /*RCC_CFGR3_USBSW_HSI48*/
<> 134:ad3be0349dc5 396 #define LL_RCC_USB_CLKSOURCE_PLL RCC_CFGR3_USBSW_PLLCLK /*!< PLL selected as USB clock source */
<> 134:ad3be0349dc5 397 /**
<> 134:ad3be0349dc5 398 * @}
<> 134:ad3be0349dc5 399 */
<> 134:ad3be0349dc5 400
<> 134:ad3be0349dc5 401 #endif /* USB */
<> 134:ad3be0349dc5 402
<> 134:ad3be0349dc5 403 /** @defgroup RCC_LL_EC_USART1 Peripheral USART get clock source
<> 134:ad3be0349dc5 404 * @{
<> 134:ad3be0349dc5 405 */
<> 134:ad3be0349dc5 406 #define LL_RCC_USART1_CLKSOURCE RCC_POSITION_USART1SW /*!< USART1 Clock source selection */
<> 134:ad3be0349dc5 407 #if defined(RCC_CFGR3_USART2SW)
<> 134:ad3be0349dc5 408 #define LL_RCC_USART2_CLKSOURCE RCC_POSITION_USART2SW /*!< USART2 Clock source selection */
<> 134:ad3be0349dc5 409 #endif /* RCC_CFGR3_USART2SW */
<> 134:ad3be0349dc5 410 #if defined(RCC_CFGR3_USART3SW)
<> 134:ad3be0349dc5 411 #define LL_RCC_USART3_CLKSOURCE RCC_POSITION_USART3SW /*!< USART3 Clock source selection */
<> 134:ad3be0349dc5 412 #endif /* RCC_CFGR3_USART3SW */
<> 134:ad3be0349dc5 413 /**
<> 134:ad3be0349dc5 414 * @}
<> 134:ad3be0349dc5 415 */
<> 134:ad3be0349dc5 416
<> 134:ad3be0349dc5 417 /** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source
<> 134:ad3be0349dc5 418 * @{
<> 134:ad3be0349dc5 419 */
<> 134:ad3be0349dc5 420 #define LL_RCC_I2C1_CLKSOURCE RCC_CFGR3_I2C1SW /*!< I2C1 Clock source selection */
<> 134:ad3be0349dc5 421 /**
<> 134:ad3be0349dc5 422 * @}
<> 134:ad3be0349dc5 423 */
<> 134:ad3be0349dc5 424
<> 134:ad3be0349dc5 425 #if defined(CEC)
<> 134:ad3be0349dc5 426 /** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source
<> 134:ad3be0349dc5 427 * @{
<> 134:ad3be0349dc5 428 */
<> 134:ad3be0349dc5 429 #define LL_RCC_CEC_CLKSOURCE RCC_CFGR3_CECSW /*!< CEC Clock source selection */
<> 134:ad3be0349dc5 430 /**
<> 134:ad3be0349dc5 431 * @}
<> 134:ad3be0349dc5 432 */
<> 134:ad3be0349dc5 433 #endif /* CEC */
<> 134:ad3be0349dc5 434
<> 134:ad3be0349dc5 435 #if defined(USB)
<> 134:ad3be0349dc5 436 /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
<> 134:ad3be0349dc5 437 * @{
<> 134:ad3be0349dc5 438 */
<> 134:ad3be0349dc5 439 #define LL_RCC_USB_CLKSOURCE RCC_CFGR3_USBSW /*!< USB Clock source selection */
<> 134:ad3be0349dc5 440 /**
<> 134:ad3be0349dc5 441 * @}
<> 134:ad3be0349dc5 442 */
<> 134:ad3be0349dc5 443 #endif /* USB */
<> 134:ad3be0349dc5 444
<> 134:ad3be0349dc5 445 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
<> 134:ad3be0349dc5 446 * @{
<> 134:ad3be0349dc5 447 */
<> 134:ad3be0349dc5 448 #define LL_RCC_RTC_CLKSOURCE_NONE (uint32_t)0x00000000U /*!< No clock used as RTC clock */
<> 134:ad3be0349dc5 449 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
<> 134:ad3be0349dc5 450 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
<> 134:ad3be0349dc5 451 #define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */
<> 134:ad3be0349dc5 452 /**
<> 134:ad3be0349dc5 453 * @}
<> 134:ad3be0349dc5 454 */
<> 134:ad3be0349dc5 455
<> 134:ad3be0349dc5 456 /** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor
<> 134:ad3be0349dc5 457 * @{
<> 134:ad3be0349dc5 458 */
<> 134:ad3be0349dc5 459 #define LL_RCC_PLL_MUL_2 RCC_CFGR_PLLMUL2 /*!< PLL input clock*2 */
<> 134:ad3be0349dc5 460 #define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMUL3 /*!< PLL input clock*3 */
<> 134:ad3be0349dc5 461 #define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMUL4 /*!< PLL input clock*4 */
<> 134:ad3be0349dc5 462 #define LL_RCC_PLL_MUL_5 RCC_CFGR_PLLMUL5 /*!< PLL input clock*5 */
<> 134:ad3be0349dc5 463 #define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMUL6 /*!< PLL input clock*6 */
<> 134:ad3be0349dc5 464 #define LL_RCC_PLL_MUL_7 RCC_CFGR_PLLMUL7 /*!< PLL input clock*7 */
<> 134:ad3be0349dc5 465 #define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMUL8 /*!< PLL input clock*8 */
<> 134:ad3be0349dc5 466 #define LL_RCC_PLL_MUL_9 RCC_CFGR_PLLMUL9 /*!< PLL input clock*9 */
<> 134:ad3be0349dc5 467 #define LL_RCC_PLL_MUL_10 RCC_CFGR_PLLMUL10 /*!< PLL input clock*10 */
<> 134:ad3be0349dc5 468 #define LL_RCC_PLL_MUL_11 RCC_CFGR_PLLMUL11 /*!< PLL input clock*11 */
<> 134:ad3be0349dc5 469 #define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMUL12 /*!< PLL input clock*12 */
<> 134:ad3be0349dc5 470 #define LL_RCC_PLL_MUL_13 RCC_CFGR_PLLMUL13 /*!< PLL input clock*13 */
<> 134:ad3be0349dc5 471 #define LL_RCC_PLL_MUL_14 RCC_CFGR_PLLMUL14 /*!< PLL input clock*14 */
<> 134:ad3be0349dc5 472 #define LL_RCC_PLL_MUL_15 RCC_CFGR_PLLMUL15 /*!< PLL input clock*15 */
<> 134:ad3be0349dc5 473 #define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMUL16 /*!< PLL input clock*16 */
<> 134:ad3be0349dc5 474 /**
<> 134:ad3be0349dc5 475 * @}
<> 134:ad3be0349dc5 476 */
<> 134:ad3be0349dc5 477
<> 134:ad3be0349dc5 478 /** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE
<> 134:ad3be0349dc5 479 * @{
<> 134:ad3be0349dc5 480 */
<> 134:ad3be0349dc5 481 #define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< HSE/PREDIV clock selected as PLL entry clock source */
<> 134:ad3be0349dc5 482 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
<> 134:ad3be0349dc5 483 #define LL_RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV /*!< HSI/PREDIV clock selected as PLL entry clock source */
<> 134:ad3be0349dc5 484 #if defined(RCC_CFGR_SW_HSI48)
<> 134:ad3be0349dc5 485 #define LL_RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV /*!< HSI48/PREDIV clock selected as PLL entry clock source */
<> 134:ad3be0349dc5 486 #endif /* RCC_CFGR_SW_HSI48 */
<> 134:ad3be0349dc5 487 #else
<> 134:ad3be0349dc5 488 #define LL_RCC_PLLSOURCE_HSI_DIV_2 RCC_CFGR_PLLSRC_HSI_DIV2 /*!< HSI clock divided by 2 selected as PLL entry clock source */
<> 134:ad3be0349dc5 489 #define LL_RCC_PLLSOURCE_HSE_DIV_1 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV1) /*!< HSE clock selected as PLL entry clock source */
<> 134:ad3be0349dc5 490 #define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV2) /*!< HSE/2 clock selected as PLL entry clock source */
<> 134:ad3be0349dc5 491 #define LL_RCC_PLLSOURCE_HSE_DIV_3 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV3) /*!< HSE/3 clock selected as PLL entry clock source */
<> 134:ad3be0349dc5 492 #define LL_RCC_PLLSOURCE_HSE_DIV_4 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV4) /*!< HSE/4 clock selected as PLL entry clock source */
<> 134:ad3be0349dc5 493 #define LL_RCC_PLLSOURCE_HSE_DIV_5 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV5) /*!< HSE/5 clock selected as PLL entry clock source */
<> 134:ad3be0349dc5 494 #define LL_RCC_PLLSOURCE_HSE_DIV_6 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV6) /*!< HSE/6 clock selected as PLL entry clock source */
<> 134:ad3be0349dc5 495 #define LL_RCC_PLLSOURCE_HSE_DIV_7 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV7) /*!< HSE/7 clock selected as PLL entry clock source */
<> 134:ad3be0349dc5 496 #define LL_RCC_PLLSOURCE_HSE_DIV_8 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV8) /*!< HSE/8 clock selected as PLL entry clock source */
<> 134:ad3be0349dc5 497 #define LL_RCC_PLLSOURCE_HSE_DIV_9 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV9) /*!< HSE/9 clock selected as PLL entry clock source */
<> 134:ad3be0349dc5 498 #define LL_RCC_PLLSOURCE_HSE_DIV_10 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV10) /*!< HSE/10 clock selected as PLL entry clock source */
<> 134:ad3be0349dc5 499 #define LL_RCC_PLLSOURCE_HSE_DIV_11 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV11) /*!< HSE/11 clock selected as PLL entry clock source */
<> 134:ad3be0349dc5 500 #define LL_RCC_PLLSOURCE_HSE_DIV_12 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV12) /*!< HSE/12 clock selected as PLL entry clock source */
<> 134:ad3be0349dc5 501 #define LL_RCC_PLLSOURCE_HSE_DIV_13 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV13) /*!< HSE/13 clock selected as PLL entry clock source */
<> 134:ad3be0349dc5 502 #define LL_RCC_PLLSOURCE_HSE_DIV_14 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV14) /*!< HSE/14 clock selected as PLL entry clock source */
<> 134:ad3be0349dc5 503 #define LL_RCC_PLLSOURCE_HSE_DIV_15 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV15) /*!< HSE/15 clock selected as PLL entry clock source */
<> 134:ad3be0349dc5 504 #define LL_RCC_PLLSOURCE_HSE_DIV_16 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV16) /*!< HSE/16 clock selected as PLL entry clock source */
<> 134:ad3be0349dc5 505 #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
<> 134:ad3be0349dc5 506 /**
<> 134:ad3be0349dc5 507 * @}
<> 134:ad3be0349dc5 508 */
<> 134:ad3be0349dc5 509
<> 134:ad3be0349dc5 510 /** @defgroup RCC_LL_EC_PREDIV_DIV PREDIV Division factor
<> 134:ad3be0349dc5 511 * @{
<> 134:ad3be0349dc5 512 */
<> 134:ad3be0349dc5 513 #define LL_RCC_PREDIV_DIV_1 RCC_CFGR2_PREDIV_DIV1 /*!< PREDIV input clock not divided */
<> 134:ad3be0349dc5 514 #define LL_RCC_PREDIV_DIV_2 RCC_CFGR2_PREDIV_DIV2 /*!< PREDIV input clock divided by 2 */
<> 134:ad3be0349dc5 515 #define LL_RCC_PREDIV_DIV_3 RCC_CFGR2_PREDIV_DIV3 /*!< PREDIV input clock divided by 3 */
<> 134:ad3be0349dc5 516 #define LL_RCC_PREDIV_DIV_4 RCC_CFGR2_PREDIV_DIV4 /*!< PREDIV input clock divided by 4 */
<> 134:ad3be0349dc5 517 #define LL_RCC_PREDIV_DIV_5 RCC_CFGR2_PREDIV_DIV5 /*!< PREDIV input clock divided by 5 */
<> 134:ad3be0349dc5 518 #define LL_RCC_PREDIV_DIV_6 RCC_CFGR2_PREDIV_DIV6 /*!< PREDIV input clock divided by 6 */
<> 134:ad3be0349dc5 519 #define LL_RCC_PREDIV_DIV_7 RCC_CFGR2_PREDIV_DIV7 /*!< PREDIV input clock divided by 7 */
<> 134:ad3be0349dc5 520 #define LL_RCC_PREDIV_DIV_8 RCC_CFGR2_PREDIV_DIV8 /*!< PREDIV input clock divided by 8 */
<> 134:ad3be0349dc5 521 #define LL_RCC_PREDIV_DIV_9 RCC_CFGR2_PREDIV_DIV9 /*!< PREDIV input clock divided by 9 */
<> 134:ad3be0349dc5 522 #define LL_RCC_PREDIV_DIV_10 RCC_CFGR2_PREDIV_DIV10 /*!< PREDIV input clock divided by 10 */
<> 134:ad3be0349dc5 523 #define LL_RCC_PREDIV_DIV_11 RCC_CFGR2_PREDIV_DIV11 /*!< PREDIV input clock divided by 11 */
<> 134:ad3be0349dc5 524 #define LL_RCC_PREDIV_DIV_12 RCC_CFGR2_PREDIV_DIV12 /*!< PREDIV input clock divided by 12 */
<> 134:ad3be0349dc5 525 #define LL_RCC_PREDIV_DIV_13 RCC_CFGR2_PREDIV_DIV13 /*!< PREDIV input clock divided by 13 */
<> 134:ad3be0349dc5 526 #define LL_RCC_PREDIV_DIV_14 RCC_CFGR2_PREDIV_DIV14 /*!< PREDIV input clock divided by 14 */
<> 134:ad3be0349dc5 527 #define LL_RCC_PREDIV_DIV_15 RCC_CFGR2_PREDIV_DIV15 /*!< PREDIV input clock divided by 15 */
<> 134:ad3be0349dc5 528 #define LL_RCC_PREDIV_DIV_16 RCC_CFGR2_PREDIV_DIV16 /*!< PREDIV input clock divided by 16 */
<> 134:ad3be0349dc5 529 /**
<> 134:ad3be0349dc5 530 * @}
<> 134:ad3be0349dc5 531 */
<> 134:ad3be0349dc5 532
<> 134:ad3be0349dc5 533 /**
<> 134:ad3be0349dc5 534 * @}
<> 134:ad3be0349dc5 535 */
<> 134:ad3be0349dc5 536
<> 134:ad3be0349dc5 537 /* Exported macro ------------------------------------------------------------*/
<> 134:ad3be0349dc5 538 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
<> 134:ad3be0349dc5 539 * @{
<> 134:ad3be0349dc5 540 */
<> 134:ad3be0349dc5 541
<> 134:ad3be0349dc5 542 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
<> 134:ad3be0349dc5 543 * @{
<> 134:ad3be0349dc5 544 */
<> 134:ad3be0349dc5 545
<> 134:ad3be0349dc5 546 /**
<> 134:ad3be0349dc5 547 * @brief Write a value in RCC register
<> 134:ad3be0349dc5 548 * @param __REG__ Register to be written
<> 134:ad3be0349dc5 549 * @param __VALUE__ Value to be written in the register
<> 134:ad3be0349dc5 550 * @retval None
<> 134:ad3be0349dc5 551 */
<> 134:ad3be0349dc5 552 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
<> 134:ad3be0349dc5 553
<> 134:ad3be0349dc5 554 /**
<> 134:ad3be0349dc5 555 * @brief Read a value in RCC register
<> 134:ad3be0349dc5 556 * @param __REG__ Register to be read
<> 134:ad3be0349dc5 557 * @retval Register value
<> 134:ad3be0349dc5 558 */
<> 134:ad3be0349dc5 559 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
<> 134:ad3be0349dc5 560 /**
<> 134:ad3be0349dc5 561 * @}
<> 134:ad3be0349dc5 562 */
<> 134:ad3be0349dc5 563
<> 134:ad3be0349dc5 564 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
<> 134:ad3be0349dc5 565 * @{
<> 134:ad3be0349dc5 566 */
<> 134:ad3be0349dc5 567
<> 134:ad3be0349dc5 568 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
<> 134:ad3be0349dc5 569 /**
<> 134:ad3be0349dc5 570 * @brief Helper macro to calculate the PLLCLK frequency
<> 134:ad3be0349dc5 571 * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetMultiplicator()
<> 134:ad3be0349dc5 572 * , @ref LL_RCC_PLL_GetPrediv());
<> 134:ad3be0349dc5 573 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI/HSI48)
<> 134:ad3be0349dc5 574 * @param __PLLMUL__: This parameter can be one of the following values:
<> 134:ad3be0349dc5 575 * @arg @ref LL_RCC_PLL_MUL_2
<> 134:ad3be0349dc5 576 * @arg @ref LL_RCC_PLL_MUL_3
<> 134:ad3be0349dc5 577 * @arg @ref LL_RCC_PLL_MUL_4
<> 134:ad3be0349dc5 578 * @arg @ref LL_RCC_PLL_MUL_5
<> 134:ad3be0349dc5 579 * @arg @ref LL_RCC_PLL_MUL_6
<> 134:ad3be0349dc5 580 * @arg @ref LL_RCC_PLL_MUL_7
<> 134:ad3be0349dc5 581 * @arg @ref LL_RCC_PLL_MUL_8
<> 134:ad3be0349dc5 582 * @arg @ref LL_RCC_PLL_MUL_9
<> 134:ad3be0349dc5 583 * @arg @ref LL_RCC_PLL_MUL_10
<> 134:ad3be0349dc5 584 * @arg @ref LL_RCC_PLL_MUL_11
<> 134:ad3be0349dc5 585 * @arg @ref LL_RCC_PLL_MUL_12
<> 134:ad3be0349dc5 586 * @arg @ref LL_RCC_PLL_MUL_13
<> 134:ad3be0349dc5 587 * @arg @ref LL_RCC_PLL_MUL_14
<> 134:ad3be0349dc5 588 * @arg @ref LL_RCC_PLL_MUL_15
<> 134:ad3be0349dc5 589 * @arg @ref LL_RCC_PLL_MUL_16
<> 134:ad3be0349dc5 590 * @param __PLLPREDIV__: This parameter can be one of the following values:
<> 134:ad3be0349dc5 591 * @arg @ref LL_RCC_PREDIV_DIV_1
<> 134:ad3be0349dc5 592 * @arg @ref LL_RCC_PREDIV_DIV_2
<> 134:ad3be0349dc5 593 * @arg @ref LL_RCC_PREDIV_DIV_3
<> 134:ad3be0349dc5 594 * @arg @ref LL_RCC_PREDIV_DIV_4
<> 134:ad3be0349dc5 595 * @arg @ref LL_RCC_PREDIV_DIV_5
<> 134:ad3be0349dc5 596 * @arg @ref LL_RCC_PREDIV_DIV_6
<> 134:ad3be0349dc5 597 * @arg @ref LL_RCC_PREDIV_DIV_7
<> 134:ad3be0349dc5 598 * @arg @ref LL_RCC_PREDIV_DIV_8
<> 134:ad3be0349dc5 599 * @arg @ref LL_RCC_PREDIV_DIV_9
<> 134:ad3be0349dc5 600 * @arg @ref LL_RCC_PREDIV_DIV_10
<> 134:ad3be0349dc5 601 * @arg @ref LL_RCC_PREDIV_DIV_11
<> 134:ad3be0349dc5 602 * @arg @ref LL_RCC_PREDIV_DIV_12
<> 134:ad3be0349dc5 603 * @arg @ref LL_RCC_PREDIV_DIV_13
<> 134:ad3be0349dc5 604 * @arg @ref LL_RCC_PREDIV_DIV_14
<> 134:ad3be0349dc5 605 * @arg @ref LL_RCC_PREDIV_DIV_15
<> 134:ad3be0349dc5 606 * @arg @ref LL_RCC_PREDIV_DIV_16
<> 134:ad3be0349dc5 607 * @retval PLL clock frequency (in Hz)
<> 134:ad3be0349dc5 608 */
<> 134:ad3be0349dc5 609 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__, __PLLPREDIV__) \
<> 134:ad3be0349dc5 610 (((__INPUTFREQ__) / ((((__PLLPREDIV__) & RCC_CFGR2_PREDIV) + 1U))) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U))
<> 134:ad3be0349dc5 611
<> 134:ad3be0349dc5 612 #else
<> 134:ad3be0349dc5 613 /**
<> 134:ad3be0349dc5 614 * @brief Helper macro to calculate the PLLCLK frequency
<> 134:ad3be0349dc5 615 * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator());
<> 134:ad3be0349dc5 616 * @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv / HSI div 2)
<> 134:ad3be0349dc5 617 * @param __PLLMUL__: This parameter can be one of the following values:
<> 134:ad3be0349dc5 618 * @arg @ref LL_RCC_PLL_MUL_2
<> 134:ad3be0349dc5 619 * @arg @ref LL_RCC_PLL_MUL_3
<> 134:ad3be0349dc5 620 * @arg @ref LL_RCC_PLL_MUL_4
<> 134:ad3be0349dc5 621 * @arg @ref LL_RCC_PLL_MUL_5
<> 134:ad3be0349dc5 622 * @arg @ref LL_RCC_PLL_MUL_6
<> 134:ad3be0349dc5 623 * @arg @ref LL_RCC_PLL_MUL_7
<> 134:ad3be0349dc5 624 * @arg @ref LL_RCC_PLL_MUL_8
<> 134:ad3be0349dc5 625 * @arg @ref LL_RCC_PLL_MUL_9
<> 134:ad3be0349dc5 626 * @arg @ref LL_RCC_PLL_MUL_10
<> 134:ad3be0349dc5 627 * @arg @ref LL_RCC_PLL_MUL_11
<> 134:ad3be0349dc5 628 * @arg @ref LL_RCC_PLL_MUL_12
<> 134:ad3be0349dc5 629 * @arg @ref LL_RCC_PLL_MUL_13
<> 134:ad3be0349dc5 630 * @arg @ref LL_RCC_PLL_MUL_14
<> 134:ad3be0349dc5 631 * @arg @ref LL_RCC_PLL_MUL_15
<> 134:ad3be0349dc5 632 * @arg @ref LL_RCC_PLL_MUL_16
<> 134:ad3be0349dc5 633 * @retval PLL clock frequency (in Hz)
<> 134:ad3be0349dc5 634 */
<> 134:ad3be0349dc5 635 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) \
<> 134:ad3be0349dc5 636 ((__INPUTFREQ__) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U))
<> 134:ad3be0349dc5 637 #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
<> 134:ad3be0349dc5 638 /**
<> 134:ad3be0349dc5 639 * @brief Helper macro to calculate the HCLK frequency
<> 134:ad3be0349dc5 640 * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler
<> 134:ad3be0349dc5 641 * ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler())
<> 134:ad3be0349dc5 642 * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
<> 134:ad3be0349dc5 643 * @param __AHBPRESCALER__: This parameter can be one of the following values:
<> 134:ad3be0349dc5 644 * @arg @ref LL_RCC_SYSCLK_DIV_1
<> 134:ad3be0349dc5 645 * @arg @ref LL_RCC_SYSCLK_DIV_2
<> 134:ad3be0349dc5 646 * @arg @ref LL_RCC_SYSCLK_DIV_4
<> 134:ad3be0349dc5 647 * @arg @ref LL_RCC_SYSCLK_DIV_8
<> 134:ad3be0349dc5 648 * @arg @ref LL_RCC_SYSCLK_DIV_16
<> 134:ad3be0349dc5 649 * @arg @ref LL_RCC_SYSCLK_DIV_64
<> 134:ad3be0349dc5 650 * @arg @ref LL_RCC_SYSCLK_DIV_128
<> 134:ad3be0349dc5 651 * @arg @ref LL_RCC_SYSCLK_DIV_256
<> 134:ad3be0349dc5 652 * @arg @ref LL_RCC_SYSCLK_DIV_512
<> 134:ad3be0349dc5 653 * @retval HCLK clock frequency (in Hz)
<> 134:ad3be0349dc5 654 */
<> 134:ad3be0349dc5 655 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_POSITION_HPRE])
<> 134:ad3be0349dc5 656
<> 134:ad3be0349dc5 657 /**
<> 134:ad3be0349dc5 658 * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
<> 134:ad3be0349dc5 659 * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler
<> 134:ad3be0349dc5 660 * ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler())
<> 134:ad3be0349dc5 661 * @param __HCLKFREQ__ HCLK frequency
<> 134:ad3be0349dc5 662 * @param __APB1PRESCALER__: This parameter can be one of the following values:
<> 134:ad3be0349dc5 663 * @arg @ref LL_RCC_APB1_DIV_1
<> 134:ad3be0349dc5 664 * @arg @ref LL_RCC_APB1_DIV_2
<> 134:ad3be0349dc5 665 * @arg @ref LL_RCC_APB1_DIV_4
<> 134:ad3be0349dc5 666 * @arg @ref LL_RCC_APB1_DIV_8
<> 134:ad3be0349dc5 667 * @arg @ref LL_RCC_APB1_DIV_16
<> 134:ad3be0349dc5 668 * @retval PCLK1 clock frequency (in Hz)
<> 134:ad3be0349dc5 669 */
<> 134:ad3be0349dc5 670 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_POSITION_PPRE1])
<> 134:ad3be0349dc5 671
<> 134:ad3be0349dc5 672 /**
<> 134:ad3be0349dc5 673 * @}
<> 134:ad3be0349dc5 674 */
<> 134:ad3be0349dc5 675
<> 134:ad3be0349dc5 676 /**
<> 134:ad3be0349dc5 677 * @}
<> 134:ad3be0349dc5 678 */
<> 134:ad3be0349dc5 679
<> 134:ad3be0349dc5 680 /* Exported functions --------------------------------------------------------*/
<> 134:ad3be0349dc5 681 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
<> 134:ad3be0349dc5 682 * @{
<> 134:ad3be0349dc5 683 */
<> 134:ad3be0349dc5 684
<> 134:ad3be0349dc5 685 /** @defgroup RCC_LL_EF_HSE HSE
<> 134:ad3be0349dc5 686 * @{
<> 134:ad3be0349dc5 687 */
<> 134:ad3be0349dc5 688
<> 134:ad3be0349dc5 689 /**
<> 134:ad3be0349dc5 690 * @brief Enable the Clock Security System.
<> 134:ad3be0349dc5 691 * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
<> 134:ad3be0349dc5 692 * @retval None
<> 134:ad3be0349dc5 693 */
<> 134:ad3be0349dc5 694 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
<> 134:ad3be0349dc5 695 {
<> 134:ad3be0349dc5 696 SET_BIT(RCC->CR, RCC_CR_CSSON);
<> 134:ad3be0349dc5 697 }
<> 134:ad3be0349dc5 698
<> 134:ad3be0349dc5 699 /**
<> 134:ad3be0349dc5 700 * @brief Disable the Clock Security System.
<> 134:ad3be0349dc5 701 * @note Cannot be disabled in HSE is ready (only by hardware)
<> 134:ad3be0349dc5 702 * @rmtoll CR CSSON LL_RCC_HSE_DisableCSS
<> 134:ad3be0349dc5 703 * @retval None
<> 134:ad3be0349dc5 704 */
<> 134:ad3be0349dc5 705 __STATIC_INLINE void LL_RCC_HSE_DisableCSS(void)
<> 134:ad3be0349dc5 706 {
<> 134:ad3be0349dc5 707 CLEAR_BIT(RCC->CR, RCC_CR_CSSON);
<> 134:ad3be0349dc5 708 }
<> 134:ad3be0349dc5 709
<> 134:ad3be0349dc5 710 /**
<> 134:ad3be0349dc5 711 * @brief Enable HSE external oscillator (HSE Bypass)
<> 134:ad3be0349dc5 712 * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
<> 134:ad3be0349dc5 713 * @retval None
<> 134:ad3be0349dc5 714 */
<> 134:ad3be0349dc5 715 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
<> 134:ad3be0349dc5 716 {
<> 134:ad3be0349dc5 717 SET_BIT(RCC->CR, RCC_CR_HSEBYP);
<> 134:ad3be0349dc5 718 }
<> 134:ad3be0349dc5 719
<> 134:ad3be0349dc5 720 /**
<> 134:ad3be0349dc5 721 * @brief Disable HSE external oscillator (HSE Bypass)
<> 134:ad3be0349dc5 722 * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
<> 134:ad3be0349dc5 723 * @retval None
<> 134:ad3be0349dc5 724 */
<> 134:ad3be0349dc5 725 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
<> 134:ad3be0349dc5 726 {
<> 134:ad3be0349dc5 727 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
<> 134:ad3be0349dc5 728 }
<> 134:ad3be0349dc5 729
<> 134:ad3be0349dc5 730 /**
<> 134:ad3be0349dc5 731 * @brief Enable HSE crystal oscillator (HSE ON)
<> 134:ad3be0349dc5 732 * @rmtoll CR HSEON LL_RCC_HSE_Enable
<> 134:ad3be0349dc5 733 * @retval None
<> 134:ad3be0349dc5 734 */
<> 134:ad3be0349dc5 735 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
<> 134:ad3be0349dc5 736 {
<> 134:ad3be0349dc5 737 SET_BIT(RCC->CR, RCC_CR_HSEON);
<> 134:ad3be0349dc5 738 }
<> 134:ad3be0349dc5 739
<> 134:ad3be0349dc5 740 /**
<> 134:ad3be0349dc5 741 * @brief Disable HSE crystal oscillator (HSE ON)
<> 134:ad3be0349dc5 742 * @rmtoll CR HSEON LL_RCC_HSE_Disable
<> 134:ad3be0349dc5 743 * @retval None
<> 134:ad3be0349dc5 744 */
<> 134:ad3be0349dc5 745 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
<> 134:ad3be0349dc5 746 {
<> 134:ad3be0349dc5 747 CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
<> 134:ad3be0349dc5 748 }
<> 134:ad3be0349dc5 749
<> 134:ad3be0349dc5 750 /**
<> 134:ad3be0349dc5 751 * @brief Check if HSE oscillator Ready
<> 134:ad3be0349dc5 752 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
<> 134:ad3be0349dc5 753 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 754 */
<> 134:ad3be0349dc5 755 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
<> 134:ad3be0349dc5 756 {
<> 134:ad3be0349dc5 757 return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
<> 134:ad3be0349dc5 758 }
<> 134:ad3be0349dc5 759
<> 134:ad3be0349dc5 760 /**
<> 134:ad3be0349dc5 761 * @}
<> 134:ad3be0349dc5 762 */
<> 134:ad3be0349dc5 763
<> 134:ad3be0349dc5 764 /** @defgroup RCC_LL_EF_HSI HSI
<> 134:ad3be0349dc5 765 * @{
<> 134:ad3be0349dc5 766 */
<> 134:ad3be0349dc5 767
<> 134:ad3be0349dc5 768 /**
<> 134:ad3be0349dc5 769 * @brief Enable HSI oscillator
<> 134:ad3be0349dc5 770 * @rmtoll CR HSION LL_RCC_HSI_Enable
<> 134:ad3be0349dc5 771 * @retval None
<> 134:ad3be0349dc5 772 */
<> 134:ad3be0349dc5 773 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
<> 134:ad3be0349dc5 774 {
<> 134:ad3be0349dc5 775 SET_BIT(RCC->CR, RCC_CR_HSION);
<> 134:ad3be0349dc5 776 }
<> 134:ad3be0349dc5 777
<> 134:ad3be0349dc5 778 /**
<> 134:ad3be0349dc5 779 * @brief Disable HSI oscillator
<> 134:ad3be0349dc5 780 * @rmtoll CR HSION LL_RCC_HSI_Disable
<> 134:ad3be0349dc5 781 * @retval None
<> 134:ad3be0349dc5 782 */
<> 134:ad3be0349dc5 783 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
<> 134:ad3be0349dc5 784 {
<> 134:ad3be0349dc5 785 CLEAR_BIT(RCC->CR, RCC_CR_HSION);
<> 134:ad3be0349dc5 786 }
<> 134:ad3be0349dc5 787
<> 134:ad3be0349dc5 788 /**
<> 134:ad3be0349dc5 789 * @brief Check if HSI clock is ready
<> 134:ad3be0349dc5 790 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
<> 134:ad3be0349dc5 791 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 792 */
<> 134:ad3be0349dc5 793 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
<> 134:ad3be0349dc5 794 {
<> 134:ad3be0349dc5 795 return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
<> 134:ad3be0349dc5 796 }
<> 134:ad3be0349dc5 797
<> 134:ad3be0349dc5 798 /**
<> 134:ad3be0349dc5 799 * @brief Get HSI Calibration value
<> 134:ad3be0349dc5 800 * @note When HSITRIM is written, HSICAL is updated with the sum of
<> 134:ad3be0349dc5 801 * HSITRIM and the factory trim value
<> 134:ad3be0349dc5 802 * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration
<> 134:ad3be0349dc5 803 * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
<> 134:ad3be0349dc5 804 */
<> 134:ad3be0349dc5 805 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
<> 134:ad3be0349dc5 806 {
<> 134:ad3be0349dc5 807 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_POSITION_HSICAL);
<> 134:ad3be0349dc5 808 }
<> 134:ad3be0349dc5 809
<> 134:ad3be0349dc5 810 /**
<> 134:ad3be0349dc5 811 * @brief Set HSI Calibration trimming
<> 134:ad3be0349dc5 812 * @note user-programmable trimming value that is added to the HSICAL
<> 134:ad3be0349dc5 813 * @note Default value is 16, which, when added to the HSICAL value,
<> 134:ad3be0349dc5 814 * should trim the HSI to 16 MHz +/- 1 %
<> 134:ad3be0349dc5 815 * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming
<> 134:ad3be0349dc5 816 * @param Value between Min_Data = 0x00 and Max_Data = 0x1F
<> 134:ad3be0349dc5 817 * @retval None
<> 134:ad3be0349dc5 818 */
<> 134:ad3be0349dc5 819 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
<> 134:ad3be0349dc5 820 {
<> 134:ad3be0349dc5 821 MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_POSITION_HSITRIM);
<> 134:ad3be0349dc5 822 }
<> 134:ad3be0349dc5 823
<> 134:ad3be0349dc5 824 /**
<> 134:ad3be0349dc5 825 * @brief Get HSI Calibration trimming
<> 134:ad3be0349dc5 826 * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming
<> 134:ad3be0349dc5 827 * @retval Between Min_Data = 0x00 and Max_Data = 0x1F
<> 134:ad3be0349dc5 828 */
<> 134:ad3be0349dc5 829 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
<> 134:ad3be0349dc5 830 {
<> 134:ad3be0349dc5 831 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_POSITION_HSITRIM);
<> 134:ad3be0349dc5 832 }
<> 134:ad3be0349dc5 833
<> 134:ad3be0349dc5 834 /**
<> 134:ad3be0349dc5 835 * @}
<> 134:ad3be0349dc5 836 */
<> 134:ad3be0349dc5 837
<> 134:ad3be0349dc5 838 #if defined(RCC_HSI48_SUPPORT)
<> 134:ad3be0349dc5 839 /** @defgroup RCC_LL_EF_HSI48 HSI48
<> 134:ad3be0349dc5 840 * @{
<> 134:ad3be0349dc5 841 */
<> 134:ad3be0349dc5 842
<> 134:ad3be0349dc5 843 /**
<> 134:ad3be0349dc5 844 * @brief Enable HSI48
<> 134:ad3be0349dc5 845 * @rmtoll CR2 HSI48ON LL_RCC_HSI48_Enable
<> 134:ad3be0349dc5 846 * @retval None
<> 134:ad3be0349dc5 847 */
<> 134:ad3be0349dc5 848 __STATIC_INLINE void LL_RCC_HSI48_Enable(void)
<> 134:ad3be0349dc5 849 {
<> 134:ad3be0349dc5 850 SET_BIT(RCC->CR2, RCC_CR2_HSI48ON);
<> 134:ad3be0349dc5 851 }
<> 134:ad3be0349dc5 852
<> 134:ad3be0349dc5 853 /**
<> 134:ad3be0349dc5 854 * @brief Disable HSI48
<> 134:ad3be0349dc5 855 * @rmtoll CR2 HSI48ON LL_RCC_HSI48_Disable
<> 134:ad3be0349dc5 856 * @retval None
<> 134:ad3be0349dc5 857 */
<> 134:ad3be0349dc5 858 __STATIC_INLINE void LL_RCC_HSI48_Disable(void)
<> 134:ad3be0349dc5 859 {
<> 134:ad3be0349dc5 860 CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON);
<> 134:ad3be0349dc5 861 }
<> 134:ad3be0349dc5 862
<> 134:ad3be0349dc5 863 /**
<> 134:ad3be0349dc5 864 * @brief Check if HSI48 oscillator Ready
<> 134:ad3be0349dc5 865 * @rmtoll CR2 HSI48RDY LL_RCC_HSI48_IsReady
<> 134:ad3be0349dc5 866 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 867 */
<> 134:ad3be0349dc5 868 __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
<> 134:ad3be0349dc5 869 {
<> 134:ad3be0349dc5 870 return (READ_BIT(RCC->CR2, RCC_CR2_HSI48RDY) == (RCC_CR2_HSI48RDY));
<> 134:ad3be0349dc5 871 }
<> 134:ad3be0349dc5 872
<> 134:ad3be0349dc5 873 /**
<> 134:ad3be0349dc5 874 * @brief Get HSI48 Calibration value
<> 134:ad3be0349dc5 875 * @rmtoll CR2 HSI48CAL LL_RCC_HSI48_GetCalibration
<> 134:ad3be0349dc5 876 * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
<> 134:ad3be0349dc5 877 */
<> 134:ad3be0349dc5 878 __STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
<> 134:ad3be0349dc5 879 {
<> 134:ad3be0349dc5 880 return (uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI48CAL) >> RCC_POSITION_HSI48CAL);
<> 134:ad3be0349dc5 881 }
<> 134:ad3be0349dc5 882
<> 134:ad3be0349dc5 883 /**
<> 134:ad3be0349dc5 884 * @}
<> 134:ad3be0349dc5 885 */
<> 134:ad3be0349dc5 886
<> 134:ad3be0349dc5 887 #endif /* RCC_HSI48_SUPPORT */
<> 134:ad3be0349dc5 888
<> 134:ad3be0349dc5 889 /** @defgroup RCC_LL_EF_HSI14 HSI14
<> 134:ad3be0349dc5 890 * @{
<> 134:ad3be0349dc5 891 */
<> 134:ad3be0349dc5 892
<> 134:ad3be0349dc5 893 /**
<> 134:ad3be0349dc5 894 * @brief Enable HSI14
<> 134:ad3be0349dc5 895 * @rmtoll CR2 HSI14ON LL_RCC_HSI14_Enable
<> 134:ad3be0349dc5 896 * @retval None
<> 134:ad3be0349dc5 897 */
<> 134:ad3be0349dc5 898 __STATIC_INLINE void LL_RCC_HSI14_Enable(void)
<> 134:ad3be0349dc5 899 {
<> 134:ad3be0349dc5 900 SET_BIT(RCC->CR2, RCC_CR2_HSI14ON);
<> 134:ad3be0349dc5 901 }
<> 134:ad3be0349dc5 902
<> 134:ad3be0349dc5 903 /**
<> 134:ad3be0349dc5 904 * @brief Disable HSI14
<> 134:ad3be0349dc5 905 * @rmtoll CR2 HSI14ON LL_RCC_HSI14_Disable
<> 134:ad3be0349dc5 906 * @retval None
<> 134:ad3be0349dc5 907 */
<> 134:ad3be0349dc5 908 __STATIC_INLINE void LL_RCC_HSI14_Disable(void)
<> 134:ad3be0349dc5 909 {
<> 134:ad3be0349dc5 910 CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14ON);
<> 134:ad3be0349dc5 911 }
<> 134:ad3be0349dc5 912
<> 134:ad3be0349dc5 913 /**
<> 134:ad3be0349dc5 914 * @brief Check if HSI14 oscillator Ready
<> 134:ad3be0349dc5 915 * @rmtoll CR2 HSI14RDY LL_RCC_HSI14_IsReady
<> 134:ad3be0349dc5 916 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 917 */
<> 134:ad3be0349dc5 918 __STATIC_INLINE uint32_t LL_RCC_HSI14_IsReady(void)
<> 134:ad3be0349dc5 919 {
<> 134:ad3be0349dc5 920 return (READ_BIT(RCC->CR2, RCC_CR2_HSI14RDY) == (RCC_CR2_HSI14RDY));
<> 134:ad3be0349dc5 921 }
<> 134:ad3be0349dc5 922
<> 134:ad3be0349dc5 923 /**
<> 134:ad3be0349dc5 924 * @brief ADC interface can turn on the HSI14 oscillator
<> 134:ad3be0349dc5 925 * @rmtoll CR2 HSI14DIS LL_RCC_HSI14_EnableADCControl
<> 134:ad3be0349dc5 926 * @retval None
<> 134:ad3be0349dc5 927 */
<> 134:ad3be0349dc5 928 __STATIC_INLINE void LL_RCC_HSI14_EnableADCControl(void)
<> 134:ad3be0349dc5 929 {
<> 134:ad3be0349dc5 930 CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14DIS);
<> 134:ad3be0349dc5 931 }
<> 134:ad3be0349dc5 932
<> 134:ad3be0349dc5 933 /**
<> 134:ad3be0349dc5 934 * @brief ADC interface can not turn on the HSI14 oscillator
<> 134:ad3be0349dc5 935 * @rmtoll CR2 HSI14DIS LL_RCC_HSI14_DisableADCControl
<> 134:ad3be0349dc5 936 * @retval None
<> 134:ad3be0349dc5 937 */
<> 134:ad3be0349dc5 938 __STATIC_INLINE void LL_RCC_HSI14_DisableADCControl(void)
<> 134:ad3be0349dc5 939 {
<> 134:ad3be0349dc5 940 SET_BIT(RCC->CR2, RCC_CR2_HSI14DIS);
<> 134:ad3be0349dc5 941 }
<> 134:ad3be0349dc5 942
<> 134:ad3be0349dc5 943 /**
<> 134:ad3be0349dc5 944 * @brief Set HSI14 Calibration trimming
<> 134:ad3be0349dc5 945 * @note user-programmable trimming value that is added to the HSI14CAL
<> 134:ad3be0349dc5 946 * @note Default value is 16, which, when added to the HSI14CAL value,
<> 134:ad3be0349dc5 947 * should trim the HSI14 to 14 MHz +/- 1 %
<> 134:ad3be0349dc5 948 * @rmtoll CR2 HSI14TRIM LL_RCC_HSI14_SetCalibTrimming
<> 134:ad3be0349dc5 949 * @param Value between Min_Data = 0x00 and Max_Data = 0xFF
<> 134:ad3be0349dc5 950 * @retval None
<> 134:ad3be0349dc5 951 */
<> 134:ad3be0349dc5 952 __STATIC_INLINE void LL_RCC_HSI14_SetCalibTrimming(uint32_t Value)
<> 134:ad3be0349dc5 953 {
<> 134:ad3be0349dc5 954 MODIFY_REG(RCC->CR2, RCC_CR2_HSI14TRIM, Value << RCC_POSITION_HSI14TRIM);
<> 134:ad3be0349dc5 955 }
<> 134:ad3be0349dc5 956
<> 134:ad3be0349dc5 957 /**
<> 134:ad3be0349dc5 958 * @brief Get HSI14 Calibration value
<> 134:ad3be0349dc5 959 * @note When HSI14TRIM is written, HSI14CAL is updated with the sum of
<> 134:ad3be0349dc5 960 * HSI14TRIM and the factory trim value
<> 134:ad3be0349dc5 961 * @rmtoll CR2 HSI14TRIM LL_RCC_HSI14_GetCalibTrimming
<> 134:ad3be0349dc5 962 * @retval Between Min_Data = 0x00 and Max_Data = 0x1F
<> 134:ad3be0349dc5 963 */
<> 134:ad3be0349dc5 964 __STATIC_INLINE uint32_t LL_RCC_HSI14_GetCalibTrimming(void)
<> 134:ad3be0349dc5 965 {
<> 134:ad3be0349dc5 966 return (uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI14TRIM) >> RCC_POSITION_HSI14TRIM);
<> 134:ad3be0349dc5 967 }
<> 134:ad3be0349dc5 968
<> 134:ad3be0349dc5 969 /**
<> 134:ad3be0349dc5 970 * @brief Get HSI14 Calibration trimming
<> 134:ad3be0349dc5 971 * @rmtoll CR2 HSI14CAL LL_RCC_HSI14_GetCalibration
<> 134:ad3be0349dc5 972 * @retval Between Min_Data = 0x00 and Max_Data = 0x1F
<> 134:ad3be0349dc5 973 */
<> 134:ad3be0349dc5 974 __STATIC_INLINE uint32_t LL_RCC_HSI14_GetCalibration(void)
<> 134:ad3be0349dc5 975 {
<> 134:ad3be0349dc5 976 return (uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI14CAL) >> RCC_POSITION_HSI14CAL);
<> 134:ad3be0349dc5 977 }
<> 134:ad3be0349dc5 978
<> 134:ad3be0349dc5 979 /**
<> 134:ad3be0349dc5 980 * @}
<> 134:ad3be0349dc5 981 */
<> 134:ad3be0349dc5 982
<> 134:ad3be0349dc5 983 /** @defgroup RCC_LL_EF_LSE LSE
<> 134:ad3be0349dc5 984 * @{
<> 134:ad3be0349dc5 985 */
<> 134:ad3be0349dc5 986
<> 134:ad3be0349dc5 987 /**
<> 134:ad3be0349dc5 988 * @brief Enable Low Speed External (LSE) crystal.
<> 134:ad3be0349dc5 989 * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
<> 134:ad3be0349dc5 990 * @retval None
<> 134:ad3be0349dc5 991 */
<> 134:ad3be0349dc5 992 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
<> 134:ad3be0349dc5 993 {
<> 134:ad3be0349dc5 994 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
<> 134:ad3be0349dc5 995 }
<> 134:ad3be0349dc5 996
<> 134:ad3be0349dc5 997 /**
<> 134:ad3be0349dc5 998 * @brief Disable Low Speed External (LSE) crystal.
<> 134:ad3be0349dc5 999 * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
<> 134:ad3be0349dc5 1000 * @retval None
<> 134:ad3be0349dc5 1001 */
<> 134:ad3be0349dc5 1002 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
<> 134:ad3be0349dc5 1003 {
<> 134:ad3be0349dc5 1004 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
<> 134:ad3be0349dc5 1005 }
<> 134:ad3be0349dc5 1006
<> 134:ad3be0349dc5 1007 /**
<> 134:ad3be0349dc5 1008 * @brief Enable external clock source (LSE bypass).
<> 134:ad3be0349dc5 1009 * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
<> 134:ad3be0349dc5 1010 * @retval None
<> 134:ad3be0349dc5 1011 */
<> 134:ad3be0349dc5 1012 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
<> 134:ad3be0349dc5 1013 {
<> 134:ad3be0349dc5 1014 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
<> 134:ad3be0349dc5 1015 }
<> 134:ad3be0349dc5 1016
<> 134:ad3be0349dc5 1017 /**
<> 134:ad3be0349dc5 1018 * @brief Disable external clock source (LSE bypass).
<> 134:ad3be0349dc5 1019 * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
<> 134:ad3be0349dc5 1020 * @retval None
<> 134:ad3be0349dc5 1021 */
<> 134:ad3be0349dc5 1022 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
<> 134:ad3be0349dc5 1023 {
<> 134:ad3be0349dc5 1024 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
<> 134:ad3be0349dc5 1025 }
<> 134:ad3be0349dc5 1026
<> 134:ad3be0349dc5 1027 /**
<> 134:ad3be0349dc5 1028 * @brief Set LSE oscillator drive capability
<> 134:ad3be0349dc5 1029 * @note The oscillator is in Xtal mode when it is not in bypass mode.
<> 134:ad3be0349dc5 1030 * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
<> 134:ad3be0349dc5 1031 * @param LSEDrive This parameter can be one of the following values:
<> 134:ad3be0349dc5 1032 * @arg @ref LL_RCC_LSEDRIVE_LOW
<> 134:ad3be0349dc5 1033 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
<> 134:ad3be0349dc5 1034 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
<> 134:ad3be0349dc5 1035 * @arg @ref LL_RCC_LSEDRIVE_HIGH
<> 134:ad3be0349dc5 1036 * @retval None
<> 134:ad3be0349dc5 1037 */
<> 134:ad3be0349dc5 1038 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
<> 134:ad3be0349dc5 1039 {
<> 134:ad3be0349dc5 1040 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
<> 134:ad3be0349dc5 1041 }
<> 134:ad3be0349dc5 1042
<> 134:ad3be0349dc5 1043 /**
<> 134:ad3be0349dc5 1044 * @brief Get LSE oscillator drive capability
<> 134:ad3be0349dc5 1045 * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
<> 134:ad3be0349dc5 1046 * @retval Returned value can be one of the following values:
<> 134:ad3be0349dc5 1047 * @arg @ref LL_RCC_LSEDRIVE_LOW
<> 134:ad3be0349dc5 1048 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
<> 134:ad3be0349dc5 1049 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
<> 134:ad3be0349dc5 1050 * @arg @ref LL_RCC_LSEDRIVE_HIGH
<> 134:ad3be0349dc5 1051 */
<> 134:ad3be0349dc5 1052 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
<> 134:ad3be0349dc5 1053 {
<> 134:ad3be0349dc5 1054 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
<> 134:ad3be0349dc5 1055 }
<> 134:ad3be0349dc5 1056
<> 134:ad3be0349dc5 1057 /**
<> 134:ad3be0349dc5 1058 * @brief Check if LSE oscillator Ready
<> 134:ad3be0349dc5 1059 * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
<> 134:ad3be0349dc5 1060 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 1061 */
<> 134:ad3be0349dc5 1062 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
<> 134:ad3be0349dc5 1063 {
<> 134:ad3be0349dc5 1064 return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
<> 134:ad3be0349dc5 1065 }
<> 134:ad3be0349dc5 1066
<> 134:ad3be0349dc5 1067 /**
<> 134:ad3be0349dc5 1068 * @}
<> 134:ad3be0349dc5 1069 */
<> 134:ad3be0349dc5 1070
<> 134:ad3be0349dc5 1071 /** @defgroup RCC_LL_EF_LSI LSI
<> 134:ad3be0349dc5 1072 * @{
<> 134:ad3be0349dc5 1073 */
<> 134:ad3be0349dc5 1074
<> 134:ad3be0349dc5 1075 /**
<> 134:ad3be0349dc5 1076 * @brief Enable LSI Oscillator
<> 134:ad3be0349dc5 1077 * @rmtoll CSR LSION LL_RCC_LSI_Enable
<> 134:ad3be0349dc5 1078 * @retval None
<> 134:ad3be0349dc5 1079 */
<> 134:ad3be0349dc5 1080 __STATIC_INLINE void LL_RCC_LSI_Enable(void)
<> 134:ad3be0349dc5 1081 {
<> 134:ad3be0349dc5 1082 SET_BIT(RCC->CSR, RCC_CSR_LSION);
<> 134:ad3be0349dc5 1083 }
<> 134:ad3be0349dc5 1084
<> 134:ad3be0349dc5 1085 /**
<> 134:ad3be0349dc5 1086 * @brief Disable LSI Oscillator
<> 134:ad3be0349dc5 1087 * @rmtoll CSR LSION LL_RCC_LSI_Disable
<> 134:ad3be0349dc5 1088 * @retval None
<> 134:ad3be0349dc5 1089 */
<> 134:ad3be0349dc5 1090 __STATIC_INLINE void LL_RCC_LSI_Disable(void)
<> 134:ad3be0349dc5 1091 {
<> 134:ad3be0349dc5 1092 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
<> 134:ad3be0349dc5 1093 }
<> 134:ad3be0349dc5 1094
<> 134:ad3be0349dc5 1095 /**
<> 134:ad3be0349dc5 1096 * @brief Check if LSI is Ready
<> 134:ad3be0349dc5 1097 * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
<> 134:ad3be0349dc5 1098 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 1099 */
<> 134:ad3be0349dc5 1100 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
<> 134:ad3be0349dc5 1101 {
<> 134:ad3be0349dc5 1102 return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
<> 134:ad3be0349dc5 1103 }
<> 134:ad3be0349dc5 1104
<> 134:ad3be0349dc5 1105 /**
<> 134:ad3be0349dc5 1106 * @}
<> 134:ad3be0349dc5 1107 */
<> 134:ad3be0349dc5 1108
<> 134:ad3be0349dc5 1109 /** @defgroup RCC_LL_EF_System System
<> 134:ad3be0349dc5 1110 * @{
<> 134:ad3be0349dc5 1111 */
<> 134:ad3be0349dc5 1112
<> 134:ad3be0349dc5 1113 /**
<> 134:ad3be0349dc5 1114 * @brief Configure the system clock source
<> 134:ad3be0349dc5 1115 * @rmtoll CFGR SW LL_RCC_SetSysClkSource
<> 134:ad3be0349dc5 1116 * @param Source This parameter can be one of the following values:
<> 134:ad3be0349dc5 1117 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
<> 134:ad3be0349dc5 1118 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
<> 134:ad3be0349dc5 1119 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
<> 134:ad3be0349dc5 1120 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI48 (*)
<> 134:ad3be0349dc5 1121 *
<> 134:ad3be0349dc5 1122 * (*) value not defined in all devices
<> 134:ad3be0349dc5 1123 * @retval None
<> 134:ad3be0349dc5 1124 */
<> 134:ad3be0349dc5 1125 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
<> 134:ad3be0349dc5 1126 {
<> 134:ad3be0349dc5 1127 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
<> 134:ad3be0349dc5 1128 }
<> 134:ad3be0349dc5 1129
<> 134:ad3be0349dc5 1130 /**
<> 134:ad3be0349dc5 1131 * @brief Get the system clock source
<> 134:ad3be0349dc5 1132 * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
<> 134:ad3be0349dc5 1133 * @retval Returned value can be one of the following values:
<> 134:ad3be0349dc5 1134 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
<> 134:ad3be0349dc5 1135 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
<> 134:ad3be0349dc5 1136 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
<> 134:ad3be0349dc5 1137 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI48 (*)
<> 134:ad3be0349dc5 1138 *
<> 134:ad3be0349dc5 1139 * (*) value not defined in all devices
<> 134:ad3be0349dc5 1140 */
<> 134:ad3be0349dc5 1141 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
<> 134:ad3be0349dc5 1142 {
<> 134:ad3be0349dc5 1143 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
<> 134:ad3be0349dc5 1144 }
<> 134:ad3be0349dc5 1145
<> 134:ad3be0349dc5 1146 /**
<> 134:ad3be0349dc5 1147 * @brief Set AHB prescaler
<> 134:ad3be0349dc5 1148 * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
<> 134:ad3be0349dc5 1149 * @param Prescaler This parameter can be one of the following values:
<> 134:ad3be0349dc5 1150 * @arg @ref LL_RCC_SYSCLK_DIV_1
<> 134:ad3be0349dc5 1151 * @arg @ref LL_RCC_SYSCLK_DIV_2
<> 134:ad3be0349dc5 1152 * @arg @ref LL_RCC_SYSCLK_DIV_4
<> 134:ad3be0349dc5 1153 * @arg @ref LL_RCC_SYSCLK_DIV_8
<> 134:ad3be0349dc5 1154 * @arg @ref LL_RCC_SYSCLK_DIV_16
<> 134:ad3be0349dc5 1155 * @arg @ref LL_RCC_SYSCLK_DIV_64
<> 134:ad3be0349dc5 1156 * @arg @ref LL_RCC_SYSCLK_DIV_128
<> 134:ad3be0349dc5 1157 * @arg @ref LL_RCC_SYSCLK_DIV_256
<> 134:ad3be0349dc5 1158 * @arg @ref LL_RCC_SYSCLK_DIV_512
<> 134:ad3be0349dc5 1159 * @retval None
<> 134:ad3be0349dc5 1160 */
<> 134:ad3be0349dc5 1161 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
<> 134:ad3be0349dc5 1162 {
<> 134:ad3be0349dc5 1163 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
<> 134:ad3be0349dc5 1164 }
<> 134:ad3be0349dc5 1165
<> 134:ad3be0349dc5 1166 /**
<> 134:ad3be0349dc5 1167 * @brief Set APB1 prescaler
<> 134:ad3be0349dc5 1168 * @rmtoll CFGR PPRE LL_RCC_SetAPB1Prescaler
<> 134:ad3be0349dc5 1169 * @param Prescaler This parameter can be one of the following values:
<> 134:ad3be0349dc5 1170 * @arg @ref LL_RCC_APB1_DIV_1
<> 134:ad3be0349dc5 1171 * @arg @ref LL_RCC_APB1_DIV_2
<> 134:ad3be0349dc5 1172 * @arg @ref LL_RCC_APB1_DIV_4
<> 134:ad3be0349dc5 1173 * @arg @ref LL_RCC_APB1_DIV_8
<> 134:ad3be0349dc5 1174 * @arg @ref LL_RCC_APB1_DIV_16
<> 134:ad3be0349dc5 1175 * @retval None
<> 134:ad3be0349dc5 1176 */
<> 134:ad3be0349dc5 1177 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
<> 134:ad3be0349dc5 1178 {
<> 134:ad3be0349dc5 1179 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, Prescaler);
<> 134:ad3be0349dc5 1180 }
<> 134:ad3be0349dc5 1181
<> 134:ad3be0349dc5 1182 /**
<> 134:ad3be0349dc5 1183 * @brief Get AHB prescaler
<> 134:ad3be0349dc5 1184 * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
<> 134:ad3be0349dc5 1185 * @retval Returned value can be one of the following values:
<> 134:ad3be0349dc5 1186 * @arg @ref LL_RCC_SYSCLK_DIV_1
<> 134:ad3be0349dc5 1187 * @arg @ref LL_RCC_SYSCLK_DIV_2
<> 134:ad3be0349dc5 1188 * @arg @ref LL_RCC_SYSCLK_DIV_4
<> 134:ad3be0349dc5 1189 * @arg @ref LL_RCC_SYSCLK_DIV_8
<> 134:ad3be0349dc5 1190 * @arg @ref LL_RCC_SYSCLK_DIV_16
<> 134:ad3be0349dc5 1191 * @arg @ref LL_RCC_SYSCLK_DIV_64
<> 134:ad3be0349dc5 1192 * @arg @ref LL_RCC_SYSCLK_DIV_128
<> 134:ad3be0349dc5 1193 * @arg @ref LL_RCC_SYSCLK_DIV_256
<> 134:ad3be0349dc5 1194 * @arg @ref LL_RCC_SYSCLK_DIV_512
<> 134:ad3be0349dc5 1195 */
<> 134:ad3be0349dc5 1196 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
<> 134:ad3be0349dc5 1197 {
<> 134:ad3be0349dc5 1198 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
<> 134:ad3be0349dc5 1199 }
<> 134:ad3be0349dc5 1200
<> 134:ad3be0349dc5 1201 /**
<> 134:ad3be0349dc5 1202 * @brief Get APB1 prescaler
<> 134:ad3be0349dc5 1203 * @rmtoll CFGR PPRE LL_RCC_GetAPB1Prescaler
<> 134:ad3be0349dc5 1204 * @retval Returned value can be one of the following values:
<> 134:ad3be0349dc5 1205 * @arg @ref LL_RCC_APB1_DIV_1
<> 134:ad3be0349dc5 1206 * @arg @ref LL_RCC_APB1_DIV_2
<> 134:ad3be0349dc5 1207 * @arg @ref LL_RCC_APB1_DIV_4
<> 134:ad3be0349dc5 1208 * @arg @ref LL_RCC_APB1_DIV_8
<> 134:ad3be0349dc5 1209 * @arg @ref LL_RCC_APB1_DIV_16
<> 134:ad3be0349dc5 1210 */
<> 134:ad3be0349dc5 1211 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
<> 134:ad3be0349dc5 1212 {
<> 134:ad3be0349dc5 1213 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE));
<> 134:ad3be0349dc5 1214 }
<> 134:ad3be0349dc5 1215
<> 134:ad3be0349dc5 1216 /**
<> 134:ad3be0349dc5 1217 * @}
<> 134:ad3be0349dc5 1218 */
<> 134:ad3be0349dc5 1219
<> 134:ad3be0349dc5 1220 /** @defgroup RCC_LL_EF_MCO MCO
<> 134:ad3be0349dc5 1221 * @{
<> 134:ad3be0349dc5 1222 */
<> 134:ad3be0349dc5 1223
<> 134:ad3be0349dc5 1224 /**
<> 134:ad3be0349dc5 1225 * @brief Configure MCOx
<> 134:ad3be0349dc5 1226 * @rmtoll CFGR MCO LL_RCC_ConfigMCO\n
<> 134:ad3be0349dc5 1227 * CFGR MCOPRE LL_RCC_ConfigMCO\n
<> 134:ad3be0349dc5 1228 * CFGR PLLNODIV LL_RCC_ConfigMCO
<> 134:ad3be0349dc5 1229 * @param MCOxSource This parameter can be one of the following values:
<> 134:ad3be0349dc5 1230 * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
<> 134:ad3be0349dc5 1231 * @arg @ref LL_RCC_MCO1SOURCE_HSI14
<> 134:ad3be0349dc5 1232 * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
<> 134:ad3be0349dc5 1233 * @arg @ref LL_RCC_MCO1SOURCE_HSI
<> 134:ad3be0349dc5 1234 * @arg @ref LL_RCC_MCO1SOURCE_HSE
<> 134:ad3be0349dc5 1235 * @arg @ref LL_RCC_MCO1SOURCE_LSI
<> 134:ad3be0349dc5 1236 * @arg @ref LL_RCC_MCO1SOURCE_LSE
<> 134:ad3be0349dc5 1237 * @arg @ref LL_RCC_MCO1SOURCE_HSI48 (*)
<> 134:ad3be0349dc5 1238 * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK (*)
<> 134:ad3be0349dc5 1239 * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK_DIV_2
<> 134:ad3be0349dc5 1240 *
<> 134:ad3be0349dc5 1241 * (*) value not defined in all devices
<> 134:ad3be0349dc5 1242 * @param MCOxPrescaler This parameter can be one of the following values:
<> 134:ad3be0349dc5 1243 * @arg @ref LL_RCC_MCO1_DIV_1
<> 134:ad3be0349dc5 1244 * @arg @ref LL_RCC_MCO1_DIV_2 (*)
<> 134:ad3be0349dc5 1245 * @arg @ref LL_RCC_MCO1_DIV_4 (*)
<> 134:ad3be0349dc5 1246 * @arg @ref LL_RCC_MCO1_DIV_8 (*)
<> 134:ad3be0349dc5 1247 * @arg @ref LL_RCC_MCO1_DIV_16 (*)
<> 134:ad3be0349dc5 1248 * @arg @ref LL_RCC_MCO1_DIV_32 (*)
<> 134:ad3be0349dc5 1249 * @arg @ref LL_RCC_MCO1_DIV_64 (*)
<> 134:ad3be0349dc5 1250 * @arg @ref LL_RCC_MCO1_DIV_128 (*)
<> 134:ad3be0349dc5 1251 *
<> 134:ad3be0349dc5 1252 * (*) value not defined in all devices
<> 134:ad3be0349dc5 1253 * @retval None
<> 134:ad3be0349dc5 1254 */
<> 134:ad3be0349dc5 1255 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
<> 134:ad3be0349dc5 1256 {
<> 134:ad3be0349dc5 1257 #if defined(RCC_CFGR_MCOPRE)
<> 134:ad3be0349dc5 1258 #if defined(RCC_CFGR_PLLNODIV)
<> 134:ad3be0349dc5 1259 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE | RCC_CFGR_PLLNODIV, MCOxSource | MCOxPrescaler);
<> 134:ad3be0349dc5 1260 #else
<> 134:ad3be0349dc5 1261 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler);
<> 134:ad3be0349dc5 1262 #endif /* RCC_CFGR_PLLNODIV */
<> 134:ad3be0349dc5 1263 #else
<> 134:ad3be0349dc5 1264 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL, MCOxSource);
<> 134:ad3be0349dc5 1265 #endif /* RCC_CFGR_MCOPRE */
<> 134:ad3be0349dc5 1266 }
<> 134:ad3be0349dc5 1267
<> 134:ad3be0349dc5 1268 /**
<> 134:ad3be0349dc5 1269 * @}
<> 134:ad3be0349dc5 1270 */
<> 134:ad3be0349dc5 1271
<> 134:ad3be0349dc5 1272 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
<> 134:ad3be0349dc5 1273 * @{
<> 134:ad3be0349dc5 1274 */
<> 134:ad3be0349dc5 1275
<> 134:ad3be0349dc5 1276 /**
<> 134:ad3be0349dc5 1277 * @brief Configure USARTx clock source
<> 134:ad3be0349dc5 1278 * @rmtoll CFGR3 USART1SW LL_RCC_SetUSARTClockSource\n
<> 134:ad3be0349dc5 1279 * CFGR3 USART2SW LL_RCC_SetUSARTClockSource\n
<> 134:ad3be0349dc5 1280 * CFGR3 USART3SW LL_RCC_SetUSARTClockSource
<> 134:ad3be0349dc5 1281 * @param USARTxSource This parameter can be one of the following values:
<> 134:ad3be0349dc5 1282 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1
<> 134:ad3be0349dc5 1283 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
<> 134:ad3be0349dc5 1284 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
<> 134:ad3be0349dc5 1285 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
<> 134:ad3be0349dc5 1286 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*)
<> 134:ad3be0349dc5 1287 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*)
<> 134:ad3be0349dc5 1288 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*)
<> 134:ad3be0349dc5 1289 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*)
<> 134:ad3be0349dc5 1290 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
<> 134:ad3be0349dc5 1291 * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
<> 134:ad3be0349dc5 1292 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
<> 134:ad3be0349dc5 1293 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
<> 134:ad3be0349dc5 1294 *
<> 134:ad3be0349dc5 1295 * (*) value not defined in all devices.
<> 134:ad3be0349dc5 1296 * @retval None
<> 134:ad3be0349dc5 1297 */
<> 134:ad3be0349dc5 1298 __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
<> 134:ad3be0349dc5 1299 {
<> 134:ad3be0349dc5 1300 MODIFY_REG(RCC->CFGR3, (RCC_CFGR3_USART1SW << ((USARTxSource & 0xFF000000U) >> 24U)), (USARTxSource & 0x00FFFFFFU));
<> 134:ad3be0349dc5 1301 }
<> 134:ad3be0349dc5 1302
<> 134:ad3be0349dc5 1303 /**
<> 134:ad3be0349dc5 1304 * @brief Configure I2Cx clock source
<> 134:ad3be0349dc5 1305 * @rmtoll CFGR3 I2C1SW LL_RCC_SetI2CClockSource
<> 134:ad3be0349dc5 1306 * @param I2CxSource This parameter can be one of the following values:
<> 134:ad3be0349dc5 1307 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
<> 134:ad3be0349dc5 1308 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
<> 134:ad3be0349dc5 1309 * @retval None
<> 134:ad3be0349dc5 1310 */
<> 134:ad3be0349dc5 1311 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
<> 134:ad3be0349dc5 1312 {
<> 134:ad3be0349dc5 1313 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, I2CxSource);
<> 134:ad3be0349dc5 1314 }
<> 134:ad3be0349dc5 1315
<> 134:ad3be0349dc5 1316 #if defined(CEC)
<> 134:ad3be0349dc5 1317 /**
<> 134:ad3be0349dc5 1318 * @brief Configure CEC clock source
<> 134:ad3be0349dc5 1319 * @rmtoll CFGR3 CECSW LL_RCC_SetCECClockSource
<> 134:ad3be0349dc5 1320 * @param CECxSource This parameter can be one of the following values:
<> 134:ad3be0349dc5 1321 * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV244
<> 134:ad3be0349dc5 1322 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
<> 134:ad3be0349dc5 1323 * @retval None
<> 134:ad3be0349dc5 1324 */
<> 134:ad3be0349dc5 1325 __STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t CECxSource)
<> 134:ad3be0349dc5 1326 {
<> 134:ad3be0349dc5 1327 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, CECxSource);
<> 134:ad3be0349dc5 1328 }
<> 134:ad3be0349dc5 1329 #endif /* CEC */
<> 134:ad3be0349dc5 1330
<> 134:ad3be0349dc5 1331 #if defined(USB)
<> 134:ad3be0349dc5 1332 /**
<> 134:ad3be0349dc5 1333 * @brief Configure USB clock source
<> 134:ad3be0349dc5 1334 * @rmtoll CFGR3 USBSW LL_RCC_SetUSBClockSource
<> 134:ad3be0349dc5 1335 * @param USBxSource This parameter can be one of the following values:
<> 134:ad3be0349dc5 1336 * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*)
<> 134:ad3be0349dc5 1337 * @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*)
<> 134:ad3be0349dc5 1338 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
<> 134:ad3be0349dc5 1339 *
<> 134:ad3be0349dc5 1340 * (*) value not defined in all devices.
<> 134:ad3be0349dc5 1341 * @retval None
<> 134:ad3be0349dc5 1342 */
<> 134:ad3be0349dc5 1343 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
<> 134:ad3be0349dc5 1344 {
<> 134:ad3be0349dc5 1345 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USBSW, USBxSource);
<> 134:ad3be0349dc5 1346 }
<> 134:ad3be0349dc5 1347 #endif /* USB */
<> 134:ad3be0349dc5 1348
<> 134:ad3be0349dc5 1349 /**
<> 134:ad3be0349dc5 1350 * @brief Get USARTx clock source
<> 134:ad3be0349dc5 1351 * @rmtoll CFGR3 USART1SW LL_RCC_GetUSARTClockSource\n
<> 134:ad3be0349dc5 1352 * CFGR3 USART2SW LL_RCC_GetUSARTClockSource\n
<> 134:ad3be0349dc5 1353 * CFGR3 USART3SW LL_RCC_GetUSARTClockSource
<> 134:ad3be0349dc5 1354 * @param USARTx This parameter can be one of the following values:
<> 134:ad3be0349dc5 1355 * @arg @ref LL_RCC_USART1_CLKSOURCE
<> 134:ad3be0349dc5 1356 * @arg @ref LL_RCC_USART2_CLKSOURCE (*)
<> 134:ad3be0349dc5 1357 * @arg @ref LL_RCC_USART3_CLKSOURCE (*)
<> 134:ad3be0349dc5 1358 *
<> 134:ad3be0349dc5 1359 * (*) value not defined in all devices.
<> 134:ad3be0349dc5 1360 * @retval Returned value can be one of the following values:
<> 134:ad3be0349dc5 1361 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1
<> 134:ad3be0349dc5 1362 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
<> 134:ad3be0349dc5 1363 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
<> 134:ad3be0349dc5 1364 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
<> 134:ad3be0349dc5 1365 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*)
<> 134:ad3be0349dc5 1366 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*)
<> 134:ad3be0349dc5 1367 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*)
<> 134:ad3be0349dc5 1368 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*)
<> 134:ad3be0349dc5 1369 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
<> 134:ad3be0349dc5 1370 * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
<> 134:ad3be0349dc5 1371 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
<> 134:ad3be0349dc5 1372 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
<> 134:ad3be0349dc5 1373 *
<> 134:ad3be0349dc5 1374 * (*) value not defined in all devices.
<> 134:ad3be0349dc5 1375 */
<> 134:ad3be0349dc5 1376 __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
<> 134:ad3be0349dc5 1377 {
<> 134:ad3be0349dc5 1378 return (uint32_t)(READ_BIT(RCC->CFGR3, (RCC_CFGR3_USART1SW << USARTx)) | (USARTx << 24U));
<> 134:ad3be0349dc5 1379 }
<> 134:ad3be0349dc5 1380
<> 134:ad3be0349dc5 1381 /**
<> 134:ad3be0349dc5 1382 * @brief Get I2Cx clock source
<> 134:ad3be0349dc5 1383 * @rmtoll CFGR3 I2C1SW LL_RCC_GetI2CClockSource
<> 134:ad3be0349dc5 1384 * @param I2Cx This parameter can be one of the following values:
<> 134:ad3be0349dc5 1385 * @arg @ref LL_RCC_I2C1_CLKSOURCE
<> 134:ad3be0349dc5 1386 * @retval Returned value can be one of the following values:
<> 134:ad3be0349dc5 1387 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
<> 134:ad3be0349dc5 1388 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
<> 134:ad3be0349dc5 1389 */
<> 134:ad3be0349dc5 1390 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
<> 134:ad3be0349dc5 1391 {
<> 134:ad3be0349dc5 1392 return (uint32_t)(READ_BIT(RCC->CFGR3, I2Cx));
<> 134:ad3be0349dc5 1393 }
<> 134:ad3be0349dc5 1394
<> 134:ad3be0349dc5 1395 #if defined(CEC)
<> 134:ad3be0349dc5 1396 /**
<> 134:ad3be0349dc5 1397 * @brief Get CEC clock source
<> 134:ad3be0349dc5 1398 * @rmtoll CFGR3 CECSW LL_RCC_GetCECClockSource
<> 134:ad3be0349dc5 1399 * @param CECx This parameter can be one of the following values:
<> 134:ad3be0349dc5 1400 * @arg @ref LL_RCC_CEC_CLKSOURCE
<> 134:ad3be0349dc5 1401 * @retval Returned value can be one of the following values:
<> 134:ad3be0349dc5 1402 * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV244
<> 134:ad3be0349dc5 1403 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
<> 134:ad3be0349dc5 1404 */
<> 134:ad3be0349dc5 1405 __STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx)
<> 134:ad3be0349dc5 1406 {
<> 134:ad3be0349dc5 1407 return (uint32_t)(READ_BIT(RCC->CFGR3, CECx));
<> 134:ad3be0349dc5 1408 }
<> 134:ad3be0349dc5 1409 #endif /* CEC */
<> 134:ad3be0349dc5 1410
<> 134:ad3be0349dc5 1411 #if defined(USB)
<> 134:ad3be0349dc5 1412 /**
<> 134:ad3be0349dc5 1413 * @brief Get USBx clock source
<> 134:ad3be0349dc5 1414 * @rmtoll CFGR3 USBSW LL_RCC_GetUSBClockSource
<> 134:ad3be0349dc5 1415 * @param USBx This parameter can be one of the following values:
<> 134:ad3be0349dc5 1416 * @arg @ref LL_RCC_USB_CLKSOURCE
<> 134:ad3be0349dc5 1417 * @retval Returned value can be one of the following values:
<> 134:ad3be0349dc5 1418 * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*)
<> 134:ad3be0349dc5 1419 * @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*)
<> 134:ad3be0349dc5 1420 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
<> 134:ad3be0349dc5 1421 *
<> 134:ad3be0349dc5 1422 * (*) value not defined in all devices.
<> 134:ad3be0349dc5 1423 */
<> 134:ad3be0349dc5 1424 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
<> 134:ad3be0349dc5 1425 {
<> 134:ad3be0349dc5 1426 return (uint32_t)(READ_BIT(RCC->CFGR3, USBx));
<> 134:ad3be0349dc5 1427 }
<> 134:ad3be0349dc5 1428 #endif /* USB */
<> 134:ad3be0349dc5 1429
<> 134:ad3be0349dc5 1430 /**
<> 134:ad3be0349dc5 1431 * @}
<> 134:ad3be0349dc5 1432 */
<> 134:ad3be0349dc5 1433
<> 134:ad3be0349dc5 1434 /** @defgroup RCC_LL_EF_RTC RTC
<> 134:ad3be0349dc5 1435 * @{
<> 134:ad3be0349dc5 1436 */
<> 134:ad3be0349dc5 1437
<> 134:ad3be0349dc5 1438 /**
<> 134:ad3be0349dc5 1439 * @brief Set RTC Clock Source
<> 134:ad3be0349dc5 1440 * @note Once the RTC clock source has been selected, it cannot be changed any more unless
<> 134:ad3be0349dc5 1441 * the Backup domain is reset. The BDRST bit can be used to reset them.
<> 134:ad3be0349dc5 1442 * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
<> 134:ad3be0349dc5 1443 * @param Source This parameter can be one of the following values:
<> 134:ad3be0349dc5 1444 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
<> 134:ad3be0349dc5 1445 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
<> 134:ad3be0349dc5 1446 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
<> 134:ad3be0349dc5 1447 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
<> 134:ad3be0349dc5 1448 * @retval None
<> 134:ad3be0349dc5 1449 */
<> 134:ad3be0349dc5 1450 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
<> 134:ad3be0349dc5 1451 {
<> 134:ad3be0349dc5 1452 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
<> 134:ad3be0349dc5 1453 }
<> 134:ad3be0349dc5 1454
<> 134:ad3be0349dc5 1455 /**
<> 134:ad3be0349dc5 1456 * @brief Get RTC Clock Source
<> 134:ad3be0349dc5 1457 * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
<> 134:ad3be0349dc5 1458 * @retval Returned value can be one of the following values:
<> 134:ad3be0349dc5 1459 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
<> 134:ad3be0349dc5 1460 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
<> 134:ad3be0349dc5 1461 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
<> 134:ad3be0349dc5 1462 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
<> 134:ad3be0349dc5 1463 */
<> 134:ad3be0349dc5 1464 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
<> 134:ad3be0349dc5 1465 {
<> 134:ad3be0349dc5 1466 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
<> 134:ad3be0349dc5 1467 }
<> 134:ad3be0349dc5 1468
<> 134:ad3be0349dc5 1469 /**
<> 134:ad3be0349dc5 1470 * @brief Enable RTC
<> 134:ad3be0349dc5 1471 * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
<> 134:ad3be0349dc5 1472 * @retval None
<> 134:ad3be0349dc5 1473 */
<> 134:ad3be0349dc5 1474 __STATIC_INLINE void LL_RCC_EnableRTC(void)
<> 134:ad3be0349dc5 1475 {
<> 134:ad3be0349dc5 1476 SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
<> 134:ad3be0349dc5 1477 }
<> 134:ad3be0349dc5 1478
<> 134:ad3be0349dc5 1479 /**
<> 134:ad3be0349dc5 1480 * @brief Disable RTC
<> 134:ad3be0349dc5 1481 * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
<> 134:ad3be0349dc5 1482 * @retval None
<> 134:ad3be0349dc5 1483 */
<> 134:ad3be0349dc5 1484 __STATIC_INLINE void LL_RCC_DisableRTC(void)
<> 134:ad3be0349dc5 1485 {
<> 134:ad3be0349dc5 1486 CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
<> 134:ad3be0349dc5 1487 }
<> 134:ad3be0349dc5 1488
<> 134:ad3be0349dc5 1489 /**
<> 134:ad3be0349dc5 1490 * @brief Check if RTC has been enabled or not
<> 134:ad3be0349dc5 1491 * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
<> 134:ad3be0349dc5 1492 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 1493 */
<> 134:ad3be0349dc5 1494 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
<> 134:ad3be0349dc5 1495 {
<> 134:ad3be0349dc5 1496 return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
<> 134:ad3be0349dc5 1497 }
<> 134:ad3be0349dc5 1498
<> 134:ad3be0349dc5 1499 /**
<> 134:ad3be0349dc5 1500 * @brief Force the Backup domain reset
<> 134:ad3be0349dc5 1501 * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
<> 134:ad3be0349dc5 1502 * @retval None
<> 134:ad3be0349dc5 1503 */
<> 134:ad3be0349dc5 1504 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
<> 134:ad3be0349dc5 1505 {
<> 134:ad3be0349dc5 1506 SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
<> 134:ad3be0349dc5 1507 }
<> 134:ad3be0349dc5 1508
<> 134:ad3be0349dc5 1509 /**
<> 134:ad3be0349dc5 1510 * @brief Release the Backup domain reset
<> 134:ad3be0349dc5 1511 * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
<> 134:ad3be0349dc5 1512 * @retval None
<> 134:ad3be0349dc5 1513 */
<> 134:ad3be0349dc5 1514 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
<> 134:ad3be0349dc5 1515 {
<> 134:ad3be0349dc5 1516 CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
<> 134:ad3be0349dc5 1517 }
<> 134:ad3be0349dc5 1518
<> 134:ad3be0349dc5 1519 /**
<> 134:ad3be0349dc5 1520 * @}
<> 134:ad3be0349dc5 1521 */
<> 134:ad3be0349dc5 1522
<> 134:ad3be0349dc5 1523 /** @defgroup RCC_LL_EF_PLL PLL
<> 134:ad3be0349dc5 1524 * @{
<> 134:ad3be0349dc5 1525 */
<> 134:ad3be0349dc5 1526
<> 134:ad3be0349dc5 1527 /**
<> 134:ad3be0349dc5 1528 * @brief Enable PLL
<> 134:ad3be0349dc5 1529 * @rmtoll CR PLLON LL_RCC_PLL_Enable
<> 134:ad3be0349dc5 1530 * @retval None
<> 134:ad3be0349dc5 1531 */
<> 134:ad3be0349dc5 1532 __STATIC_INLINE void LL_RCC_PLL_Enable(void)
<> 134:ad3be0349dc5 1533 {
<> 134:ad3be0349dc5 1534 SET_BIT(RCC->CR, RCC_CR_PLLON);
<> 134:ad3be0349dc5 1535 }
<> 134:ad3be0349dc5 1536
<> 134:ad3be0349dc5 1537 /**
<> 134:ad3be0349dc5 1538 * @brief Disable PLL
<> 134:ad3be0349dc5 1539 * @note Cannot be disabled if the PLL clock is used as the system clock
<> 134:ad3be0349dc5 1540 * @rmtoll CR PLLON LL_RCC_PLL_Disable
<> 134:ad3be0349dc5 1541 * @retval None
<> 134:ad3be0349dc5 1542 */
<> 134:ad3be0349dc5 1543 __STATIC_INLINE void LL_RCC_PLL_Disable(void)
<> 134:ad3be0349dc5 1544 {
<> 134:ad3be0349dc5 1545 CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
<> 134:ad3be0349dc5 1546 }
<> 134:ad3be0349dc5 1547
<> 134:ad3be0349dc5 1548 /**
<> 134:ad3be0349dc5 1549 * @brief Check if PLL Ready
<> 134:ad3be0349dc5 1550 * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
<> 134:ad3be0349dc5 1551 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 1552 */
<> 134:ad3be0349dc5 1553 __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
<> 134:ad3be0349dc5 1554 {
<> 134:ad3be0349dc5 1555 return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
<> 134:ad3be0349dc5 1556 }
<> 134:ad3be0349dc5 1557
<> 134:ad3be0349dc5 1558 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
<> 134:ad3be0349dc5 1559 /**
<> 134:ad3be0349dc5 1560 * @brief Configure PLL used for SYSCLK Domain
<> 134:ad3be0349dc5 1561 * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
<> 134:ad3be0349dc5 1562 * CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n
<> 134:ad3be0349dc5 1563 * CFGR2 PREDIV LL_RCC_PLL_ConfigDomain_SYS
<> 134:ad3be0349dc5 1564 * @param Source This parameter can be one of the following values:
<> 134:ad3be0349dc5 1565 * @arg @ref LL_RCC_PLLSOURCE_HSI
<> 134:ad3be0349dc5 1566 * @arg @ref LL_RCC_PLLSOURCE_HSE
<> 134:ad3be0349dc5 1567 * @arg @ref LL_RCC_PLLSOURCE_HSI48 (*)
<> 134:ad3be0349dc5 1568 *
<> 134:ad3be0349dc5 1569 * (*) value not defined in all devices
<> 134:ad3be0349dc5 1570 * @param PLLMul This parameter can be one of the following values:
<> 134:ad3be0349dc5 1571 * @arg @ref LL_RCC_PLL_MUL_2
<> 134:ad3be0349dc5 1572 * @arg @ref LL_RCC_PLL_MUL_3
<> 134:ad3be0349dc5 1573 * @arg @ref LL_RCC_PLL_MUL_4
<> 134:ad3be0349dc5 1574 * @arg @ref LL_RCC_PLL_MUL_5
<> 134:ad3be0349dc5 1575 * @arg @ref LL_RCC_PLL_MUL_6
<> 134:ad3be0349dc5 1576 * @arg @ref LL_RCC_PLL_MUL_7
<> 134:ad3be0349dc5 1577 * @arg @ref LL_RCC_PLL_MUL_8
<> 134:ad3be0349dc5 1578 * @arg @ref LL_RCC_PLL_MUL_9
<> 134:ad3be0349dc5 1579 * @arg @ref LL_RCC_PLL_MUL_10
<> 134:ad3be0349dc5 1580 * @arg @ref LL_RCC_PLL_MUL_11
<> 134:ad3be0349dc5 1581 * @arg @ref LL_RCC_PLL_MUL_12
<> 134:ad3be0349dc5 1582 * @arg @ref LL_RCC_PLL_MUL_13
<> 134:ad3be0349dc5 1583 * @arg @ref LL_RCC_PLL_MUL_14
<> 134:ad3be0349dc5 1584 * @arg @ref LL_RCC_PLL_MUL_15
<> 134:ad3be0349dc5 1585 * @arg @ref LL_RCC_PLL_MUL_16
<> 134:ad3be0349dc5 1586 * @param PLLDiv This parameter can be one of the following values:
<> 134:ad3be0349dc5 1587 * @arg @ref LL_RCC_PREDIV_DIV_1
<> 134:ad3be0349dc5 1588 * @arg @ref LL_RCC_PREDIV_DIV_2
<> 134:ad3be0349dc5 1589 * @arg @ref LL_RCC_PREDIV_DIV_3
<> 134:ad3be0349dc5 1590 * @arg @ref LL_RCC_PREDIV_DIV_4
<> 134:ad3be0349dc5 1591 * @arg @ref LL_RCC_PREDIV_DIV_5
<> 134:ad3be0349dc5 1592 * @arg @ref LL_RCC_PREDIV_DIV_6
<> 134:ad3be0349dc5 1593 * @arg @ref LL_RCC_PREDIV_DIV_7
<> 134:ad3be0349dc5 1594 * @arg @ref LL_RCC_PREDIV_DIV_8
<> 134:ad3be0349dc5 1595 * @arg @ref LL_RCC_PREDIV_DIV_9
<> 134:ad3be0349dc5 1596 * @arg @ref LL_RCC_PREDIV_DIV_10
<> 134:ad3be0349dc5 1597 * @arg @ref LL_RCC_PREDIV_DIV_11
<> 134:ad3be0349dc5 1598 * @arg @ref LL_RCC_PREDIV_DIV_12
<> 134:ad3be0349dc5 1599 * @arg @ref LL_RCC_PREDIV_DIV_13
<> 134:ad3be0349dc5 1600 * @arg @ref LL_RCC_PREDIV_DIV_14
<> 134:ad3be0349dc5 1601 * @arg @ref LL_RCC_PREDIV_DIV_15
<> 134:ad3be0349dc5 1602 * @arg @ref LL_RCC_PREDIV_DIV_16
<> 134:ad3be0349dc5 1603 * @retval None
<> 134:ad3be0349dc5 1604 */
<> 134:ad3be0349dc5 1605 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul, uint32_t PLLDiv)
<> 134:ad3be0349dc5 1606 {
<> 134:ad3be0349dc5 1607 MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL, Source | PLLMul);
<> 134:ad3be0349dc5 1608 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, PLLDiv);
<> 134:ad3be0349dc5 1609 }
<> 134:ad3be0349dc5 1610
<> 134:ad3be0349dc5 1611 #else
<> 134:ad3be0349dc5 1612
<> 134:ad3be0349dc5 1613 /**
<> 134:ad3be0349dc5 1614 * @brief Configure PLL used for SYSCLK Domain
<> 134:ad3be0349dc5 1615 * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
<> 134:ad3be0349dc5 1616 * CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n
<> 134:ad3be0349dc5 1617 * CFGR2 PREDIV LL_RCC_PLL_ConfigDomain_SYS
<> 134:ad3be0349dc5 1618 * @param Source This parameter can be one of the following values:
<> 134:ad3be0349dc5 1619 * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2
<> 134:ad3be0349dc5 1620 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_1
<> 134:ad3be0349dc5 1621 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_2
<> 134:ad3be0349dc5 1622 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_3
<> 134:ad3be0349dc5 1623 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_4
<> 134:ad3be0349dc5 1624 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_5
<> 134:ad3be0349dc5 1625 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_6
<> 134:ad3be0349dc5 1626 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_7
<> 134:ad3be0349dc5 1627 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_8
<> 134:ad3be0349dc5 1628 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_9
<> 134:ad3be0349dc5 1629 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_10
<> 134:ad3be0349dc5 1630 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_11
<> 134:ad3be0349dc5 1631 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_12
<> 134:ad3be0349dc5 1632 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_13
<> 134:ad3be0349dc5 1633 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_14
<> 134:ad3be0349dc5 1634 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_15
<> 134:ad3be0349dc5 1635 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_16
<> 134:ad3be0349dc5 1636 * @param PLLMul This parameter can be one of the following values:
<> 134:ad3be0349dc5 1637 * @arg @ref LL_RCC_PLL_MUL_2
<> 134:ad3be0349dc5 1638 * @arg @ref LL_RCC_PLL_MUL_3
<> 134:ad3be0349dc5 1639 * @arg @ref LL_RCC_PLL_MUL_4
<> 134:ad3be0349dc5 1640 * @arg @ref LL_RCC_PLL_MUL_5
<> 134:ad3be0349dc5 1641 * @arg @ref LL_RCC_PLL_MUL_6
<> 134:ad3be0349dc5 1642 * @arg @ref LL_RCC_PLL_MUL_7
<> 134:ad3be0349dc5 1643 * @arg @ref LL_RCC_PLL_MUL_8
<> 134:ad3be0349dc5 1644 * @arg @ref LL_RCC_PLL_MUL_9
<> 134:ad3be0349dc5 1645 * @arg @ref LL_RCC_PLL_MUL_10
<> 134:ad3be0349dc5 1646 * @arg @ref LL_RCC_PLL_MUL_11
<> 134:ad3be0349dc5 1647 * @arg @ref LL_RCC_PLL_MUL_12
<> 134:ad3be0349dc5 1648 * @arg @ref LL_RCC_PLL_MUL_13
<> 134:ad3be0349dc5 1649 * @arg @ref LL_RCC_PLL_MUL_14
<> 134:ad3be0349dc5 1650 * @arg @ref LL_RCC_PLL_MUL_15
<> 134:ad3be0349dc5 1651 * @arg @ref LL_RCC_PLL_MUL_16
<> 134:ad3be0349dc5 1652 * @retval None
<> 134:ad3be0349dc5 1653 */
<> 134:ad3be0349dc5 1654 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul)
<> 134:ad3be0349dc5 1655 {
<> 134:ad3be0349dc5 1656 MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL, (Source & RCC_CFGR_PLLSRC) | PLLMul);
<> 134:ad3be0349dc5 1657 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (Source & RCC_CFGR2_PREDIV));
<> 134:ad3be0349dc5 1658 }
<> 134:ad3be0349dc5 1659 #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
<> 134:ad3be0349dc5 1660
<> 134:ad3be0349dc5 1661 /**
<> 134:ad3be0349dc5 1662 * @brief Get the oscillator used as PLL clock source.
<> 134:ad3be0349dc5 1663 * @rmtoll CFGR PLLSRC LL_RCC_PLL_GetMainSource
<> 134:ad3be0349dc5 1664 * @retval Returned value can be one of the following values:
<> 134:ad3be0349dc5 1665 * @arg @ref LL_RCC_PLLSOURCE_HSI (*)
<> 134:ad3be0349dc5 1666 * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 (*)
<> 134:ad3be0349dc5 1667 * @arg @ref LL_RCC_PLLSOURCE_HSE
<> 134:ad3be0349dc5 1668 * @arg @ref LL_RCC_PLLSOURCE_HSI48 (*)
<> 134:ad3be0349dc5 1669 *
<> 134:ad3be0349dc5 1670 * (*) value not defined in all devices
<> 134:ad3be0349dc5 1671 */
<> 134:ad3be0349dc5 1672 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
<> 134:ad3be0349dc5 1673 {
<> 134:ad3be0349dc5 1674 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC));
<> 134:ad3be0349dc5 1675 }
<> 134:ad3be0349dc5 1676
<> 134:ad3be0349dc5 1677 /**
<> 134:ad3be0349dc5 1678 * @brief Get PLL multiplication Factor
<> 134:ad3be0349dc5 1679 * @rmtoll CFGR PLLMUL LL_RCC_PLL_GetMultiplicator
<> 134:ad3be0349dc5 1680 * @retval Returned value can be one of the following values:
<> 134:ad3be0349dc5 1681 * @arg @ref LL_RCC_PLL_MUL_2
<> 134:ad3be0349dc5 1682 * @arg @ref LL_RCC_PLL_MUL_3
<> 134:ad3be0349dc5 1683 * @arg @ref LL_RCC_PLL_MUL_4
<> 134:ad3be0349dc5 1684 * @arg @ref LL_RCC_PLL_MUL_5
<> 134:ad3be0349dc5 1685 * @arg @ref LL_RCC_PLL_MUL_6
<> 134:ad3be0349dc5 1686 * @arg @ref LL_RCC_PLL_MUL_7
<> 134:ad3be0349dc5 1687 * @arg @ref LL_RCC_PLL_MUL_8
<> 134:ad3be0349dc5 1688 * @arg @ref LL_RCC_PLL_MUL_9
<> 134:ad3be0349dc5 1689 * @arg @ref LL_RCC_PLL_MUL_10
<> 134:ad3be0349dc5 1690 * @arg @ref LL_RCC_PLL_MUL_11
<> 134:ad3be0349dc5 1691 * @arg @ref LL_RCC_PLL_MUL_12
<> 134:ad3be0349dc5 1692 * @arg @ref LL_RCC_PLL_MUL_13
<> 134:ad3be0349dc5 1693 * @arg @ref LL_RCC_PLL_MUL_14
<> 134:ad3be0349dc5 1694 * @arg @ref LL_RCC_PLL_MUL_15
<> 134:ad3be0349dc5 1695 * @arg @ref LL_RCC_PLL_MUL_16
<> 134:ad3be0349dc5 1696 */
<> 134:ad3be0349dc5 1697 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void)
<> 134:ad3be0349dc5 1698 {
<> 134:ad3be0349dc5 1699 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMUL));
<> 134:ad3be0349dc5 1700 }
<> 134:ad3be0349dc5 1701
<> 134:ad3be0349dc5 1702 /**
<> 134:ad3be0349dc5 1703 * @brief Get PREDIV division factor for the main PLL
<> 134:ad3be0349dc5 1704 * @note They can be written only when the PLL is disabled
<> 134:ad3be0349dc5 1705 * @rmtoll CFGR2 PREDIV LL_RCC_PLL_GetPrediv
<> 134:ad3be0349dc5 1706 * @retval Returned value can be one of the following values:
<> 134:ad3be0349dc5 1707 * @arg @ref LL_RCC_PREDIV_DIV_1
<> 134:ad3be0349dc5 1708 * @arg @ref LL_RCC_PREDIV_DIV_2
<> 134:ad3be0349dc5 1709 * @arg @ref LL_RCC_PREDIV_DIV_3
<> 134:ad3be0349dc5 1710 * @arg @ref LL_RCC_PREDIV_DIV_4
<> 134:ad3be0349dc5 1711 * @arg @ref LL_RCC_PREDIV_DIV_5
<> 134:ad3be0349dc5 1712 * @arg @ref LL_RCC_PREDIV_DIV_6
<> 134:ad3be0349dc5 1713 * @arg @ref LL_RCC_PREDIV_DIV_7
<> 134:ad3be0349dc5 1714 * @arg @ref LL_RCC_PREDIV_DIV_8
<> 134:ad3be0349dc5 1715 * @arg @ref LL_RCC_PREDIV_DIV_9
<> 134:ad3be0349dc5 1716 * @arg @ref LL_RCC_PREDIV_DIV_10
<> 134:ad3be0349dc5 1717 * @arg @ref LL_RCC_PREDIV_DIV_11
<> 134:ad3be0349dc5 1718 * @arg @ref LL_RCC_PREDIV_DIV_12
<> 134:ad3be0349dc5 1719 * @arg @ref LL_RCC_PREDIV_DIV_13
<> 134:ad3be0349dc5 1720 * @arg @ref LL_RCC_PREDIV_DIV_14
<> 134:ad3be0349dc5 1721 * @arg @ref LL_RCC_PREDIV_DIV_15
<> 134:ad3be0349dc5 1722 * @arg @ref LL_RCC_PREDIV_DIV_16
<> 134:ad3be0349dc5 1723 */
<> 134:ad3be0349dc5 1724 __STATIC_INLINE uint32_t LL_RCC_PLL_GetPrediv(void)
<> 134:ad3be0349dc5 1725 {
<> 134:ad3be0349dc5 1726 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV));
<> 134:ad3be0349dc5 1727 }
<> 134:ad3be0349dc5 1728
<> 134:ad3be0349dc5 1729 /**
<> 134:ad3be0349dc5 1730 * @}
<> 134:ad3be0349dc5 1731 */
<> 134:ad3be0349dc5 1732
<> 134:ad3be0349dc5 1733 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
<> 134:ad3be0349dc5 1734 * @{
<> 134:ad3be0349dc5 1735 */
<> 134:ad3be0349dc5 1736
<> 134:ad3be0349dc5 1737 /**
<> 134:ad3be0349dc5 1738 * @brief Clear LSI ready interrupt flag
<> 134:ad3be0349dc5 1739 * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY
<> 134:ad3be0349dc5 1740 * @retval None
<> 134:ad3be0349dc5 1741 */
<> 134:ad3be0349dc5 1742 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
<> 134:ad3be0349dc5 1743 {
<> 134:ad3be0349dc5 1744 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
<> 134:ad3be0349dc5 1745 }
<> 134:ad3be0349dc5 1746
<> 134:ad3be0349dc5 1747 /**
<> 134:ad3be0349dc5 1748 * @brief Clear LSE ready interrupt flag
<> 134:ad3be0349dc5 1749 * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY
<> 134:ad3be0349dc5 1750 * @retval None
<> 134:ad3be0349dc5 1751 */
<> 134:ad3be0349dc5 1752 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
<> 134:ad3be0349dc5 1753 {
<> 134:ad3be0349dc5 1754 SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
<> 134:ad3be0349dc5 1755 }
<> 134:ad3be0349dc5 1756
<> 134:ad3be0349dc5 1757 /**
<> 134:ad3be0349dc5 1758 * @brief Clear HSI ready interrupt flag
<> 134:ad3be0349dc5 1759 * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY
<> 134:ad3be0349dc5 1760 * @retval None
<> 134:ad3be0349dc5 1761 */
<> 134:ad3be0349dc5 1762 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
<> 134:ad3be0349dc5 1763 {
<> 134:ad3be0349dc5 1764 SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
<> 134:ad3be0349dc5 1765 }
<> 134:ad3be0349dc5 1766
<> 134:ad3be0349dc5 1767 /**
<> 134:ad3be0349dc5 1768 * @brief Clear HSE ready interrupt flag
<> 134:ad3be0349dc5 1769 * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY
<> 134:ad3be0349dc5 1770 * @retval None
<> 134:ad3be0349dc5 1771 */
<> 134:ad3be0349dc5 1772 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
<> 134:ad3be0349dc5 1773 {
<> 134:ad3be0349dc5 1774 SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
<> 134:ad3be0349dc5 1775 }
<> 134:ad3be0349dc5 1776
<> 134:ad3be0349dc5 1777 /**
<> 134:ad3be0349dc5 1778 * @brief Clear PLL ready interrupt flag
<> 134:ad3be0349dc5 1779 * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY
<> 134:ad3be0349dc5 1780 * @retval None
<> 134:ad3be0349dc5 1781 */
<> 134:ad3be0349dc5 1782 __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
<> 134:ad3be0349dc5 1783 {
<> 134:ad3be0349dc5 1784 SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
<> 134:ad3be0349dc5 1785 }
<> 134:ad3be0349dc5 1786
<> 134:ad3be0349dc5 1787 /**
<> 134:ad3be0349dc5 1788 * @brief Clear HSI14 ready interrupt flag
<> 134:ad3be0349dc5 1789 * @rmtoll CIR HSI14RDYC LL_RCC_ClearFlag_HSI14RDY
<> 134:ad3be0349dc5 1790 * @retval None
<> 134:ad3be0349dc5 1791 */
<> 134:ad3be0349dc5 1792 __STATIC_INLINE void LL_RCC_ClearFlag_HSI14RDY(void)
<> 134:ad3be0349dc5 1793 {
<> 134:ad3be0349dc5 1794 SET_BIT(RCC->CIR, RCC_CIR_HSI14RDYC);
<> 134:ad3be0349dc5 1795 }
<> 134:ad3be0349dc5 1796
<> 134:ad3be0349dc5 1797 #if defined(RCC_HSI48_SUPPORT)
<> 134:ad3be0349dc5 1798 /**
<> 134:ad3be0349dc5 1799 * @brief Clear HSI48 ready interrupt flag
<> 134:ad3be0349dc5 1800 * @rmtoll CIR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY
<> 134:ad3be0349dc5 1801 * @retval None
<> 134:ad3be0349dc5 1802 */
<> 134:ad3be0349dc5 1803 __STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
<> 134:ad3be0349dc5 1804 {
<> 134:ad3be0349dc5 1805 SET_BIT(RCC->CIR, RCC_CIR_HSI48RDYC);
<> 134:ad3be0349dc5 1806 }
<> 134:ad3be0349dc5 1807 #endif /* RCC_HSI48_SUPPORT */
<> 134:ad3be0349dc5 1808
<> 134:ad3be0349dc5 1809 /**
<> 134:ad3be0349dc5 1810 * @brief Clear Clock security system interrupt flag
<> 134:ad3be0349dc5 1811 * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS
<> 134:ad3be0349dc5 1812 * @retval None
<> 134:ad3be0349dc5 1813 */
<> 134:ad3be0349dc5 1814 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
<> 134:ad3be0349dc5 1815 {
<> 134:ad3be0349dc5 1816 SET_BIT(RCC->CIR, RCC_CIR_CSSC);
<> 134:ad3be0349dc5 1817 }
<> 134:ad3be0349dc5 1818
<> 134:ad3be0349dc5 1819 /**
<> 134:ad3be0349dc5 1820 * @brief Check if LSI ready interrupt occurred or not
<> 134:ad3be0349dc5 1821 * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
<> 134:ad3be0349dc5 1822 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 1823 */
<> 134:ad3be0349dc5 1824 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
<> 134:ad3be0349dc5 1825 {
<> 134:ad3be0349dc5 1826 return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));
<> 134:ad3be0349dc5 1827 }
<> 134:ad3be0349dc5 1828
<> 134:ad3be0349dc5 1829 /**
<> 134:ad3be0349dc5 1830 * @brief Check if LSE ready interrupt occurred or not
<> 134:ad3be0349dc5 1831 * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY
<> 134:ad3be0349dc5 1832 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 1833 */
<> 134:ad3be0349dc5 1834 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
<> 134:ad3be0349dc5 1835 {
<> 134:ad3be0349dc5 1836 return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));
<> 134:ad3be0349dc5 1837 }
<> 134:ad3be0349dc5 1838
<> 134:ad3be0349dc5 1839 /**
<> 134:ad3be0349dc5 1840 * @brief Check if HSI ready interrupt occurred or not
<> 134:ad3be0349dc5 1841 * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
<> 134:ad3be0349dc5 1842 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 1843 */
<> 134:ad3be0349dc5 1844 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
<> 134:ad3be0349dc5 1845 {
<> 134:ad3be0349dc5 1846 return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));
<> 134:ad3be0349dc5 1847 }
<> 134:ad3be0349dc5 1848
<> 134:ad3be0349dc5 1849 /**
<> 134:ad3be0349dc5 1850 * @brief Check if HSE ready interrupt occurred or not
<> 134:ad3be0349dc5 1851 * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY
<> 134:ad3be0349dc5 1852 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 1853 */
<> 134:ad3be0349dc5 1854 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
<> 134:ad3be0349dc5 1855 {
<> 134:ad3be0349dc5 1856 return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));
<> 134:ad3be0349dc5 1857 }
<> 134:ad3be0349dc5 1858
<> 134:ad3be0349dc5 1859 /**
<> 134:ad3be0349dc5 1860 * @brief Check if PLL ready interrupt occurred or not
<> 134:ad3be0349dc5 1861 * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
<> 134:ad3be0349dc5 1862 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 1863 */
<> 134:ad3be0349dc5 1864 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
<> 134:ad3be0349dc5 1865 {
<> 134:ad3be0349dc5 1866 return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));
<> 134:ad3be0349dc5 1867 }
<> 134:ad3be0349dc5 1868
<> 134:ad3be0349dc5 1869 /**
<> 134:ad3be0349dc5 1870 * @brief Check if HSI14 ready interrupt occurred or not
<> 134:ad3be0349dc5 1871 * @rmtoll CIR HSI14RDYF LL_RCC_IsActiveFlag_HSI14RDY
<> 134:ad3be0349dc5 1872 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 1873 */
<> 134:ad3be0349dc5 1874 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI14RDY(void)
<> 134:ad3be0349dc5 1875 {
<> 134:ad3be0349dc5 1876 return (READ_BIT(RCC->CIR, RCC_CIR_HSI14RDYF) == (RCC_CIR_HSI14RDYF));
<> 134:ad3be0349dc5 1877 }
<> 134:ad3be0349dc5 1878
<> 134:ad3be0349dc5 1879 #if defined(RCC_HSI48_SUPPORT)
<> 134:ad3be0349dc5 1880 /**
<> 134:ad3be0349dc5 1881 * @brief Check if HSI48 ready interrupt occurred or not
<> 134:ad3be0349dc5 1882 * @rmtoll CIR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY
<> 134:ad3be0349dc5 1883 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 1884 */
<> 134:ad3be0349dc5 1885 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
<> 134:ad3be0349dc5 1886 {
<> 134:ad3be0349dc5 1887 return (READ_BIT(RCC->CIR, RCC_CIR_HSI48RDYF) == (RCC_CIR_HSI48RDYF));
<> 134:ad3be0349dc5 1888 }
<> 134:ad3be0349dc5 1889 #endif /* RCC_HSI48_SUPPORT */
<> 134:ad3be0349dc5 1890
<> 134:ad3be0349dc5 1891 /**
<> 134:ad3be0349dc5 1892 * @brief Check if Clock security system interrupt occurred or not
<> 134:ad3be0349dc5 1893 * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS
<> 134:ad3be0349dc5 1894 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 1895 */
<> 134:ad3be0349dc5 1896 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
<> 134:ad3be0349dc5 1897 {
<> 134:ad3be0349dc5 1898 return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));
<> 134:ad3be0349dc5 1899 }
<> 134:ad3be0349dc5 1900
<> 134:ad3be0349dc5 1901 /**
<> 134:ad3be0349dc5 1902 * @brief Check if RCC flag Independent Watchdog reset is set or not.
<> 134:ad3be0349dc5 1903 * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
<> 134:ad3be0349dc5 1904 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 1905 */
<> 134:ad3be0349dc5 1906 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
<> 134:ad3be0349dc5 1907 {
<> 134:ad3be0349dc5 1908 return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
<> 134:ad3be0349dc5 1909 }
<> 134:ad3be0349dc5 1910
<> 134:ad3be0349dc5 1911 /**
<> 134:ad3be0349dc5 1912 * @brief Check if RCC flag Low Power reset is set or not.
<> 134:ad3be0349dc5 1913 * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
<> 134:ad3be0349dc5 1914 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 1915 */
<> 134:ad3be0349dc5 1916 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
<> 134:ad3be0349dc5 1917 {
<> 134:ad3be0349dc5 1918 return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
<> 134:ad3be0349dc5 1919 }
<> 134:ad3be0349dc5 1920
<> 134:ad3be0349dc5 1921 /**
<> 134:ad3be0349dc5 1922 * @brief Check if RCC flag is set or not.
<> 134:ad3be0349dc5 1923 * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST
<> 134:ad3be0349dc5 1924 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 1925 */
<> 134:ad3be0349dc5 1926 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
<> 134:ad3be0349dc5 1927 {
<> 134:ad3be0349dc5 1928 return (READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF));
<> 134:ad3be0349dc5 1929 }
<> 134:ad3be0349dc5 1930
<> 134:ad3be0349dc5 1931 /**
<> 134:ad3be0349dc5 1932 * @brief Check if RCC flag Pin reset is set or not.
<> 134:ad3be0349dc5 1933 * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
<> 134:ad3be0349dc5 1934 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 1935 */
<> 134:ad3be0349dc5 1936 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
<> 134:ad3be0349dc5 1937 {
<> 134:ad3be0349dc5 1938 return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
<> 134:ad3be0349dc5 1939 }
<> 134:ad3be0349dc5 1940
<> 134:ad3be0349dc5 1941 /**
<> 134:ad3be0349dc5 1942 * @brief Check if RCC flag POR/PDR reset is set or not.
<> 134:ad3be0349dc5 1943 * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST
<> 134:ad3be0349dc5 1944 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 1945 */
<> 134:ad3be0349dc5 1946 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
<> 134:ad3be0349dc5 1947 {
<> 134:ad3be0349dc5 1948 return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
<> 134:ad3be0349dc5 1949 }
<> 134:ad3be0349dc5 1950
<> 134:ad3be0349dc5 1951 /**
<> 134:ad3be0349dc5 1952 * @brief Check if RCC flag Software reset is set or not.
<> 134:ad3be0349dc5 1953 * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
<> 134:ad3be0349dc5 1954 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 1955 */
<> 134:ad3be0349dc5 1956 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
<> 134:ad3be0349dc5 1957 {
<> 134:ad3be0349dc5 1958 return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
<> 134:ad3be0349dc5 1959 }
<> 134:ad3be0349dc5 1960
<> 134:ad3be0349dc5 1961 /**
<> 134:ad3be0349dc5 1962 * @brief Check if RCC flag Window Watchdog reset is set or not.
<> 134:ad3be0349dc5 1963 * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
<> 134:ad3be0349dc5 1964 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 1965 */
<> 134:ad3be0349dc5 1966 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
<> 134:ad3be0349dc5 1967 {
<> 134:ad3be0349dc5 1968 return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
<> 134:ad3be0349dc5 1969 }
<> 134:ad3be0349dc5 1970
<> 134:ad3be0349dc5 1971 #if defined(RCC_CSR_V18PWRRSTF)
<> 134:ad3be0349dc5 1972 /**
<> 134:ad3be0349dc5 1973 * @brief Check if RCC Reset flag of the 1.8 V domain is set or not.
<> 134:ad3be0349dc5 1974 * @rmtoll CSR V18PWRRSTF LL_RCC_IsActiveFlag_V18PWRRST
<> 134:ad3be0349dc5 1975 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 1976 */
<> 134:ad3be0349dc5 1977 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_V18PWRRST(void)
<> 134:ad3be0349dc5 1978 {
<> 134:ad3be0349dc5 1979 return (READ_BIT(RCC->CSR, RCC_CSR_V18PWRRSTF) == (RCC_CSR_V18PWRRSTF));
<> 134:ad3be0349dc5 1980 }
<> 134:ad3be0349dc5 1981 #endif /* RCC_CSR_V18PWRRSTF */
<> 134:ad3be0349dc5 1982
<> 134:ad3be0349dc5 1983 /**
<> 134:ad3be0349dc5 1984 * @brief Set RMVF bit to clear the reset flags.
<> 134:ad3be0349dc5 1985 * @rmtoll CSR RMVF LL_RCC_ClearResetFlags
<> 134:ad3be0349dc5 1986 * @retval None
<> 134:ad3be0349dc5 1987 */
<> 134:ad3be0349dc5 1988 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
<> 134:ad3be0349dc5 1989 {
<> 134:ad3be0349dc5 1990 SET_BIT(RCC->CSR, RCC_CSR_RMVF);
<> 134:ad3be0349dc5 1991 }
<> 134:ad3be0349dc5 1992
<> 134:ad3be0349dc5 1993 /**
<> 134:ad3be0349dc5 1994 * @}
<> 134:ad3be0349dc5 1995 */
<> 134:ad3be0349dc5 1996
<> 134:ad3be0349dc5 1997 /** @defgroup RCC_LL_EF_IT_Management IT Management
<> 134:ad3be0349dc5 1998 * @{
<> 134:ad3be0349dc5 1999 */
<> 134:ad3be0349dc5 2000
<> 134:ad3be0349dc5 2001 /**
<> 134:ad3be0349dc5 2002 * @brief Enable LSI ready interrupt
<> 134:ad3be0349dc5 2003 * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY
<> 134:ad3be0349dc5 2004 * @retval None
<> 134:ad3be0349dc5 2005 */
<> 134:ad3be0349dc5 2006 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
<> 134:ad3be0349dc5 2007 {
<> 134:ad3be0349dc5 2008 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
<> 134:ad3be0349dc5 2009 }
<> 134:ad3be0349dc5 2010
<> 134:ad3be0349dc5 2011 /**
<> 134:ad3be0349dc5 2012 * @brief Enable LSE ready interrupt
<> 134:ad3be0349dc5 2013 * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY
<> 134:ad3be0349dc5 2014 * @retval None
<> 134:ad3be0349dc5 2015 */
<> 134:ad3be0349dc5 2016 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
<> 134:ad3be0349dc5 2017 {
<> 134:ad3be0349dc5 2018 SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
<> 134:ad3be0349dc5 2019 }
<> 134:ad3be0349dc5 2020
<> 134:ad3be0349dc5 2021 /**
<> 134:ad3be0349dc5 2022 * @brief Enable HSI ready interrupt
<> 134:ad3be0349dc5 2023 * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY
<> 134:ad3be0349dc5 2024 * @retval None
<> 134:ad3be0349dc5 2025 */
<> 134:ad3be0349dc5 2026 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
<> 134:ad3be0349dc5 2027 {
<> 134:ad3be0349dc5 2028 SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
<> 134:ad3be0349dc5 2029 }
<> 134:ad3be0349dc5 2030
<> 134:ad3be0349dc5 2031 /**
<> 134:ad3be0349dc5 2032 * @brief Enable HSE ready interrupt
<> 134:ad3be0349dc5 2033 * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY
<> 134:ad3be0349dc5 2034 * @retval None
<> 134:ad3be0349dc5 2035 */
<> 134:ad3be0349dc5 2036 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
<> 134:ad3be0349dc5 2037 {
<> 134:ad3be0349dc5 2038 SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
<> 134:ad3be0349dc5 2039 }
<> 134:ad3be0349dc5 2040
<> 134:ad3be0349dc5 2041 /**
<> 134:ad3be0349dc5 2042 * @brief Enable PLL ready interrupt
<> 134:ad3be0349dc5 2043 * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY
<> 134:ad3be0349dc5 2044 * @retval None
<> 134:ad3be0349dc5 2045 */
<> 134:ad3be0349dc5 2046 __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
<> 134:ad3be0349dc5 2047 {
<> 134:ad3be0349dc5 2048 SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
<> 134:ad3be0349dc5 2049 }
<> 134:ad3be0349dc5 2050
<> 134:ad3be0349dc5 2051 /**
<> 134:ad3be0349dc5 2052 * @brief Enable HSI14 ready interrupt
<> 134:ad3be0349dc5 2053 * @rmtoll CIR HSI14RDYIE LL_RCC_EnableIT_HSI14RDY
<> 134:ad3be0349dc5 2054 * @retval None
<> 134:ad3be0349dc5 2055 */
<> 134:ad3be0349dc5 2056 __STATIC_INLINE void LL_RCC_EnableIT_HSI14RDY(void)
<> 134:ad3be0349dc5 2057 {
<> 134:ad3be0349dc5 2058 SET_BIT(RCC->CIR, RCC_CIR_HSI14RDYIE);
<> 134:ad3be0349dc5 2059 }
<> 134:ad3be0349dc5 2060
<> 134:ad3be0349dc5 2061 #if defined(RCC_HSI48_SUPPORT)
<> 134:ad3be0349dc5 2062 /**
<> 134:ad3be0349dc5 2063 * @brief Enable HSI48 ready interrupt
<> 134:ad3be0349dc5 2064 * @rmtoll CIR HSI48RDYIE LL_RCC_EnableIT_HSI48RDY
<> 134:ad3be0349dc5 2065 * @retval None
<> 134:ad3be0349dc5 2066 */
<> 134:ad3be0349dc5 2067 __STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
<> 134:ad3be0349dc5 2068 {
<> 134:ad3be0349dc5 2069 SET_BIT(RCC->CIR, RCC_CIR_HSI48RDYIE);
<> 134:ad3be0349dc5 2070 }
<> 134:ad3be0349dc5 2071 #endif /* RCC_HSI48_SUPPORT */
<> 134:ad3be0349dc5 2072
<> 134:ad3be0349dc5 2073 /**
<> 134:ad3be0349dc5 2074 * @brief Disable LSI ready interrupt
<> 134:ad3be0349dc5 2075 * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY
<> 134:ad3be0349dc5 2076 * @retval None
<> 134:ad3be0349dc5 2077 */
<> 134:ad3be0349dc5 2078 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
<> 134:ad3be0349dc5 2079 {
<> 134:ad3be0349dc5 2080 CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
<> 134:ad3be0349dc5 2081 }
<> 134:ad3be0349dc5 2082
<> 134:ad3be0349dc5 2083 /**
<> 134:ad3be0349dc5 2084 * @brief Disable LSE ready interrupt
<> 134:ad3be0349dc5 2085 * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY
<> 134:ad3be0349dc5 2086 * @retval None
<> 134:ad3be0349dc5 2087 */
<> 134:ad3be0349dc5 2088 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
<> 134:ad3be0349dc5 2089 {
<> 134:ad3be0349dc5 2090 CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
<> 134:ad3be0349dc5 2091 }
<> 134:ad3be0349dc5 2092
<> 134:ad3be0349dc5 2093 /**
<> 134:ad3be0349dc5 2094 * @brief Disable HSI ready interrupt
<> 134:ad3be0349dc5 2095 * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY
<> 134:ad3be0349dc5 2096 * @retval None
<> 134:ad3be0349dc5 2097 */
<> 134:ad3be0349dc5 2098 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
<> 134:ad3be0349dc5 2099 {
<> 134:ad3be0349dc5 2100 CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
<> 134:ad3be0349dc5 2101 }
<> 134:ad3be0349dc5 2102
<> 134:ad3be0349dc5 2103 /**
<> 134:ad3be0349dc5 2104 * @brief Disable HSE ready interrupt
<> 134:ad3be0349dc5 2105 * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY
<> 134:ad3be0349dc5 2106 * @retval None
<> 134:ad3be0349dc5 2107 */
<> 134:ad3be0349dc5 2108 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
<> 134:ad3be0349dc5 2109 {
<> 134:ad3be0349dc5 2110 CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
<> 134:ad3be0349dc5 2111 }
<> 134:ad3be0349dc5 2112
<> 134:ad3be0349dc5 2113 /**
<> 134:ad3be0349dc5 2114 * @brief Disable PLL ready interrupt
<> 134:ad3be0349dc5 2115 * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY
<> 134:ad3be0349dc5 2116 * @retval None
<> 134:ad3be0349dc5 2117 */
<> 134:ad3be0349dc5 2118 __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
<> 134:ad3be0349dc5 2119 {
<> 134:ad3be0349dc5 2120 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
<> 134:ad3be0349dc5 2121 }
<> 134:ad3be0349dc5 2122
<> 134:ad3be0349dc5 2123 /**
<> 134:ad3be0349dc5 2124 * @brief Disable HSI14 ready interrupt
<> 134:ad3be0349dc5 2125 * @rmtoll CIR HSI14RDYIE LL_RCC_DisableIT_HSI14RDY
<> 134:ad3be0349dc5 2126 * @retval None
<> 134:ad3be0349dc5 2127 */
<> 134:ad3be0349dc5 2128 __STATIC_INLINE void LL_RCC_DisableIT_HSI14RDY(void)
<> 134:ad3be0349dc5 2129 {
<> 134:ad3be0349dc5 2130 CLEAR_BIT(RCC->CIR, RCC_CIR_HSI14RDYIE);
<> 134:ad3be0349dc5 2131 }
<> 134:ad3be0349dc5 2132
<> 134:ad3be0349dc5 2133 #if defined(RCC_HSI48_SUPPORT)
<> 134:ad3be0349dc5 2134 /**
<> 134:ad3be0349dc5 2135 * @brief Disable HSI48 ready interrupt
<> 134:ad3be0349dc5 2136 * @rmtoll CIR HSI48RDYIE LL_RCC_DisableIT_HSI48RDY
<> 134:ad3be0349dc5 2137 * @retval None
<> 134:ad3be0349dc5 2138 */
<> 134:ad3be0349dc5 2139 __STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
<> 134:ad3be0349dc5 2140 {
<> 134:ad3be0349dc5 2141 CLEAR_BIT(RCC->CIR, RCC_CIR_HSI48RDYIE);
<> 134:ad3be0349dc5 2142 }
<> 134:ad3be0349dc5 2143 #endif /* RCC_HSI48_SUPPORT */
<> 134:ad3be0349dc5 2144
<> 134:ad3be0349dc5 2145 /**
<> 134:ad3be0349dc5 2146 * @brief Checks if LSI ready interrupt source is enabled or disabled.
<> 134:ad3be0349dc5 2147 * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
<> 134:ad3be0349dc5 2148 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 2149 */
<> 134:ad3be0349dc5 2150 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
<> 134:ad3be0349dc5 2151 {
<> 134:ad3be0349dc5 2152 return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));
<> 134:ad3be0349dc5 2153 }
<> 134:ad3be0349dc5 2154
<> 134:ad3be0349dc5 2155 /**
<> 134:ad3be0349dc5 2156 * @brief Checks if LSE ready interrupt source is enabled or disabled.
<> 134:ad3be0349dc5 2157 * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY
<> 134:ad3be0349dc5 2158 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 2159 */
<> 134:ad3be0349dc5 2160 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
<> 134:ad3be0349dc5 2161 {
<> 134:ad3be0349dc5 2162 return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));
<> 134:ad3be0349dc5 2163 }
<> 134:ad3be0349dc5 2164
<> 134:ad3be0349dc5 2165 /**
<> 134:ad3be0349dc5 2166 * @brief Checks if HSI ready interrupt source is enabled or disabled.
<> 134:ad3be0349dc5 2167 * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
<> 134:ad3be0349dc5 2168 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 2169 */
<> 134:ad3be0349dc5 2170 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
<> 134:ad3be0349dc5 2171 {
<> 134:ad3be0349dc5 2172 return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));
<> 134:ad3be0349dc5 2173 }
<> 134:ad3be0349dc5 2174
<> 134:ad3be0349dc5 2175 /**
<> 134:ad3be0349dc5 2176 * @brief Checks if HSE ready interrupt source is enabled or disabled.
<> 134:ad3be0349dc5 2177 * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY
<> 134:ad3be0349dc5 2178 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 2179 */
<> 134:ad3be0349dc5 2180 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
<> 134:ad3be0349dc5 2181 {
<> 134:ad3be0349dc5 2182 return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));
<> 134:ad3be0349dc5 2183 }
<> 134:ad3be0349dc5 2184
<> 134:ad3be0349dc5 2185 /**
<> 134:ad3be0349dc5 2186 * @brief Checks if PLL ready interrupt source is enabled or disabled.
<> 134:ad3be0349dc5 2187 * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
<> 134:ad3be0349dc5 2188 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 2189 */
<> 134:ad3be0349dc5 2190 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
<> 134:ad3be0349dc5 2191 {
<> 134:ad3be0349dc5 2192 return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));
<> 134:ad3be0349dc5 2193 }
<> 134:ad3be0349dc5 2194
<> 134:ad3be0349dc5 2195 /**
<> 134:ad3be0349dc5 2196 * @brief Checks if HSI14 ready interrupt source is enabled or disabled.
<> 134:ad3be0349dc5 2197 * @rmtoll CIR HSI14RDYIE LL_RCC_IsEnabledIT_HSI14RDY
<> 134:ad3be0349dc5 2198 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 2199 */
<> 134:ad3be0349dc5 2200 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI14RDY(void)
<> 134:ad3be0349dc5 2201 {
<> 134:ad3be0349dc5 2202 return (READ_BIT(RCC->CIR, RCC_CIR_HSI14RDYIE) == (RCC_CIR_HSI14RDYIE));
<> 134:ad3be0349dc5 2203 }
<> 134:ad3be0349dc5 2204
<> 134:ad3be0349dc5 2205 #if defined(RCC_HSI48_SUPPORT)
<> 134:ad3be0349dc5 2206 /**
<> 134:ad3be0349dc5 2207 * @brief Checks if HSI48 ready interrupt source is enabled or disabled.
<> 134:ad3be0349dc5 2208 * @rmtoll CIR HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY
<> 134:ad3be0349dc5 2209 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 2210 */
<> 134:ad3be0349dc5 2211 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void)
<> 134:ad3be0349dc5 2212 {
<> 134:ad3be0349dc5 2213 return (READ_BIT(RCC->CIR, RCC_CIR_HSI48RDYIE) == (RCC_CIR_HSI48RDYIE));
<> 134:ad3be0349dc5 2214 }
<> 134:ad3be0349dc5 2215 #endif /* RCC_HSI48_SUPPORT */
<> 134:ad3be0349dc5 2216
<> 134:ad3be0349dc5 2217 /**
<> 134:ad3be0349dc5 2218 * @}
<> 134:ad3be0349dc5 2219 */
<> 134:ad3be0349dc5 2220
<> 134:ad3be0349dc5 2221 #if defined(USE_FULL_LL_DRIVER)
<> 134:ad3be0349dc5 2222 /** @defgroup RCC_LL_EF_Init De-initialization function
<> 134:ad3be0349dc5 2223 * @{
<> 134:ad3be0349dc5 2224 */
<> 134:ad3be0349dc5 2225 ErrorStatus LL_RCC_DeInit(void);
<> 134:ad3be0349dc5 2226 /**
<> 134:ad3be0349dc5 2227 * @}
<> 134:ad3be0349dc5 2228 */
<> 134:ad3be0349dc5 2229
<> 134:ad3be0349dc5 2230 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
<> 134:ad3be0349dc5 2231 * @{
<> 134:ad3be0349dc5 2232 */
<> 134:ad3be0349dc5 2233 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
<> 134:ad3be0349dc5 2234 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
<> 134:ad3be0349dc5 2235 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
<> 134:ad3be0349dc5 2236 #if defined(USB_OTG_FS) || defined(USB)
<> 134:ad3be0349dc5 2237 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
<> 134:ad3be0349dc5 2238 #endif /* USB_OTG_FS || USB */
<> 134:ad3be0349dc5 2239 #if defined(CEC)
<> 134:ad3be0349dc5 2240 uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource);
<> 134:ad3be0349dc5 2241 #endif /* CEC */
<> 134:ad3be0349dc5 2242 /**
<> 134:ad3be0349dc5 2243 * @}
<> 134:ad3be0349dc5 2244 */
<> 134:ad3be0349dc5 2245 #endif /* USE_FULL_LL_DRIVER */
<> 134:ad3be0349dc5 2246
<> 134:ad3be0349dc5 2247 /**
<> 134:ad3be0349dc5 2248 * @}
<> 134:ad3be0349dc5 2249 */
<> 134:ad3be0349dc5 2250
<> 134:ad3be0349dc5 2251 /**
<> 134:ad3be0349dc5 2252 * @}
<> 134:ad3be0349dc5 2253 */
<> 134:ad3be0349dc5 2254
<> 134:ad3be0349dc5 2255 #endif /* RCC */
<> 134:ad3be0349dc5 2256
<> 134:ad3be0349dc5 2257 /**
<> 134:ad3be0349dc5 2258 * @}
<> 134:ad3be0349dc5 2259 */
<> 134:ad3be0349dc5 2260
<> 134:ad3be0349dc5 2261 #ifdef __cplusplus
<> 134:ad3be0349dc5 2262 }
<> 134:ad3be0349dc5 2263 #endif
<> 134:ad3be0349dc5 2264
<> 134:ad3be0349dc5 2265 #endif /* __STM32F0xx_LL_RCC_H */
<> 134:ad3be0349dc5 2266
<> 134:ad3be0349dc5 2267 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/