mbed official / mbed

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

TARGET_MAX32600MBED/TARGET_Maxim/TARGET_MAX32600/device/pt_regs.h@138:093f2bd7b9eb, 2017-03-14 (annotated)

Committer:
<>
Date:
Tue Mar 14 16:20:51 2017 +0000
Revision:
138:093f2bd7b9eb
Parent:
128:9bcdf88f62b0 
Release 138 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3716: fix for issue #3715: correction in startup files for ARM and IAR, alignment of system_stm32f429xx.c files https://github.com/ARMmbed/mbed-os/pull/3716

3741: STM32 remove warning in hal_tick_32b.c file https://github.com/ARMmbed/mbed-os/pull/3741

3780: STM32L4 : Fix GPIO G port compatibility https://github.com/ARMmbed/mbed-os/pull/3780

3831: NCS36510: SPISLAVE enabled (Conflict resolved) https://github.com/ARMmbed/mbed-os/pull/3831

3836: Allow to redefine nRF's PSTORAGE_NUM_OF_PAGES outside of the mbed-os https://github.com/ARMmbed/mbed-os/pull/3836

3840: STM32: gpio SPEED - always set High Speed by default https://github.com/ARMmbed/mbed-os/pull/3840

3844: STM32 GPIO: Typo correction. Update comment (GPIO_IP_WITHOUT_BRR) https://github.com/ARMmbed/mbed-os/pull/3844

3850: STM32: change spi error to debug warning https://github.com/ARMmbed/mbed-os/pull/3850

3860: Define GPIO_IP_WITHOUT_BRR for xDot platform https://github.com/ARMmbed/mbed-os/pull/3860

3880: DISCO_F469NI: allow the use of CAN2 instance when CAN1 is not activated https://github.com/ARMmbed/mbed-os/pull/3880

3795: Fix pwm period calc https://github.com/ARMmbed/mbed-os/pull/3795

3828: STM32 CAN API: correct format and type https://github.com/ARMmbed/mbed-os/pull/3828

3842: TARGET_NRF: corrected spi_init() to properly handle re-initialization https://github.com/ARMmbed/mbed-os/pull/3842

3843: STM32L476xG: set APB2 clock to 80MHz (instead of 40MHz) https://github.com/ARMmbed/mbed-os/pull/3843

3879: NUCLEO_F446ZE: Add missing AnalogIn pins on PF_3, PF_5 and PF_10. https://github.com/ARMmbed/mbed-os/pull/3879

3902: Fix heap and stack size for NUCLEO_F746ZG https://github.com/ARMmbed/mbed-os/pull/3902

3829: can_write(): return error code when no tx mailboxes are available https://github.com/ARMmbed/mbed-os/pull/3829

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 /*******************************************************************************
<> 128:9bcdf88f62b0 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
<> 128:9bcdf88f62b0 3 *
<> 128:9bcdf88f62b0 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 128:9bcdf88f62b0 5 * copy of this software and associated documentation files (the "Software"),
<> 128:9bcdf88f62b0 6 * to deal in the Software without restriction, including without limitation
<> 128:9bcdf88f62b0 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 128:9bcdf88f62b0 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 128:9bcdf88f62b0 9 * Software is furnished to do so, subject to the following conditions:
<> 128:9bcdf88f62b0 10 *
<> 128:9bcdf88f62b0 11 * The above copyright notice and this permission notice shall be included
<> 128:9bcdf88f62b0 12 * in all copies or substantial portions of the Software.
<> 128:9bcdf88f62b0 13 *
<> 128:9bcdf88f62b0 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 128:9bcdf88f62b0 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 128:9bcdf88f62b0 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 128:9bcdf88f62b0 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 128:9bcdf88f62b0 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 128:9bcdf88f62b0 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 128:9bcdf88f62b0 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 128:9bcdf88f62b0 21 *
<> 128:9bcdf88f62b0 22 * Except as contained in this notice, the name of Maxim Integrated
<> 128:9bcdf88f62b0 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 128:9bcdf88f62b0 24 * Products, Inc. Branding Policy.
<> 128:9bcdf88f62b0 25 *
<> 128:9bcdf88f62b0 26 * The mere transfer of this software does not imply any licenses
<> 128:9bcdf88f62b0 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 128:9bcdf88f62b0 28 * trademarks, maskwork rights, or any other form of intellectual
<> 128:9bcdf88f62b0 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 128:9bcdf88f62b0 30 * ownership rights.
<> 128:9bcdf88f62b0 31 *******************************************************************************
<> 128:9bcdf88f62b0 32 */
<> 128:9bcdf88f62b0 33
<> 128:9bcdf88f62b0 34 #ifndef _MXC_PT_REGS_H_
<> 128:9bcdf88f62b0 35 #define _MXC_PT_REGS_H_
<> 128:9bcdf88f62b0 36
<> 128:9bcdf88f62b0 37 #ifdef __cplusplus
<> 128:9bcdf88f62b0 38 extern "C" {
<> 128:9bcdf88f62b0 39 #endif
<> 128:9bcdf88f62b0 40
<> 128:9bcdf88f62b0 41 #include <stdint.h>
<> 128:9bcdf88f62b0 42
<> 128:9bcdf88f62b0 43 /**
<> 128:9bcdf88f62b0 44 * @file pt_regs.h
<> 128:9bcdf88f62b0 45 * @addtogroup pt PT
<> 128:9bcdf88f62b0 46 * @{
<> 128:9bcdf88f62b0 47 */
<> 128:9bcdf88f62b0 48
<> 128:9bcdf88f62b0 49 typedef struct {
<> 128:9bcdf88f62b0 50 __IO uint32_t ctrl;
<> 128:9bcdf88f62b0 51 __IO uint32_t resync;
<> 128:9bcdf88f62b0 52 } mxc_ptg_regs_t;
<> 128:9bcdf88f62b0 53
<> 128:9bcdf88f62b0 54 /* Offset Register Description
<> 128:9bcdf88f62b0 55 ====== ================================================== */
<> 128:9bcdf88f62b0 56 typedef struct {
<> 128:9bcdf88f62b0 57 __IO uint32_t rate_length; /* 0x0000 Pulse train Output length and rate */
<> 128:9bcdf88f62b0 58 __IO uint32_t train; /* 0x0004 Pulse Train Output Pattern */
<> 128:9bcdf88f62b0 59 } mxc_pt_regs_t;
<> 128:9bcdf88f62b0 60
<> 128:9bcdf88f62b0 61 /*
<> 128:9bcdf88f62b0 62 Register offsets for module PT.
<> 128:9bcdf88f62b0 63 */
<> 128:9bcdf88f62b0 64 #define MXC_R_PTG_OFFS_CTRL ((uint32_t)0x00000000UL)
<> 128:9bcdf88f62b0 65 #define MXC_R_PTG_OFFS_RESYNC ((uint32_t)0x00000004UL)
<> 128:9bcdf88f62b0 66 #define MXC_R_PT_OFFS_RATE_LENGTH ((uint32_t)0x00000000UL)
<> 128:9bcdf88f62b0 67 #define MXC_R_PT_OFFS_TRAIN ((uint32_t)0x00000004UL)
<> 128:9bcdf88f62b0 68
<> 128:9bcdf88f62b0 69
<> 128:9bcdf88f62b0 70 /*
<> 128:9bcdf88f62b0 71 Field positions and masks for module PT.
<> 128:9bcdf88f62b0 72 */
<> 128:9bcdf88f62b0 73 #define MXC_F_PT_CTRL_ENABLE_ALL_POS 1
<> 128:9bcdf88f62b0 74 #define MXC_F_PT_CTRL_ENABLE_ALL ((uint32_t)(0x00000001UL << MXC_F_PT_CTRL_ENABLE_ALL_POS))
<> 128:9bcdf88f62b0 75
<> 128:9bcdf88f62b0 76 #define MXC_F_PT_RESYNC_PT0_POS 0
<> 128:9bcdf88f62b0 77 #define MXC_F_PT_RESYNC_PT0 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT0_POS))
<> 128:9bcdf88f62b0 78 #define MXC_F_PT_RESYNC_PT1_POS 1
<> 128:9bcdf88f62b0 79 #define MXC_F_PT_RESYNC_PT1 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT1_POS))
<> 128:9bcdf88f62b0 80 #define MXC_F_PT_RESYNC_PT2_POS 2
<> 128:9bcdf88f62b0 81 #define MXC_F_PT_RESYNC_PT2 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT2_POS))
<> 128:9bcdf88f62b0 82 #define MXC_F_PT_RESYNC_PT3_POS 3
<> 128:9bcdf88f62b0 83 #define MXC_F_PT_RESYNC_PT3 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT3_POS))
<> 128:9bcdf88f62b0 84 #define MXC_F_PT_RESYNC_PT4_POS 4
<> 128:9bcdf88f62b0 85 #define MXC_F_PT_RESYNC_PT4 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT4_POS))
<> 128:9bcdf88f62b0 86 #define MXC_F_PT_RESYNC_PT5_POS 5
<> 128:9bcdf88f62b0 87 #define MXC_F_PT_RESYNC_PT5 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT5_POS))
<> 128:9bcdf88f62b0 88 #define MXC_F_PT_RESYNC_PT6_POS 6
<> 128:9bcdf88f62b0 89 #define MXC_F_PT_RESYNC_PT6 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT6_POS))
<> 128:9bcdf88f62b0 90 #define MXC_F_PT_RESYNC_PT7_POS 7
<> 128:9bcdf88f62b0 91 #define MXC_F_PT_RESYNC_PT7 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT7_POS))
<> 128:9bcdf88f62b0 92
<> 128:9bcdf88f62b0 93 #define MXC_F_PT_RATE_LENGTH_RATE_CONTROL_POS 0
<> 128:9bcdf88f62b0 94 #define MXC_F_PT_RATE_LENGTH_RATE_CONTROL ((uint32_t)(0x07FFFFFFUL << MXC_F_PT_RATE_LENGTH_RATE_CONTROL_POS))
<> 128:9bcdf88f62b0 95 #define MXC_F_PT_RATE_LENGTH_MODE_POS 27
<> 128:9bcdf88f62b0 96 #define MXC_F_PT_RATE_LENGTH_MODE ((uint32_t)(0x0000001FUL << MXC_F_PT_RATE_LENGTH_MODE_POS))
<> 128:9bcdf88f62b0 97
<> 128:9bcdf88f62b0 98 /*
<> 128:9bcdf88f62b0 99 Field values and shifted values for module PT.
<> 128:9bcdf88f62b0 100 */
<> 128:9bcdf88f62b0 101 #define MXC_V_PT_RATE_LENGTH_MODE_32_BIT_PATTERN ((uint32_t)(0x0x00000000UL))
<> 128:9bcdf88f62b0 102 #define MXC_V_PT_RATE_LENGTH_MODE_SQUARE_WAVE ((uint32_t)(0x0x00000001UL))
<> 128:9bcdf88f62b0 103 #define MXC_V_PT_RATE_LENGTH_MODE_2_BIT_PATTERN ((uint32_t)(0x0x00000002UL))
<> 128:9bcdf88f62b0 104 #define MXC_V_PT_RATE_LENGTH_MODE_3_BIT_PATTERN ((uint32_t)(0x0x00000003UL))
<> 128:9bcdf88f62b0 105 #define MXC_V_PT_RATE_LENGTH_MODE_4_BIT_PATTERN ((uint32_t)(0x0x00000004UL))
<> 128:9bcdf88f62b0 106 #define MXC_V_PT_RATE_LENGTH_MODE_5_BIT_PATTERN ((uint32_t)(0x0x00000005UL))
<> 128:9bcdf88f62b0 107 #define MXC_V_PT_RATE_LENGTH_MODE_6_BIT_PATTERN ((uint32_t)(0x0x00000006UL))
<> 128:9bcdf88f62b0 108 #define MXC_V_PT_RATE_LENGTH_MODE_7_BIT_PATTERN ((uint32_t)(0x0x00000007UL))
<> 128:9bcdf88f62b0 109 #define MXC_V_PT_RATE_LENGTH_MODE_8_BIT_PATTERN ((uint32_t)(0x0x00000008UL))
<> 128:9bcdf88f62b0 110 #define MXC_V_PT_RATE_LENGTH_MODE_9_BIT_PATTERN ((uint32_t)(0x0x00000009UL))
<> 128:9bcdf88f62b0 111 #define MXC_V_PT_RATE_LENGTH_MODE_10_BIT_PATTERN ((uint32_t)(0x0x00000010UL))
<> 128:9bcdf88f62b0 112 #define MXC_V_PT_RATE_LENGTH_MODE_11_BIT_PATTERN ((uint32_t)(0x0x00000011UL))
<> 128:9bcdf88f62b0 113 #define MXC_V_PT_RATE_LENGTH_MODE_12_BIT_PATTERN ((uint32_t)(0x0x00000012UL))
<> 128:9bcdf88f62b0 114 #define MXC_V_PT_RATE_LENGTH_MODE_13_BIT_PATTERN ((uint32_t)(0x0x00000013UL))
<> 128:9bcdf88f62b0 115 #define MXC_V_PT_RATE_LENGTH_MODE_14_BIT_PATTERN ((uint32_t)(0x0x00000014UL))
<> 128:9bcdf88f62b0 116 #define MXC_V_PT_RATE_LENGTH_MODE_15_BIT_PATTERN ((uint32_t)(0x0x00000015UL))
<> 128:9bcdf88f62b0 117 #define MXC_V_PT_RATE_LENGTH_MODE_16_BIT_PATTERN ((uint32_t)(0x0x00000016UL))
<> 128:9bcdf88f62b0 118 #define MXC_V_PT_RATE_LENGTH_MODE_17_BIT_PATTERN ((uint32_t)(0x0x00000017UL))
<> 128:9bcdf88f62b0 119 #define MXC_V_PT_RATE_LENGTH_MODE_18_BIT_PATTERN ((uint32_t)(0x0x00000018UL))
<> 128:9bcdf88f62b0 120 #define MXC_V_PT_RATE_LENGTH_MODE_19_BIT_PATTERN ((uint32_t)(0x0x00000019UL))
<> 128:9bcdf88f62b0 121 #define MXC_V_PT_RATE_LENGTH_MODE_20_BIT_PATTERN ((uint32_t)(0x0x00000020UL))
<> 128:9bcdf88f62b0 122 #define MXC_V_PT_RATE_LENGTH_MODE_21_BIT_PATTERN ((uint32_t)(0x0x00000021UL))
<> 128:9bcdf88f62b0 123 #define MXC_V_PT_RATE_LENGTH_MODE_22_BIT_PATTERN ((uint32_t)(0x0x00000022UL))
<> 128:9bcdf88f62b0 124 #define MXC_V_PT_RATE_LENGTH_MODE_23_BIT_PATTERN ((uint32_t)(0x0x00000023UL))
<> 128:9bcdf88f62b0 125 #define MXC_V_PT_RATE_LENGTH_MODE_24_BIT_PATTERN ((uint32_t)(0x0x00000024UL))
<> 128:9bcdf88f62b0 126 #define MXC_V_PT_RATE_LENGTH_MODE_25_BIT_PATTERN ((uint32_t)(0x0x00000025UL))
<> 128:9bcdf88f62b0 127 #define MXC_V_PT_RATE_LENGTH_MODE_26_BIT_PATTERN ((uint32_t)(0x0x00000026UL))
<> 128:9bcdf88f62b0 128 #define MXC_V_PT_RATE_LENGTH_MODE_27_BIT_PATTERN ((uint32_t)(0x0x00000027UL))
<> 128:9bcdf88f62b0 129 #define MXC_V_PT_RATE_LENGTH_MODE_28_BIT_PATTERN ((uint32_t)(0x0x00000028UL))
<> 128:9bcdf88f62b0 130 #define MXC_V_PT_RATE_LENGTH_MODE_29_BIT_PATTERN ((uint32_t)(0x0x00000029UL))
<> 128:9bcdf88f62b0 131 #define MXC_V_PT_RATE_LENGTH_MODE_30_BIT_PATTERN ((uint32_t)(0x0x00000030UL))
<> 128:9bcdf88f62b0 132 #define MXC_V_PT_RATE_LENGTH_MODE_31_BIT_PATTERN ((uint32_t)(0x0x00000031UL))
<> 128:9bcdf88f62b0 133
<> 128:9bcdf88f62b0 134 #define MXC_S_PT_RATE_LENGTH_MODE_32_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_32_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
<> 128:9bcdf88f62b0 135 #define MXC_S_PT_RATE_LENGTH_MODE_SQUARE_WAVE ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_SQUARE_WAVE << MXC_F_PT_RATE_LENGTH_MODE_POS))
<> 128:9bcdf88f62b0 136 #define MXC_S_PT_RATE_LENGTH_MODE_2_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_2_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
<> 128:9bcdf88f62b0 137 #define MXC_S_PT_RATE_LENGTH_MODE_3_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_3_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
<> 128:9bcdf88f62b0 138 #define MXC_S_PT_RATE_LENGTH_MODE_4_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_4_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
<> 128:9bcdf88f62b0 139 #define MXC_S_PT_RATE_LENGTH_MODE_5_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_5_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
<> 128:9bcdf88f62b0 140 #define MXC_S_PT_RATE_LENGTH_MODE_6_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_6_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
<> 128:9bcdf88f62b0 141 #define MXC_S_PT_RATE_LENGTH_MODE_7_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_7_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
<> 128:9bcdf88f62b0 142 #define MXC_S_PT_RATE_LENGTH_MODE_8_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_8_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
<> 128:9bcdf88f62b0 143 #define MXC_S_PT_RATE_LENGTH_MODE_9_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_9_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
<> 128:9bcdf88f62b0 144 #define MXC_S_PT_RATE_LENGTH_MODE_10_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_10_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
<> 128:9bcdf88f62b0 145 #define MXC_S_PT_RATE_LENGTH_MODE_11_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_11_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
<> 128:9bcdf88f62b0 146 #define MXC_S_PT_RATE_LENGTH_MODE_12_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_12_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
<> 128:9bcdf88f62b0 147 #define MXC_S_PT_RATE_LENGTH_MODE_13_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_13_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
<> 128:9bcdf88f62b0 148 #define MXC_S_PT_RATE_LENGTH_MODE_14_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_14_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
<> 128:9bcdf88f62b0 149 #define MXC_S_PT_RATE_LENGTH_MODE_15_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_15_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
<> 128:9bcdf88f62b0 150 #define MXC_S_PT_RATE_LENGTH_MODE_16_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_16_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
<> 128:9bcdf88f62b0 151 #define MXC_S_PT_RATE_LENGTH_MODE_17_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_17_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
<> 128:9bcdf88f62b0 152 #define MXC_S_PT_RATE_LENGTH_MODE_18_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_18_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
<> 128:9bcdf88f62b0 153 #define MXC_S_PT_RATE_LENGTH_MODE_19_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_19_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
<> 128:9bcdf88f62b0 154 #define MXC_S_PT_RATE_LENGTH_MODE_20_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_20_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
<> 128:9bcdf88f62b0 155 #define MXC_S_PT_RATE_LENGTH_MODE_21_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_21_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
<> 128:9bcdf88f62b0 156 #define MXC_S_PT_RATE_LENGTH_MODE_22_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_22_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
<> 128:9bcdf88f62b0 157 #define MXC_S_PT_RATE_LENGTH_MODE_23_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_23_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
<> 128:9bcdf88f62b0 158 #define MXC_S_PT_RATE_LENGTH_MODE_24_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_24_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
<> 128:9bcdf88f62b0 159 #define MXC_S_PT_RATE_LENGTH_MODE_25_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_25_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
<> 128:9bcdf88f62b0 160 #define MXC_S_PT_RATE_LENGTH_MODE_26_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_26_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
<> 128:9bcdf88f62b0 161 #define MXC_S_PT_RATE_LENGTH_MODE_27_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_27_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
<> 128:9bcdf88f62b0 162 #define MXC_S_PT_RATE_LENGTH_MODE_28_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_28_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
<> 128:9bcdf88f62b0 163 #define MXC_S_PT_RATE_LENGTH_MODE_29_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_29_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
<> 128:9bcdf88f62b0 164 #define MXC_S_PT_RATE_LENGTH_MODE_30_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_30_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
<> 128:9bcdf88f62b0 165 #define MXC_S_PT_RATE_LENGTH_MODE_31_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_31_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
<> 128:9bcdf88f62b0 166
<> 128:9bcdf88f62b0 167 #ifdef __cplusplus
<> 128:9bcdf88f62b0 168 }
<> 128:9bcdf88f62b0 169 #endif
<> 128:9bcdf88f62b0 170
<> 128:9bcdf88f62b0 171 /**
<> 128:9bcdf88f62b0 172 * @}
<> 128:9bcdf88f62b0 173 */
<> 128:9bcdf88f62b0 174
<> 128:9bcdf88f62b0 175 #endif /* _MXC_PT_REGS_H_ */