The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.
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mbed 2
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Diff: TARGET_SSCI824/core_sc000.h
- Revision:
- 169:a7c7b631e539
- Parent:
- 160:5571c4ff569f
diff -r b9e159c1930a -r a7c7b631e539 TARGET_SSCI824/core_sc000.h --- a/TARGET_SSCI824/core_sc000.h Thu May 24 15:35:55 2018 +0100 +++ b/TARGET_SSCI824/core_sc000.h Fri Jun 22 15:38:59 2018 +0100 @@ -1,11 +1,11 @@ /**************************************************************************//** * @file core_sc000.h * @brief CMSIS SC000 Core Peripheral Access Layer Header File - * @version V5.0.2 - * @date 19. April 2017 + * @version V5.0.3 + * @date 10. January 2018 ******************************************************************************/ /* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -23,8 +23,8 @@ */ #if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif @@ -727,7 +727,7 @@ #define NVIC_USER_IRQ_OFFSET 16 -/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* Interrupt Priorities are WORD accessible only under Armv6-M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) @@ -744,7 +744,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } @@ -761,7 +761,7 @@ { if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -780,7 +780,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } @@ -799,7 +799,7 @@ { if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { @@ -818,7 +818,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } @@ -833,7 +833,7 @@ { if ((int32_t)(IRQn) >= 0) { - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } }