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TARGET_KW41Z/TOOLCHAIN_ARM_STD/MKW41Z512xxx4.sct@141:794e51388b66, 2017-04-28 (annotated)
- Committer:
- Anna Bridge
- Date:
- Fri Apr 28 13:09:19 2017 +0100
- Revision:
- 141:794e51388b66
- Parent:
- 132:9baf128c2fab
Release 141 of the mbed library
Ports for Upcoming Targets
Fixes and Changes
4008: [NUC472/M453] Support Bootloader and FlashIAP https://github.com/ARMmbed/mbed-os/pull/4008
4102: Add SCL and SDA defs for I2C[0-2]; redefine I2C_[SCL,SDA] to I2C2 https://github.com/ARMmbed/mbed-os/pull/4102
4118: STM32F4 Internal ADC channels rework https://github.com/ARMmbed/mbed-os/pull/4118
4126: STM32F4 : remove SERIAL_TX and SERIAL_RX from available pins https://github.com/ARMmbed/mbed-os/pull/4126
4148: Revert "STM32F4 Internal ADC channels rework" https://github.com/ARMmbed/mbed-os/pull/4148
4152: STM32F4 Internal ADC channels rework https://github.com/ARMmbed/mbed-os/pull/4152
4074: [Silicon Labs] Update pinout https://github.com/ARMmbed/mbed-os/pull/4074
4133: U-BLOX_C030: Default XTAL is now 12MHz onboard. Option to use Debug 8MHz https://github.com/ARMmbed/mbed-os/pull/4133
4142: EFM32: Fixed `pwmout_all_inactive` being inversed https://github.com/ARMmbed/mbed-os/pull/4142
4016: [NRF5]: fix rtc overflow-while-set-timestamp issue https://github.com/ARMmbed/mbed-os/pull/4016
4031: STM32 increase IAR heap size for big RAM targets https://github.com/ARMmbed/mbed-os/pull/4031
4137: MCUXpresso: Update ARM linker files to eliminate reserving RAM for stack & heap https://github.com/ARMmbed/mbed-os/pull/4137
4176: STM32L4 Internal ADC channels rework https://github.com/ARMmbed/mbed-os/pull/4176
4154: STM32F7 Internal ADC channels rework https://github.com/ARMmbed/mbed-os/pull/4154
4174: [NRF52840]: fix rtc overflow-while-set-timestamp issue https://github.com/ARMmbed/mbed-os/pull/4174
4180: [UBLOX_C030] create target hierarchy for the specific versions of the C030 board https://github.com/ARMmbed/mbed-os/pull/4180
4153: STM32F2: Internal ADC channels rework https://github.com/ARMmbed/mbed-os/pull/4153
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 132:9baf128c2fab | 1 | #! armcc -E |
<> | 132:9baf128c2fab | 2 | /* |
<> | 132:9baf128c2fab | 3 | ** ################################################################### |
<> | 132:9baf128c2fab | 4 | ** Processor: MKW41Z512VHT4 |
<> | 132:9baf128c2fab | 5 | ** Compiler: Keil ARM C/C++ Compiler |
<> | 132:9baf128c2fab | 6 | ** Reference manual: MKW41Z512RM Rev. 0.1, 04/2016 |
<> | 132:9baf128c2fab | 7 | ** Version: rev. 1.0, 2015-09-23 |
<> | 132:9baf128c2fab | 8 | ** Build: b160720 |
<> | 132:9baf128c2fab | 9 | ** |
<> | 132:9baf128c2fab | 10 | ** Abstract: |
<> | 132:9baf128c2fab | 11 | ** Linker file for the Keil ARM C/C++ Compiler |
<> | 132:9baf128c2fab | 12 | ** |
<> | 132:9baf128c2fab | 13 | ** Copyright (c) 2016 Freescale Semiconductor, Inc. |
<> | 132:9baf128c2fab | 14 | ** All rights reserved. |
<> | 132:9baf128c2fab | 15 | ** |
<> | 132:9baf128c2fab | 16 | ** Redistribution and use in source and binary forms, with or without modification, |
<> | 132:9baf128c2fab | 17 | ** are permitted provided that the following conditions are met: |
<> | 132:9baf128c2fab | 18 | ** |
<> | 132:9baf128c2fab | 19 | ** o Redistributions of source code must retain the above copyright notice, this list |
<> | 132:9baf128c2fab | 20 | ** of conditions and the following disclaimer. |
<> | 132:9baf128c2fab | 21 | ** |
<> | 132:9baf128c2fab | 22 | ** o Redistributions in binary form must reproduce the above copyright notice, this |
<> | 132:9baf128c2fab | 23 | ** list of conditions and the following disclaimer in the documentation and/or |
<> | 132:9baf128c2fab | 24 | ** other materials provided with the distribution. |
<> | 132:9baf128c2fab | 25 | ** |
<> | 132:9baf128c2fab | 26 | ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
<> | 132:9baf128c2fab | 27 | ** contributors may be used to endorse or promote products derived from this |
<> | 132:9baf128c2fab | 28 | ** software without specific prior written permission. |
<> | 132:9baf128c2fab | 29 | ** |
<> | 132:9baf128c2fab | 30 | ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
<> | 132:9baf128c2fab | 31 | ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
<> | 132:9baf128c2fab | 32 | ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 132:9baf128c2fab | 33 | ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
<> | 132:9baf128c2fab | 34 | ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
<> | 132:9baf128c2fab | 35 | ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
<> | 132:9baf128c2fab | 36 | ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
<> | 132:9baf128c2fab | 37 | ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
<> | 132:9baf128c2fab | 38 | ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
<> | 132:9baf128c2fab | 39 | ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 132:9baf128c2fab | 40 | ** |
<> | 132:9baf128c2fab | 41 | ** http: www.freescale.com |
<> | 132:9baf128c2fab | 42 | ** mail: support@freescale.com |
<> | 132:9baf128c2fab | 43 | ** |
<> | 132:9baf128c2fab | 44 | ** ################################################################### |
<> | 132:9baf128c2fab | 45 | */ |
<> | 132:9baf128c2fab | 46 | #define __ram_vector_table__ 1 |
<> | 132:9baf128c2fab | 47 | |
<> | 132:9baf128c2fab | 48 | #if (defined(__ram_vector_table__)) |
<> | 132:9baf128c2fab | 49 | #define __ram_vector_table_size__ 0x00000200 |
<> | 132:9baf128c2fab | 50 | #else |
<> | 132:9baf128c2fab | 51 | #define __ram_vector_table_size__ 0x00000000 |
<> | 132:9baf128c2fab | 52 | #endif |
<> | 132:9baf128c2fab | 53 | |
<> | 132:9baf128c2fab | 54 | #define m_interrupts_start 0x00000000 |
<> | 132:9baf128c2fab | 55 | #define m_interrupts_size 0x00000200 |
<> | 132:9baf128c2fab | 56 | |
<> | 132:9baf128c2fab | 57 | #define m_flash_config_start 0x00000400 |
<> | 132:9baf128c2fab | 58 | #define m_flash_config_size 0x00000010 |
<> | 132:9baf128c2fab | 59 | |
<> | 132:9baf128c2fab | 60 | #define m_text_start 0x00000410 |
<> | 132:9baf128c2fab | 61 | #define m_text_size 0x0007FBF0 |
<> | 132:9baf128c2fab | 62 | |
<> | 132:9baf128c2fab | 63 | #define m_interrupts_ram_start 0x1FFF8000 |
<> | 132:9baf128c2fab | 64 | #define m_interrupts_ram_size __ram_vector_table_size__ |
<> | 132:9baf128c2fab | 65 | |
<> | 132:9baf128c2fab | 66 | #define m_data_start (m_interrupts_ram_start + m_interrupts_ram_size) |
<> | 132:9baf128c2fab | 67 | #define m_data_size (0x00020000 - m_interrupts_ram_size) |
<> | 132:9baf128c2fab | 68 | |
<> | 132:9baf128c2fab | 69 | /* Sizes */ |
<> | 132:9baf128c2fab | 70 | #if (defined(__stack_size__)) |
<> | 132:9baf128c2fab | 71 | #define Stack_Size __stack_size__ |
<> | 132:9baf128c2fab | 72 | #else |
<> | 132:9baf128c2fab | 73 | #define Stack_Size 0x0400 |
<> | 132:9baf128c2fab | 74 | #endif |
<> | 132:9baf128c2fab | 75 | |
<> | 132:9baf128c2fab | 76 | #if (defined(__heap_size__)) |
<> | 132:9baf128c2fab | 77 | #define Heap_Size __heap_size__ |
<> | 132:9baf128c2fab | 78 | #else |
<> | 132:9baf128c2fab | 79 | #define Heap_Size 0x0400 |
<> | 132:9baf128c2fab | 80 | #endif |
<> | 132:9baf128c2fab | 81 | |
<> | 132:9baf128c2fab | 82 | LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region |
<> | 132:9baf128c2fab | 83 | VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address |
<> | 132:9baf128c2fab | 84 | * (RESET,+FIRST) |
<> | 132:9baf128c2fab | 85 | } |
<> | 132:9baf128c2fab | 86 | ER_m_flash_config m_flash_config_start FIXED m_flash_config_size { ; load address = execution address |
<> | 132:9baf128c2fab | 87 | * (FlashConfig) |
<> | 132:9baf128c2fab | 88 | } |
<> | 132:9baf128c2fab | 89 | ER_m_text m_text_start m_text_size { ; load address = execution address |
<> | 132:9baf128c2fab | 90 | * (InRoot$$Sections) |
<> | 132:9baf128c2fab | 91 | .ANY (+RO) |
<> | 132:9baf128c2fab | 92 | } |
<> | 132:9baf128c2fab | 93 | |
<> | 132:9baf128c2fab | 94 | #if (defined(__ram_vector_table__)) |
<> | 132:9baf128c2fab | 95 | VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size { |
<> | 132:9baf128c2fab | 96 | } |
<> | 132:9baf128c2fab | 97 | #else |
<> | 132:9baf128c2fab | 98 | VECTOR_RAM m_interrupts_start EMPTY 0 { |
<> | 132:9baf128c2fab | 99 | } |
<> | 132:9baf128c2fab | 100 | #endif |
<> | 132:9baf128c2fab | 101 | RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data |
<> | 132:9baf128c2fab | 102 | .ANY (+RW +ZI) |
<> | 132:9baf128c2fab | 103 | } |
<> | 132:9baf128c2fab | 104 | RW_IRAM1 +0 { ; Heap region growing up |
<> | 132:9baf128c2fab | 105 | } |
<> | 132:9baf128c2fab | 106 | } |
<> | 132:9baf128c2fab | 107 |