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TARGET_NUCLEO_F030R8/TOOLCHAIN_IAR/stm32f0xx_ll_rcc.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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AnnaBridge | 171:3a7713b1edbc | 1 | /** |
AnnaBridge | 171:3a7713b1edbc | 2 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 3 | * @file stm32f0xx_ll_rcc.h |
AnnaBridge | 171:3a7713b1edbc | 4 | * @author MCD Application Team |
AnnaBridge | 171:3a7713b1edbc | 5 | * @brief Header file of RCC LL module. |
AnnaBridge | 171:3a7713b1edbc | 6 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 7 | * @attention |
AnnaBridge | 171:3a7713b1edbc | 8 | * |
AnnaBridge | 171:3a7713b1edbc | 9 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
AnnaBridge | 171:3a7713b1edbc | 10 | * |
AnnaBridge | 171:3a7713b1edbc | 11 | * Redistribution and use in source and binary forms, with or without modification, |
AnnaBridge | 171:3a7713b1edbc | 12 | * are permitted provided that the following conditions are met: |
AnnaBridge | 171:3a7713b1edbc | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 14 | * this list of conditions and the following disclaimer. |
AnnaBridge | 171:3a7713b1edbc | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 171:3a7713b1edbc | 17 | * and/or other materials provided with the distribution. |
AnnaBridge | 171:3a7713b1edbc | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
AnnaBridge | 171:3a7713b1edbc | 19 | * may be used to endorse or promote products derived from this software |
AnnaBridge | 171:3a7713b1edbc | 20 | * without specific prior written permission. |
AnnaBridge | 171:3a7713b1edbc | 21 | * |
AnnaBridge | 171:3a7713b1edbc | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
AnnaBridge | 171:3a7713b1edbc | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
AnnaBridge | 171:3a7713b1edbc | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 171:3a7713b1edbc | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
AnnaBridge | 171:3a7713b1edbc | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 171:3a7713b1edbc | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
AnnaBridge | 171:3a7713b1edbc | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
AnnaBridge | 171:3a7713b1edbc | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
AnnaBridge | 171:3a7713b1edbc | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
AnnaBridge | 171:3a7713b1edbc | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 171:3a7713b1edbc | 32 | * |
AnnaBridge | 171:3a7713b1edbc | 33 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 34 | */ |
AnnaBridge | 171:3a7713b1edbc | 35 | |
AnnaBridge | 171:3a7713b1edbc | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 37 | #ifndef __STM32F0xx_LL_RCC_H |
AnnaBridge | 171:3a7713b1edbc | 38 | #define __STM32F0xx_LL_RCC_H |
AnnaBridge | 171:3a7713b1edbc | 39 | |
AnnaBridge | 171:3a7713b1edbc | 40 | #ifdef __cplusplus |
AnnaBridge | 171:3a7713b1edbc | 41 | extern "C" { |
AnnaBridge | 171:3a7713b1edbc | 42 | #endif |
AnnaBridge | 171:3a7713b1edbc | 43 | |
AnnaBridge | 171:3a7713b1edbc | 44 | /* Includes ------------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 45 | #include "stm32f0xx.h" |
AnnaBridge | 171:3a7713b1edbc | 46 | |
AnnaBridge | 171:3a7713b1edbc | 47 | /** @addtogroup STM32F0xx_LL_Driver |
AnnaBridge | 171:3a7713b1edbc | 48 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 49 | */ |
AnnaBridge | 171:3a7713b1edbc | 50 | |
AnnaBridge | 171:3a7713b1edbc | 51 | #if defined(RCC) |
AnnaBridge | 171:3a7713b1edbc | 52 | |
AnnaBridge | 171:3a7713b1edbc | 53 | /** @defgroup RCC_LL RCC |
AnnaBridge | 171:3a7713b1edbc | 54 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 55 | */ |
AnnaBridge | 171:3a7713b1edbc | 56 | |
AnnaBridge | 171:3a7713b1edbc | 57 | /* Private types -------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 58 | /* Private variables ---------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 59 | /* Private constants ---------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 60 | /** @defgroup RCC_LL_Private_Constants RCC Private Constants |
AnnaBridge | 171:3a7713b1edbc | 61 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 62 | */ |
AnnaBridge | 171:3a7713b1edbc | 63 | /* Defines used for the bit position in the register and perform offsets*/ |
AnnaBridge | 171:3a7713b1edbc | 64 | #define RCC_POSITION_HPRE (uint32_t)4U /*!< field position in register RCC_CFGR */ |
AnnaBridge | 171:3a7713b1edbc | 65 | #define RCC_POSITION_PPRE1 (uint32_t)8U /*!< field position in register RCC_CFGR */ |
AnnaBridge | 171:3a7713b1edbc | 66 | #define RCC_POSITION_PLLMUL (uint32_t)18U /*!< field position in register RCC_CFGR */ |
AnnaBridge | 171:3a7713b1edbc | 67 | #define RCC_POSITION_HSICAL (uint32_t)8U /*!< field position in register RCC_CR */ |
AnnaBridge | 171:3a7713b1edbc | 68 | #define RCC_POSITION_HSITRIM (uint32_t)3U /*!< field position in register RCC_CR */ |
AnnaBridge | 171:3a7713b1edbc | 69 | #define RCC_POSITION_HSI14TRIM (uint32_t)3U /*!< field position in register RCC_CR2 */ |
AnnaBridge | 171:3a7713b1edbc | 70 | #define RCC_POSITION_HSI14CAL (uint32_t)8U /*!< field position in register RCC_CR2 */ |
AnnaBridge | 171:3a7713b1edbc | 71 | #if defined(RCC_HSI48_SUPPORT) |
AnnaBridge | 171:3a7713b1edbc | 72 | #define RCC_POSITION_HSI48CAL (uint32_t)24U /*!< field position in register RCC_CR2 */ |
AnnaBridge | 171:3a7713b1edbc | 73 | #endif /* RCC_HSI48_SUPPORT */ |
AnnaBridge | 171:3a7713b1edbc | 74 | #define RCC_POSITION_USART1SW (uint32_t)0U /*!< field position in register RCC_CFGR3 */ |
AnnaBridge | 171:3a7713b1edbc | 75 | #define RCC_POSITION_USART2SW (uint32_t)16U /*!< field position in register RCC_CFGR3 */ |
AnnaBridge | 171:3a7713b1edbc | 76 | #define RCC_POSITION_USART3SW (uint32_t)18U /*!< field position in register RCC_CFGR3 */ |
AnnaBridge | 171:3a7713b1edbc | 77 | |
AnnaBridge | 171:3a7713b1edbc | 78 | /** |
AnnaBridge | 171:3a7713b1edbc | 79 | * @} |
AnnaBridge | 171:3a7713b1edbc | 80 | */ |
AnnaBridge | 171:3a7713b1edbc | 81 | |
AnnaBridge | 171:3a7713b1edbc | 82 | /* Private macros ------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 83 | #if defined(USE_FULL_LL_DRIVER) |
AnnaBridge | 171:3a7713b1edbc | 84 | /** @defgroup RCC_LL_Private_Macros RCC Private Macros |
AnnaBridge | 171:3a7713b1edbc | 85 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 86 | */ |
AnnaBridge | 171:3a7713b1edbc | 87 | /** |
AnnaBridge | 171:3a7713b1edbc | 88 | * @} |
AnnaBridge | 171:3a7713b1edbc | 89 | */ |
AnnaBridge | 171:3a7713b1edbc | 90 | #endif /*USE_FULL_LL_DRIVER*/ |
AnnaBridge | 171:3a7713b1edbc | 91 | /* Exported types ------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 92 | #if defined(USE_FULL_LL_DRIVER) |
AnnaBridge | 171:3a7713b1edbc | 93 | /** @defgroup RCC_LL_Exported_Types RCC Exported Types |
AnnaBridge | 171:3a7713b1edbc | 94 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 95 | */ |
AnnaBridge | 171:3a7713b1edbc | 96 | |
AnnaBridge | 171:3a7713b1edbc | 97 | /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure |
AnnaBridge | 171:3a7713b1edbc | 98 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 99 | */ |
AnnaBridge | 171:3a7713b1edbc | 100 | |
AnnaBridge | 171:3a7713b1edbc | 101 | /** |
AnnaBridge | 171:3a7713b1edbc | 102 | * @brief RCC Clocks Frequency Structure |
AnnaBridge | 171:3a7713b1edbc | 103 | */ |
AnnaBridge | 171:3a7713b1edbc | 104 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 105 | { |
AnnaBridge | 171:3a7713b1edbc | 106 | uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ |
AnnaBridge | 171:3a7713b1edbc | 107 | uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ |
AnnaBridge | 171:3a7713b1edbc | 108 | uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ |
AnnaBridge | 171:3a7713b1edbc | 109 | } LL_RCC_ClocksTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 110 | |
AnnaBridge | 171:3a7713b1edbc | 111 | /** |
AnnaBridge | 171:3a7713b1edbc | 112 | * @} |
AnnaBridge | 171:3a7713b1edbc | 113 | */ |
AnnaBridge | 171:3a7713b1edbc | 114 | |
AnnaBridge | 171:3a7713b1edbc | 115 | /** |
AnnaBridge | 171:3a7713b1edbc | 116 | * @} |
AnnaBridge | 171:3a7713b1edbc | 117 | */ |
AnnaBridge | 171:3a7713b1edbc | 118 | #endif /* USE_FULL_LL_DRIVER */ |
AnnaBridge | 171:3a7713b1edbc | 119 | |
AnnaBridge | 171:3a7713b1edbc | 120 | /* Exported constants --------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 121 | /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants |
AnnaBridge | 171:3a7713b1edbc | 122 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 123 | */ |
AnnaBridge | 171:3a7713b1edbc | 124 | |
AnnaBridge | 171:3a7713b1edbc | 125 | /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation |
AnnaBridge | 171:3a7713b1edbc | 126 | * @brief Defines used to adapt values of different oscillators |
AnnaBridge | 171:3a7713b1edbc | 127 | * @note These values could be modified in the user environment according to |
AnnaBridge | 171:3a7713b1edbc | 128 | * HW set-up. |
AnnaBridge | 171:3a7713b1edbc | 129 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 130 | */ |
AnnaBridge | 171:3a7713b1edbc | 131 | #if !defined (HSE_VALUE) |
AnnaBridge | 171:3a7713b1edbc | 132 | #define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */ |
AnnaBridge | 171:3a7713b1edbc | 133 | #endif /* HSE_VALUE */ |
AnnaBridge | 171:3a7713b1edbc | 134 | |
AnnaBridge | 171:3a7713b1edbc | 135 | #if !defined (HSI_VALUE) |
AnnaBridge | 171:3a7713b1edbc | 136 | #define HSI_VALUE 8000000U /*!< Value of the HSI oscillator in Hz */ |
AnnaBridge | 171:3a7713b1edbc | 137 | #endif /* HSI_VALUE */ |
AnnaBridge | 171:3a7713b1edbc | 138 | |
AnnaBridge | 171:3a7713b1edbc | 139 | #if !defined (LSE_VALUE) |
AnnaBridge | 171:3a7713b1edbc | 140 | #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ |
AnnaBridge | 171:3a7713b1edbc | 141 | #endif /* LSE_VALUE */ |
AnnaBridge | 171:3a7713b1edbc | 142 | |
AnnaBridge | 171:3a7713b1edbc | 143 | #if !defined (LSI_VALUE) |
AnnaBridge | 171:3a7713b1edbc | 144 | #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ |
AnnaBridge | 171:3a7713b1edbc | 145 | #endif /* LSI_VALUE */ |
AnnaBridge | 171:3a7713b1edbc | 146 | #if defined(RCC_HSI48_SUPPORT) |
AnnaBridge | 171:3a7713b1edbc | 147 | |
AnnaBridge | 171:3a7713b1edbc | 148 | #if !defined (HSI48_VALUE) |
AnnaBridge | 171:3a7713b1edbc | 149 | #define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */ |
AnnaBridge | 171:3a7713b1edbc | 150 | #endif /* HSI48_VALUE */ |
AnnaBridge | 171:3a7713b1edbc | 151 | #endif /* RCC_HSI48_SUPPORT */ |
AnnaBridge | 171:3a7713b1edbc | 152 | /** |
AnnaBridge | 171:3a7713b1edbc | 153 | * @} |
AnnaBridge | 171:3a7713b1edbc | 154 | */ |
AnnaBridge | 171:3a7713b1edbc | 155 | |
AnnaBridge | 171:3a7713b1edbc | 156 | /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines |
AnnaBridge | 171:3a7713b1edbc | 157 | * @brief Flags defines which can be used with LL_RCC_WriteReg function |
AnnaBridge | 171:3a7713b1edbc | 158 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 159 | */ |
AnnaBridge | 171:3a7713b1edbc | 160 | #define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */ |
AnnaBridge | 171:3a7713b1edbc | 161 | #define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */ |
AnnaBridge | 171:3a7713b1edbc | 162 | #define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */ |
AnnaBridge | 171:3a7713b1edbc | 163 | #define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */ |
AnnaBridge | 171:3a7713b1edbc | 164 | #define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */ |
AnnaBridge | 171:3a7713b1edbc | 165 | #define LL_RCC_CIR_HSI14RDYC RCC_CIR_HSI14RDYC /*!< HSI14 Ready Interrupt Clear */ |
AnnaBridge | 171:3a7713b1edbc | 166 | #if defined(RCC_HSI48_SUPPORT) |
AnnaBridge | 171:3a7713b1edbc | 167 | #define LL_RCC_CIR_HSI48RDYC RCC_CIR_HSI48RDYC /*!< HSI48 Ready Interrupt Clear */ |
AnnaBridge | 171:3a7713b1edbc | 168 | #endif /* RCC_HSI48_SUPPORT */ |
AnnaBridge | 171:3a7713b1edbc | 169 | #define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */ |
AnnaBridge | 171:3a7713b1edbc | 170 | /** |
AnnaBridge | 171:3a7713b1edbc | 171 | * @} |
AnnaBridge | 171:3a7713b1edbc | 172 | */ |
AnnaBridge | 171:3a7713b1edbc | 173 | |
AnnaBridge | 171:3a7713b1edbc | 174 | /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines |
AnnaBridge | 171:3a7713b1edbc | 175 | * @brief Flags defines which can be used with LL_RCC_ReadReg function |
AnnaBridge | 171:3a7713b1edbc | 176 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 177 | */ |
AnnaBridge | 171:3a7713b1edbc | 178 | #define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */ |
AnnaBridge | 171:3a7713b1edbc | 179 | #define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */ |
AnnaBridge | 171:3a7713b1edbc | 180 | #define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */ |
AnnaBridge | 171:3a7713b1edbc | 181 | #define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */ |
AnnaBridge | 171:3a7713b1edbc | 182 | #define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */ |
AnnaBridge | 171:3a7713b1edbc | 183 | #define LL_RCC_CIR_HSI14RDYF RCC_CIR_HSI14RDYF /*!< HSI14 Ready Interrupt flag */ |
AnnaBridge | 171:3a7713b1edbc | 184 | #if defined(RCC_HSI48_SUPPORT) |
AnnaBridge | 171:3a7713b1edbc | 185 | #define LL_RCC_CIR_HSI48RDYF RCC_CIR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ |
AnnaBridge | 171:3a7713b1edbc | 186 | #endif /* RCC_HSI48_SUPPORT */ |
AnnaBridge | 171:3a7713b1edbc | 187 | #define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */ |
AnnaBridge | 171:3a7713b1edbc | 188 | #define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */ |
AnnaBridge | 171:3a7713b1edbc | 189 | #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ |
AnnaBridge | 171:3a7713b1edbc | 190 | #define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */ |
AnnaBridge | 171:3a7713b1edbc | 191 | #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ |
AnnaBridge | 171:3a7713b1edbc | 192 | #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ |
AnnaBridge | 171:3a7713b1edbc | 193 | #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ |
AnnaBridge | 171:3a7713b1edbc | 194 | #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ |
AnnaBridge | 171:3a7713b1edbc | 195 | #if defined(RCC_CSR_V18PWRRSTF) |
AnnaBridge | 171:3a7713b1edbc | 196 | #define LL_RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF /*!< Reset flag of the 1.8 V domain. */ |
AnnaBridge | 171:3a7713b1edbc | 197 | #endif /* RCC_CSR_V18PWRRSTF */ |
AnnaBridge | 171:3a7713b1edbc | 198 | /** |
AnnaBridge | 171:3a7713b1edbc | 199 | * @} |
AnnaBridge | 171:3a7713b1edbc | 200 | */ |
AnnaBridge | 171:3a7713b1edbc | 201 | |
AnnaBridge | 171:3a7713b1edbc | 202 | /** @defgroup RCC_LL_EC_IT IT Defines |
AnnaBridge | 171:3a7713b1edbc | 203 | * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions |
AnnaBridge | 171:3a7713b1edbc | 204 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 205 | */ |
AnnaBridge | 171:3a7713b1edbc | 206 | #define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 207 | #define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 208 | #define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 209 | #define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 210 | #define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 211 | #define LL_RCC_CIR_HSI14RDYIE RCC_CIR_HSI14RDYIE /*!< HSI14 Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 212 | #if defined(RCC_HSI48_SUPPORT) |
AnnaBridge | 171:3a7713b1edbc | 213 | #define LL_RCC_CIR_HSI48RDYIE RCC_CIR_HSI48RDYIE /*!< HSI48 Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 214 | #endif /* RCC_HSI48_SUPPORT */ |
AnnaBridge | 171:3a7713b1edbc | 215 | /** |
AnnaBridge | 171:3a7713b1edbc | 216 | * @} |
AnnaBridge | 171:3a7713b1edbc | 217 | */ |
AnnaBridge | 171:3a7713b1edbc | 218 | |
AnnaBridge | 171:3a7713b1edbc | 219 | /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability |
AnnaBridge | 171:3a7713b1edbc | 220 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 221 | */ |
AnnaBridge | 171:3a7713b1edbc | 222 | #define LL_RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) /*!< Xtal mode lower driving capability */ |
AnnaBridge | 171:3a7713b1edbc | 223 | #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low driving capability */ |
AnnaBridge | 171:3a7713b1edbc | 224 | #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high driving capability */ |
AnnaBridge | 171:3a7713b1edbc | 225 | #define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */ |
AnnaBridge | 171:3a7713b1edbc | 226 | /** |
AnnaBridge | 171:3a7713b1edbc | 227 | * @} |
AnnaBridge | 171:3a7713b1edbc | 228 | */ |
AnnaBridge | 171:3a7713b1edbc | 229 | |
AnnaBridge | 171:3a7713b1edbc | 230 | /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch |
AnnaBridge | 171:3a7713b1edbc | 231 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 232 | */ |
AnnaBridge | 171:3a7713b1edbc | 233 | #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ |
AnnaBridge | 171:3a7713b1edbc | 234 | #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ |
AnnaBridge | 171:3a7713b1edbc | 235 | #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ |
AnnaBridge | 171:3a7713b1edbc | 236 | #if defined(RCC_CFGR_SW_HSI48) |
AnnaBridge | 171:3a7713b1edbc | 237 | #define LL_RCC_SYS_CLKSOURCE_HSI48 RCC_CFGR_SW_HSI48 /*!< HSI48 selection as system clock */ |
AnnaBridge | 171:3a7713b1edbc | 238 | #endif /* RCC_CFGR_SW_HSI48 */ |
AnnaBridge | 171:3a7713b1edbc | 239 | /** |
AnnaBridge | 171:3a7713b1edbc | 240 | * @} |
AnnaBridge | 171:3a7713b1edbc | 241 | */ |
AnnaBridge | 171:3a7713b1edbc | 242 | |
AnnaBridge | 171:3a7713b1edbc | 243 | /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status |
AnnaBridge | 171:3a7713b1edbc | 244 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 245 | */ |
AnnaBridge | 171:3a7713b1edbc | 246 | #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ |
AnnaBridge | 171:3a7713b1edbc | 247 | #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ |
AnnaBridge | 171:3a7713b1edbc | 248 | #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ |
AnnaBridge | 171:3a7713b1edbc | 249 | #if defined(RCC_CFGR_SWS_HSI48) |
AnnaBridge | 171:3a7713b1edbc | 250 | #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48 /*!< HSI48 used as system clock */ |
AnnaBridge | 171:3a7713b1edbc | 251 | #endif /* RCC_CFGR_SWS_HSI48 */ |
AnnaBridge | 171:3a7713b1edbc | 252 | /** |
AnnaBridge | 171:3a7713b1edbc | 253 | * @} |
AnnaBridge | 171:3a7713b1edbc | 254 | */ |
AnnaBridge | 171:3a7713b1edbc | 255 | |
AnnaBridge | 171:3a7713b1edbc | 256 | /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler |
AnnaBridge | 171:3a7713b1edbc | 257 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 258 | */ |
AnnaBridge | 171:3a7713b1edbc | 259 | #define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ |
AnnaBridge | 171:3a7713b1edbc | 260 | #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ |
AnnaBridge | 171:3a7713b1edbc | 261 | #define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ |
AnnaBridge | 171:3a7713b1edbc | 262 | #define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ |
AnnaBridge | 171:3a7713b1edbc | 263 | #define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ |
AnnaBridge | 171:3a7713b1edbc | 264 | #define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ |
AnnaBridge | 171:3a7713b1edbc | 265 | #define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ |
AnnaBridge | 171:3a7713b1edbc | 266 | #define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ |
AnnaBridge | 171:3a7713b1edbc | 267 | #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ |
AnnaBridge | 171:3a7713b1edbc | 268 | /** |
AnnaBridge | 171:3a7713b1edbc | 269 | * @} |
AnnaBridge | 171:3a7713b1edbc | 270 | */ |
AnnaBridge | 171:3a7713b1edbc | 271 | |
AnnaBridge | 171:3a7713b1edbc | 272 | /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) |
AnnaBridge | 171:3a7713b1edbc | 273 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 274 | */ |
AnnaBridge | 171:3a7713b1edbc | 275 | #define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE_DIV1 /*!< HCLK not divided */ |
AnnaBridge | 171:3a7713b1edbc | 276 | #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE_DIV2 /*!< HCLK divided by 2 */ |
AnnaBridge | 171:3a7713b1edbc | 277 | #define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE_DIV4 /*!< HCLK divided by 4 */ |
AnnaBridge | 171:3a7713b1edbc | 278 | #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE_DIV8 /*!< HCLK divided by 8 */ |
AnnaBridge | 171:3a7713b1edbc | 279 | #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE_DIV16 /*!< HCLK divided by 16 */ |
AnnaBridge | 171:3a7713b1edbc | 280 | /** |
AnnaBridge | 171:3a7713b1edbc | 281 | * @} |
AnnaBridge | 171:3a7713b1edbc | 282 | */ |
AnnaBridge | 171:3a7713b1edbc | 283 | |
AnnaBridge | 171:3a7713b1edbc | 284 | /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection |
AnnaBridge | 171:3a7713b1edbc | 285 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 286 | */ |
AnnaBridge | 171:3a7713b1edbc | 287 | #define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK /*!< MCO output disabled, no clock on MCO */ |
AnnaBridge | 171:3a7713b1edbc | 288 | #define LL_RCC_MCO1SOURCE_HSI14 RCC_CFGR_MCOSEL_HSI14 /*!< HSI14 oscillator clock selected */ |
AnnaBridge | 171:3a7713b1edbc | 289 | #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK /*!< SYSCLK selection as MCO source */ |
AnnaBridge | 171:3a7713b1edbc | 290 | #define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI /*!< HSI selection as MCO source */ |
AnnaBridge | 171:3a7713b1edbc | 291 | #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE /*!< HSE selection as MCO source */ |
AnnaBridge | 171:3a7713b1edbc | 292 | #define LL_RCC_MCO1SOURCE_LSI RCC_CFGR_MCOSEL_LSI /*!< LSI selection as MCO source */ |
AnnaBridge | 171:3a7713b1edbc | 293 | #define LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_LSE /*!< LSE selection as MCO source */ |
AnnaBridge | 171:3a7713b1edbc | 294 | #if defined(RCC_CFGR_MCOSEL_HSI48) |
AnnaBridge | 171:3a7713b1edbc | 295 | #define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_HSI48 /*!< HSI48 selection as MCO source */ |
AnnaBridge | 171:3a7713b1edbc | 296 | #endif /* RCC_CFGR_MCOSEL_HSI48 */ |
AnnaBridge | 171:3a7713b1edbc | 297 | #define LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 RCC_CFGR_MCOSEL_PLL_DIV2 /*!< PLL clock divided by 2*/ |
AnnaBridge | 171:3a7713b1edbc | 298 | #if defined(RCC_CFGR_PLLNODIV) |
AnnaBridge | 171:3a7713b1edbc | 299 | #define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_PLL_DIV2 | RCC_CFGR_PLLNODIV) /*!< PLL clock selected*/ |
AnnaBridge | 171:3a7713b1edbc | 300 | #endif /* RCC_CFGR_PLLNODIV */ |
AnnaBridge | 171:3a7713b1edbc | 301 | /** |
AnnaBridge | 171:3a7713b1edbc | 302 | * @} |
AnnaBridge | 171:3a7713b1edbc | 303 | */ |
AnnaBridge | 171:3a7713b1edbc | 304 | |
AnnaBridge | 171:3a7713b1edbc | 305 | /** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler |
AnnaBridge | 171:3a7713b1edbc | 306 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 307 | */ |
AnnaBridge | 171:3a7713b1edbc | 308 | #define LL_RCC_MCO1_DIV_1 ((uint32_t)0x00000000U)/*!< MCO Clock divided by 1 */ |
AnnaBridge | 171:3a7713b1edbc | 309 | #if defined(RCC_CFGR_MCOPRE) |
AnnaBridge | 171:3a7713b1edbc | 310 | #define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO Clock divided by 2 */ |
AnnaBridge | 171:3a7713b1edbc | 311 | #define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO Clock divided by 4 */ |
AnnaBridge | 171:3a7713b1edbc | 312 | #define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO Clock divided by 8 */ |
AnnaBridge | 171:3a7713b1edbc | 313 | #define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO Clock divided by 16 */ |
AnnaBridge | 171:3a7713b1edbc | 314 | #define LL_RCC_MCO1_DIV_32 RCC_CFGR_MCOPRE_DIV32 /*!< MCO Clock divided by 32 */ |
AnnaBridge | 171:3a7713b1edbc | 315 | #define LL_RCC_MCO1_DIV_64 RCC_CFGR_MCOPRE_DIV64 /*!< MCO Clock divided by 64 */ |
AnnaBridge | 171:3a7713b1edbc | 316 | #define LL_RCC_MCO1_DIV_128 RCC_CFGR_MCOPRE_DIV128 /*!< MCO Clock divided by 128 */ |
AnnaBridge | 171:3a7713b1edbc | 317 | #endif /* RCC_CFGR_MCOPRE */ |
AnnaBridge | 171:3a7713b1edbc | 318 | /** |
AnnaBridge | 171:3a7713b1edbc | 319 | * @} |
AnnaBridge | 171:3a7713b1edbc | 320 | */ |
AnnaBridge | 171:3a7713b1edbc | 321 | |
AnnaBridge | 171:3a7713b1edbc | 322 | #if defined(USE_FULL_LL_DRIVER) |
AnnaBridge | 171:3a7713b1edbc | 323 | /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency |
AnnaBridge | 171:3a7713b1edbc | 324 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 325 | */ |
AnnaBridge | 171:3a7713b1edbc | 326 | #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */ |
AnnaBridge | 171:3a7713b1edbc | 327 | #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ |
AnnaBridge | 171:3a7713b1edbc | 328 | /** |
AnnaBridge | 171:3a7713b1edbc | 329 | * @} |
AnnaBridge | 171:3a7713b1edbc | 330 | */ |
AnnaBridge | 171:3a7713b1edbc | 331 | #endif /* USE_FULL_LL_DRIVER */ |
AnnaBridge | 171:3a7713b1edbc | 332 | |
AnnaBridge | 171:3a7713b1edbc | 333 | /** @defgroup RCC_LL_EC_USART1_CLKSOURCE Peripheral USART clock source selection |
AnnaBridge | 171:3a7713b1edbc | 334 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 335 | */ |
AnnaBridge | 171:3a7713b1edbc | 336 | #define LL_RCC_USART1_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART1SW << 24) | RCC_CFGR3_USART1SW_PCLK) /*!< PCLK1 clock used as USART1 clock source */ |
AnnaBridge | 171:3a7713b1edbc | 337 | #define LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART1SW << 24) | RCC_CFGR3_USART1SW_SYSCLK) /*!< System clock selected as USART1 clock source */ |
AnnaBridge | 171:3a7713b1edbc | 338 | #define LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART1SW << 24) | RCC_CFGR3_USART1SW_LSE) /*!< LSE oscillator clock used as USART1 clock source */ |
AnnaBridge | 171:3a7713b1edbc | 339 | #define LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART1SW << 24) | RCC_CFGR3_USART1SW_HSI) /*!< HSI oscillator clock used as USART1 clock source */ |
AnnaBridge | 171:3a7713b1edbc | 340 | #if defined(RCC_CFGR3_USART2SW) |
AnnaBridge | 171:3a7713b1edbc | 341 | #define LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART2SW << 24) | RCC_CFGR3_USART2SW_PCLK) /*!< PCLK1 clock used as USART2 clock source */ |
AnnaBridge | 171:3a7713b1edbc | 342 | #define LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART2SW << 24) | RCC_CFGR3_USART2SW_SYSCLK) /*!< System clock selected as USART2 clock source */ |
AnnaBridge | 171:3a7713b1edbc | 343 | #define LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART2SW << 24) | RCC_CFGR3_USART2SW_LSE) /*!< LSE oscillator clock used as USART2 clock source */ |
AnnaBridge | 171:3a7713b1edbc | 344 | #define LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART2SW << 24) | RCC_CFGR3_USART2SW_HSI) /*!< HSI oscillator clock used as USART2 clock source */ |
AnnaBridge | 171:3a7713b1edbc | 345 | #endif /* RCC_CFGR3_USART2SW */ |
AnnaBridge | 171:3a7713b1edbc | 346 | #if defined(RCC_CFGR3_USART3SW) |
AnnaBridge | 171:3a7713b1edbc | 347 | #define LL_RCC_USART3_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART3SW << 24) | RCC_CFGR3_USART3SW_PCLK) /*!< PCLK1 clock used as USART3 clock source */ |
AnnaBridge | 171:3a7713b1edbc | 348 | #define LL_RCC_USART3_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART3SW << 24) | RCC_CFGR3_USART3SW_SYSCLK) /*!< System clock selected as USART3 clock source */ |
AnnaBridge | 171:3a7713b1edbc | 349 | #define LL_RCC_USART3_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART3SW << 24) | RCC_CFGR3_USART3SW_LSE) /*!< LSE oscillator clock used as USART3 clock source */ |
AnnaBridge | 171:3a7713b1edbc | 350 | #define LL_RCC_USART3_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART3SW << 24) | RCC_CFGR3_USART3SW_HSI) /*!< HSI oscillator clock used as USART3 clock source */ |
AnnaBridge | 171:3a7713b1edbc | 351 | #endif /* RCC_CFGR3_USART3SW */ |
AnnaBridge | 171:3a7713b1edbc | 352 | /** |
AnnaBridge | 171:3a7713b1edbc | 353 | * @} |
AnnaBridge | 171:3a7713b1edbc | 354 | */ |
AnnaBridge | 171:3a7713b1edbc | 355 | |
AnnaBridge | 171:3a7713b1edbc | 356 | /** @defgroup RCC_LL_EC_I2C1_CLKSOURCE Peripheral I2C clock source selection |
AnnaBridge | 171:3a7713b1edbc | 357 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 358 | */ |
AnnaBridge | 171:3a7713b1edbc | 359 | #define LL_RCC_I2C1_CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI /*!< HSI oscillator clock used as I2C1 clock source */ |
AnnaBridge | 171:3a7713b1edbc | 360 | #define LL_RCC_I2C1_CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK /*!< System clock selected as I2C1 clock source */ |
AnnaBridge | 171:3a7713b1edbc | 361 | /** |
AnnaBridge | 171:3a7713b1edbc | 362 | * @} |
AnnaBridge | 171:3a7713b1edbc | 363 | */ |
AnnaBridge | 171:3a7713b1edbc | 364 | |
AnnaBridge | 171:3a7713b1edbc | 365 | #if defined(CEC) |
AnnaBridge | 171:3a7713b1edbc | 366 | /** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection |
AnnaBridge | 171:3a7713b1edbc | 367 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 368 | */ |
AnnaBridge | 171:3a7713b1edbc | 369 | #define LL_RCC_CEC_CLKSOURCE_HSI_DIV244 RCC_CFGR3_CECSW_HSI_DIV244 /*!< HSI clock divided by 244 selected as HDMI CEC entry clock source */ |
AnnaBridge | 171:3a7713b1edbc | 370 | #define LL_RCC_CEC_CLKSOURCE_LSE RCC_CFGR3_CECSW_LSE /*!< LSE clock selected as HDMI CEC entry clock source */ |
AnnaBridge | 171:3a7713b1edbc | 371 | /** |
AnnaBridge | 171:3a7713b1edbc | 372 | * @} |
AnnaBridge | 171:3a7713b1edbc | 373 | */ |
AnnaBridge | 171:3a7713b1edbc | 374 | |
AnnaBridge | 171:3a7713b1edbc | 375 | #endif /* CEC */ |
AnnaBridge | 171:3a7713b1edbc | 376 | |
AnnaBridge | 171:3a7713b1edbc | 377 | #if defined(USB) |
AnnaBridge | 171:3a7713b1edbc | 378 | /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection |
AnnaBridge | 171:3a7713b1edbc | 379 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 380 | */ |
AnnaBridge | 171:3a7713b1edbc | 381 | #if defined(RCC_CFGR3_USBSW_HSI48) |
AnnaBridge | 171:3a7713b1edbc | 382 | #define LL_RCC_USB_CLKSOURCE_HSI48 RCC_CFGR3_USBSW_HSI48 /*!< HSI48 oscillator clock used as USB clock source */ |
AnnaBridge | 171:3a7713b1edbc | 383 | #else |
AnnaBridge | 171:3a7713b1edbc | 384 | #define LL_RCC_USB_CLKSOURCE_NONE ((uint32_t)0x00000000) /*!< USB Clock disabled */ |
AnnaBridge | 171:3a7713b1edbc | 385 | #endif /*RCC_CFGR3_USBSW_HSI48*/ |
AnnaBridge | 171:3a7713b1edbc | 386 | #define LL_RCC_USB_CLKSOURCE_PLL RCC_CFGR3_USBSW_PLLCLK /*!< PLL selected as USB clock source */ |
AnnaBridge | 171:3a7713b1edbc | 387 | /** |
AnnaBridge | 171:3a7713b1edbc | 388 | * @} |
AnnaBridge | 171:3a7713b1edbc | 389 | */ |
AnnaBridge | 171:3a7713b1edbc | 390 | |
AnnaBridge | 171:3a7713b1edbc | 391 | #endif /* USB */ |
AnnaBridge | 171:3a7713b1edbc | 392 | |
AnnaBridge | 171:3a7713b1edbc | 393 | /** @defgroup RCC_LL_EC_USART1 Peripheral USART get clock source |
AnnaBridge | 171:3a7713b1edbc | 394 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 395 | */ |
AnnaBridge | 171:3a7713b1edbc | 396 | #define LL_RCC_USART1_CLKSOURCE RCC_POSITION_USART1SW /*!< USART1 Clock source selection */ |
AnnaBridge | 171:3a7713b1edbc | 397 | #if defined(RCC_CFGR3_USART2SW) |
AnnaBridge | 171:3a7713b1edbc | 398 | #define LL_RCC_USART2_CLKSOURCE RCC_POSITION_USART2SW /*!< USART2 Clock source selection */ |
AnnaBridge | 171:3a7713b1edbc | 399 | #endif /* RCC_CFGR3_USART2SW */ |
AnnaBridge | 171:3a7713b1edbc | 400 | #if defined(RCC_CFGR3_USART3SW) |
AnnaBridge | 171:3a7713b1edbc | 401 | #define LL_RCC_USART3_CLKSOURCE RCC_POSITION_USART3SW /*!< USART3 Clock source selection */ |
AnnaBridge | 171:3a7713b1edbc | 402 | #endif /* RCC_CFGR3_USART3SW */ |
AnnaBridge | 171:3a7713b1edbc | 403 | /** |
AnnaBridge | 171:3a7713b1edbc | 404 | * @} |
AnnaBridge | 171:3a7713b1edbc | 405 | */ |
AnnaBridge | 171:3a7713b1edbc | 406 | |
AnnaBridge | 171:3a7713b1edbc | 407 | /** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source |
AnnaBridge | 171:3a7713b1edbc | 408 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 409 | */ |
AnnaBridge | 171:3a7713b1edbc | 410 | #define LL_RCC_I2C1_CLKSOURCE RCC_CFGR3_I2C1SW /*!< I2C1 Clock source selection */ |
AnnaBridge | 171:3a7713b1edbc | 411 | /** |
AnnaBridge | 171:3a7713b1edbc | 412 | * @} |
AnnaBridge | 171:3a7713b1edbc | 413 | */ |
AnnaBridge | 171:3a7713b1edbc | 414 | |
AnnaBridge | 171:3a7713b1edbc | 415 | #if defined(CEC) |
AnnaBridge | 171:3a7713b1edbc | 416 | /** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source |
AnnaBridge | 171:3a7713b1edbc | 417 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 418 | */ |
AnnaBridge | 171:3a7713b1edbc | 419 | #define LL_RCC_CEC_CLKSOURCE RCC_CFGR3_CECSW /*!< CEC Clock source selection */ |
AnnaBridge | 171:3a7713b1edbc | 420 | /** |
AnnaBridge | 171:3a7713b1edbc | 421 | * @} |
AnnaBridge | 171:3a7713b1edbc | 422 | */ |
AnnaBridge | 171:3a7713b1edbc | 423 | #endif /* CEC */ |
AnnaBridge | 171:3a7713b1edbc | 424 | |
AnnaBridge | 171:3a7713b1edbc | 425 | #if defined(USB) |
AnnaBridge | 171:3a7713b1edbc | 426 | /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source |
AnnaBridge | 171:3a7713b1edbc | 427 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 428 | */ |
AnnaBridge | 171:3a7713b1edbc | 429 | #define LL_RCC_USB_CLKSOURCE RCC_CFGR3_USBSW /*!< USB Clock source selection */ |
AnnaBridge | 171:3a7713b1edbc | 430 | /** |
AnnaBridge | 171:3a7713b1edbc | 431 | * @} |
AnnaBridge | 171:3a7713b1edbc | 432 | */ |
AnnaBridge | 171:3a7713b1edbc | 433 | #endif /* USB */ |
AnnaBridge | 171:3a7713b1edbc | 434 | |
AnnaBridge | 171:3a7713b1edbc | 435 | /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection |
AnnaBridge | 171:3a7713b1edbc | 436 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 437 | */ |
AnnaBridge | 171:3a7713b1edbc | 438 | #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ |
AnnaBridge | 171:3a7713b1edbc | 439 | #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ |
AnnaBridge | 171:3a7713b1edbc | 440 | #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ |
AnnaBridge | 171:3a7713b1edbc | 441 | #define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ |
AnnaBridge | 171:3a7713b1edbc | 442 | /** |
AnnaBridge | 171:3a7713b1edbc | 443 | * @} |
AnnaBridge | 171:3a7713b1edbc | 444 | */ |
AnnaBridge | 171:3a7713b1edbc | 445 | |
AnnaBridge | 171:3a7713b1edbc | 446 | /** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor |
AnnaBridge | 171:3a7713b1edbc | 447 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 448 | */ |
AnnaBridge | 171:3a7713b1edbc | 449 | #define LL_RCC_PLL_MUL_2 RCC_CFGR_PLLMUL2 /*!< PLL input clock*2 */ |
AnnaBridge | 171:3a7713b1edbc | 450 | #define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMUL3 /*!< PLL input clock*3 */ |
AnnaBridge | 171:3a7713b1edbc | 451 | #define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMUL4 /*!< PLL input clock*4 */ |
AnnaBridge | 171:3a7713b1edbc | 452 | #define LL_RCC_PLL_MUL_5 RCC_CFGR_PLLMUL5 /*!< PLL input clock*5 */ |
AnnaBridge | 171:3a7713b1edbc | 453 | #define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMUL6 /*!< PLL input clock*6 */ |
AnnaBridge | 171:3a7713b1edbc | 454 | #define LL_RCC_PLL_MUL_7 RCC_CFGR_PLLMUL7 /*!< PLL input clock*7 */ |
AnnaBridge | 171:3a7713b1edbc | 455 | #define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMUL8 /*!< PLL input clock*8 */ |
AnnaBridge | 171:3a7713b1edbc | 456 | #define LL_RCC_PLL_MUL_9 RCC_CFGR_PLLMUL9 /*!< PLL input clock*9 */ |
AnnaBridge | 171:3a7713b1edbc | 457 | #define LL_RCC_PLL_MUL_10 RCC_CFGR_PLLMUL10 /*!< PLL input clock*10 */ |
AnnaBridge | 171:3a7713b1edbc | 458 | #define LL_RCC_PLL_MUL_11 RCC_CFGR_PLLMUL11 /*!< PLL input clock*11 */ |
AnnaBridge | 171:3a7713b1edbc | 459 | #define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMUL12 /*!< PLL input clock*12 */ |
AnnaBridge | 171:3a7713b1edbc | 460 | #define LL_RCC_PLL_MUL_13 RCC_CFGR_PLLMUL13 /*!< PLL input clock*13 */ |
AnnaBridge | 171:3a7713b1edbc | 461 | #define LL_RCC_PLL_MUL_14 RCC_CFGR_PLLMUL14 /*!< PLL input clock*14 */ |
AnnaBridge | 171:3a7713b1edbc | 462 | #define LL_RCC_PLL_MUL_15 RCC_CFGR_PLLMUL15 /*!< PLL input clock*15 */ |
AnnaBridge | 171:3a7713b1edbc | 463 | #define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMUL16 /*!< PLL input clock*16 */ |
AnnaBridge | 171:3a7713b1edbc | 464 | /** |
AnnaBridge | 171:3a7713b1edbc | 465 | * @} |
AnnaBridge | 171:3a7713b1edbc | 466 | */ |
AnnaBridge | 171:3a7713b1edbc | 467 | |
AnnaBridge | 171:3a7713b1edbc | 468 | /** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE |
AnnaBridge | 171:3a7713b1edbc | 469 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 470 | */ |
AnnaBridge | 171:3a7713b1edbc | 471 | #define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< HSE/PREDIV clock selected as PLL entry clock source */ |
AnnaBridge | 171:3a7713b1edbc | 472 | #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) |
AnnaBridge | 171:3a7713b1edbc | 473 | #define LL_RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV /*!< HSI/PREDIV clock selected as PLL entry clock source */ |
AnnaBridge | 171:3a7713b1edbc | 474 | #if defined(RCC_CFGR_SW_HSI48) |
AnnaBridge | 171:3a7713b1edbc | 475 | #define LL_RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV /*!< HSI48/PREDIV clock selected as PLL entry clock source */ |
AnnaBridge | 171:3a7713b1edbc | 476 | #endif /* RCC_CFGR_SW_HSI48 */ |
AnnaBridge | 171:3a7713b1edbc | 477 | #else |
AnnaBridge | 171:3a7713b1edbc | 478 | #define LL_RCC_PLLSOURCE_HSI_DIV_2 RCC_CFGR_PLLSRC_HSI_DIV2 /*!< HSI clock divided by 2 selected as PLL entry clock source */ |
AnnaBridge | 171:3a7713b1edbc | 479 | #define LL_RCC_PLLSOURCE_HSE_DIV_1 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV1) /*!< HSE clock selected as PLL entry clock source */ |
AnnaBridge | 171:3a7713b1edbc | 480 | #define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV2) /*!< HSE/2 clock selected as PLL entry clock source */ |
AnnaBridge | 171:3a7713b1edbc | 481 | #define LL_RCC_PLLSOURCE_HSE_DIV_3 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV3) /*!< HSE/3 clock selected as PLL entry clock source */ |
AnnaBridge | 171:3a7713b1edbc | 482 | #define LL_RCC_PLLSOURCE_HSE_DIV_4 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV4) /*!< HSE/4 clock selected as PLL entry clock source */ |
AnnaBridge | 171:3a7713b1edbc | 483 | #define LL_RCC_PLLSOURCE_HSE_DIV_5 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV5) /*!< HSE/5 clock selected as PLL entry clock source */ |
AnnaBridge | 171:3a7713b1edbc | 484 | #define LL_RCC_PLLSOURCE_HSE_DIV_6 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV6) /*!< HSE/6 clock selected as PLL entry clock source */ |
AnnaBridge | 171:3a7713b1edbc | 485 | #define LL_RCC_PLLSOURCE_HSE_DIV_7 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV7) /*!< HSE/7 clock selected as PLL entry clock source */ |
AnnaBridge | 171:3a7713b1edbc | 486 | #define LL_RCC_PLLSOURCE_HSE_DIV_8 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV8) /*!< HSE/8 clock selected as PLL entry clock source */ |
AnnaBridge | 171:3a7713b1edbc | 487 | #define LL_RCC_PLLSOURCE_HSE_DIV_9 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV9) /*!< HSE/9 clock selected as PLL entry clock source */ |
AnnaBridge | 171:3a7713b1edbc | 488 | #define LL_RCC_PLLSOURCE_HSE_DIV_10 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV10) /*!< HSE/10 clock selected as PLL entry clock source */ |
AnnaBridge | 171:3a7713b1edbc | 489 | #define LL_RCC_PLLSOURCE_HSE_DIV_11 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV11) /*!< HSE/11 clock selected as PLL entry clock source */ |
AnnaBridge | 171:3a7713b1edbc | 490 | #define LL_RCC_PLLSOURCE_HSE_DIV_12 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV12) /*!< HSE/12 clock selected as PLL entry clock source */ |
AnnaBridge | 171:3a7713b1edbc | 491 | #define LL_RCC_PLLSOURCE_HSE_DIV_13 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV13) /*!< HSE/13 clock selected as PLL entry clock source */ |
AnnaBridge | 171:3a7713b1edbc | 492 | #define LL_RCC_PLLSOURCE_HSE_DIV_14 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV14) /*!< HSE/14 clock selected as PLL entry clock source */ |
AnnaBridge | 171:3a7713b1edbc | 493 | #define LL_RCC_PLLSOURCE_HSE_DIV_15 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV15) /*!< HSE/15 clock selected as PLL entry clock source */ |
AnnaBridge | 171:3a7713b1edbc | 494 | #define LL_RCC_PLLSOURCE_HSE_DIV_16 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV16) /*!< HSE/16 clock selected as PLL entry clock source */ |
AnnaBridge | 171:3a7713b1edbc | 495 | #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ |
AnnaBridge | 171:3a7713b1edbc | 496 | /** |
AnnaBridge | 171:3a7713b1edbc | 497 | * @} |
AnnaBridge | 171:3a7713b1edbc | 498 | */ |
AnnaBridge | 171:3a7713b1edbc | 499 | |
AnnaBridge | 171:3a7713b1edbc | 500 | /** @defgroup RCC_LL_EC_PREDIV_DIV PREDIV Division factor |
AnnaBridge | 171:3a7713b1edbc | 501 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 502 | */ |
AnnaBridge | 171:3a7713b1edbc | 503 | #define LL_RCC_PREDIV_DIV_1 RCC_CFGR2_PREDIV_DIV1 /*!< PREDIV input clock not divided */ |
AnnaBridge | 171:3a7713b1edbc | 504 | #define LL_RCC_PREDIV_DIV_2 RCC_CFGR2_PREDIV_DIV2 /*!< PREDIV input clock divided by 2 */ |
AnnaBridge | 171:3a7713b1edbc | 505 | #define LL_RCC_PREDIV_DIV_3 RCC_CFGR2_PREDIV_DIV3 /*!< PREDIV input clock divided by 3 */ |
AnnaBridge | 171:3a7713b1edbc | 506 | #define LL_RCC_PREDIV_DIV_4 RCC_CFGR2_PREDIV_DIV4 /*!< PREDIV input clock divided by 4 */ |
AnnaBridge | 171:3a7713b1edbc | 507 | #define LL_RCC_PREDIV_DIV_5 RCC_CFGR2_PREDIV_DIV5 /*!< PREDIV input clock divided by 5 */ |
AnnaBridge | 171:3a7713b1edbc | 508 | #define LL_RCC_PREDIV_DIV_6 RCC_CFGR2_PREDIV_DIV6 /*!< PREDIV input clock divided by 6 */ |
AnnaBridge | 171:3a7713b1edbc | 509 | #define LL_RCC_PREDIV_DIV_7 RCC_CFGR2_PREDIV_DIV7 /*!< PREDIV input clock divided by 7 */ |
AnnaBridge | 171:3a7713b1edbc | 510 | #define LL_RCC_PREDIV_DIV_8 RCC_CFGR2_PREDIV_DIV8 /*!< PREDIV input clock divided by 8 */ |
AnnaBridge | 171:3a7713b1edbc | 511 | #define LL_RCC_PREDIV_DIV_9 RCC_CFGR2_PREDIV_DIV9 /*!< PREDIV input clock divided by 9 */ |
AnnaBridge | 171:3a7713b1edbc | 512 | #define LL_RCC_PREDIV_DIV_10 RCC_CFGR2_PREDIV_DIV10 /*!< PREDIV input clock divided by 10 */ |
AnnaBridge | 171:3a7713b1edbc | 513 | #define LL_RCC_PREDIV_DIV_11 RCC_CFGR2_PREDIV_DIV11 /*!< PREDIV input clock divided by 11 */ |
AnnaBridge | 171:3a7713b1edbc | 514 | #define LL_RCC_PREDIV_DIV_12 RCC_CFGR2_PREDIV_DIV12 /*!< PREDIV input clock divided by 12 */ |
AnnaBridge | 171:3a7713b1edbc | 515 | #define LL_RCC_PREDIV_DIV_13 RCC_CFGR2_PREDIV_DIV13 /*!< PREDIV input clock divided by 13 */ |
AnnaBridge | 171:3a7713b1edbc | 516 | #define LL_RCC_PREDIV_DIV_14 RCC_CFGR2_PREDIV_DIV14 /*!< PREDIV input clock divided by 14 */ |
AnnaBridge | 171:3a7713b1edbc | 517 | #define LL_RCC_PREDIV_DIV_15 RCC_CFGR2_PREDIV_DIV15 /*!< PREDIV input clock divided by 15 */ |
AnnaBridge | 171:3a7713b1edbc | 518 | #define LL_RCC_PREDIV_DIV_16 RCC_CFGR2_PREDIV_DIV16 /*!< PREDIV input clock divided by 16 */ |
AnnaBridge | 171:3a7713b1edbc | 519 | /** |
AnnaBridge | 171:3a7713b1edbc | 520 | * @} |
AnnaBridge | 171:3a7713b1edbc | 521 | */ |
AnnaBridge | 171:3a7713b1edbc | 522 | |
AnnaBridge | 171:3a7713b1edbc | 523 | /** |
AnnaBridge | 171:3a7713b1edbc | 524 | * @} |
AnnaBridge | 171:3a7713b1edbc | 525 | */ |
AnnaBridge | 171:3a7713b1edbc | 526 | |
AnnaBridge | 171:3a7713b1edbc | 527 | /* Exported macro ------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 528 | /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros |
AnnaBridge | 171:3a7713b1edbc | 529 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 530 | */ |
AnnaBridge | 171:3a7713b1edbc | 531 | |
AnnaBridge | 171:3a7713b1edbc | 532 | /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros |
AnnaBridge | 171:3a7713b1edbc | 533 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 534 | */ |
AnnaBridge | 171:3a7713b1edbc | 535 | |
AnnaBridge | 171:3a7713b1edbc | 536 | /** |
AnnaBridge | 171:3a7713b1edbc | 537 | * @brief Write a value in RCC register |
AnnaBridge | 171:3a7713b1edbc | 538 | * @param __REG__ Register to be written |
AnnaBridge | 171:3a7713b1edbc | 539 | * @param __VALUE__ Value to be written in the register |
AnnaBridge | 171:3a7713b1edbc | 540 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 541 | */ |
AnnaBridge | 171:3a7713b1edbc | 542 | #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) |
AnnaBridge | 171:3a7713b1edbc | 543 | |
AnnaBridge | 171:3a7713b1edbc | 544 | /** |
AnnaBridge | 171:3a7713b1edbc | 545 | * @brief Read a value in RCC register |
AnnaBridge | 171:3a7713b1edbc | 546 | * @param __REG__ Register to be read |
AnnaBridge | 171:3a7713b1edbc | 547 | * @retval Register value |
AnnaBridge | 171:3a7713b1edbc | 548 | */ |
AnnaBridge | 171:3a7713b1edbc | 549 | #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) |
AnnaBridge | 171:3a7713b1edbc | 550 | /** |
AnnaBridge | 171:3a7713b1edbc | 551 | * @} |
AnnaBridge | 171:3a7713b1edbc | 552 | */ |
AnnaBridge | 171:3a7713b1edbc | 553 | |
AnnaBridge | 171:3a7713b1edbc | 554 | /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies |
AnnaBridge | 171:3a7713b1edbc | 555 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 556 | */ |
AnnaBridge | 171:3a7713b1edbc | 557 | |
AnnaBridge | 171:3a7713b1edbc | 558 | #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) |
AnnaBridge | 171:3a7713b1edbc | 559 | /** |
AnnaBridge | 171:3a7713b1edbc | 560 | * @brief Helper macro to calculate the PLLCLK frequency |
AnnaBridge | 171:3a7713b1edbc | 561 | * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetMultiplicator() |
AnnaBridge | 171:3a7713b1edbc | 562 | * , @ref LL_RCC_PLL_GetPrediv()); |
AnnaBridge | 171:3a7713b1edbc | 563 | * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI/HSI48) |
AnnaBridge | 171:3a7713b1edbc | 564 | * @param __PLLMUL__ This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 565 | * @arg @ref LL_RCC_PLL_MUL_2 |
AnnaBridge | 171:3a7713b1edbc | 566 | * @arg @ref LL_RCC_PLL_MUL_3 |
AnnaBridge | 171:3a7713b1edbc | 567 | * @arg @ref LL_RCC_PLL_MUL_4 |
AnnaBridge | 171:3a7713b1edbc | 568 | * @arg @ref LL_RCC_PLL_MUL_5 |
AnnaBridge | 171:3a7713b1edbc | 569 | * @arg @ref LL_RCC_PLL_MUL_6 |
AnnaBridge | 171:3a7713b1edbc | 570 | * @arg @ref LL_RCC_PLL_MUL_7 |
AnnaBridge | 171:3a7713b1edbc | 571 | * @arg @ref LL_RCC_PLL_MUL_8 |
AnnaBridge | 171:3a7713b1edbc | 572 | * @arg @ref LL_RCC_PLL_MUL_9 |
AnnaBridge | 171:3a7713b1edbc | 573 | * @arg @ref LL_RCC_PLL_MUL_10 |
AnnaBridge | 171:3a7713b1edbc | 574 | * @arg @ref LL_RCC_PLL_MUL_11 |
AnnaBridge | 171:3a7713b1edbc | 575 | * @arg @ref LL_RCC_PLL_MUL_12 |
AnnaBridge | 171:3a7713b1edbc | 576 | * @arg @ref LL_RCC_PLL_MUL_13 |
AnnaBridge | 171:3a7713b1edbc | 577 | * @arg @ref LL_RCC_PLL_MUL_14 |
AnnaBridge | 171:3a7713b1edbc | 578 | * @arg @ref LL_RCC_PLL_MUL_15 |
AnnaBridge | 171:3a7713b1edbc | 579 | * @arg @ref LL_RCC_PLL_MUL_16 |
AnnaBridge | 171:3a7713b1edbc | 580 | * @param __PLLPREDIV__ This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 581 | * @arg @ref LL_RCC_PREDIV_DIV_1 |
AnnaBridge | 171:3a7713b1edbc | 582 | * @arg @ref LL_RCC_PREDIV_DIV_2 |
AnnaBridge | 171:3a7713b1edbc | 583 | * @arg @ref LL_RCC_PREDIV_DIV_3 |
AnnaBridge | 171:3a7713b1edbc | 584 | * @arg @ref LL_RCC_PREDIV_DIV_4 |
AnnaBridge | 171:3a7713b1edbc | 585 | * @arg @ref LL_RCC_PREDIV_DIV_5 |
AnnaBridge | 171:3a7713b1edbc | 586 | * @arg @ref LL_RCC_PREDIV_DIV_6 |
AnnaBridge | 171:3a7713b1edbc | 587 | * @arg @ref LL_RCC_PREDIV_DIV_7 |
AnnaBridge | 171:3a7713b1edbc | 588 | * @arg @ref LL_RCC_PREDIV_DIV_8 |
AnnaBridge | 171:3a7713b1edbc | 589 | * @arg @ref LL_RCC_PREDIV_DIV_9 |
AnnaBridge | 171:3a7713b1edbc | 590 | * @arg @ref LL_RCC_PREDIV_DIV_10 |
AnnaBridge | 171:3a7713b1edbc | 591 | * @arg @ref LL_RCC_PREDIV_DIV_11 |
AnnaBridge | 171:3a7713b1edbc | 592 | * @arg @ref LL_RCC_PREDIV_DIV_12 |
AnnaBridge | 171:3a7713b1edbc | 593 | * @arg @ref LL_RCC_PREDIV_DIV_13 |
AnnaBridge | 171:3a7713b1edbc | 594 | * @arg @ref LL_RCC_PREDIV_DIV_14 |
AnnaBridge | 171:3a7713b1edbc | 595 | * @arg @ref LL_RCC_PREDIV_DIV_15 |
AnnaBridge | 171:3a7713b1edbc | 596 | * @arg @ref LL_RCC_PREDIV_DIV_16 |
AnnaBridge | 171:3a7713b1edbc | 597 | * @retval PLL clock frequency (in Hz) |
AnnaBridge | 171:3a7713b1edbc | 598 | */ |
AnnaBridge | 171:3a7713b1edbc | 599 | #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__, __PLLPREDIV__) \ |
AnnaBridge | 171:3a7713b1edbc | 600 | (((__INPUTFREQ__) / ((((__PLLPREDIV__) & RCC_CFGR2_PREDIV) + 1U))) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U)) |
AnnaBridge | 171:3a7713b1edbc | 601 | |
AnnaBridge | 171:3a7713b1edbc | 602 | #else |
AnnaBridge | 171:3a7713b1edbc | 603 | /** |
AnnaBridge | 171:3a7713b1edbc | 604 | * @brief Helper macro to calculate the PLLCLK frequency |
AnnaBridge | 171:3a7713b1edbc | 605 | * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator()); |
AnnaBridge | 171:3a7713b1edbc | 606 | * @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv / HSI div 2) |
AnnaBridge | 171:3a7713b1edbc | 607 | * @param __PLLMUL__ This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 608 | * @arg @ref LL_RCC_PLL_MUL_2 |
AnnaBridge | 171:3a7713b1edbc | 609 | * @arg @ref LL_RCC_PLL_MUL_3 |
AnnaBridge | 171:3a7713b1edbc | 610 | * @arg @ref LL_RCC_PLL_MUL_4 |
AnnaBridge | 171:3a7713b1edbc | 611 | * @arg @ref LL_RCC_PLL_MUL_5 |
AnnaBridge | 171:3a7713b1edbc | 612 | * @arg @ref LL_RCC_PLL_MUL_6 |
AnnaBridge | 171:3a7713b1edbc | 613 | * @arg @ref LL_RCC_PLL_MUL_7 |
AnnaBridge | 171:3a7713b1edbc | 614 | * @arg @ref LL_RCC_PLL_MUL_8 |
AnnaBridge | 171:3a7713b1edbc | 615 | * @arg @ref LL_RCC_PLL_MUL_9 |
AnnaBridge | 171:3a7713b1edbc | 616 | * @arg @ref LL_RCC_PLL_MUL_10 |
AnnaBridge | 171:3a7713b1edbc | 617 | * @arg @ref LL_RCC_PLL_MUL_11 |
AnnaBridge | 171:3a7713b1edbc | 618 | * @arg @ref LL_RCC_PLL_MUL_12 |
AnnaBridge | 171:3a7713b1edbc | 619 | * @arg @ref LL_RCC_PLL_MUL_13 |
AnnaBridge | 171:3a7713b1edbc | 620 | * @arg @ref LL_RCC_PLL_MUL_14 |
AnnaBridge | 171:3a7713b1edbc | 621 | * @arg @ref LL_RCC_PLL_MUL_15 |
AnnaBridge | 171:3a7713b1edbc | 622 | * @arg @ref LL_RCC_PLL_MUL_16 |
AnnaBridge | 171:3a7713b1edbc | 623 | * @retval PLL clock frequency (in Hz) |
AnnaBridge | 171:3a7713b1edbc | 624 | */ |
AnnaBridge | 171:3a7713b1edbc | 625 | #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) \ |
AnnaBridge | 171:3a7713b1edbc | 626 | ((__INPUTFREQ__) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U)) |
AnnaBridge | 171:3a7713b1edbc | 627 | #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ |
AnnaBridge | 171:3a7713b1edbc | 628 | /** |
AnnaBridge | 171:3a7713b1edbc | 629 | * @brief Helper macro to calculate the HCLK frequency |
AnnaBridge | 171:3a7713b1edbc | 630 | * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler |
AnnaBridge | 171:3a7713b1edbc | 631 | * ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler()) |
AnnaBridge | 171:3a7713b1edbc | 632 | * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK) |
AnnaBridge | 171:3a7713b1edbc | 633 | * @param __AHBPRESCALER__ This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 634 | * @arg @ref LL_RCC_SYSCLK_DIV_1 |
AnnaBridge | 171:3a7713b1edbc | 635 | * @arg @ref LL_RCC_SYSCLK_DIV_2 |
AnnaBridge | 171:3a7713b1edbc | 636 | * @arg @ref LL_RCC_SYSCLK_DIV_4 |
AnnaBridge | 171:3a7713b1edbc | 637 | * @arg @ref LL_RCC_SYSCLK_DIV_8 |
AnnaBridge | 171:3a7713b1edbc | 638 | * @arg @ref LL_RCC_SYSCLK_DIV_16 |
AnnaBridge | 171:3a7713b1edbc | 639 | * @arg @ref LL_RCC_SYSCLK_DIV_64 |
AnnaBridge | 171:3a7713b1edbc | 640 | * @arg @ref LL_RCC_SYSCLK_DIV_128 |
AnnaBridge | 171:3a7713b1edbc | 641 | * @arg @ref LL_RCC_SYSCLK_DIV_256 |
AnnaBridge | 171:3a7713b1edbc | 642 | * @arg @ref LL_RCC_SYSCLK_DIV_512 |
AnnaBridge | 171:3a7713b1edbc | 643 | * @retval HCLK clock frequency (in Hz) |
AnnaBridge | 171:3a7713b1edbc | 644 | */ |
AnnaBridge | 171:3a7713b1edbc | 645 | #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) |
AnnaBridge | 171:3a7713b1edbc | 646 | |
AnnaBridge | 171:3a7713b1edbc | 647 | /** |
AnnaBridge | 171:3a7713b1edbc | 648 | * @brief Helper macro to calculate the PCLK1 frequency (ABP1) |
AnnaBridge | 171:3a7713b1edbc | 649 | * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler |
AnnaBridge | 171:3a7713b1edbc | 650 | * ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler()) |
AnnaBridge | 171:3a7713b1edbc | 651 | * @param __HCLKFREQ__ HCLK frequency |
AnnaBridge | 171:3a7713b1edbc | 652 | * @param __APB1PRESCALER__ This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 653 | * @arg @ref LL_RCC_APB1_DIV_1 |
AnnaBridge | 171:3a7713b1edbc | 654 | * @arg @ref LL_RCC_APB1_DIV_2 |
AnnaBridge | 171:3a7713b1edbc | 655 | * @arg @ref LL_RCC_APB1_DIV_4 |
AnnaBridge | 171:3a7713b1edbc | 656 | * @arg @ref LL_RCC_APB1_DIV_8 |
AnnaBridge | 171:3a7713b1edbc | 657 | * @arg @ref LL_RCC_APB1_DIV_16 |
AnnaBridge | 171:3a7713b1edbc | 658 | * @retval PCLK1 clock frequency (in Hz) |
AnnaBridge | 171:3a7713b1edbc | 659 | */ |
AnnaBridge | 171:3a7713b1edbc | 660 | #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE_Pos]) |
AnnaBridge | 171:3a7713b1edbc | 661 | |
AnnaBridge | 171:3a7713b1edbc | 662 | /** |
AnnaBridge | 171:3a7713b1edbc | 663 | * @} |
AnnaBridge | 171:3a7713b1edbc | 664 | */ |
AnnaBridge | 171:3a7713b1edbc | 665 | |
AnnaBridge | 171:3a7713b1edbc | 666 | /** |
AnnaBridge | 171:3a7713b1edbc | 667 | * @} |
AnnaBridge | 171:3a7713b1edbc | 668 | */ |
AnnaBridge | 171:3a7713b1edbc | 669 | |
AnnaBridge | 171:3a7713b1edbc | 670 | /* Exported functions --------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 671 | /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions |
AnnaBridge | 171:3a7713b1edbc | 672 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 673 | */ |
AnnaBridge | 171:3a7713b1edbc | 674 | |
AnnaBridge | 171:3a7713b1edbc | 675 | /** @defgroup RCC_LL_EF_HSE HSE |
AnnaBridge | 171:3a7713b1edbc | 676 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 677 | */ |
AnnaBridge | 171:3a7713b1edbc | 678 | |
AnnaBridge | 171:3a7713b1edbc | 679 | /** |
AnnaBridge | 171:3a7713b1edbc | 680 | * @brief Enable the Clock Security System. |
AnnaBridge | 171:3a7713b1edbc | 681 | * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS |
AnnaBridge | 171:3a7713b1edbc | 682 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 683 | */ |
AnnaBridge | 171:3a7713b1edbc | 684 | __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) |
AnnaBridge | 171:3a7713b1edbc | 685 | { |
AnnaBridge | 171:3a7713b1edbc | 686 | SET_BIT(RCC->CR, RCC_CR_CSSON); |
AnnaBridge | 171:3a7713b1edbc | 687 | } |
AnnaBridge | 171:3a7713b1edbc | 688 | |
AnnaBridge | 171:3a7713b1edbc | 689 | /** |
AnnaBridge | 171:3a7713b1edbc | 690 | * @brief Disable the Clock Security System. |
AnnaBridge | 171:3a7713b1edbc | 691 | * @note Cannot be disabled in HSE is ready (only by hardware) |
AnnaBridge | 171:3a7713b1edbc | 692 | * @rmtoll CR CSSON LL_RCC_HSE_DisableCSS |
AnnaBridge | 171:3a7713b1edbc | 693 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 694 | */ |
AnnaBridge | 171:3a7713b1edbc | 695 | __STATIC_INLINE void LL_RCC_HSE_DisableCSS(void) |
AnnaBridge | 171:3a7713b1edbc | 696 | { |
AnnaBridge | 171:3a7713b1edbc | 697 | CLEAR_BIT(RCC->CR, RCC_CR_CSSON); |
AnnaBridge | 171:3a7713b1edbc | 698 | } |
AnnaBridge | 171:3a7713b1edbc | 699 | |
AnnaBridge | 171:3a7713b1edbc | 700 | /** |
AnnaBridge | 171:3a7713b1edbc | 701 | * @brief Enable HSE external oscillator (HSE Bypass) |
AnnaBridge | 171:3a7713b1edbc | 702 | * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass |
AnnaBridge | 171:3a7713b1edbc | 703 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 704 | */ |
AnnaBridge | 171:3a7713b1edbc | 705 | __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) |
AnnaBridge | 171:3a7713b1edbc | 706 | { |
AnnaBridge | 171:3a7713b1edbc | 707 | SET_BIT(RCC->CR, RCC_CR_HSEBYP); |
AnnaBridge | 171:3a7713b1edbc | 708 | } |
AnnaBridge | 171:3a7713b1edbc | 709 | |
AnnaBridge | 171:3a7713b1edbc | 710 | /** |
AnnaBridge | 171:3a7713b1edbc | 711 | * @brief Disable HSE external oscillator (HSE Bypass) |
AnnaBridge | 171:3a7713b1edbc | 712 | * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass |
AnnaBridge | 171:3a7713b1edbc | 713 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 714 | */ |
AnnaBridge | 171:3a7713b1edbc | 715 | __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) |
AnnaBridge | 171:3a7713b1edbc | 716 | { |
AnnaBridge | 171:3a7713b1edbc | 717 | CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); |
AnnaBridge | 171:3a7713b1edbc | 718 | } |
AnnaBridge | 171:3a7713b1edbc | 719 | |
AnnaBridge | 171:3a7713b1edbc | 720 | /** |
AnnaBridge | 171:3a7713b1edbc | 721 | * @brief Enable HSE crystal oscillator (HSE ON) |
AnnaBridge | 171:3a7713b1edbc | 722 | * @rmtoll CR HSEON LL_RCC_HSE_Enable |
AnnaBridge | 171:3a7713b1edbc | 723 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 724 | */ |
AnnaBridge | 171:3a7713b1edbc | 725 | __STATIC_INLINE void LL_RCC_HSE_Enable(void) |
AnnaBridge | 171:3a7713b1edbc | 726 | { |
AnnaBridge | 171:3a7713b1edbc | 727 | SET_BIT(RCC->CR, RCC_CR_HSEON); |
AnnaBridge | 171:3a7713b1edbc | 728 | } |
AnnaBridge | 171:3a7713b1edbc | 729 | |
AnnaBridge | 171:3a7713b1edbc | 730 | /** |
AnnaBridge | 171:3a7713b1edbc | 731 | * @brief Disable HSE crystal oscillator (HSE ON) |
AnnaBridge | 171:3a7713b1edbc | 732 | * @rmtoll CR HSEON LL_RCC_HSE_Disable |
AnnaBridge | 171:3a7713b1edbc | 733 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 734 | */ |
AnnaBridge | 171:3a7713b1edbc | 735 | __STATIC_INLINE void LL_RCC_HSE_Disable(void) |
AnnaBridge | 171:3a7713b1edbc | 736 | { |
AnnaBridge | 171:3a7713b1edbc | 737 | CLEAR_BIT(RCC->CR, RCC_CR_HSEON); |
AnnaBridge | 171:3a7713b1edbc | 738 | } |
AnnaBridge | 171:3a7713b1edbc | 739 | |
AnnaBridge | 171:3a7713b1edbc | 740 | /** |
AnnaBridge | 171:3a7713b1edbc | 741 | * @brief Check if HSE oscillator Ready |
AnnaBridge | 171:3a7713b1edbc | 742 | * @rmtoll CR HSERDY LL_RCC_HSE_IsReady |
AnnaBridge | 171:3a7713b1edbc | 743 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 744 | */ |
AnnaBridge | 171:3a7713b1edbc | 745 | __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) |
AnnaBridge | 171:3a7713b1edbc | 746 | { |
AnnaBridge | 171:3a7713b1edbc | 747 | return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)); |
AnnaBridge | 171:3a7713b1edbc | 748 | } |
AnnaBridge | 171:3a7713b1edbc | 749 | |
AnnaBridge | 171:3a7713b1edbc | 750 | /** |
AnnaBridge | 171:3a7713b1edbc | 751 | * @} |
AnnaBridge | 171:3a7713b1edbc | 752 | */ |
AnnaBridge | 171:3a7713b1edbc | 753 | |
AnnaBridge | 171:3a7713b1edbc | 754 | /** @defgroup RCC_LL_EF_HSI HSI |
AnnaBridge | 171:3a7713b1edbc | 755 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 756 | */ |
AnnaBridge | 171:3a7713b1edbc | 757 | |
AnnaBridge | 171:3a7713b1edbc | 758 | /** |
AnnaBridge | 171:3a7713b1edbc | 759 | * @brief Enable HSI oscillator |
AnnaBridge | 171:3a7713b1edbc | 760 | * @rmtoll CR HSION LL_RCC_HSI_Enable |
AnnaBridge | 171:3a7713b1edbc | 761 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 762 | */ |
AnnaBridge | 171:3a7713b1edbc | 763 | __STATIC_INLINE void LL_RCC_HSI_Enable(void) |
AnnaBridge | 171:3a7713b1edbc | 764 | { |
AnnaBridge | 171:3a7713b1edbc | 765 | SET_BIT(RCC->CR, RCC_CR_HSION); |
AnnaBridge | 171:3a7713b1edbc | 766 | } |
AnnaBridge | 171:3a7713b1edbc | 767 | |
AnnaBridge | 171:3a7713b1edbc | 768 | /** |
AnnaBridge | 171:3a7713b1edbc | 769 | * @brief Disable HSI oscillator |
AnnaBridge | 171:3a7713b1edbc | 770 | * @rmtoll CR HSION LL_RCC_HSI_Disable |
AnnaBridge | 171:3a7713b1edbc | 771 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 772 | */ |
AnnaBridge | 171:3a7713b1edbc | 773 | __STATIC_INLINE void LL_RCC_HSI_Disable(void) |
AnnaBridge | 171:3a7713b1edbc | 774 | { |
AnnaBridge | 171:3a7713b1edbc | 775 | CLEAR_BIT(RCC->CR, RCC_CR_HSION); |
AnnaBridge | 171:3a7713b1edbc | 776 | } |
AnnaBridge | 171:3a7713b1edbc | 777 | |
AnnaBridge | 171:3a7713b1edbc | 778 | /** |
AnnaBridge | 171:3a7713b1edbc | 779 | * @brief Check if HSI clock is ready |
AnnaBridge | 171:3a7713b1edbc | 780 | * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady |
AnnaBridge | 171:3a7713b1edbc | 781 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 782 | */ |
AnnaBridge | 171:3a7713b1edbc | 783 | __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) |
AnnaBridge | 171:3a7713b1edbc | 784 | { |
AnnaBridge | 171:3a7713b1edbc | 785 | return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)); |
AnnaBridge | 171:3a7713b1edbc | 786 | } |
AnnaBridge | 171:3a7713b1edbc | 787 | |
AnnaBridge | 171:3a7713b1edbc | 788 | /** |
AnnaBridge | 171:3a7713b1edbc | 789 | * @brief Get HSI Calibration value |
AnnaBridge | 171:3a7713b1edbc | 790 | * @note When HSITRIM is written, HSICAL is updated with the sum of |
AnnaBridge | 171:3a7713b1edbc | 791 | * HSITRIM and the factory trim value |
AnnaBridge | 171:3a7713b1edbc | 792 | * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration |
AnnaBridge | 171:3a7713b1edbc | 793 | * @retval Between Min_Data = 0x00 and Max_Data = 0xFF |
AnnaBridge | 171:3a7713b1edbc | 794 | */ |
AnnaBridge | 171:3a7713b1edbc | 795 | __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) |
AnnaBridge | 171:3a7713b1edbc | 796 | { |
AnnaBridge | 171:3a7713b1edbc | 797 | return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos); |
AnnaBridge | 171:3a7713b1edbc | 798 | } |
AnnaBridge | 171:3a7713b1edbc | 799 | |
AnnaBridge | 171:3a7713b1edbc | 800 | /** |
AnnaBridge | 171:3a7713b1edbc | 801 | * @brief Set HSI Calibration trimming |
AnnaBridge | 171:3a7713b1edbc | 802 | * @note user-programmable trimming value that is added to the HSICAL |
AnnaBridge | 171:3a7713b1edbc | 803 | * @note Default value is 16, which, when added to the HSICAL value, |
AnnaBridge | 171:3a7713b1edbc | 804 | * should trim the HSI to 16 MHz +/- 1 % |
AnnaBridge | 171:3a7713b1edbc | 805 | * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming |
AnnaBridge | 171:3a7713b1edbc | 806 | * @param Value between Min_Data = 0x00 and Max_Data = 0x1F |
AnnaBridge | 171:3a7713b1edbc | 807 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 808 | */ |
AnnaBridge | 171:3a7713b1edbc | 809 | __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) |
AnnaBridge | 171:3a7713b1edbc | 810 | { |
AnnaBridge | 171:3a7713b1edbc | 811 | MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos); |
AnnaBridge | 171:3a7713b1edbc | 812 | } |
AnnaBridge | 171:3a7713b1edbc | 813 | |
AnnaBridge | 171:3a7713b1edbc | 814 | /** |
AnnaBridge | 171:3a7713b1edbc | 815 | * @brief Get HSI Calibration trimming |
AnnaBridge | 171:3a7713b1edbc | 816 | * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming |
AnnaBridge | 171:3a7713b1edbc | 817 | * @retval Between Min_Data = 0x00 and Max_Data = 0x1F |
AnnaBridge | 171:3a7713b1edbc | 818 | */ |
AnnaBridge | 171:3a7713b1edbc | 819 | __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) |
AnnaBridge | 171:3a7713b1edbc | 820 | { |
AnnaBridge | 171:3a7713b1edbc | 821 | return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); |
AnnaBridge | 171:3a7713b1edbc | 822 | } |
AnnaBridge | 171:3a7713b1edbc | 823 | |
AnnaBridge | 171:3a7713b1edbc | 824 | /** |
AnnaBridge | 171:3a7713b1edbc | 825 | * @} |
AnnaBridge | 171:3a7713b1edbc | 826 | */ |
AnnaBridge | 171:3a7713b1edbc | 827 | |
AnnaBridge | 171:3a7713b1edbc | 828 | #if defined(RCC_HSI48_SUPPORT) |
AnnaBridge | 171:3a7713b1edbc | 829 | /** @defgroup RCC_LL_EF_HSI48 HSI48 |
AnnaBridge | 171:3a7713b1edbc | 830 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 831 | */ |
AnnaBridge | 171:3a7713b1edbc | 832 | |
AnnaBridge | 171:3a7713b1edbc | 833 | /** |
AnnaBridge | 171:3a7713b1edbc | 834 | * @brief Enable HSI48 |
AnnaBridge | 171:3a7713b1edbc | 835 | * @rmtoll CR2 HSI48ON LL_RCC_HSI48_Enable |
AnnaBridge | 171:3a7713b1edbc | 836 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 837 | */ |
AnnaBridge | 171:3a7713b1edbc | 838 | __STATIC_INLINE void LL_RCC_HSI48_Enable(void) |
AnnaBridge | 171:3a7713b1edbc | 839 | { |
AnnaBridge | 171:3a7713b1edbc | 840 | SET_BIT(RCC->CR2, RCC_CR2_HSI48ON); |
AnnaBridge | 171:3a7713b1edbc | 841 | } |
AnnaBridge | 171:3a7713b1edbc | 842 | |
AnnaBridge | 171:3a7713b1edbc | 843 | /** |
AnnaBridge | 171:3a7713b1edbc | 844 | * @brief Disable HSI48 |
AnnaBridge | 171:3a7713b1edbc | 845 | * @rmtoll CR2 HSI48ON LL_RCC_HSI48_Disable |
AnnaBridge | 171:3a7713b1edbc | 846 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 847 | */ |
AnnaBridge | 171:3a7713b1edbc | 848 | __STATIC_INLINE void LL_RCC_HSI48_Disable(void) |
AnnaBridge | 171:3a7713b1edbc | 849 | { |
AnnaBridge | 171:3a7713b1edbc | 850 | CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON); |
AnnaBridge | 171:3a7713b1edbc | 851 | } |
AnnaBridge | 171:3a7713b1edbc | 852 | |
AnnaBridge | 171:3a7713b1edbc | 853 | /** |
AnnaBridge | 171:3a7713b1edbc | 854 | * @brief Check if HSI48 oscillator Ready |
AnnaBridge | 171:3a7713b1edbc | 855 | * @rmtoll CR2 HSI48RDY LL_RCC_HSI48_IsReady |
AnnaBridge | 171:3a7713b1edbc | 856 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 857 | */ |
AnnaBridge | 171:3a7713b1edbc | 858 | __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void) |
AnnaBridge | 171:3a7713b1edbc | 859 | { |
AnnaBridge | 171:3a7713b1edbc | 860 | return (READ_BIT(RCC->CR2, RCC_CR2_HSI48RDY) == (RCC_CR2_HSI48RDY)); |
AnnaBridge | 171:3a7713b1edbc | 861 | } |
AnnaBridge | 171:3a7713b1edbc | 862 | |
AnnaBridge | 171:3a7713b1edbc | 863 | /** |
AnnaBridge | 171:3a7713b1edbc | 864 | * @brief Get HSI48 Calibration value |
AnnaBridge | 171:3a7713b1edbc | 865 | * @rmtoll CR2 HSI48CAL LL_RCC_HSI48_GetCalibration |
AnnaBridge | 171:3a7713b1edbc | 866 | * @retval Between Min_Data = 0x00 and Max_Data = 0xFF |
AnnaBridge | 171:3a7713b1edbc | 867 | */ |
AnnaBridge | 171:3a7713b1edbc | 868 | __STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void) |
AnnaBridge | 171:3a7713b1edbc | 869 | { |
AnnaBridge | 171:3a7713b1edbc | 870 | return (uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI48CAL) >> RCC_POSITION_HSI48CAL); |
AnnaBridge | 171:3a7713b1edbc | 871 | } |
AnnaBridge | 171:3a7713b1edbc | 872 | |
AnnaBridge | 171:3a7713b1edbc | 873 | /** |
AnnaBridge | 171:3a7713b1edbc | 874 | * @} |
AnnaBridge | 171:3a7713b1edbc | 875 | */ |
AnnaBridge | 171:3a7713b1edbc | 876 | |
AnnaBridge | 171:3a7713b1edbc | 877 | #endif /* RCC_HSI48_SUPPORT */ |
AnnaBridge | 171:3a7713b1edbc | 878 | |
AnnaBridge | 171:3a7713b1edbc | 879 | /** @defgroup RCC_LL_EF_HSI14 HSI14 |
AnnaBridge | 171:3a7713b1edbc | 880 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 881 | */ |
AnnaBridge | 171:3a7713b1edbc | 882 | |
AnnaBridge | 171:3a7713b1edbc | 883 | /** |
AnnaBridge | 171:3a7713b1edbc | 884 | * @brief Enable HSI14 |
AnnaBridge | 171:3a7713b1edbc | 885 | * @rmtoll CR2 HSI14ON LL_RCC_HSI14_Enable |
AnnaBridge | 171:3a7713b1edbc | 886 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 887 | */ |
AnnaBridge | 171:3a7713b1edbc | 888 | __STATIC_INLINE void LL_RCC_HSI14_Enable(void) |
AnnaBridge | 171:3a7713b1edbc | 889 | { |
AnnaBridge | 171:3a7713b1edbc | 890 | SET_BIT(RCC->CR2, RCC_CR2_HSI14ON); |
AnnaBridge | 171:3a7713b1edbc | 891 | } |
AnnaBridge | 171:3a7713b1edbc | 892 | |
AnnaBridge | 171:3a7713b1edbc | 893 | /** |
AnnaBridge | 171:3a7713b1edbc | 894 | * @brief Disable HSI14 |
AnnaBridge | 171:3a7713b1edbc | 895 | * @rmtoll CR2 HSI14ON LL_RCC_HSI14_Disable |
AnnaBridge | 171:3a7713b1edbc | 896 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 897 | */ |
AnnaBridge | 171:3a7713b1edbc | 898 | __STATIC_INLINE void LL_RCC_HSI14_Disable(void) |
AnnaBridge | 171:3a7713b1edbc | 899 | { |
AnnaBridge | 171:3a7713b1edbc | 900 | CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14ON); |
AnnaBridge | 171:3a7713b1edbc | 901 | } |
AnnaBridge | 171:3a7713b1edbc | 902 | |
AnnaBridge | 171:3a7713b1edbc | 903 | /** |
AnnaBridge | 171:3a7713b1edbc | 904 | * @brief Check if HSI14 oscillator Ready |
AnnaBridge | 171:3a7713b1edbc | 905 | * @rmtoll CR2 HSI14RDY LL_RCC_HSI14_IsReady |
AnnaBridge | 171:3a7713b1edbc | 906 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 907 | */ |
AnnaBridge | 171:3a7713b1edbc | 908 | __STATIC_INLINE uint32_t LL_RCC_HSI14_IsReady(void) |
AnnaBridge | 171:3a7713b1edbc | 909 | { |
AnnaBridge | 171:3a7713b1edbc | 910 | return (READ_BIT(RCC->CR2, RCC_CR2_HSI14RDY) == (RCC_CR2_HSI14RDY)); |
AnnaBridge | 171:3a7713b1edbc | 911 | } |
AnnaBridge | 171:3a7713b1edbc | 912 | |
AnnaBridge | 171:3a7713b1edbc | 913 | /** |
AnnaBridge | 171:3a7713b1edbc | 914 | * @brief ADC interface can turn on the HSI14 oscillator |
AnnaBridge | 171:3a7713b1edbc | 915 | * @rmtoll CR2 HSI14DIS LL_RCC_HSI14_EnableADCControl |
AnnaBridge | 171:3a7713b1edbc | 916 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 917 | */ |
AnnaBridge | 171:3a7713b1edbc | 918 | __STATIC_INLINE void LL_RCC_HSI14_EnableADCControl(void) |
AnnaBridge | 171:3a7713b1edbc | 919 | { |
AnnaBridge | 171:3a7713b1edbc | 920 | CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14DIS); |
AnnaBridge | 171:3a7713b1edbc | 921 | } |
AnnaBridge | 171:3a7713b1edbc | 922 | |
AnnaBridge | 171:3a7713b1edbc | 923 | /** |
AnnaBridge | 171:3a7713b1edbc | 924 | * @brief ADC interface can not turn on the HSI14 oscillator |
AnnaBridge | 171:3a7713b1edbc | 925 | * @rmtoll CR2 HSI14DIS LL_RCC_HSI14_DisableADCControl |
AnnaBridge | 171:3a7713b1edbc | 926 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 927 | */ |
AnnaBridge | 171:3a7713b1edbc | 928 | __STATIC_INLINE void LL_RCC_HSI14_DisableADCControl(void) |
AnnaBridge | 171:3a7713b1edbc | 929 | { |
AnnaBridge | 171:3a7713b1edbc | 930 | SET_BIT(RCC->CR2, RCC_CR2_HSI14DIS); |
AnnaBridge | 171:3a7713b1edbc | 931 | } |
AnnaBridge | 171:3a7713b1edbc | 932 | |
AnnaBridge | 171:3a7713b1edbc | 933 | /** |
AnnaBridge | 171:3a7713b1edbc | 934 | * @brief Set HSI14 Calibration trimming |
AnnaBridge | 171:3a7713b1edbc | 935 | * @note user-programmable trimming value that is added to the HSI14CAL |
AnnaBridge | 171:3a7713b1edbc | 936 | * @note Default value is 16, which, when added to the HSI14CAL value, |
AnnaBridge | 171:3a7713b1edbc | 937 | * should trim the HSI14 to 14 MHz +/- 1 % |
AnnaBridge | 171:3a7713b1edbc | 938 | * @rmtoll CR2 HSI14TRIM LL_RCC_HSI14_SetCalibTrimming |
AnnaBridge | 171:3a7713b1edbc | 939 | * @param Value between Min_Data = 0x00 and Max_Data = 0xFF |
AnnaBridge | 171:3a7713b1edbc | 940 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 941 | */ |
AnnaBridge | 171:3a7713b1edbc | 942 | __STATIC_INLINE void LL_RCC_HSI14_SetCalibTrimming(uint32_t Value) |
AnnaBridge | 171:3a7713b1edbc | 943 | { |
AnnaBridge | 171:3a7713b1edbc | 944 | MODIFY_REG(RCC->CR2, RCC_CR2_HSI14TRIM, Value << RCC_POSITION_HSI14TRIM); |
AnnaBridge | 171:3a7713b1edbc | 945 | } |
AnnaBridge | 171:3a7713b1edbc | 946 | |
AnnaBridge | 171:3a7713b1edbc | 947 | /** |
AnnaBridge | 171:3a7713b1edbc | 948 | * @brief Get HSI14 Calibration value |
AnnaBridge | 171:3a7713b1edbc | 949 | * @note When HSI14TRIM is written, HSI14CAL is updated with the sum of |
AnnaBridge | 171:3a7713b1edbc | 950 | * HSI14TRIM and the factory trim value |
AnnaBridge | 171:3a7713b1edbc | 951 | * @rmtoll CR2 HSI14TRIM LL_RCC_HSI14_GetCalibTrimming |
AnnaBridge | 171:3a7713b1edbc | 952 | * @retval Between Min_Data = 0x00 and Max_Data = 0x1F |
AnnaBridge | 171:3a7713b1edbc | 953 | */ |
AnnaBridge | 171:3a7713b1edbc | 954 | __STATIC_INLINE uint32_t LL_RCC_HSI14_GetCalibTrimming(void) |
AnnaBridge | 171:3a7713b1edbc | 955 | { |
AnnaBridge | 171:3a7713b1edbc | 956 | return (uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI14TRIM) >> RCC_POSITION_HSI14TRIM); |
AnnaBridge | 171:3a7713b1edbc | 957 | } |
AnnaBridge | 171:3a7713b1edbc | 958 | |
AnnaBridge | 171:3a7713b1edbc | 959 | /** |
AnnaBridge | 171:3a7713b1edbc | 960 | * @brief Get HSI14 Calibration trimming |
AnnaBridge | 171:3a7713b1edbc | 961 | * @rmtoll CR2 HSI14CAL LL_RCC_HSI14_GetCalibration |
AnnaBridge | 171:3a7713b1edbc | 962 | * @retval Between Min_Data = 0x00 and Max_Data = 0x1F |
AnnaBridge | 171:3a7713b1edbc | 963 | */ |
AnnaBridge | 171:3a7713b1edbc | 964 | __STATIC_INLINE uint32_t LL_RCC_HSI14_GetCalibration(void) |
AnnaBridge | 171:3a7713b1edbc | 965 | { |
AnnaBridge | 171:3a7713b1edbc | 966 | return (uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI14CAL) >> RCC_POSITION_HSI14CAL); |
AnnaBridge | 171:3a7713b1edbc | 967 | } |
AnnaBridge | 171:3a7713b1edbc | 968 | |
AnnaBridge | 171:3a7713b1edbc | 969 | /** |
AnnaBridge | 171:3a7713b1edbc | 970 | * @} |
AnnaBridge | 171:3a7713b1edbc | 971 | */ |
AnnaBridge | 171:3a7713b1edbc | 972 | |
AnnaBridge | 171:3a7713b1edbc | 973 | /** @defgroup RCC_LL_EF_LSE LSE |
AnnaBridge | 171:3a7713b1edbc | 974 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 975 | */ |
AnnaBridge | 171:3a7713b1edbc | 976 | |
AnnaBridge | 171:3a7713b1edbc | 977 | /** |
AnnaBridge | 171:3a7713b1edbc | 978 | * @brief Enable Low Speed External (LSE) crystal. |
AnnaBridge | 171:3a7713b1edbc | 979 | * @rmtoll BDCR LSEON LL_RCC_LSE_Enable |
AnnaBridge | 171:3a7713b1edbc | 980 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 981 | */ |
AnnaBridge | 171:3a7713b1edbc | 982 | __STATIC_INLINE void LL_RCC_LSE_Enable(void) |
AnnaBridge | 171:3a7713b1edbc | 983 | { |
AnnaBridge | 171:3a7713b1edbc | 984 | SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); |
AnnaBridge | 171:3a7713b1edbc | 985 | } |
AnnaBridge | 171:3a7713b1edbc | 986 | |
AnnaBridge | 171:3a7713b1edbc | 987 | /** |
AnnaBridge | 171:3a7713b1edbc | 988 | * @brief Disable Low Speed External (LSE) crystal. |
AnnaBridge | 171:3a7713b1edbc | 989 | * @rmtoll BDCR LSEON LL_RCC_LSE_Disable |
AnnaBridge | 171:3a7713b1edbc | 990 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 991 | */ |
AnnaBridge | 171:3a7713b1edbc | 992 | __STATIC_INLINE void LL_RCC_LSE_Disable(void) |
AnnaBridge | 171:3a7713b1edbc | 993 | { |
AnnaBridge | 171:3a7713b1edbc | 994 | CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); |
AnnaBridge | 171:3a7713b1edbc | 995 | } |
AnnaBridge | 171:3a7713b1edbc | 996 | |
AnnaBridge | 171:3a7713b1edbc | 997 | /** |
AnnaBridge | 171:3a7713b1edbc | 998 | * @brief Enable external clock source (LSE bypass). |
AnnaBridge | 171:3a7713b1edbc | 999 | * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass |
AnnaBridge | 171:3a7713b1edbc | 1000 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1001 | */ |
AnnaBridge | 171:3a7713b1edbc | 1002 | __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) |
AnnaBridge | 171:3a7713b1edbc | 1003 | { |
AnnaBridge | 171:3a7713b1edbc | 1004 | SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); |
AnnaBridge | 171:3a7713b1edbc | 1005 | } |
AnnaBridge | 171:3a7713b1edbc | 1006 | |
AnnaBridge | 171:3a7713b1edbc | 1007 | /** |
AnnaBridge | 171:3a7713b1edbc | 1008 | * @brief Disable external clock source (LSE bypass). |
AnnaBridge | 171:3a7713b1edbc | 1009 | * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass |
AnnaBridge | 171:3a7713b1edbc | 1010 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1011 | */ |
AnnaBridge | 171:3a7713b1edbc | 1012 | __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) |
AnnaBridge | 171:3a7713b1edbc | 1013 | { |
AnnaBridge | 171:3a7713b1edbc | 1014 | CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); |
AnnaBridge | 171:3a7713b1edbc | 1015 | } |
AnnaBridge | 171:3a7713b1edbc | 1016 | |
AnnaBridge | 171:3a7713b1edbc | 1017 | /** |
AnnaBridge | 171:3a7713b1edbc | 1018 | * @brief Set LSE oscillator drive capability |
AnnaBridge | 171:3a7713b1edbc | 1019 | * @note The oscillator is in Xtal mode when it is not in bypass mode. |
AnnaBridge | 171:3a7713b1edbc | 1020 | * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability |
AnnaBridge | 171:3a7713b1edbc | 1021 | * @param LSEDrive This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1022 | * @arg @ref LL_RCC_LSEDRIVE_LOW |
AnnaBridge | 171:3a7713b1edbc | 1023 | * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW |
AnnaBridge | 171:3a7713b1edbc | 1024 | * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH |
AnnaBridge | 171:3a7713b1edbc | 1025 | * @arg @ref LL_RCC_LSEDRIVE_HIGH |
AnnaBridge | 171:3a7713b1edbc | 1026 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1027 | */ |
AnnaBridge | 171:3a7713b1edbc | 1028 | __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) |
AnnaBridge | 171:3a7713b1edbc | 1029 | { |
AnnaBridge | 171:3a7713b1edbc | 1030 | MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive); |
AnnaBridge | 171:3a7713b1edbc | 1031 | } |
AnnaBridge | 171:3a7713b1edbc | 1032 | |
AnnaBridge | 171:3a7713b1edbc | 1033 | /** |
AnnaBridge | 171:3a7713b1edbc | 1034 | * @brief Get LSE oscillator drive capability |
AnnaBridge | 171:3a7713b1edbc | 1035 | * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability |
AnnaBridge | 171:3a7713b1edbc | 1036 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1037 | * @arg @ref LL_RCC_LSEDRIVE_LOW |
AnnaBridge | 171:3a7713b1edbc | 1038 | * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW |
AnnaBridge | 171:3a7713b1edbc | 1039 | * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH |
AnnaBridge | 171:3a7713b1edbc | 1040 | * @arg @ref LL_RCC_LSEDRIVE_HIGH |
AnnaBridge | 171:3a7713b1edbc | 1041 | */ |
AnnaBridge | 171:3a7713b1edbc | 1042 | __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void) |
AnnaBridge | 171:3a7713b1edbc | 1043 | { |
AnnaBridge | 171:3a7713b1edbc | 1044 | return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV)); |
AnnaBridge | 171:3a7713b1edbc | 1045 | } |
AnnaBridge | 171:3a7713b1edbc | 1046 | |
AnnaBridge | 171:3a7713b1edbc | 1047 | /** |
AnnaBridge | 171:3a7713b1edbc | 1048 | * @brief Check if LSE oscillator Ready |
AnnaBridge | 171:3a7713b1edbc | 1049 | * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady |
AnnaBridge | 171:3a7713b1edbc | 1050 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1051 | */ |
AnnaBridge | 171:3a7713b1edbc | 1052 | __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) |
AnnaBridge | 171:3a7713b1edbc | 1053 | { |
AnnaBridge | 171:3a7713b1edbc | 1054 | return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)); |
AnnaBridge | 171:3a7713b1edbc | 1055 | } |
AnnaBridge | 171:3a7713b1edbc | 1056 | |
AnnaBridge | 171:3a7713b1edbc | 1057 | /** |
AnnaBridge | 171:3a7713b1edbc | 1058 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1059 | */ |
AnnaBridge | 171:3a7713b1edbc | 1060 | |
AnnaBridge | 171:3a7713b1edbc | 1061 | /** @defgroup RCC_LL_EF_LSI LSI |
AnnaBridge | 171:3a7713b1edbc | 1062 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1063 | */ |
AnnaBridge | 171:3a7713b1edbc | 1064 | |
AnnaBridge | 171:3a7713b1edbc | 1065 | /** |
AnnaBridge | 171:3a7713b1edbc | 1066 | * @brief Enable LSI Oscillator |
AnnaBridge | 171:3a7713b1edbc | 1067 | * @rmtoll CSR LSION LL_RCC_LSI_Enable |
AnnaBridge | 171:3a7713b1edbc | 1068 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1069 | */ |
AnnaBridge | 171:3a7713b1edbc | 1070 | __STATIC_INLINE void LL_RCC_LSI_Enable(void) |
AnnaBridge | 171:3a7713b1edbc | 1071 | { |
AnnaBridge | 171:3a7713b1edbc | 1072 | SET_BIT(RCC->CSR, RCC_CSR_LSION); |
AnnaBridge | 171:3a7713b1edbc | 1073 | } |
AnnaBridge | 171:3a7713b1edbc | 1074 | |
AnnaBridge | 171:3a7713b1edbc | 1075 | /** |
AnnaBridge | 171:3a7713b1edbc | 1076 | * @brief Disable LSI Oscillator |
AnnaBridge | 171:3a7713b1edbc | 1077 | * @rmtoll CSR LSION LL_RCC_LSI_Disable |
AnnaBridge | 171:3a7713b1edbc | 1078 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1079 | */ |
AnnaBridge | 171:3a7713b1edbc | 1080 | __STATIC_INLINE void LL_RCC_LSI_Disable(void) |
AnnaBridge | 171:3a7713b1edbc | 1081 | { |
AnnaBridge | 171:3a7713b1edbc | 1082 | CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); |
AnnaBridge | 171:3a7713b1edbc | 1083 | } |
AnnaBridge | 171:3a7713b1edbc | 1084 | |
AnnaBridge | 171:3a7713b1edbc | 1085 | /** |
AnnaBridge | 171:3a7713b1edbc | 1086 | * @brief Check if LSI is Ready |
AnnaBridge | 171:3a7713b1edbc | 1087 | * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady |
AnnaBridge | 171:3a7713b1edbc | 1088 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1089 | */ |
AnnaBridge | 171:3a7713b1edbc | 1090 | __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) |
AnnaBridge | 171:3a7713b1edbc | 1091 | { |
AnnaBridge | 171:3a7713b1edbc | 1092 | return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)); |
AnnaBridge | 171:3a7713b1edbc | 1093 | } |
AnnaBridge | 171:3a7713b1edbc | 1094 | |
AnnaBridge | 171:3a7713b1edbc | 1095 | /** |
AnnaBridge | 171:3a7713b1edbc | 1096 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1097 | */ |
AnnaBridge | 171:3a7713b1edbc | 1098 | |
AnnaBridge | 171:3a7713b1edbc | 1099 | /** @defgroup RCC_LL_EF_System System |
AnnaBridge | 171:3a7713b1edbc | 1100 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1101 | */ |
AnnaBridge | 171:3a7713b1edbc | 1102 | |
AnnaBridge | 171:3a7713b1edbc | 1103 | /** |
AnnaBridge | 171:3a7713b1edbc | 1104 | * @brief Configure the system clock source |
AnnaBridge | 171:3a7713b1edbc | 1105 | * @rmtoll CFGR SW LL_RCC_SetSysClkSource |
AnnaBridge | 171:3a7713b1edbc | 1106 | * @param Source This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1107 | * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI |
AnnaBridge | 171:3a7713b1edbc | 1108 | * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE |
AnnaBridge | 171:3a7713b1edbc | 1109 | * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL |
AnnaBridge | 171:3a7713b1edbc | 1110 | * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI48 (*) |
AnnaBridge | 171:3a7713b1edbc | 1111 | * |
AnnaBridge | 171:3a7713b1edbc | 1112 | * (*) value not defined in all devices |
AnnaBridge | 171:3a7713b1edbc | 1113 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1114 | */ |
AnnaBridge | 171:3a7713b1edbc | 1115 | __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) |
AnnaBridge | 171:3a7713b1edbc | 1116 | { |
AnnaBridge | 171:3a7713b1edbc | 1117 | MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); |
AnnaBridge | 171:3a7713b1edbc | 1118 | } |
AnnaBridge | 171:3a7713b1edbc | 1119 | |
AnnaBridge | 171:3a7713b1edbc | 1120 | /** |
AnnaBridge | 171:3a7713b1edbc | 1121 | * @brief Get the system clock source |
AnnaBridge | 171:3a7713b1edbc | 1122 | * @rmtoll CFGR SWS LL_RCC_GetSysClkSource |
AnnaBridge | 171:3a7713b1edbc | 1123 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1124 | * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI |
AnnaBridge | 171:3a7713b1edbc | 1125 | * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE |
AnnaBridge | 171:3a7713b1edbc | 1126 | * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL |
AnnaBridge | 171:3a7713b1edbc | 1127 | * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI48 (*) |
AnnaBridge | 171:3a7713b1edbc | 1128 | * |
AnnaBridge | 171:3a7713b1edbc | 1129 | * (*) value not defined in all devices |
AnnaBridge | 171:3a7713b1edbc | 1130 | */ |
AnnaBridge | 171:3a7713b1edbc | 1131 | __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) |
AnnaBridge | 171:3a7713b1edbc | 1132 | { |
AnnaBridge | 171:3a7713b1edbc | 1133 | return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); |
AnnaBridge | 171:3a7713b1edbc | 1134 | } |
AnnaBridge | 171:3a7713b1edbc | 1135 | |
AnnaBridge | 171:3a7713b1edbc | 1136 | /** |
AnnaBridge | 171:3a7713b1edbc | 1137 | * @brief Set AHB prescaler |
AnnaBridge | 171:3a7713b1edbc | 1138 | * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler |
AnnaBridge | 171:3a7713b1edbc | 1139 | * @param Prescaler This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1140 | * @arg @ref LL_RCC_SYSCLK_DIV_1 |
AnnaBridge | 171:3a7713b1edbc | 1141 | * @arg @ref LL_RCC_SYSCLK_DIV_2 |
AnnaBridge | 171:3a7713b1edbc | 1142 | * @arg @ref LL_RCC_SYSCLK_DIV_4 |
AnnaBridge | 171:3a7713b1edbc | 1143 | * @arg @ref LL_RCC_SYSCLK_DIV_8 |
AnnaBridge | 171:3a7713b1edbc | 1144 | * @arg @ref LL_RCC_SYSCLK_DIV_16 |
AnnaBridge | 171:3a7713b1edbc | 1145 | * @arg @ref LL_RCC_SYSCLK_DIV_64 |
AnnaBridge | 171:3a7713b1edbc | 1146 | * @arg @ref LL_RCC_SYSCLK_DIV_128 |
AnnaBridge | 171:3a7713b1edbc | 1147 | * @arg @ref LL_RCC_SYSCLK_DIV_256 |
AnnaBridge | 171:3a7713b1edbc | 1148 | * @arg @ref LL_RCC_SYSCLK_DIV_512 |
AnnaBridge | 171:3a7713b1edbc | 1149 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1150 | */ |
AnnaBridge | 171:3a7713b1edbc | 1151 | __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) |
AnnaBridge | 171:3a7713b1edbc | 1152 | { |
AnnaBridge | 171:3a7713b1edbc | 1153 | MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); |
AnnaBridge | 171:3a7713b1edbc | 1154 | } |
AnnaBridge | 171:3a7713b1edbc | 1155 | |
AnnaBridge | 171:3a7713b1edbc | 1156 | /** |
AnnaBridge | 171:3a7713b1edbc | 1157 | * @brief Set APB1 prescaler |
AnnaBridge | 171:3a7713b1edbc | 1158 | * @rmtoll CFGR PPRE LL_RCC_SetAPB1Prescaler |
AnnaBridge | 171:3a7713b1edbc | 1159 | * @param Prescaler This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1160 | * @arg @ref LL_RCC_APB1_DIV_1 |
AnnaBridge | 171:3a7713b1edbc | 1161 | * @arg @ref LL_RCC_APB1_DIV_2 |
AnnaBridge | 171:3a7713b1edbc | 1162 | * @arg @ref LL_RCC_APB1_DIV_4 |
AnnaBridge | 171:3a7713b1edbc | 1163 | * @arg @ref LL_RCC_APB1_DIV_8 |
AnnaBridge | 171:3a7713b1edbc | 1164 | * @arg @ref LL_RCC_APB1_DIV_16 |
AnnaBridge | 171:3a7713b1edbc | 1165 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1166 | */ |
AnnaBridge | 171:3a7713b1edbc | 1167 | __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) |
AnnaBridge | 171:3a7713b1edbc | 1168 | { |
AnnaBridge | 171:3a7713b1edbc | 1169 | MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, Prescaler); |
AnnaBridge | 171:3a7713b1edbc | 1170 | } |
AnnaBridge | 171:3a7713b1edbc | 1171 | |
AnnaBridge | 171:3a7713b1edbc | 1172 | /** |
AnnaBridge | 171:3a7713b1edbc | 1173 | * @brief Get AHB prescaler |
AnnaBridge | 171:3a7713b1edbc | 1174 | * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler |
AnnaBridge | 171:3a7713b1edbc | 1175 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1176 | * @arg @ref LL_RCC_SYSCLK_DIV_1 |
AnnaBridge | 171:3a7713b1edbc | 1177 | * @arg @ref LL_RCC_SYSCLK_DIV_2 |
AnnaBridge | 171:3a7713b1edbc | 1178 | * @arg @ref LL_RCC_SYSCLK_DIV_4 |
AnnaBridge | 171:3a7713b1edbc | 1179 | * @arg @ref LL_RCC_SYSCLK_DIV_8 |
AnnaBridge | 171:3a7713b1edbc | 1180 | * @arg @ref LL_RCC_SYSCLK_DIV_16 |
AnnaBridge | 171:3a7713b1edbc | 1181 | * @arg @ref LL_RCC_SYSCLK_DIV_64 |
AnnaBridge | 171:3a7713b1edbc | 1182 | * @arg @ref LL_RCC_SYSCLK_DIV_128 |
AnnaBridge | 171:3a7713b1edbc | 1183 | * @arg @ref LL_RCC_SYSCLK_DIV_256 |
AnnaBridge | 171:3a7713b1edbc | 1184 | * @arg @ref LL_RCC_SYSCLK_DIV_512 |
AnnaBridge | 171:3a7713b1edbc | 1185 | */ |
AnnaBridge | 171:3a7713b1edbc | 1186 | __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) |
AnnaBridge | 171:3a7713b1edbc | 1187 | { |
AnnaBridge | 171:3a7713b1edbc | 1188 | return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); |
AnnaBridge | 171:3a7713b1edbc | 1189 | } |
AnnaBridge | 171:3a7713b1edbc | 1190 | |
AnnaBridge | 171:3a7713b1edbc | 1191 | /** |
AnnaBridge | 171:3a7713b1edbc | 1192 | * @brief Get APB1 prescaler |
AnnaBridge | 171:3a7713b1edbc | 1193 | * @rmtoll CFGR PPRE LL_RCC_GetAPB1Prescaler |
AnnaBridge | 171:3a7713b1edbc | 1194 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1195 | * @arg @ref LL_RCC_APB1_DIV_1 |
AnnaBridge | 171:3a7713b1edbc | 1196 | * @arg @ref LL_RCC_APB1_DIV_2 |
AnnaBridge | 171:3a7713b1edbc | 1197 | * @arg @ref LL_RCC_APB1_DIV_4 |
AnnaBridge | 171:3a7713b1edbc | 1198 | * @arg @ref LL_RCC_APB1_DIV_8 |
AnnaBridge | 171:3a7713b1edbc | 1199 | * @arg @ref LL_RCC_APB1_DIV_16 |
AnnaBridge | 171:3a7713b1edbc | 1200 | */ |
AnnaBridge | 171:3a7713b1edbc | 1201 | __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) |
AnnaBridge | 171:3a7713b1edbc | 1202 | { |
AnnaBridge | 171:3a7713b1edbc | 1203 | return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE)); |
AnnaBridge | 171:3a7713b1edbc | 1204 | } |
AnnaBridge | 171:3a7713b1edbc | 1205 | |
AnnaBridge | 171:3a7713b1edbc | 1206 | /** |
AnnaBridge | 171:3a7713b1edbc | 1207 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1208 | */ |
AnnaBridge | 171:3a7713b1edbc | 1209 | |
AnnaBridge | 171:3a7713b1edbc | 1210 | /** @defgroup RCC_LL_EF_MCO MCO |
AnnaBridge | 171:3a7713b1edbc | 1211 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1212 | */ |
AnnaBridge | 171:3a7713b1edbc | 1213 | |
AnnaBridge | 171:3a7713b1edbc | 1214 | /** |
AnnaBridge | 171:3a7713b1edbc | 1215 | * @brief Configure MCOx |
AnnaBridge | 171:3a7713b1edbc | 1216 | * @rmtoll CFGR MCO LL_RCC_ConfigMCO\n |
AnnaBridge | 171:3a7713b1edbc | 1217 | * CFGR MCOPRE LL_RCC_ConfigMCO\n |
AnnaBridge | 171:3a7713b1edbc | 1218 | * CFGR PLLNODIV LL_RCC_ConfigMCO |
AnnaBridge | 171:3a7713b1edbc | 1219 | * @param MCOxSource This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1220 | * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK |
AnnaBridge | 171:3a7713b1edbc | 1221 | * @arg @ref LL_RCC_MCO1SOURCE_HSI14 |
AnnaBridge | 171:3a7713b1edbc | 1222 | * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK |
AnnaBridge | 171:3a7713b1edbc | 1223 | * @arg @ref LL_RCC_MCO1SOURCE_HSI |
AnnaBridge | 171:3a7713b1edbc | 1224 | * @arg @ref LL_RCC_MCO1SOURCE_HSE |
AnnaBridge | 171:3a7713b1edbc | 1225 | * @arg @ref LL_RCC_MCO1SOURCE_LSI |
AnnaBridge | 171:3a7713b1edbc | 1226 | * @arg @ref LL_RCC_MCO1SOURCE_LSE |
AnnaBridge | 171:3a7713b1edbc | 1227 | * @arg @ref LL_RCC_MCO1SOURCE_HSI48 (*) |
AnnaBridge | 171:3a7713b1edbc | 1228 | * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK (*) |
AnnaBridge | 171:3a7713b1edbc | 1229 | * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 |
AnnaBridge | 171:3a7713b1edbc | 1230 | * |
AnnaBridge | 171:3a7713b1edbc | 1231 | * (*) value not defined in all devices |
AnnaBridge | 171:3a7713b1edbc | 1232 | * @param MCOxPrescaler This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1233 | * @arg @ref LL_RCC_MCO1_DIV_1 |
AnnaBridge | 171:3a7713b1edbc | 1234 | * @arg @ref LL_RCC_MCO1_DIV_2 (*) |
AnnaBridge | 171:3a7713b1edbc | 1235 | * @arg @ref LL_RCC_MCO1_DIV_4 (*) |
AnnaBridge | 171:3a7713b1edbc | 1236 | * @arg @ref LL_RCC_MCO1_DIV_8 (*) |
AnnaBridge | 171:3a7713b1edbc | 1237 | * @arg @ref LL_RCC_MCO1_DIV_16 (*) |
AnnaBridge | 171:3a7713b1edbc | 1238 | * @arg @ref LL_RCC_MCO1_DIV_32 (*) |
AnnaBridge | 171:3a7713b1edbc | 1239 | * @arg @ref LL_RCC_MCO1_DIV_64 (*) |
AnnaBridge | 171:3a7713b1edbc | 1240 | * @arg @ref LL_RCC_MCO1_DIV_128 (*) |
AnnaBridge | 171:3a7713b1edbc | 1241 | * |
AnnaBridge | 171:3a7713b1edbc | 1242 | * (*) value not defined in all devices |
AnnaBridge | 171:3a7713b1edbc | 1243 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1244 | */ |
AnnaBridge | 171:3a7713b1edbc | 1245 | __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) |
AnnaBridge | 171:3a7713b1edbc | 1246 | { |
AnnaBridge | 171:3a7713b1edbc | 1247 | #if defined(RCC_CFGR_MCOPRE) |
AnnaBridge | 171:3a7713b1edbc | 1248 | #if defined(RCC_CFGR_PLLNODIV) |
AnnaBridge | 171:3a7713b1edbc | 1249 | MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE | RCC_CFGR_PLLNODIV, MCOxSource | MCOxPrescaler); |
AnnaBridge | 171:3a7713b1edbc | 1250 | #else |
AnnaBridge | 171:3a7713b1edbc | 1251 | MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler); |
AnnaBridge | 171:3a7713b1edbc | 1252 | #endif /* RCC_CFGR_PLLNODIV */ |
AnnaBridge | 171:3a7713b1edbc | 1253 | #else |
AnnaBridge | 171:3a7713b1edbc | 1254 | MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL, MCOxSource); |
AnnaBridge | 171:3a7713b1edbc | 1255 | #endif /* RCC_CFGR_MCOPRE */ |
AnnaBridge | 171:3a7713b1edbc | 1256 | } |
AnnaBridge | 171:3a7713b1edbc | 1257 | |
AnnaBridge | 171:3a7713b1edbc | 1258 | /** |
AnnaBridge | 171:3a7713b1edbc | 1259 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1260 | */ |
AnnaBridge | 171:3a7713b1edbc | 1261 | |
AnnaBridge | 171:3a7713b1edbc | 1262 | /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source |
AnnaBridge | 171:3a7713b1edbc | 1263 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1264 | */ |
AnnaBridge | 171:3a7713b1edbc | 1265 | |
AnnaBridge | 171:3a7713b1edbc | 1266 | /** |
AnnaBridge | 171:3a7713b1edbc | 1267 | * @brief Configure USARTx clock source |
AnnaBridge | 171:3a7713b1edbc | 1268 | * @rmtoll CFGR3 USART1SW LL_RCC_SetUSARTClockSource\n |
AnnaBridge | 171:3a7713b1edbc | 1269 | * CFGR3 USART2SW LL_RCC_SetUSARTClockSource\n |
AnnaBridge | 171:3a7713b1edbc | 1270 | * CFGR3 USART3SW LL_RCC_SetUSARTClockSource |
AnnaBridge | 171:3a7713b1edbc | 1271 | * @param USARTxSource This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1272 | * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1 |
AnnaBridge | 171:3a7713b1edbc | 1273 | * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK |
AnnaBridge | 171:3a7713b1edbc | 1274 | * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE |
AnnaBridge | 171:3a7713b1edbc | 1275 | * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI |
AnnaBridge | 171:3a7713b1edbc | 1276 | * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*) |
AnnaBridge | 171:3a7713b1edbc | 1277 | * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*) |
AnnaBridge | 171:3a7713b1edbc | 1278 | * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*) |
AnnaBridge | 171:3a7713b1edbc | 1279 | * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*) |
AnnaBridge | 171:3a7713b1edbc | 1280 | * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*) |
AnnaBridge | 171:3a7713b1edbc | 1281 | * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*) |
AnnaBridge | 171:3a7713b1edbc | 1282 | * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*) |
AnnaBridge | 171:3a7713b1edbc | 1283 | * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*) |
AnnaBridge | 171:3a7713b1edbc | 1284 | * |
AnnaBridge | 171:3a7713b1edbc | 1285 | * (*) value not defined in all devices. |
AnnaBridge | 171:3a7713b1edbc | 1286 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1287 | */ |
AnnaBridge | 171:3a7713b1edbc | 1288 | __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource) |
AnnaBridge | 171:3a7713b1edbc | 1289 | { |
AnnaBridge | 171:3a7713b1edbc | 1290 | MODIFY_REG(RCC->CFGR3, (RCC_CFGR3_USART1SW << ((USARTxSource & 0xFF000000U) >> 24U)), (USARTxSource & 0x00FFFFFFU)); |
AnnaBridge | 171:3a7713b1edbc | 1291 | } |
AnnaBridge | 171:3a7713b1edbc | 1292 | |
AnnaBridge | 171:3a7713b1edbc | 1293 | /** |
AnnaBridge | 171:3a7713b1edbc | 1294 | * @brief Configure I2Cx clock source |
AnnaBridge | 171:3a7713b1edbc | 1295 | * @rmtoll CFGR3 I2C1SW LL_RCC_SetI2CClockSource |
AnnaBridge | 171:3a7713b1edbc | 1296 | * @param I2CxSource This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1297 | * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI |
AnnaBridge | 171:3a7713b1edbc | 1298 | * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK |
AnnaBridge | 171:3a7713b1edbc | 1299 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1300 | */ |
AnnaBridge | 171:3a7713b1edbc | 1301 | __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) |
AnnaBridge | 171:3a7713b1edbc | 1302 | { |
AnnaBridge | 171:3a7713b1edbc | 1303 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, I2CxSource); |
AnnaBridge | 171:3a7713b1edbc | 1304 | } |
AnnaBridge | 171:3a7713b1edbc | 1305 | |
AnnaBridge | 171:3a7713b1edbc | 1306 | #if defined(CEC) |
AnnaBridge | 171:3a7713b1edbc | 1307 | /** |
AnnaBridge | 171:3a7713b1edbc | 1308 | * @brief Configure CEC clock source |
AnnaBridge | 171:3a7713b1edbc | 1309 | * @rmtoll CFGR3 CECSW LL_RCC_SetCECClockSource |
AnnaBridge | 171:3a7713b1edbc | 1310 | * @param CECxSource This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1311 | * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV244 |
AnnaBridge | 171:3a7713b1edbc | 1312 | * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE |
AnnaBridge | 171:3a7713b1edbc | 1313 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1314 | */ |
AnnaBridge | 171:3a7713b1edbc | 1315 | __STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t CECxSource) |
AnnaBridge | 171:3a7713b1edbc | 1316 | { |
AnnaBridge | 171:3a7713b1edbc | 1317 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, CECxSource); |
AnnaBridge | 171:3a7713b1edbc | 1318 | } |
AnnaBridge | 171:3a7713b1edbc | 1319 | #endif /* CEC */ |
AnnaBridge | 171:3a7713b1edbc | 1320 | |
AnnaBridge | 171:3a7713b1edbc | 1321 | #if defined(USB) |
AnnaBridge | 171:3a7713b1edbc | 1322 | /** |
AnnaBridge | 171:3a7713b1edbc | 1323 | * @brief Configure USB clock source |
AnnaBridge | 171:3a7713b1edbc | 1324 | * @rmtoll CFGR3 USBSW LL_RCC_SetUSBClockSource |
AnnaBridge | 171:3a7713b1edbc | 1325 | * @param USBxSource This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1326 | * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*) |
AnnaBridge | 171:3a7713b1edbc | 1327 | * @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*) |
AnnaBridge | 171:3a7713b1edbc | 1328 | * @arg @ref LL_RCC_USB_CLKSOURCE_PLL |
AnnaBridge | 171:3a7713b1edbc | 1329 | * |
AnnaBridge | 171:3a7713b1edbc | 1330 | * (*) value not defined in all devices. |
AnnaBridge | 171:3a7713b1edbc | 1331 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1332 | */ |
AnnaBridge | 171:3a7713b1edbc | 1333 | __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) |
AnnaBridge | 171:3a7713b1edbc | 1334 | { |
AnnaBridge | 171:3a7713b1edbc | 1335 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USBSW, USBxSource); |
AnnaBridge | 171:3a7713b1edbc | 1336 | } |
AnnaBridge | 171:3a7713b1edbc | 1337 | #endif /* USB */ |
AnnaBridge | 171:3a7713b1edbc | 1338 | |
AnnaBridge | 171:3a7713b1edbc | 1339 | /** |
AnnaBridge | 171:3a7713b1edbc | 1340 | * @brief Get USARTx clock source |
AnnaBridge | 171:3a7713b1edbc | 1341 | * @rmtoll CFGR3 USART1SW LL_RCC_GetUSARTClockSource\n |
AnnaBridge | 171:3a7713b1edbc | 1342 | * CFGR3 USART2SW LL_RCC_GetUSARTClockSource\n |
AnnaBridge | 171:3a7713b1edbc | 1343 | * CFGR3 USART3SW LL_RCC_GetUSARTClockSource |
AnnaBridge | 171:3a7713b1edbc | 1344 | * @param USARTx This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1345 | * @arg @ref LL_RCC_USART1_CLKSOURCE |
AnnaBridge | 171:3a7713b1edbc | 1346 | * @arg @ref LL_RCC_USART2_CLKSOURCE (*) |
AnnaBridge | 171:3a7713b1edbc | 1347 | * @arg @ref LL_RCC_USART3_CLKSOURCE (*) |
AnnaBridge | 171:3a7713b1edbc | 1348 | * |
AnnaBridge | 171:3a7713b1edbc | 1349 | * (*) value not defined in all devices. |
AnnaBridge | 171:3a7713b1edbc | 1350 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1351 | * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1 |
AnnaBridge | 171:3a7713b1edbc | 1352 | * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK |
AnnaBridge | 171:3a7713b1edbc | 1353 | * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE |
AnnaBridge | 171:3a7713b1edbc | 1354 | * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI |
AnnaBridge | 171:3a7713b1edbc | 1355 | * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*) |
AnnaBridge | 171:3a7713b1edbc | 1356 | * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*) |
AnnaBridge | 171:3a7713b1edbc | 1357 | * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*) |
AnnaBridge | 171:3a7713b1edbc | 1358 | * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*) |
AnnaBridge | 171:3a7713b1edbc | 1359 | * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*) |
AnnaBridge | 171:3a7713b1edbc | 1360 | * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*) |
AnnaBridge | 171:3a7713b1edbc | 1361 | * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*) |
AnnaBridge | 171:3a7713b1edbc | 1362 | * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*) |
AnnaBridge | 171:3a7713b1edbc | 1363 | * |
AnnaBridge | 171:3a7713b1edbc | 1364 | * (*) value not defined in all devices. |
AnnaBridge | 171:3a7713b1edbc | 1365 | */ |
AnnaBridge | 171:3a7713b1edbc | 1366 | __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx) |
AnnaBridge | 171:3a7713b1edbc | 1367 | { |
AnnaBridge | 171:3a7713b1edbc | 1368 | return (uint32_t)(READ_BIT(RCC->CFGR3, (RCC_CFGR3_USART1SW << USARTx)) | (USARTx << 24U)); |
AnnaBridge | 171:3a7713b1edbc | 1369 | } |
AnnaBridge | 171:3a7713b1edbc | 1370 | |
AnnaBridge | 171:3a7713b1edbc | 1371 | /** |
AnnaBridge | 171:3a7713b1edbc | 1372 | * @brief Get I2Cx clock source |
AnnaBridge | 171:3a7713b1edbc | 1373 | * @rmtoll CFGR3 I2C1SW LL_RCC_GetI2CClockSource |
AnnaBridge | 171:3a7713b1edbc | 1374 | * @param I2Cx This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1375 | * @arg @ref LL_RCC_I2C1_CLKSOURCE |
AnnaBridge | 171:3a7713b1edbc | 1376 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1377 | * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI |
AnnaBridge | 171:3a7713b1edbc | 1378 | * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK |
AnnaBridge | 171:3a7713b1edbc | 1379 | */ |
AnnaBridge | 171:3a7713b1edbc | 1380 | __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx) |
AnnaBridge | 171:3a7713b1edbc | 1381 | { |
AnnaBridge | 171:3a7713b1edbc | 1382 | return (uint32_t)(READ_BIT(RCC->CFGR3, I2Cx)); |
AnnaBridge | 171:3a7713b1edbc | 1383 | } |
AnnaBridge | 171:3a7713b1edbc | 1384 | |
AnnaBridge | 171:3a7713b1edbc | 1385 | #if defined(CEC) |
AnnaBridge | 171:3a7713b1edbc | 1386 | /** |
AnnaBridge | 171:3a7713b1edbc | 1387 | * @brief Get CEC clock source |
AnnaBridge | 171:3a7713b1edbc | 1388 | * @rmtoll CFGR3 CECSW LL_RCC_GetCECClockSource |
AnnaBridge | 171:3a7713b1edbc | 1389 | * @param CECx This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1390 | * @arg @ref LL_RCC_CEC_CLKSOURCE |
AnnaBridge | 171:3a7713b1edbc | 1391 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1392 | * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV244 |
AnnaBridge | 171:3a7713b1edbc | 1393 | * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE |
AnnaBridge | 171:3a7713b1edbc | 1394 | */ |
AnnaBridge | 171:3a7713b1edbc | 1395 | __STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx) |
AnnaBridge | 171:3a7713b1edbc | 1396 | { |
AnnaBridge | 171:3a7713b1edbc | 1397 | return (uint32_t)(READ_BIT(RCC->CFGR3, CECx)); |
AnnaBridge | 171:3a7713b1edbc | 1398 | } |
AnnaBridge | 171:3a7713b1edbc | 1399 | #endif /* CEC */ |
AnnaBridge | 171:3a7713b1edbc | 1400 | |
AnnaBridge | 171:3a7713b1edbc | 1401 | #if defined(USB) |
AnnaBridge | 171:3a7713b1edbc | 1402 | /** |
AnnaBridge | 171:3a7713b1edbc | 1403 | * @brief Get USBx clock source |
AnnaBridge | 171:3a7713b1edbc | 1404 | * @rmtoll CFGR3 USBSW LL_RCC_GetUSBClockSource |
AnnaBridge | 171:3a7713b1edbc | 1405 | * @param USBx This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1406 | * @arg @ref LL_RCC_USB_CLKSOURCE |
AnnaBridge | 171:3a7713b1edbc | 1407 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1408 | * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*) |
AnnaBridge | 171:3a7713b1edbc | 1409 | * @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*) |
AnnaBridge | 171:3a7713b1edbc | 1410 | * @arg @ref LL_RCC_USB_CLKSOURCE_PLL |
AnnaBridge | 171:3a7713b1edbc | 1411 | * |
AnnaBridge | 171:3a7713b1edbc | 1412 | * (*) value not defined in all devices. |
AnnaBridge | 171:3a7713b1edbc | 1413 | */ |
AnnaBridge | 171:3a7713b1edbc | 1414 | __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) |
AnnaBridge | 171:3a7713b1edbc | 1415 | { |
AnnaBridge | 171:3a7713b1edbc | 1416 | return (uint32_t)(READ_BIT(RCC->CFGR3, USBx)); |
AnnaBridge | 171:3a7713b1edbc | 1417 | } |
AnnaBridge | 171:3a7713b1edbc | 1418 | #endif /* USB */ |
AnnaBridge | 171:3a7713b1edbc | 1419 | |
AnnaBridge | 171:3a7713b1edbc | 1420 | /** |
AnnaBridge | 171:3a7713b1edbc | 1421 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1422 | */ |
AnnaBridge | 171:3a7713b1edbc | 1423 | |
AnnaBridge | 171:3a7713b1edbc | 1424 | /** @defgroup RCC_LL_EF_RTC RTC |
AnnaBridge | 171:3a7713b1edbc | 1425 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1426 | */ |
AnnaBridge | 171:3a7713b1edbc | 1427 | |
AnnaBridge | 171:3a7713b1edbc | 1428 | /** |
AnnaBridge | 171:3a7713b1edbc | 1429 | * @brief Set RTC Clock Source |
AnnaBridge | 171:3a7713b1edbc | 1430 | * @note Once the RTC clock source has been selected, it cannot be changed any more unless |
AnnaBridge | 171:3a7713b1edbc | 1431 | * the Backup domain is reset. The BDRST bit can be used to reset them. |
AnnaBridge | 171:3a7713b1edbc | 1432 | * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource |
AnnaBridge | 171:3a7713b1edbc | 1433 | * @param Source This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1434 | * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE |
AnnaBridge | 171:3a7713b1edbc | 1435 | * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE |
AnnaBridge | 171:3a7713b1edbc | 1436 | * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI |
AnnaBridge | 171:3a7713b1edbc | 1437 | * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32 |
AnnaBridge | 171:3a7713b1edbc | 1438 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1439 | */ |
AnnaBridge | 171:3a7713b1edbc | 1440 | __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) |
AnnaBridge | 171:3a7713b1edbc | 1441 | { |
AnnaBridge | 171:3a7713b1edbc | 1442 | MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); |
AnnaBridge | 171:3a7713b1edbc | 1443 | } |
AnnaBridge | 171:3a7713b1edbc | 1444 | |
AnnaBridge | 171:3a7713b1edbc | 1445 | /** |
AnnaBridge | 171:3a7713b1edbc | 1446 | * @brief Get RTC Clock Source |
AnnaBridge | 171:3a7713b1edbc | 1447 | * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource |
AnnaBridge | 171:3a7713b1edbc | 1448 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1449 | * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE |
AnnaBridge | 171:3a7713b1edbc | 1450 | * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE |
AnnaBridge | 171:3a7713b1edbc | 1451 | * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI |
AnnaBridge | 171:3a7713b1edbc | 1452 | * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32 |
AnnaBridge | 171:3a7713b1edbc | 1453 | */ |
AnnaBridge | 171:3a7713b1edbc | 1454 | __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) |
AnnaBridge | 171:3a7713b1edbc | 1455 | { |
AnnaBridge | 171:3a7713b1edbc | 1456 | return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); |
AnnaBridge | 171:3a7713b1edbc | 1457 | } |
AnnaBridge | 171:3a7713b1edbc | 1458 | |
AnnaBridge | 171:3a7713b1edbc | 1459 | /** |
AnnaBridge | 171:3a7713b1edbc | 1460 | * @brief Enable RTC |
AnnaBridge | 171:3a7713b1edbc | 1461 | * @rmtoll BDCR RTCEN LL_RCC_EnableRTC |
AnnaBridge | 171:3a7713b1edbc | 1462 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1463 | */ |
AnnaBridge | 171:3a7713b1edbc | 1464 | __STATIC_INLINE void LL_RCC_EnableRTC(void) |
AnnaBridge | 171:3a7713b1edbc | 1465 | { |
AnnaBridge | 171:3a7713b1edbc | 1466 | SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); |
AnnaBridge | 171:3a7713b1edbc | 1467 | } |
AnnaBridge | 171:3a7713b1edbc | 1468 | |
AnnaBridge | 171:3a7713b1edbc | 1469 | /** |
AnnaBridge | 171:3a7713b1edbc | 1470 | * @brief Disable RTC |
AnnaBridge | 171:3a7713b1edbc | 1471 | * @rmtoll BDCR RTCEN LL_RCC_DisableRTC |
AnnaBridge | 171:3a7713b1edbc | 1472 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1473 | */ |
AnnaBridge | 171:3a7713b1edbc | 1474 | __STATIC_INLINE void LL_RCC_DisableRTC(void) |
AnnaBridge | 171:3a7713b1edbc | 1475 | { |
AnnaBridge | 171:3a7713b1edbc | 1476 | CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); |
AnnaBridge | 171:3a7713b1edbc | 1477 | } |
AnnaBridge | 171:3a7713b1edbc | 1478 | |
AnnaBridge | 171:3a7713b1edbc | 1479 | /** |
AnnaBridge | 171:3a7713b1edbc | 1480 | * @brief Check if RTC has been enabled or not |
AnnaBridge | 171:3a7713b1edbc | 1481 | * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC |
AnnaBridge | 171:3a7713b1edbc | 1482 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1483 | */ |
AnnaBridge | 171:3a7713b1edbc | 1484 | __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) |
AnnaBridge | 171:3a7713b1edbc | 1485 | { |
AnnaBridge | 171:3a7713b1edbc | 1486 | return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)); |
AnnaBridge | 171:3a7713b1edbc | 1487 | } |
AnnaBridge | 171:3a7713b1edbc | 1488 | |
AnnaBridge | 171:3a7713b1edbc | 1489 | /** |
AnnaBridge | 171:3a7713b1edbc | 1490 | * @brief Force the Backup domain reset |
AnnaBridge | 171:3a7713b1edbc | 1491 | * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset |
AnnaBridge | 171:3a7713b1edbc | 1492 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1493 | */ |
AnnaBridge | 171:3a7713b1edbc | 1494 | __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) |
AnnaBridge | 171:3a7713b1edbc | 1495 | { |
AnnaBridge | 171:3a7713b1edbc | 1496 | SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); |
AnnaBridge | 171:3a7713b1edbc | 1497 | } |
AnnaBridge | 171:3a7713b1edbc | 1498 | |
AnnaBridge | 171:3a7713b1edbc | 1499 | /** |
AnnaBridge | 171:3a7713b1edbc | 1500 | * @brief Release the Backup domain reset |
AnnaBridge | 171:3a7713b1edbc | 1501 | * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset |
AnnaBridge | 171:3a7713b1edbc | 1502 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1503 | */ |
AnnaBridge | 171:3a7713b1edbc | 1504 | __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) |
AnnaBridge | 171:3a7713b1edbc | 1505 | { |
AnnaBridge | 171:3a7713b1edbc | 1506 | CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); |
AnnaBridge | 171:3a7713b1edbc | 1507 | } |
AnnaBridge | 171:3a7713b1edbc | 1508 | |
AnnaBridge | 171:3a7713b1edbc | 1509 | /** |
AnnaBridge | 171:3a7713b1edbc | 1510 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1511 | */ |
AnnaBridge | 171:3a7713b1edbc | 1512 | |
AnnaBridge | 171:3a7713b1edbc | 1513 | /** @defgroup RCC_LL_EF_PLL PLL |
AnnaBridge | 171:3a7713b1edbc | 1514 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1515 | */ |
AnnaBridge | 171:3a7713b1edbc | 1516 | |
AnnaBridge | 171:3a7713b1edbc | 1517 | /** |
AnnaBridge | 171:3a7713b1edbc | 1518 | * @brief Enable PLL |
AnnaBridge | 171:3a7713b1edbc | 1519 | * @rmtoll CR PLLON LL_RCC_PLL_Enable |
AnnaBridge | 171:3a7713b1edbc | 1520 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1521 | */ |
AnnaBridge | 171:3a7713b1edbc | 1522 | __STATIC_INLINE void LL_RCC_PLL_Enable(void) |
AnnaBridge | 171:3a7713b1edbc | 1523 | { |
AnnaBridge | 171:3a7713b1edbc | 1524 | SET_BIT(RCC->CR, RCC_CR_PLLON); |
AnnaBridge | 171:3a7713b1edbc | 1525 | } |
AnnaBridge | 171:3a7713b1edbc | 1526 | |
AnnaBridge | 171:3a7713b1edbc | 1527 | /** |
AnnaBridge | 171:3a7713b1edbc | 1528 | * @brief Disable PLL |
AnnaBridge | 171:3a7713b1edbc | 1529 | * @note Cannot be disabled if the PLL clock is used as the system clock |
AnnaBridge | 171:3a7713b1edbc | 1530 | * @rmtoll CR PLLON LL_RCC_PLL_Disable |
AnnaBridge | 171:3a7713b1edbc | 1531 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1532 | */ |
AnnaBridge | 171:3a7713b1edbc | 1533 | __STATIC_INLINE void LL_RCC_PLL_Disable(void) |
AnnaBridge | 171:3a7713b1edbc | 1534 | { |
AnnaBridge | 171:3a7713b1edbc | 1535 | CLEAR_BIT(RCC->CR, RCC_CR_PLLON); |
AnnaBridge | 171:3a7713b1edbc | 1536 | } |
AnnaBridge | 171:3a7713b1edbc | 1537 | |
AnnaBridge | 171:3a7713b1edbc | 1538 | /** |
AnnaBridge | 171:3a7713b1edbc | 1539 | * @brief Check if PLL Ready |
AnnaBridge | 171:3a7713b1edbc | 1540 | * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady |
AnnaBridge | 171:3a7713b1edbc | 1541 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1542 | */ |
AnnaBridge | 171:3a7713b1edbc | 1543 | __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) |
AnnaBridge | 171:3a7713b1edbc | 1544 | { |
AnnaBridge | 171:3a7713b1edbc | 1545 | return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)); |
AnnaBridge | 171:3a7713b1edbc | 1546 | } |
AnnaBridge | 171:3a7713b1edbc | 1547 | |
AnnaBridge | 171:3a7713b1edbc | 1548 | #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) |
AnnaBridge | 171:3a7713b1edbc | 1549 | /** |
AnnaBridge | 171:3a7713b1edbc | 1550 | * @brief Configure PLL used for SYSCLK Domain |
AnnaBridge | 171:3a7713b1edbc | 1551 | * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n |
AnnaBridge | 171:3a7713b1edbc | 1552 | * CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n |
AnnaBridge | 171:3a7713b1edbc | 1553 | * CFGR2 PREDIV LL_RCC_PLL_ConfigDomain_SYS |
AnnaBridge | 171:3a7713b1edbc | 1554 | * @param Source This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1555 | * @arg @ref LL_RCC_PLLSOURCE_HSI |
AnnaBridge | 171:3a7713b1edbc | 1556 | * @arg @ref LL_RCC_PLLSOURCE_HSE |
AnnaBridge | 171:3a7713b1edbc | 1557 | * @arg @ref LL_RCC_PLLSOURCE_HSI48 (*) |
AnnaBridge | 171:3a7713b1edbc | 1558 | * |
AnnaBridge | 171:3a7713b1edbc | 1559 | * (*) value not defined in all devices |
AnnaBridge | 171:3a7713b1edbc | 1560 | * @param PLLMul This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1561 | * @arg @ref LL_RCC_PLL_MUL_2 |
AnnaBridge | 171:3a7713b1edbc | 1562 | * @arg @ref LL_RCC_PLL_MUL_3 |
AnnaBridge | 171:3a7713b1edbc | 1563 | * @arg @ref LL_RCC_PLL_MUL_4 |
AnnaBridge | 171:3a7713b1edbc | 1564 | * @arg @ref LL_RCC_PLL_MUL_5 |
AnnaBridge | 171:3a7713b1edbc | 1565 | * @arg @ref LL_RCC_PLL_MUL_6 |
AnnaBridge | 171:3a7713b1edbc | 1566 | * @arg @ref LL_RCC_PLL_MUL_7 |
AnnaBridge | 171:3a7713b1edbc | 1567 | * @arg @ref LL_RCC_PLL_MUL_8 |
AnnaBridge | 171:3a7713b1edbc | 1568 | * @arg @ref LL_RCC_PLL_MUL_9 |
AnnaBridge | 171:3a7713b1edbc | 1569 | * @arg @ref LL_RCC_PLL_MUL_10 |
AnnaBridge | 171:3a7713b1edbc | 1570 | * @arg @ref LL_RCC_PLL_MUL_11 |
AnnaBridge | 171:3a7713b1edbc | 1571 | * @arg @ref LL_RCC_PLL_MUL_12 |
AnnaBridge | 171:3a7713b1edbc | 1572 | * @arg @ref LL_RCC_PLL_MUL_13 |
AnnaBridge | 171:3a7713b1edbc | 1573 | * @arg @ref LL_RCC_PLL_MUL_14 |
AnnaBridge | 171:3a7713b1edbc | 1574 | * @arg @ref LL_RCC_PLL_MUL_15 |
AnnaBridge | 171:3a7713b1edbc | 1575 | * @arg @ref LL_RCC_PLL_MUL_16 |
AnnaBridge | 171:3a7713b1edbc | 1576 | * @param PLLDiv This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1577 | * @arg @ref LL_RCC_PREDIV_DIV_1 |
AnnaBridge | 171:3a7713b1edbc | 1578 | * @arg @ref LL_RCC_PREDIV_DIV_2 |
AnnaBridge | 171:3a7713b1edbc | 1579 | * @arg @ref LL_RCC_PREDIV_DIV_3 |
AnnaBridge | 171:3a7713b1edbc | 1580 | * @arg @ref LL_RCC_PREDIV_DIV_4 |
AnnaBridge | 171:3a7713b1edbc | 1581 | * @arg @ref LL_RCC_PREDIV_DIV_5 |
AnnaBridge | 171:3a7713b1edbc | 1582 | * @arg @ref LL_RCC_PREDIV_DIV_6 |
AnnaBridge | 171:3a7713b1edbc | 1583 | * @arg @ref LL_RCC_PREDIV_DIV_7 |
AnnaBridge | 171:3a7713b1edbc | 1584 | * @arg @ref LL_RCC_PREDIV_DIV_8 |
AnnaBridge | 171:3a7713b1edbc | 1585 | * @arg @ref LL_RCC_PREDIV_DIV_9 |
AnnaBridge | 171:3a7713b1edbc | 1586 | * @arg @ref LL_RCC_PREDIV_DIV_10 |
AnnaBridge | 171:3a7713b1edbc | 1587 | * @arg @ref LL_RCC_PREDIV_DIV_11 |
AnnaBridge | 171:3a7713b1edbc | 1588 | * @arg @ref LL_RCC_PREDIV_DIV_12 |
AnnaBridge | 171:3a7713b1edbc | 1589 | * @arg @ref LL_RCC_PREDIV_DIV_13 |
AnnaBridge | 171:3a7713b1edbc | 1590 | * @arg @ref LL_RCC_PREDIV_DIV_14 |
AnnaBridge | 171:3a7713b1edbc | 1591 | * @arg @ref LL_RCC_PREDIV_DIV_15 |
AnnaBridge | 171:3a7713b1edbc | 1592 | * @arg @ref LL_RCC_PREDIV_DIV_16 |
AnnaBridge | 171:3a7713b1edbc | 1593 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1594 | */ |
AnnaBridge | 171:3a7713b1edbc | 1595 | __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul, uint32_t PLLDiv) |
AnnaBridge | 171:3a7713b1edbc | 1596 | { |
AnnaBridge | 171:3a7713b1edbc | 1597 | MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL, Source | PLLMul); |
AnnaBridge | 171:3a7713b1edbc | 1598 | MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, PLLDiv); |
AnnaBridge | 171:3a7713b1edbc | 1599 | } |
AnnaBridge | 171:3a7713b1edbc | 1600 | |
AnnaBridge | 171:3a7713b1edbc | 1601 | #else |
AnnaBridge | 171:3a7713b1edbc | 1602 | |
AnnaBridge | 171:3a7713b1edbc | 1603 | /** |
AnnaBridge | 171:3a7713b1edbc | 1604 | * @brief Configure PLL used for SYSCLK Domain |
AnnaBridge | 171:3a7713b1edbc | 1605 | * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n |
AnnaBridge | 171:3a7713b1edbc | 1606 | * CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n |
AnnaBridge | 171:3a7713b1edbc | 1607 | * CFGR2 PREDIV LL_RCC_PLL_ConfigDomain_SYS |
AnnaBridge | 171:3a7713b1edbc | 1608 | * @param Source This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1609 | * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 |
AnnaBridge | 171:3a7713b1edbc | 1610 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_1 |
AnnaBridge | 171:3a7713b1edbc | 1611 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_2 |
AnnaBridge | 171:3a7713b1edbc | 1612 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_3 |
AnnaBridge | 171:3a7713b1edbc | 1613 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_4 |
AnnaBridge | 171:3a7713b1edbc | 1614 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_5 |
AnnaBridge | 171:3a7713b1edbc | 1615 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_6 |
AnnaBridge | 171:3a7713b1edbc | 1616 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_7 |
AnnaBridge | 171:3a7713b1edbc | 1617 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_8 |
AnnaBridge | 171:3a7713b1edbc | 1618 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_9 |
AnnaBridge | 171:3a7713b1edbc | 1619 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_10 |
AnnaBridge | 171:3a7713b1edbc | 1620 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_11 |
AnnaBridge | 171:3a7713b1edbc | 1621 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_12 |
AnnaBridge | 171:3a7713b1edbc | 1622 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_13 |
AnnaBridge | 171:3a7713b1edbc | 1623 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_14 |
AnnaBridge | 171:3a7713b1edbc | 1624 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_15 |
AnnaBridge | 171:3a7713b1edbc | 1625 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_16 |
AnnaBridge | 171:3a7713b1edbc | 1626 | * @param PLLMul This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1627 | * @arg @ref LL_RCC_PLL_MUL_2 |
AnnaBridge | 171:3a7713b1edbc | 1628 | * @arg @ref LL_RCC_PLL_MUL_3 |
AnnaBridge | 171:3a7713b1edbc | 1629 | * @arg @ref LL_RCC_PLL_MUL_4 |
AnnaBridge | 171:3a7713b1edbc | 1630 | * @arg @ref LL_RCC_PLL_MUL_5 |
AnnaBridge | 171:3a7713b1edbc | 1631 | * @arg @ref LL_RCC_PLL_MUL_6 |
AnnaBridge | 171:3a7713b1edbc | 1632 | * @arg @ref LL_RCC_PLL_MUL_7 |
AnnaBridge | 171:3a7713b1edbc | 1633 | * @arg @ref LL_RCC_PLL_MUL_8 |
AnnaBridge | 171:3a7713b1edbc | 1634 | * @arg @ref LL_RCC_PLL_MUL_9 |
AnnaBridge | 171:3a7713b1edbc | 1635 | * @arg @ref LL_RCC_PLL_MUL_10 |
AnnaBridge | 171:3a7713b1edbc | 1636 | * @arg @ref LL_RCC_PLL_MUL_11 |
AnnaBridge | 171:3a7713b1edbc | 1637 | * @arg @ref LL_RCC_PLL_MUL_12 |
AnnaBridge | 171:3a7713b1edbc | 1638 | * @arg @ref LL_RCC_PLL_MUL_13 |
AnnaBridge | 171:3a7713b1edbc | 1639 | * @arg @ref LL_RCC_PLL_MUL_14 |
AnnaBridge | 171:3a7713b1edbc | 1640 | * @arg @ref LL_RCC_PLL_MUL_15 |
AnnaBridge | 171:3a7713b1edbc | 1641 | * @arg @ref LL_RCC_PLL_MUL_16 |
AnnaBridge | 171:3a7713b1edbc | 1642 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1643 | */ |
AnnaBridge | 171:3a7713b1edbc | 1644 | __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul) |
AnnaBridge | 171:3a7713b1edbc | 1645 | { |
AnnaBridge | 171:3a7713b1edbc | 1646 | MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL, (Source & RCC_CFGR_PLLSRC) | PLLMul); |
AnnaBridge | 171:3a7713b1edbc | 1647 | MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (Source & RCC_CFGR2_PREDIV)); |
AnnaBridge | 171:3a7713b1edbc | 1648 | } |
AnnaBridge | 171:3a7713b1edbc | 1649 | #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ |
AnnaBridge | 171:3a7713b1edbc | 1650 | |
AnnaBridge | 171:3a7713b1edbc | 1651 | /** |
AnnaBridge | 171:3a7713b1edbc | 1652 | * @brief Get the oscillator used as PLL clock source. |
AnnaBridge | 171:3a7713b1edbc | 1653 | * @rmtoll CFGR PLLSRC LL_RCC_PLL_GetMainSource |
AnnaBridge | 171:3a7713b1edbc | 1654 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1655 | * @arg @ref LL_RCC_PLLSOURCE_HSI (*) |
AnnaBridge | 171:3a7713b1edbc | 1656 | * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 (*) |
AnnaBridge | 171:3a7713b1edbc | 1657 | * @arg @ref LL_RCC_PLLSOURCE_HSE |
AnnaBridge | 171:3a7713b1edbc | 1658 | * @arg @ref LL_RCC_PLLSOURCE_HSI48 (*) |
AnnaBridge | 171:3a7713b1edbc | 1659 | * |
AnnaBridge | 171:3a7713b1edbc | 1660 | * (*) value not defined in all devices |
AnnaBridge | 171:3a7713b1edbc | 1661 | */ |
AnnaBridge | 171:3a7713b1edbc | 1662 | __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) |
AnnaBridge | 171:3a7713b1edbc | 1663 | { |
AnnaBridge | 171:3a7713b1edbc | 1664 | return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)); |
AnnaBridge | 171:3a7713b1edbc | 1665 | } |
AnnaBridge | 171:3a7713b1edbc | 1666 | |
AnnaBridge | 171:3a7713b1edbc | 1667 | /** |
AnnaBridge | 171:3a7713b1edbc | 1668 | * @brief Get PLL multiplication Factor |
AnnaBridge | 171:3a7713b1edbc | 1669 | * @rmtoll CFGR PLLMUL LL_RCC_PLL_GetMultiplicator |
AnnaBridge | 171:3a7713b1edbc | 1670 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1671 | * @arg @ref LL_RCC_PLL_MUL_2 |
AnnaBridge | 171:3a7713b1edbc | 1672 | * @arg @ref LL_RCC_PLL_MUL_3 |
AnnaBridge | 171:3a7713b1edbc | 1673 | * @arg @ref LL_RCC_PLL_MUL_4 |
AnnaBridge | 171:3a7713b1edbc | 1674 | * @arg @ref LL_RCC_PLL_MUL_5 |
AnnaBridge | 171:3a7713b1edbc | 1675 | * @arg @ref LL_RCC_PLL_MUL_6 |
AnnaBridge | 171:3a7713b1edbc | 1676 | * @arg @ref LL_RCC_PLL_MUL_7 |
AnnaBridge | 171:3a7713b1edbc | 1677 | * @arg @ref LL_RCC_PLL_MUL_8 |
AnnaBridge | 171:3a7713b1edbc | 1678 | * @arg @ref LL_RCC_PLL_MUL_9 |
AnnaBridge | 171:3a7713b1edbc | 1679 | * @arg @ref LL_RCC_PLL_MUL_10 |
AnnaBridge | 171:3a7713b1edbc | 1680 | * @arg @ref LL_RCC_PLL_MUL_11 |
AnnaBridge | 171:3a7713b1edbc | 1681 | * @arg @ref LL_RCC_PLL_MUL_12 |
AnnaBridge | 171:3a7713b1edbc | 1682 | * @arg @ref LL_RCC_PLL_MUL_13 |
AnnaBridge | 171:3a7713b1edbc | 1683 | * @arg @ref LL_RCC_PLL_MUL_14 |
AnnaBridge | 171:3a7713b1edbc | 1684 | * @arg @ref LL_RCC_PLL_MUL_15 |
AnnaBridge | 171:3a7713b1edbc | 1685 | * @arg @ref LL_RCC_PLL_MUL_16 |
AnnaBridge | 171:3a7713b1edbc | 1686 | */ |
AnnaBridge | 171:3a7713b1edbc | 1687 | __STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void) |
AnnaBridge | 171:3a7713b1edbc | 1688 | { |
AnnaBridge | 171:3a7713b1edbc | 1689 | return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMUL)); |
AnnaBridge | 171:3a7713b1edbc | 1690 | } |
AnnaBridge | 171:3a7713b1edbc | 1691 | |
AnnaBridge | 171:3a7713b1edbc | 1692 | /** |
AnnaBridge | 171:3a7713b1edbc | 1693 | * @brief Get PREDIV division factor for the main PLL |
AnnaBridge | 171:3a7713b1edbc | 1694 | * @note They can be written only when the PLL is disabled |
AnnaBridge | 171:3a7713b1edbc | 1695 | * @rmtoll CFGR2 PREDIV LL_RCC_PLL_GetPrediv |
AnnaBridge | 171:3a7713b1edbc | 1696 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1697 | * @arg @ref LL_RCC_PREDIV_DIV_1 |
AnnaBridge | 171:3a7713b1edbc | 1698 | * @arg @ref LL_RCC_PREDIV_DIV_2 |
AnnaBridge | 171:3a7713b1edbc | 1699 | * @arg @ref LL_RCC_PREDIV_DIV_3 |
AnnaBridge | 171:3a7713b1edbc | 1700 | * @arg @ref LL_RCC_PREDIV_DIV_4 |
AnnaBridge | 171:3a7713b1edbc | 1701 | * @arg @ref LL_RCC_PREDIV_DIV_5 |
AnnaBridge | 171:3a7713b1edbc | 1702 | * @arg @ref LL_RCC_PREDIV_DIV_6 |
AnnaBridge | 171:3a7713b1edbc | 1703 | * @arg @ref LL_RCC_PREDIV_DIV_7 |
AnnaBridge | 171:3a7713b1edbc | 1704 | * @arg @ref LL_RCC_PREDIV_DIV_8 |
AnnaBridge | 171:3a7713b1edbc | 1705 | * @arg @ref LL_RCC_PREDIV_DIV_9 |
AnnaBridge | 171:3a7713b1edbc | 1706 | * @arg @ref LL_RCC_PREDIV_DIV_10 |
AnnaBridge | 171:3a7713b1edbc | 1707 | * @arg @ref LL_RCC_PREDIV_DIV_11 |
AnnaBridge | 171:3a7713b1edbc | 1708 | * @arg @ref LL_RCC_PREDIV_DIV_12 |
AnnaBridge | 171:3a7713b1edbc | 1709 | * @arg @ref LL_RCC_PREDIV_DIV_13 |
AnnaBridge | 171:3a7713b1edbc | 1710 | * @arg @ref LL_RCC_PREDIV_DIV_14 |
AnnaBridge | 171:3a7713b1edbc | 1711 | * @arg @ref LL_RCC_PREDIV_DIV_15 |
AnnaBridge | 171:3a7713b1edbc | 1712 | * @arg @ref LL_RCC_PREDIV_DIV_16 |
AnnaBridge | 171:3a7713b1edbc | 1713 | */ |
AnnaBridge | 171:3a7713b1edbc | 1714 | __STATIC_INLINE uint32_t LL_RCC_PLL_GetPrediv(void) |
AnnaBridge | 171:3a7713b1edbc | 1715 | { |
AnnaBridge | 171:3a7713b1edbc | 1716 | return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV)); |
AnnaBridge | 171:3a7713b1edbc | 1717 | } |
AnnaBridge | 171:3a7713b1edbc | 1718 | |
AnnaBridge | 171:3a7713b1edbc | 1719 | /** |
AnnaBridge | 171:3a7713b1edbc | 1720 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1721 | */ |
AnnaBridge | 171:3a7713b1edbc | 1722 | |
AnnaBridge | 171:3a7713b1edbc | 1723 | /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management |
AnnaBridge | 171:3a7713b1edbc | 1724 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1725 | */ |
AnnaBridge | 171:3a7713b1edbc | 1726 | |
AnnaBridge | 171:3a7713b1edbc | 1727 | /** |
AnnaBridge | 171:3a7713b1edbc | 1728 | * @brief Clear LSI ready interrupt flag |
AnnaBridge | 171:3a7713b1edbc | 1729 | * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY |
AnnaBridge | 171:3a7713b1edbc | 1730 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1731 | */ |
AnnaBridge | 171:3a7713b1edbc | 1732 | __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) |
AnnaBridge | 171:3a7713b1edbc | 1733 | { |
AnnaBridge | 171:3a7713b1edbc | 1734 | SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC); |
AnnaBridge | 171:3a7713b1edbc | 1735 | } |
AnnaBridge | 171:3a7713b1edbc | 1736 | |
AnnaBridge | 171:3a7713b1edbc | 1737 | /** |
AnnaBridge | 171:3a7713b1edbc | 1738 | * @brief Clear LSE ready interrupt flag |
AnnaBridge | 171:3a7713b1edbc | 1739 | * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY |
AnnaBridge | 171:3a7713b1edbc | 1740 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1741 | */ |
AnnaBridge | 171:3a7713b1edbc | 1742 | __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) |
AnnaBridge | 171:3a7713b1edbc | 1743 | { |
AnnaBridge | 171:3a7713b1edbc | 1744 | SET_BIT(RCC->CIR, RCC_CIR_LSERDYC); |
AnnaBridge | 171:3a7713b1edbc | 1745 | } |
AnnaBridge | 171:3a7713b1edbc | 1746 | |
AnnaBridge | 171:3a7713b1edbc | 1747 | /** |
AnnaBridge | 171:3a7713b1edbc | 1748 | * @brief Clear HSI ready interrupt flag |
AnnaBridge | 171:3a7713b1edbc | 1749 | * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY |
AnnaBridge | 171:3a7713b1edbc | 1750 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1751 | */ |
AnnaBridge | 171:3a7713b1edbc | 1752 | __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) |
AnnaBridge | 171:3a7713b1edbc | 1753 | { |
AnnaBridge | 171:3a7713b1edbc | 1754 | SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC); |
AnnaBridge | 171:3a7713b1edbc | 1755 | } |
AnnaBridge | 171:3a7713b1edbc | 1756 | |
AnnaBridge | 171:3a7713b1edbc | 1757 | /** |
AnnaBridge | 171:3a7713b1edbc | 1758 | * @brief Clear HSE ready interrupt flag |
AnnaBridge | 171:3a7713b1edbc | 1759 | * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY |
AnnaBridge | 171:3a7713b1edbc | 1760 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1761 | */ |
AnnaBridge | 171:3a7713b1edbc | 1762 | __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) |
AnnaBridge | 171:3a7713b1edbc | 1763 | { |
AnnaBridge | 171:3a7713b1edbc | 1764 | SET_BIT(RCC->CIR, RCC_CIR_HSERDYC); |
AnnaBridge | 171:3a7713b1edbc | 1765 | } |
AnnaBridge | 171:3a7713b1edbc | 1766 | |
AnnaBridge | 171:3a7713b1edbc | 1767 | /** |
AnnaBridge | 171:3a7713b1edbc | 1768 | * @brief Clear PLL ready interrupt flag |
AnnaBridge | 171:3a7713b1edbc | 1769 | * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY |
AnnaBridge | 171:3a7713b1edbc | 1770 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1771 | */ |
AnnaBridge | 171:3a7713b1edbc | 1772 | __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void) |
AnnaBridge | 171:3a7713b1edbc | 1773 | { |
AnnaBridge | 171:3a7713b1edbc | 1774 | SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC); |
AnnaBridge | 171:3a7713b1edbc | 1775 | } |
AnnaBridge | 171:3a7713b1edbc | 1776 | |
AnnaBridge | 171:3a7713b1edbc | 1777 | /** |
AnnaBridge | 171:3a7713b1edbc | 1778 | * @brief Clear HSI14 ready interrupt flag |
AnnaBridge | 171:3a7713b1edbc | 1779 | * @rmtoll CIR HSI14RDYC LL_RCC_ClearFlag_HSI14RDY |
AnnaBridge | 171:3a7713b1edbc | 1780 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1781 | */ |
AnnaBridge | 171:3a7713b1edbc | 1782 | __STATIC_INLINE void LL_RCC_ClearFlag_HSI14RDY(void) |
AnnaBridge | 171:3a7713b1edbc | 1783 | { |
AnnaBridge | 171:3a7713b1edbc | 1784 | SET_BIT(RCC->CIR, RCC_CIR_HSI14RDYC); |
AnnaBridge | 171:3a7713b1edbc | 1785 | } |
AnnaBridge | 171:3a7713b1edbc | 1786 | |
AnnaBridge | 171:3a7713b1edbc | 1787 | #if defined(RCC_HSI48_SUPPORT) |
AnnaBridge | 171:3a7713b1edbc | 1788 | /** |
AnnaBridge | 171:3a7713b1edbc | 1789 | * @brief Clear HSI48 ready interrupt flag |
AnnaBridge | 171:3a7713b1edbc | 1790 | * @rmtoll CIR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY |
AnnaBridge | 171:3a7713b1edbc | 1791 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1792 | */ |
AnnaBridge | 171:3a7713b1edbc | 1793 | __STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void) |
AnnaBridge | 171:3a7713b1edbc | 1794 | { |
AnnaBridge | 171:3a7713b1edbc | 1795 | SET_BIT(RCC->CIR, RCC_CIR_HSI48RDYC); |
AnnaBridge | 171:3a7713b1edbc | 1796 | } |
AnnaBridge | 171:3a7713b1edbc | 1797 | #endif /* RCC_HSI48_SUPPORT */ |
AnnaBridge | 171:3a7713b1edbc | 1798 | |
AnnaBridge | 171:3a7713b1edbc | 1799 | /** |
AnnaBridge | 171:3a7713b1edbc | 1800 | * @brief Clear Clock security system interrupt flag |
AnnaBridge | 171:3a7713b1edbc | 1801 | * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS |
AnnaBridge | 171:3a7713b1edbc | 1802 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1803 | */ |
AnnaBridge | 171:3a7713b1edbc | 1804 | __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) |
AnnaBridge | 171:3a7713b1edbc | 1805 | { |
AnnaBridge | 171:3a7713b1edbc | 1806 | SET_BIT(RCC->CIR, RCC_CIR_CSSC); |
AnnaBridge | 171:3a7713b1edbc | 1807 | } |
AnnaBridge | 171:3a7713b1edbc | 1808 | |
AnnaBridge | 171:3a7713b1edbc | 1809 | /** |
AnnaBridge | 171:3a7713b1edbc | 1810 | * @brief Check if LSI ready interrupt occurred or not |
AnnaBridge | 171:3a7713b1edbc | 1811 | * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY |
AnnaBridge | 171:3a7713b1edbc | 1812 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1813 | */ |
AnnaBridge | 171:3a7713b1edbc | 1814 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) |
AnnaBridge | 171:3a7713b1edbc | 1815 | { |
AnnaBridge | 171:3a7713b1edbc | 1816 | return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF)); |
AnnaBridge | 171:3a7713b1edbc | 1817 | } |
AnnaBridge | 171:3a7713b1edbc | 1818 | |
AnnaBridge | 171:3a7713b1edbc | 1819 | /** |
AnnaBridge | 171:3a7713b1edbc | 1820 | * @brief Check if LSE ready interrupt occurred or not |
AnnaBridge | 171:3a7713b1edbc | 1821 | * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY |
AnnaBridge | 171:3a7713b1edbc | 1822 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1823 | */ |
AnnaBridge | 171:3a7713b1edbc | 1824 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) |
AnnaBridge | 171:3a7713b1edbc | 1825 | { |
AnnaBridge | 171:3a7713b1edbc | 1826 | return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF)); |
AnnaBridge | 171:3a7713b1edbc | 1827 | } |
AnnaBridge | 171:3a7713b1edbc | 1828 | |
AnnaBridge | 171:3a7713b1edbc | 1829 | /** |
AnnaBridge | 171:3a7713b1edbc | 1830 | * @brief Check if HSI ready interrupt occurred or not |
AnnaBridge | 171:3a7713b1edbc | 1831 | * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY |
AnnaBridge | 171:3a7713b1edbc | 1832 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1833 | */ |
AnnaBridge | 171:3a7713b1edbc | 1834 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) |
AnnaBridge | 171:3a7713b1edbc | 1835 | { |
AnnaBridge | 171:3a7713b1edbc | 1836 | return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF)); |
AnnaBridge | 171:3a7713b1edbc | 1837 | } |
AnnaBridge | 171:3a7713b1edbc | 1838 | |
AnnaBridge | 171:3a7713b1edbc | 1839 | /** |
AnnaBridge | 171:3a7713b1edbc | 1840 | * @brief Check if HSE ready interrupt occurred or not |
AnnaBridge | 171:3a7713b1edbc | 1841 | * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY |
AnnaBridge | 171:3a7713b1edbc | 1842 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1843 | */ |
AnnaBridge | 171:3a7713b1edbc | 1844 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) |
AnnaBridge | 171:3a7713b1edbc | 1845 | { |
AnnaBridge | 171:3a7713b1edbc | 1846 | return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF)); |
AnnaBridge | 171:3a7713b1edbc | 1847 | } |
AnnaBridge | 171:3a7713b1edbc | 1848 | |
AnnaBridge | 171:3a7713b1edbc | 1849 | /** |
AnnaBridge | 171:3a7713b1edbc | 1850 | * @brief Check if PLL ready interrupt occurred or not |
AnnaBridge | 171:3a7713b1edbc | 1851 | * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY |
AnnaBridge | 171:3a7713b1edbc | 1852 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1853 | */ |
AnnaBridge | 171:3a7713b1edbc | 1854 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void) |
AnnaBridge | 171:3a7713b1edbc | 1855 | { |
AnnaBridge | 171:3a7713b1edbc | 1856 | return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF)); |
AnnaBridge | 171:3a7713b1edbc | 1857 | } |
AnnaBridge | 171:3a7713b1edbc | 1858 | |
AnnaBridge | 171:3a7713b1edbc | 1859 | /** |
AnnaBridge | 171:3a7713b1edbc | 1860 | * @brief Check if HSI14 ready interrupt occurred or not |
AnnaBridge | 171:3a7713b1edbc | 1861 | * @rmtoll CIR HSI14RDYF LL_RCC_IsActiveFlag_HSI14RDY |
AnnaBridge | 171:3a7713b1edbc | 1862 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1863 | */ |
AnnaBridge | 171:3a7713b1edbc | 1864 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI14RDY(void) |
AnnaBridge | 171:3a7713b1edbc | 1865 | { |
AnnaBridge | 171:3a7713b1edbc | 1866 | return (READ_BIT(RCC->CIR, RCC_CIR_HSI14RDYF) == (RCC_CIR_HSI14RDYF)); |
AnnaBridge | 171:3a7713b1edbc | 1867 | } |
AnnaBridge | 171:3a7713b1edbc | 1868 | |
AnnaBridge | 171:3a7713b1edbc | 1869 | #if defined(RCC_HSI48_SUPPORT) |
AnnaBridge | 171:3a7713b1edbc | 1870 | /** |
AnnaBridge | 171:3a7713b1edbc | 1871 | * @brief Check if HSI48 ready interrupt occurred or not |
AnnaBridge | 171:3a7713b1edbc | 1872 | * @rmtoll CIR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY |
AnnaBridge | 171:3a7713b1edbc | 1873 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1874 | */ |
AnnaBridge | 171:3a7713b1edbc | 1875 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void) |
AnnaBridge | 171:3a7713b1edbc | 1876 | { |
AnnaBridge | 171:3a7713b1edbc | 1877 | return (READ_BIT(RCC->CIR, RCC_CIR_HSI48RDYF) == (RCC_CIR_HSI48RDYF)); |
AnnaBridge | 171:3a7713b1edbc | 1878 | } |
AnnaBridge | 171:3a7713b1edbc | 1879 | #endif /* RCC_HSI48_SUPPORT */ |
AnnaBridge | 171:3a7713b1edbc | 1880 | |
AnnaBridge | 171:3a7713b1edbc | 1881 | /** |
AnnaBridge | 171:3a7713b1edbc | 1882 | * @brief Check if Clock security system interrupt occurred or not |
AnnaBridge | 171:3a7713b1edbc | 1883 | * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS |
AnnaBridge | 171:3a7713b1edbc | 1884 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1885 | */ |
AnnaBridge | 171:3a7713b1edbc | 1886 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) |
AnnaBridge | 171:3a7713b1edbc | 1887 | { |
AnnaBridge | 171:3a7713b1edbc | 1888 | return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF)); |
AnnaBridge | 171:3a7713b1edbc | 1889 | } |
AnnaBridge | 171:3a7713b1edbc | 1890 | |
AnnaBridge | 171:3a7713b1edbc | 1891 | /** |
AnnaBridge | 171:3a7713b1edbc | 1892 | * @brief Check if RCC flag Independent Watchdog reset is set or not. |
AnnaBridge | 171:3a7713b1edbc | 1893 | * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST |
AnnaBridge | 171:3a7713b1edbc | 1894 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1895 | */ |
AnnaBridge | 171:3a7713b1edbc | 1896 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) |
AnnaBridge | 171:3a7713b1edbc | 1897 | { |
AnnaBridge | 171:3a7713b1edbc | 1898 | return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)); |
AnnaBridge | 171:3a7713b1edbc | 1899 | } |
AnnaBridge | 171:3a7713b1edbc | 1900 | |
AnnaBridge | 171:3a7713b1edbc | 1901 | /** |
AnnaBridge | 171:3a7713b1edbc | 1902 | * @brief Check if RCC flag Low Power reset is set or not. |
AnnaBridge | 171:3a7713b1edbc | 1903 | * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST |
AnnaBridge | 171:3a7713b1edbc | 1904 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1905 | */ |
AnnaBridge | 171:3a7713b1edbc | 1906 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) |
AnnaBridge | 171:3a7713b1edbc | 1907 | { |
AnnaBridge | 171:3a7713b1edbc | 1908 | return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)); |
AnnaBridge | 171:3a7713b1edbc | 1909 | } |
AnnaBridge | 171:3a7713b1edbc | 1910 | |
AnnaBridge | 171:3a7713b1edbc | 1911 | /** |
AnnaBridge | 171:3a7713b1edbc | 1912 | * @brief Check if RCC flag is set or not. |
AnnaBridge | 171:3a7713b1edbc | 1913 | * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST |
AnnaBridge | 171:3a7713b1edbc | 1914 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1915 | */ |
AnnaBridge | 171:3a7713b1edbc | 1916 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void) |
AnnaBridge | 171:3a7713b1edbc | 1917 | { |
AnnaBridge | 171:3a7713b1edbc | 1918 | return (READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF)); |
AnnaBridge | 171:3a7713b1edbc | 1919 | } |
AnnaBridge | 171:3a7713b1edbc | 1920 | |
AnnaBridge | 171:3a7713b1edbc | 1921 | /** |
AnnaBridge | 171:3a7713b1edbc | 1922 | * @brief Check if RCC flag Pin reset is set or not. |
AnnaBridge | 171:3a7713b1edbc | 1923 | * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST |
AnnaBridge | 171:3a7713b1edbc | 1924 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1925 | */ |
AnnaBridge | 171:3a7713b1edbc | 1926 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) |
AnnaBridge | 171:3a7713b1edbc | 1927 | { |
AnnaBridge | 171:3a7713b1edbc | 1928 | return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)); |
AnnaBridge | 171:3a7713b1edbc | 1929 | } |
AnnaBridge | 171:3a7713b1edbc | 1930 | |
AnnaBridge | 171:3a7713b1edbc | 1931 | /** |
AnnaBridge | 171:3a7713b1edbc | 1932 | * @brief Check if RCC flag POR/PDR reset is set or not. |
AnnaBridge | 171:3a7713b1edbc | 1933 | * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST |
AnnaBridge | 171:3a7713b1edbc | 1934 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1935 | */ |
AnnaBridge | 171:3a7713b1edbc | 1936 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void) |
AnnaBridge | 171:3a7713b1edbc | 1937 | { |
AnnaBridge | 171:3a7713b1edbc | 1938 | return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF)); |
AnnaBridge | 171:3a7713b1edbc | 1939 | } |
AnnaBridge | 171:3a7713b1edbc | 1940 | |
AnnaBridge | 171:3a7713b1edbc | 1941 | /** |
AnnaBridge | 171:3a7713b1edbc | 1942 | * @brief Check if RCC flag Software reset is set or not. |
AnnaBridge | 171:3a7713b1edbc | 1943 | * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST |
AnnaBridge | 171:3a7713b1edbc | 1944 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1945 | */ |
AnnaBridge | 171:3a7713b1edbc | 1946 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) |
AnnaBridge | 171:3a7713b1edbc | 1947 | { |
AnnaBridge | 171:3a7713b1edbc | 1948 | return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)); |
AnnaBridge | 171:3a7713b1edbc | 1949 | } |
AnnaBridge | 171:3a7713b1edbc | 1950 | |
AnnaBridge | 171:3a7713b1edbc | 1951 | /** |
AnnaBridge | 171:3a7713b1edbc | 1952 | * @brief Check if RCC flag Window Watchdog reset is set or not. |
AnnaBridge | 171:3a7713b1edbc | 1953 | * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST |
AnnaBridge | 171:3a7713b1edbc | 1954 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1955 | */ |
AnnaBridge | 171:3a7713b1edbc | 1956 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) |
AnnaBridge | 171:3a7713b1edbc | 1957 | { |
AnnaBridge | 171:3a7713b1edbc | 1958 | return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)); |
AnnaBridge | 171:3a7713b1edbc | 1959 | } |
AnnaBridge | 171:3a7713b1edbc | 1960 | |
AnnaBridge | 171:3a7713b1edbc | 1961 | #if defined(RCC_CSR_V18PWRRSTF) |
AnnaBridge | 171:3a7713b1edbc | 1962 | /** |
AnnaBridge | 171:3a7713b1edbc | 1963 | * @brief Check if RCC Reset flag of the 1.8 V domain is set or not. |
AnnaBridge | 171:3a7713b1edbc | 1964 | * @rmtoll CSR V18PWRRSTF LL_RCC_IsActiveFlag_V18PWRRST |
AnnaBridge | 171:3a7713b1edbc | 1965 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1966 | */ |
AnnaBridge | 171:3a7713b1edbc | 1967 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_V18PWRRST(void) |
AnnaBridge | 171:3a7713b1edbc | 1968 | { |
AnnaBridge | 171:3a7713b1edbc | 1969 | return (READ_BIT(RCC->CSR, RCC_CSR_V18PWRRSTF) == (RCC_CSR_V18PWRRSTF)); |
AnnaBridge | 171:3a7713b1edbc | 1970 | } |
AnnaBridge | 171:3a7713b1edbc | 1971 | #endif /* RCC_CSR_V18PWRRSTF */ |
AnnaBridge | 171:3a7713b1edbc | 1972 | |
AnnaBridge | 171:3a7713b1edbc | 1973 | /** |
AnnaBridge | 171:3a7713b1edbc | 1974 | * @brief Set RMVF bit to clear the reset flags. |
AnnaBridge | 171:3a7713b1edbc | 1975 | * @rmtoll CSR RMVF LL_RCC_ClearResetFlags |
AnnaBridge | 171:3a7713b1edbc | 1976 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1977 | */ |
AnnaBridge | 171:3a7713b1edbc | 1978 | __STATIC_INLINE void LL_RCC_ClearResetFlags(void) |
AnnaBridge | 171:3a7713b1edbc | 1979 | { |
AnnaBridge | 171:3a7713b1edbc | 1980 | SET_BIT(RCC->CSR, RCC_CSR_RMVF); |
AnnaBridge | 171:3a7713b1edbc | 1981 | } |
AnnaBridge | 171:3a7713b1edbc | 1982 | |
AnnaBridge | 171:3a7713b1edbc | 1983 | /** |
AnnaBridge | 171:3a7713b1edbc | 1984 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1985 | */ |
AnnaBridge | 171:3a7713b1edbc | 1986 | |
AnnaBridge | 171:3a7713b1edbc | 1987 | /** @defgroup RCC_LL_EF_IT_Management IT Management |
AnnaBridge | 171:3a7713b1edbc | 1988 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1989 | */ |
AnnaBridge | 171:3a7713b1edbc | 1990 | |
AnnaBridge | 171:3a7713b1edbc | 1991 | /** |
AnnaBridge | 171:3a7713b1edbc | 1992 | * @brief Enable LSI ready interrupt |
AnnaBridge | 171:3a7713b1edbc | 1993 | * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY |
AnnaBridge | 171:3a7713b1edbc | 1994 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1995 | */ |
AnnaBridge | 171:3a7713b1edbc | 1996 | __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) |
AnnaBridge | 171:3a7713b1edbc | 1997 | { |
AnnaBridge | 171:3a7713b1edbc | 1998 | SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); |
AnnaBridge | 171:3a7713b1edbc | 1999 | } |
AnnaBridge | 171:3a7713b1edbc | 2000 | |
AnnaBridge | 171:3a7713b1edbc | 2001 | /** |
AnnaBridge | 171:3a7713b1edbc | 2002 | * @brief Enable LSE ready interrupt |
AnnaBridge | 171:3a7713b1edbc | 2003 | * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY |
AnnaBridge | 171:3a7713b1edbc | 2004 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2005 | */ |
AnnaBridge | 171:3a7713b1edbc | 2006 | __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) |
AnnaBridge | 171:3a7713b1edbc | 2007 | { |
AnnaBridge | 171:3a7713b1edbc | 2008 | SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE); |
AnnaBridge | 171:3a7713b1edbc | 2009 | } |
AnnaBridge | 171:3a7713b1edbc | 2010 | |
AnnaBridge | 171:3a7713b1edbc | 2011 | /** |
AnnaBridge | 171:3a7713b1edbc | 2012 | * @brief Enable HSI ready interrupt |
AnnaBridge | 171:3a7713b1edbc | 2013 | * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY |
AnnaBridge | 171:3a7713b1edbc | 2014 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2015 | */ |
AnnaBridge | 171:3a7713b1edbc | 2016 | __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) |
AnnaBridge | 171:3a7713b1edbc | 2017 | { |
AnnaBridge | 171:3a7713b1edbc | 2018 | SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); |
AnnaBridge | 171:3a7713b1edbc | 2019 | } |
AnnaBridge | 171:3a7713b1edbc | 2020 | |
AnnaBridge | 171:3a7713b1edbc | 2021 | /** |
AnnaBridge | 171:3a7713b1edbc | 2022 | * @brief Enable HSE ready interrupt |
AnnaBridge | 171:3a7713b1edbc | 2023 | * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY |
AnnaBridge | 171:3a7713b1edbc | 2024 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2025 | */ |
AnnaBridge | 171:3a7713b1edbc | 2026 | __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) |
AnnaBridge | 171:3a7713b1edbc | 2027 | { |
AnnaBridge | 171:3a7713b1edbc | 2028 | SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE); |
AnnaBridge | 171:3a7713b1edbc | 2029 | } |
AnnaBridge | 171:3a7713b1edbc | 2030 | |
AnnaBridge | 171:3a7713b1edbc | 2031 | /** |
AnnaBridge | 171:3a7713b1edbc | 2032 | * @brief Enable PLL ready interrupt |
AnnaBridge | 171:3a7713b1edbc | 2033 | * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY |
AnnaBridge | 171:3a7713b1edbc | 2034 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2035 | */ |
AnnaBridge | 171:3a7713b1edbc | 2036 | __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void) |
AnnaBridge | 171:3a7713b1edbc | 2037 | { |
AnnaBridge | 171:3a7713b1edbc | 2038 | SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); |
AnnaBridge | 171:3a7713b1edbc | 2039 | } |
AnnaBridge | 171:3a7713b1edbc | 2040 | |
AnnaBridge | 171:3a7713b1edbc | 2041 | /** |
AnnaBridge | 171:3a7713b1edbc | 2042 | * @brief Enable HSI14 ready interrupt |
AnnaBridge | 171:3a7713b1edbc | 2043 | * @rmtoll CIR HSI14RDYIE LL_RCC_EnableIT_HSI14RDY |
AnnaBridge | 171:3a7713b1edbc | 2044 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2045 | */ |
AnnaBridge | 171:3a7713b1edbc | 2046 | __STATIC_INLINE void LL_RCC_EnableIT_HSI14RDY(void) |
AnnaBridge | 171:3a7713b1edbc | 2047 | { |
AnnaBridge | 171:3a7713b1edbc | 2048 | SET_BIT(RCC->CIR, RCC_CIR_HSI14RDYIE); |
AnnaBridge | 171:3a7713b1edbc | 2049 | } |
AnnaBridge | 171:3a7713b1edbc | 2050 | |
AnnaBridge | 171:3a7713b1edbc | 2051 | #if defined(RCC_HSI48_SUPPORT) |
AnnaBridge | 171:3a7713b1edbc | 2052 | /** |
AnnaBridge | 171:3a7713b1edbc | 2053 | * @brief Enable HSI48 ready interrupt |
AnnaBridge | 171:3a7713b1edbc | 2054 | * @rmtoll CIR HSI48RDYIE LL_RCC_EnableIT_HSI48RDY |
AnnaBridge | 171:3a7713b1edbc | 2055 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2056 | */ |
AnnaBridge | 171:3a7713b1edbc | 2057 | __STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void) |
AnnaBridge | 171:3a7713b1edbc | 2058 | { |
AnnaBridge | 171:3a7713b1edbc | 2059 | SET_BIT(RCC->CIR, RCC_CIR_HSI48RDYIE); |
AnnaBridge | 171:3a7713b1edbc | 2060 | } |
AnnaBridge | 171:3a7713b1edbc | 2061 | #endif /* RCC_HSI48_SUPPORT */ |
AnnaBridge | 171:3a7713b1edbc | 2062 | |
AnnaBridge | 171:3a7713b1edbc | 2063 | /** |
AnnaBridge | 171:3a7713b1edbc | 2064 | * @brief Disable LSI ready interrupt |
AnnaBridge | 171:3a7713b1edbc | 2065 | * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY |
AnnaBridge | 171:3a7713b1edbc | 2066 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2067 | */ |
AnnaBridge | 171:3a7713b1edbc | 2068 | __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) |
AnnaBridge | 171:3a7713b1edbc | 2069 | { |
AnnaBridge | 171:3a7713b1edbc | 2070 | CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); |
AnnaBridge | 171:3a7713b1edbc | 2071 | } |
AnnaBridge | 171:3a7713b1edbc | 2072 | |
AnnaBridge | 171:3a7713b1edbc | 2073 | /** |
AnnaBridge | 171:3a7713b1edbc | 2074 | * @brief Disable LSE ready interrupt |
AnnaBridge | 171:3a7713b1edbc | 2075 | * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY |
AnnaBridge | 171:3a7713b1edbc | 2076 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2077 | */ |
AnnaBridge | 171:3a7713b1edbc | 2078 | __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) |
AnnaBridge | 171:3a7713b1edbc | 2079 | { |
AnnaBridge | 171:3a7713b1edbc | 2080 | CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE); |
AnnaBridge | 171:3a7713b1edbc | 2081 | } |
AnnaBridge | 171:3a7713b1edbc | 2082 | |
AnnaBridge | 171:3a7713b1edbc | 2083 | /** |
AnnaBridge | 171:3a7713b1edbc | 2084 | * @brief Disable HSI ready interrupt |
AnnaBridge | 171:3a7713b1edbc | 2085 | * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY |
AnnaBridge | 171:3a7713b1edbc | 2086 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2087 | */ |
AnnaBridge | 171:3a7713b1edbc | 2088 | __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) |
AnnaBridge | 171:3a7713b1edbc | 2089 | { |
AnnaBridge | 171:3a7713b1edbc | 2090 | CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); |
AnnaBridge | 171:3a7713b1edbc | 2091 | } |
AnnaBridge | 171:3a7713b1edbc | 2092 | |
AnnaBridge | 171:3a7713b1edbc | 2093 | /** |
AnnaBridge | 171:3a7713b1edbc | 2094 | * @brief Disable HSE ready interrupt |
AnnaBridge | 171:3a7713b1edbc | 2095 | * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY |
AnnaBridge | 171:3a7713b1edbc | 2096 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2097 | */ |
AnnaBridge | 171:3a7713b1edbc | 2098 | __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) |
AnnaBridge | 171:3a7713b1edbc | 2099 | { |
AnnaBridge | 171:3a7713b1edbc | 2100 | CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE); |
AnnaBridge | 171:3a7713b1edbc | 2101 | } |
AnnaBridge | 171:3a7713b1edbc | 2102 | |
AnnaBridge | 171:3a7713b1edbc | 2103 | /** |
AnnaBridge | 171:3a7713b1edbc | 2104 | * @brief Disable PLL ready interrupt |
AnnaBridge | 171:3a7713b1edbc | 2105 | * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY |
AnnaBridge | 171:3a7713b1edbc | 2106 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2107 | */ |
AnnaBridge | 171:3a7713b1edbc | 2108 | __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void) |
AnnaBridge | 171:3a7713b1edbc | 2109 | { |
AnnaBridge | 171:3a7713b1edbc | 2110 | CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); |
AnnaBridge | 171:3a7713b1edbc | 2111 | } |
AnnaBridge | 171:3a7713b1edbc | 2112 | |
AnnaBridge | 171:3a7713b1edbc | 2113 | /** |
AnnaBridge | 171:3a7713b1edbc | 2114 | * @brief Disable HSI14 ready interrupt |
AnnaBridge | 171:3a7713b1edbc | 2115 | * @rmtoll CIR HSI14RDYIE LL_RCC_DisableIT_HSI14RDY |
AnnaBridge | 171:3a7713b1edbc | 2116 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2117 | */ |
AnnaBridge | 171:3a7713b1edbc | 2118 | __STATIC_INLINE void LL_RCC_DisableIT_HSI14RDY(void) |
AnnaBridge | 171:3a7713b1edbc | 2119 | { |
AnnaBridge | 171:3a7713b1edbc | 2120 | CLEAR_BIT(RCC->CIR, RCC_CIR_HSI14RDYIE); |
AnnaBridge | 171:3a7713b1edbc | 2121 | } |
AnnaBridge | 171:3a7713b1edbc | 2122 | |
AnnaBridge | 171:3a7713b1edbc | 2123 | #if defined(RCC_HSI48_SUPPORT) |
AnnaBridge | 171:3a7713b1edbc | 2124 | /** |
AnnaBridge | 171:3a7713b1edbc | 2125 | * @brief Disable HSI48 ready interrupt |
AnnaBridge | 171:3a7713b1edbc | 2126 | * @rmtoll CIR HSI48RDYIE LL_RCC_DisableIT_HSI48RDY |
AnnaBridge | 171:3a7713b1edbc | 2127 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2128 | */ |
AnnaBridge | 171:3a7713b1edbc | 2129 | __STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void) |
AnnaBridge | 171:3a7713b1edbc | 2130 | { |
AnnaBridge | 171:3a7713b1edbc | 2131 | CLEAR_BIT(RCC->CIR, RCC_CIR_HSI48RDYIE); |
AnnaBridge | 171:3a7713b1edbc | 2132 | } |
AnnaBridge | 171:3a7713b1edbc | 2133 | #endif /* RCC_HSI48_SUPPORT */ |
AnnaBridge | 171:3a7713b1edbc | 2134 | |
AnnaBridge | 171:3a7713b1edbc | 2135 | /** |
AnnaBridge | 171:3a7713b1edbc | 2136 | * @brief Checks if LSI ready interrupt source is enabled or disabled. |
AnnaBridge | 171:3a7713b1edbc | 2137 | * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY |
AnnaBridge | 171:3a7713b1edbc | 2138 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 2139 | */ |
AnnaBridge | 171:3a7713b1edbc | 2140 | __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) |
AnnaBridge | 171:3a7713b1edbc | 2141 | { |
AnnaBridge | 171:3a7713b1edbc | 2142 | return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE)); |
AnnaBridge | 171:3a7713b1edbc | 2143 | } |
AnnaBridge | 171:3a7713b1edbc | 2144 | |
AnnaBridge | 171:3a7713b1edbc | 2145 | /** |
AnnaBridge | 171:3a7713b1edbc | 2146 | * @brief Checks if LSE ready interrupt source is enabled or disabled. |
AnnaBridge | 171:3a7713b1edbc | 2147 | * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY |
AnnaBridge | 171:3a7713b1edbc | 2148 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 2149 | */ |
AnnaBridge | 171:3a7713b1edbc | 2150 | __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) |
AnnaBridge | 171:3a7713b1edbc | 2151 | { |
AnnaBridge | 171:3a7713b1edbc | 2152 | return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE)); |
AnnaBridge | 171:3a7713b1edbc | 2153 | } |
AnnaBridge | 171:3a7713b1edbc | 2154 | |
AnnaBridge | 171:3a7713b1edbc | 2155 | /** |
AnnaBridge | 171:3a7713b1edbc | 2156 | * @brief Checks if HSI ready interrupt source is enabled or disabled. |
AnnaBridge | 171:3a7713b1edbc | 2157 | * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY |
AnnaBridge | 171:3a7713b1edbc | 2158 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 2159 | */ |
AnnaBridge | 171:3a7713b1edbc | 2160 | __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) |
AnnaBridge | 171:3a7713b1edbc | 2161 | { |
AnnaBridge | 171:3a7713b1edbc | 2162 | return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE)); |
AnnaBridge | 171:3a7713b1edbc | 2163 | } |
AnnaBridge | 171:3a7713b1edbc | 2164 | |
AnnaBridge | 171:3a7713b1edbc | 2165 | /** |
AnnaBridge | 171:3a7713b1edbc | 2166 | * @brief Checks if HSE ready interrupt source is enabled or disabled. |
AnnaBridge | 171:3a7713b1edbc | 2167 | * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY |
AnnaBridge | 171:3a7713b1edbc | 2168 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 2169 | */ |
AnnaBridge | 171:3a7713b1edbc | 2170 | __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) |
AnnaBridge | 171:3a7713b1edbc | 2171 | { |
AnnaBridge | 171:3a7713b1edbc | 2172 | return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE)); |
AnnaBridge | 171:3a7713b1edbc | 2173 | } |
AnnaBridge | 171:3a7713b1edbc | 2174 | |
AnnaBridge | 171:3a7713b1edbc | 2175 | /** |
AnnaBridge | 171:3a7713b1edbc | 2176 | * @brief Checks if PLL ready interrupt source is enabled or disabled. |
AnnaBridge | 171:3a7713b1edbc | 2177 | * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY |
AnnaBridge | 171:3a7713b1edbc | 2178 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 2179 | */ |
AnnaBridge | 171:3a7713b1edbc | 2180 | __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void) |
AnnaBridge | 171:3a7713b1edbc | 2181 | { |
AnnaBridge | 171:3a7713b1edbc | 2182 | return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE)); |
AnnaBridge | 171:3a7713b1edbc | 2183 | } |
AnnaBridge | 171:3a7713b1edbc | 2184 | |
AnnaBridge | 171:3a7713b1edbc | 2185 | /** |
AnnaBridge | 171:3a7713b1edbc | 2186 | * @brief Checks if HSI14 ready interrupt source is enabled or disabled. |
AnnaBridge | 171:3a7713b1edbc | 2187 | * @rmtoll CIR HSI14RDYIE LL_RCC_IsEnabledIT_HSI14RDY |
AnnaBridge | 171:3a7713b1edbc | 2188 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 2189 | */ |
AnnaBridge | 171:3a7713b1edbc | 2190 | __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI14RDY(void) |
AnnaBridge | 171:3a7713b1edbc | 2191 | { |
AnnaBridge | 171:3a7713b1edbc | 2192 | return (READ_BIT(RCC->CIR, RCC_CIR_HSI14RDYIE) == (RCC_CIR_HSI14RDYIE)); |
AnnaBridge | 171:3a7713b1edbc | 2193 | } |
AnnaBridge | 171:3a7713b1edbc | 2194 | |
AnnaBridge | 171:3a7713b1edbc | 2195 | #if defined(RCC_HSI48_SUPPORT) |
AnnaBridge | 171:3a7713b1edbc | 2196 | /** |
AnnaBridge | 171:3a7713b1edbc | 2197 | * @brief Checks if HSI48 ready interrupt source is enabled or disabled. |
AnnaBridge | 171:3a7713b1edbc | 2198 | * @rmtoll CIR HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY |
AnnaBridge | 171:3a7713b1edbc | 2199 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 2200 | */ |
AnnaBridge | 171:3a7713b1edbc | 2201 | __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void) |
AnnaBridge | 171:3a7713b1edbc | 2202 | { |
AnnaBridge | 171:3a7713b1edbc | 2203 | return (READ_BIT(RCC->CIR, RCC_CIR_HSI48RDYIE) == (RCC_CIR_HSI48RDYIE)); |
AnnaBridge | 171:3a7713b1edbc | 2204 | } |
AnnaBridge | 171:3a7713b1edbc | 2205 | #endif /* RCC_HSI48_SUPPORT */ |
AnnaBridge | 171:3a7713b1edbc | 2206 | |
AnnaBridge | 171:3a7713b1edbc | 2207 | /** |
AnnaBridge | 171:3a7713b1edbc | 2208 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2209 | */ |
AnnaBridge | 171:3a7713b1edbc | 2210 | |
AnnaBridge | 171:3a7713b1edbc | 2211 | #if defined(USE_FULL_LL_DRIVER) |
AnnaBridge | 171:3a7713b1edbc | 2212 | /** @defgroup RCC_LL_EF_Init De-initialization function |
AnnaBridge | 171:3a7713b1edbc | 2213 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 2214 | */ |
AnnaBridge | 171:3a7713b1edbc | 2215 | ErrorStatus LL_RCC_DeInit(void); |
AnnaBridge | 171:3a7713b1edbc | 2216 | /** |
AnnaBridge | 171:3a7713b1edbc | 2217 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2218 | */ |
AnnaBridge | 171:3a7713b1edbc | 2219 | |
AnnaBridge | 171:3a7713b1edbc | 2220 | /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions |
AnnaBridge | 171:3a7713b1edbc | 2221 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 2222 | */ |
AnnaBridge | 171:3a7713b1edbc | 2223 | void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); |
AnnaBridge | 171:3a7713b1edbc | 2224 | uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource); |
AnnaBridge | 171:3a7713b1edbc | 2225 | uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource); |
AnnaBridge | 171:3a7713b1edbc | 2226 | #if defined(USB_OTG_FS) || defined(USB) |
AnnaBridge | 171:3a7713b1edbc | 2227 | uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); |
AnnaBridge | 171:3a7713b1edbc | 2228 | #endif /* USB_OTG_FS || USB */ |
AnnaBridge | 171:3a7713b1edbc | 2229 | #if defined(CEC) |
AnnaBridge | 171:3a7713b1edbc | 2230 | uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource); |
AnnaBridge | 171:3a7713b1edbc | 2231 | #endif /* CEC */ |
AnnaBridge | 171:3a7713b1edbc | 2232 | /** |
AnnaBridge | 171:3a7713b1edbc | 2233 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2234 | */ |
AnnaBridge | 171:3a7713b1edbc | 2235 | #endif /* USE_FULL_LL_DRIVER */ |
AnnaBridge | 171:3a7713b1edbc | 2236 | |
AnnaBridge | 171:3a7713b1edbc | 2237 | /** |
AnnaBridge | 171:3a7713b1edbc | 2238 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2239 | */ |
AnnaBridge | 171:3a7713b1edbc | 2240 | |
AnnaBridge | 171:3a7713b1edbc | 2241 | /** |
AnnaBridge | 171:3a7713b1edbc | 2242 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2243 | */ |
AnnaBridge | 171:3a7713b1edbc | 2244 | |
AnnaBridge | 171:3a7713b1edbc | 2245 | #endif /* RCC */ |
AnnaBridge | 171:3a7713b1edbc | 2246 | |
AnnaBridge | 171:3a7713b1edbc | 2247 | /** |
AnnaBridge | 171:3a7713b1edbc | 2248 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2249 | */ |
AnnaBridge | 171:3a7713b1edbc | 2250 | |
AnnaBridge | 171:3a7713b1edbc | 2251 | #ifdef __cplusplus |
AnnaBridge | 171:3a7713b1edbc | 2252 | } |
AnnaBridge | 171:3a7713b1edbc | 2253 | #endif |
AnnaBridge | 171:3a7713b1edbc | 2254 | |
AnnaBridge | 171:3a7713b1edbc | 2255 | #endif /* __STM32F0xx_LL_RCC_H */ |
AnnaBridge | 171:3a7713b1edbc | 2256 | |
AnnaBridge | 171:3a7713b1edbc | 2257 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |