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TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_STD/stm32f0xx_hal_dma_ex.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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AnnaBridge | 171:3a7713b1edbc | 1 | /** |
AnnaBridge | 171:3a7713b1edbc | 2 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 3 | * @file stm32f0xx_hal_dma_ex.h |
AnnaBridge | 171:3a7713b1edbc | 4 | * @author MCD Application Team |
AnnaBridge | 171:3a7713b1edbc | 5 | * @brief Header file of DMA HAL Extension module. |
AnnaBridge | 171:3a7713b1edbc | 6 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 7 | * @attention |
AnnaBridge | 171:3a7713b1edbc | 8 | * |
AnnaBridge | 171:3a7713b1edbc | 9 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
AnnaBridge | 171:3a7713b1edbc | 10 | * |
AnnaBridge | 171:3a7713b1edbc | 11 | * Redistribution and use in source and binary forms, with or without modification, |
AnnaBridge | 171:3a7713b1edbc | 12 | * are permitted provided that the following conditions are met: |
AnnaBridge | 171:3a7713b1edbc | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 14 | * this list of conditions and the following disclaimer. |
AnnaBridge | 171:3a7713b1edbc | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 171:3a7713b1edbc | 17 | * and/or other materials provided with the distribution. |
AnnaBridge | 171:3a7713b1edbc | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
AnnaBridge | 171:3a7713b1edbc | 19 | * may be used to endorse or promote products derived from this software |
AnnaBridge | 171:3a7713b1edbc | 20 | * without specific prior written permission. |
AnnaBridge | 171:3a7713b1edbc | 21 | * |
AnnaBridge | 171:3a7713b1edbc | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
AnnaBridge | 171:3a7713b1edbc | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
AnnaBridge | 171:3a7713b1edbc | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 171:3a7713b1edbc | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
AnnaBridge | 171:3a7713b1edbc | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 171:3a7713b1edbc | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
AnnaBridge | 171:3a7713b1edbc | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
AnnaBridge | 171:3a7713b1edbc | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
AnnaBridge | 171:3a7713b1edbc | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
AnnaBridge | 171:3a7713b1edbc | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 171:3a7713b1edbc | 32 | * |
AnnaBridge | 171:3a7713b1edbc | 33 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 34 | */ |
AnnaBridge | 171:3a7713b1edbc | 35 | |
AnnaBridge | 171:3a7713b1edbc | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 37 | #ifndef __STM32F0xx_HAL_DMA_EX_H |
AnnaBridge | 171:3a7713b1edbc | 38 | #define __STM32F0xx_HAL_DMA_EX_H |
AnnaBridge | 171:3a7713b1edbc | 39 | |
AnnaBridge | 171:3a7713b1edbc | 40 | #ifdef __cplusplus |
AnnaBridge | 171:3a7713b1edbc | 41 | extern "C" { |
AnnaBridge | 171:3a7713b1edbc | 42 | #endif |
AnnaBridge | 171:3a7713b1edbc | 43 | |
AnnaBridge | 171:3a7713b1edbc | 44 | /* Includes ------------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 45 | #include "stm32f0xx_hal_def.h" |
AnnaBridge | 171:3a7713b1edbc | 46 | |
AnnaBridge | 171:3a7713b1edbc | 47 | /** @addtogroup STM32F0xx_HAL_Driver |
AnnaBridge | 171:3a7713b1edbc | 48 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 49 | */ |
AnnaBridge | 171:3a7713b1edbc | 50 | |
AnnaBridge | 171:3a7713b1edbc | 51 | /** @defgroup DMAEx DMAEx |
AnnaBridge | 171:3a7713b1edbc | 52 | * @brief DMA HAL module driver |
AnnaBridge | 171:3a7713b1edbc | 53 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 54 | */ |
AnnaBridge | 171:3a7713b1edbc | 55 | |
AnnaBridge | 171:3a7713b1edbc | 56 | /* Exported types ------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 57 | /* Exported constants --------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 58 | #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) |
AnnaBridge | 171:3a7713b1edbc | 59 | /** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants |
AnnaBridge | 171:3a7713b1edbc | 60 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 61 | */ |
AnnaBridge | 171:3a7713b1edbc | 62 | #define DMA1_CHANNEL1_RMP 0x00000000 /*!< Internal define for remaping on STM32F09x/30xC */ |
AnnaBridge | 171:3a7713b1edbc | 63 | #define DMA1_CHANNEL2_RMP 0x10000000 /*!< Internal define for remaping on STM32F09x/30xC */ |
AnnaBridge | 171:3a7713b1edbc | 64 | #define DMA1_CHANNEL3_RMP 0x20000000 /*!< Internal define for remaping on STM32F09x/30xC */ |
AnnaBridge | 171:3a7713b1edbc | 65 | #define DMA1_CHANNEL4_RMP 0x30000000 /*!< Internal define for remaping on STM32F09x/30xC */ |
AnnaBridge | 171:3a7713b1edbc | 66 | #define DMA1_CHANNEL5_RMP 0x40000000 /*!< Internal define for remaping on STM32F09x/30xC */ |
AnnaBridge | 171:3a7713b1edbc | 67 | #if !defined(STM32F030xC) |
AnnaBridge | 171:3a7713b1edbc | 68 | #define DMA1_CHANNEL6_RMP 0x50000000 /*!< Internal define for remaping on STM32F09x/30xC */ |
AnnaBridge | 171:3a7713b1edbc | 69 | #define DMA1_CHANNEL7_RMP 0x60000000 /*!< Internal define for remaping on STM32F09x/30xC */ |
AnnaBridge | 171:3a7713b1edbc | 70 | #define DMA2_CHANNEL1_RMP 0x00000000 /*!< Internal define for remaping on STM32F09x/30xC */ |
AnnaBridge | 171:3a7713b1edbc | 71 | #define DMA2_CHANNEL2_RMP 0x10000000 /*!< Internal define for remaping on STM32F09x/30xC */ |
AnnaBridge | 171:3a7713b1edbc | 72 | #define DMA2_CHANNEL3_RMP 0x20000000 /*!< Internal define for remaping on STM32F09x/30xC */ |
AnnaBridge | 171:3a7713b1edbc | 73 | #define DMA2_CHANNEL4_RMP 0x30000000 /*!< Internal define for remaping on STM32F09x/30xC */ |
AnnaBridge | 171:3a7713b1edbc | 74 | #define DMA2_CHANNEL5_RMP 0x40000000 /*!< Internal define for remaping on STM32F09x/30xC */ |
AnnaBridge | 171:3a7713b1edbc | 75 | #endif /* !defined(STM32F030xC) */ |
AnnaBridge | 171:3a7713b1edbc | 76 | |
AnnaBridge | 171:3a7713b1edbc | 77 | /****************** DMA1 remap bit field definition********************/ |
AnnaBridge | 171:3a7713b1edbc | 78 | /* DMA1 - Channel 1 */ |
AnnaBridge | 171:3a7713b1edbc | 79 | #define HAL_DMA1_CH1_DEFAULT (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ |
AnnaBridge | 171:3a7713b1edbc | 80 | #define HAL_DMA1_CH1_ADC (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_ADC) /*!< Remap ADC on DMA1 Channel 1*/ |
AnnaBridge | 171:3a7713b1edbc | 81 | #define HAL_DMA1_CH1_TIM17_CH1 (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 1 */ |
AnnaBridge | 171:3a7713b1edbc | 82 | #define HAL_DMA1_CH1_TIM17_UP (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 1 */ |
AnnaBridge | 171:3a7713b1edbc | 83 | #define HAL_DMA1_CH1_USART1_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 1 */ |
AnnaBridge | 171:3a7713b1edbc | 84 | #define HAL_DMA1_CH1_USART2_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 1 */ |
AnnaBridge | 171:3a7713b1edbc | 85 | #define HAL_DMA1_CH1_USART3_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 1 */ |
AnnaBridge | 171:3a7713b1edbc | 86 | #define HAL_DMA1_CH1_USART4_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 1 */ |
AnnaBridge | 171:3a7713b1edbc | 87 | #define HAL_DMA1_CH1_USART5_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 1 */ |
AnnaBridge | 171:3a7713b1edbc | 88 | #define HAL_DMA1_CH1_USART6_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 1 */ |
AnnaBridge | 171:3a7713b1edbc | 89 | #if !defined(STM32F030xC) |
AnnaBridge | 171:3a7713b1edbc | 90 | #define HAL_DMA1_CH1_USART7_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 1 */ |
AnnaBridge | 171:3a7713b1edbc | 91 | #define HAL_DMA1_CH1_USART8_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 1 */ |
AnnaBridge | 171:3a7713b1edbc | 92 | #endif /* !defined(STM32F030xC) */ |
AnnaBridge | 171:3a7713b1edbc | 93 | |
AnnaBridge | 171:3a7713b1edbc | 94 | /* DMA1 - Channel 2 */ |
AnnaBridge | 171:3a7713b1edbc | 95 | #define HAL_DMA1_CH2_DEFAULT (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ |
AnnaBridge | 171:3a7713b1edbc | 96 | #define HAL_DMA1_CH2_ADC (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_ADC) /*!< Remap ADC on DMA1 channel 2 */ |
AnnaBridge | 171:3a7713b1edbc | 97 | #define HAL_DMA1_CH2_I2C1_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 2 */ |
AnnaBridge | 171:3a7713b1edbc | 98 | #define HAL_DMA1_CH2_SPI1_RX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_SPI1_RX) /*!< Remap SPI1 Rx on DMA1 channel 2 */ |
AnnaBridge | 171:3a7713b1edbc | 99 | #define HAL_DMA1_CH2_TIM1_CH1 (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 2 */ |
AnnaBridge | 171:3a7713b1edbc | 100 | #define HAL_DMA1_CH2_TIM17_CH1 (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 2 */ |
AnnaBridge | 171:3a7713b1edbc | 101 | #define HAL_DMA1_CH2_TIM17_UP (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 2 */ |
AnnaBridge | 171:3a7713b1edbc | 102 | #define HAL_DMA1_CH2_USART1_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 2 */ |
AnnaBridge | 171:3a7713b1edbc | 103 | #define HAL_DMA1_CH2_USART2_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 2 */ |
AnnaBridge | 171:3a7713b1edbc | 104 | #define HAL_DMA1_CH2_USART3_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 2 */ |
AnnaBridge | 171:3a7713b1edbc | 105 | #define HAL_DMA1_CH2_USART4_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 2 */ |
AnnaBridge | 171:3a7713b1edbc | 106 | #define HAL_DMA1_CH2_USART5_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 2 */ |
AnnaBridge | 171:3a7713b1edbc | 107 | #define HAL_DMA1_CH2_USART6_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 2 */ |
AnnaBridge | 171:3a7713b1edbc | 108 | #if !defined(STM32F030xC) |
AnnaBridge | 171:3a7713b1edbc | 109 | #define HAL_DMA1_CH2_USART7_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 2 */ |
AnnaBridge | 171:3a7713b1edbc | 110 | #define HAL_DMA1_CH2_USART8_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 2 */ |
AnnaBridge | 171:3a7713b1edbc | 111 | #endif /* !defined(STM32F030xC) */ |
AnnaBridge | 171:3a7713b1edbc | 112 | |
AnnaBridge | 171:3a7713b1edbc | 113 | /* DMA1 - Channel 3 */ |
AnnaBridge | 171:3a7713b1edbc | 114 | #define HAL_DMA1_CH3_DEFAULT (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ |
AnnaBridge | 171:3a7713b1edbc | 115 | #define HAL_DMA1_CH3_TIM6_UP (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA1 channel 3 */ |
AnnaBridge | 171:3a7713b1edbc | 116 | #if !defined(STM32F030xC) |
AnnaBridge | 171:3a7713b1edbc | 117 | #define HAL_DMA1_CH3_DAC_CH1 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_DAC_CH1) /*!< Remap DAC Channel 1on DMA1 channel 3 */ |
AnnaBridge | 171:3a7713b1edbc | 118 | #endif /* !defined(STM32F030xC) */ |
AnnaBridge | 171:3a7713b1edbc | 119 | #define HAL_DMA1_CH3_I2C1_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 3 */ |
AnnaBridge | 171:3a7713b1edbc | 120 | #define HAL_DMA1_CH3_SPI1_TX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_SPI1_TX) /*!< Remap SPI1 Tx on DMA1 channel 3 */ |
AnnaBridge | 171:3a7713b1edbc | 121 | #define HAL_DMA1_CH3_TIM1_CH2 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 3 */ |
AnnaBridge | 171:3a7713b1edbc | 122 | #if !defined(STM32F030xC) |
AnnaBridge | 171:3a7713b1edbc | 123 | #define HAL_DMA1_CH3_TIM2_CH2 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 3 */ |
AnnaBridge | 171:3a7713b1edbc | 124 | #endif /* !defined(STM32F030xC) */ |
AnnaBridge | 171:3a7713b1edbc | 125 | #define HAL_DMA1_CH3_TIM16_CH1 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 3 */ |
AnnaBridge | 171:3a7713b1edbc | 126 | #define HAL_DMA1_CH3_TIM16_UP (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 3 */ |
AnnaBridge | 171:3a7713b1edbc | 127 | #define HAL_DMA1_CH3_USART1_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 3 */ |
AnnaBridge | 171:3a7713b1edbc | 128 | #define HAL_DMA1_CH3_USART2_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 3 */ |
AnnaBridge | 171:3a7713b1edbc | 129 | #define HAL_DMA1_CH3_USART3_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 3 */ |
AnnaBridge | 171:3a7713b1edbc | 130 | #define HAL_DMA1_CH3_USART4_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 3 */ |
AnnaBridge | 171:3a7713b1edbc | 131 | #define HAL_DMA1_CH3_USART5_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 3 */ |
AnnaBridge | 171:3a7713b1edbc | 132 | #define HAL_DMA1_CH3_USART6_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 3 */ |
AnnaBridge | 171:3a7713b1edbc | 133 | #if !defined(STM32F030xC) |
AnnaBridge | 171:3a7713b1edbc | 134 | #define HAL_DMA1_CH3_USART7_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 3 */ |
AnnaBridge | 171:3a7713b1edbc | 135 | #define HAL_DMA1_CH3_USART8_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 3 */ |
AnnaBridge | 171:3a7713b1edbc | 136 | #endif /* !defined(STM32F030xC) */ |
AnnaBridge | 171:3a7713b1edbc | 137 | |
AnnaBridge | 171:3a7713b1edbc | 138 | /* DMA1 - Channel 4 */ |
AnnaBridge | 171:3a7713b1edbc | 139 | #define HAL_DMA1_CH4_DEFAULT (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ |
AnnaBridge | 171:3a7713b1edbc | 140 | #define HAL_DMA1_CH4_TIM7_UP (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA1 channel 4 */ |
AnnaBridge | 171:3a7713b1edbc | 141 | #if !defined(STM32F030xC) |
AnnaBridge | 171:3a7713b1edbc | 142 | #define HAL_DMA1_CH4_DAC_CH2 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_DAC_CH2) /*!< Remap DAC Channel 2 on DMA1 channel 4 */ |
AnnaBridge | 171:3a7713b1edbc | 143 | #endif /* !defined(STM32F030xC) */ |
AnnaBridge | 171:3a7713b1edbc | 144 | #define HAL_DMA1_CH4_I2C2_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_I2C2_TX) /*!< Remap I2C2 Tx on DMA1 channel 4 */ |
AnnaBridge | 171:3a7713b1edbc | 145 | #define HAL_DMA1_CH4_SPI2_RX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 4 */ |
AnnaBridge | 171:3a7713b1edbc | 146 | #if !defined(STM32F030xC) |
AnnaBridge | 171:3a7713b1edbc | 147 | #define HAL_DMA1_CH4_TIM2_CH4 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 4 */ |
AnnaBridge | 171:3a7713b1edbc | 148 | #endif /* !defined(STM32F030xC) */ |
AnnaBridge | 171:3a7713b1edbc | 149 | #define HAL_DMA1_CH4_TIM3_CH1 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 4 */ |
AnnaBridge | 171:3a7713b1edbc | 150 | #define HAL_DMA1_CH4_TIM3_TRIG (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 4 */ |
AnnaBridge | 171:3a7713b1edbc | 151 | #define HAL_DMA1_CH4_TIM16_CH1 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 4 */ |
AnnaBridge | 171:3a7713b1edbc | 152 | #define HAL_DMA1_CH4_TIM16_UP (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 4 */ |
AnnaBridge | 171:3a7713b1edbc | 153 | #define HAL_DMA1_CH4_USART1_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 4 */ |
AnnaBridge | 171:3a7713b1edbc | 154 | #define HAL_DMA1_CH4_USART2_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 4 */ |
AnnaBridge | 171:3a7713b1edbc | 155 | #define HAL_DMA1_CH4_USART3_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 4 */ |
AnnaBridge | 171:3a7713b1edbc | 156 | #define HAL_DMA1_CH4_USART4_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 4 */ |
AnnaBridge | 171:3a7713b1edbc | 157 | #define HAL_DMA1_CH4_USART5_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 4 */ |
AnnaBridge | 171:3a7713b1edbc | 158 | #define HAL_DMA1_CH4_USART6_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 4 */ |
AnnaBridge | 171:3a7713b1edbc | 159 | #if !defined(STM32F030xC) |
AnnaBridge | 171:3a7713b1edbc | 160 | #define HAL_DMA1_CH4_USART7_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 4 */ |
AnnaBridge | 171:3a7713b1edbc | 161 | #define HAL_DMA1_CH4_USART8_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 4 */ |
AnnaBridge | 171:3a7713b1edbc | 162 | #endif /* !defined(STM32F030xC) */ |
AnnaBridge | 171:3a7713b1edbc | 163 | |
AnnaBridge | 171:3a7713b1edbc | 164 | /* DMA1 - Channel 5 */ |
AnnaBridge | 171:3a7713b1edbc | 165 | #define HAL_DMA1_CH5_DEFAULT (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ |
AnnaBridge | 171:3a7713b1edbc | 166 | #define HAL_DMA1_CH5_I2C2_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_I2C2_RX) /*!< Remap I2C2 Rx on DMA1 channel 5 */ |
AnnaBridge | 171:3a7713b1edbc | 167 | #define HAL_DMA1_CH5_SPI2_TX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_SPI2_TX) /*!< Remap SPI1 Tx on DMA1 channel 5 */ |
AnnaBridge | 171:3a7713b1edbc | 168 | #define HAL_DMA1_CH5_TIM1_CH3 (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 5 */ |
AnnaBridge | 171:3a7713b1edbc | 169 | #define HAL_DMA1_CH5_USART1_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 5 */ |
AnnaBridge | 171:3a7713b1edbc | 170 | #define HAL_DMA1_CH5_USART2_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 5 */ |
AnnaBridge | 171:3a7713b1edbc | 171 | #define HAL_DMA1_CH5_USART3_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 5 */ |
AnnaBridge | 171:3a7713b1edbc | 172 | #define HAL_DMA1_CH5_USART4_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 5 */ |
AnnaBridge | 171:3a7713b1edbc | 173 | #define HAL_DMA1_CH5_USART5_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 5 */ |
AnnaBridge | 171:3a7713b1edbc | 174 | #define HAL_DMA1_CH5_USART6_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 5 */ |
AnnaBridge | 171:3a7713b1edbc | 175 | #if !defined(STM32F030xC) |
AnnaBridge | 171:3a7713b1edbc | 176 | #define HAL_DMA1_CH5_USART7_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 5 */ |
AnnaBridge | 171:3a7713b1edbc | 177 | #define HAL_DMA1_CH5_USART8_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 5 */ |
AnnaBridge | 171:3a7713b1edbc | 178 | #endif /* !defined(STM32F030xC) */ |
AnnaBridge | 171:3a7713b1edbc | 179 | |
AnnaBridge | 171:3a7713b1edbc | 180 | #if !defined(STM32F030xC) |
AnnaBridge | 171:3a7713b1edbc | 181 | /* DMA1 - Channel 6 */ |
AnnaBridge | 171:3a7713b1edbc | 182 | #define HAL_DMA1_CH6_DEFAULT (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ |
AnnaBridge | 171:3a7713b1edbc | 183 | #define HAL_DMA1_CH6_I2C1_TX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 6 */ |
AnnaBridge | 171:3a7713b1edbc | 184 | #define HAL_DMA1_CH6_SPI2_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 6 */ |
AnnaBridge | 171:3a7713b1edbc | 185 | #define HAL_DMA1_CH6_TIM1_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 6 */ |
AnnaBridge | 171:3a7713b1edbc | 186 | #define HAL_DMA1_CH6_TIM1_CH2 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 6 */ |
AnnaBridge | 171:3a7713b1edbc | 187 | #define HAL_DMA1_CH6_TIM1_CH3 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 6 */ |
AnnaBridge | 171:3a7713b1edbc | 188 | #define HAL_DMA1_CH6_TIM3_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 6 */ |
AnnaBridge | 171:3a7713b1edbc | 189 | #define HAL_DMA1_CH6_TIM3_TRIG (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 6 */ |
AnnaBridge | 171:3a7713b1edbc | 190 | #define HAL_DMA1_CH6_TIM16_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 6 */ |
AnnaBridge | 171:3a7713b1edbc | 191 | #define HAL_DMA1_CH6_TIM16_UP (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 6 */ |
AnnaBridge | 171:3a7713b1edbc | 192 | #define HAL_DMA1_CH6_USART1_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 6 */ |
AnnaBridge | 171:3a7713b1edbc | 193 | #define HAL_DMA1_CH6_USART2_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 6 */ |
AnnaBridge | 171:3a7713b1edbc | 194 | #define HAL_DMA1_CH6_USART3_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 6 */ |
AnnaBridge | 171:3a7713b1edbc | 195 | #define HAL_DMA1_CH6_USART4_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 6 */ |
AnnaBridge | 171:3a7713b1edbc | 196 | #define HAL_DMA1_CH6_USART5_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 6 */ |
AnnaBridge | 171:3a7713b1edbc | 197 | #define HAL_DMA1_CH6_USART6_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 6 */ |
AnnaBridge | 171:3a7713b1edbc | 198 | #define HAL_DMA1_CH6_USART7_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 6 */ |
AnnaBridge | 171:3a7713b1edbc | 199 | #define HAL_DMA1_CH6_USART8_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 6 */ |
AnnaBridge | 171:3a7713b1edbc | 200 | /* DMA1 - Channel 7 */ |
AnnaBridge | 171:3a7713b1edbc | 201 | #define HAL_DMA1_CH7_DEFAULT (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ |
AnnaBridge | 171:3a7713b1edbc | 202 | #define HAL_DMA1_CH7_I2C1_RX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 7 */ |
AnnaBridge | 171:3a7713b1edbc | 203 | #define HAL_DMA1_CH7_SPI2_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_SPI2_TX) /*!< Remap SPI2 Tx on DMA1 channel 7 */ |
AnnaBridge | 171:3a7713b1edbc | 204 | #define HAL_DMA1_CH7_TIM2_CH2 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 7 */ |
AnnaBridge | 171:3a7713b1edbc | 205 | #define HAL_DMA1_CH7_TIM2_CH4 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 7 */ |
AnnaBridge | 171:3a7713b1edbc | 206 | #define HAL_DMA1_CH7_TIM17_CH1 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 7 */ |
AnnaBridge | 171:3a7713b1edbc | 207 | #define HAL_DMA1_CH7_TIM17_UP (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 7 */ |
AnnaBridge | 171:3a7713b1edbc | 208 | #define HAL_DMA1_CH7_USART1_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 7 */ |
AnnaBridge | 171:3a7713b1edbc | 209 | #define HAL_DMA1_CH7_USART2_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 7 */ |
AnnaBridge | 171:3a7713b1edbc | 210 | #define HAL_DMA1_CH7_USART3_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 7 */ |
AnnaBridge | 171:3a7713b1edbc | 211 | #define HAL_DMA1_CH7_USART4_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 7 */ |
AnnaBridge | 171:3a7713b1edbc | 212 | #define HAL_DMA1_CH7_USART5_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 7 */ |
AnnaBridge | 171:3a7713b1edbc | 213 | #define HAL_DMA1_CH7_USART6_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 7 */ |
AnnaBridge | 171:3a7713b1edbc | 214 | #define HAL_DMA1_CH7_USART7_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 7 */ |
AnnaBridge | 171:3a7713b1edbc | 215 | #define HAL_DMA1_CH7_USART8_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 7 */ |
AnnaBridge | 171:3a7713b1edbc | 216 | |
AnnaBridge | 171:3a7713b1edbc | 217 | /****************** DMA2 remap bit field definition********************/ |
AnnaBridge | 171:3a7713b1edbc | 218 | /* DMA2 - Channel 1 */ |
AnnaBridge | 171:3a7713b1edbc | 219 | #define HAL_DMA2_CH1_DEFAULT (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */ |
AnnaBridge | 171:3a7713b1edbc | 220 | #define HAL_DMA2_CH1_I2C2_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_I2C2_TX) /*!< Remap I2C2 TX on DMA2 channel 1 */ |
AnnaBridge | 171:3a7713b1edbc | 221 | #define HAL_DMA2_CH1_USART1_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 1 */ |
AnnaBridge | 171:3a7713b1edbc | 222 | #define HAL_DMA2_CH1_USART2_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 1 */ |
AnnaBridge | 171:3a7713b1edbc | 223 | #define HAL_DMA2_CH1_USART3_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 1 */ |
AnnaBridge | 171:3a7713b1edbc | 224 | #define HAL_DMA2_CH1_USART4_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 1 */ |
AnnaBridge | 171:3a7713b1edbc | 225 | #define HAL_DMA2_CH1_USART5_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 1 */ |
AnnaBridge | 171:3a7713b1edbc | 226 | #define HAL_DMA2_CH1_USART6_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 1 */ |
AnnaBridge | 171:3a7713b1edbc | 227 | #define HAL_DMA2_CH1_USART7_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 1 */ |
AnnaBridge | 171:3a7713b1edbc | 228 | #define HAL_DMA2_CH1_USART8_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 1 */ |
AnnaBridge | 171:3a7713b1edbc | 229 | /* DMA2 - Channel 2 */ |
AnnaBridge | 171:3a7713b1edbc | 230 | #define HAL_DMA2_CH2_DEFAULT (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */ |
AnnaBridge | 171:3a7713b1edbc | 231 | #define HAL_DMA2_CH2_I2C2_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_I2C2_RX) /*!< Remap I2C2 Rx on DMA2 channel 2 */ |
AnnaBridge | 171:3a7713b1edbc | 232 | #define HAL_DMA2_CH2_USART1_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 2 */ |
AnnaBridge | 171:3a7713b1edbc | 233 | #define HAL_DMA2_CH2_USART2_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 2 */ |
AnnaBridge | 171:3a7713b1edbc | 234 | #define HAL_DMA2_CH2_USART3_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 2 */ |
AnnaBridge | 171:3a7713b1edbc | 235 | #define HAL_DMA2_CH2_USART4_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 2 */ |
AnnaBridge | 171:3a7713b1edbc | 236 | #define HAL_DMA2_CH2_USART5_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 2 */ |
AnnaBridge | 171:3a7713b1edbc | 237 | #define HAL_DMA2_CH2_USART6_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 2 */ |
AnnaBridge | 171:3a7713b1edbc | 238 | #define HAL_DMA2_CH2_USART7_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 2 */ |
AnnaBridge | 171:3a7713b1edbc | 239 | #define HAL_DMA2_CH2_USART8_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 2 */ |
AnnaBridge | 171:3a7713b1edbc | 240 | /* DMA2 - Channel 3 */ |
AnnaBridge | 171:3a7713b1edbc | 241 | #define HAL_DMA2_CH3_DEFAULT (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */ |
AnnaBridge | 171:3a7713b1edbc | 242 | #define HAL_DMA2_CH3_TIM6_UP (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA2 channel 3 */ |
AnnaBridge | 171:3a7713b1edbc | 243 | #define HAL_DMA2_CH3_DAC_CH1 (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_DAC_CH1) /*!< Remap DAC channel 1 on DMA2 channel 3 */ |
AnnaBridge | 171:3a7713b1edbc | 244 | #define HAL_DMA2_CH3_SPI1_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_SPI1_RX) /*!< Remap SPI1 Rx on DMA2 channel 3 */ |
AnnaBridge | 171:3a7713b1edbc | 245 | #define HAL_DMA2_CH3_USART1_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 3 */ |
AnnaBridge | 171:3a7713b1edbc | 246 | #define HAL_DMA2_CH3_USART2_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 3 */ |
AnnaBridge | 171:3a7713b1edbc | 247 | #define HAL_DMA2_CH3_USART3_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 3 */ |
AnnaBridge | 171:3a7713b1edbc | 248 | #define HAL_DMA2_CH3_USART4_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 3 */ |
AnnaBridge | 171:3a7713b1edbc | 249 | #define HAL_DMA2_CH3_USART5_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 3 */ |
AnnaBridge | 171:3a7713b1edbc | 250 | #define HAL_DMA2_CH3_USART6_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 3 */ |
AnnaBridge | 171:3a7713b1edbc | 251 | #define HAL_DMA2_CH3_USART7_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 3 */ |
AnnaBridge | 171:3a7713b1edbc | 252 | #define HAL_DMA2_CH3_USART8_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 3 */ |
AnnaBridge | 171:3a7713b1edbc | 253 | /* DMA2 - Channel 4 */ |
AnnaBridge | 171:3a7713b1edbc | 254 | #define HAL_DMA2_CH4_DEFAULT (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */ |
AnnaBridge | 171:3a7713b1edbc | 255 | #define HAL_DMA2_CH4_TIM7_UP (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA2 channel 4 */ |
AnnaBridge | 171:3a7713b1edbc | 256 | #define HAL_DMA2_CH4_DAC_CH2 (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_DAC_CH2) /*!< Remap DAC channel 2 on DMA2 channel 4 */ |
AnnaBridge | 171:3a7713b1edbc | 257 | #define HAL_DMA2_CH4_SPI1_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_SPI1_TX) /*!< Remap SPI1 Tx on DMA2 channel 4 */ |
AnnaBridge | 171:3a7713b1edbc | 258 | #define HAL_DMA2_CH4_USART1_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 4 */ |
AnnaBridge | 171:3a7713b1edbc | 259 | #define HAL_DMA2_CH4_USART2_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 4 */ |
AnnaBridge | 171:3a7713b1edbc | 260 | #define HAL_DMA2_CH4_USART3_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 4 */ |
AnnaBridge | 171:3a7713b1edbc | 261 | #define HAL_DMA2_CH4_USART4_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 4 */ |
AnnaBridge | 171:3a7713b1edbc | 262 | #define HAL_DMA2_CH4_USART5_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 4 */ |
AnnaBridge | 171:3a7713b1edbc | 263 | #define HAL_DMA2_CH4_USART6_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 4 */ |
AnnaBridge | 171:3a7713b1edbc | 264 | #define HAL_DMA2_CH4_USART7_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 4 */ |
AnnaBridge | 171:3a7713b1edbc | 265 | #define HAL_DMA2_CH4_USART8_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 4 */ |
AnnaBridge | 171:3a7713b1edbc | 266 | /* DMA2 - Channel 5 */ |
AnnaBridge | 171:3a7713b1edbc | 267 | #define HAL_DMA2_CH5_DEFAULT (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */ |
AnnaBridge | 171:3a7713b1edbc | 268 | #define HAL_DMA2_CH5_ADC (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_ADC) /*!< Remap ADC on DMA2 channel 5 */ |
AnnaBridge | 171:3a7713b1edbc | 269 | #define HAL_DMA2_CH5_USART1_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 5 */ |
AnnaBridge | 171:3a7713b1edbc | 270 | #define HAL_DMA2_CH5_USART2_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 5 */ |
AnnaBridge | 171:3a7713b1edbc | 271 | #define HAL_DMA2_CH5_USART3_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 5 */ |
AnnaBridge | 171:3a7713b1edbc | 272 | #define HAL_DMA2_CH5_USART4_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 5 */ |
AnnaBridge | 171:3a7713b1edbc | 273 | #define HAL_DMA2_CH5_USART5_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 5 */ |
AnnaBridge | 171:3a7713b1edbc | 274 | #define HAL_DMA2_CH5_USART6_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 5 */ |
AnnaBridge | 171:3a7713b1edbc | 275 | #define HAL_DMA2_CH5_USART7_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 5 */ |
AnnaBridge | 171:3a7713b1edbc | 276 | #define HAL_DMA2_CH5_USART8_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 5 */ |
AnnaBridge | 171:3a7713b1edbc | 277 | #endif /* !defined(STM32F030xC) */ |
AnnaBridge | 171:3a7713b1edbc | 278 | |
AnnaBridge | 171:3a7713b1edbc | 279 | #if defined(STM32F091xC) || defined(STM32F098xx) |
AnnaBridge | 171:3a7713b1edbc | 280 | #define IS_HAL_DMA1_REMAP(REQUEST) (((REQUEST) == HAL_DMA1_CH1_DEFAULT) ||\ |
AnnaBridge | 171:3a7713b1edbc | 281 | ((REQUEST) == HAL_DMA1_CH1_ADC) ||\ |
AnnaBridge | 171:3a7713b1edbc | 282 | ((REQUEST) == HAL_DMA1_CH1_TIM17_CH1) ||\ |
AnnaBridge | 171:3a7713b1edbc | 283 | ((REQUEST) == HAL_DMA1_CH1_TIM17_UP) ||\ |
AnnaBridge | 171:3a7713b1edbc | 284 | ((REQUEST) == HAL_DMA1_CH1_USART1_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 285 | ((REQUEST) == HAL_DMA1_CH1_USART2_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 286 | ((REQUEST) == HAL_DMA1_CH1_USART3_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 287 | ((REQUEST) == HAL_DMA1_CH1_USART4_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 288 | ((REQUEST) == HAL_DMA1_CH1_USART5_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 289 | ((REQUEST) == HAL_DMA1_CH1_USART6_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 290 | ((REQUEST) == HAL_DMA1_CH1_USART7_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 291 | ((REQUEST) == HAL_DMA1_CH1_USART8_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 292 | ((REQUEST) == HAL_DMA1_CH2_DEFAULT) ||\ |
AnnaBridge | 171:3a7713b1edbc | 293 | ((REQUEST) == HAL_DMA1_CH2_ADC) ||\ |
AnnaBridge | 171:3a7713b1edbc | 294 | ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 295 | ((REQUEST) == HAL_DMA1_CH2_SPI1_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 296 | ((REQUEST) == HAL_DMA1_CH2_TIM1_CH1) ||\ |
AnnaBridge | 171:3a7713b1edbc | 297 | ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 298 | ((REQUEST) == HAL_DMA1_CH2_TIM17_CH1) ||\ |
AnnaBridge | 171:3a7713b1edbc | 299 | ((REQUEST) == HAL_DMA1_CH2_TIM17_UP) ||\ |
AnnaBridge | 171:3a7713b1edbc | 300 | ((REQUEST) == HAL_DMA1_CH2_USART1_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 301 | ((REQUEST) == HAL_DMA1_CH2_USART2_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 302 | ((REQUEST) == HAL_DMA1_CH2_USART3_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 303 | ((REQUEST) == HAL_DMA1_CH2_USART4_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 304 | ((REQUEST) == HAL_DMA1_CH2_USART5_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 305 | ((REQUEST) == HAL_DMA1_CH2_USART6_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 306 | ((REQUEST) == HAL_DMA1_CH2_USART7_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 307 | ((REQUEST) == HAL_DMA1_CH2_USART8_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 308 | ((REQUEST) == HAL_DMA1_CH3_DEFAULT) ||\ |
AnnaBridge | 171:3a7713b1edbc | 309 | ((REQUEST) == HAL_DMA1_CH3_TIM6_UP) ||\ |
AnnaBridge | 171:3a7713b1edbc | 310 | ((REQUEST) == HAL_DMA1_CH3_DAC_CH1) ||\ |
AnnaBridge | 171:3a7713b1edbc | 311 | ((REQUEST) == HAL_DMA1_CH3_I2C1_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 312 | ((REQUEST) == HAL_DMA1_CH3_SPI1_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 313 | ((REQUEST) == HAL_DMA1_CH3_TIM1_CH2) ||\ |
AnnaBridge | 171:3a7713b1edbc | 314 | ((REQUEST) == HAL_DMA1_CH3_TIM2_CH2) ||\ |
AnnaBridge | 171:3a7713b1edbc | 315 | ((REQUEST) == HAL_DMA1_CH3_TIM16_CH1) ||\ |
AnnaBridge | 171:3a7713b1edbc | 316 | ((REQUEST) == HAL_DMA1_CH3_TIM16_UP) ||\ |
AnnaBridge | 171:3a7713b1edbc | 317 | ((REQUEST) == HAL_DMA1_CH3_USART1_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 318 | ((REQUEST) == HAL_DMA1_CH3_USART2_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 319 | ((REQUEST) == HAL_DMA1_CH3_USART3_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 320 | ((REQUEST) == HAL_DMA1_CH3_USART4_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 321 | ((REQUEST) == HAL_DMA1_CH3_USART5_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 322 | ((REQUEST) == HAL_DMA1_CH3_USART6_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 323 | ((REQUEST) == HAL_DMA1_CH3_USART7_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 324 | ((REQUEST) == HAL_DMA1_CH3_USART8_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 325 | ((REQUEST) == HAL_DMA1_CH4_DEFAULT) ||\ |
AnnaBridge | 171:3a7713b1edbc | 326 | ((REQUEST) == HAL_DMA1_CH4_TIM7_UP) ||\ |
AnnaBridge | 171:3a7713b1edbc | 327 | ((REQUEST) == HAL_DMA1_CH4_DAC_CH2) ||\ |
AnnaBridge | 171:3a7713b1edbc | 328 | ((REQUEST) == HAL_DMA1_CH4_I2C2_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 329 | ((REQUEST) == HAL_DMA1_CH4_SPI2_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 330 | ((REQUEST) == HAL_DMA1_CH4_TIM2_CH4) ||\ |
AnnaBridge | 171:3a7713b1edbc | 331 | ((REQUEST) == HAL_DMA1_CH4_TIM3_CH1) ||\ |
AnnaBridge | 171:3a7713b1edbc | 332 | ((REQUEST) == HAL_DMA1_CH4_TIM3_TRIG) ||\ |
AnnaBridge | 171:3a7713b1edbc | 333 | ((REQUEST) == HAL_DMA1_CH4_TIM16_CH1) ||\ |
AnnaBridge | 171:3a7713b1edbc | 334 | ((REQUEST) == HAL_DMA1_CH4_TIM16_UP) ||\ |
AnnaBridge | 171:3a7713b1edbc | 335 | ((REQUEST) == HAL_DMA1_CH4_USART1_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 336 | ((REQUEST) == HAL_DMA1_CH4_USART2_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 337 | ((REQUEST) == HAL_DMA1_CH4_USART3_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 338 | ((REQUEST) == HAL_DMA1_CH4_USART4_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 339 | ((REQUEST) == HAL_DMA1_CH4_USART5_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 340 | ((REQUEST) == HAL_DMA1_CH4_USART6_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 341 | ((REQUEST) == HAL_DMA1_CH4_USART7_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 342 | ((REQUEST) == HAL_DMA1_CH4_USART8_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 343 | ((REQUEST) == HAL_DMA1_CH5_DEFAULT) ||\ |
AnnaBridge | 171:3a7713b1edbc | 344 | ((REQUEST) == HAL_DMA1_CH5_I2C2_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 345 | ((REQUEST) == HAL_DMA1_CH5_SPI2_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 346 | ((REQUEST) == HAL_DMA1_CH5_TIM1_CH3) ||\ |
AnnaBridge | 171:3a7713b1edbc | 347 | ((REQUEST) == HAL_DMA1_CH5_USART1_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 348 | ((REQUEST) == HAL_DMA1_CH5_USART2_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 349 | ((REQUEST) == HAL_DMA1_CH5_USART3_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 350 | ((REQUEST) == HAL_DMA1_CH5_USART4_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 351 | ((REQUEST) == HAL_DMA1_CH5_USART5_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 352 | ((REQUEST) == HAL_DMA1_CH5_USART6_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 353 | ((REQUEST) == HAL_DMA1_CH5_USART7_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 354 | ((REQUEST) == HAL_DMA1_CH5_USART8_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 355 | ((REQUEST) == HAL_DMA1_CH6_DEFAULT) ||\ |
AnnaBridge | 171:3a7713b1edbc | 356 | ((REQUEST) == HAL_DMA1_CH6_I2C1_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 357 | ((REQUEST) == HAL_DMA1_CH6_SPI2_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 358 | ((REQUEST) == HAL_DMA1_CH6_TIM1_CH1) ||\ |
AnnaBridge | 171:3a7713b1edbc | 359 | ((REQUEST) == HAL_DMA1_CH6_TIM1_CH2) ||\ |
AnnaBridge | 171:3a7713b1edbc | 360 | ((REQUEST) == HAL_DMA1_CH6_TIM1_CH3) ||\ |
AnnaBridge | 171:3a7713b1edbc | 361 | ((REQUEST) == HAL_DMA1_CH6_TIM3_CH1) ||\ |
AnnaBridge | 171:3a7713b1edbc | 362 | ((REQUEST) == HAL_DMA1_CH6_TIM3_TRIG) ||\ |
AnnaBridge | 171:3a7713b1edbc | 363 | ((REQUEST) == HAL_DMA1_CH6_TIM16_CH1) ||\ |
AnnaBridge | 171:3a7713b1edbc | 364 | ((REQUEST) == HAL_DMA1_CH6_TIM16_UP) ||\ |
AnnaBridge | 171:3a7713b1edbc | 365 | ((REQUEST) == HAL_DMA1_CH6_USART1_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 366 | ((REQUEST) == HAL_DMA1_CH6_USART2_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 367 | ((REQUEST) == HAL_DMA1_CH6_USART3_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 368 | ((REQUEST) == HAL_DMA1_CH6_USART4_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 369 | ((REQUEST) == HAL_DMA1_CH6_USART5_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 370 | ((REQUEST) == HAL_DMA1_CH6_USART6_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 371 | ((REQUEST) == HAL_DMA1_CH6_USART7_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 372 | ((REQUEST) == HAL_DMA1_CH6_USART8_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 373 | ((REQUEST) == HAL_DMA1_CH7_DEFAULT) ||\ |
AnnaBridge | 171:3a7713b1edbc | 374 | ((REQUEST) == HAL_DMA1_CH7_I2C1_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 375 | ((REQUEST) == HAL_DMA1_CH7_SPI2_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 376 | ((REQUEST) == HAL_DMA1_CH7_TIM2_CH2) ||\ |
AnnaBridge | 171:3a7713b1edbc | 377 | ((REQUEST) == HAL_DMA1_CH7_TIM2_CH4) ||\ |
AnnaBridge | 171:3a7713b1edbc | 378 | ((REQUEST) == HAL_DMA1_CH7_TIM17_CH1) ||\ |
AnnaBridge | 171:3a7713b1edbc | 379 | ((REQUEST) == HAL_DMA1_CH7_TIM17_UP) ||\ |
AnnaBridge | 171:3a7713b1edbc | 380 | ((REQUEST) == HAL_DMA1_CH7_USART1_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 381 | ((REQUEST) == HAL_DMA1_CH7_USART2_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 382 | ((REQUEST) == HAL_DMA1_CH7_USART3_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 383 | ((REQUEST) == HAL_DMA1_CH7_USART4_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 384 | ((REQUEST) == HAL_DMA1_CH7_USART5_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 385 | ((REQUEST) == HAL_DMA1_CH7_USART6_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 386 | ((REQUEST) == HAL_DMA1_CH7_USART7_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 387 | ((REQUEST) == HAL_DMA1_CH7_USART8_TX)) |
AnnaBridge | 171:3a7713b1edbc | 388 | |
AnnaBridge | 171:3a7713b1edbc | 389 | #define IS_HAL_DMA2_REMAP(REQUEST) (((REQUEST) == HAL_DMA2_CH1_DEFAULT) ||\ |
AnnaBridge | 171:3a7713b1edbc | 390 | ((REQUEST) == HAL_DMA2_CH1_I2C2_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 391 | ((REQUEST) == HAL_DMA2_CH1_USART1_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 392 | ((REQUEST) == HAL_DMA2_CH1_USART2_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 393 | ((REQUEST) == HAL_DMA2_CH1_USART3_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 394 | ((REQUEST) == HAL_DMA2_CH1_USART4_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 395 | ((REQUEST) == HAL_DMA2_CH1_USART5_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 396 | ((REQUEST) == HAL_DMA2_CH1_USART6_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 397 | ((REQUEST) == HAL_DMA2_CH1_USART7_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 398 | ((REQUEST) == HAL_DMA2_CH1_USART8_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 399 | ((REQUEST) == HAL_DMA2_CH2_DEFAULT) ||\ |
AnnaBridge | 171:3a7713b1edbc | 400 | ((REQUEST) == HAL_DMA2_CH2_I2C2_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 401 | ((REQUEST) == HAL_DMA2_CH2_USART1_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 402 | ((REQUEST) == HAL_DMA2_CH2_USART2_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 403 | ((REQUEST) == HAL_DMA2_CH2_USART3_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 404 | ((REQUEST) == HAL_DMA2_CH2_USART4_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 405 | ((REQUEST) == HAL_DMA2_CH2_USART5_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 406 | ((REQUEST) == HAL_DMA2_CH2_USART6_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 407 | ((REQUEST) == HAL_DMA2_CH2_USART7_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 408 | ((REQUEST) == HAL_DMA2_CH2_USART8_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 409 | ((REQUEST) == HAL_DMA2_CH3_DEFAULT) ||\ |
AnnaBridge | 171:3a7713b1edbc | 410 | ((REQUEST) == HAL_DMA2_CH3_TIM6_UP) ||\ |
AnnaBridge | 171:3a7713b1edbc | 411 | ((REQUEST) == HAL_DMA2_CH3_DAC_CH1) ||\ |
AnnaBridge | 171:3a7713b1edbc | 412 | ((REQUEST) == HAL_DMA2_CH3_SPI1_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 413 | ((REQUEST) == HAL_DMA2_CH3_USART1_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 414 | ((REQUEST) == HAL_DMA2_CH3_USART2_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 415 | ((REQUEST) == HAL_DMA2_CH3_USART3_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 416 | ((REQUEST) == HAL_DMA2_CH3_USART4_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 417 | ((REQUEST) == HAL_DMA2_CH3_USART5_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 418 | ((REQUEST) == HAL_DMA2_CH3_USART6_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 419 | ((REQUEST) == HAL_DMA2_CH3_USART7_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 420 | ((REQUEST) == HAL_DMA2_CH3_USART8_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 421 | ((REQUEST) == HAL_DMA2_CH4_DEFAULT) ||\ |
AnnaBridge | 171:3a7713b1edbc | 422 | ((REQUEST) == HAL_DMA2_CH4_TIM7_UP) ||\ |
AnnaBridge | 171:3a7713b1edbc | 423 | ((REQUEST) == HAL_DMA2_CH4_DAC_CH2) ||\ |
AnnaBridge | 171:3a7713b1edbc | 424 | ((REQUEST) == HAL_DMA2_CH4_SPI1_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 425 | ((REQUEST) == HAL_DMA2_CH4_USART1_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 426 | ((REQUEST) == HAL_DMA2_CH4_USART2_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 427 | ((REQUEST) == HAL_DMA2_CH4_USART3_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 428 | ((REQUEST) == HAL_DMA2_CH4_USART4_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 429 | ((REQUEST) == HAL_DMA2_CH4_USART5_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 430 | ((REQUEST) == HAL_DMA2_CH4_USART6_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 431 | ((REQUEST) == HAL_DMA2_CH4_USART7_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 432 | ((REQUEST) == HAL_DMA2_CH4_USART8_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 433 | ((REQUEST) == HAL_DMA2_CH5_DEFAULT) ||\ |
AnnaBridge | 171:3a7713b1edbc | 434 | ((REQUEST) == HAL_DMA2_CH5_ADC) ||\ |
AnnaBridge | 171:3a7713b1edbc | 435 | ((REQUEST) == HAL_DMA2_CH5_USART1_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 436 | ((REQUEST) == HAL_DMA2_CH5_USART2_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 437 | ((REQUEST) == HAL_DMA2_CH5_USART3_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 438 | ((REQUEST) == HAL_DMA2_CH5_USART4_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 439 | ((REQUEST) == HAL_DMA2_CH5_USART5_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 440 | ((REQUEST) == HAL_DMA2_CH5_USART6_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 441 | ((REQUEST) == HAL_DMA2_CH5_USART7_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 442 | ((REQUEST) == HAL_DMA2_CH5_USART8_TX )) |
AnnaBridge | 171:3a7713b1edbc | 443 | #endif /* STM32F091xC || STM32F098xx */ |
AnnaBridge | 171:3a7713b1edbc | 444 | |
AnnaBridge | 171:3a7713b1edbc | 445 | #if defined(STM32F030xC) |
AnnaBridge | 171:3a7713b1edbc | 446 | #define IS_HAL_DMA1_REMAP(REQUEST) (((REQUEST) == HAL_DMA1_CH1_DEFAULT) ||\ |
AnnaBridge | 171:3a7713b1edbc | 447 | ((REQUEST) == HAL_DMA1_CH1_ADC) ||\ |
AnnaBridge | 171:3a7713b1edbc | 448 | ((REQUEST) == HAL_DMA1_CH1_TIM17_CH1) ||\ |
AnnaBridge | 171:3a7713b1edbc | 449 | ((REQUEST) == HAL_DMA1_CH1_TIM17_UP) ||\ |
AnnaBridge | 171:3a7713b1edbc | 450 | ((REQUEST) == HAL_DMA1_CH1_USART1_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 451 | ((REQUEST) == HAL_DMA1_CH1_USART2_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 452 | ((REQUEST) == HAL_DMA1_CH1_USART3_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 453 | ((REQUEST) == HAL_DMA1_CH1_USART4_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 454 | ((REQUEST) == HAL_DMA1_CH1_USART5_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 455 | ((REQUEST) == HAL_DMA1_CH1_USART6_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 456 | ((REQUEST) == HAL_DMA1_CH2_DEFAULT) ||\ |
AnnaBridge | 171:3a7713b1edbc | 457 | ((REQUEST) == HAL_DMA1_CH2_ADC) ||\ |
AnnaBridge | 171:3a7713b1edbc | 458 | ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 459 | ((REQUEST) == HAL_DMA1_CH2_SPI1_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 460 | ((REQUEST) == HAL_DMA1_CH2_TIM1_CH1) ||\ |
AnnaBridge | 171:3a7713b1edbc | 461 | ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 462 | ((REQUEST) == HAL_DMA1_CH2_TIM17_CH1) ||\ |
AnnaBridge | 171:3a7713b1edbc | 463 | ((REQUEST) == HAL_DMA1_CH2_TIM17_UP) ||\ |
AnnaBridge | 171:3a7713b1edbc | 464 | ((REQUEST) == HAL_DMA1_CH2_USART1_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 465 | ((REQUEST) == HAL_DMA1_CH2_USART2_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 466 | ((REQUEST) == HAL_DMA1_CH2_USART3_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 467 | ((REQUEST) == HAL_DMA1_CH2_USART4_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 468 | ((REQUEST) == HAL_DMA1_CH2_USART5_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 469 | ((REQUEST) == HAL_DMA1_CH2_USART6_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 470 | ((REQUEST) == HAL_DMA1_CH3_DEFAULT) ||\ |
AnnaBridge | 171:3a7713b1edbc | 471 | ((REQUEST) == HAL_DMA1_CH3_TIM6_UP) ||\ |
AnnaBridge | 171:3a7713b1edbc | 472 | ((REQUEST) == HAL_DMA1_CH3_I2C1_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 473 | ((REQUEST) == HAL_DMA1_CH3_SPI1_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 474 | ((REQUEST) == HAL_DMA1_CH3_TIM1_CH2) ||\ |
AnnaBridge | 171:3a7713b1edbc | 475 | ((REQUEST) == HAL_DMA1_CH3_TIM16_CH1) ||\ |
AnnaBridge | 171:3a7713b1edbc | 476 | ((REQUEST) == HAL_DMA1_CH3_TIM16_UP) ||\ |
AnnaBridge | 171:3a7713b1edbc | 477 | ((REQUEST) == HAL_DMA1_CH3_USART1_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 478 | ((REQUEST) == HAL_DMA1_CH3_USART2_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 479 | ((REQUEST) == HAL_DMA1_CH3_USART3_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 480 | ((REQUEST) == HAL_DMA1_CH3_USART4_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 481 | ((REQUEST) == HAL_DMA1_CH3_USART5_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 482 | ((REQUEST) == HAL_DMA1_CH3_USART6_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 483 | ((REQUEST) == HAL_DMA1_CH4_DEFAULT) ||\ |
AnnaBridge | 171:3a7713b1edbc | 484 | ((REQUEST) == HAL_DMA1_CH4_TIM7_UP) ||\ |
AnnaBridge | 171:3a7713b1edbc | 485 | ((REQUEST) == HAL_DMA1_CH4_I2C2_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 486 | ((REQUEST) == HAL_DMA1_CH4_SPI2_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 487 | ((REQUEST) == HAL_DMA1_CH4_TIM3_CH1) ||\ |
AnnaBridge | 171:3a7713b1edbc | 488 | ((REQUEST) == HAL_DMA1_CH4_TIM3_TRIG) ||\ |
AnnaBridge | 171:3a7713b1edbc | 489 | ((REQUEST) == HAL_DMA1_CH4_TIM16_CH1) ||\ |
AnnaBridge | 171:3a7713b1edbc | 490 | ((REQUEST) == HAL_DMA1_CH4_TIM16_UP) ||\ |
AnnaBridge | 171:3a7713b1edbc | 491 | ((REQUEST) == HAL_DMA1_CH4_USART1_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 492 | ((REQUEST) == HAL_DMA1_CH4_USART2_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 493 | ((REQUEST) == HAL_DMA1_CH4_USART3_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 494 | ((REQUEST) == HAL_DMA1_CH4_USART4_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 495 | ((REQUEST) == HAL_DMA1_CH4_USART5_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 496 | ((REQUEST) == HAL_DMA1_CH4_USART6_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 497 | ((REQUEST) == HAL_DMA1_CH5_DEFAULT) ||\ |
AnnaBridge | 171:3a7713b1edbc | 498 | ((REQUEST) == HAL_DMA1_CH5_I2C2_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 499 | ((REQUEST) == HAL_DMA1_CH5_SPI2_TX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 500 | ((REQUEST) == HAL_DMA1_CH5_TIM1_CH3) ||\ |
AnnaBridge | 171:3a7713b1edbc | 501 | ((REQUEST) == HAL_DMA1_CH5_USART1_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 502 | ((REQUEST) == HAL_DMA1_CH5_USART2_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 503 | ((REQUEST) == HAL_DMA1_CH5_USART3_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 504 | ((REQUEST) == HAL_DMA1_CH5_USART4_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 505 | ((REQUEST) == HAL_DMA1_CH5_USART5_RX) ||\ |
AnnaBridge | 171:3a7713b1edbc | 506 | ((REQUEST) == HAL_DMA1_CH5_USART6_RX)) |
AnnaBridge | 171:3a7713b1edbc | 507 | #endif /* STM32F030xC */ |
AnnaBridge | 171:3a7713b1edbc | 508 | |
AnnaBridge | 171:3a7713b1edbc | 509 | /** |
AnnaBridge | 171:3a7713b1edbc | 510 | * @} |
AnnaBridge | 171:3a7713b1edbc | 511 | */ |
AnnaBridge | 171:3a7713b1edbc | 512 | #endif /* STM32F091xC || STM32F098xx || STM32F030xC */ |
AnnaBridge | 171:3a7713b1edbc | 513 | |
AnnaBridge | 171:3a7713b1edbc | 514 | /* Exported macros -----------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 515 | |
AnnaBridge | 171:3a7713b1edbc | 516 | /** @defgroup DMAEx_Exported_Macros DMAEx Exported Macros |
AnnaBridge | 171:3a7713b1edbc | 517 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 518 | */ |
AnnaBridge | 171:3a7713b1edbc | 519 | /* Interrupt & Flag management */ |
AnnaBridge | 171:3a7713b1edbc | 520 | |
AnnaBridge | 171:3a7713b1edbc | 521 | #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) |
AnnaBridge | 171:3a7713b1edbc | 522 | /** |
AnnaBridge | 171:3a7713b1edbc | 523 | * @brief Returns the current DMA Channel transfer complete flag. |
AnnaBridge | 171:3a7713b1edbc | 524 | * @param __HANDLE__ DMA handle |
AnnaBridge | 171:3a7713b1edbc | 525 | * @retval The specified transfer complete flag index. |
AnnaBridge | 171:3a7713b1edbc | 526 | */ |
AnnaBridge | 171:3a7713b1edbc | 527 | #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ |
AnnaBridge | 171:3a7713b1edbc | 528 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ |
AnnaBridge | 171:3a7713b1edbc | 529 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ |
AnnaBridge | 171:3a7713b1edbc | 530 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ |
AnnaBridge | 171:3a7713b1edbc | 531 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ |
AnnaBridge | 171:3a7713b1edbc | 532 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ |
AnnaBridge | 171:3a7713b1edbc | 533 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ |
AnnaBridge | 171:3a7713b1edbc | 534 | DMA_FLAG_TC7) |
AnnaBridge | 171:3a7713b1edbc | 535 | |
AnnaBridge | 171:3a7713b1edbc | 536 | /** |
AnnaBridge | 171:3a7713b1edbc | 537 | * @brief Returns the current DMA Channel half transfer complete flag. |
AnnaBridge | 171:3a7713b1edbc | 538 | * @param __HANDLE__ DMA handle |
AnnaBridge | 171:3a7713b1edbc | 539 | * @retval The specified half transfer complete flag index. |
AnnaBridge | 171:3a7713b1edbc | 540 | */ |
AnnaBridge | 171:3a7713b1edbc | 541 | #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ |
AnnaBridge | 171:3a7713b1edbc | 542 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ |
AnnaBridge | 171:3a7713b1edbc | 543 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ |
AnnaBridge | 171:3a7713b1edbc | 544 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ |
AnnaBridge | 171:3a7713b1edbc | 545 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ |
AnnaBridge | 171:3a7713b1edbc | 546 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ |
AnnaBridge | 171:3a7713b1edbc | 547 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ |
AnnaBridge | 171:3a7713b1edbc | 548 | DMA_FLAG_HT7) |
AnnaBridge | 171:3a7713b1edbc | 549 | |
AnnaBridge | 171:3a7713b1edbc | 550 | /** |
AnnaBridge | 171:3a7713b1edbc | 551 | * @brief Returns the current DMA Channel transfer error flag. |
AnnaBridge | 171:3a7713b1edbc | 552 | * @param __HANDLE__ DMA handle |
AnnaBridge | 171:3a7713b1edbc | 553 | * @retval The specified transfer error flag index. |
AnnaBridge | 171:3a7713b1edbc | 554 | */ |
AnnaBridge | 171:3a7713b1edbc | 555 | #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ |
AnnaBridge | 171:3a7713b1edbc | 556 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ |
AnnaBridge | 171:3a7713b1edbc | 557 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ |
AnnaBridge | 171:3a7713b1edbc | 558 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ |
AnnaBridge | 171:3a7713b1edbc | 559 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ |
AnnaBridge | 171:3a7713b1edbc | 560 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ |
AnnaBridge | 171:3a7713b1edbc | 561 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ |
AnnaBridge | 171:3a7713b1edbc | 562 | DMA_FLAG_TE7) |
AnnaBridge | 171:3a7713b1edbc | 563 | |
AnnaBridge | 171:3a7713b1edbc | 564 | /** |
AnnaBridge | 171:3a7713b1edbc | 565 | * @brief Return the current DMA Channel Global interrupt flag. |
AnnaBridge | 171:3a7713b1edbc | 566 | * @param __HANDLE__ DMA handle |
AnnaBridge | 171:3a7713b1edbc | 567 | * @retval The specified transfer error flag index. |
AnnaBridge | 171:3a7713b1edbc | 568 | */ |
AnnaBridge | 171:3a7713b1edbc | 569 | #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ |
AnnaBridge | 171:3a7713b1edbc | 570 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\ |
AnnaBridge | 171:3a7713b1edbc | 571 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\ |
AnnaBridge | 171:3a7713b1edbc | 572 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\ |
AnnaBridge | 171:3a7713b1edbc | 573 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\ |
AnnaBridge | 171:3a7713b1edbc | 574 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\ |
AnnaBridge | 171:3a7713b1edbc | 575 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\ |
AnnaBridge | 171:3a7713b1edbc | 576 | DMA_FLAG_GL7) |
AnnaBridge | 171:3a7713b1edbc | 577 | |
AnnaBridge | 171:3a7713b1edbc | 578 | /** |
AnnaBridge | 171:3a7713b1edbc | 579 | * @brief Get the DMA Channel pending flags. |
AnnaBridge | 171:3a7713b1edbc | 580 | * @param __HANDLE__ DMA handle |
AnnaBridge | 171:3a7713b1edbc | 581 | * @param __FLAG__ Get the specified flag. |
AnnaBridge | 171:3a7713b1edbc | 582 | * This parameter can be any combination of the following values: |
AnnaBridge | 171:3a7713b1edbc | 583 | * @arg DMA_FLAG_TCx: Transfer complete flag |
AnnaBridge | 171:3a7713b1edbc | 584 | * @arg DMA_FLAG_HTx: Half transfer complete flag |
AnnaBridge | 171:3a7713b1edbc | 585 | * @arg DMA_FLAG_TEx: Transfer error flag |
AnnaBridge | 171:3a7713b1edbc | 586 | * Where x can be 1_7 to select the DMA Channel flag. |
AnnaBridge | 171:3a7713b1edbc | 587 | * @retval The state of FLAG (SET or RESET). |
AnnaBridge | 171:3a7713b1edbc | 588 | */ |
AnnaBridge | 171:3a7713b1edbc | 589 | |
AnnaBridge | 171:3a7713b1edbc | 590 | #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) |
AnnaBridge | 171:3a7713b1edbc | 591 | |
AnnaBridge | 171:3a7713b1edbc | 592 | /** |
AnnaBridge | 171:3a7713b1edbc | 593 | * @brief Clears the DMA Channel pending flags. |
AnnaBridge | 171:3a7713b1edbc | 594 | * @param __HANDLE__ DMA handle |
AnnaBridge | 171:3a7713b1edbc | 595 | * @param __FLAG__ specifies the flag to clear. |
AnnaBridge | 171:3a7713b1edbc | 596 | * This parameter can be any combination of the following values: |
AnnaBridge | 171:3a7713b1edbc | 597 | * @arg DMA_FLAG_TCx: Transfer complete flag |
AnnaBridge | 171:3a7713b1edbc | 598 | * @arg DMA_FLAG_HTx: Half transfer complete flag |
AnnaBridge | 171:3a7713b1edbc | 599 | * @arg DMA_FLAG_TEx: Transfer error flag |
AnnaBridge | 171:3a7713b1edbc | 600 | * Where x can be 1_7 to select the DMA Channel flag. |
AnnaBridge | 171:3a7713b1edbc | 601 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 602 | */ |
AnnaBridge | 171:3a7713b1edbc | 603 | #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) |
AnnaBridge | 171:3a7713b1edbc | 604 | |
AnnaBridge | 171:3a7713b1edbc | 605 | #elif defined(STM32F091xC) || defined(STM32F098xx) |
AnnaBridge | 171:3a7713b1edbc | 606 | /** |
AnnaBridge | 171:3a7713b1edbc | 607 | * @brief Returns the current DMA Channel transfer complete flag. |
AnnaBridge | 171:3a7713b1edbc | 608 | * @param __HANDLE__ DMA handle |
AnnaBridge | 171:3a7713b1edbc | 609 | * @retval The specified transfer complete flag index. |
AnnaBridge | 171:3a7713b1edbc | 610 | */ |
AnnaBridge | 171:3a7713b1edbc | 611 | #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ |
AnnaBridge | 171:3a7713b1edbc | 612 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ |
AnnaBridge | 171:3a7713b1edbc | 613 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ |
AnnaBridge | 171:3a7713b1edbc | 614 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ |
AnnaBridge | 171:3a7713b1edbc | 615 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ |
AnnaBridge | 171:3a7713b1edbc | 616 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ |
AnnaBridge | 171:3a7713b1edbc | 617 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ |
AnnaBridge | 171:3a7713b1edbc | 618 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\ |
AnnaBridge | 171:3a7713b1edbc | 619 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ |
AnnaBridge | 171:3a7713b1edbc | 620 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ |
AnnaBridge | 171:3a7713b1edbc | 621 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ |
AnnaBridge | 171:3a7713b1edbc | 622 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ |
AnnaBridge | 171:3a7713b1edbc | 623 | DMA_FLAG_TC5) |
AnnaBridge | 171:3a7713b1edbc | 624 | |
AnnaBridge | 171:3a7713b1edbc | 625 | /** |
AnnaBridge | 171:3a7713b1edbc | 626 | * @brief Returns the current DMA Channel half transfer complete flag. |
AnnaBridge | 171:3a7713b1edbc | 627 | * @param __HANDLE__ DMA handle |
AnnaBridge | 171:3a7713b1edbc | 628 | * @retval The specified half transfer complete flag index. |
AnnaBridge | 171:3a7713b1edbc | 629 | */ |
AnnaBridge | 171:3a7713b1edbc | 630 | #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ |
AnnaBridge | 171:3a7713b1edbc | 631 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ |
AnnaBridge | 171:3a7713b1edbc | 632 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ |
AnnaBridge | 171:3a7713b1edbc | 633 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ |
AnnaBridge | 171:3a7713b1edbc | 634 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ |
AnnaBridge | 171:3a7713b1edbc | 635 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ |
AnnaBridge | 171:3a7713b1edbc | 636 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ |
AnnaBridge | 171:3a7713b1edbc | 637 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\ |
AnnaBridge | 171:3a7713b1edbc | 638 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ |
AnnaBridge | 171:3a7713b1edbc | 639 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ |
AnnaBridge | 171:3a7713b1edbc | 640 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ |
AnnaBridge | 171:3a7713b1edbc | 641 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ |
AnnaBridge | 171:3a7713b1edbc | 642 | DMA_FLAG_HT5) |
AnnaBridge | 171:3a7713b1edbc | 643 | |
AnnaBridge | 171:3a7713b1edbc | 644 | /** |
AnnaBridge | 171:3a7713b1edbc | 645 | * @brief Returns the current DMA Channel transfer error flag. |
AnnaBridge | 171:3a7713b1edbc | 646 | * @param __HANDLE__ DMA handle |
AnnaBridge | 171:3a7713b1edbc | 647 | * @retval The specified transfer error flag index. |
AnnaBridge | 171:3a7713b1edbc | 648 | */ |
AnnaBridge | 171:3a7713b1edbc | 649 | #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ |
AnnaBridge | 171:3a7713b1edbc | 650 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ |
AnnaBridge | 171:3a7713b1edbc | 651 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ |
AnnaBridge | 171:3a7713b1edbc | 652 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ |
AnnaBridge | 171:3a7713b1edbc | 653 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ |
AnnaBridge | 171:3a7713b1edbc | 654 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ |
AnnaBridge | 171:3a7713b1edbc | 655 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ |
AnnaBridge | 171:3a7713b1edbc | 656 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\ |
AnnaBridge | 171:3a7713b1edbc | 657 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ |
AnnaBridge | 171:3a7713b1edbc | 658 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ |
AnnaBridge | 171:3a7713b1edbc | 659 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ |
AnnaBridge | 171:3a7713b1edbc | 660 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ |
AnnaBridge | 171:3a7713b1edbc | 661 | DMA_FLAG_TE5) |
AnnaBridge | 171:3a7713b1edbc | 662 | |
AnnaBridge | 171:3a7713b1edbc | 663 | /** |
AnnaBridge | 171:3a7713b1edbc | 664 | * @brief Return the current DMA Channel Global interrupt flag. |
AnnaBridge | 171:3a7713b1edbc | 665 | * @param __HANDLE__ DMA handle |
AnnaBridge | 171:3a7713b1edbc | 666 | * @retval The specified transfer error flag index. |
AnnaBridge | 171:3a7713b1edbc | 667 | */ |
AnnaBridge | 171:3a7713b1edbc | 668 | #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ |
AnnaBridge | 171:3a7713b1edbc | 669 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\ |
AnnaBridge | 171:3a7713b1edbc | 670 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\ |
AnnaBridge | 171:3a7713b1edbc | 671 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\ |
AnnaBridge | 171:3a7713b1edbc | 672 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\ |
AnnaBridge | 171:3a7713b1edbc | 673 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\ |
AnnaBridge | 171:3a7713b1edbc | 674 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\ |
AnnaBridge | 171:3a7713b1edbc | 675 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 :\ |
AnnaBridge | 171:3a7713b1edbc | 676 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 :\ |
AnnaBridge | 171:3a7713b1edbc | 677 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GL2 :\ |
AnnaBridge | 171:3a7713b1edbc | 678 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GL3 :\ |
AnnaBridge | 171:3a7713b1edbc | 679 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GL4 :\ |
AnnaBridge | 171:3a7713b1edbc | 680 | DMA_FLAG_GL5) |
AnnaBridge | 171:3a7713b1edbc | 681 | |
AnnaBridge | 171:3a7713b1edbc | 682 | /** |
AnnaBridge | 171:3a7713b1edbc | 683 | * @brief Get the DMA Channel pending flags. |
AnnaBridge | 171:3a7713b1edbc | 684 | * @param __HANDLE__ DMA handle |
AnnaBridge | 171:3a7713b1edbc | 685 | * @param __FLAG__ Get the specified flag. |
AnnaBridge | 171:3a7713b1edbc | 686 | * This parameter can be any combination of the following values: |
AnnaBridge | 171:3a7713b1edbc | 687 | * @arg DMA_FLAG_TCx: Transfer complete flag |
AnnaBridge | 171:3a7713b1edbc | 688 | * @arg DMA_FLAG_HTx: Half transfer complete flag |
AnnaBridge | 171:3a7713b1edbc | 689 | * @arg DMA_FLAG_TEx: Transfer error flag |
AnnaBridge | 171:3a7713b1edbc | 690 | * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag. |
AnnaBridge | 171:3a7713b1edbc | 691 | * @retval The state of FLAG (SET or RESET). |
AnnaBridge | 171:3a7713b1edbc | 692 | */ |
AnnaBridge | 171:3a7713b1edbc | 693 | |
AnnaBridge | 171:3a7713b1edbc | 694 | #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ |
AnnaBridge | 171:3a7713b1edbc | 695 | (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\ |
AnnaBridge | 171:3a7713b1edbc | 696 | (DMA1->ISR & (__FLAG__))) |
AnnaBridge | 171:3a7713b1edbc | 697 | |
AnnaBridge | 171:3a7713b1edbc | 698 | /** |
AnnaBridge | 171:3a7713b1edbc | 699 | * @brief Clears the DMA Channel pending flags. |
AnnaBridge | 171:3a7713b1edbc | 700 | * @param __HANDLE__ DMA handle |
AnnaBridge | 171:3a7713b1edbc | 701 | * @param __FLAG__ specifies the flag to clear. |
AnnaBridge | 171:3a7713b1edbc | 702 | * This parameter can be any combination of the following values: |
AnnaBridge | 171:3a7713b1edbc | 703 | * @arg DMA_FLAG_TCx: Transfer complete flag |
AnnaBridge | 171:3a7713b1edbc | 704 | * @arg DMA_FLAG_HTx: Half transfer complete flag |
AnnaBridge | 171:3a7713b1edbc | 705 | * @arg DMA_FLAG_TEx: Transfer error flag |
AnnaBridge | 171:3a7713b1edbc | 706 | * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag. |
AnnaBridge | 171:3a7713b1edbc | 707 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 708 | */ |
AnnaBridge | 171:3a7713b1edbc | 709 | #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ |
AnnaBridge | 171:3a7713b1edbc | 710 | (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\ |
AnnaBridge | 171:3a7713b1edbc | 711 | (DMA1->IFCR = (__FLAG__))) |
AnnaBridge | 171:3a7713b1edbc | 712 | |
AnnaBridge | 171:3a7713b1edbc | 713 | #else /* STM32F030x8_STM32F030xC_STM32F031x6_STM32F038xx_STM32F051x8_STM32F058xx_STM32F070x6_STM32F070xB Product devices */ |
AnnaBridge | 171:3a7713b1edbc | 714 | /** |
AnnaBridge | 171:3a7713b1edbc | 715 | * @brief Returns the current DMA Channel transfer complete flag. |
AnnaBridge | 171:3a7713b1edbc | 716 | * @param __HANDLE__ DMA handle |
AnnaBridge | 171:3a7713b1edbc | 717 | * @retval The specified transfer complete flag index. |
AnnaBridge | 171:3a7713b1edbc | 718 | */ |
AnnaBridge | 171:3a7713b1edbc | 719 | #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ |
AnnaBridge | 171:3a7713b1edbc | 720 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ |
AnnaBridge | 171:3a7713b1edbc | 721 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ |
AnnaBridge | 171:3a7713b1edbc | 722 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ |
AnnaBridge | 171:3a7713b1edbc | 723 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ |
AnnaBridge | 171:3a7713b1edbc | 724 | DMA_FLAG_TC5) |
AnnaBridge | 171:3a7713b1edbc | 725 | |
AnnaBridge | 171:3a7713b1edbc | 726 | /** |
AnnaBridge | 171:3a7713b1edbc | 727 | * @brief Returns the current DMA Channel half transfer complete flag. |
AnnaBridge | 171:3a7713b1edbc | 728 | * @param __HANDLE__ DMA handle |
AnnaBridge | 171:3a7713b1edbc | 729 | * @retval The specified half transfer complete flag index. |
AnnaBridge | 171:3a7713b1edbc | 730 | */ |
AnnaBridge | 171:3a7713b1edbc | 731 | #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ |
AnnaBridge | 171:3a7713b1edbc | 732 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ |
AnnaBridge | 171:3a7713b1edbc | 733 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ |
AnnaBridge | 171:3a7713b1edbc | 734 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ |
AnnaBridge | 171:3a7713b1edbc | 735 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ |
AnnaBridge | 171:3a7713b1edbc | 736 | DMA_FLAG_HT5) |
AnnaBridge | 171:3a7713b1edbc | 737 | |
AnnaBridge | 171:3a7713b1edbc | 738 | /** |
AnnaBridge | 171:3a7713b1edbc | 739 | * @brief Returns the current DMA Channel transfer error flag. |
AnnaBridge | 171:3a7713b1edbc | 740 | * @param __HANDLE__ DMA handle |
AnnaBridge | 171:3a7713b1edbc | 741 | * @retval The specified transfer error flag index. |
AnnaBridge | 171:3a7713b1edbc | 742 | */ |
AnnaBridge | 171:3a7713b1edbc | 743 | #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ |
AnnaBridge | 171:3a7713b1edbc | 744 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ |
AnnaBridge | 171:3a7713b1edbc | 745 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ |
AnnaBridge | 171:3a7713b1edbc | 746 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ |
AnnaBridge | 171:3a7713b1edbc | 747 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ |
AnnaBridge | 171:3a7713b1edbc | 748 | DMA_FLAG_TE5) |
AnnaBridge | 171:3a7713b1edbc | 749 | |
AnnaBridge | 171:3a7713b1edbc | 750 | /** |
AnnaBridge | 171:3a7713b1edbc | 751 | * @brief Return the current DMA Channel Global interrupt flag. |
AnnaBridge | 171:3a7713b1edbc | 752 | * @param __HANDLE__ DMA handle |
AnnaBridge | 171:3a7713b1edbc | 753 | * @retval The specified transfer error flag index. |
AnnaBridge | 171:3a7713b1edbc | 754 | */ |
AnnaBridge | 171:3a7713b1edbc | 755 | #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ |
AnnaBridge | 171:3a7713b1edbc | 756 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\ |
AnnaBridge | 171:3a7713b1edbc | 757 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\ |
AnnaBridge | 171:3a7713b1edbc | 758 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\ |
AnnaBridge | 171:3a7713b1edbc | 759 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\ |
AnnaBridge | 171:3a7713b1edbc | 760 | DMA_FLAG_GL5) |
AnnaBridge | 171:3a7713b1edbc | 761 | |
AnnaBridge | 171:3a7713b1edbc | 762 | /** |
AnnaBridge | 171:3a7713b1edbc | 763 | * @brief Get the DMA Channel pending flags. |
AnnaBridge | 171:3a7713b1edbc | 764 | * @param __HANDLE__ DMA handle |
AnnaBridge | 171:3a7713b1edbc | 765 | * @param __FLAG__ Get the specified flag. |
AnnaBridge | 171:3a7713b1edbc | 766 | * This parameter can be any combination of the following values: |
AnnaBridge | 171:3a7713b1edbc | 767 | * @arg DMA_FLAG_TCx: Transfer complete flag |
AnnaBridge | 171:3a7713b1edbc | 768 | * @arg DMA_FLAG_HTx: Half transfer complete flag |
AnnaBridge | 171:3a7713b1edbc | 769 | * @arg DMA_FLAG_TEx: Transfer error flag |
AnnaBridge | 171:3a7713b1edbc | 770 | * Where x can be 1_5 to select the DMA Channel flag. |
AnnaBridge | 171:3a7713b1edbc | 771 | * @retval The state of FLAG (SET or RESET). |
AnnaBridge | 171:3a7713b1edbc | 772 | */ |
AnnaBridge | 171:3a7713b1edbc | 773 | |
AnnaBridge | 171:3a7713b1edbc | 774 | #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) |
AnnaBridge | 171:3a7713b1edbc | 775 | |
AnnaBridge | 171:3a7713b1edbc | 776 | /** |
AnnaBridge | 171:3a7713b1edbc | 777 | * @brief Clears the DMA Channel pending flags. |
AnnaBridge | 171:3a7713b1edbc | 778 | * @param __HANDLE__ DMA handle |
AnnaBridge | 171:3a7713b1edbc | 779 | * @param __FLAG__ specifies the flag to clear. |
AnnaBridge | 171:3a7713b1edbc | 780 | * This parameter can be any combination of the following values: |
AnnaBridge | 171:3a7713b1edbc | 781 | * @arg DMA_FLAG_TCx: Transfer complete flag |
AnnaBridge | 171:3a7713b1edbc | 782 | * @arg DMA_FLAG_HTx: Half transfer complete flag |
AnnaBridge | 171:3a7713b1edbc | 783 | * @arg DMA_FLAG_TEx: Transfer error flag |
AnnaBridge | 171:3a7713b1edbc | 784 | * Where x can be 1_5 to select the DMA Channel flag. |
AnnaBridge | 171:3a7713b1edbc | 785 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 786 | */ |
AnnaBridge | 171:3a7713b1edbc | 787 | #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) |
AnnaBridge | 171:3a7713b1edbc | 788 | |
AnnaBridge | 171:3a7713b1edbc | 789 | #endif |
AnnaBridge | 171:3a7713b1edbc | 790 | |
AnnaBridge | 171:3a7713b1edbc | 791 | |
AnnaBridge | 171:3a7713b1edbc | 792 | #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) |
AnnaBridge | 171:3a7713b1edbc | 793 | #define __HAL_DMA1_REMAP(__REQUEST__) \ |
AnnaBridge | 171:3a7713b1edbc | 794 | do { assert_param(IS_HAL_DMA1_REMAP(__REQUEST__)); \ |
AnnaBridge | 171:3a7713b1edbc | 795 | DMA1->CSELR &= ~(0x0FU << (uint32_t)(((__REQUEST__) >> 28U) * 4U)); \ |
AnnaBridge | 171:3a7713b1edbc | 796 | DMA1->CSELR |= (uint32_t)((__REQUEST__) & 0x0FFFFFFFU); \ |
AnnaBridge | 171:3a7713b1edbc | 797 | }while(0) |
AnnaBridge | 171:3a7713b1edbc | 798 | |
AnnaBridge | 171:3a7713b1edbc | 799 | #if defined(STM32F091xC) || defined(STM32F098xx) |
AnnaBridge | 171:3a7713b1edbc | 800 | #define __HAL_DMA2_REMAP(__REQUEST__) \ |
AnnaBridge | 171:3a7713b1edbc | 801 | do { assert_param(IS_HAL_DMA2_REMAP(__REQUEST__)); \ |
AnnaBridge | 171:3a7713b1edbc | 802 | DMA2->CSELR &= ~(0x0FU << (uint32_t)(((__REQUEST__) >> 28U) * 4U)); \ |
AnnaBridge | 171:3a7713b1edbc | 803 | DMA2->CSELR |= (uint32_t)((__REQUEST__) & 0x0FFFFFFFU); \ |
AnnaBridge | 171:3a7713b1edbc | 804 | }while(0) |
AnnaBridge | 171:3a7713b1edbc | 805 | #endif /* STM32F091xC || STM32F098xx */ |
AnnaBridge | 171:3a7713b1edbc | 806 | |
AnnaBridge | 171:3a7713b1edbc | 807 | #endif /* STM32F091xC || STM32F098xx || STM32F030xC */ |
AnnaBridge | 171:3a7713b1edbc | 808 | |
AnnaBridge | 171:3a7713b1edbc | 809 | /** |
AnnaBridge | 171:3a7713b1edbc | 810 | * @} |
AnnaBridge | 171:3a7713b1edbc | 811 | */ |
AnnaBridge | 171:3a7713b1edbc | 812 | |
AnnaBridge | 171:3a7713b1edbc | 813 | /** |
AnnaBridge | 171:3a7713b1edbc | 814 | * @} |
AnnaBridge | 171:3a7713b1edbc | 815 | */ |
AnnaBridge | 171:3a7713b1edbc | 816 | |
AnnaBridge | 171:3a7713b1edbc | 817 | /** |
AnnaBridge | 171:3a7713b1edbc | 818 | * @} |
AnnaBridge | 171:3a7713b1edbc | 819 | */ |
AnnaBridge | 171:3a7713b1edbc | 820 | |
AnnaBridge | 171:3a7713b1edbc | 821 | #ifdef __cplusplus |
AnnaBridge | 171:3a7713b1edbc | 822 | } |
AnnaBridge | 171:3a7713b1edbc | 823 | #endif |
AnnaBridge | 171:3a7713b1edbc | 824 | |
AnnaBridge | 171:3a7713b1edbc | 825 | #endif /* __STM32F0xx_HAL_DMA_EX_H */ |
AnnaBridge | 171:3a7713b1edbc | 826 | |
AnnaBridge | 171:3a7713b1edbc | 827 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |