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TARGET_SAMR21G18A/TOOLCHAIN_ARM_STD/comp_sysctrl.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
mbed library. Release version 164
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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AnnaBridge | 171:3a7713b1edbc | 1 | /** |
AnnaBridge | 171:3a7713b1edbc | 2 | * \file |
AnnaBridge | 171:3a7713b1edbc | 3 | * |
AnnaBridge | 171:3a7713b1edbc | 4 | * \brief Component description for SYSCTRL |
AnnaBridge | 171:3a7713b1edbc | 5 | * |
AnnaBridge | 171:3a7713b1edbc | 6 | * Copyright (c) 2015 Atmel Corporation. All rights reserved. |
AnnaBridge | 171:3a7713b1edbc | 7 | * |
AnnaBridge | 171:3a7713b1edbc | 8 | * \asf_license_start |
AnnaBridge | 171:3a7713b1edbc | 9 | * |
AnnaBridge | 171:3a7713b1edbc | 10 | * \page License |
AnnaBridge | 171:3a7713b1edbc | 11 | * |
AnnaBridge | 171:3a7713b1edbc | 12 | * Redistribution and use in source and binary forms, with or without |
AnnaBridge | 171:3a7713b1edbc | 13 | * modification, are permitted provided that the following conditions are met: |
AnnaBridge | 171:3a7713b1edbc | 14 | * |
AnnaBridge | 171:3a7713b1edbc | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer. |
AnnaBridge | 171:3a7713b1edbc | 17 | * |
AnnaBridge | 171:3a7713b1edbc | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 19 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 171:3a7713b1edbc | 20 | * and/or other materials provided with the distribution. |
AnnaBridge | 171:3a7713b1edbc | 21 | * |
AnnaBridge | 171:3a7713b1edbc | 22 | * 3. The name of Atmel may not be used to endorse or promote products derived |
AnnaBridge | 171:3a7713b1edbc | 23 | * from this software without specific prior written permission. |
AnnaBridge | 171:3a7713b1edbc | 24 | * |
AnnaBridge | 171:3a7713b1edbc | 25 | * 4. This software may only be redistributed and used in connection with an |
AnnaBridge | 171:3a7713b1edbc | 26 | * Atmel microcontroller product. |
AnnaBridge | 171:3a7713b1edbc | 27 | * |
AnnaBridge | 171:3a7713b1edbc | 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED |
AnnaBridge | 171:3a7713b1edbc | 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
AnnaBridge | 171:3a7713b1edbc | 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE |
AnnaBridge | 171:3a7713b1edbc | 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR |
AnnaBridge | 171:3a7713b1edbc | 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 171:3a7713b1edbc | 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
AnnaBridge | 171:3a7713b1edbc | 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
AnnaBridge | 171:3a7713b1edbc | 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
AnnaBridge | 171:3a7713b1edbc | 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
AnnaBridge | 171:3a7713b1edbc | 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
AnnaBridge | 171:3a7713b1edbc | 38 | * POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 171:3a7713b1edbc | 39 | * |
AnnaBridge | 171:3a7713b1edbc | 40 | * \asf_license_stop |
AnnaBridge | 171:3a7713b1edbc | 41 | * |
AnnaBridge | 171:3a7713b1edbc | 42 | */ |
AnnaBridge | 171:3a7713b1edbc | 43 | |
AnnaBridge | 171:3a7713b1edbc | 44 | #ifndef _SAMR21_SYSCTRL_COMPONENT_ |
AnnaBridge | 171:3a7713b1edbc | 45 | #define _SAMR21_SYSCTRL_COMPONENT_ |
AnnaBridge | 171:3a7713b1edbc | 46 | |
AnnaBridge | 171:3a7713b1edbc | 47 | /* ========================================================================== */ |
AnnaBridge | 171:3a7713b1edbc | 48 | /** SOFTWARE API DEFINITION FOR SYSCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 49 | /* ========================================================================== */ |
AnnaBridge | 171:3a7713b1edbc | 50 | /** \addtogroup SAMR21_SYSCTRL System Control */ |
AnnaBridge | 171:3a7713b1edbc | 51 | /*@{*/ |
AnnaBridge | 171:3a7713b1edbc | 52 | |
AnnaBridge | 171:3a7713b1edbc | 53 | #define SYSCTRL_U2100 |
AnnaBridge | 171:3a7713b1edbc | 54 | #define REV_SYSCTRL 0x201 |
AnnaBridge | 171:3a7713b1edbc | 55 | |
AnnaBridge | 171:3a7713b1edbc | 56 | /* -------- SYSCTRL_INTENCLR : (SYSCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */ |
AnnaBridge | 171:3a7713b1edbc | 57 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 58 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 59 | struct { |
AnnaBridge | 171:3a7713b1edbc | 60 | uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 61 | uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 62 | uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 63 | uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 64 | uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 65 | uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 66 | uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 67 | uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 68 | uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 69 | uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 70 | uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 71 | uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 72 | uint32_t :3; /*!< bit: 12..14 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 73 | uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 74 | uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 75 | uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 76 | uint32_t :14; /*!< bit: 18..31 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 77 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 78 | uint32_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 79 | } SYSCTRL_INTENCLR_Type; |
AnnaBridge | 171:3a7713b1edbc | 80 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 81 | |
AnnaBridge | 171:3a7713b1edbc | 82 | #define SYSCTRL_INTENCLR_OFFSET 0x00 /**< \brief (SYSCTRL_INTENCLR offset) Interrupt Enable Clear */ |
AnnaBridge | 171:3a7713b1edbc | 83 | #define SYSCTRL_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_INTENCLR reset_value) Interrupt Enable Clear */ |
AnnaBridge | 171:3a7713b1edbc | 84 | |
AnnaBridge | 171:3a7713b1edbc | 85 | #define SYSCTRL_INTENCLR_XOSCRDY_Pos 0 /**< \brief (SYSCTRL_INTENCLR) XOSC Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 86 | #define SYSCTRL_INTENCLR_XOSCRDY (0x1ul << SYSCTRL_INTENCLR_XOSCRDY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 87 | #define SYSCTRL_INTENCLR_XOSC32KRDY_Pos 1 /**< \brief (SYSCTRL_INTENCLR) XOSC32K Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 88 | #define SYSCTRL_INTENCLR_XOSC32KRDY (0x1ul << SYSCTRL_INTENCLR_XOSC32KRDY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 89 | #define SYSCTRL_INTENCLR_OSC32KRDY_Pos 2 /**< \brief (SYSCTRL_INTENCLR) OSC32K Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 90 | #define SYSCTRL_INTENCLR_OSC32KRDY (0x1ul << SYSCTRL_INTENCLR_OSC32KRDY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 91 | #define SYSCTRL_INTENCLR_OSC8MRDY_Pos 3 /**< \brief (SYSCTRL_INTENCLR) OSC8M Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 92 | #define SYSCTRL_INTENCLR_OSC8MRDY (0x1ul << SYSCTRL_INTENCLR_OSC8MRDY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 93 | #define SYSCTRL_INTENCLR_DFLLRDY_Pos 4 /**< \brief (SYSCTRL_INTENCLR) DFLL Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 94 | #define SYSCTRL_INTENCLR_DFLLRDY (0x1ul << SYSCTRL_INTENCLR_DFLLRDY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 95 | #define SYSCTRL_INTENCLR_DFLLOOB_Pos 5 /**< \brief (SYSCTRL_INTENCLR) DFLL Out Of Bounds Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 96 | #define SYSCTRL_INTENCLR_DFLLOOB (0x1ul << SYSCTRL_INTENCLR_DFLLOOB_Pos) |
AnnaBridge | 171:3a7713b1edbc | 97 | #define SYSCTRL_INTENCLR_DFLLLCKF_Pos 6 /**< \brief (SYSCTRL_INTENCLR) DFLL Lock Fine Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 98 | #define SYSCTRL_INTENCLR_DFLLLCKF (0x1ul << SYSCTRL_INTENCLR_DFLLLCKF_Pos) |
AnnaBridge | 171:3a7713b1edbc | 99 | #define SYSCTRL_INTENCLR_DFLLLCKC_Pos 7 /**< \brief (SYSCTRL_INTENCLR) DFLL Lock Coarse Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 100 | #define SYSCTRL_INTENCLR_DFLLLCKC (0x1ul << SYSCTRL_INTENCLR_DFLLLCKC_Pos) |
AnnaBridge | 171:3a7713b1edbc | 101 | #define SYSCTRL_INTENCLR_DFLLRCS_Pos 8 /**< \brief (SYSCTRL_INTENCLR) DFLL Reference Clock Stopped Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 102 | #define SYSCTRL_INTENCLR_DFLLRCS (0x1ul << SYSCTRL_INTENCLR_DFLLRCS_Pos) |
AnnaBridge | 171:3a7713b1edbc | 103 | #define SYSCTRL_INTENCLR_BOD33RDY_Pos 9 /**< \brief (SYSCTRL_INTENCLR) BOD33 Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 104 | #define SYSCTRL_INTENCLR_BOD33RDY (0x1ul << SYSCTRL_INTENCLR_BOD33RDY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 105 | #define SYSCTRL_INTENCLR_BOD33DET_Pos 10 /**< \brief (SYSCTRL_INTENCLR) BOD33 Detection Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 106 | #define SYSCTRL_INTENCLR_BOD33DET (0x1ul << SYSCTRL_INTENCLR_BOD33DET_Pos) |
AnnaBridge | 171:3a7713b1edbc | 107 | #define SYSCTRL_INTENCLR_B33SRDY_Pos 11 /**< \brief (SYSCTRL_INTENCLR) BOD33 Synchronization Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 108 | #define SYSCTRL_INTENCLR_B33SRDY (0x1ul << SYSCTRL_INTENCLR_B33SRDY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 109 | #define SYSCTRL_INTENCLR_DPLLLCKR_Pos 15 /**< \brief (SYSCTRL_INTENCLR) DPLL Lock Rise Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 110 | #define SYSCTRL_INTENCLR_DPLLLCKR (0x1ul << SYSCTRL_INTENCLR_DPLLLCKR_Pos) |
AnnaBridge | 171:3a7713b1edbc | 111 | #define SYSCTRL_INTENCLR_DPLLLCKF_Pos 16 /**< \brief (SYSCTRL_INTENCLR) DPLL Lock Fall Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 112 | #define SYSCTRL_INTENCLR_DPLLLCKF (0x1ul << SYSCTRL_INTENCLR_DPLLLCKF_Pos) |
AnnaBridge | 171:3a7713b1edbc | 113 | #define SYSCTRL_INTENCLR_DPLLLTO_Pos 17 /**< \brief (SYSCTRL_INTENCLR) DPLL Lock Timeout Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 114 | #define SYSCTRL_INTENCLR_DPLLLTO (0x1ul << SYSCTRL_INTENCLR_DPLLLTO_Pos) |
AnnaBridge | 171:3a7713b1edbc | 115 | #define SYSCTRL_INTENCLR_MASK 0x00038FFFul /**< \brief (SYSCTRL_INTENCLR) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 116 | |
AnnaBridge | 171:3a7713b1edbc | 117 | /* -------- SYSCTRL_INTENSET : (SYSCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */ |
AnnaBridge | 171:3a7713b1edbc | 118 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 119 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 120 | struct { |
AnnaBridge | 171:3a7713b1edbc | 121 | uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 122 | uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 123 | uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 124 | uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 125 | uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 126 | uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 127 | uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 128 | uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 129 | uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 130 | uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 131 | uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 132 | uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 133 | uint32_t :3; /*!< bit: 12..14 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 134 | uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 135 | uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 136 | uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 137 | uint32_t :14; /*!< bit: 18..31 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 138 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 139 | uint32_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 140 | } SYSCTRL_INTENSET_Type; |
AnnaBridge | 171:3a7713b1edbc | 141 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 142 | |
AnnaBridge | 171:3a7713b1edbc | 143 | #define SYSCTRL_INTENSET_OFFSET 0x04 /**< \brief (SYSCTRL_INTENSET offset) Interrupt Enable Set */ |
AnnaBridge | 171:3a7713b1edbc | 144 | #define SYSCTRL_INTENSET_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_INTENSET reset_value) Interrupt Enable Set */ |
AnnaBridge | 171:3a7713b1edbc | 145 | |
AnnaBridge | 171:3a7713b1edbc | 146 | #define SYSCTRL_INTENSET_XOSCRDY_Pos 0 /**< \brief (SYSCTRL_INTENSET) XOSC Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 147 | #define SYSCTRL_INTENSET_XOSCRDY (0x1ul << SYSCTRL_INTENSET_XOSCRDY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 148 | #define SYSCTRL_INTENSET_XOSC32KRDY_Pos 1 /**< \brief (SYSCTRL_INTENSET) XOSC32K Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 149 | #define SYSCTRL_INTENSET_XOSC32KRDY (0x1ul << SYSCTRL_INTENSET_XOSC32KRDY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 150 | #define SYSCTRL_INTENSET_OSC32KRDY_Pos 2 /**< \brief (SYSCTRL_INTENSET) OSC32K Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 151 | #define SYSCTRL_INTENSET_OSC32KRDY (0x1ul << SYSCTRL_INTENSET_OSC32KRDY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 152 | #define SYSCTRL_INTENSET_OSC8MRDY_Pos 3 /**< \brief (SYSCTRL_INTENSET) OSC8M Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 153 | #define SYSCTRL_INTENSET_OSC8MRDY (0x1ul << SYSCTRL_INTENSET_OSC8MRDY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 154 | #define SYSCTRL_INTENSET_DFLLRDY_Pos 4 /**< \brief (SYSCTRL_INTENSET) DFLL Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 155 | #define SYSCTRL_INTENSET_DFLLRDY (0x1ul << SYSCTRL_INTENSET_DFLLRDY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 156 | #define SYSCTRL_INTENSET_DFLLOOB_Pos 5 /**< \brief (SYSCTRL_INTENSET) DFLL Out Of Bounds Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 157 | #define SYSCTRL_INTENSET_DFLLOOB (0x1ul << SYSCTRL_INTENSET_DFLLOOB_Pos) |
AnnaBridge | 171:3a7713b1edbc | 158 | #define SYSCTRL_INTENSET_DFLLLCKF_Pos 6 /**< \brief (SYSCTRL_INTENSET) DFLL Lock Fine Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 159 | #define SYSCTRL_INTENSET_DFLLLCKF (0x1ul << SYSCTRL_INTENSET_DFLLLCKF_Pos) |
AnnaBridge | 171:3a7713b1edbc | 160 | #define SYSCTRL_INTENSET_DFLLLCKC_Pos 7 /**< \brief (SYSCTRL_INTENSET) DFLL Lock Coarse Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 161 | #define SYSCTRL_INTENSET_DFLLLCKC (0x1ul << SYSCTRL_INTENSET_DFLLLCKC_Pos) |
AnnaBridge | 171:3a7713b1edbc | 162 | #define SYSCTRL_INTENSET_DFLLRCS_Pos 8 /**< \brief (SYSCTRL_INTENSET) DFLL Reference Clock Stopped Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 163 | #define SYSCTRL_INTENSET_DFLLRCS (0x1ul << SYSCTRL_INTENSET_DFLLRCS_Pos) |
AnnaBridge | 171:3a7713b1edbc | 164 | #define SYSCTRL_INTENSET_BOD33RDY_Pos 9 /**< \brief (SYSCTRL_INTENSET) BOD33 Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 165 | #define SYSCTRL_INTENSET_BOD33RDY (0x1ul << SYSCTRL_INTENSET_BOD33RDY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 166 | #define SYSCTRL_INTENSET_BOD33DET_Pos 10 /**< \brief (SYSCTRL_INTENSET) BOD33 Detection Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 167 | #define SYSCTRL_INTENSET_BOD33DET (0x1ul << SYSCTRL_INTENSET_BOD33DET_Pos) |
AnnaBridge | 171:3a7713b1edbc | 168 | #define SYSCTRL_INTENSET_B33SRDY_Pos 11 /**< \brief (SYSCTRL_INTENSET) BOD33 Synchronization Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 169 | #define SYSCTRL_INTENSET_B33SRDY (0x1ul << SYSCTRL_INTENSET_B33SRDY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 170 | #define SYSCTRL_INTENSET_DPLLLCKR_Pos 15 /**< \brief (SYSCTRL_INTENSET) DPLL Lock Rise Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 171 | #define SYSCTRL_INTENSET_DPLLLCKR (0x1ul << SYSCTRL_INTENSET_DPLLLCKR_Pos) |
AnnaBridge | 171:3a7713b1edbc | 172 | #define SYSCTRL_INTENSET_DPLLLCKF_Pos 16 /**< \brief (SYSCTRL_INTENSET) DPLL Lock Fall Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 173 | #define SYSCTRL_INTENSET_DPLLLCKF (0x1ul << SYSCTRL_INTENSET_DPLLLCKF_Pos) |
AnnaBridge | 171:3a7713b1edbc | 174 | #define SYSCTRL_INTENSET_DPLLLTO_Pos 17 /**< \brief (SYSCTRL_INTENSET) DPLL Lock Timeout Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 175 | #define SYSCTRL_INTENSET_DPLLLTO (0x1ul << SYSCTRL_INTENSET_DPLLLTO_Pos) |
AnnaBridge | 171:3a7713b1edbc | 176 | #define SYSCTRL_INTENSET_MASK 0x00038FFFul /**< \brief (SYSCTRL_INTENSET) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 177 | |
AnnaBridge | 171:3a7713b1edbc | 178 | /* -------- SYSCTRL_INTFLAG : (SYSCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */ |
AnnaBridge | 171:3a7713b1edbc | 179 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 180 | typedef union { // __I to avoid read-modify-write on write-to-clear register |
AnnaBridge | 171:3a7713b1edbc | 181 | struct { |
AnnaBridge | 171:3a7713b1edbc | 182 | __I uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */ |
AnnaBridge | 171:3a7713b1edbc | 183 | __I uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */ |
AnnaBridge | 171:3a7713b1edbc | 184 | __I uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */ |
AnnaBridge | 171:3a7713b1edbc | 185 | __I uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */ |
AnnaBridge | 171:3a7713b1edbc | 186 | __I uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */ |
AnnaBridge | 171:3a7713b1edbc | 187 | __I uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */ |
AnnaBridge | 171:3a7713b1edbc | 188 | __I uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */ |
AnnaBridge | 171:3a7713b1edbc | 189 | __I uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */ |
AnnaBridge | 171:3a7713b1edbc | 190 | __I uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */ |
AnnaBridge | 171:3a7713b1edbc | 191 | __I uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */ |
AnnaBridge | 171:3a7713b1edbc | 192 | __I uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */ |
AnnaBridge | 171:3a7713b1edbc | 193 | __I uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */ |
AnnaBridge | 171:3a7713b1edbc | 194 | __I uint32_t :3; /*!< bit: 12..14 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 195 | __I uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */ |
AnnaBridge | 171:3a7713b1edbc | 196 | __I uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */ |
AnnaBridge | 171:3a7713b1edbc | 197 | __I uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */ |
AnnaBridge | 171:3a7713b1edbc | 198 | __I uint32_t :14; /*!< bit: 18..31 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 199 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 200 | uint32_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 201 | } SYSCTRL_INTFLAG_Type; |
AnnaBridge | 171:3a7713b1edbc | 202 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 203 | |
AnnaBridge | 171:3a7713b1edbc | 204 | #define SYSCTRL_INTFLAG_OFFSET 0x08 /**< \brief (SYSCTRL_INTFLAG offset) Interrupt Flag Status and Clear */ |
AnnaBridge | 171:3a7713b1edbc | 205 | #define SYSCTRL_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */ |
AnnaBridge | 171:3a7713b1edbc | 206 | |
AnnaBridge | 171:3a7713b1edbc | 207 | #define SYSCTRL_INTFLAG_XOSCRDY_Pos 0 /**< \brief (SYSCTRL_INTFLAG) XOSC Ready */ |
AnnaBridge | 171:3a7713b1edbc | 208 | #define SYSCTRL_INTFLAG_XOSCRDY (0x1ul << SYSCTRL_INTFLAG_XOSCRDY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 209 | #define SYSCTRL_INTFLAG_XOSC32KRDY_Pos 1 /**< \brief (SYSCTRL_INTFLAG) XOSC32K Ready */ |
AnnaBridge | 171:3a7713b1edbc | 210 | #define SYSCTRL_INTFLAG_XOSC32KRDY (0x1ul << SYSCTRL_INTFLAG_XOSC32KRDY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 211 | #define SYSCTRL_INTFLAG_OSC32KRDY_Pos 2 /**< \brief (SYSCTRL_INTFLAG) OSC32K Ready */ |
AnnaBridge | 171:3a7713b1edbc | 212 | #define SYSCTRL_INTFLAG_OSC32KRDY (0x1ul << SYSCTRL_INTFLAG_OSC32KRDY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 213 | #define SYSCTRL_INTFLAG_OSC8MRDY_Pos 3 /**< \brief (SYSCTRL_INTFLAG) OSC8M Ready */ |
AnnaBridge | 171:3a7713b1edbc | 214 | #define SYSCTRL_INTFLAG_OSC8MRDY (0x1ul << SYSCTRL_INTFLAG_OSC8MRDY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 215 | #define SYSCTRL_INTFLAG_DFLLRDY_Pos 4 /**< \brief (SYSCTRL_INTFLAG) DFLL Ready */ |
AnnaBridge | 171:3a7713b1edbc | 216 | #define SYSCTRL_INTFLAG_DFLLRDY (0x1ul << SYSCTRL_INTFLAG_DFLLRDY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 217 | #define SYSCTRL_INTFLAG_DFLLOOB_Pos 5 /**< \brief (SYSCTRL_INTFLAG) DFLL Out Of Bounds */ |
AnnaBridge | 171:3a7713b1edbc | 218 | #define SYSCTRL_INTFLAG_DFLLOOB (0x1ul << SYSCTRL_INTFLAG_DFLLOOB_Pos) |
AnnaBridge | 171:3a7713b1edbc | 219 | #define SYSCTRL_INTFLAG_DFLLLCKF_Pos 6 /**< \brief (SYSCTRL_INTFLAG) DFLL Lock Fine */ |
AnnaBridge | 171:3a7713b1edbc | 220 | #define SYSCTRL_INTFLAG_DFLLLCKF (0x1ul << SYSCTRL_INTFLAG_DFLLLCKF_Pos) |
AnnaBridge | 171:3a7713b1edbc | 221 | #define SYSCTRL_INTFLAG_DFLLLCKC_Pos 7 /**< \brief (SYSCTRL_INTFLAG) DFLL Lock Coarse */ |
AnnaBridge | 171:3a7713b1edbc | 222 | #define SYSCTRL_INTFLAG_DFLLLCKC (0x1ul << SYSCTRL_INTFLAG_DFLLLCKC_Pos) |
AnnaBridge | 171:3a7713b1edbc | 223 | #define SYSCTRL_INTFLAG_DFLLRCS_Pos 8 /**< \brief (SYSCTRL_INTFLAG) DFLL Reference Clock Stopped */ |
AnnaBridge | 171:3a7713b1edbc | 224 | #define SYSCTRL_INTFLAG_DFLLRCS (0x1ul << SYSCTRL_INTFLAG_DFLLRCS_Pos) |
AnnaBridge | 171:3a7713b1edbc | 225 | #define SYSCTRL_INTFLAG_BOD33RDY_Pos 9 /**< \brief (SYSCTRL_INTFLAG) BOD33 Ready */ |
AnnaBridge | 171:3a7713b1edbc | 226 | #define SYSCTRL_INTFLAG_BOD33RDY (0x1ul << SYSCTRL_INTFLAG_BOD33RDY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 227 | #define SYSCTRL_INTFLAG_BOD33DET_Pos 10 /**< \brief (SYSCTRL_INTFLAG) BOD33 Detection */ |
AnnaBridge | 171:3a7713b1edbc | 228 | #define SYSCTRL_INTFLAG_BOD33DET (0x1ul << SYSCTRL_INTFLAG_BOD33DET_Pos) |
AnnaBridge | 171:3a7713b1edbc | 229 | #define SYSCTRL_INTFLAG_B33SRDY_Pos 11 /**< \brief (SYSCTRL_INTFLAG) BOD33 Synchronization Ready */ |
AnnaBridge | 171:3a7713b1edbc | 230 | #define SYSCTRL_INTFLAG_B33SRDY (0x1ul << SYSCTRL_INTFLAG_B33SRDY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 231 | #define SYSCTRL_INTFLAG_DPLLLCKR_Pos 15 /**< \brief (SYSCTRL_INTFLAG) DPLL Lock Rise */ |
AnnaBridge | 171:3a7713b1edbc | 232 | #define SYSCTRL_INTFLAG_DPLLLCKR (0x1ul << SYSCTRL_INTFLAG_DPLLLCKR_Pos) |
AnnaBridge | 171:3a7713b1edbc | 233 | #define SYSCTRL_INTFLAG_DPLLLCKF_Pos 16 /**< \brief (SYSCTRL_INTFLAG) DPLL Lock Fall */ |
AnnaBridge | 171:3a7713b1edbc | 234 | #define SYSCTRL_INTFLAG_DPLLLCKF (0x1ul << SYSCTRL_INTFLAG_DPLLLCKF_Pos) |
AnnaBridge | 171:3a7713b1edbc | 235 | #define SYSCTRL_INTFLAG_DPLLLTO_Pos 17 /**< \brief (SYSCTRL_INTFLAG) DPLL Lock Timeout */ |
AnnaBridge | 171:3a7713b1edbc | 236 | #define SYSCTRL_INTFLAG_DPLLLTO (0x1ul << SYSCTRL_INTFLAG_DPLLLTO_Pos) |
AnnaBridge | 171:3a7713b1edbc | 237 | #define SYSCTRL_INTFLAG_MASK 0x00038FFFul /**< \brief (SYSCTRL_INTFLAG) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 238 | |
AnnaBridge | 171:3a7713b1edbc | 239 | /* -------- SYSCTRL_PCLKSR : (SYSCTRL Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */ |
AnnaBridge | 171:3a7713b1edbc | 240 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 241 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 242 | struct { |
AnnaBridge | 171:3a7713b1edbc | 243 | uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */ |
AnnaBridge | 171:3a7713b1edbc | 244 | uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */ |
AnnaBridge | 171:3a7713b1edbc | 245 | uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */ |
AnnaBridge | 171:3a7713b1edbc | 246 | uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */ |
AnnaBridge | 171:3a7713b1edbc | 247 | uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */ |
AnnaBridge | 171:3a7713b1edbc | 248 | uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */ |
AnnaBridge | 171:3a7713b1edbc | 249 | uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */ |
AnnaBridge | 171:3a7713b1edbc | 250 | uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */ |
AnnaBridge | 171:3a7713b1edbc | 251 | uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */ |
AnnaBridge | 171:3a7713b1edbc | 252 | uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */ |
AnnaBridge | 171:3a7713b1edbc | 253 | uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */ |
AnnaBridge | 171:3a7713b1edbc | 254 | uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */ |
AnnaBridge | 171:3a7713b1edbc | 255 | uint32_t :3; /*!< bit: 12..14 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 256 | uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */ |
AnnaBridge | 171:3a7713b1edbc | 257 | uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */ |
AnnaBridge | 171:3a7713b1edbc | 258 | uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */ |
AnnaBridge | 171:3a7713b1edbc | 259 | uint32_t :14; /*!< bit: 18..31 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 260 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 261 | uint32_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 262 | } SYSCTRL_PCLKSR_Type; |
AnnaBridge | 171:3a7713b1edbc | 263 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 264 | |
AnnaBridge | 171:3a7713b1edbc | 265 | #define SYSCTRL_PCLKSR_OFFSET 0x0C /**< \brief (SYSCTRL_PCLKSR offset) Power and Clocks Status */ |
AnnaBridge | 171:3a7713b1edbc | 266 | #define SYSCTRL_PCLKSR_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_PCLKSR reset_value) Power and Clocks Status */ |
AnnaBridge | 171:3a7713b1edbc | 267 | |
AnnaBridge | 171:3a7713b1edbc | 268 | #define SYSCTRL_PCLKSR_XOSCRDY_Pos 0 /**< \brief (SYSCTRL_PCLKSR) XOSC Ready */ |
AnnaBridge | 171:3a7713b1edbc | 269 | #define SYSCTRL_PCLKSR_XOSCRDY (0x1ul << SYSCTRL_PCLKSR_XOSCRDY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 270 | #define SYSCTRL_PCLKSR_XOSC32KRDY_Pos 1 /**< \brief (SYSCTRL_PCLKSR) XOSC32K Ready */ |
AnnaBridge | 171:3a7713b1edbc | 271 | #define SYSCTRL_PCLKSR_XOSC32KRDY (0x1ul << SYSCTRL_PCLKSR_XOSC32KRDY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 272 | #define SYSCTRL_PCLKSR_OSC32KRDY_Pos 2 /**< \brief (SYSCTRL_PCLKSR) OSC32K Ready */ |
AnnaBridge | 171:3a7713b1edbc | 273 | #define SYSCTRL_PCLKSR_OSC32KRDY (0x1ul << SYSCTRL_PCLKSR_OSC32KRDY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 274 | #define SYSCTRL_PCLKSR_OSC8MRDY_Pos 3 /**< \brief (SYSCTRL_PCLKSR) OSC8M Ready */ |
AnnaBridge | 171:3a7713b1edbc | 275 | #define SYSCTRL_PCLKSR_OSC8MRDY (0x1ul << SYSCTRL_PCLKSR_OSC8MRDY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 276 | #define SYSCTRL_PCLKSR_DFLLRDY_Pos 4 /**< \brief (SYSCTRL_PCLKSR) DFLL Ready */ |
AnnaBridge | 171:3a7713b1edbc | 277 | #define SYSCTRL_PCLKSR_DFLLRDY (0x1ul << SYSCTRL_PCLKSR_DFLLRDY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 278 | #define SYSCTRL_PCLKSR_DFLLOOB_Pos 5 /**< \brief (SYSCTRL_PCLKSR) DFLL Out Of Bounds */ |
AnnaBridge | 171:3a7713b1edbc | 279 | #define SYSCTRL_PCLKSR_DFLLOOB (0x1ul << SYSCTRL_PCLKSR_DFLLOOB_Pos) |
AnnaBridge | 171:3a7713b1edbc | 280 | #define SYSCTRL_PCLKSR_DFLLLCKF_Pos 6 /**< \brief (SYSCTRL_PCLKSR) DFLL Lock Fine */ |
AnnaBridge | 171:3a7713b1edbc | 281 | #define SYSCTRL_PCLKSR_DFLLLCKF (0x1ul << SYSCTRL_PCLKSR_DFLLLCKF_Pos) |
AnnaBridge | 171:3a7713b1edbc | 282 | #define SYSCTRL_PCLKSR_DFLLLCKC_Pos 7 /**< \brief (SYSCTRL_PCLKSR) DFLL Lock Coarse */ |
AnnaBridge | 171:3a7713b1edbc | 283 | #define SYSCTRL_PCLKSR_DFLLLCKC (0x1ul << SYSCTRL_PCLKSR_DFLLLCKC_Pos) |
AnnaBridge | 171:3a7713b1edbc | 284 | #define SYSCTRL_PCLKSR_DFLLRCS_Pos 8 /**< \brief (SYSCTRL_PCLKSR) DFLL Reference Clock Stopped */ |
AnnaBridge | 171:3a7713b1edbc | 285 | #define SYSCTRL_PCLKSR_DFLLRCS (0x1ul << SYSCTRL_PCLKSR_DFLLRCS_Pos) |
AnnaBridge | 171:3a7713b1edbc | 286 | #define SYSCTRL_PCLKSR_BOD33RDY_Pos 9 /**< \brief (SYSCTRL_PCLKSR) BOD33 Ready */ |
AnnaBridge | 171:3a7713b1edbc | 287 | #define SYSCTRL_PCLKSR_BOD33RDY (0x1ul << SYSCTRL_PCLKSR_BOD33RDY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 288 | #define SYSCTRL_PCLKSR_BOD33DET_Pos 10 /**< \brief (SYSCTRL_PCLKSR) BOD33 Detection */ |
AnnaBridge | 171:3a7713b1edbc | 289 | #define SYSCTRL_PCLKSR_BOD33DET (0x1ul << SYSCTRL_PCLKSR_BOD33DET_Pos) |
AnnaBridge | 171:3a7713b1edbc | 290 | #define SYSCTRL_PCLKSR_B33SRDY_Pos 11 /**< \brief (SYSCTRL_PCLKSR) BOD33 Synchronization Ready */ |
AnnaBridge | 171:3a7713b1edbc | 291 | #define SYSCTRL_PCLKSR_B33SRDY (0x1ul << SYSCTRL_PCLKSR_B33SRDY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 292 | #define SYSCTRL_PCLKSR_DPLLLCKR_Pos 15 /**< \brief (SYSCTRL_PCLKSR) DPLL Lock Rise */ |
AnnaBridge | 171:3a7713b1edbc | 293 | #define SYSCTRL_PCLKSR_DPLLLCKR (0x1ul << SYSCTRL_PCLKSR_DPLLLCKR_Pos) |
AnnaBridge | 171:3a7713b1edbc | 294 | #define SYSCTRL_PCLKSR_DPLLLCKF_Pos 16 /**< \brief (SYSCTRL_PCLKSR) DPLL Lock Fall */ |
AnnaBridge | 171:3a7713b1edbc | 295 | #define SYSCTRL_PCLKSR_DPLLLCKF (0x1ul << SYSCTRL_PCLKSR_DPLLLCKF_Pos) |
AnnaBridge | 171:3a7713b1edbc | 296 | #define SYSCTRL_PCLKSR_DPLLLTO_Pos 17 /**< \brief (SYSCTRL_PCLKSR) DPLL Lock Timeout */ |
AnnaBridge | 171:3a7713b1edbc | 297 | #define SYSCTRL_PCLKSR_DPLLLTO (0x1ul << SYSCTRL_PCLKSR_DPLLLTO_Pos) |
AnnaBridge | 171:3a7713b1edbc | 298 | #define SYSCTRL_PCLKSR_MASK 0x00038FFFul /**< \brief (SYSCTRL_PCLKSR) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 299 | |
AnnaBridge | 171:3a7713b1edbc | 300 | /* -------- SYSCTRL_XOSC : (SYSCTRL Offset: 0x10) (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control -------- */ |
AnnaBridge | 171:3a7713b1edbc | 301 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 302 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 303 | struct { |
AnnaBridge | 171:3a7713b1edbc | 304 | uint16_t :1; /*!< bit: 0 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 305 | uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ |
AnnaBridge | 171:3a7713b1edbc | 306 | uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */ |
AnnaBridge | 171:3a7713b1edbc | 307 | uint16_t :3; /*!< bit: 3.. 5 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 308 | uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ |
AnnaBridge | 171:3a7713b1edbc | 309 | uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ |
AnnaBridge | 171:3a7713b1edbc | 310 | uint16_t GAIN:3; /*!< bit: 8..10 Oscillator Gain */ |
AnnaBridge | 171:3a7713b1edbc | 311 | uint16_t AMPGC:1; /*!< bit: 11 Automatic Amplitude Gain Control */ |
AnnaBridge | 171:3a7713b1edbc | 312 | uint16_t STARTUP:4; /*!< bit: 12..15 Start-Up Time */ |
AnnaBridge | 171:3a7713b1edbc | 313 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 314 | uint16_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 315 | } SYSCTRL_XOSC_Type; |
AnnaBridge | 171:3a7713b1edbc | 316 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 317 | |
AnnaBridge | 171:3a7713b1edbc | 318 | #define SYSCTRL_XOSC_OFFSET 0x10 /**< \brief (SYSCTRL_XOSC offset) External Multipurpose Crystal Oscillator (XOSC) Control */ |
AnnaBridge | 171:3a7713b1edbc | 319 | #define SYSCTRL_XOSC_RESETVALUE 0x0080ul /**< \brief (SYSCTRL_XOSC reset_value) External Multipurpose Crystal Oscillator (XOSC) Control */ |
AnnaBridge | 171:3a7713b1edbc | 320 | |
AnnaBridge | 171:3a7713b1edbc | 321 | #define SYSCTRL_XOSC_ENABLE_Pos 1 /**< \brief (SYSCTRL_XOSC) Oscillator Enable */ |
AnnaBridge | 171:3a7713b1edbc | 322 | #define SYSCTRL_XOSC_ENABLE (0x1ul << SYSCTRL_XOSC_ENABLE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 323 | #define SYSCTRL_XOSC_XTALEN_Pos 2 /**< \brief (SYSCTRL_XOSC) Crystal Oscillator Enable */ |
AnnaBridge | 171:3a7713b1edbc | 324 | #define SYSCTRL_XOSC_XTALEN (0x1ul << SYSCTRL_XOSC_XTALEN_Pos) |
AnnaBridge | 171:3a7713b1edbc | 325 | #define SYSCTRL_XOSC_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_XOSC) Run in Standby */ |
AnnaBridge | 171:3a7713b1edbc | 326 | #define SYSCTRL_XOSC_RUNSTDBY (0x1ul << SYSCTRL_XOSC_RUNSTDBY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 327 | #define SYSCTRL_XOSC_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_XOSC) On Demand Control */ |
AnnaBridge | 171:3a7713b1edbc | 328 | #define SYSCTRL_XOSC_ONDEMAND (0x1ul << SYSCTRL_XOSC_ONDEMAND_Pos) |
AnnaBridge | 171:3a7713b1edbc | 329 | #define SYSCTRL_XOSC_GAIN_Pos 8 /**< \brief (SYSCTRL_XOSC) Oscillator Gain */ |
AnnaBridge | 171:3a7713b1edbc | 330 | #define SYSCTRL_XOSC_GAIN_Msk (0x7ul << SYSCTRL_XOSC_GAIN_Pos) |
AnnaBridge | 171:3a7713b1edbc | 331 | #define SYSCTRL_XOSC_GAIN(value) (SYSCTRL_XOSC_GAIN_Msk & ((value) << SYSCTRL_XOSC_GAIN_Pos)) |
AnnaBridge | 171:3a7713b1edbc | 332 | #define SYSCTRL_XOSC_GAIN_0_Val 0x0ul /**< \brief (SYSCTRL_XOSC) 2MHz */ |
AnnaBridge | 171:3a7713b1edbc | 333 | #define SYSCTRL_XOSC_GAIN_1_Val 0x1ul /**< \brief (SYSCTRL_XOSC) 4MHz */ |
AnnaBridge | 171:3a7713b1edbc | 334 | #define SYSCTRL_XOSC_GAIN_2_Val 0x2ul /**< \brief (SYSCTRL_XOSC) 8MHz */ |
AnnaBridge | 171:3a7713b1edbc | 335 | #define SYSCTRL_XOSC_GAIN_3_Val 0x3ul /**< \brief (SYSCTRL_XOSC) 16MHz */ |
AnnaBridge | 171:3a7713b1edbc | 336 | #define SYSCTRL_XOSC_GAIN_4_Val 0x4ul /**< \brief (SYSCTRL_XOSC) 30MHz */ |
AnnaBridge | 171:3a7713b1edbc | 337 | #define SYSCTRL_XOSC_GAIN_0 (SYSCTRL_XOSC_GAIN_0_Val << SYSCTRL_XOSC_GAIN_Pos) |
AnnaBridge | 171:3a7713b1edbc | 338 | #define SYSCTRL_XOSC_GAIN_1 (SYSCTRL_XOSC_GAIN_1_Val << SYSCTRL_XOSC_GAIN_Pos) |
AnnaBridge | 171:3a7713b1edbc | 339 | #define SYSCTRL_XOSC_GAIN_2 (SYSCTRL_XOSC_GAIN_2_Val << SYSCTRL_XOSC_GAIN_Pos) |
AnnaBridge | 171:3a7713b1edbc | 340 | #define SYSCTRL_XOSC_GAIN_3 (SYSCTRL_XOSC_GAIN_3_Val << SYSCTRL_XOSC_GAIN_Pos) |
AnnaBridge | 171:3a7713b1edbc | 341 | #define SYSCTRL_XOSC_GAIN_4 (SYSCTRL_XOSC_GAIN_4_Val << SYSCTRL_XOSC_GAIN_Pos) |
AnnaBridge | 171:3a7713b1edbc | 342 | #define SYSCTRL_XOSC_AMPGC_Pos 11 /**< \brief (SYSCTRL_XOSC) Automatic Amplitude Gain Control */ |
AnnaBridge | 171:3a7713b1edbc | 343 | #define SYSCTRL_XOSC_AMPGC (0x1ul << SYSCTRL_XOSC_AMPGC_Pos) |
AnnaBridge | 171:3a7713b1edbc | 344 | #define SYSCTRL_XOSC_STARTUP_Pos 12 /**< \brief (SYSCTRL_XOSC) Start-Up Time */ |
AnnaBridge | 171:3a7713b1edbc | 345 | #define SYSCTRL_XOSC_STARTUP_Msk (0xFul << SYSCTRL_XOSC_STARTUP_Pos) |
AnnaBridge | 171:3a7713b1edbc | 346 | #define SYSCTRL_XOSC_STARTUP(value) (SYSCTRL_XOSC_STARTUP_Msk & ((value) << SYSCTRL_XOSC_STARTUP_Pos)) |
AnnaBridge | 171:3a7713b1edbc | 347 | #define SYSCTRL_XOSC_MASK 0xFFC6ul /**< \brief (SYSCTRL_XOSC) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 348 | |
AnnaBridge | 171:3a7713b1edbc | 349 | /* -------- SYSCTRL_XOSC32K : (SYSCTRL Offset: 0x14) (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */ |
AnnaBridge | 171:3a7713b1edbc | 350 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 351 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 352 | struct { |
AnnaBridge | 171:3a7713b1edbc | 353 | uint16_t :1; /*!< bit: 0 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 354 | uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ |
AnnaBridge | 171:3a7713b1edbc | 355 | uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */ |
AnnaBridge | 171:3a7713b1edbc | 356 | uint16_t EN32K:1; /*!< bit: 3 32kHz Output Enable */ |
AnnaBridge | 171:3a7713b1edbc | 357 | uint16_t EN1K:1; /*!< bit: 4 1kHz Output Enable */ |
AnnaBridge | 171:3a7713b1edbc | 358 | uint16_t AAMPEN:1; /*!< bit: 5 Automatic Amplitude Control Enable */ |
AnnaBridge | 171:3a7713b1edbc | 359 | uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ |
AnnaBridge | 171:3a7713b1edbc | 360 | uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ |
AnnaBridge | 171:3a7713b1edbc | 361 | uint16_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */ |
AnnaBridge | 171:3a7713b1edbc | 362 | uint16_t :1; /*!< bit: 11 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 363 | uint16_t WRTLOCK:1; /*!< bit: 12 Write Lock */ |
AnnaBridge | 171:3a7713b1edbc | 364 | uint16_t :3; /*!< bit: 13..15 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 365 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 366 | uint16_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 367 | } SYSCTRL_XOSC32K_Type; |
AnnaBridge | 171:3a7713b1edbc | 368 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 369 | |
AnnaBridge | 171:3a7713b1edbc | 370 | #define SYSCTRL_XOSC32K_OFFSET 0x14 /**< \brief (SYSCTRL_XOSC32K offset) 32kHz External Crystal Oscillator (XOSC32K) Control */ |
AnnaBridge | 171:3a7713b1edbc | 371 | #define SYSCTRL_XOSC32K_RESETVALUE 0x0080ul /**< \brief (SYSCTRL_XOSC32K reset_value) 32kHz External Crystal Oscillator (XOSC32K) Control */ |
AnnaBridge | 171:3a7713b1edbc | 372 | |
AnnaBridge | 171:3a7713b1edbc | 373 | #define SYSCTRL_XOSC32K_ENABLE_Pos 1 /**< \brief (SYSCTRL_XOSC32K) Oscillator Enable */ |
AnnaBridge | 171:3a7713b1edbc | 374 | #define SYSCTRL_XOSC32K_ENABLE (0x1ul << SYSCTRL_XOSC32K_ENABLE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 375 | #define SYSCTRL_XOSC32K_XTALEN_Pos 2 /**< \brief (SYSCTRL_XOSC32K) Crystal Oscillator Enable */ |
AnnaBridge | 171:3a7713b1edbc | 376 | #define SYSCTRL_XOSC32K_XTALEN (0x1ul << SYSCTRL_XOSC32K_XTALEN_Pos) |
AnnaBridge | 171:3a7713b1edbc | 377 | #define SYSCTRL_XOSC32K_EN32K_Pos 3 /**< \brief (SYSCTRL_XOSC32K) 32kHz Output Enable */ |
AnnaBridge | 171:3a7713b1edbc | 378 | #define SYSCTRL_XOSC32K_EN32K (0x1ul << SYSCTRL_XOSC32K_EN32K_Pos) |
AnnaBridge | 171:3a7713b1edbc | 379 | #define SYSCTRL_XOSC32K_EN1K_Pos 4 /**< \brief (SYSCTRL_XOSC32K) 1kHz Output Enable */ |
AnnaBridge | 171:3a7713b1edbc | 380 | #define SYSCTRL_XOSC32K_EN1K (0x1ul << SYSCTRL_XOSC32K_EN1K_Pos) |
AnnaBridge | 171:3a7713b1edbc | 381 | #define SYSCTRL_XOSC32K_AAMPEN_Pos 5 /**< \brief (SYSCTRL_XOSC32K) Automatic Amplitude Control Enable */ |
AnnaBridge | 171:3a7713b1edbc | 382 | #define SYSCTRL_XOSC32K_AAMPEN (0x1ul << SYSCTRL_XOSC32K_AAMPEN_Pos) |
AnnaBridge | 171:3a7713b1edbc | 383 | #define SYSCTRL_XOSC32K_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_XOSC32K) Run in Standby */ |
AnnaBridge | 171:3a7713b1edbc | 384 | #define SYSCTRL_XOSC32K_RUNSTDBY (0x1ul << SYSCTRL_XOSC32K_RUNSTDBY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 385 | #define SYSCTRL_XOSC32K_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_XOSC32K) On Demand Control */ |
AnnaBridge | 171:3a7713b1edbc | 386 | #define SYSCTRL_XOSC32K_ONDEMAND (0x1ul << SYSCTRL_XOSC32K_ONDEMAND_Pos) |
AnnaBridge | 171:3a7713b1edbc | 387 | #define SYSCTRL_XOSC32K_STARTUP_Pos 8 /**< \brief (SYSCTRL_XOSC32K) Oscillator Start-Up Time */ |
AnnaBridge | 171:3a7713b1edbc | 388 | #define SYSCTRL_XOSC32K_STARTUP_Msk (0x7ul << SYSCTRL_XOSC32K_STARTUP_Pos) |
AnnaBridge | 171:3a7713b1edbc | 389 | #define SYSCTRL_XOSC32K_STARTUP(value) (SYSCTRL_XOSC32K_STARTUP_Msk & ((value) << SYSCTRL_XOSC32K_STARTUP_Pos)) |
AnnaBridge | 171:3a7713b1edbc | 390 | #define SYSCTRL_XOSC32K_WRTLOCK_Pos 12 /**< \brief (SYSCTRL_XOSC32K) Write Lock */ |
AnnaBridge | 171:3a7713b1edbc | 391 | #define SYSCTRL_XOSC32K_WRTLOCK (0x1ul << SYSCTRL_XOSC32K_WRTLOCK_Pos) |
AnnaBridge | 171:3a7713b1edbc | 392 | #define SYSCTRL_XOSC32K_MASK 0x17FEul /**< \brief (SYSCTRL_XOSC32K) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 393 | |
AnnaBridge | 171:3a7713b1edbc | 394 | /* -------- SYSCTRL_OSC32K : (SYSCTRL Offset: 0x18) (R/W 32) 32kHz Internal Oscillator (OSC32K) Control -------- */ |
AnnaBridge | 171:3a7713b1edbc | 395 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 396 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 397 | struct { |
AnnaBridge | 171:3a7713b1edbc | 398 | uint32_t :1; /*!< bit: 0 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 399 | uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ |
AnnaBridge | 171:3a7713b1edbc | 400 | uint32_t EN32K:1; /*!< bit: 2 32kHz Output Enable */ |
AnnaBridge | 171:3a7713b1edbc | 401 | uint32_t EN1K:1; /*!< bit: 3 1kHz Output Enable */ |
AnnaBridge | 171:3a7713b1edbc | 402 | uint32_t :2; /*!< bit: 4.. 5 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 403 | uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ |
AnnaBridge | 171:3a7713b1edbc | 404 | uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ |
AnnaBridge | 171:3a7713b1edbc | 405 | uint32_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */ |
AnnaBridge | 171:3a7713b1edbc | 406 | uint32_t :1; /*!< bit: 11 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 407 | uint32_t WRTLOCK:1; /*!< bit: 12 Write Lock */ |
AnnaBridge | 171:3a7713b1edbc | 408 | uint32_t :3; /*!< bit: 13..15 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 409 | uint32_t CALIB:7; /*!< bit: 16..22 Oscillator Calibration */ |
AnnaBridge | 171:3a7713b1edbc | 410 | uint32_t :9; /*!< bit: 23..31 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 411 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 412 | uint32_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 413 | } SYSCTRL_OSC32K_Type; |
AnnaBridge | 171:3a7713b1edbc | 414 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 415 | |
AnnaBridge | 171:3a7713b1edbc | 416 | #define SYSCTRL_OSC32K_OFFSET 0x18 /**< \brief (SYSCTRL_OSC32K offset) 32kHz Internal Oscillator (OSC32K) Control */ |
AnnaBridge | 171:3a7713b1edbc | 417 | #define SYSCTRL_OSC32K_RESETVALUE 0x003F0080ul /**< \brief (SYSCTRL_OSC32K reset_value) 32kHz Internal Oscillator (OSC32K) Control */ |
AnnaBridge | 171:3a7713b1edbc | 418 | |
AnnaBridge | 171:3a7713b1edbc | 419 | #define SYSCTRL_OSC32K_ENABLE_Pos 1 /**< \brief (SYSCTRL_OSC32K) Oscillator Enable */ |
AnnaBridge | 171:3a7713b1edbc | 420 | #define SYSCTRL_OSC32K_ENABLE (0x1ul << SYSCTRL_OSC32K_ENABLE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 421 | #define SYSCTRL_OSC32K_EN32K_Pos 2 /**< \brief (SYSCTRL_OSC32K) 32kHz Output Enable */ |
AnnaBridge | 171:3a7713b1edbc | 422 | #define SYSCTRL_OSC32K_EN32K (0x1ul << SYSCTRL_OSC32K_EN32K_Pos) |
AnnaBridge | 171:3a7713b1edbc | 423 | #define SYSCTRL_OSC32K_EN1K_Pos 3 /**< \brief (SYSCTRL_OSC32K) 1kHz Output Enable */ |
AnnaBridge | 171:3a7713b1edbc | 424 | #define SYSCTRL_OSC32K_EN1K (0x1ul << SYSCTRL_OSC32K_EN1K_Pos) |
AnnaBridge | 171:3a7713b1edbc | 425 | #define SYSCTRL_OSC32K_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_OSC32K) Run in Standby */ |
AnnaBridge | 171:3a7713b1edbc | 426 | #define SYSCTRL_OSC32K_RUNSTDBY (0x1ul << SYSCTRL_OSC32K_RUNSTDBY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 427 | #define SYSCTRL_OSC32K_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_OSC32K) On Demand Control */ |
AnnaBridge | 171:3a7713b1edbc | 428 | #define SYSCTRL_OSC32K_ONDEMAND (0x1ul << SYSCTRL_OSC32K_ONDEMAND_Pos) |
AnnaBridge | 171:3a7713b1edbc | 429 | #define SYSCTRL_OSC32K_STARTUP_Pos 8 /**< \brief (SYSCTRL_OSC32K) Oscillator Start-Up Time */ |
AnnaBridge | 171:3a7713b1edbc | 430 | #define SYSCTRL_OSC32K_STARTUP_Msk (0x7ul << SYSCTRL_OSC32K_STARTUP_Pos) |
AnnaBridge | 171:3a7713b1edbc | 431 | #define SYSCTRL_OSC32K_STARTUP(value) (SYSCTRL_OSC32K_STARTUP_Msk & ((value) << SYSCTRL_OSC32K_STARTUP_Pos)) |
AnnaBridge | 171:3a7713b1edbc | 432 | #define SYSCTRL_OSC32K_WRTLOCK_Pos 12 /**< \brief (SYSCTRL_OSC32K) Write Lock */ |
AnnaBridge | 171:3a7713b1edbc | 433 | #define SYSCTRL_OSC32K_WRTLOCK (0x1ul << SYSCTRL_OSC32K_WRTLOCK_Pos) |
AnnaBridge | 171:3a7713b1edbc | 434 | #define SYSCTRL_OSC32K_CALIB_Pos 16 /**< \brief (SYSCTRL_OSC32K) Oscillator Calibration */ |
AnnaBridge | 171:3a7713b1edbc | 435 | #define SYSCTRL_OSC32K_CALIB_Msk (0x7Ful << SYSCTRL_OSC32K_CALIB_Pos) |
AnnaBridge | 171:3a7713b1edbc | 436 | #define SYSCTRL_OSC32K_CALIB(value) (SYSCTRL_OSC32K_CALIB_Msk & ((value) << SYSCTRL_OSC32K_CALIB_Pos)) |
AnnaBridge | 171:3a7713b1edbc | 437 | #define SYSCTRL_OSC32K_MASK 0x007F17CEul /**< \brief (SYSCTRL_OSC32K) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 438 | |
AnnaBridge | 171:3a7713b1edbc | 439 | /* -------- SYSCTRL_OSCULP32K : (SYSCTRL Offset: 0x1C) (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */ |
AnnaBridge | 171:3a7713b1edbc | 440 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 441 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 442 | struct { |
AnnaBridge | 171:3a7713b1edbc | 443 | uint8_t CALIB:5; /*!< bit: 0.. 4 Oscillator Calibration */ |
AnnaBridge | 171:3a7713b1edbc | 444 | uint8_t :2; /*!< bit: 5.. 6 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 445 | uint8_t WRTLOCK:1; /*!< bit: 7 Write Lock */ |
AnnaBridge | 171:3a7713b1edbc | 446 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 447 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 448 | } SYSCTRL_OSCULP32K_Type; |
AnnaBridge | 171:3a7713b1edbc | 449 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 450 | |
AnnaBridge | 171:3a7713b1edbc | 451 | #define SYSCTRL_OSCULP32K_OFFSET 0x1C /**< \brief (SYSCTRL_OSCULP32K offset) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ |
AnnaBridge | 171:3a7713b1edbc | 452 | #define SYSCTRL_OSCULP32K_RESETVALUE 0x1Ful /**< \brief (SYSCTRL_OSCULP32K reset_value) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ |
AnnaBridge | 171:3a7713b1edbc | 453 | |
AnnaBridge | 171:3a7713b1edbc | 454 | #define SYSCTRL_OSCULP32K_CALIB_Pos 0 /**< \brief (SYSCTRL_OSCULP32K) Oscillator Calibration */ |
AnnaBridge | 171:3a7713b1edbc | 455 | #define SYSCTRL_OSCULP32K_CALIB_Msk (0x1Ful << SYSCTRL_OSCULP32K_CALIB_Pos) |
AnnaBridge | 171:3a7713b1edbc | 456 | #define SYSCTRL_OSCULP32K_CALIB(value) (SYSCTRL_OSCULP32K_CALIB_Msk & ((value) << SYSCTRL_OSCULP32K_CALIB_Pos)) |
AnnaBridge | 171:3a7713b1edbc | 457 | #define SYSCTRL_OSCULP32K_WRTLOCK_Pos 7 /**< \brief (SYSCTRL_OSCULP32K) Write Lock */ |
AnnaBridge | 171:3a7713b1edbc | 458 | #define SYSCTRL_OSCULP32K_WRTLOCK (0x1ul << SYSCTRL_OSCULP32K_WRTLOCK_Pos) |
AnnaBridge | 171:3a7713b1edbc | 459 | #define SYSCTRL_OSCULP32K_MASK 0x9Ful /**< \brief (SYSCTRL_OSCULP32K) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 460 | |
AnnaBridge | 171:3a7713b1edbc | 461 | /* -------- SYSCTRL_OSC8M : (SYSCTRL Offset: 0x20) (R/W 32) 8MHz Internal Oscillator (OSC8M) Control -------- */ |
AnnaBridge | 171:3a7713b1edbc | 462 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 463 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 464 | struct { |
AnnaBridge | 171:3a7713b1edbc | 465 | uint32_t :1; /*!< bit: 0 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 466 | uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ |
AnnaBridge | 171:3a7713b1edbc | 467 | uint32_t :4; /*!< bit: 2.. 5 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 468 | uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ |
AnnaBridge | 171:3a7713b1edbc | 469 | uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ |
AnnaBridge | 171:3a7713b1edbc | 470 | uint32_t PRESC:2; /*!< bit: 8.. 9 Oscillator Prescaler */ |
AnnaBridge | 171:3a7713b1edbc | 471 | uint32_t :6; /*!< bit: 10..15 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 472 | uint32_t CALIB:12; /*!< bit: 16..27 Oscillator Calibration */ |
AnnaBridge | 171:3a7713b1edbc | 473 | uint32_t :2; /*!< bit: 28..29 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 474 | uint32_t FRANGE:2; /*!< bit: 30..31 Oscillator Frequency Range */ |
AnnaBridge | 171:3a7713b1edbc | 475 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 476 | uint32_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 477 | } SYSCTRL_OSC8M_Type; |
AnnaBridge | 171:3a7713b1edbc | 478 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 479 | |
AnnaBridge | 171:3a7713b1edbc | 480 | #define SYSCTRL_OSC8M_OFFSET 0x20 /**< \brief (SYSCTRL_OSC8M offset) 8MHz Internal Oscillator (OSC8M) Control */ |
AnnaBridge | 171:3a7713b1edbc | 481 | #define SYSCTRL_OSC8M_RESETVALUE 0x87070382ul /**< \brief (SYSCTRL_OSC8M reset_value) 8MHz Internal Oscillator (OSC8M) Control */ |
AnnaBridge | 171:3a7713b1edbc | 482 | |
AnnaBridge | 171:3a7713b1edbc | 483 | #define SYSCTRL_OSC8M_ENABLE_Pos 1 /**< \brief (SYSCTRL_OSC8M) Oscillator Enable */ |
AnnaBridge | 171:3a7713b1edbc | 484 | #define SYSCTRL_OSC8M_ENABLE (0x1ul << SYSCTRL_OSC8M_ENABLE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 485 | #define SYSCTRL_OSC8M_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_OSC8M) Run in Standby */ |
AnnaBridge | 171:3a7713b1edbc | 486 | #define SYSCTRL_OSC8M_RUNSTDBY (0x1ul << SYSCTRL_OSC8M_RUNSTDBY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 487 | #define SYSCTRL_OSC8M_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_OSC8M) On Demand Control */ |
AnnaBridge | 171:3a7713b1edbc | 488 | #define SYSCTRL_OSC8M_ONDEMAND (0x1ul << SYSCTRL_OSC8M_ONDEMAND_Pos) |
AnnaBridge | 171:3a7713b1edbc | 489 | #define SYSCTRL_OSC8M_PRESC_Pos 8 /**< \brief (SYSCTRL_OSC8M) Oscillator Prescaler */ |
AnnaBridge | 171:3a7713b1edbc | 490 | #define SYSCTRL_OSC8M_PRESC_Msk (0x3ul << SYSCTRL_OSC8M_PRESC_Pos) |
AnnaBridge | 171:3a7713b1edbc | 491 | #define SYSCTRL_OSC8M_PRESC(value) (SYSCTRL_OSC8M_PRESC_Msk & ((value) << SYSCTRL_OSC8M_PRESC_Pos)) |
AnnaBridge | 171:3a7713b1edbc | 492 | #define SYSCTRL_OSC8M_PRESC_0_Val 0x0ul /**< \brief (SYSCTRL_OSC8M) 1 */ |
AnnaBridge | 171:3a7713b1edbc | 493 | #define SYSCTRL_OSC8M_PRESC_1_Val 0x1ul /**< \brief (SYSCTRL_OSC8M) 2 */ |
AnnaBridge | 171:3a7713b1edbc | 494 | #define SYSCTRL_OSC8M_PRESC_2_Val 0x2ul /**< \brief (SYSCTRL_OSC8M) 4 */ |
AnnaBridge | 171:3a7713b1edbc | 495 | #define SYSCTRL_OSC8M_PRESC_3_Val 0x3ul /**< \brief (SYSCTRL_OSC8M) 8 */ |
AnnaBridge | 171:3a7713b1edbc | 496 | #define SYSCTRL_OSC8M_PRESC_0 (SYSCTRL_OSC8M_PRESC_0_Val << SYSCTRL_OSC8M_PRESC_Pos) |
AnnaBridge | 171:3a7713b1edbc | 497 | #define SYSCTRL_OSC8M_PRESC_1 (SYSCTRL_OSC8M_PRESC_1_Val << SYSCTRL_OSC8M_PRESC_Pos) |
AnnaBridge | 171:3a7713b1edbc | 498 | #define SYSCTRL_OSC8M_PRESC_2 (SYSCTRL_OSC8M_PRESC_2_Val << SYSCTRL_OSC8M_PRESC_Pos) |
AnnaBridge | 171:3a7713b1edbc | 499 | #define SYSCTRL_OSC8M_PRESC_3 (SYSCTRL_OSC8M_PRESC_3_Val << SYSCTRL_OSC8M_PRESC_Pos) |
AnnaBridge | 171:3a7713b1edbc | 500 | #define SYSCTRL_OSC8M_CALIB_Pos 16 /**< \brief (SYSCTRL_OSC8M) Oscillator Calibration */ |
AnnaBridge | 171:3a7713b1edbc | 501 | #define SYSCTRL_OSC8M_CALIB_Msk (0xFFFul << SYSCTRL_OSC8M_CALIB_Pos) |
AnnaBridge | 171:3a7713b1edbc | 502 | #define SYSCTRL_OSC8M_CALIB(value) (SYSCTRL_OSC8M_CALIB_Msk & ((value) << SYSCTRL_OSC8M_CALIB_Pos)) |
AnnaBridge | 171:3a7713b1edbc | 503 | #define SYSCTRL_OSC8M_FRANGE_Pos 30 /**< \brief (SYSCTRL_OSC8M) Oscillator Frequency Range */ |
AnnaBridge | 171:3a7713b1edbc | 504 | #define SYSCTRL_OSC8M_FRANGE_Msk (0x3ul << SYSCTRL_OSC8M_FRANGE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 505 | #define SYSCTRL_OSC8M_FRANGE(value) (SYSCTRL_OSC8M_FRANGE_Msk & ((value) << SYSCTRL_OSC8M_FRANGE_Pos)) |
AnnaBridge | 171:3a7713b1edbc | 506 | #define SYSCTRL_OSC8M_FRANGE_0_Val 0x0ul /**< \brief (SYSCTRL_OSC8M) 4 to 6MHz */ |
AnnaBridge | 171:3a7713b1edbc | 507 | #define SYSCTRL_OSC8M_FRANGE_1_Val 0x1ul /**< \brief (SYSCTRL_OSC8M) 6 to 8MHz */ |
AnnaBridge | 171:3a7713b1edbc | 508 | #define SYSCTRL_OSC8M_FRANGE_2_Val 0x2ul /**< \brief (SYSCTRL_OSC8M) 8 to 11MHz */ |
AnnaBridge | 171:3a7713b1edbc | 509 | #define SYSCTRL_OSC8M_FRANGE_3_Val 0x3ul /**< \brief (SYSCTRL_OSC8M) 11 to 15MHz */ |
AnnaBridge | 171:3a7713b1edbc | 510 | #define SYSCTRL_OSC8M_FRANGE_0 (SYSCTRL_OSC8M_FRANGE_0_Val << SYSCTRL_OSC8M_FRANGE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 511 | #define SYSCTRL_OSC8M_FRANGE_1 (SYSCTRL_OSC8M_FRANGE_1_Val << SYSCTRL_OSC8M_FRANGE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 512 | #define SYSCTRL_OSC8M_FRANGE_2 (SYSCTRL_OSC8M_FRANGE_2_Val << SYSCTRL_OSC8M_FRANGE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 513 | #define SYSCTRL_OSC8M_FRANGE_3 (SYSCTRL_OSC8M_FRANGE_3_Val << SYSCTRL_OSC8M_FRANGE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 514 | #define SYSCTRL_OSC8M_MASK 0xCFFF03C2ul /**< \brief (SYSCTRL_OSC8M) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 515 | |
AnnaBridge | 171:3a7713b1edbc | 516 | /* -------- SYSCTRL_DFLLCTRL : (SYSCTRL Offset: 0x24) (R/W 16) DFLL48M Control -------- */ |
AnnaBridge | 171:3a7713b1edbc | 517 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 518 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 519 | struct { |
AnnaBridge | 171:3a7713b1edbc | 520 | uint16_t :1; /*!< bit: 0 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 521 | uint16_t ENABLE:1; /*!< bit: 1 DFLL Enable */ |
AnnaBridge | 171:3a7713b1edbc | 522 | uint16_t MODE:1; /*!< bit: 2 Operating Mode Selection */ |
AnnaBridge | 171:3a7713b1edbc | 523 | uint16_t STABLE:1; /*!< bit: 3 Stable DFLL Frequency */ |
AnnaBridge | 171:3a7713b1edbc | 524 | uint16_t LLAW:1; /*!< bit: 4 Lose Lock After Wake */ |
AnnaBridge | 171:3a7713b1edbc | 525 | uint16_t USBCRM:1; /*!< bit: 5 USB Clock Recovery Mode */ |
AnnaBridge | 171:3a7713b1edbc | 526 | uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ |
AnnaBridge | 171:3a7713b1edbc | 527 | uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ |
AnnaBridge | 171:3a7713b1edbc | 528 | uint16_t CCDIS:1; /*!< bit: 8 Chill Cycle Disable */ |
AnnaBridge | 171:3a7713b1edbc | 529 | uint16_t QLDIS:1; /*!< bit: 9 Quick Lock Disable */ |
AnnaBridge | 171:3a7713b1edbc | 530 | uint16_t BPLCKC:1; /*!< bit: 10 Bypass Coarse Lock */ |
AnnaBridge | 171:3a7713b1edbc | 531 | uint16_t WAITLOCK:1; /*!< bit: 11 Wait Lock */ |
AnnaBridge | 171:3a7713b1edbc | 532 | uint16_t :4; /*!< bit: 12..15 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 533 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 534 | uint16_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 535 | } SYSCTRL_DFLLCTRL_Type; |
AnnaBridge | 171:3a7713b1edbc | 536 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 537 | |
AnnaBridge | 171:3a7713b1edbc | 538 | #define SYSCTRL_DFLLCTRL_OFFSET 0x24 /**< \brief (SYSCTRL_DFLLCTRL offset) DFLL48M Control */ |
AnnaBridge | 171:3a7713b1edbc | 539 | #define SYSCTRL_DFLLCTRL_RESETVALUE 0x0080ul /**< \brief (SYSCTRL_DFLLCTRL reset_value) DFLL48M Control */ |
AnnaBridge | 171:3a7713b1edbc | 540 | |
AnnaBridge | 171:3a7713b1edbc | 541 | #define SYSCTRL_DFLLCTRL_ENABLE_Pos 1 /**< \brief (SYSCTRL_DFLLCTRL) DFLL Enable */ |
AnnaBridge | 171:3a7713b1edbc | 542 | #define SYSCTRL_DFLLCTRL_ENABLE (0x1ul << SYSCTRL_DFLLCTRL_ENABLE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 543 | #define SYSCTRL_DFLLCTRL_MODE_Pos 2 /**< \brief (SYSCTRL_DFLLCTRL) Operating Mode Selection */ |
AnnaBridge | 171:3a7713b1edbc | 544 | #define SYSCTRL_DFLLCTRL_MODE (0x1ul << SYSCTRL_DFLLCTRL_MODE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 545 | #define SYSCTRL_DFLLCTRL_STABLE_Pos 3 /**< \brief (SYSCTRL_DFLLCTRL) Stable DFLL Frequency */ |
AnnaBridge | 171:3a7713b1edbc | 546 | #define SYSCTRL_DFLLCTRL_STABLE (0x1ul << SYSCTRL_DFLLCTRL_STABLE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 547 | #define SYSCTRL_DFLLCTRL_LLAW_Pos 4 /**< \brief (SYSCTRL_DFLLCTRL) Lose Lock After Wake */ |
AnnaBridge | 171:3a7713b1edbc | 548 | #define SYSCTRL_DFLLCTRL_LLAW (0x1ul << SYSCTRL_DFLLCTRL_LLAW_Pos) |
AnnaBridge | 171:3a7713b1edbc | 549 | #define SYSCTRL_DFLLCTRL_USBCRM_Pos 5 /**< \brief (SYSCTRL_DFLLCTRL) USB Clock Recovery Mode */ |
AnnaBridge | 171:3a7713b1edbc | 550 | #define SYSCTRL_DFLLCTRL_USBCRM (0x1ul << SYSCTRL_DFLLCTRL_USBCRM_Pos) |
AnnaBridge | 171:3a7713b1edbc | 551 | #define SYSCTRL_DFLLCTRL_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_DFLLCTRL) Run in Standby */ |
AnnaBridge | 171:3a7713b1edbc | 552 | #define SYSCTRL_DFLLCTRL_RUNSTDBY (0x1ul << SYSCTRL_DFLLCTRL_RUNSTDBY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 553 | #define SYSCTRL_DFLLCTRL_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_DFLLCTRL) On Demand Control */ |
AnnaBridge | 171:3a7713b1edbc | 554 | #define SYSCTRL_DFLLCTRL_ONDEMAND (0x1ul << SYSCTRL_DFLLCTRL_ONDEMAND_Pos) |
AnnaBridge | 171:3a7713b1edbc | 555 | #define SYSCTRL_DFLLCTRL_CCDIS_Pos 8 /**< \brief (SYSCTRL_DFLLCTRL) Chill Cycle Disable */ |
AnnaBridge | 171:3a7713b1edbc | 556 | #define SYSCTRL_DFLLCTRL_CCDIS (0x1ul << SYSCTRL_DFLLCTRL_CCDIS_Pos) |
AnnaBridge | 171:3a7713b1edbc | 557 | #define SYSCTRL_DFLLCTRL_QLDIS_Pos 9 /**< \brief (SYSCTRL_DFLLCTRL) Quick Lock Disable */ |
AnnaBridge | 171:3a7713b1edbc | 558 | #define SYSCTRL_DFLLCTRL_QLDIS (0x1ul << SYSCTRL_DFLLCTRL_QLDIS_Pos) |
AnnaBridge | 171:3a7713b1edbc | 559 | #define SYSCTRL_DFLLCTRL_BPLCKC_Pos 10 /**< \brief (SYSCTRL_DFLLCTRL) Bypass Coarse Lock */ |
AnnaBridge | 171:3a7713b1edbc | 560 | #define SYSCTRL_DFLLCTRL_BPLCKC (0x1ul << SYSCTRL_DFLLCTRL_BPLCKC_Pos) |
AnnaBridge | 171:3a7713b1edbc | 561 | #define SYSCTRL_DFLLCTRL_WAITLOCK_Pos 11 /**< \brief (SYSCTRL_DFLLCTRL) Wait Lock */ |
AnnaBridge | 171:3a7713b1edbc | 562 | #define SYSCTRL_DFLLCTRL_WAITLOCK (0x1ul << SYSCTRL_DFLLCTRL_WAITLOCK_Pos) |
AnnaBridge | 171:3a7713b1edbc | 563 | #define SYSCTRL_DFLLCTRL_MASK 0x0FFEul /**< \brief (SYSCTRL_DFLLCTRL) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 564 | |
AnnaBridge | 171:3a7713b1edbc | 565 | /* -------- SYSCTRL_DFLLVAL : (SYSCTRL Offset: 0x28) (R/W 32) DFLL48M Value -------- */ |
AnnaBridge | 171:3a7713b1edbc | 566 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 567 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 568 | struct { |
AnnaBridge | 171:3a7713b1edbc | 569 | uint32_t FINE:10; /*!< bit: 0.. 9 Fine Value */ |
AnnaBridge | 171:3a7713b1edbc | 570 | uint32_t COARSE:6; /*!< bit: 10..15 Coarse Value */ |
AnnaBridge | 171:3a7713b1edbc | 571 | uint32_t DIFF:16; /*!< bit: 16..31 Multiplication Ratio Difference */ |
AnnaBridge | 171:3a7713b1edbc | 572 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 573 | uint32_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 574 | } SYSCTRL_DFLLVAL_Type; |
AnnaBridge | 171:3a7713b1edbc | 575 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 576 | |
AnnaBridge | 171:3a7713b1edbc | 577 | #define SYSCTRL_DFLLVAL_OFFSET 0x28 /**< \brief (SYSCTRL_DFLLVAL offset) DFLL48M Value */ |
AnnaBridge | 171:3a7713b1edbc | 578 | #define SYSCTRL_DFLLVAL_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_DFLLVAL reset_value) DFLL48M Value */ |
AnnaBridge | 171:3a7713b1edbc | 579 | |
AnnaBridge | 171:3a7713b1edbc | 580 | #define SYSCTRL_DFLLVAL_FINE_Pos 0 /**< \brief (SYSCTRL_DFLLVAL) Fine Value */ |
AnnaBridge | 171:3a7713b1edbc | 581 | #define SYSCTRL_DFLLVAL_FINE_Msk (0x3FFul << SYSCTRL_DFLLVAL_FINE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 582 | #define SYSCTRL_DFLLVAL_FINE(value) (SYSCTRL_DFLLVAL_FINE_Msk & ((value) << SYSCTRL_DFLLVAL_FINE_Pos)) |
AnnaBridge | 171:3a7713b1edbc | 583 | #define SYSCTRL_DFLLVAL_COARSE_Pos 10 /**< \brief (SYSCTRL_DFLLVAL) Coarse Value */ |
AnnaBridge | 171:3a7713b1edbc | 584 | #define SYSCTRL_DFLLVAL_COARSE_Msk (0x3Ful << SYSCTRL_DFLLVAL_COARSE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 585 | #define SYSCTRL_DFLLVAL_COARSE(value) (SYSCTRL_DFLLVAL_COARSE_Msk & ((value) << SYSCTRL_DFLLVAL_COARSE_Pos)) |
AnnaBridge | 171:3a7713b1edbc | 586 | #define SYSCTRL_DFLLVAL_DIFF_Pos 16 /**< \brief (SYSCTRL_DFLLVAL) Multiplication Ratio Difference */ |
AnnaBridge | 171:3a7713b1edbc | 587 | #define SYSCTRL_DFLLVAL_DIFF_Msk (0xFFFFul << SYSCTRL_DFLLVAL_DIFF_Pos) |
AnnaBridge | 171:3a7713b1edbc | 588 | #define SYSCTRL_DFLLVAL_DIFF(value) (SYSCTRL_DFLLVAL_DIFF_Msk & ((value) << SYSCTRL_DFLLVAL_DIFF_Pos)) |
AnnaBridge | 171:3a7713b1edbc | 589 | #define SYSCTRL_DFLLVAL_MASK 0xFFFFFFFFul /**< \brief (SYSCTRL_DFLLVAL) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 590 | |
AnnaBridge | 171:3a7713b1edbc | 591 | /* -------- SYSCTRL_DFLLMUL : (SYSCTRL Offset: 0x2C) (R/W 32) DFLL48M Multiplier -------- */ |
AnnaBridge | 171:3a7713b1edbc | 592 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 593 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 594 | struct { |
AnnaBridge | 171:3a7713b1edbc | 595 | uint32_t MUL:16; /*!< bit: 0..15 DFLL Multiply Factor */ |
AnnaBridge | 171:3a7713b1edbc | 596 | uint32_t FSTEP:10; /*!< bit: 16..25 Fine Maximum Step */ |
AnnaBridge | 171:3a7713b1edbc | 597 | uint32_t CSTEP:6; /*!< bit: 26..31 Coarse Maximum Step */ |
AnnaBridge | 171:3a7713b1edbc | 598 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 599 | uint32_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 600 | } SYSCTRL_DFLLMUL_Type; |
AnnaBridge | 171:3a7713b1edbc | 601 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 602 | |
AnnaBridge | 171:3a7713b1edbc | 603 | #define SYSCTRL_DFLLMUL_OFFSET 0x2C /**< \brief (SYSCTRL_DFLLMUL offset) DFLL48M Multiplier */ |
AnnaBridge | 171:3a7713b1edbc | 604 | #define SYSCTRL_DFLLMUL_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_DFLLMUL reset_value) DFLL48M Multiplier */ |
AnnaBridge | 171:3a7713b1edbc | 605 | |
AnnaBridge | 171:3a7713b1edbc | 606 | #define SYSCTRL_DFLLMUL_MUL_Pos 0 /**< \brief (SYSCTRL_DFLLMUL) DFLL Multiply Factor */ |
AnnaBridge | 171:3a7713b1edbc | 607 | #define SYSCTRL_DFLLMUL_MUL_Msk (0xFFFFul << SYSCTRL_DFLLMUL_MUL_Pos) |
AnnaBridge | 171:3a7713b1edbc | 608 | #define SYSCTRL_DFLLMUL_MUL(value) (SYSCTRL_DFLLMUL_MUL_Msk & ((value) << SYSCTRL_DFLLMUL_MUL_Pos)) |
AnnaBridge | 171:3a7713b1edbc | 609 | #define SYSCTRL_DFLLMUL_FSTEP_Pos 16 /**< \brief (SYSCTRL_DFLLMUL) Fine Maximum Step */ |
AnnaBridge | 171:3a7713b1edbc | 610 | #define SYSCTRL_DFLLMUL_FSTEP_Msk (0x3FFul << SYSCTRL_DFLLMUL_FSTEP_Pos) |
AnnaBridge | 171:3a7713b1edbc | 611 | #define SYSCTRL_DFLLMUL_FSTEP(value) (SYSCTRL_DFLLMUL_FSTEP_Msk & ((value) << SYSCTRL_DFLLMUL_FSTEP_Pos)) |
AnnaBridge | 171:3a7713b1edbc | 612 | #define SYSCTRL_DFLLMUL_CSTEP_Pos 26 /**< \brief (SYSCTRL_DFLLMUL) Coarse Maximum Step */ |
AnnaBridge | 171:3a7713b1edbc | 613 | #define SYSCTRL_DFLLMUL_CSTEP_Msk (0x3Ful << SYSCTRL_DFLLMUL_CSTEP_Pos) |
AnnaBridge | 171:3a7713b1edbc | 614 | #define SYSCTRL_DFLLMUL_CSTEP(value) (SYSCTRL_DFLLMUL_CSTEP_Msk & ((value) << SYSCTRL_DFLLMUL_CSTEP_Pos)) |
AnnaBridge | 171:3a7713b1edbc | 615 | #define SYSCTRL_DFLLMUL_MASK 0xFFFFFFFFul /**< \brief (SYSCTRL_DFLLMUL) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 616 | |
AnnaBridge | 171:3a7713b1edbc | 617 | /* -------- SYSCTRL_DFLLSYNC : (SYSCTRL Offset: 0x30) (R/W 8) DFLL48M Synchronization -------- */ |
AnnaBridge | 171:3a7713b1edbc | 618 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 619 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 620 | struct { |
AnnaBridge | 171:3a7713b1edbc | 621 | uint8_t :7; /*!< bit: 0.. 6 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 622 | uint8_t READREQ:1; /*!< bit: 7 Read Request */ |
AnnaBridge | 171:3a7713b1edbc | 623 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 624 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 625 | } SYSCTRL_DFLLSYNC_Type; |
AnnaBridge | 171:3a7713b1edbc | 626 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 627 | |
AnnaBridge | 171:3a7713b1edbc | 628 | #define SYSCTRL_DFLLSYNC_OFFSET 0x30 /**< \brief (SYSCTRL_DFLLSYNC offset) DFLL48M Synchronization */ |
AnnaBridge | 171:3a7713b1edbc | 629 | #define SYSCTRL_DFLLSYNC_RESETVALUE 0x00ul /**< \brief (SYSCTRL_DFLLSYNC reset_value) DFLL48M Synchronization */ |
AnnaBridge | 171:3a7713b1edbc | 630 | |
AnnaBridge | 171:3a7713b1edbc | 631 | #define SYSCTRL_DFLLSYNC_READREQ_Pos 7 /**< \brief (SYSCTRL_DFLLSYNC) Read Request */ |
AnnaBridge | 171:3a7713b1edbc | 632 | #define SYSCTRL_DFLLSYNC_READREQ (0x1ul << SYSCTRL_DFLLSYNC_READREQ_Pos) |
AnnaBridge | 171:3a7713b1edbc | 633 | #define SYSCTRL_DFLLSYNC_MASK 0x80ul /**< \brief (SYSCTRL_DFLLSYNC) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 634 | |
AnnaBridge | 171:3a7713b1edbc | 635 | /* -------- SYSCTRL_BOD33 : (SYSCTRL Offset: 0x34) (R/W 32) 3.3V Brown-Out Detector (BOD33) Control -------- */ |
AnnaBridge | 171:3a7713b1edbc | 636 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 637 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 638 | struct { |
AnnaBridge | 171:3a7713b1edbc | 639 | uint32_t :1; /*!< bit: 0 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 640 | uint32_t ENABLE:1; /*!< bit: 1 Enable */ |
AnnaBridge | 171:3a7713b1edbc | 641 | uint32_t HYST:1; /*!< bit: 2 Hysteresis */ |
AnnaBridge | 171:3a7713b1edbc | 642 | uint32_t ACTION:2; /*!< bit: 3.. 4 BOD33 Action */ |
AnnaBridge | 171:3a7713b1edbc | 643 | uint32_t :1; /*!< bit: 5 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 644 | uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ |
AnnaBridge | 171:3a7713b1edbc | 645 | uint32_t :1; /*!< bit: 7 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 646 | uint32_t MODE:1; /*!< bit: 8 Operation Mode */ |
AnnaBridge | 171:3a7713b1edbc | 647 | uint32_t CEN:1; /*!< bit: 9 Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 648 | uint32_t :2; /*!< bit: 10..11 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 649 | uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */ |
AnnaBridge | 171:3a7713b1edbc | 650 | uint32_t LEVEL:6; /*!< bit: 16..21 BOD33 Threshold Level */ |
AnnaBridge | 171:3a7713b1edbc | 651 | uint32_t :10; /*!< bit: 22..31 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 652 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 653 | uint32_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 654 | } SYSCTRL_BOD33_Type; |
AnnaBridge | 171:3a7713b1edbc | 655 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 656 | |
AnnaBridge | 171:3a7713b1edbc | 657 | #define SYSCTRL_BOD33_OFFSET 0x34 /**< \brief (SYSCTRL_BOD33 offset) 3.3V Brown-Out Detector (BOD33) Control */ |
AnnaBridge | 171:3a7713b1edbc | 658 | #define SYSCTRL_BOD33_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_BOD33 reset_value) 3.3V Brown-Out Detector (BOD33) Control */ |
AnnaBridge | 171:3a7713b1edbc | 659 | |
AnnaBridge | 171:3a7713b1edbc | 660 | #define SYSCTRL_BOD33_ENABLE_Pos 1 /**< \brief (SYSCTRL_BOD33) Enable */ |
AnnaBridge | 171:3a7713b1edbc | 661 | #define SYSCTRL_BOD33_ENABLE (0x1ul << SYSCTRL_BOD33_ENABLE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 662 | #define SYSCTRL_BOD33_HYST_Pos 2 /**< \brief (SYSCTRL_BOD33) Hysteresis */ |
AnnaBridge | 171:3a7713b1edbc | 663 | #define SYSCTRL_BOD33_HYST (0x1ul << SYSCTRL_BOD33_HYST_Pos) |
AnnaBridge | 171:3a7713b1edbc | 664 | #define SYSCTRL_BOD33_ACTION_Pos 3 /**< \brief (SYSCTRL_BOD33) BOD33 Action */ |
AnnaBridge | 171:3a7713b1edbc | 665 | #define SYSCTRL_BOD33_ACTION_Msk (0x3ul << SYSCTRL_BOD33_ACTION_Pos) |
AnnaBridge | 171:3a7713b1edbc | 666 | #define SYSCTRL_BOD33_ACTION(value) (SYSCTRL_BOD33_ACTION_Msk & ((value) << SYSCTRL_BOD33_ACTION_Pos)) |
AnnaBridge | 171:3a7713b1edbc | 667 | #define SYSCTRL_BOD33_ACTION_NONE_Val 0x0ul /**< \brief (SYSCTRL_BOD33) No action */ |
AnnaBridge | 171:3a7713b1edbc | 668 | #define SYSCTRL_BOD33_ACTION_RESET_Val 0x1ul /**< \brief (SYSCTRL_BOD33) The BOD33 generates a reset */ |
AnnaBridge | 171:3a7713b1edbc | 669 | #define SYSCTRL_BOD33_ACTION_INTERRUPT_Val 0x2ul /**< \brief (SYSCTRL_BOD33) The BOD33 generates an interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 670 | #define SYSCTRL_BOD33_ACTION_NONE (SYSCTRL_BOD33_ACTION_NONE_Val << SYSCTRL_BOD33_ACTION_Pos) |
AnnaBridge | 171:3a7713b1edbc | 671 | #define SYSCTRL_BOD33_ACTION_RESET (SYSCTRL_BOD33_ACTION_RESET_Val << SYSCTRL_BOD33_ACTION_Pos) |
AnnaBridge | 171:3a7713b1edbc | 672 | #define SYSCTRL_BOD33_ACTION_INTERRUPT (SYSCTRL_BOD33_ACTION_INTERRUPT_Val << SYSCTRL_BOD33_ACTION_Pos) |
AnnaBridge | 171:3a7713b1edbc | 673 | #define SYSCTRL_BOD33_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_BOD33) Run in Standby */ |
AnnaBridge | 171:3a7713b1edbc | 674 | #define SYSCTRL_BOD33_RUNSTDBY (0x1ul << SYSCTRL_BOD33_RUNSTDBY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 675 | #define SYSCTRL_BOD33_MODE_Pos 8 /**< \brief (SYSCTRL_BOD33) Operation Mode */ |
AnnaBridge | 171:3a7713b1edbc | 676 | #define SYSCTRL_BOD33_MODE (0x1ul << SYSCTRL_BOD33_MODE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 677 | #define SYSCTRL_BOD33_CEN_Pos 9 /**< \brief (SYSCTRL_BOD33) Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 678 | #define SYSCTRL_BOD33_CEN (0x1ul << SYSCTRL_BOD33_CEN_Pos) |
AnnaBridge | 171:3a7713b1edbc | 679 | #define SYSCTRL_BOD33_PSEL_Pos 12 /**< \brief (SYSCTRL_BOD33) Prescaler Select */ |
AnnaBridge | 171:3a7713b1edbc | 680 | #define SYSCTRL_BOD33_PSEL_Msk (0xFul << SYSCTRL_BOD33_PSEL_Pos) |
AnnaBridge | 171:3a7713b1edbc | 681 | #define SYSCTRL_BOD33_PSEL(value) (SYSCTRL_BOD33_PSEL_Msk & ((value) << SYSCTRL_BOD33_PSEL_Pos)) |
AnnaBridge | 171:3a7713b1edbc | 682 | #define SYSCTRL_BOD33_PSEL_DIV2_Val 0x0ul /**< \brief (SYSCTRL_BOD33) Divide clock by 2 */ |
AnnaBridge | 171:3a7713b1edbc | 683 | #define SYSCTRL_BOD33_PSEL_DIV4_Val 0x1ul /**< \brief (SYSCTRL_BOD33) Divide clock by 4 */ |
AnnaBridge | 171:3a7713b1edbc | 684 | #define SYSCTRL_BOD33_PSEL_DIV8_Val 0x2ul /**< \brief (SYSCTRL_BOD33) Divide clock by 8 */ |
AnnaBridge | 171:3a7713b1edbc | 685 | #define SYSCTRL_BOD33_PSEL_DIV16_Val 0x3ul /**< \brief (SYSCTRL_BOD33) Divide clock by 16 */ |
AnnaBridge | 171:3a7713b1edbc | 686 | #define SYSCTRL_BOD33_PSEL_DIV32_Val 0x4ul /**< \brief (SYSCTRL_BOD33) Divide clock by 32 */ |
AnnaBridge | 171:3a7713b1edbc | 687 | #define SYSCTRL_BOD33_PSEL_DIV64_Val 0x5ul /**< \brief (SYSCTRL_BOD33) Divide clock by 64 */ |
AnnaBridge | 171:3a7713b1edbc | 688 | #define SYSCTRL_BOD33_PSEL_DIV128_Val 0x6ul /**< \brief (SYSCTRL_BOD33) Divide clock by 128 */ |
AnnaBridge | 171:3a7713b1edbc | 689 | #define SYSCTRL_BOD33_PSEL_DIV256_Val 0x7ul /**< \brief (SYSCTRL_BOD33) Divide clock by 256 */ |
AnnaBridge | 171:3a7713b1edbc | 690 | #define SYSCTRL_BOD33_PSEL_DIV512_Val 0x8ul /**< \brief (SYSCTRL_BOD33) Divide clock by 512 */ |
AnnaBridge | 171:3a7713b1edbc | 691 | #define SYSCTRL_BOD33_PSEL_DIV1K_Val 0x9ul /**< \brief (SYSCTRL_BOD33) Divide clock by 1024 */ |
AnnaBridge | 171:3a7713b1edbc | 692 | #define SYSCTRL_BOD33_PSEL_DIV2K_Val 0xAul /**< \brief (SYSCTRL_BOD33) Divide clock by 2048 */ |
AnnaBridge | 171:3a7713b1edbc | 693 | #define SYSCTRL_BOD33_PSEL_DIV4K_Val 0xBul /**< \brief (SYSCTRL_BOD33) Divide clock by 4096 */ |
AnnaBridge | 171:3a7713b1edbc | 694 | #define SYSCTRL_BOD33_PSEL_DIV8K_Val 0xCul /**< \brief (SYSCTRL_BOD33) Divide clock by 8192 */ |
AnnaBridge | 171:3a7713b1edbc | 695 | #define SYSCTRL_BOD33_PSEL_DIV16K_Val 0xDul /**< \brief (SYSCTRL_BOD33) Divide clock by 16384 */ |
AnnaBridge | 171:3a7713b1edbc | 696 | #define SYSCTRL_BOD33_PSEL_DIV32K_Val 0xEul /**< \brief (SYSCTRL_BOD33) Divide clock by 32768 */ |
AnnaBridge | 171:3a7713b1edbc | 697 | #define SYSCTRL_BOD33_PSEL_DIV64K_Val 0xFul /**< \brief (SYSCTRL_BOD33) Divide clock by 65536 */ |
AnnaBridge | 171:3a7713b1edbc | 698 | #define SYSCTRL_BOD33_PSEL_DIV2 (SYSCTRL_BOD33_PSEL_DIV2_Val << SYSCTRL_BOD33_PSEL_Pos) |
AnnaBridge | 171:3a7713b1edbc | 699 | #define SYSCTRL_BOD33_PSEL_DIV4 (SYSCTRL_BOD33_PSEL_DIV4_Val << SYSCTRL_BOD33_PSEL_Pos) |
AnnaBridge | 171:3a7713b1edbc | 700 | #define SYSCTRL_BOD33_PSEL_DIV8 (SYSCTRL_BOD33_PSEL_DIV8_Val << SYSCTRL_BOD33_PSEL_Pos) |
AnnaBridge | 171:3a7713b1edbc | 701 | #define SYSCTRL_BOD33_PSEL_DIV16 (SYSCTRL_BOD33_PSEL_DIV16_Val << SYSCTRL_BOD33_PSEL_Pos) |
AnnaBridge | 171:3a7713b1edbc | 702 | #define SYSCTRL_BOD33_PSEL_DIV32 (SYSCTRL_BOD33_PSEL_DIV32_Val << SYSCTRL_BOD33_PSEL_Pos) |
AnnaBridge | 171:3a7713b1edbc | 703 | #define SYSCTRL_BOD33_PSEL_DIV64 (SYSCTRL_BOD33_PSEL_DIV64_Val << SYSCTRL_BOD33_PSEL_Pos) |
AnnaBridge | 171:3a7713b1edbc | 704 | #define SYSCTRL_BOD33_PSEL_DIV128 (SYSCTRL_BOD33_PSEL_DIV128_Val << SYSCTRL_BOD33_PSEL_Pos) |
AnnaBridge | 171:3a7713b1edbc | 705 | #define SYSCTRL_BOD33_PSEL_DIV256 (SYSCTRL_BOD33_PSEL_DIV256_Val << SYSCTRL_BOD33_PSEL_Pos) |
AnnaBridge | 171:3a7713b1edbc | 706 | #define SYSCTRL_BOD33_PSEL_DIV512 (SYSCTRL_BOD33_PSEL_DIV512_Val << SYSCTRL_BOD33_PSEL_Pos) |
AnnaBridge | 171:3a7713b1edbc | 707 | #define SYSCTRL_BOD33_PSEL_DIV1K (SYSCTRL_BOD33_PSEL_DIV1K_Val << SYSCTRL_BOD33_PSEL_Pos) |
AnnaBridge | 171:3a7713b1edbc | 708 | #define SYSCTRL_BOD33_PSEL_DIV2K (SYSCTRL_BOD33_PSEL_DIV2K_Val << SYSCTRL_BOD33_PSEL_Pos) |
AnnaBridge | 171:3a7713b1edbc | 709 | #define SYSCTRL_BOD33_PSEL_DIV4K (SYSCTRL_BOD33_PSEL_DIV4K_Val << SYSCTRL_BOD33_PSEL_Pos) |
AnnaBridge | 171:3a7713b1edbc | 710 | #define SYSCTRL_BOD33_PSEL_DIV8K (SYSCTRL_BOD33_PSEL_DIV8K_Val << SYSCTRL_BOD33_PSEL_Pos) |
AnnaBridge | 171:3a7713b1edbc | 711 | #define SYSCTRL_BOD33_PSEL_DIV16K (SYSCTRL_BOD33_PSEL_DIV16K_Val << SYSCTRL_BOD33_PSEL_Pos) |
AnnaBridge | 171:3a7713b1edbc | 712 | #define SYSCTRL_BOD33_PSEL_DIV32K (SYSCTRL_BOD33_PSEL_DIV32K_Val << SYSCTRL_BOD33_PSEL_Pos) |
AnnaBridge | 171:3a7713b1edbc | 713 | #define SYSCTRL_BOD33_PSEL_DIV64K (SYSCTRL_BOD33_PSEL_DIV64K_Val << SYSCTRL_BOD33_PSEL_Pos) |
AnnaBridge | 171:3a7713b1edbc | 714 | #define SYSCTRL_BOD33_LEVEL_Pos 16 /**< \brief (SYSCTRL_BOD33) BOD33 Threshold Level */ |
AnnaBridge | 171:3a7713b1edbc | 715 | #define SYSCTRL_BOD33_LEVEL_Msk (0x3Ful << SYSCTRL_BOD33_LEVEL_Pos) |
AnnaBridge | 171:3a7713b1edbc | 716 | #define SYSCTRL_BOD33_LEVEL(value) (SYSCTRL_BOD33_LEVEL_Msk & ((value) << SYSCTRL_BOD33_LEVEL_Pos)) |
AnnaBridge | 171:3a7713b1edbc | 717 | #define SYSCTRL_BOD33_MASK 0x003FF35Eul /**< \brief (SYSCTRL_BOD33) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 718 | |
AnnaBridge | 171:3a7713b1edbc | 719 | /* -------- SYSCTRL_VREG : (SYSCTRL Offset: 0x3C) (R/W 16) Voltage Regulator System (VREG) Control -------- */ |
AnnaBridge | 171:3a7713b1edbc | 720 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 721 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 722 | struct { |
AnnaBridge | 171:3a7713b1edbc | 723 | uint16_t :6; /*!< bit: 0.. 5 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 724 | uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ |
AnnaBridge | 171:3a7713b1edbc | 725 | uint16_t :6; /*!< bit: 7..12 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 726 | uint16_t FORCELDO:1; /*!< bit: 13 Force LDO Voltage Regulator */ |
AnnaBridge | 171:3a7713b1edbc | 727 | uint16_t :2; /*!< bit: 14..15 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 728 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 729 | uint16_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 730 | } SYSCTRL_VREG_Type; |
AnnaBridge | 171:3a7713b1edbc | 731 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 732 | |
AnnaBridge | 171:3a7713b1edbc | 733 | #define SYSCTRL_VREG_OFFSET 0x3C /**< \brief (SYSCTRL_VREG offset) Voltage Regulator System (VREG) Control */ |
AnnaBridge | 171:3a7713b1edbc | 734 | #define SYSCTRL_VREG_RESETVALUE 0x0000ul /**< \brief (SYSCTRL_VREG reset_value) Voltage Regulator System (VREG) Control */ |
AnnaBridge | 171:3a7713b1edbc | 735 | |
AnnaBridge | 171:3a7713b1edbc | 736 | #define SYSCTRL_VREG_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_VREG) Run in Standby */ |
AnnaBridge | 171:3a7713b1edbc | 737 | #define SYSCTRL_VREG_RUNSTDBY (0x1ul << SYSCTRL_VREG_RUNSTDBY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 738 | #define SYSCTRL_VREG_FORCELDO_Pos 13 /**< \brief (SYSCTRL_VREG) Force LDO Voltage Regulator */ |
AnnaBridge | 171:3a7713b1edbc | 739 | #define SYSCTRL_VREG_FORCELDO (0x1ul << SYSCTRL_VREG_FORCELDO_Pos) |
AnnaBridge | 171:3a7713b1edbc | 740 | #define SYSCTRL_VREG_MASK 0x2040ul /**< \brief (SYSCTRL_VREG) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 741 | |
AnnaBridge | 171:3a7713b1edbc | 742 | /* -------- SYSCTRL_VREF : (SYSCTRL Offset: 0x40) (R/W 32) Voltage References System (VREF) Control -------- */ |
AnnaBridge | 171:3a7713b1edbc | 743 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 744 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 745 | struct { |
AnnaBridge | 171:3a7713b1edbc | 746 | uint32_t :1; /*!< bit: 0 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 747 | uint32_t TSEN:1; /*!< bit: 1 Temperature Sensor Enable */ |
AnnaBridge | 171:3a7713b1edbc | 748 | uint32_t BGOUTEN:1; /*!< bit: 2 Bandgap Output Enable */ |
AnnaBridge | 171:3a7713b1edbc | 749 | uint32_t :13; /*!< bit: 3..15 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 750 | uint32_t CALIB:11; /*!< bit: 16..26 Bandgap Voltage Generator Calibration */ |
AnnaBridge | 171:3a7713b1edbc | 751 | uint32_t :5; /*!< bit: 27..31 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 752 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 753 | uint32_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 754 | } SYSCTRL_VREF_Type; |
AnnaBridge | 171:3a7713b1edbc | 755 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 756 | |
AnnaBridge | 171:3a7713b1edbc | 757 | #define SYSCTRL_VREF_OFFSET 0x40 /**< \brief (SYSCTRL_VREF offset) Voltage References System (VREF) Control */ |
AnnaBridge | 171:3a7713b1edbc | 758 | #define SYSCTRL_VREF_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_VREF reset_value) Voltage References System (VREF) Control */ |
AnnaBridge | 171:3a7713b1edbc | 759 | |
AnnaBridge | 171:3a7713b1edbc | 760 | #define SYSCTRL_VREF_TSEN_Pos 1 /**< \brief (SYSCTRL_VREF) Temperature Sensor Enable */ |
AnnaBridge | 171:3a7713b1edbc | 761 | #define SYSCTRL_VREF_TSEN (0x1ul << SYSCTRL_VREF_TSEN_Pos) |
AnnaBridge | 171:3a7713b1edbc | 762 | #define SYSCTRL_VREF_BGOUTEN_Pos 2 /**< \brief (SYSCTRL_VREF) Bandgap Output Enable */ |
AnnaBridge | 171:3a7713b1edbc | 763 | #define SYSCTRL_VREF_BGOUTEN (0x1ul << SYSCTRL_VREF_BGOUTEN_Pos) |
AnnaBridge | 171:3a7713b1edbc | 764 | #define SYSCTRL_VREF_CALIB_Pos 16 /**< \brief (SYSCTRL_VREF) Bandgap Voltage Generator Calibration */ |
AnnaBridge | 171:3a7713b1edbc | 765 | #define SYSCTRL_VREF_CALIB_Msk (0x7FFul << SYSCTRL_VREF_CALIB_Pos) |
AnnaBridge | 171:3a7713b1edbc | 766 | #define SYSCTRL_VREF_CALIB(value) (SYSCTRL_VREF_CALIB_Msk & ((value) << SYSCTRL_VREF_CALIB_Pos)) |
AnnaBridge | 171:3a7713b1edbc | 767 | #define SYSCTRL_VREF_MASK 0x07FF0006ul /**< \brief (SYSCTRL_VREF) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 768 | |
AnnaBridge | 171:3a7713b1edbc | 769 | /* -------- SYSCTRL_DPLLCTRLA : (SYSCTRL Offset: 0x44) (R/W 8) DPLL Control A -------- */ |
AnnaBridge | 171:3a7713b1edbc | 770 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 771 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 772 | struct { |
AnnaBridge | 171:3a7713b1edbc | 773 | uint8_t :1; /*!< bit: 0 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 774 | uint8_t ENABLE:1; /*!< bit: 1 DPLL Enable */ |
AnnaBridge | 171:3a7713b1edbc | 775 | uint8_t :4; /*!< bit: 2.. 5 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 776 | uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ |
AnnaBridge | 171:3a7713b1edbc | 777 | uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Clock Activation */ |
AnnaBridge | 171:3a7713b1edbc | 778 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 779 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 780 | } SYSCTRL_DPLLCTRLA_Type; |
AnnaBridge | 171:3a7713b1edbc | 781 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 782 | |
AnnaBridge | 171:3a7713b1edbc | 783 | #define SYSCTRL_DPLLCTRLA_OFFSET 0x44 /**< \brief (SYSCTRL_DPLLCTRLA offset) DPLL Control A */ |
AnnaBridge | 171:3a7713b1edbc | 784 | #define SYSCTRL_DPLLCTRLA_RESETVALUE 0x80ul /**< \brief (SYSCTRL_DPLLCTRLA reset_value) DPLL Control A */ |
AnnaBridge | 171:3a7713b1edbc | 785 | |
AnnaBridge | 171:3a7713b1edbc | 786 | #define SYSCTRL_DPLLCTRLA_ENABLE_Pos 1 /**< \brief (SYSCTRL_DPLLCTRLA) DPLL Enable */ |
AnnaBridge | 171:3a7713b1edbc | 787 | #define SYSCTRL_DPLLCTRLA_ENABLE (0x1ul << SYSCTRL_DPLLCTRLA_ENABLE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 788 | #define SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_DPLLCTRLA) Run in Standby */ |
AnnaBridge | 171:3a7713b1edbc | 789 | #define SYSCTRL_DPLLCTRLA_RUNSTDBY (0x1ul << SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 790 | #define SYSCTRL_DPLLCTRLA_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_DPLLCTRLA) On Demand Clock Activation */ |
AnnaBridge | 171:3a7713b1edbc | 791 | #define SYSCTRL_DPLLCTRLA_ONDEMAND (0x1ul << SYSCTRL_DPLLCTRLA_ONDEMAND_Pos) |
AnnaBridge | 171:3a7713b1edbc | 792 | #define SYSCTRL_DPLLCTRLA_MASK 0xC2ul /**< \brief (SYSCTRL_DPLLCTRLA) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 793 | |
AnnaBridge | 171:3a7713b1edbc | 794 | /* -------- SYSCTRL_DPLLRATIO : (SYSCTRL Offset: 0x48) (R/W 32) DPLL Ratio Control -------- */ |
AnnaBridge | 171:3a7713b1edbc | 795 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 796 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 797 | struct { |
AnnaBridge | 171:3a7713b1edbc | 798 | uint32_t LDR:12; /*!< bit: 0..11 Loop Divider Ratio */ |
AnnaBridge | 171:3a7713b1edbc | 799 | uint32_t :4; /*!< bit: 12..15 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 800 | uint32_t LDRFRAC:4; /*!< bit: 16..19 Loop Divider Ratio Fractional Part */ |
AnnaBridge | 171:3a7713b1edbc | 801 | uint32_t :12; /*!< bit: 20..31 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 802 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 803 | uint32_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 804 | } SYSCTRL_DPLLRATIO_Type; |
AnnaBridge | 171:3a7713b1edbc | 805 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 806 | |
AnnaBridge | 171:3a7713b1edbc | 807 | #define SYSCTRL_DPLLRATIO_OFFSET 0x48 /**< \brief (SYSCTRL_DPLLRATIO offset) DPLL Ratio Control */ |
AnnaBridge | 171:3a7713b1edbc | 808 | #define SYSCTRL_DPLLRATIO_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_DPLLRATIO reset_value) DPLL Ratio Control */ |
AnnaBridge | 171:3a7713b1edbc | 809 | |
AnnaBridge | 171:3a7713b1edbc | 810 | #define SYSCTRL_DPLLRATIO_LDR_Pos 0 /**< \brief (SYSCTRL_DPLLRATIO) Loop Divider Ratio */ |
AnnaBridge | 171:3a7713b1edbc | 811 | #define SYSCTRL_DPLLRATIO_LDR_Msk (0xFFFul << SYSCTRL_DPLLRATIO_LDR_Pos) |
AnnaBridge | 171:3a7713b1edbc | 812 | #define SYSCTRL_DPLLRATIO_LDR(value) (SYSCTRL_DPLLRATIO_LDR_Msk & ((value) << SYSCTRL_DPLLRATIO_LDR_Pos)) |
AnnaBridge | 171:3a7713b1edbc | 813 | #define SYSCTRL_DPLLRATIO_LDRFRAC_Pos 16 /**< \brief (SYSCTRL_DPLLRATIO) Loop Divider Ratio Fractional Part */ |
AnnaBridge | 171:3a7713b1edbc | 814 | #define SYSCTRL_DPLLRATIO_LDRFRAC_Msk (0xFul << SYSCTRL_DPLLRATIO_LDRFRAC_Pos) |
AnnaBridge | 171:3a7713b1edbc | 815 | #define SYSCTRL_DPLLRATIO_LDRFRAC(value) (SYSCTRL_DPLLRATIO_LDRFRAC_Msk & ((value) << SYSCTRL_DPLLRATIO_LDRFRAC_Pos)) |
AnnaBridge | 171:3a7713b1edbc | 816 | #define SYSCTRL_DPLLRATIO_MASK 0x000F0FFFul /**< \brief (SYSCTRL_DPLLRATIO) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 817 | |
AnnaBridge | 171:3a7713b1edbc | 818 | /* -------- SYSCTRL_DPLLCTRLB : (SYSCTRL Offset: 0x4C) (R/W 32) DPLL Control B -------- */ |
AnnaBridge | 171:3a7713b1edbc | 819 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 820 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 821 | struct { |
AnnaBridge | 171:3a7713b1edbc | 822 | uint32_t FILTER:2; /*!< bit: 0.. 1 Proportional Integral Filter Selection */ |
AnnaBridge | 171:3a7713b1edbc | 823 | uint32_t LPEN:1; /*!< bit: 2 Low-Power Enable */ |
AnnaBridge | 171:3a7713b1edbc | 824 | uint32_t WUF:1; /*!< bit: 3 Wake Up Fast */ |
AnnaBridge | 171:3a7713b1edbc | 825 | uint32_t REFCLK:2; /*!< bit: 4.. 5 Reference Clock Selection */ |
AnnaBridge | 171:3a7713b1edbc | 826 | uint32_t :2; /*!< bit: 6.. 7 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 827 | uint32_t LTIME:3; /*!< bit: 8..10 Lock Time */ |
AnnaBridge | 171:3a7713b1edbc | 828 | uint32_t :1; /*!< bit: 11 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 829 | uint32_t LBYPASS:1; /*!< bit: 12 Lock Bypass */ |
AnnaBridge | 171:3a7713b1edbc | 830 | uint32_t :3; /*!< bit: 13..15 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 831 | uint32_t DIV:11; /*!< bit: 16..26 Clock Divider */ |
AnnaBridge | 171:3a7713b1edbc | 832 | uint32_t :5; /*!< bit: 27..31 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 833 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 834 | uint32_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 835 | } SYSCTRL_DPLLCTRLB_Type; |
AnnaBridge | 171:3a7713b1edbc | 836 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 837 | |
AnnaBridge | 171:3a7713b1edbc | 838 | #define SYSCTRL_DPLLCTRLB_OFFSET 0x4C /**< \brief (SYSCTRL_DPLLCTRLB offset) DPLL Control B */ |
AnnaBridge | 171:3a7713b1edbc | 839 | #define SYSCTRL_DPLLCTRLB_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_DPLLCTRLB reset_value) DPLL Control B */ |
AnnaBridge | 171:3a7713b1edbc | 840 | |
AnnaBridge | 171:3a7713b1edbc | 841 | #define SYSCTRL_DPLLCTRLB_FILTER_Pos 0 /**< \brief (SYSCTRL_DPLLCTRLB) Proportional Integral Filter Selection */ |
AnnaBridge | 171:3a7713b1edbc | 842 | #define SYSCTRL_DPLLCTRLB_FILTER_Msk (0x3ul << SYSCTRL_DPLLCTRLB_FILTER_Pos) |
AnnaBridge | 171:3a7713b1edbc | 843 | #define SYSCTRL_DPLLCTRLB_FILTER(value) (SYSCTRL_DPLLCTRLB_FILTER_Msk & ((value) << SYSCTRL_DPLLCTRLB_FILTER_Pos)) |
AnnaBridge | 171:3a7713b1edbc | 844 | #define SYSCTRL_DPLLCTRLB_FILTER_DEFAULT_Val 0x0ul /**< \brief (SYSCTRL_DPLLCTRLB) Default filter mode */ |
AnnaBridge | 171:3a7713b1edbc | 845 | #define SYSCTRL_DPLLCTRLB_FILTER_LBFILT_Val 0x1ul /**< \brief (SYSCTRL_DPLLCTRLB) Low bandwidth filter */ |
AnnaBridge | 171:3a7713b1edbc | 846 | #define SYSCTRL_DPLLCTRLB_FILTER_HBFILT_Val 0x2ul /**< \brief (SYSCTRL_DPLLCTRLB) High bandwidth filter */ |
AnnaBridge | 171:3a7713b1edbc | 847 | #define SYSCTRL_DPLLCTRLB_FILTER_HDFILT_Val 0x3ul /**< \brief (SYSCTRL_DPLLCTRLB) High damping filter */ |
AnnaBridge | 171:3a7713b1edbc | 848 | #define SYSCTRL_DPLLCTRLB_FILTER_DEFAULT (SYSCTRL_DPLLCTRLB_FILTER_DEFAULT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos) |
AnnaBridge | 171:3a7713b1edbc | 849 | #define SYSCTRL_DPLLCTRLB_FILTER_LBFILT (SYSCTRL_DPLLCTRLB_FILTER_LBFILT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos) |
AnnaBridge | 171:3a7713b1edbc | 850 | #define SYSCTRL_DPLLCTRLB_FILTER_HBFILT (SYSCTRL_DPLLCTRLB_FILTER_HBFILT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos) |
AnnaBridge | 171:3a7713b1edbc | 851 | #define SYSCTRL_DPLLCTRLB_FILTER_HDFILT (SYSCTRL_DPLLCTRLB_FILTER_HDFILT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos) |
AnnaBridge | 171:3a7713b1edbc | 852 | #define SYSCTRL_DPLLCTRLB_LPEN_Pos 2 /**< \brief (SYSCTRL_DPLLCTRLB) Low-Power Enable */ |
AnnaBridge | 171:3a7713b1edbc | 853 | #define SYSCTRL_DPLLCTRLB_LPEN (0x1ul << SYSCTRL_DPLLCTRLB_LPEN_Pos) |
AnnaBridge | 171:3a7713b1edbc | 854 | #define SYSCTRL_DPLLCTRLB_WUF_Pos 3 /**< \brief (SYSCTRL_DPLLCTRLB) Wake Up Fast */ |
AnnaBridge | 171:3a7713b1edbc | 855 | #define SYSCTRL_DPLLCTRLB_WUF (0x1ul << SYSCTRL_DPLLCTRLB_WUF_Pos) |
AnnaBridge | 171:3a7713b1edbc | 856 | #define SYSCTRL_DPLLCTRLB_REFCLK_Pos 4 /**< \brief (SYSCTRL_DPLLCTRLB) Reference Clock Selection */ |
AnnaBridge | 171:3a7713b1edbc | 857 | #define SYSCTRL_DPLLCTRLB_REFCLK_Msk (0x3ul << SYSCTRL_DPLLCTRLB_REFCLK_Pos) |
AnnaBridge | 171:3a7713b1edbc | 858 | #define SYSCTRL_DPLLCTRLB_REFCLK(value) (SYSCTRL_DPLLCTRLB_REFCLK_Msk & ((value) << SYSCTRL_DPLLCTRLB_REFCLK_Pos)) |
AnnaBridge | 171:3a7713b1edbc | 859 | #define SYSCTRL_DPLLCTRLB_REFCLK_REF0_Val 0x0ul /**< \brief (SYSCTRL_DPLLCTRLB) CLK_DPLL_REF0 clock reference */ |
AnnaBridge | 171:3a7713b1edbc | 860 | #define SYSCTRL_DPLLCTRLB_REFCLK_REF1_Val 0x1ul /**< \brief (SYSCTRL_DPLLCTRLB) CLK_DPLL_REF1 clock reference */ |
AnnaBridge | 171:3a7713b1edbc | 861 | #define SYSCTRL_DPLLCTRLB_REFCLK_GCLK_Val 0x2ul /**< \brief (SYSCTRL_DPLLCTRLB) GCLK_DPLL clock reference */ |
AnnaBridge | 171:3a7713b1edbc | 862 | #define SYSCTRL_DPLLCTRLB_REFCLK_REF0 (SYSCTRL_DPLLCTRLB_REFCLK_REF0_Val << SYSCTRL_DPLLCTRLB_REFCLK_Pos) |
AnnaBridge | 171:3a7713b1edbc | 863 | #define SYSCTRL_DPLLCTRLB_REFCLK_REF1 (SYSCTRL_DPLLCTRLB_REFCLK_REF1_Val << SYSCTRL_DPLLCTRLB_REFCLK_Pos) |
AnnaBridge | 171:3a7713b1edbc | 864 | #define SYSCTRL_DPLLCTRLB_REFCLK_GCLK (SYSCTRL_DPLLCTRLB_REFCLK_GCLK_Val << SYSCTRL_DPLLCTRLB_REFCLK_Pos) |
AnnaBridge | 171:3a7713b1edbc | 865 | #define SYSCTRL_DPLLCTRLB_LTIME_Pos 8 /**< \brief (SYSCTRL_DPLLCTRLB) Lock Time */ |
AnnaBridge | 171:3a7713b1edbc | 866 | #define SYSCTRL_DPLLCTRLB_LTIME_Msk (0x7ul << SYSCTRL_DPLLCTRLB_LTIME_Pos) |
AnnaBridge | 171:3a7713b1edbc | 867 | #define SYSCTRL_DPLLCTRLB_LTIME(value) (SYSCTRL_DPLLCTRLB_LTIME_Msk & ((value) << SYSCTRL_DPLLCTRLB_LTIME_Pos)) |
AnnaBridge | 171:3a7713b1edbc | 868 | #define SYSCTRL_DPLLCTRLB_LTIME_DEFAULT_Val 0x0ul /**< \brief (SYSCTRL_DPLLCTRLB) No time-out */ |
AnnaBridge | 171:3a7713b1edbc | 869 | #define SYSCTRL_DPLLCTRLB_LTIME_8MS_Val 0x4ul /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 8 ms */ |
AnnaBridge | 171:3a7713b1edbc | 870 | #define SYSCTRL_DPLLCTRLB_LTIME_9MS_Val 0x5ul /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 9 ms */ |
AnnaBridge | 171:3a7713b1edbc | 871 | #define SYSCTRL_DPLLCTRLB_LTIME_10MS_Val 0x6ul /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 10 ms */ |
AnnaBridge | 171:3a7713b1edbc | 872 | #define SYSCTRL_DPLLCTRLB_LTIME_11MS_Val 0x7ul /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 11 ms */ |
AnnaBridge | 171:3a7713b1edbc | 873 | #define SYSCTRL_DPLLCTRLB_LTIME_DEFAULT (SYSCTRL_DPLLCTRLB_LTIME_DEFAULT_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos) |
AnnaBridge | 171:3a7713b1edbc | 874 | #define SYSCTRL_DPLLCTRLB_LTIME_8MS (SYSCTRL_DPLLCTRLB_LTIME_8MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos) |
AnnaBridge | 171:3a7713b1edbc | 875 | #define SYSCTRL_DPLLCTRLB_LTIME_9MS (SYSCTRL_DPLLCTRLB_LTIME_9MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos) |
AnnaBridge | 171:3a7713b1edbc | 876 | #define SYSCTRL_DPLLCTRLB_LTIME_10MS (SYSCTRL_DPLLCTRLB_LTIME_10MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos) |
AnnaBridge | 171:3a7713b1edbc | 877 | #define SYSCTRL_DPLLCTRLB_LTIME_11MS (SYSCTRL_DPLLCTRLB_LTIME_11MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos) |
AnnaBridge | 171:3a7713b1edbc | 878 | #define SYSCTRL_DPLLCTRLB_LBYPASS_Pos 12 /**< \brief (SYSCTRL_DPLLCTRLB) Lock Bypass */ |
AnnaBridge | 171:3a7713b1edbc | 879 | #define SYSCTRL_DPLLCTRLB_LBYPASS (0x1ul << SYSCTRL_DPLLCTRLB_LBYPASS_Pos) |
AnnaBridge | 171:3a7713b1edbc | 880 | #define SYSCTRL_DPLLCTRLB_DIV_Pos 16 /**< \brief (SYSCTRL_DPLLCTRLB) Clock Divider */ |
AnnaBridge | 171:3a7713b1edbc | 881 | #define SYSCTRL_DPLLCTRLB_DIV_Msk (0x7FFul << SYSCTRL_DPLLCTRLB_DIV_Pos) |
AnnaBridge | 171:3a7713b1edbc | 882 | #define SYSCTRL_DPLLCTRLB_DIV(value) (SYSCTRL_DPLLCTRLB_DIV_Msk & ((value) << SYSCTRL_DPLLCTRLB_DIV_Pos)) |
AnnaBridge | 171:3a7713b1edbc | 883 | #define SYSCTRL_DPLLCTRLB_MASK 0x07FF173Ful /**< \brief (SYSCTRL_DPLLCTRLB) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 884 | |
AnnaBridge | 171:3a7713b1edbc | 885 | /* -------- SYSCTRL_DPLLSTATUS : (SYSCTRL Offset: 0x50) (R/ 8) DPLL Status -------- */ |
AnnaBridge | 171:3a7713b1edbc | 886 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 887 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 888 | struct { |
AnnaBridge | 171:3a7713b1edbc | 889 | uint8_t LOCK:1; /*!< bit: 0 DPLL Lock Status */ |
AnnaBridge | 171:3a7713b1edbc | 890 | uint8_t CLKRDY:1; /*!< bit: 1 Output Clock Ready */ |
AnnaBridge | 171:3a7713b1edbc | 891 | uint8_t ENABLE:1; /*!< bit: 2 DPLL Enable */ |
AnnaBridge | 171:3a7713b1edbc | 892 | uint8_t DIV:1; /*!< bit: 3 Divider Enable */ |
AnnaBridge | 171:3a7713b1edbc | 893 | uint8_t :4; /*!< bit: 4.. 7 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 894 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 895 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 896 | } SYSCTRL_DPLLSTATUS_Type; |
AnnaBridge | 171:3a7713b1edbc | 897 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 898 | |
AnnaBridge | 171:3a7713b1edbc | 899 | #define SYSCTRL_DPLLSTATUS_OFFSET 0x50 /**< \brief (SYSCTRL_DPLLSTATUS offset) DPLL Status */ |
AnnaBridge | 171:3a7713b1edbc | 900 | #define SYSCTRL_DPLLSTATUS_RESETVALUE 0x00ul /**< \brief (SYSCTRL_DPLLSTATUS reset_value) DPLL Status */ |
AnnaBridge | 171:3a7713b1edbc | 901 | |
AnnaBridge | 171:3a7713b1edbc | 902 | #define SYSCTRL_DPLLSTATUS_LOCK_Pos 0 /**< \brief (SYSCTRL_DPLLSTATUS) DPLL Lock Status */ |
AnnaBridge | 171:3a7713b1edbc | 903 | #define SYSCTRL_DPLLSTATUS_LOCK (0x1ul << SYSCTRL_DPLLSTATUS_LOCK_Pos) |
AnnaBridge | 171:3a7713b1edbc | 904 | #define SYSCTRL_DPLLSTATUS_CLKRDY_Pos 1 /**< \brief (SYSCTRL_DPLLSTATUS) Output Clock Ready */ |
AnnaBridge | 171:3a7713b1edbc | 905 | #define SYSCTRL_DPLLSTATUS_CLKRDY (0x1ul << SYSCTRL_DPLLSTATUS_CLKRDY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 906 | #define SYSCTRL_DPLLSTATUS_ENABLE_Pos 2 /**< \brief (SYSCTRL_DPLLSTATUS) DPLL Enable */ |
AnnaBridge | 171:3a7713b1edbc | 907 | #define SYSCTRL_DPLLSTATUS_ENABLE (0x1ul << SYSCTRL_DPLLSTATUS_ENABLE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 908 | #define SYSCTRL_DPLLSTATUS_DIV_Pos 3 /**< \brief (SYSCTRL_DPLLSTATUS) Divider Enable */ |
AnnaBridge | 171:3a7713b1edbc | 909 | #define SYSCTRL_DPLLSTATUS_DIV (0x1ul << SYSCTRL_DPLLSTATUS_DIV_Pos) |
AnnaBridge | 171:3a7713b1edbc | 910 | #define SYSCTRL_DPLLSTATUS_MASK 0x0Ful /**< \brief (SYSCTRL_DPLLSTATUS) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 911 | |
AnnaBridge | 171:3a7713b1edbc | 912 | /** \brief SYSCTRL hardware registers */ |
AnnaBridge | 171:3a7713b1edbc | 913 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 914 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 915 | __IO SYSCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */ |
AnnaBridge | 171:3a7713b1edbc | 916 | __IO SYSCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */ |
AnnaBridge | 171:3a7713b1edbc | 917 | __IO SYSCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */ |
AnnaBridge | 171:3a7713b1edbc | 918 | __I SYSCTRL_PCLKSR_Type PCLKSR; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */ |
AnnaBridge | 171:3a7713b1edbc | 919 | __IO SYSCTRL_XOSC_Type XOSC; /**< \brief Offset: 0x10 (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control */ |
AnnaBridge | 171:3a7713b1edbc | 920 | RoReg8 Reserved1[0x2]; |
AnnaBridge | 171:3a7713b1edbc | 921 | __IO SYSCTRL_XOSC32K_Type XOSC32K; /**< \brief Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control */ |
AnnaBridge | 171:3a7713b1edbc | 922 | RoReg8 Reserved2[0x2]; |
AnnaBridge | 171:3a7713b1edbc | 923 | __IO SYSCTRL_OSC32K_Type OSC32K; /**< \brief Offset: 0x18 (R/W 32) 32kHz Internal Oscillator (OSC32K) Control */ |
AnnaBridge | 171:3a7713b1edbc | 924 | __IO SYSCTRL_OSCULP32K_Type OSCULP32K; /**< \brief Offset: 0x1C (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ |
AnnaBridge | 171:3a7713b1edbc | 925 | RoReg8 Reserved3[0x3]; |
AnnaBridge | 171:3a7713b1edbc | 926 | __IO SYSCTRL_OSC8M_Type OSC8M; /**< \brief Offset: 0x20 (R/W 32) 8MHz Internal Oscillator (OSC8M) Control */ |
AnnaBridge | 171:3a7713b1edbc | 927 | __IO SYSCTRL_DFLLCTRL_Type DFLLCTRL; /**< \brief Offset: 0x24 (R/W 16) DFLL48M Control */ |
AnnaBridge | 171:3a7713b1edbc | 928 | RoReg8 Reserved4[0x2]; |
AnnaBridge | 171:3a7713b1edbc | 929 | __IO SYSCTRL_DFLLVAL_Type DFLLVAL; /**< \brief Offset: 0x28 (R/W 32) DFLL48M Value */ |
AnnaBridge | 171:3a7713b1edbc | 930 | __IO SYSCTRL_DFLLMUL_Type DFLLMUL; /**< \brief Offset: 0x2C (R/W 32) DFLL48M Multiplier */ |
AnnaBridge | 171:3a7713b1edbc | 931 | __IO SYSCTRL_DFLLSYNC_Type DFLLSYNC; /**< \brief Offset: 0x30 (R/W 8) DFLL48M Synchronization */ |
AnnaBridge | 171:3a7713b1edbc | 932 | RoReg8 Reserved5[0x3]; |
AnnaBridge | 171:3a7713b1edbc | 933 | __IO SYSCTRL_BOD33_Type BOD33; /**< \brief Offset: 0x34 (R/W 32) 3.3V Brown-Out Detector (BOD33) Control */ |
AnnaBridge | 171:3a7713b1edbc | 934 | RoReg8 Reserved6[0x4]; |
AnnaBridge | 171:3a7713b1edbc | 935 | __IO SYSCTRL_VREG_Type VREG; /**< \brief Offset: 0x3C (R/W 16) Voltage Regulator System (VREG) Control */ |
AnnaBridge | 171:3a7713b1edbc | 936 | RoReg8 Reserved7[0x2]; |
AnnaBridge | 171:3a7713b1edbc | 937 | __IO SYSCTRL_VREF_Type VREF; /**< \brief Offset: 0x40 (R/W 32) Voltage References System (VREF) Control */ |
AnnaBridge | 171:3a7713b1edbc | 938 | __IO SYSCTRL_DPLLCTRLA_Type DPLLCTRLA; /**< \brief Offset: 0x44 (R/W 8) DPLL Control A */ |
AnnaBridge | 171:3a7713b1edbc | 939 | RoReg8 Reserved8[0x3]; |
AnnaBridge | 171:3a7713b1edbc | 940 | __IO SYSCTRL_DPLLRATIO_Type DPLLRATIO; /**< \brief Offset: 0x48 (R/W 32) DPLL Ratio Control */ |
AnnaBridge | 171:3a7713b1edbc | 941 | __IO SYSCTRL_DPLLCTRLB_Type DPLLCTRLB; /**< \brief Offset: 0x4C (R/W 32) DPLL Control B */ |
AnnaBridge | 171:3a7713b1edbc | 942 | __I SYSCTRL_DPLLSTATUS_Type DPLLSTATUS; /**< \brief Offset: 0x50 (R/ 8) DPLL Status */ |
AnnaBridge | 171:3a7713b1edbc | 943 | } Sysctrl; |
AnnaBridge | 171:3a7713b1edbc | 944 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 945 | |
AnnaBridge | 171:3a7713b1edbc | 946 | /*@}*/ |
AnnaBridge | 171:3a7713b1edbc | 947 | |
AnnaBridge | 171:3a7713b1edbc | 948 | #endif /* _SAMR21_SYSCTRL_COMPONENT_ */ |