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TARGET_NUCLEO_L496ZG_P/TOOLCHAIN_ARM_STD/stm32l4xx_hal_rcc.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
- Parent:
- TARGET_DISCO_L475VG_IOT01A/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h@161:aa5281ff4a02
mbed library. Release version 164
Who changed what in which revision?
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AnnaBridge | 145:64910690c574 | 1 | /** |
AnnaBridge | 145:64910690c574 | 2 | ****************************************************************************** |
AnnaBridge | 145:64910690c574 | 3 | * @file stm32l4xx_hal_rcc.h |
AnnaBridge | 145:64910690c574 | 4 | * @author MCD Application Team |
AnnaBridge | 145:64910690c574 | 5 | * @brief Header file of RCC HAL module. |
AnnaBridge | 145:64910690c574 | 6 | ****************************************************************************** |
AnnaBridge | 145:64910690c574 | 7 | * @attention |
AnnaBridge | 145:64910690c574 | 8 | * |
AnnaBridge | 145:64910690c574 | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
AnnaBridge | 145:64910690c574 | 10 | * |
AnnaBridge | 145:64910690c574 | 11 | * Redistribution and use in source and binary forms, with or without modification, |
AnnaBridge | 145:64910690c574 | 12 | * are permitted provided that the following conditions are met: |
AnnaBridge | 145:64910690c574 | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 145:64910690c574 | 14 | * this list of conditions and the following disclaimer. |
AnnaBridge | 145:64910690c574 | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 145:64910690c574 | 16 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 145:64910690c574 | 17 | * and/or other materials provided with the distribution. |
AnnaBridge | 145:64910690c574 | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
AnnaBridge | 145:64910690c574 | 19 | * may be used to endorse or promote products derived from this software |
AnnaBridge | 145:64910690c574 | 20 | * without specific prior written permission. |
AnnaBridge | 145:64910690c574 | 21 | * |
AnnaBridge | 145:64910690c574 | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
AnnaBridge | 145:64910690c574 | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
AnnaBridge | 145:64910690c574 | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 145:64910690c574 | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
AnnaBridge | 145:64910690c574 | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 145:64910690c574 | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
AnnaBridge | 145:64910690c574 | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
AnnaBridge | 145:64910690c574 | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
AnnaBridge | 145:64910690c574 | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
AnnaBridge | 145:64910690c574 | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 145:64910690c574 | 32 | * |
AnnaBridge | 145:64910690c574 | 33 | ****************************************************************************** |
AnnaBridge | 145:64910690c574 | 34 | */ |
AnnaBridge | 145:64910690c574 | 35 | |
AnnaBridge | 145:64910690c574 | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 37 | #ifndef __STM32L4xx_HAL_RCC_H |
AnnaBridge | 145:64910690c574 | 38 | #define __STM32L4xx_HAL_RCC_H |
AnnaBridge | 145:64910690c574 | 39 | |
AnnaBridge | 145:64910690c574 | 40 | #ifdef __cplusplus |
AnnaBridge | 145:64910690c574 | 41 | extern "C" { |
AnnaBridge | 145:64910690c574 | 42 | #endif |
AnnaBridge | 145:64910690c574 | 43 | |
AnnaBridge | 145:64910690c574 | 44 | /* Includes ------------------------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 45 | #include "stm32l4xx_hal_def.h" |
AnnaBridge | 145:64910690c574 | 46 | |
AnnaBridge | 145:64910690c574 | 47 | /** @addtogroup STM32L4xx_HAL_Driver |
AnnaBridge | 145:64910690c574 | 48 | * @{ |
AnnaBridge | 145:64910690c574 | 49 | */ |
AnnaBridge | 145:64910690c574 | 50 | |
AnnaBridge | 145:64910690c574 | 51 | /** @addtogroup RCC |
AnnaBridge | 145:64910690c574 | 52 | * @{ |
AnnaBridge | 145:64910690c574 | 53 | */ |
AnnaBridge | 145:64910690c574 | 54 | |
AnnaBridge | 145:64910690c574 | 55 | /* Exported types ------------------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 56 | /** @defgroup RCC_Exported_Types RCC Exported Types |
AnnaBridge | 145:64910690c574 | 57 | * @{ |
AnnaBridge | 145:64910690c574 | 58 | */ |
AnnaBridge | 145:64910690c574 | 59 | |
AnnaBridge | 145:64910690c574 | 60 | /** |
AnnaBridge | 145:64910690c574 | 61 | * @brief RCC PLL configuration structure definition |
AnnaBridge | 145:64910690c574 | 62 | */ |
AnnaBridge | 145:64910690c574 | 63 | typedef struct |
AnnaBridge | 145:64910690c574 | 64 | { |
AnnaBridge | 145:64910690c574 | 65 | uint32_t PLLState; /*!< The new state of the PLL. |
AnnaBridge | 145:64910690c574 | 66 | This parameter can be a value of @ref RCC_PLL_Config */ |
AnnaBridge | 145:64910690c574 | 67 | |
AnnaBridge | 145:64910690c574 | 68 | uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. |
AnnaBridge | 145:64910690c574 | 69 | This parameter must be a value of @ref RCC_PLL_Clock_Source */ |
AnnaBridge | 145:64910690c574 | 70 | |
AnnaBridge | 145:64910690c574 | 71 | uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. |
AnnaBridge | 161:aa5281ff4a02 | 72 | This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices. |
AnnaBridge | 161:aa5281ff4a02 | 73 | This parameter must be a number between Min_Data = 1 and Max_Data = 8 on the other devices */ |
AnnaBridge | 145:64910690c574 | 74 | |
AnnaBridge | 145:64910690c574 | 75 | uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. |
AnnaBridge | 145:64910690c574 | 76 | This parameter must be a number between Min_Data = 8 and Max_Data = 86 */ |
AnnaBridge | 145:64910690c574 | 77 | |
AnnaBridge | 145:64910690c574 | 78 | uint32_t PLLP; /*!< PLLP: Division factor for SAI clock. |
AnnaBridge | 145:64910690c574 | 79 | This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ |
AnnaBridge | 145:64910690c574 | 80 | |
AnnaBridge | 145:64910690c574 | 81 | uint32_t PLLQ; /*!< PLLQ: Division factor for SDMMC1, RNG and USB clocks. |
AnnaBridge | 145:64910690c574 | 82 | This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ |
AnnaBridge | 145:64910690c574 | 83 | |
AnnaBridge | 145:64910690c574 | 84 | uint32_t PLLR; /*!< PLLR: Division for the main system clock. |
AnnaBridge | 145:64910690c574 | 85 | User have to set the PLLR parameter correctly to not exceed max frequency 80MHZ. |
AnnaBridge | 145:64910690c574 | 86 | This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ |
AnnaBridge | 145:64910690c574 | 87 | |
AnnaBridge | 145:64910690c574 | 88 | }RCC_PLLInitTypeDef; |
AnnaBridge | 145:64910690c574 | 89 | |
AnnaBridge | 145:64910690c574 | 90 | /** |
AnnaBridge | 145:64910690c574 | 91 | * @brief RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) configuration structure definition |
AnnaBridge | 145:64910690c574 | 92 | */ |
AnnaBridge | 145:64910690c574 | 93 | typedef struct |
AnnaBridge | 145:64910690c574 | 94 | { |
AnnaBridge | 145:64910690c574 | 95 | uint32_t OscillatorType; /*!< The oscillators to be configured. |
AnnaBridge | 145:64910690c574 | 96 | This parameter can be a value of @ref RCC_Oscillator_Type */ |
AnnaBridge | 145:64910690c574 | 97 | |
AnnaBridge | 145:64910690c574 | 98 | uint32_t HSEState; /*!< The new state of the HSE. |
AnnaBridge | 145:64910690c574 | 99 | This parameter can be a value of @ref RCC_HSE_Config */ |
AnnaBridge | 145:64910690c574 | 100 | |
AnnaBridge | 145:64910690c574 | 101 | uint32_t LSEState; /*!< The new state of the LSE. |
AnnaBridge | 145:64910690c574 | 102 | This parameter can be a value of @ref RCC_LSE_Config */ |
AnnaBridge | 145:64910690c574 | 103 | |
AnnaBridge | 145:64910690c574 | 104 | uint32_t HSIState; /*!< The new state of the HSI. |
AnnaBridge | 145:64910690c574 | 105 | This parameter can be a value of @ref RCC_HSI_Config */ |
AnnaBridge | 145:64910690c574 | 106 | |
AnnaBridge | 145:64910690c574 | 107 | uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). |
AnnaBridge | 145:64910690c574 | 108 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F on STM32L43x/STM32L44x/STM32L47x/STM32L48x devices. |
AnnaBridge | 145:64910690c574 | 109 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F on the other devices */ |
AnnaBridge | 145:64910690c574 | 110 | |
AnnaBridge | 145:64910690c574 | 111 | uint32_t LSIState; /*!< The new state of the LSI. |
AnnaBridge | 145:64910690c574 | 112 | This parameter can be a value of @ref RCC_LSI_Config */ |
AnnaBridge | 145:64910690c574 | 113 | |
AnnaBridge | 145:64910690c574 | 114 | uint32_t MSIState; /*!< The new state of the MSI. |
AnnaBridge | 145:64910690c574 | 115 | This parameter can be a value of @ref RCC_MSI_Config */ |
AnnaBridge | 145:64910690c574 | 116 | |
AnnaBridge | 145:64910690c574 | 117 | uint32_t MSICalibrationValue; /*!< The calibration trimming value (default is RCC_MSICALIBRATION_DEFAULT). |
AnnaBridge | 145:64910690c574 | 118 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ |
AnnaBridge | 145:64910690c574 | 119 | |
AnnaBridge | 145:64910690c574 | 120 | uint32_t MSIClockRange; /*!< The MSI frequency range. |
AnnaBridge | 145:64910690c574 | 121 | This parameter can be a value of @ref RCC_MSI_Clock_Range */ |
AnnaBridge | 145:64910690c574 | 122 | |
AnnaBridge | 161:aa5281ff4a02 | 123 | uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32L43x/STM32L44x/STM32L49x/STM32L4Ax devices). |
AnnaBridge | 145:64910690c574 | 124 | This parameter can be a value of @ref RCC_HSI48_Config */ |
AnnaBridge | 145:64910690c574 | 125 | |
AnnaBridge | 145:64910690c574 | 126 | RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */ |
AnnaBridge | 145:64910690c574 | 127 | |
AnnaBridge | 145:64910690c574 | 128 | }RCC_OscInitTypeDef; |
AnnaBridge | 145:64910690c574 | 129 | |
AnnaBridge | 145:64910690c574 | 130 | /** |
AnnaBridge | 145:64910690c574 | 131 | * @brief RCC System, AHB and APB busses clock configuration structure definition |
AnnaBridge | 145:64910690c574 | 132 | */ |
AnnaBridge | 145:64910690c574 | 133 | typedef struct |
AnnaBridge | 145:64910690c574 | 134 | { |
AnnaBridge | 145:64910690c574 | 135 | uint32_t ClockType; /*!< The clock to be configured. |
AnnaBridge | 145:64910690c574 | 136 | This parameter can be a value of @ref RCC_System_Clock_Type */ |
AnnaBridge | 145:64910690c574 | 137 | |
AnnaBridge | 145:64910690c574 | 138 | uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK). |
AnnaBridge | 145:64910690c574 | 139 | This parameter can be a value of @ref RCC_System_Clock_Source */ |
AnnaBridge | 145:64910690c574 | 140 | |
AnnaBridge | 145:64910690c574 | 141 | uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). |
AnnaBridge | 145:64910690c574 | 142 | This parameter can be a value of @ref RCC_AHB_Clock_Source */ |
AnnaBridge | 145:64910690c574 | 143 | |
AnnaBridge | 145:64910690c574 | 144 | uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). |
AnnaBridge | 145:64910690c574 | 145 | This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ |
AnnaBridge | 145:64910690c574 | 146 | |
AnnaBridge | 145:64910690c574 | 147 | uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). |
AnnaBridge | 145:64910690c574 | 148 | This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ |
AnnaBridge | 145:64910690c574 | 149 | |
AnnaBridge | 145:64910690c574 | 150 | }RCC_ClkInitTypeDef; |
AnnaBridge | 145:64910690c574 | 151 | |
AnnaBridge | 145:64910690c574 | 152 | /** |
AnnaBridge | 145:64910690c574 | 153 | * @} |
AnnaBridge | 145:64910690c574 | 154 | */ |
AnnaBridge | 145:64910690c574 | 155 | |
AnnaBridge | 145:64910690c574 | 156 | /* Exported constants --------------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 157 | /** @defgroup RCC_Exported_Constants RCC Exported Constants |
AnnaBridge | 145:64910690c574 | 158 | * @{ |
AnnaBridge | 145:64910690c574 | 159 | */ |
AnnaBridge | 145:64910690c574 | 160 | |
AnnaBridge | 145:64910690c574 | 161 | /** @defgroup RCC_Timeout_Value Timeout Values |
AnnaBridge | 145:64910690c574 | 162 | * @{ |
AnnaBridge | 145:64910690c574 | 163 | */ |
AnnaBridge | 161:aa5281ff4a02 | 164 | #define RCC_DBP_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ |
AnnaBridge | 145:64910690c574 | 165 | #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT |
AnnaBridge | 145:64910690c574 | 166 | /** |
AnnaBridge | 145:64910690c574 | 167 | * @} |
AnnaBridge | 145:64910690c574 | 168 | */ |
AnnaBridge | 145:64910690c574 | 169 | |
AnnaBridge | 145:64910690c574 | 170 | /** @defgroup RCC_Oscillator_Type Oscillator Type |
AnnaBridge | 145:64910690c574 | 171 | * @{ |
AnnaBridge | 145:64910690c574 | 172 | */ |
AnnaBridge | 161:aa5281ff4a02 | 173 | #define RCC_OSCILLATORTYPE_NONE 0x00000000U /*!< Oscillator configuration unchanged */ |
AnnaBridge | 161:aa5281ff4a02 | 174 | #define RCC_OSCILLATORTYPE_HSE 0x00000001U /*!< HSE to configure */ |
AnnaBridge | 161:aa5281ff4a02 | 175 | #define RCC_OSCILLATORTYPE_HSI 0x00000002U /*!< HSI to configure */ |
AnnaBridge | 161:aa5281ff4a02 | 176 | #define RCC_OSCILLATORTYPE_LSE 0x00000004U /*!< LSE to configure */ |
AnnaBridge | 161:aa5281ff4a02 | 177 | #define RCC_OSCILLATORTYPE_LSI 0x00000008U /*!< LSI to configure */ |
AnnaBridge | 161:aa5281ff4a02 | 178 | #define RCC_OSCILLATORTYPE_MSI 0x00000010U /*!< MSI to configure */ |
AnnaBridge | 145:64910690c574 | 179 | #if defined(RCC_HSI48_SUPPORT) |
AnnaBridge | 161:aa5281ff4a02 | 180 | #define RCC_OSCILLATORTYPE_HSI48 0x00000020U /*!< HSI48 to configure */ |
AnnaBridge | 145:64910690c574 | 181 | #endif /* RCC_HSI48_SUPPORT */ |
AnnaBridge | 145:64910690c574 | 182 | /** |
AnnaBridge | 145:64910690c574 | 183 | * @} |
AnnaBridge | 145:64910690c574 | 184 | */ |
AnnaBridge | 145:64910690c574 | 185 | |
AnnaBridge | 145:64910690c574 | 186 | /** @defgroup RCC_HSE_Config HSE Config |
AnnaBridge | 145:64910690c574 | 187 | * @{ |
AnnaBridge | 145:64910690c574 | 188 | */ |
AnnaBridge | 161:aa5281ff4a02 | 189 | #define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */ |
AnnaBridge | 161:aa5281ff4a02 | 190 | #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ |
AnnaBridge | 161:aa5281ff4a02 | 191 | #define RCC_HSE_BYPASS (RCC_CR_HSEBYP | RCC_CR_HSEON) /*!< External clock source for HSE clock */ |
AnnaBridge | 145:64910690c574 | 192 | /** |
AnnaBridge | 145:64910690c574 | 193 | * @} |
AnnaBridge | 145:64910690c574 | 194 | */ |
AnnaBridge | 145:64910690c574 | 195 | |
AnnaBridge | 145:64910690c574 | 196 | /** @defgroup RCC_LSE_Config LSE Config |
AnnaBridge | 145:64910690c574 | 197 | * @{ |
AnnaBridge | 145:64910690c574 | 198 | */ |
AnnaBridge | 161:aa5281ff4a02 | 199 | #define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */ |
AnnaBridge | 161:aa5281ff4a02 | 200 | #define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ |
AnnaBridge | 161:aa5281ff4a02 | 201 | #define RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON) /*!< External clock source for LSE clock */ |
AnnaBridge | 145:64910690c574 | 202 | /** |
AnnaBridge | 145:64910690c574 | 203 | * @} |
AnnaBridge | 145:64910690c574 | 204 | */ |
AnnaBridge | 145:64910690c574 | 205 | |
AnnaBridge | 145:64910690c574 | 206 | /** @defgroup RCC_HSI_Config HSI Config |
AnnaBridge | 145:64910690c574 | 207 | * @{ |
AnnaBridge | 145:64910690c574 | 208 | */ |
AnnaBridge | 161:aa5281ff4a02 | 209 | #define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ |
AnnaBridge | 161:aa5281ff4a02 | 210 | #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ |
AnnaBridge | 145:64910690c574 | 211 | |
AnnaBridge | 145:64910690c574 | 212 | #if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ |
AnnaBridge | 145:64910690c574 | 213 | defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) |
AnnaBridge | 161:aa5281ff4a02 | 214 | #define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */ |
AnnaBridge | 145:64910690c574 | 215 | #else |
AnnaBridge | 161:aa5281ff4a02 | 216 | #define RCC_HSICALIBRATION_DEFAULT 0x40U /* Default HSI calibration trimming value */ |
AnnaBridge | 145:64910690c574 | 217 | #endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ |
AnnaBridge | 145:64910690c574 | 218 | /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ |
AnnaBridge | 145:64910690c574 | 219 | /** |
AnnaBridge | 145:64910690c574 | 220 | * @} |
AnnaBridge | 145:64910690c574 | 221 | */ |
AnnaBridge | 145:64910690c574 | 222 | |
AnnaBridge | 145:64910690c574 | 223 | /** @defgroup RCC_LSI_Config LSI Config |
AnnaBridge | 145:64910690c574 | 224 | * @{ |
AnnaBridge | 145:64910690c574 | 225 | */ |
AnnaBridge | 161:aa5281ff4a02 | 226 | #define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */ |
AnnaBridge | 161:aa5281ff4a02 | 227 | #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ |
AnnaBridge | 145:64910690c574 | 228 | /** |
AnnaBridge | 145:64910690c574 | 229 | * @} |
AnnaBridge | 145:64910690c574 | 230 | */ |
AnnaBridge | 145:64910690c574 | 231 | |
AnnaBridge | 145:64910690c574 | 232 | /** @defgroup RCC_MSI_Config MSI Config |
AnnaBridge | 145:64910690c574 | 233 | * @{ |
AnnaBridge | 145:64910690c574 | 234 | */ |
AnnaBridge | 161:aa5281ff4a02 | 235 | #define RCC_MSI_OFF 0x00000000U /*!< MSI clock deactivation */ |
AnnaBridge | 161:aa5281ff4a02 | 236 | #define RCC_MSI_ON RCC_CR_MSION /*!< MSI clock activation */ |
AnnaBridge | 161:aa5281ff4a02 | 237 | |
AnnaBridge | 161:aa5281ff4a02 | 238 | #define RCC_MSICALIBRATION_DEFAULT 0U /*!< Default MSI calibration trimming value */ |
AnnaBridge | 145:64910690c574 | 239 | /** |
AnnaBridge | 145:64910690c574 | 240 | * @} |
AnnaBridge | 145:64910690c574 | 241 | */ |
AnnaBridge | 145:64910690c574 | 242 | |
AnnaBridge | 145:64910690c574 | 243 | #if defined(RCC_HSI48_SUPPORT) |
AnnaBridge | 145:64910690c574 | 244 | /** @defgroup RCC_HSI48_Config HSI48 Config |
AnnaBridge | 145:64910690c574 | 245 | * @{ |
AnnaBridge | 145:64910690c574 | 246 | */ |
AnnaBridge | 161:aa5281ff4a02 | 247 | #define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */ |
AnnaBridge | 161:aa5281ff4a02 | 248 | #define RCC_HSI48_ON RCC_CRRCR_HSI48ON /*!< HSI48 clock activation */ |
AnnaBridge | 145:64910690c574 | 249 | /** |
AnnaBridge | 145:64910690c574 | 250 | * @} |
AnnaBridge | 145:64910690c574 | 251 | */ |
AnnaBridge | 145:64910690c574 | 252 | #else |
AnnaBridge | 145:64910690c574 | 253 | /** @defgroup RCC_HSI48_Config HSI48 Config |
AnnaBridge | 145:64910690c574 | 254 | * @{ |
AnnaBridge | 145:64910690c574 | 255 | */ |
AnnaBridge | 161:aa5281ff4a02 | 256 | #define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */ |
AnnaBridge | 145:64910690c574 | 257 | /** |
AnnaBridge | 145:64910690c574 | 258 | * @} |
AnnaBridge | 145:64910690c574 | 259 | */ |
AnnaBridge | 145:64910690c574 | 260 | #endif /* RCC_HSI48_SUPPORT */ |
AnnaBridge | 145:64910690c574 | 261 | |
AnnaBridge | 145:64910690c574 | 262 | /** @defgroup RCC_PLL_Config PLL Config |
AnnaBridge | 145:64910690c574 | 263 | * @{ |
AnnaBridge | 145:64910690c574 | 264 | */ |
AnnaBridge | 161:aa5281ff4a02 | 265 | #define RCC_PLL_NONE 0x00000000U /*!< PLL configuration unchanged */ |
AnnaBridge | 161:aa5281ff4a02 | 266 | #define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */ |
AnnaBridge | 161:aa5281ff4a02 | 267 | #define RCC_PLL_ON 0x00000002U /*!< PLL activation */ |
AnnaBridge | 145:64910690c574 | 268 | /** |
AnnaBridge | 145:64910690c574 | 269 | * @} |
AnnaBridge | 145:64910690c574 | 270 | */ |
AnnaBridge | 145:64910690c574 | 271 | |
AnnaBridge | 145:64910690c574 | 272 | /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider |
AnnaBridge | 145:64910690c574 | 273 | * @{ |
AnnaBridge | 145:64910690c574 | 274 | */ |
AnnaBridge | 145:64910690c574 | 275 | #if defined(RCC_PLLP_DIV_2_31_SUPPORT) |
AnnaBridge | 161:aa5281ff4a02 | 276 | #define RCC_PLLP_DIV2 0x00000002U /*!< PLLP division factor = 2 */ |
AnnaBridge | 161:aa5281ff4a02 | 277 | #define RCC_PLLP_DIV3 0x00000003U /*!< PLLP division factor = 3 */ |
AnnaBridge | 161:aa5281ff4a02 | 278 | #define RCC_PLLP_DIV4 0x00000004U /*!< PLLP division factor = 4 */ |
AnnaBridge | 161:aa5281ff4a02 | 279 | #define RCC_PLLP_DIV5 0x00000005U /*!< PLLP division factor = 5 */ |
AnnaBridge | 161:aa5281ff4a02 | 280 | #define RCC_PLLP_DIV6 0x00000006U /*!< PLLP division factor = 6 */ |
AnnaBridge | 161:aa5281ff4a02 | 281 | #define RCC_PLLP_DIV7 0x00000007U /*!< PLLP division factor = 7 */ |
AnnaBridge | 161:aa5281ff4a02 | 282 | #define RCC_PLLP_DIV8 0x00000008U /*!< PLLP division factor = 8 */ |
AnnaBridge | 161:aa5281ff4a02 | 283 | #define RCC_PLLP_DIV9 0x00000009U /*!< PLLP division factor = 9 */ |
AnnaBridge | 161:aa5281ff4a02 | 284 | #define RCC_PLLP_DIV10 0x0000000AU /*!< PLLP division factor = 10 */ |
AnnaBridge | 161:aa5281ff4a02 | 285 | #define RCC_PLLP_DIV11 0x0000000BU /*!< PLLP division factor = 11 */ |
AnnaBridge | 161:aa5281ff4a02 | 286 | #define RCC_PLLP_DIV12 0x0000000CU /*!< PLLP division factor = 12 */ |
AnnaBridge | 161:aa5281ff4a02 | 287 | #define RCC_PLLP_DIV13 0x0000000DU /*!< PLLP division factor = 13 */ |
AnnaBridge | 161:aa5281ff4a02 | 288 | #define RCC_PLLP_DIV14 0x0000000EU /*!< PLLP division factor = 14 */ |
AnnaBridge | 161:aa5281ff4a02 | 289 | #define RCC_PLLP_DIV15 0x0000000FU /*!< PLLP division factor = 15 */ |
AnnaBridge | 161:aa5281ff4a02 | 290 | #define RCC_PLLP_DIV16 0x00000010U /*!< PLLP division factor = 16 */ |
AnnaBridge | 161:aa5281ff4a02 | 291 | #define RCC_PLLP_DIV17 0x00000011U /*!< PLLP division factor = 17 */ |
AnnaBridge | 161:aa5281ff4a02 | 292 | #define RCC_PLLP_DIV18 0x00000012U /*!< PLLP division factor = 18 */ |
AnnaBridge | 161:aa5281ff4a02 | 293 | #define RCC_PLLP_DIV19 0x00000013U /*!< PLLP division factor = 19 */ |
AnnaBridge | 161:aa5281ff4a02 | 294 | #define RCC_PLLP_DIV20 0x00000014U /*!< PLLP division factor = 20 */ |
AnnaBridge | 161:aa5281ff4a02 | 295 | #define RCC_PLLP_DIV21 0x00000015U /*!< PLLP division factor = 21 */ |
AnnaBridge | 161:aa5281ff4a02 | 296 | #define RCC_PLLP_DIV22 0x00000016U /*!< PLLP division factor = 22 */ |
AnnaBridge | 161:aa5281ff4a02 | 297 | #define RCC_PLLP_DIV23 0x00000017U /*!< PLLP division factor = 23 */ |
AnnaBridge | 161:aa5281ff4a02 | 298 | #define RCC_PLLP_DIV24 0x00000018U /*!< PLLP division factor = 24 */ |
AnnaBridge | 161:aa5281ff4a02 | 299 | #define RCC_PLLP_DIV25 0x00000019U /*!< PLLP division factor = 25 */ |
AnnaBridge | 161:aa5281ff4a02 | 300 | #define RCC_PLLP_DIV26 0x0000001AU /*!< PLLP division factor = 26 */ |
AnnaBridge | 161:aa5281ff4a02 | 301 | #define RCC_PLLP_DIV27 0x0000001BU /*!< PLLP division factor = 27 */ |
AnnaBridge | 161:aa5281ff4a02 | 302 | #define RCC_PLLP_DIV28 0x0000001CU /*!< PLLP division factor = 28 */ |
AnnaBridge | 161:aa5281ff4a02 | 303 | #define RCC_PLLP_DIV29 0x0000001DU /*!< PLLP division factor = 29 */ |
AnnaBridge | 161:aa5281ff4a02 | 304 | #define RCC_PLLP_DIV30 0x0000001EU /*!< PLLP division factor = 30 */ |
AnnaBridge | 161:aa5281ff4a02 | 305 | #define RCC_PLLP_DIV31 0x0000001FU /*!< PLLP division factor = 31 */ |
AnnaBridge | 145:64910690c574 | 306 | #else |
AnnaBridge | 161:aa5281ff4a02 | 307 | #define RCC_PLLP_DIV7 0x00000007U /*!< PLLP division factor = 7 */ |
AnnaBridge | 161:aa5281ff4a02 | 308 | #define RCC_PLLP_DIV17 0x00000011U /*!< PLLP division factor = 17 */ |
AnnaBridge | 145:64910690c574 | 309 | #endif /* RCC_PLLP_DIV_2_31_SUPPORT */ |
AnnaBridge | 145:64910690c574 | 310 | /** |
AnnaBridge | 145:64910690c574 | 311 | * @} |
AnnaBridge | 145:64910690c574 | 312 | */ |
AnnaBridge | 145:64910690c574 | 313 | |
AnnaBridge | 145:64910690c574 | 314 | /** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider |
AnnaBridge | 145:64910690c574 | 315 | * @{ |
AnnaBridge | 145:64910690c574 | 316 | */ |
AnnaBridge | 161:aa5281ff4a02 | 317 | #define RCC_PLLQ_DIV2 0x00000002U /*!< PLLQ division factor = 2 */ |
AnnaBridge | 161:aa5281ff4a02 | 318 | #define RCC_PLLQ_DIV4 0x00000004U /*!< PLLQ division factor = 4 */ |
AnnaBridge | 161:aa5281ff4a02 | 319 | #define RCC_PLLQ_DIV6 0x00000006U /*!< PLLQ division factor = 6 */ |
AnnaBridge | 161:aa5281ff4a02 | 320 | #define RCC_PLLQ_DIV8 0x00000008U /*!< PLLQ division factor = 8 */ |
AnnaBridge | 145:64910690c574 | 321 | /** |
AnnaBridge | 145:64910690c574 | 322 | * @} |
AnnaBridge | 145:64910690c574 | 323 | */ |
AnnaBridge | 145:64910690c574 | 324 | |
AnnaBridge | 145:64910690c574 | 325 | /** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider |
AnnaBridge | 145:64910690c574 | 326 | * @{ |
AnnaBridge | 145:64910690c574 | 327 | */ |
AnnaBridge | 161:aa5281ff4a02 | 328 | #define RCC_PLLR_DIV2 0x00000002U /*!< PLLR division factor = 2 */ |
AnnaBridge | 161:aa5281ff4a02 | 329 | #define RCC_PLLR_DIV4 0x00000004U /*!< PLLR division factor = 4 */ |
AnnaBridge | 161:aa5281ff4a02 | 330 | #define RCC_PLLR_DIV6 0x00000006U /*!< PLLR division factor = 6 */ |
AnnaBridge | 161:aa5281ff4a02 | 331 | #define RCC_PLLR_DIV8 0x00000008U /*!< PLLR division factor = 8 */ |
AnnaBridge | 145:64910690c574 | 332 | /** |
AnnaBridge | 145:64910690c574 | 333 | * @} |
AnnaBridge | 145:64910690c574 | 334 | */ |
AnnaBridge | 145:64910690c574 | 335 | |
AnnaBridge | 145:64910690c574 | 336 | /** @defgroup RCC_PLL_Clock_Source PLL Clock Source |
AnnaBridge | 145:64910690c574 | 337 | * @{ |
AnnaBridge | 145:64910690c574 | 338 | */ |
AnnaBridge | 161:aa5281ff4a02 | 339 | #define RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock selected as PLL entry clock source */ |
AnnaBridge | 145:64910690c574 | 340 | #define RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI /*!< MSI clock selected as PLL entry clock source */ |
AnnaBridge | 145:64910690c574 | 341 | #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */ |
AnnaBridge | 145:64910690c574 | 342 | #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */ |
AnnaBridge | 145:64910690c574 | 343 | /** |
AnnaBridge | 145:64910690c574 | 344 | * @} |
AnnaBridge | 145:64910690c574 | 345 | */ |
AnnaBridge | 145:64910690c574 | 346 | |
AnnaBridge | 145:64910690c574 | 347 | /** @defgroup RCC_PLL_Clock_Output PLL Clock Output |
AnnaBridge | 145:64910690c574 | 348 | * @{ |
AnnaBridge | 145:64910690c574 | 349 | */ |
AnnaBridge | 145:64910690c574 | 350 | #if defined(RCC_PLLSAI2_SUPPORT) |
AnnaBridge | 145:64910690c574 | 351 | #define RCC_PLL_SAI3CLK RCC_PLLCFGR_PLLPEN /*!< PLLSAI3CLK selection from main PLL (for devices with PLLSAI2) */ |
AnnaBridge | 145:64910690c574 | 352 | #else |
AnnaBridge | 145:64910690c574 | 353 | #define RCC_PLL_SAI2CLK RCC_PLLCFGR_PLLPEN /*!< PLLSAI2CLK selection from main PLL (for devices without PLLSAI2) */ |
AnnaBridge | 145:64910690c574 | 354 | #endif /* RCC_PLLSAI2_SUPPORT */ |
AnnaBridge | 145:64910690c574 | 355 | #define RCC_PLL_48M1CLK RCC_PLLCFGR_PLLQEN /*!< PLL48M1CLK selection from main PLL */ |
AnnaBridge | 145:64910690c574 | 356 | #define RCC_PLL_SYSCLK RCC_PLLCFGR_PLLREN /*!< PLLCLK selection from main PLL */ |
AnnaBridge | 145:64910690c574 | 357 | /** |
AnnaBridge | 145:64910690c574 | 358 | * @} |
AnnaBridge | 145:64910690c574 | 359 | */ |
AnnaBridge | 145:64910690c574 | 360 | |
AnnaBridge | 145:64910690c574 | 361 | /** @defgroup RCC_PLLSAI1_Clock_Output PLLSAI1 Clock Output |
AnnaBridge | 145:64910690c574 | 362 | * @{ |
AnnaBridge | 145:64910690c574 | 363 | */ |
AnnaBridge | 145:64910690c574 | 364 | #define RCC_PLLSAI1_SAI1CLK RCC_PLLSAI1CFGR_PLLSAI1PEN /*!< PLLSAI1CLK selection from PLLSAI1 */ |
AnnaBridge | 145:64910690c574 | 365 | #define RCC_PLLSAI1_48M2CLK RCC_PLLSAI1CFGR_PLLSAI1QEN /*!< PLL48M2CLK selection from PLLSAI1 */ |
AnnaBridge | 145:64910690c574 | 366 | #define RCC_PLLSAI1_ADC1CLK RCC_PLLSAI1CFGR_PLLSAI1REN /*!< PLLADC1CLK selection from PLLSAI1 */ |
AnnaBridge | 145:64910690c574 | 367 | /** |
AnnaBridge | 145:64910690c574 | 368 | * @} |
AnnaBridge | 145:64910690c574 | 369 | */ |
AnnaBridge | 145:64910690c574 | 370 | |
AnnaBridge | 145:64910690c574 | 371 | #if defined(RCC_PLLSAI2_SUPPORT) |
AnnaBridge | 145:64910690c574 | 372 | |
AnnaBridge | 145:64910690c574 | 373 | /** @defgroup RCC_PLLSAI2_Clock_Output PLLSAI2 Clock Output |
AnnaBridge | 145:64910690c574 | 374 | * @{ |
AnnaBridge | 145:64910690c574 | 375 | */ |
AnnaBridge | 145:64910690c574 | 376 | #define RCC_PLLSAI2_SAI2CLK RCC_PLLSAI2CFGR_PLLSAI2PEN /*!< PLLSAI2CLK selection from PLLSAI2 */ |
AnnaBridge | 161:aa5281ff4a02 | 377 | #if defined(RCC_PLLSAI2Q_DIV_SUPPORT) |
AnnaBridge | 161:aa5281ff4a02 | 378 | #define RCC_PLLSAI2_DSICLK RCC_PLLSAI2CFGR_PLLSAI2QEN /*!< PLLDSICLK selection from PLLSAI2 */ |
AnnaBridge | 161:aa5281ff4a02 | 379 | #endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ |
AnnaBridge | 161:aa5281ff4a02 | 380 | #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) |
AnnaBridge | 145:64910690c574 | 381 | #define RCC_PLLSAI2_ADC2CLK RCC_PLLSAI2CFGR_PLLSAI2REN /*!< PLLADC2CLK selection from PLLSAI2 */ |
AnnaBridge | 161:aa5281ff4a02 | 382 | #else |
AnnaBridge | 161:aa5281ff4a02 | 383 | #define RCC_PLLSAI2_LTDCCLK RCC_PLLSAI2CFGR_PLLSAI2REN /*!< PLLLTDCCLK selection from PLLSAI2 */ |
AnnaBridge | 161:aa5281ff4a02 | 384 | #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ |
AnnaBridge | 145:64910690c574 | 385 | /** |
AnnaBridge | 145:64910690c574 | 386 | * @} |
AnnaBridge | 145:64910690c574 | 387 | */ |
AnnaBridge | 145:64910690c574 | 388 | |
AnnaBridge | 145:64910690c574 | 389 | #endif /* RCC_PLLSAI2_SUPPORT */ |
AnnaBridge | 145:64910690c574 | 390 | |
AnnaBridge | 145:64910690c574 | 391 | /** @defgroup RCC_MSI_Clock_Range MSI Clock Range |
AnnaBridge | 145:64910690c574 | 392 | * @{ |
AnnaBridge | 145:64910690c574 | 393 | */ |
AnnaBridge | 145:64910690c574 | 394 | #define RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0 /*!< MSI = 100 KHz */ |
AnnaBridge | 145:64910690c574 | 395 | #define RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1 /*!< MSI = 200 KHz */ |
AnnaBridge | 145:64910690c574 | 396 | #define RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2 /*!< MSI = 400 KHz */ |
AnnaBridge | 145:64910690c574 | 397 | #define RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3 /*!< MSI = 800 KHz */ |
AnnaBridge | 145:64910690c574 | 398 | #define RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4 /*!< MSI = 1 MHz */ |
AnnaBridge | 145:64910690c574 | 399 | #define RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5 /*!< MSI = 2 MHz */ |
AnnaBridge | 145:64910690c574 | 400 | #define RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6 /*!< MSI = 4 MHz */ |
AnnaBridge | 145:64910690c574 | 401 | #define RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7 /*!< MSI = 8 MHz */ |
AnnaBridge | 145:64910690c574 | 402 | #define RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8 /*!< MSI = 16 MHz */ |
AnnaBridge | 145:64910690c574 | 403 | #define RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9 /*!< MSI = 24 MHz */ |
AnnaBridge | 145:64910690c574 | 404 | #define RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10 /*!< MSI = 32 MHz */ |
AnnaBridge | 145:64910690c574 | 405 | #define RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11 /*!< MSI = 48 MHz */ |
AnnaBridge | 145:64910690c574 | 406 | /** |
AnnaBridge | 145:64910690c574 | 407 | * @} |
AnnaBridge | 145:64910690c574 | 408 | */ |
AnnaBridge | 145:64910690c574 | 409 | |
AnnaBridge | 145:64910690c574 | 410 | /** @defgroup RCC_System_Clock_Type System Clock Type |
AnnaBridge | 145:64910690c574 | 411 | * @{ |
AnnaBridge | 145:64910690c574 | 412 | */ |
AnnaBridge | 161:aa5281ff4a02 | 413 | #define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ |
AnnaBridge | 161:aa5281ff4a02 | 414 | #define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ |
AnnaBridge | 161:aa5281ff4a02 | 415 | #define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ |
AnnaBridge | 161:aa5281ff4a02 | 416 | #define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */ |
AnnaBridge | 145:64910690c574 | 417 | /** |
AnnaBridge | 145:64910690c574 | 418 | * @} |
AnnaBridge | 145:64910690c574 | 419 | */ |
AnnaBridge | 145:64910690c574 | 420 | |
AnnaBridge | 145:64910690c574 | 421 | /** @defgroup RCC_System_Clock_Source System Clock Source |
AnnaBridge | 145:64910690c574 | 422 | * @{ |
AnnaBridge | 145:64910690c574 | 423 | */ |
AnnaBridge | 145:64910690c574 | 424 | #define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI /*!< MSI selection as system clock */ |
AnnaBridge | 145:64910690c574 | 425 | #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ |
AnnaBridge | 145:64910690c574 | 426 | #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ |
AnnaBridge | 145:64910690c574 | 427 | #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ |
AnnaBridge | 145:64910690c574 | 428 | /** |
AnnaBridge | 145:64910690c574 | 429 | * @} |
AnnaBridge | 145:64910690c574 | 430 | */ |
AnnaBridge | 145:64910690c574 | 431 | |
AnnaBridge | 145:64910690c574 | 432 | /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status |
AnnaBridge | 145:64910690c574 | 433 | * @{ |
AnnaBridge | 145:64910690c574 | 434 | */ |
AnnaBridge | 145:64910690c574 | 435 | #define RCC_SYSCLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /*!< MSI used as system clock */ |
AnnaBridge | 145:64910690c574 | 436 | #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ |
AnnaBridge | 145:64910690c574 | 437 | #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ |
AnnaBridge | 145:64910690c574 | 438 | #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ |
AnnaBridge | 145:64910690c574 | 439 | /** |
AnnaBridge | 145:64910690c574 | 440 | * @} |
AnnaBridge | 145:64910690c574 | 441 | */ |
AnnaBridge | 145:64910690c574 | 442 | |
AnnaBridge | 145:64910690c574 | 443 | /** @defgroup RCC_AHB_Clock_Source AHB Clock Source |
AnnaBridge | 145:64910690c574 | 444 | * @{ |
AnnaBridge | 145:64910690c574 | 445 | */ |
AnnaBridge | 145:64910690c574 | 446 | #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ |
AnnaBridge | 145:64910690c574 | 447 | #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ |
AnnaBridge | 145:64910690c574 | 448 | #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ |
AnnaBridge | 145:64910690c574 | 449 | #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ |
AnnaBridge | 145:64910690c574 | 450 | #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ |
AnnaBridge | 145:64910690c574 | 451 | #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ |
AnnaBridge | 145:64910690c574 | 452 | #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ |
AnnaBridge | 145:64910690c574 | 453 | #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ |
AnnaBridge | 145:64910690c574 | 454 | #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ |
AnnaBridge | 145:64910690c574 | 455 | /** |
AnnaBridge | 145:64910690c574 | 456 | * @} |
AnnaBridge | 145:64910690c574 | 457 | */ |
AnnaBridge | 145:64910690c574 | 458 | |
AnnaBridge | 145:64910690c574 | 459 | /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source |
AnnaBridge | 145:64910690c574 | 460 | * @{ |
AnnaBridge | 145:64910690c574 | 461 | */ |
AnnaBridge | 145:64910690c574 | 462 | #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ |
AnnaBridge | 145:64910690c574 | 463 | #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ |
AnnaBridge | 145:64910690c574 | 464 | #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ |
AnnaBridge | 145:64910690c574 | 465 | #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ |
AnnaBridge | 145:64910690c574 | 466 | #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ |
AnnaBridge | 145:64910690c574 | 467 | /** |
AnnaBridge | 145:64910690c574 | 468 | * @} |
AnnaBridge | 145:64910690c574 | 469 | */ |
AnnaBridge | 145:64910690c574 | 470 | |
AnnaBridge | 145:64910690c574 | 471 | /** @defgroup RCC_RTC_Clock_Source RTC Clock Source |
AnnaBridge | 145:64910690c574 | 472 | * @{ |
AnnaBridge | 145:64910690c574 | 473 | */ |
AnnaBridge | 161:aa5281ff4a02 | 474 | #define RCC_RTCCLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ |
AnnaBridge | 161:aa5281ff4a02 | 475 | #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ |
AnnaBridge | 161:aa5281ff4a02 | 476 | #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ |
AnnaBridge | 161:aa5281ff4a02 | 477 | #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ |
AnnaBridge | 145:64910690c574 | 478 | /** |
AnnaBridge | 145:64910690c574 | 479 | * @} |
AnnaBridge | 145:64910690c574 | 480 | */ |
AnnaBridge | 145:64910690c574 | 481 | |
AnnaBridge | 145:64910690c574 | 482 | /** @defgroup RCC_MCO_Index MCO Index |
AnnaBridge | 145:64910690c574 | 483 | * @{ |
AnnaBridge | 145:64910690c574 | 484 | */ |
AnnaBridge | 161:aa5281ff4a02 | 485 | #define RCC_MCO1 0x00000000U |
AnnaBridge | 161:aa5281ff4a02 | 486 | #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ |
AnnaBridge | 145:64910690c574 | 487 | /** |
AnnaBridge | 145:64910690c574 | 488 | * @} |
AnnaBridge | 145:64910690c574 | 489 | */ |
AnnaBridge | 145:64910690c574 | 490 | |
AnnaBridge | 145:64910690c574 | 491 | /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source |
AnnaBridge | 145:64910690c574 | 492 | * @{ |
AnnaBridge | 145:64910690c574 | 493 | */ |
AnnaBridge | 161:aa5281ff4a02 | 494 | #define RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO1 output disabled, no clock on MCO1 */ |
AnnaBridge | 145:64910690c574 | 495 | #define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ |
AnnaBridge | 145:64910690c574 | 496 | #define RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /*!< MSI selection as MCO1 source */ |
AnnaBridge | 145:64910690c574 | 497 | #define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */ |
AnnaBridge | 145:64910690c574 | 498 | #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */ |
AnnaBridge | 145:64910690c574 | 499 | #define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< PLLCLK selection as MCO1 source */ |
AnnaBridge | 145:64910690c574 | 500 | #define RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */ |
AnnaBridge | 145:64910690c574 | 501 | #define RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */ |
AnnaBridge | 145:64910690c574 | 502 | #if defined(RCC_HSI48_SUPPORT) |
AnnaBridge | 145:64910690c574 | 503 | #define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3 /*!< HSI48 selection as MCO1 source (STM32L43x/STM32L44x devices) */ |
AnnaBridge | 145:64910690c574 | 504 | #endif /* RCC_HSI48_SUPPORT */ |
AnnaBridge | 145:64910690c574 | 505 | /** |
AnnaBridge | 145:64910690c574 | 506 | * @} |
AnnaBridge | 145:64910690c574 | 507 | */ |
AnnaBridge | 145:64910690c574 | 508 | |
AnnaBridge | 145:64910690c574 | 509 | /** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler |
AnnaBridge | 145:64910690c574 | 510 | * @{ |
AnnaBridge | 145:64910690c574 | 511 | */ |
AnnaBridge | 161:aa5281ff4a02 | 512 | #define RCC_MCODIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO not divided */ |
AnnaBridge | 145:64910690c574 | 513 | #define RCC_MCODIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO divided by 2 */ |
AnnaBridge | 145:64910690c574 | 514 | #define RCC_MCODIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO divided by 4 */ |
AnnaBridge | 145:64910690c574 | 515 | #define RCC_MCODIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO divided by 8 */ |
AnnaBridge | 145:64910690c574 | 516 | #define RCC_MCODIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO divided by 16 */ |
AnnaBridge | 145:64910690c574 | 517 | /** |
AnnaBridge | 145:64910690c574 | 518 | * @} |
AnnaBridge | 145:64910690c574 | 519 | */ |
AnnaBridge | 145:64910690c574 | 520 | |
AnnaBridge | 145:64910690c574 | 521 | /** @defgroup RCC_Interrupt Interrupts |
AnnaBridge | 145:64910690c574 | 522 | * @{ |
AnnaBridge | 145:64910690c574 | 523 | */ |
AnnaBridge | 145:64910690c574 | 524 | #define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ |
AnnaBridge | 145:64910690c574 | 525 | #define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ |
AnnaBridge | 145:64910690c574 | 526 | #define RCC_IT_MSIRDY RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */ |
AnnaBridge | 145:64910690c574 | 527 | #define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI16 Ready Interrupt flag */ |
AnnaBridge | 145:64910690c574 | 528 | #define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ |
AnnaBridge | 145:64910690c574 | 529 | #define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */ |
AnnaBridge | 145:64910690c574 | 530 | #define RCC_IT_PLLSAI1RDY RCC_CIFR_PLLSAI1RDYF /*!< PLLSAI1 Ready Interrupt flag */ |
AnnaBridge | 145:64910690c574 | 531 | #if defined(RCC_PLLSAI2_SUPPORT) |
AnnaBridge | 145:64910690c574 | 532 | #define RCC_IT_PLLSAI2RDY RCC_CIFR_PLLSAI2RDYF /*!< PLLSAI2 Ready Interrupt flag */ |
AnnaBridge | 145:64910690c574 | 533 | #endif /* RCC_PLLSAI2_SUPPORT */ |
AnnaBridge | 145:64910690c574 | 534 | #define RCC_IT_CSS RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */ |
AnnaBridge | 145:64910690c574 | 535 | #define RCC_IT_LSECSS RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */ |
AnnaBridge | 145:64910690c574 | 536 | #if defined(RCC_HSI48_SUPPORT) |
AnnaBridge | 145:64910690c574 | 537 | #define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ |
AnnaBridge | 145:64910690c574 | 538 | #endif /* RCC_HSI48_SUPPORT */ |
AnnaBridge | 145:64910690c574 | 539 | /** |
AnnaBridge | 145:64910690c574 | 540 | * @} |
AnnaBridge | 145:64910690c574 | 541 | */ |
AnnaBridge | 145:64910690c574 | 542 | |
AnnaBridge | 145:64910690c574 | 543 | /** @defgroup RCC_Flag Flags |
AnnaBridge | 145:64910690c574 | 544 | * Elements values convention: XXXYYYYYb |
AnnaBridge | 145:64910690c574 | 545 | * - YYYYY : Flag position in the register |
AnnaBridge | 145:64910690c574 | 546 | * - XXX : Register index |
AnnaBridge | 145:64910690c574 | 547 | * - 001: CR register |
AnnaBridge | 145:64910690c574 | 548 | * - 010: BDCR register |
AnnaBridge | 145:64910690c574 | 549 | * - 011: CSR register |
AnnaBridge | 145:64910690c574 | 550 | * - 100: CRRCR register |
AnnaBridge | 145:64910690c574 | 551 | * @{ |
AnnaBridge | 145:64910690c574 | 552 | */ |
AnnaBridge | 145:64910690c574 | 553 | /* Flags in the CR register */ |
AnnaBridge | 161:aa5281ff4a02 | 554 | #define RCC_FLAG_MSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_MSIRDY_Pos) /*!< MSI Ready flag */ |
AnnaBridge | 161:aa5281ff4a02 | 555 | #define RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */ |
AnnaBridge | 161:aa5281ff4a02 | 556 | #define RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */ |
AnnaBridge | 161:aa5281ff4a02 | 557 | #define RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos) /*!< PLL Ready flag */ |
AnnaBridge | 161:aa5281ff4a02 | 558 | #define RCC_FLAG_PLLSAI1RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI1RDY_Pos) /*!< PLLSAI1 Ready flag */ |
AnnaBridge | 145:64910690c574 | 559 | #if defined(RCC_PLLSAI2_SUPPORT) |
AnnaBridge | 161:aa5281ff4a02 | 560 | #define RCC_FLAG_PLLSAI2RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI2RDY_Pos) /*!< PLLSAI2 Ready flag */ |
AnnaBridge | 145:64910690c574 | 561 | #endif /* RCC_PLLSAI2_SUPPORT */ |
AnnaBridge | 145:64910690c574 | 562 | |
AnnaBridge | 145:64910690c574 | 563 | /* Flags in the BDCR register */ |
AnnaBridge | 161:aa5281ff4a02 | 564 | #define RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos) /*!< LSE Ready flag */ |
AnnaBridge | 161:aa5281ff4a02 | 565 | #define RCC_FLAG_LSECSSD ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos) /*!< LSE Clock Security System Interrupt flag */ |
AnnaBridge | 145:64910690c574 | 566 | |
AnnaBridge | 145:64910690c574 | 567 | /* Flags in the CSR register */ |
AnnaBridge | 161:aa5281ff4a02 | 568 | #define RCC_FLAG_LSIRDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos) /*!< LSI Ready flag */ |
AnnaBridge | 161:aa5281ff4a02 | 569 | #define RCC_FLAG_RMVF ((CSR_REG_INDEX << 5U) | RCC_CSR_RMVF_Pos) /*!< Remove reset flag */ |
AnnaBridge | 161:aa5281ff4a02 | 570 | #define RCC_FLAG_FWRST ((CSR_REG_INDEX << 5U) | RCC_CSR_FWRSTF_Pos) /*!< Firewall reset flag */ |
AnnaBridge | 161:aa5281ff4a02 | 571 | #define RCC_FLAG_OBLRST ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos) /*!< Option Byte Loader reset flag */ |
AnnaBridge | 161:aa5281ff4a02 | 572 | #define RCC_FLAG_PINRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos) /*!< PIN reset flag */ |
AnnaBridge | 161:aa5281ff4a02 | 573 | #define RCC_FLAG_BORRST ((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos) /*!< BOR reset flag */ |
AnnaBridge | 161:aa5281ff4a02 | 574 | #define RCC_FLAG_SFTRST ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos) /*!< Software Reset flag */ |
AnnaBridge | 161:aa5281ff4a02 | 575 | #define RCC_FLAG_IWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos) /*!< Independent Watchdog reset flag */ |
AnnaBridge | 161:aa5281ff4a02 | 576 | #define RCC_FLAG_WWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos) /*!< Window watchdog reset flag */ |
AnnaBridge | 161:aa5281ff4a02 | 577 | #define RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */ |
AnnaBridge | 145:64910690c574 | 578 | |
AnnaBridge | 145:64910690c574 | 579 | #if defined(RCC_HSI48_SUPPORT) |
AnnaBridge | 145:64910690c574 | 580 | /* Flags in the CRRCR register */ |
AnnaBridge | 161:aa5281ff4a02 | 581 | #define RCC_FLAG_HSI48RDY ((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_HSI48RDY_Pos) /*!< HSI48 Ready flag */ |
AnnaBridge | 145:64910690c574 | 582 | #endif /* RCC_HSI48_SUPPORT */ |
AnnaBridge | 145:64910690c574 | 583 | /** |
AnnaBridge | 145:64910690c574 | 584 | * @} |
AnnaBridge | 145:64910690c574 | 585 | */ |
AnnaBridge | 145:64910690c574 | 586 | |
AnnaBridge | 145:64910690c574 | 587 | /** @defgroup RCC_LSEDrive_Config LSE Drive Config |
AnnaBridge | 145:64910690c574 | 588 | * @{ |
AnnaBridge | 145:64910690c574 | 589 | */ |
AnnaBridge | 161:aa5281ff4a02 | 590 | #define RCC_LSEDRIVE_LOW 0x00000000U /*!< LSE low drive capability */ |
AnnaBridge | 161:aa5281ff4a02 | 591 | #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */ |
AnnaBridge | 161:aa5281ff4a02 | 592 | #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */ |
AnnaBridge | 161:aa5281ff4a02 | 593 | #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */ |
AnnaBridge | 145:64910690c574 | 594 | /** |
AnnaBridge | 145:64910690c574 | 595 | * @} |
AnnaBridge | 145:64910690c574 | 596 | */ |
AnnaBridge | 145:64910690c574 | 597 | |
AnnaBridge | 161:aa5281ff4a02 | 598 | /** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock |
AnnaBridge | 145:64910690c574 | 599 | * @{ |
AnnaBridge | 145:64910690c574 | 600 | */ |
AnnaBridge | 161:aa5281ff4a02 | 601 | #define RCC_STOP_WAKEUPCLOCK_MSI 0x00000000U /*!< MSI selection after wake-up from STOP */ |
AnnaBridge | 161:aa5281ff4a02 | 602 | #define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /*!< HSI selection after wake-up from STOP */ |
AnnaBridge | 145:64910690c574 | 603 | /** |
AnnaBridge | 145:64910690c574 | 604 | * @} |
AnnaBridge | 145:64910690c574 | 605 | */ |
AnnaBridge | 145:64910690c574 | 606 | |
AnnaBridge | 145:64910690c574 | 607 | /** |
AnnaBridge | 145:64910690c574 | 608 | * @} |
AnnaBridge | 145:64910690c574 | 609 | */ |
AnnaBridge | 145:64910690c574 | 610 | |
AnnaBridge | 145:64910690c574 | 611 | /* Exported macros -----------------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 612 | |
AnnaBridge | 145:64910690c574 | 613 | /** @defgroup RCC_Exported_Macros RCC Exported Macros |
AnnaBridge | 145:64910690c574 | 614 | * @{ |
AnnaBridge | 145:64910690c574 | 615 | */ |
AnnaBridge | 145:64910690c574 | 616 | |
AnnaBridge | 145:64910690c574 | 617 | /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable |
AnnaBridge | 145:64910690c574 | 618 | * @brief Enable or disable the AHB1 peripheral clock. |
AnnaBridge | 145:64910690c574 | 619 | * @note After reset, the peripheral clock (used for registers read/write access) |
AnnaBridge | 145:64910690c574 | 620 | * is disabled and the application software has to enable this clock before |
AnnaBridge | 145:64910690c574 | 621 | * using it. |
AnnaBridge | 145:64910690c574 | 622 | * @{ |
AnnaBridge | 145:64910690c574 | 623 | */ |
AnnaBridge | 145:64910690c574 | 624 | |
AnnaBridge | 145:64910690c574 | 625 | #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 626 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 627 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \ |
AnnaBridge | 145:64910690c574 | 628 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 629 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \ |
AnnaBridge | 145:64910690c574 | 630 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 631 | } while(0) |
AnnaBridge | 145:64910690c574 | 632 | |
AnnaBridge | 145:64910690c574 | 633 | #define __HAL_RCC_DMA2_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 634 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 635 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \ |
AnnaBridge | 145:64910690c574 | 636 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 637 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \ |
AnnaBridge | 145:64910690c574 | 638 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 639 | } while(0) |
AnnaBridge | 145:64910690c574 | 640 | |
AnnaBridge | 161:aa5281ff4a02 | 641 | #if defined(DMAMUX1) |
AnnaBridge | 161:aa5281ff4a02 | 642 | #define __HAL_RCC_DMAMUX1_CLK_ENABLE() do { \ |
AnnaBridge | 161:aa5281ff4a02 | 643 | __IO uint32_t tmpreg; \ |
AnnaBridge | 161:aa5281ff4a02 | 644 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \ |
AnnaBridge | 161:aa5281ff4a02 | 645 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 161:aa5281ff4a02 | 646 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \ |
AnnaBridge | 161:aa5281ff4a02 | 647 | UNUSED(tmpreg); \ |
AnnaBridge | 161:aa5281ff4a02 | 648 | } while(0) |
AnnaBridge | 161:aa5281ff4a02 | 649 | #endif /* DMAMUX1 */ |
AnnaBridge | 161:aa5281ff4a02 | 650 | |
AnnaBridge | 145:64910690c574 | 651 | #define __HAL_RCC_FLASH_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 652 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 653 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ |
AnnaBridge | 145:64910690c574 | 654 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 655 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ |
AnnaBridge | 145:64910690c574 | 656 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 657 | } while(0) |
AnnaBridge | 145:64910690c574 | 658 | |
AnnaBridge | 145:64910690c574 | 659 | #define __HAL_RCC_CRC_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 660 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 661 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ |
AnnaBridge | 145:64910690c574 | 662 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 663 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ |
AnnaBridge | 145:64910690c574 | 664 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 665 | } while(0) |
AnnaBridge | 145:64910690c574 | 666 | |
AnnaBridge | 145:64910690c574 | 667 | #define __HAL_RCC_TSC_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 668 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 669 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ |
AnnaBridge | 145:64910690c574 | 670 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 671 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ |
AnnaBridge | 145:64910690c574 | 672 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 673 | } while(0) |
AnnaBridge | 161:aa5281ff4a02 | 674 | |
AnnaBridge | 145:64910690c574 | 675 | #if defined(DMA2D) |
AnnaBridge | 145:64910690c574 | 676 | #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 677 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 678 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \ |
AnnaBridge | 145:64910690c574 | 679 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 680 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \ |
AnnaBridge | 145:64910690c574 | 681 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 682 | } while(0) |
AnnaBridge | 161:aa5281ff4a02 | 683 | #endif /* DMA2D */ |
AnnaBridge | 161:aa5281ff4a02 | 684 | |
AnnaBridge | 161:aa5281ff4a02 | 685 | #if defined(GFXMMU) |
AnnaBridge | 161:aa5281ff4a02 | 686 | #define __HAL_RCC_GFXMMU_CLK_ENABLE() do { \ |
AnnaBridge | 161:aa5281ff4a02 | 687 | __IO uint32_t tmpreg; \ |
AnnaBridge | 161:aa5281ff4a02 | 688 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \ |
AnnaBridge | 161:aa5281ff4a02 | 689 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 161:aa5281ff4a02 | 690 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \ |
AnnaBridge | 161:aa5281ff4a02 | 691 | UNUSED(tmpreg); \ |
AnnaBridge | 161:aa5281ff4a02 | 692 | } while(0) |
AnnaBridge | 161:aa5281ff4a02 | 693 | #endif /* GFXMMU */ |
AnnaBridge | 145:64910690c574 | 694 | |
AnnaBridge | 145:64910690c574 | 695 | |
AnnaBridge | 145:64910690c574 | 696 | #define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) |
AnnaBridge | 145:64910690c574 | 697 | |
AnnaBridge | 145:64910690c574 | 698 | #define __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) |
AnnaBridge | 145:64910690c574 | 699 | |
AnnaBridge | 161:aa5281ff4a02 | 700 | #if defined(DMAMUX1) |
AnnaBridge | 161:aa5281ff4a02 | 701 | #define __HAL_RCC_DMAMUX1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) |
AnnaBridge | 161:aa5281ff4a02 | 702 | #endif /* DMAMUX1 */ |
AnnaBridge | 161:aa5281ff4a02 | 703 | |
AnnaBridge | 145:64910690c574 | 704 | #define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) |
AnnaBridge | 145:64910690c574 | 705 | |
AnnaBridge | 145:64910690c574 | 706 | #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) |
AnnaBridge | 145:64910690c574 | 707 | |
AnnaBridge | 145:64910690c574 | 708 | #define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) |
AnnaBridge | 145:64910690c574 | 709 | |
AnnaBridge | 145:64910690c574 | 710 | #if defined(DMA2D) |
AnnaBridge | 145:64910690c574 | 711 | #define __HAL_RCC_DMA2D_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) |
AnnaBridge | 161:aa5281ff4a02 | 712 | #endif /* DMA2D */ |
AnnaBridge | 161:aa5281ff4a02 | 713 | |
AnnaBridge | 161:aa5281ff4a02 | 714 | #if defined(GFXMMU) |
AnnaBridge | 161:aa5281ff4a02 | 715 | #define __HAL_RCC_GFXMMU_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) |
AnnaBridge | 161:aa5281ff4a02 | 716 | #endif /* GFXMMU */ |
AnnaBridge | 145:64910690c574 | 717 | |
AnnaBridge | 145:64910690c574 | 718 | /** |
AnnaBridge | 145:64910690c574 | 719 | * @} |
AnnaBridge | 145:64910690c574 | 720 | */ |
AnnaBridge | 145:64910690c574 | 721 | |
AnnaBridge | 145:64910690c574 | 722 | /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable |
AnnaBridge | 145:64910690c574 | 723 | * @brief Enable or disable the AHB2 peripheral clock. |
AnnaBridge | 145:64910690c574 | 724 | * @note After reset, the peripheral clock (used for registers read/write access) |
AnnaBridge | 145:64910690c574 | 725 | * is disabled and the application software has to enable this clock before |
AnnaBridge | 145:64910690c574 | 726 | * using it. |
AnnaBridge | 145:64910690c574 | 727 | * @{ |
AnnaBridge | 145:64910690c574 | 728 | */ |
AnnaBridge | 145:64910690c574 | 729 | |
AnnaBridge | 145:64910690c574 | 730 | #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 731 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 732 | SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ |
AnnaBridge | 145:64910690c574 | 733 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 734 | tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ |
AnnaBridge | 145:64910690c574 | 735 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 736 | } while(0) |
AnnaBridge | 145:64910690c574 | 737 | |
AnnaBridge | 145:64910690c574 | 738 | #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 739 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 740 | SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ |
AnnaBridge | 145:64910690c574 | 741 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 742 | tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ |
AnnaBridge | 145:64910690c574 | 743 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 744 | } while(0) |
AnnaBridge | 145:64910690c574 | 745 | |
AnnaBridge | 145:64910690c574 | 746 | #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 747 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 748 | SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ |
AnnaBridge | 145:64910690c574 | 749 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 750 | tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ |
AnnaBridge | 145:64910690c574 | 751 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 752 | } while(0) |
AnnaBridge | 145:64910690c574 | 753 | |
AnnaBridge | 145:64910690c574 | 754 | #if defined(GPIOD) |
AnnaBridge | 145:64910690c574 | 755 | #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 756 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 757 | SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \ |
AnnaBridge | 145:64910690c574 | 758 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 759 | tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \ |
AnnaBridge | 145:64910690c574 | 760 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 761 | } while(0) |
AnnaBridge | 145:64910690c574 | 762 | #endif /* GPIOD */ |
AnnaBridge | 145:64910690c574 | 763 | |
AnnaBridge | 145:64910690c574 | 764 | #if defined(GPIOE) |
AnnaBridge | 145:64910690c574 | 765 | #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 766 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 767 | SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \ |
AnnaBridge | 145:64910690c574 | 768 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 769 | tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \ |
AnnaBridge | 145:64910690c574 | 770 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 771 | } while(0) |
AnnaBridge | 145:64910690c574 | 772 | #endif /* GPIOE */ |
AnnaBridge | 145:64910690c574 | 773 | |
AnnaBridge | 145:64910690c574 | 774 | #if defined(GPIOF) |
AnnaBridge | 145:64910690c574 | 775 | #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 776 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 777 | SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \ |
AnnaBridge | 145:64910690c574 | 778 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 779 | tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \ |
AnnaBridge | 145:64910690c574 | 780 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 781 | } while(0) |
AnnaBridge | 145:64910690c574 | 782 | #endif /* GPIOF */ |
AnnaBridge | 145:64910690c574 | 783 | |
AnnaBridge | 145:64910690c574 | 784 | #if defined(GPIOG) |
AnnaBridge | 145:64910690c574 | 785 | #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 786 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 787 | SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \ |
AnnaBridge | 145:64910690c574 | 788 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 789 | tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \ |
AnnaBridge | 145:64910690c574 | 790 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 791 | } while(0) |
AnnaBridge | 145:64910690c574 | 792 | #endif /* GPIOG */ |
AnnaBridge | 145:64910690c574 | 793 | |
AnnaBridge | 145:64910690c574 | 794 | #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 795 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 796 | SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \ |
AnnaBridge | 145:64910690c574 | 797 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 798 | tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \ |
AnnaBridge | 145:64910690c574 | 799 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 800 | } while(0) |
AnnaBridge | 145:64910690c574 | 801 | |
AnnaBridge | 145:64910690c574 | 802 | #if defined(GPIOI) |
AnnaBridge | 145:64910690c574 | 803 | #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 804 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 805 | SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN); \ |
AnnaBridge | 145:64910690c574 | 806 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 807 | tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN); \ |
AnnaBridge | 145:64910690c574 | 808 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 809 | } while(0) |
AnnaBridge | 145:64910690c574 | 810 | #endif /* GPIOI */ |
AnnaBridge | 145:64910690c574 | 811 | |
AnnaBridge | 145:64910690c574 | 812 | #if defined(USB_OTG_FS) |
AnnaBridge | 145:64910690c574 | 813 | #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 814 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 815 | SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \ |
AnnaBridge | 145:64910690c574 | 816 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 817 | tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \ |
AnnaBridge | 145:64910690c574 | 818 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 819 | } while(0) |
AnnaBridge | 145:64910690c574 | 820 | #endif /* USB_OTG_FS */ |
AnnaBridge | 145:64910690c574 | 821 | |
AnnaBridge | 145:64910690c574 | 822 | #define __HAL_RCC_ADC_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 823 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 824 | SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \ |
AnnaBridge | 145:64910690c574 | 825 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 826 | tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \ |
AnnaBridge | 145:64910690c574 | 827 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 828 | } while(0) |
AnnaBridge | 145:64910690c574 | 829 | |
AnnaBridge | 145:64910690c574 | 830 | #if defined(DCMI) |
AnnaBridge | 145:64910690c574 | 831 | #define __HAL_RCC_DCMI_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 832 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 833 | SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN); \ |
AnnaBridge | 145:64910690c574 | 834 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 835 | tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN); \ |
AnnaBridge | 145:64910690c574 | 836 | UNUSED(tmpreg); \ |
AnnaBridge | 161:aa5281ff4a02 | 837 | } while(0) |
AnnaBridge | 145:64910690c574 | 838 | #endif /* DCMI */ |
AnnaBridge | 145:64910690c574 | 839 | |
AnnaBridge | 145:64910690c574 | 840 | #if defined(AES) |
AnnaBridge | 145:64910690c574 | 841 | #define __HAL_RCC_AES_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 842 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 843 | SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ |
AnnaBridge | 145:64910690c574 | 844 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 845 | tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ |
AnnaBridge | 145:64910690c574 | 846 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 847 | } while(0) |
AnnaBridge | 145:64910690c574 | 848 | #endif /* AES */ |
AnnaBridge | 145:64910690c574 | 849 | |
AnnaBridge | 145:64910690c574 | 850 | #if defined(HASH) |
AnnaBridge | 145:64910690c574 | 851 | #define __HAL_RCC_HASH_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 852 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 853 | SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \ |
AnnaBridge | 145:64910690c574 | 854 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 855 | tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \ |
AnnaBridge | 145:64910690c574 | 856 | UNUSED(tmpreg); \ |
AnnaBridge | 161:aa5281ff4a02 | 857 | } while(0) |
AnnaBridge | 145:64910690c574 | 858 | #endif /* HASH */ |
AnnaBridge | 145:64910690c574 | 859 | |
AnnaBridge | 145:64910690c574 | 860 | #define __HAL_RCC_RNG_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 861 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 862 | SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \ |
AnnaBridge | 145:64910690c574 | 863 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 864 | tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \ |
AnnaBridge | 145:64910690c574 | 865 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 866 | } while(0) |
AnnaBridge | 145:64910690c574 | 867 | |
AnnaBridge | 161:aa5281ff4a02 | 868 | #if defined(OCTOSPIM) |
AnnaBridge | 161:aa5281ff4a02 | 869 | #define __HAL_RCC_OSPIM_CLK_ENABLE() do { \ |
AnnaBridge | 161:aa5281ff4a02 | 870 | __IO uint32_t tmpreg; \ |
AnnaBridge | 161:aa5281ff4a02 | 871 | SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN); \ |
AnnaBridge | 161:aa5281ff4a02 | 872 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 161:aa5281ff4a02 | 873 | tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN); \ |
AnnaBridge | 161:aa5281ff4a02 | 874 | UNUSED(tmpreg); \ |
AnnaBridge | 161:aa5281ff4a02 | 875 | } while(0) |
AnnaBridge | 161:aa5281ff4a02 | 876 | #endif /* OCTOSPIM */ |
AnnaBridge | 161:aa5281ff4a02 | 877 | |
AnnaBridge | 161:aa5281ff4a02 | 878 | #if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN) |
AnnaBridge | 161:aa5281ff4a02 | 879 | #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ |
AnnaBridge | 161:aa5281ff4a02 | 880 | __IO uint32_t tmpreg; \ |
AnnaBridge | 161:aa5281ff4a02 | 881 | SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN); \ |
AnnaBridge | 161:aa5281ff4a02 | 882 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 161:aa5281ff4a02 | 883 | tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN); \ |
AnnaBridge | 161:aa5281ff4a02 | 884 | UNUSED(tmpreg); \ |
AnnaBridge | 161:aa5281ff4a02 | 885 | } while(0) |
AnnaBridge | 161:aa5281ff4a02 | 886 | #endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */ |
AnnaBridge | 161:aa5281ff4a02 | 887 | |
AnnaBridge | 145:64910690c574 | 888 | |
AnnaBridge | 145:64910690c574 | 889 | #define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) |
AnnaBridge | 145:64910690c574 | 890 | |
AnnaBridge | 145:64910690c574 | 891 | #define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) |
AnnaBridge | 145:64910690c574 | 892 | |
AnnaBridge | 145:64910690c574 | 893 | #define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) |
AnnaBridge | 145:64910690c574 | 894 | |
AnnaBridge | 145:64910690c574 | 895 | #if defined(GPIOD) |
AnnaBridge | 145:64910690c574 | 896 | #define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) |
AnnaBridge | 145:64910690c574 | 897 | #endif /* GPIOD */ |
AnnaBridge | 145:64910690c574 | 898 | |
AnnaBridge | 145:64910690c574 | 899 | #if defined(GPIOE) |
AnnaBridge | 145:64910690c574 | 900 | #define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) |
AnnaBridge | 145:64910690c574 | 901 | #endif /* GPIOE */ |
AnnaBridge | 145:64910690c574 | 902 | |
AnnaBridge | 145:64910690c574 | 903 | #if defined(GPIOF) |
AnnaBridge | 145:64910690c574 | 904 | #define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) |
AnnaBridge | 145:64910690c574 | 905 | #endif /* GPIOF */ |
AnnaBridge | 145:64910690c574 | 906 | |
AnnaBridge | 145:64910690c574 | 907 | #if defined(GPIOG) |
AnnaBridge | 145:64910690c574 | 908 | #define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) |
AnnaBridge | 145:64910690c574 | 909 | #endif /* GPIOG */ |
AnnaBridge | 145:64910690c574 | 910 | |
AnnaBridge | 145:64910690c574 | 911 | #define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) |
AnnaBridge | 145:64910690c574 | 912 | |
AnnaBridge | 145:64910690c574 | 913 | #if defined(GPIOI) |
AnnaBridge | 145:64910690c574 | 914 | #define __HAL_RCC_GPIOI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) |
AnnaBridge | 145:64910690c574 | 915 | #endif /* GPIOI */ |
AnnaBridge | 145:64910690c574 | 916 | |
AnnaBridge | 145:64910690c574 | 917 | #if defined(USB_OTG_FS) |
AnnaBridge | 145:64910690c574 | 918 | #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); |
AnnaBridge | 145:64910690c574 | 919 | #endif /* USB_OTG_FS */ |
AnnaBridge | 145:64910690c574 | 920 | |
AnnaBridge | 145:64910690c574 | 921 | #define __HAL_RCC_ADC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) |
AnnaBridge | 145:64910690c574 | 922 | |
AnnaBridge | 145:64910690c574 | 923 | #if defined(DCMI) |
AnnaBridge | 145:64910690c574 | 924 | #define __HAL_RCC_DCMI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) |
AnnaBridge | 145:64910690c574 | 925 | #endif /* DCMI */ |
AnnaBridge | 145:64910690c574 | 926 | |
AnnaBridge | 145:64910690c574 | 927 | #if defined(AES) |
AnnaBridge | 145:64910690c574 | 928 | #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); |
AnnaBridge | 145:64910690c574 | 929 | #endif /* AES */ |
AnnaBridge | 145:64910690c574 | 930 | |
AnnaBridge | 145:64910690c574 | 931 | #if defined(HASH) |
AnnaBridge | 145:64910690c574 | 932 | #define __HAL_RCC_HASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) |
AnnaBridge | 145:64910690c574 | 933 | #endif /* HASH */ |
AnnaBridge | 145:64910690c574 | 934 | |
AnnaBridge | 145:64910690c574 | 935 | #define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) |
AnnaBridge | 145:64910690c574 | 936 | |
AnnaBridge | 161:aa5281ff4a02 | 937 | #if defined(OCTOSPIM) |
AnnaBridge | 161:aa5281ff4a02 | 938 | #define __HAL_RCC_OSPIM_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN) |
AnnaBridge | 161:aa5281ff4a02 | 939 | #endif /* OCTOSPIM */ |
AnnaBridge | 161:aa5281ff4a02 | 940 | |
AnnaBridge | 161:aa5281ff4a02 | 941 | #if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN) |
AnnaBridge | 161:aa5281ff4a02 | 942 | #define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN) |
AnnaBridge | 161:aa5281ff4a02 | 943 | #endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */ |
AnnaBridge | 161:aa5281ff4a02 | 944 | |
AnnaBridge | 145:64910690c574 | 945 | /** |
AnnaBridge | 145:64910690c574 | 946 | * @} |
AnnaBridge | 145:64910690c574 | 947 | */ |
AnnaBridge | 145:64910690c574 | 948 | |
AnnaBridge | 145:64910690c574 | 949 | /** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable |
AnnaBridge | 145:64910690c574 | 950 | * @brief Enable or disable the AHB3 peripheral clock. |
AnnaBridge | 145:64910690c574 | 951 | * @note After reset, the peripheral clock (used for registers read/write access) |
AnnaBridge | 145:64910690c574 | 952 | * is disabled and the application software has to enable this clock before |
AnnaBridge | 145:64910690c574 | 953 | * using it. |
AnnaBridge | 145:64910690c574 | 954 | * @{ |
AnnaBridge | 145:64910690c574 | 955 | */ |
AnnaBridge | 145:64910690c574 | 956 | |
AnnaBridge | 145:64910690c574 | 957 | #if defined(FMC_BANK1) |
AnnaBridge | 145:64910690c574 | 958 | #define __HAL_RCC_FMC_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 959 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 960 | SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \ |
AnnaBridge | 145:64910690c574 | 961 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 962 | tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \ |
AnnaBridge | 145:64910690c574 | 963 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 964 | } while(0) |
AnnaBridge | 145:64910690c574 | 965 | #endif /* FMC_BANK1 */ |
AnnaBridge | 145:64910690c574 | 966 | |
AnnaBridge | 145:64910690c574 | 967 | #if defined(QUADSPI) |
AnnaBridge | 145:64910690c574 | 968 | #define __HAL_RCC_QSPI_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 969 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 970 | SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \ |
AnnaBridge | 145:64910690c574 | 971 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 972 | tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \ |
AnnaBridge | 145:64910690c574 | 973 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 974 | } while(0) |
AnnaBridge | 145:64910690c574 | 975 | #endif /* QUADSPI */ |
AnnaBridge | 145:64910690c574 | 976 | |
AnnaBridge | 161:aa5281ff4a02 | 977 | #if defined(OCTOSPI1) |
AnnaBridge | 161:aa5281ff4a02 | 978 | #define __HAL_RCC_OSPI1_CLK_ENABLE() do { \ |
AnnaBridge | 161:aa5281ff4a02 | 979 | __IO uint32_t tmpreg; \ |
AnnaBridge | 161:aa5281ff4a02 | 980 | SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \ |
AnnaBridge | 161:aa5281ff4a02 | 981 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 161:aa5281ff4a02 | 982 | tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \ |
AnnaBridge | 161:aa5281ff4a02 | 983 | UNUSED(tmpreg); \ |
AnnaBridge | 161:aa5281ff4a02 | 984 | } while(0) |
AnnaBridge | 161:aa5281ff4a02 | 985 | #endif /* OCTOSPI1 */ |
AnnaBridge | 161:aa5281ff4a02 | 986 | |
AnnaBridge | 161:aa5281ff4a02 | 987 | #if defined(OCTOSPI2) |
AnnaBridge | 161:aa5281ff4a02 | 988 | #define __HAL_RCC_OSPI2_CLK_ENABLE() do { \ |
AnnaBridge | 161:aa5281ff4a02 | 989 | __IO uint32_t tmpreg; \ |
AnnaBridge | 161:aa5281ff4a02 | 990 | SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN); \ |
AnnaBridge | 161:aa5281ff4a02 | 991 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 161:aa5281ff4a02 | 992 | tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN); \ |
AnnaBridge | 161:aa5281ff4a02 | 993 | UNUSED(tmpreg); \ |
AnnaBridge | 161:aa5281ff4a02 | 994 | } while(0) |
AnnaBridge | 161:aa5281ff4a02 | 995 | #endif /* OCTOSPI2 */ |
AnnaBridge | 161:aa5281ff4a02 | 996 | |
AnnaBridge | 145:64910690c574 | 997 | #if defined(FMC_BANK1) |
AnnaBridge | 145:64910690c574 | 998 | #define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) |
AnnaBridge | 145:64910690c574 | 999 | #endif /* FMC_BANK1 */ |
AnnaBridge | 145:64910690c574 | 1000 | |
AnnaBridge | 145:64910690c574 | 1001 | #if defined(QUADSPI) |
AnnaBridge | 145:64910690c574 | 1002 | #define __HAL_RCC_QSPI_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) |
AnnaBridge | 145:64910690c574 | 1003 | #endif /* QUADSPI */ |
AnnaBridge | 145:64910690c574 | 1004 | |
AnnaBridge | 161:aa5281ff4a02 | 1005 | #if defined(OCTOSPI1) |
AnnaBridge | 161:aa5281ff4a02 | 1006 | #define __HAL_RCC_OSPI1_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN) |
AnnaBridge | 161:aa5281ff4a02 | 1007 | #endif /* OCTOSPI1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1008 | |
AnnaBridge | 161:aa5281ff4a02 | 1009 | #if defined(OCTOSPI2) |
AnnaBridge | 161:aa5281ff4a02 | 1010 | #define __HAL_RCC_OSPI2_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN) |
AnnaBridge | 161:aa5281ff4a02 | 1011 | #endif /* OCTOSPI2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1012 | |
AnnaBridge | 145:64910690c574 | 1013 | /** |
AnnaBridge | 145:64910690c574 | 1014 | * @} |
AnnaBridge | 145:64910690c574 | 1015 | */ |
AnnaBridge | 145:64910690c574 | 1016 | |
AnnaBridge | 145:64910690c574 | 1017 | /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable |
AnnaBridge | 145:64910690c574 | 1018 | * @brief Enable or disable the APB1 peripheral clock. |
AnnaBridge | 145:64910690c574 | 1019 | * @note After reset, the peripheral clock (used for registers read/write access) |
AnnaBridge | 145:64910690c574 | 1020 | * is disabled and the application software has to enable this clock before |
AnnaBridge | 145:64910690c574 | 1021 | * using it. |
AnnaBridge | 145:64910690c574 | 1022 | * @{ |
AnnaBridge | 145:64910690c574 | 1023 | */ |
AnnaBridge | 145:64910690c574 | 1024 | |
AnnaBridge | 145:64910690c574 | 1025 | #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 1026 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 1027 | SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ |
AnnaBridge | 145:64910690c574 | 1028 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 1029 | tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ |
AnnaBridge | 145:64910690c574 | 1030 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 1031 | } while(0) |
AnnaBridge | 145:64910690c574 | 1032 | |
AnnaBridge | 145:64910690c574 | 1033 | #if defined(TIM3) |
AnnaBridge | 145:64910690c574 | 1034 | #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 1035 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 1036 | SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ |
AnnaBridge | 145:64910690c574 | 1037 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 1038 | tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ |
AnnaBridge | 145:64910690c574 | 1039 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 1040 | } while(0) |
AnnaBridge | 145:64910690c574 | 1041 | #endif /* TIM3 */ |
AnnaBridge | 145:64910690c574 | 1042 | |
AnnaBridge | 145:64910690c574 | 1043 | #if defined(TIM4) |
AnnaBridge | 145:64910690c574 | 1044 | #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 1045 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 1046 | SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ |
AnnaBridge | 145:64910690c574 | 1047 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 1048 | tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ |
AnnaBridge | 145:64910690c574 | 1049 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 1050 | } while(0) |
AnnaBridge | 145:64910690c574 | 1051 | #endif /* TIM4 */ |
AnnaBridge | 145:64910690c574 | 1052 | |
AnnaBridge | 145:64910690c574 | 1053 | #if defined(TIM5) |
AnnaBridge | 145:64910690c574 | 1054 | #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 1055 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 1056 | SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ |
AnnaBridge | 145:64910690c574 | 1057 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 1058 | tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ |
AnnaBridge | 145:64910690c574 | 1059 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 1060 | } while(0) |
AnnaBridge | 145:64910690c574 | 1061 | #endif /* TIM5 */ |
AnnaBridge | 145:64910690c574 | 1062 | |
AnnaBridge | 145:64910690c574 | 1063 | #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 1064 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 1065 | SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ |
AnnaBridge | 145:64910690c574 | 1066 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 1067 | tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ |
AnnaBridge | 145:64910690c574 | 1068 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 1069 | } while(0) |
AnnaBridge | 145:64910690c574 | 1070 | |
AnnaBridge | 145:64910690c574 | 1071 | #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 1072 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 1073 | SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ |
AnnaBridge | 145:64910690c574 | 1074 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 1075 | tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ |
AnnaBridge | 145:64910690c574 | 1076 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 1077 | } while(0) |
AnnaBridge | 145:64910690c574 | 1078 | |
AnnaBridge | 145:64910690c574 | 1079 | #if defined(LCD) |
AnnaBridge | 145:64910690c574 | 1080 | #define __HAL_RCC_LCD_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 1081 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 1082 | SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \ |
AnnaBridge | 145:64910690c574 | 1083 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 1084 | tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \ |
AnnaBridge | 145:64910690c574 | 1085 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 1086 | } while(0) |
AnnaBridge | 145:64910690c574 | 1087 | #endif /* LCD */ |
AnnaBridge | 145:64910690c574 | 1088 | |
AnnaBridge | 145:64910690c574 | 1089 | #if defined(RCC_APB1ENR1_RTCAPBEN) |
AnnaBridge | 145:64910690c574 | 1090 | #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 1091 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 1092 | SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \ |
AnnaBridge | 145:64910690c574 | 1093 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 1094 | tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \ |
AnnaBridge | 145:64910690c574 | 1095 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 1096 | } while(0) |
AnnaBridge | 145:64910690c574 | 1097 | #endif /* RCC_APB1ENR1_RTCAPBEN */ |
AnnaBridge | 145:64910690c574 | 1098 | |
AnnaBridge | 145:64910690c574 | 1099 | #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 1100 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 1101 | SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ |
AnnaBridge | 145:64910690c574 | 1102 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 1103 | tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ |
AnnaBridge | 145:64910690c574 | 1104 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 1105 | } while(0) |
AnnaBridge | 145:64910690c574 | 1106 | |
AnnaBridge | 145:64910690c574 | 1107 | #if defined(SPI2) |
AnnaBridge | 145:64910690c574 | 1108 | #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 1109 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 1110 | SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ |
AnnaBridge | 145:64910690c574 | 1111 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 1112 | tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ |
AnnaBridge | 145:64910690c574 | 1113 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 1114 | } while(0) |
AnnaBridge | 145:64910690c574 | 1115 | #endif /* SPI2 */ |
AnnaBridge | 145:64910690c574 | 1116 | |
AnnaBridge | 145:64910690c574 | 1117 | #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 1118 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 1119 | SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \ |
AnnaBridge | 145:64910690c574 | 1120 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 1121 | tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \ |
AnnaBridge | 145:64910690c574 | 1122 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 1123 | } while(0) |
AnnaBridge | 145:64910690c574 | 1124 | |
AnnaBridge | 145:64910690c574 | 1125 | #define __HAL_RCC_USART2_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 1126 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 1127 | SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ |
AnnaBridge | 145:64910690c574 | 1128 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 1129 | tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ |
AnnaBridge | 145:64910690c574 | 1130 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 1131 | } while(0) |
AnnaBridge | 145:64910690c574 | 1132 | |
AnnaBridge | 145:64910690c574 | 1133 | #if defined(USART3) |
AnnaBridge | 145:64910690c574 | 1134 | #define __HAL_RCC_USART3_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 1135 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 1136 | SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ |
AnnaBridge | 145:64910690c574 | 1137 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 1138 | tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ |
AnnaBridge | 145:64910690c574 | 1139 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 1140 | } while(0) |
AnnaBridge | 145:64910690c574 | 1141 | #endif /* USART3 */ |
AnnaBridge | 145:64910690c574 | 1142 | |
AnnaBridge | 145:64910690c574 | 1143 | #if defined(UART4) |
AnnaBridge | 145:64910690c574 | 1144 | #define __HAL_RCC_UART4_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 1145 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 1146 | SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ |
AnnaBridge | 145:64910690c574 | 1147 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 1148 | tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ |
AnnaBridge | 145:64910690c574 | 1149 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 1150 | } while(0) |
AnnaBridge | 145:64910690c574 | 1151 | #endif /* UART4 */ |
AnnaBridge | 145:64910690c574 | 1152 | |
AnnaBridge | 145:64910690c574 | 1153 | #if defined(UART5) |
AnnaBridge | 145:64910690c574 | 1154 | #define __HAL_RCC_UART5_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 1155 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 1156 | SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ |
AnnaBridge | 145:64910690c574 | 1157 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 1158 | tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ |
AnnaBridge | 145:64910690c574 | 1159 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 1160 | } while(0) |
AnnaBridge | 145:64910690c574 | 1161 | #endif /* UART5 */ |
AnnaBridge | 145:64910690c574 | 1162 | |
AnnaBridge | 145:64910690c574 | 1163 | #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 1164 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 1165 | SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ |
AnnaBridge | 145:64910690c574 | 1166 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 1167 | tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ |
AnnaBridge | 145:64910690c574 | 1168 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 1169 | } while(0) |
AnnaBridge | 145:64910690c574 | 1170 | |
AnnaBridge | 145:64910690c574 | 1171 | #if defined(I2C2) |
AnnaBridge | 145:64910690c574 | 1172 | #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 1173 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 1174 | SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ |
AnnaBridge | 145:64910690c574 | 1175 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 1176 | tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ |
AnnaBridge | 145:64910690c574 | 1177 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 1178 | } while(0) |
AnnaBridge | 145:64910690c574 | 1179 | #endif /* I2C2 */ |
AnnaBridge | 145:64910690c574 | 1180 | |
AnnaBridge | 145:64910690c574 | 1181 | #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 1182 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 1183 | SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \ |
AnnaBridge | 145:64910690c574 | 1184 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 1185 | tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \ |
AnnaBridge | 145:64910690c574 | 1186 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 1187 | } while(0) |
AnnaBridge | 145:64910690c574 | 1188 | |
AnnaBridge | 145:64910690c574 | 1189 | #if defined(I2C4) |
AnnaBridge | 145:64910690c574 | 1190 | #define __HAL_RCC_I2C4_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 1191 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 1192 | SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ |
AnnaBridge | 145:64910690c574 | 1193 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 1194 | tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ |
AnnaBridge | 145:64910690c574 | 1195 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 1196 | } while(0) |
AnnaBridge | 145:64910690c574 | 1197 | #endif /* I2C4 */ |
AnnaBridge | 145:64910690c574 | 1198 | |
AnnaBridge | 145:64910690c574 | 1199 | #if defined(CRS) |
AnnaBridge | 145:64910690c574 | 1200 | #define __HAL_RCC_CRS_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 1201 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 1202 | SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ |
AnnaBridge | 145:64910690c574 | 1203 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 1204 | tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ |
AnnaBridge | 145:64910690c574 | 1205 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 1206 | } while(0) |
AnnaBridge | 145:64910690c574 | 1207 | #endif /* CRS */ |
AnnaBridge | 145:64910690c574 | 1208 | |
AnnaBridge | 145:64910690c574 | 1209 | #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 1210 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 1211 | SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \ |
AnnaBridge | 145:64910690c574 | 1212 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 1213 | tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \ |
AnnaBridge | 145:64910690c574 | 1214 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 1215 | } while(0) |
AnnaBridge | 161:aa5281ff4a02 | 1216 | |
AnnaBridge | 145:64910690c574 | 1217 | #if defined(CAN2) |
AnnaBridge | 145:64910690c574 | 1218 | #define __HAL_RCC_CAN2_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 1219 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 1220 | SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN); \ |
AnnaBridge | 145:64910690c574 | 1221 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 1222 | tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN); \ |
AnnaBridge | 145:64910690c574 | 1223 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 1224 | } while(0) |
AnnaBridge | 145:64910690c574 | 1225 | #endif /* CAN2 */ |
AnnaBridge | 145:64910690c574 | 1226 | |
AnnaBridge | 145:64910690c574 | 1227 | #if defined(USB) |
AnnaBridge | 145:64910690c574 | 1228 | #define __HAL_RCC_USB_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 1229 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 1230 | SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); \ |
AnnaBridge | 145:64910690c574 | 1231 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 1232 | tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); \ |
AnnaBridge | 145:64910690c574 | 1233 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 1234 | } while(0) |
AnnaBridge | 145:64910690c574 | 1235 | #endif /* USB */ |
AnnaBridge | 145:64910690c574 | 1236 | |
AnnaBridge | 145:64910690c574 | 1237 | #define __HAL_RCC_PWR_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 1238 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 1239 | SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \ |
AnnaBridge | 145:64910690c574 | 1240 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 1241 | tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \ |
AnnaBridge | 145:64910690c574 | 1242 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 1243 | } while(0) |
AnnaBridge | 145:64910690c574 | 1244 | |
AnnaBridge | 145:64910690c574 | 1245 | #define __HAL_RCC_DAC1_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 1246 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 1247 | SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \ |
AnnaBridge | 145:64910690c574 | 1248 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 1249 | tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \ |
AnnaBridge | 145:64910690c574 | 1250 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 1251 | } while(0) |
AnnaBridge | 145:64910690c574 | 1252 | |
AnnaBridge | 145:64910690c574 | 1253 | #define __HAL_RCC_OPAMP_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 1254 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 1255 | SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \ |
AnnaBridge | 145:64910690c574 | 1256 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 1257 | tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \ |
AnnaBridge | 145:64910690c574 | 1258 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 1259 | } while(0) |
AnnaBridge | 145:64910690c574 | 1260 | |
AnnaBridge | 145:64910690c574 | 1261 | #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 1262 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 1263 | SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \ |
AnnaBridge | 145:64910690c574 | 1264 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 1265 | tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \ |
AnnaBridge | 145:64910690c574 | 1266 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 1267 | } while(0) |
AnnaBridge | 145:64910690c574 | 1268 | |
AnnaBridge | 145:64910690c574 | 1269 | #define __HAL_RCC_LPUART1_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 1270 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 1271 | SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \ |
AnnaBridge | 145:64910690c574 | 1272 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 1273 | tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \ |
AnnaBridge | 145:64910690c574 | 1274 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 1275 | } while(0) |
AnnaBridge | 145:64910690c574 | 1276 | |
AnnaBridge | 145:64910690c574 | 1277 | #if defined(SWPMI1) |
AnnaBridge | 145:64910690c574 | 1278 | #define __HAL_RCC_SWPMI1_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 1279 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 1280 | SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \ |
AnnaBridge | 145:64910690c574 | 1281 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 1282 | tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \ |
AnnaBridge | 145:64910690c574 | 1283 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 1284 | } while(0) |
AnnaBridge | 145:64910690c574 | 1285 | #endif /* SWPMI1 */ |
AnnaBridge | 145:64910690c574 | 1286 | |
AnnaBridge | 145:64910690c574 | 1287 | #define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 1288 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 1289 | SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \ |
AnnaBridge | 145:64910690c574 | 1290 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 1291 | tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \ |
AnnaBridge | 145:64910690c574 | 1292 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 1293 | } while(0) |
AnnaBridge | 145:64910690c574 | 1294 | |
AnnaBridge | 145:64910690c574 | 1295 | |
AnnaBridge | 145:64910690c574 | 1296 | #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) |
AnnaBridge | 145:64910690c574 | 1297 | |
AnnaBridge | 145:64910690c574 | 1298 | #if defined(TIM3) |
AnnaBridge | 145:64910690c574 | 1299 | #define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) |
AnnaBridge | 145:64910690c574 | 1300 | #endif /* TIM3 */ |
AnnaBridge | 145:64910690c574 | 1301 | |
AnnaBridge | 145:64910690c574 | 1302 | #if defined(TIM4) |
AnnaBridge | 145:64910690c574 | 1303 | #define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) |
AnnaBridge | 145:64910690c574 | 1304 | #endif /* TIM4 */ |
AnnaBridge | 145:64910690c574 | 1305 | |
AnnaBridge | 145:64910690c574 | 1306 | #if defined(TIM5) |
AnnaBridge | 145:64910690c574 | 1307 | #define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) |
AnnaBridge | 145:64910690c574 | 1308 | #endif /* TIM5 */ |
AnnaBridge | 145:64910690c574 | 1309 | |
AnnaBridge | 145:64910690c574 | 1310 | #define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) |
AnnaBridge | 145:64910690c574 | 1311 | |
AnnaBridge | 145:64910690c574 | 1312 | #define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) |
AnnaBridge | 145:64910690c574 | 1313 | |
AnnaBridge | 145:64910690c574 | 1314 | #if defined(LCD) |
AnnaBridge | 145:64910690c574 | 1315 | #define __HAL_RCC_LCD_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); |
AnnaBridge | 145:64910690c574 | 1316 | #endif /* LCD */ |
AnnaBridge | 145:64910690c574 | 1317 | |
AnnaBridge | 145:64910690c574 | 1318 | #if defined(RCC_APB1ENR1_RTCAPBEN) |
AnnaBridge | 145:64910690c574 | 1319 | #define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); |
AnnaBridge | 145:64910690c574 | 1320 | #endif /* RCC_APB1ENR1_RTCAPBEN */ |
AnnaBridge | 145:64910690c574 | 1321 | |
AnnaBridge | 145:64910690c574 | 1322 | #if defined(SPI2) |
AnnaBridge | 145:64910690c574 | 1323 | #define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) |
AnnaBridge | 145:64910690c574 | 1324 | #endif /* SPI2 */ |
AnnaBridge | 145:64910690c574 | 1325 | |
AnnaBridge | 145:64910690c574 | 1326 | #define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) |
AnnaBridge | 145:64910690c574 | 1327 | |
AnnaBridge | 145:64910690c574 | 1328 | #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) |
AnnaBridge | 145:64910690c574 | 1329 | |
AnnaBridge | 145:64910690c574 | 1330 | #if defined(USART3) |
AnnaBridge | 145:64910690c574 | 1331 | #define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) |
AnnaBridge | 145:64910690c574 | 1332 | #endif /* USART3 */ |
AnnaBridge | 145:64910690c574 | 1333 | |
AnnaBridge | 145:64910690c574 | 1334 | #if defined(UART4) |
AnnaBridge | 145:64910690c574 | 1335 | #define __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) |
AnnaBridge | 145:64910690c574 | 1336 | #endif /* UART4 */ |
AnnaBridge | 145:64910690c574 | 1337 | |
AnnaBridge | 145:64910690c574 | 1338 | #if defined(UART5) |
AnnaBridge | 145:64910690c574 | 1339 | #define __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) |
AnnaBridge | 145:64910690c574 | 1340 | #endif /* UART5 */ |
AnnaBridge | 145:64910690c574 | 1341 | |
AnnaBridge | 145:64910690c574 | 1342 | #define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) |
AnnaBridge | 145:64910690c574 | 1343 | |
AnnaBridge | 145:64910690c574 | 1344 | #if defined(I2C2) |
AnnaBridge | 145:64910690c574 | 1345 | #define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) |
AnnaBridge | 145:64910690c574 | 1346 | #endif /* I2C2 */ |
AnnaBridge | 145:64910690c574 | 1347 | |
AnnaBridge | 145:64910690c574 | 1348 | #define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) |
AnnaBridge | 145:64910690c574 | 1349 | |
AnnaBridge | 145:64910690c574 | 1350 | #if defined(I2C4) |
AnnaBridge | 145:64910690c574 | 1351 | #define __HAL_RCC_I2C4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) |
AnnaBridge | 145:64910690c574 | 1352 | #endif /* I2C4 */ |
AnnaBridge | 145:64910690c574 | 1353 | |
AnnaBridge | 145:64910690c574 | 1354 | #if defined(CRS) |
AnnaBridge | 145:64910690c574 | 1355 | #define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); |
AnnaBridge | 145:64910690c574 | 1356 | #endif /* CRS */ |
AnnaBridge | 145:64910690c574 | 1357 | |
AnnaBridge | 145:64910690c574 | 1358 | #define __HAL_RCC_CAN1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) |
AnnaBridge | 145:64910690c574 | 1359 | |
AnnaBridge | 145:64910690c574 | 1360 | #if defined(CAN2) |
AnnaBridge | 145:64910690c574 | 1361 | #define __HAL_RCC_CAN2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) |
AnnaBridge | 145:64910690c574 | 1362 | #endif /* CAN2 */ |
AnnaBridge | 145:64910690c574 | 1363 | |
AnnaBridge | 145:64910690c574 | 1364 | #if defined(USB) |
AnnaBridge | 145:64910690c574 | 1365 | #define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); |
AnnaBridge | 145:64910690c574 | 1366 | #endif /* USB */ |
AnnaBridge | 145:64910690c574 | 1367 | |
AnnaBridge | 145:64910690c574 | 1368 | #define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) |
AnnaBridge | 145:64910690c574 | 1369 | |
AnnaBridge | 145:64910690c574 | 1370 | #define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) |
AnnaBridge | 145:64910690c574 | 1371 | |
AnnaBridge | 145:64910690c574 | 1372 | #define __HAL_RCC_OPAMP_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) |
AnnaBridge | 145:64910690c574 | 1373 | |
AnnaBridge | 145:64910690c574 | 1374 | #define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) |
AnnaBridge | 145:64910690c574 | 1375 | |
AnnaBridge | 145:64910690c574 | 1376 | #define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) |
AnnaBridge | 145:64910690c574 | 1377 | |
AnnaBridge | 145:64910690c574 | 1378 | #if defined(SWPMI1) |
AnnaBridge | 145:64910690c574 | 1379 | #define __HAL_RCC_SWPMI1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) |
AnnaBridge | 145:64910690c574 | 1380 | #endif /* SWPMI1 */ |
AnnaBridge | 145:64910690c574 | 1381 | |
AnnaBridge | 145:64910690c574 | 1382 | #define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) |
AnnaBridge | 145:64910690c574 | 1383 | |
AnnaBridge | 145:64910690c574 | 1384 | /** |
AnnaBridge | 145:64910690c574 | 1385 | * @} |
AnnaBridge | 145:64910690c574 | 1386 | */ |
AnnaBridge | 145:64910690c574 | 1387 | |
AnnaBridge | 145:64910690c574 | 1388 | /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable |
AnnaBridge | 145:64910690c574 | 1389 | * @brief Enable or disable the APB2 peripheral clock. |
AnnaBridge | 145:64910690c574 | 1390 | * @note After reset, the peripheral clock (used for registers read/write access) |
AnnaBridge | 145:64910690c574 | 1391 | * is disabled and the application software has to enable this clock before |
AnnaBridge | 145:64910690c574 | 1392 | * using it. |
AnnaBridge | 145:64910690c574 | 1393 | * @{ |
AnnaBridge | 145:64910690c574 | 1394 | */ |
AnnaBridge | 145:64910690c574 | 1395 | |
AnnaBridge | 145:64910690c574 | 1396 | #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 1397 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 1398 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \ |
AnnaBridge | 145:64910690c574 | 1399 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 1400 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \ |
AnnaBridge | 145:64910690c574 | 1401 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 1402 | } while(0) |
AnnaBridge | 145:64910690c574 | 1403 | |
AnnaBridge | 145:64910690c574 | 1404 | #define __HAL_RCC_FIREWALL_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 1405 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 1406 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \ |
AnnaBridge | 145:64910690c574 | 1407 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 1408 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \ |
AnnaBridge | 145:64910690c574 | 1409 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 1410 | } while(0) |
AnnaBridge | 145:64910690c574 | 1411 | |
AnnaBridge | 161:aa5281ff4a02 | 1412 | #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) |
AnnaBridge | 145:64910690c574 | 1413 | #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 1414 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 1415 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \ |
AnnaBridge | 145:64910690c574 | 1416 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 1417 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \ |
AnnaBridge | 145:64910690c574 | 1418 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 1419 | } while(0) |
AnnaBridge | 161:aa5281ff4a02 | 1420 | #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ |
AnnaBridge | 145:64910690c574 | 1421 | |
AnnaBridge | 145:64910690c574 | 1422 | #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 1423 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 1424 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ |
AnnaBridge | 145:64910690c574 | 1425 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 1426 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ |
AnnaBridge | 145:64910690c574 | 1427 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 1428 | } while(0) |
AnnaBridge | 145:64910690c574 | 1429 | |
AnnaBridge | 145:64910690c574 | 1430 | #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 1431 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 1432 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ |
AnnaBridge | 145:64910690c574 | 1433 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 1434 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ |
AnnaBridge | 145:64910690c574 | 1435 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 1436 | } while(0) |
AnnaBridge | 145:64910690c574 | 1437 | |
AnnaBridge | 145:64910690c574 | 1438 | #if defined(TIM8) |
AnnaBridge | 145:64910690c574 | 1439 | #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 1440 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 1441 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ |
AnnaBridge | 145:64910690c574 | 1442 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 1443 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ |
AnnaBridge | 145:64910690c574 | 1444 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 1445 | } while(0) |
AnnaBridge | 145:64910690c574 | 1446 | #endif /* TIM8 */ |
AnnaBridge | 145:64910690c574 | 1447 | |
AnnaBridge | 145:64910690c574 | 1448 | #define __HAL_RCC_USART1_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 1449 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 1450 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ |
AnnaBridge | 145:64910690c574 | 1451 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 1452 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ |
AnnaBridge | 145:64910690c574 | 1453 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 1454 | } while(0) |
AnnaBridge | 145:64910690c574 | 1455 | |
AnnaBridge | 145:64910690c574 | 1456 | |
AnnaBridge | 145:64910690c574 | 1457 | #define __HAL_RCC_TIM15_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 1458 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 1459 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ |
AnnaBridge | 145:64910690c574 | 1460 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 1461 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ |
AnnaBridge | 145:64910690c574 | 1462 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 1463 | } while(0) |
AnnaBridge | 145:64910690c574 | 1464 | |
AnnaBridge | 145:64910690c574 | 1465 | #define __HAL_RCC_TIM16_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 1466 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 1467 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ |
AnnaBridge | 145:64910690c574 | 1468 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 1469 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ |
AnnaBridge | 145:64910690c574 | 1470 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 1471 | } while(0) |
AnnaBridge | 145:64910690c574 | 1472 | |
AnnaBridge | 145:64910690c574 | 1473 | #if defined(TIM17) |
AnnaBridge | 145:64910690c574 | 1474 | #define __HAL_RCC_TIM17_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 1475 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 1476 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ |
AnnaBridge | 145:64910690c574 | 1477 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 1478 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ |
AnnaBridge | 145:64910690c574 | 1479 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 1480 | } while(0) |
AnnaBridge | 145:64910690c574 | 1481 | #endif /* TIM17 */ |
AnnaBridge | 145:64910690c574 | 1482 | |
AnnaBridge | 145:64910690c574 | 1483 | #define __HAL_RCC_SAI1_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 1484 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 1485 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ |
AnnaBridge | 145:64910690c574 | 1486 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 1487 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ |
AnnaBridge | 145:64910690c574 | 1488 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 1489 | } while(0) |
AnnaBridge | 145:64910690c574 | 1490 | |
AnnaBridge | 145:64910690c574 | 1491 | #if defined(SAI2) |
AnnaBridge | 145:64910690c574 | 1492 | #define __HAL_RCC_SAI2_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 1493 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 1494 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ |
AnnaBridge | 145:64910690c574 | 1495 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 1496 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ |
AnnaBridge | 145:64910690c574 | 1497 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 1498 | } while(0) |
AnnaBridge | 145:64910690c574 | 1499 | #endif /* SAI2 */ |
AnnaBridge | 145:64910690c574 | 1500 | |
AnnaBridge | 145:64910690c574 | 1501 | #if defined(DFSDM1_Filter0) |
AnnaBridge | 145:64910690c574 | 1502 | #define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \ |
AnnaBridge | 145:64910690c574 | 1503 | __IO uint32_t tmpreg; \ |
AnnaBridge | 145:64910690c574 | 1504 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \ |
AnnaBridge | 145:64910690c574 | 1505 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 145:64910690c574 | 1506 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \ |
AnnaBridge | 145:64910690c574 | 1507 | UNUSED(tmpreg); \ |
AnnaBridge | 145:64910690c574 | 1508 | } while(0) |
AnnaBridge | 145:64910690c574 | 1509 | #endif /* DFSDM1_Filter0 */ |
AnnaBridge | 145:64910690c574 | 1510 | |
AnnaBridge | 161:aa5281ff4a02 | 1511 | #if defined(LTDC) |
AnnaBridge | 161:aa5281ff4a02 | 1512 | #define __HAL_RCC_LTDC_CLK_ENABLE() do { \ |
AnnaBridge | 161:aa5281ff4a02 | 1513 | __IO uint32_t tmpreg; \ |
AnnaBridge | 161:aa5281ff4a02 | 1514 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \ |
AnnaBridge | 161:aa5281ff4a02 | 1515 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 161:aa5281ff4a02 | 1516 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \ |
AnnaBridge | 161:aa5281ff4a02 | 1517 | UNUSED(tmpreg); \ |
AnnaBridge | 161:aa5281ff4a02 | 1518 | } while(0) |
AnnaBridge | 161:aa5281ff4a02 | 1519 | #endif /* LTDC */ |
AnnaBridge | 161:aa5281ff4a02 | 1520 | |
AnnaBridge | 161:aa5281ff4a02 | 1521 | #if defined(DSI) |
AnnaBridge | 161:aa5281ff4a02 | 1522 | #define __HAL_RCC_DSI_CLK_ENABLE() do { \ |
AnnaBridge | 161:aa5281ff4a02 | 1523 | __IO uint32_t tmpreg; \ |
AnnaBridge | 161:aa5281ff4a02 | 1524 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN); \ |
AnnaBridge | 161:aa5281ff4a02 | 1525 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 161:aa5281ff4a02 | 1526 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN); \ |
AnnaBridge | 161:aa5281ff4a02 | 1527 | UNUSED(tmpreg); \ |
AnnaBridge | 161:aa5281ff4a02 | 1528 | } while(0) |
AnnaBridge | 161:aa5281ff4a02 | 1529 | #endif /* DSI */ |
AnnaBridge | 161:aa5281ff4a02 | 1530 | |
AnnaBridge | 145:64910690c574 | 1531 | |
AnnaBridge | 145:64910690c574 | 1532 | #define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) |
AnnaBridge | 145:64910690c574 | 1533 | |
AnnaBridge | 161:aa5281ff4a02 | 1534 | #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) |
AnnaBridge | 145:64910690c574 | 1535 | #define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) |
AnnaBridge | 161:aa5281ff4a02 | 1536 | #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ |
AnnaBridge | 145:64910690c574 | 1537 | |
AnnaBridge | 145:64910690c574 | 1538 | #define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) |
AnnaBridge | 145:64910690c574 | 1539 | |
AnnaBridge | 145:64910690c574 | 1540 | #define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) |
AnnaBridge | 145:64910690c574 | 1541 | |
AnnaBridge | 145:64910690c574 | 1542 | #if defined(TIM8) |
AnnaBridge | 145:64910690c574 | 1543 | #define __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) |
AnnaBridge | 145:64910690c574 | 1544 | #endif /* TIM8 */ |
AnnaBridge | 145:64910690c574 | 1545 | |
AnnaBridge | 145:64910690c574 | 1546 | #define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) |
AnnaBridge | 145:64910690c574 | 1547 | |
AnnaBridge | 145:64910690c574 | 1548 | #define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) |
AnnaBridge | 145:64910690c574 | 1549 | |
AnnaBridge | 145:64910690c574 | 1550 | #define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) |
AnnaBridge | 145:64910690c574 | 1551 | |
AnnaBridge | 145:64910690c574 | 1552 | #if defined(TIM17) |
AnnaBridge | 145:64910690c574 | 1553 | #define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) |
AnnaBridge | 145:64910690c574 | 1554 | #endif /* TIM17 */ |
AnnaBridge | 145:64910690c574 | 1555 | |
AnnaBridge | 145:64910690c574 | 1556 | #define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) |
AnnaBridge | 145:64910690c574 | 1557 | |
AnnaBridge | 145:64910690c574 | 1558 | #if defined(SAI2) |
AnnaBridge | 145:64910690c574 | 1559 | #define __HAL_RCC_SAI2_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) |
AnnaBridge | 145:64910690c574 | 1560 | #endif /* SAI2 */ |
AnnaBridge | 145:64910690c574 | 1561 | |
AnnaBridge | 145:64910690c574 | 1562 | #if defined(DFSDM1_Filter0) |
AnnaBridge | 145:64910690c574 | 1563 | #define __HAL_RCC_DFSDM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) |
AnnaBridge | 145:64910690c574 | 1564 | #endif /* DFSDM1_Filter0 */ |
AnnaBridge | 145:64910690c574 | 1565 | |
AnnaBridge | 161:aa5281ff4a02 | 1566 | #if defined(LTDC) |
AnnaBridge | 161:aa5281ff4a02 | 1567 | #define __HAL_RCC_LTDC_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) |
AnnaBridge | 161:aa5281ff4a02 | 1568 | #endif /* LTDC */ |
AnnaBridge | 161:aa5281ff4a02 | 1569 | |
AnnaBridge | 161:aa5281ff4a02 | 1570 | #if defined(DSI) |
AnnaBridge | 161:aa5281ff4a02 | 1571 | #define __HAL_RCC_DSI_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) |
AnnaBridge | 161:aa5281ff4a02 | 1572 | #endif /* DSI */ |
AnnaBridge | 161:aa5281ff4a02 | 1573 | |
AnnaBridge | 145:64910690c574 | 1574 | /** |
AnnaBridge | 145:64910690c574 | 1575 | * @} |
AnnaBridge | 145:64910690c574 | 1576 | */ |
AnnaBridge | 145:64910690c574 | 1577 | |
AnnaBridge | 145:64910690c574 | 1578 | /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status |
AnnaBridge | 145:64910690c574 | 1579 | * @brief Check whether the AHB1 peripheral clock is enabled or not. |
AnnaBridge | 145:64910690c574 | 1580 | * @note After reset, the peripheral clock (used for registers read/write access) |
AnnaBridge | 145:64910690c574 | 1581 | * is disabled and the application software has to enable this clock before |
AnnaBridge | 145:64910690c574 | 1582 | * using it. |
AnnaBridge | 145:64910690c574 | 1583 | * @{ |
AnnaBridge | 145:64910690c574 | 1584 | */ |
AnnaBridge | 145:64910690c574 | 1585 | |
AnnaBridge | 145:64910690c574 | 1586 | #define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != RESET) |
AnnaBridge | 145:64910690c574 | 1587 | |
AnnaBridge | 145:64910690c574 | 1588 | #define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != RESET) |
AnnaBridge | 145:64910690c574 | 1589 | |
AnnaBridge | 161:aa5281ff4a02 | 1590 | #if defined(DMAMUX1) |
AnnaBridge | 161:aa5281ff4a02 | 1591 | #define __HAL_RCC_DMAMUX1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) != RESET) |
AnnaBridge | 161:aa5281ff4a02 | 1592 | #endif /* DMAMUX1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1593 | |
AnnaBridge | 145:64910690c574 | 1594 | #define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != RESET) |
AnnaBridge | 145:64910690c574 | 1595 | |
AnnaBridge | 145:64910690c574 | 1596 | #define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != RESET) |
AnnaBridge | 145:64910690c574 | 1597 | |
AnnaBridge | 145:64910690c574 | 1598 | #define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != RESET) |
AnnaBridge | 145:64910690c574 | 1599 | |
AnnaBridge | 145:64910690c574 | 1600 | #if defined(DMA2D) |
AnnaBridge | 145:64910690c574 | 1601 | #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) != RESET) |
AnnaBridge | 145:64910690c574 | 1602 | #endif /* DMA2D */ |
AnnaBridge | 145:64910690c574 | 1603 | |
AnnaBridge | 161:aa5281ff4a02 | 1604 | #if defined(GFXMMU) |
AnnaBridge | 161:aa5281ff4a02 | 1605 | #define __HAL_RCC_GFXMMU_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) != RESET) |
AnnaBridge | 161:aa5281ff4a02 | 1606 | #endif /* GFXMMU */ |
AnnaBridge | 161:aa5281ff4a02 | 1607 | |
AnnaBridge | 145:64910690c574 | 1608 | |
AnnaBridge | 145:64910690c574 | 1609 | #define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == RESET) |
AnnaBridge | 145:64910690c574 | 1610 | |
AnnaBridge | 145:64910690c574 | 1611 | #define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == RESET) |
AnnaBridge | 145:64910690c574 | 1612 | |
AnnaBridge | 161:aa5281ff4a02 | 1613 | #if defined(DMAMUX1) |
AnnaBridge | 161:aa5281ff4a02 | 1614 | #define __HAL_RCC_DMAMUX1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) == RESET) |
AnnaBridge | 161:aa5281ff4a02 | 1615 | #endif /* DMAMUX1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1616 | |
AnnaBridge | 145:64910690c574 | 1617 | #define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == RESET) |
AnnaBridge | 145:64910690c574 | 1618 | |
AnnaBridge | 145:64910690c574 | 1619 | #define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == RESET) |
AnnaBridge | 145:64910690c574 | 1620 | |
AnnaBridge | 145:64910690c574 | 1621 | #define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) == RESET) |
AnnaBridge | 145:64910690c574 | 1622 | |
AnnaBridge | 145:64910690c574 | 1623 | #if defined(DMA2D) |
AnnaBridge | 145:64910690c574 | 1624 | #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) == RESET) |
AnnaBridge | 145:64910690c574 | 1625 | #endif /* DMA2D */ |
AnnaBridge | 145:64910690c574 | 1626 | |
AnnaBridge | 161:aa5281ff4a02 | 1627 | #if defined(GFXMMU) |
AnnaBridge | 161:aa5281ff4a02 | 1628 | #define __HAL_RCC_GFXMMU_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) == RESET) |
AnnaBridge | 161:aa5281ff4a02 | 1629 | #endif /* GFXMMU */ |
AnnaBridge | 161:aa5281ff4a02 | 1630 | |
AnnaBridge | 145:64910690c574 | 1631 | /** |
AnnaBridge | 145:64910690c574 | 1632 | * @} |
AnnaBridge | 145:64910690c574 | 1633 | */ |
AnnaBridge | 145:64910690c574 | 1634 | |
AnnaBridge | 145:64910690c574 | 1635 | /** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status |
AnnaBridge | 145:64910690c574 | 1636 | * @brief Check whether the AHB2 peripheral clock is enabled or not. |
AnnaBridge | 145:64910690c574 | 1637 | * @note After reset, the peripheral clock (used for registers read/write access) |
AnnaBridge | 145:64910690c574 | 1638 | * is disabled and the application software has to enable this clock before |
AnnaBridge | 145:64910690c574 | 1639 | * using it. |
AnnaBridge | 145:64910690c574 | 1640 | * @{ |
AnnaBridge | 145:64910690c574 | 1641 | */ |
AnnaBridge | 145:64910690c574 | 1642 | |
AnnaBridge | 145:64910690c574 | 1643 | #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != RESET) |
AnnaBridge | 145:64910690c574 | 1644 | |
AnnaBridge | 161:aa5281ff4a02 | 1645 | #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) != RESET) |
AnnaBridge | 145:64910690c574 | 1646 | |
AnnaBridge | 145:64910690c574 | 1647 | #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET) |
AnnaBridge | 145:64910690c574 | 1648 | |
AnnaBridge | 145:64910690c574 | 1649 | #if defined(GPIOD) |
AnnaBridge | 145:64910690c574 | 1650 | #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != RESET) |
AnnaBridge | 145:64910690c574 | 1651 | #endif /* GPIOD */ |
AnnaBridge | 145:64910690c574 | 1652 | |
AnnaBridge | 145:64910690c574 | 1653 | #if defined(GPIOE) |
AnnaBridge | 145:64910690c574 | 1654 | #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != RESET) |
AnnaBridge | 145:64910690c574 | 1655 | #endif /* GPIOE */ |
AnnaBridge | 145:64910690c574 | 1656 | |
AnnaBridge | 145:64910690c574 | 1657 | #if defined(GPIOF) |
AnnaBridge | 145:64910690c574 | 1658 | #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != RESET) |
AnnaBridge | 145:64910690c574 | 1659 | #endif /* GPIOF */ |
AnnaBridge | 145:64910690c574 | 1660 | |
AnnaBridge | 145:64910690c574 | 1661 | #if defined(GPIOG) |
AnnaBridge | 145:64910690c574 | 1662 | #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != RESET) |
AnnaBridge | 145:64910690c574 | 1663 | #endif /* GPIOG */ |
AnnaBridge | 145:64910690c574 | 1664 | |
AnnaBridge | 145:64910690c574 | 1665 | #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) != RESET) |
AnnaBridge | 145:64910690c574 | 1666 | |
AnnaBridge | 145:64910690c574 | 1667 | #if defined(GPIOI) |
AnnaBridge | 145:64910690c574 | 1668 | #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) != RESET) |
AnnaBridge | 145:64910690c574 | 1669 | #endif /* GPIOI */ |
AnnaBridge | 145:64910690c574 | 1670 | |
AnnaBridge | 145:64910690c574 | 1671 | #if defined(USB_OTG_FS) |
AnnaBridge | 145:64910690c574 | 1672 | #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) != RESET) |
AnnaBridge | 145:64910690c574 | 1673 | #endif /* USB_OTG_FS */ |
AnnaBridge | 145:64910690c574 | 1674 | |
AnnaBridge | 145:64910690c574 | 1675 | #define __HAL_RCC_ADC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != RESET) |
AnnaBridge | 145:64910690c574 | 1676 | |
AnnaBridge | 145:64910690c574 | 1677 | #if defined(DCMI) |
AnnaBridge | 145:64910690c574 | 1678 | #define __HAL_RCC_DCMI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) != RESET) |
AnnaBridge | 145:64910690c574 | 1679 | #endif /* DCMI */ |
AnnaBridge | 145:64910690c574 | 1680 | |
AnnaBridge | 145:64910690c574 | 1681 | #if defined(AES) |
AnnaBridge | 145:64910690c574 | 1682 | #define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != RESET) |
AnnaBridge | 145:64910690c574 | 1683 | #endif /* AES */ |
AnnaBridge | 145:64910690c574 | 1684 | |
AnnaBridge | 145:64910690c574 | 1685 | #if defined(HASH) |
AnnaBridge | 145:64910690c574 | 1686 | #define __HAL_RCC_HASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) != RESET) |
AnnaBridge | 145:64910690c574 | 1687 | #endif /* HASH */ |
AnnaBridge | 145:64910690c574 | 1688 | |
AnnaBridge | 145:64910690c574 | 1689 | #define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != RESET) |
AnnaBridge | 145:64910690c574 | 1690 | |
AnnaBridge | 145:64910690c574 | 1691 | |
AnnaBridge | 145:64910690c574 | 1692 | #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == RESET) |
AnnaBridge | 145:64910690c574 | 1693 | |
AnnaBridge | 145:64910690c574 | 1694 | #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == RESET) |
AnnaBridge | 145:64910690c574 | 1695 | |
AnnaBridge | 145:64910690c574 | 1696 | #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == RESET) |
AnnaBridge | 145:64910690c574 | 1697 | |
AnnaBridge | 145:64910690c574 | 1698 | #if defined(GPIOD) |
AnnaBridge | 145:64910690c574 | 1699 | #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == RESET) |
AnnaBridge | 145:64910690c574 | 1700 | #endif /* GPIOD */ |
AnnaBridge | 145:64910690c574 | 1701 | |
AnnaBridge | 145:64910690c574 | 1702 | #if defined(GPIOE) |
AnnaBridge | 145:64910690c574 | 1703 | #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == RESET) |
AnnaBridge | 145:64910690c574 | 1704 | #endif /* GPIOE */ |
AnnaBridge | 145:64910690c574 | 1705 | |
AnnaBridge | 145:64910690c574 | 1706 | #if defined(GPIOF) |
AnnaBridge | 145:64910690c574 | 1707 | #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == RESET) |
AnnaBridge | 145:64910690c574 | 1708 | #endif /* GPIOF */ |
AnnaBridge | 145:64910690c574 | 1709 | |
AnnaBridge | 145:64910690c574 | 1710 | #if defined(GPIOG) |
AnnaBridge | 145:64910690c574 | 1711 | #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == RESET) |
AnnaBridge | 145:64910690c574 | 1712 | #endif /* GPIOG */ |
AnnaBridge | 145:64910690c574 | 1713 | |
AnnaBridge | 145:64910690c574 | 1714 | #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) == RESET) |
AnnaBridge | 145:64910690c574 | 1715 | |
AnnaBridge | 145:64910690c574 | 1716 | #if defined(GPIOI) |
AnnaBridge | 145:64910690c574 | 1717 | #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) == RESET) |
AnnaBridge | 145:64910690c574 | 1718 | #endif /* GPIOI */ |
AnnaBridge | 145:64910690c574 | 1719 | |
AnnaBridge | 145:64910690c574 | 1720 | #if defined(USB_OTG_FS) |
AnnaBridge | 145:64910690c574 | 1721 | #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) == RESET) |
AnnaBridge | 145:64910690c574 | 1722 | #endif /* USB_OTG_FS */ |
AnnaBridge | 145:64910690c574 | 1723 | |
AnnaBridge | 145:64910690c574 | 1724 | #define __HAL_RCC_ADC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) == RESET) |
AnnaBridge | 145:64910690c574 | 1725 | |
AnnaBridge | 145:64910690c574 | 1726 | #if defined(DCMI) |
AnnaBridge | 145:64910690c574 | 1727 | #define __HAL_RCC_DCMI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) == RESET) |
AnnaBridge | 145:64910690c574 | 1728 | #endif /* DCMI */ |
AnnaBridge | 145:64910690c574 | 1729 | |
AnnaBridge | 145:64910690c574 | 1730 | #if defined(AES) |
AnnaBridge | 145:64910690c574 | 1731 | #define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == RESET) |
AnnaBridge | 145:64910690c574 | 1732 | #endif /* AES */ |
AnnaBridge | 145:64910690c574 | 1733 | |
AnnaBridge | 145:64910690c574 | 1734 | #if defined(HASH) |
AnnaBridge | 145:64910690c574 | 1735 | #define __HAL_RCC_HASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) == RESET) |
AnnaBridge | 145:64910690c574 | 1736 | #endif /* HASH */ |
AnnaBridge | 145:64910690c574 | 1737 | |
AnnaBridge | 145:64910690c574 | 1738 | #define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == RESET) |
AnnaBridge | 145:64910690c574 | 1739 | |
AnnaBridge | 145:64910690c574 | 1740 | /** |
AnnaBridge | 145:64910690c574 | 1741 | * @} |
AnnaBridge | 145:64910690c574 | 1742 | */ |
AnnaBridge | 145:64910690c574 | 1743 | |
AnnaBridge | 145:64910690c574 | 1744 | /** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status |
AnnaBridge | 145:64910690c574 | 1745 | * @brief Check whether the AHB3 peripheral clock is enabled or not. |
AnnaBridge | 145:64910690c574 | 1746 | * @note After reset, the peripheral clock (used for registers read/write access) |
AnnaBridge | 145:64910690c574 | 1747 | * is disabled and the application software has to enable this clock before |
AnnaBridge | 145:64910690c574 | 1748 | * using it. |
AnnaBridge | 145:64910690c574 | 1749 | * @{ |
AnnaBridge | 145:64910690c574 | 1750 | */ |
AnnaBridge | 145:64910690c574 | 1751 | |
AnnaBridge | 145:64910690c574 | 1752 | #if defined(FMC_BANK1) |
AnnaBridge | 145:64910690c574 | 1753 | #define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != RESET) |
AnnaBridge | 145:64910690c574 | 1754 | #endif /* FMC_BANK1 */ |
AnnaBridge | 145:64910690c574 | 1755 | |
AnnaBridge | 145:64910690c574 | 1756 | #if defined(QUADSPI) |
AnnaBridge | 145:64910690c574 | 1757 | #define __HAL_RCC_QSPI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != RESET) |
AnnaBridge | 145:64910690c574 | 1758 | #endif /* QUADSPI */ |
AnnaBridge | 145:64910690c574 | 1759 | |
AnnaBridge | 145:64910690c574 | 1760 | #if defined(FMC_BANK1) |
AnnaBridge | 145:64910690c574 | 1761 | #define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == RESET) |
AnnaBridge | 145:64910690c574 | 1762 | #endif /* FMC_BANK1 */ |
AnnaBridge | 145:64910690c574 | 1763 | |
AnnaBridge | 145:64910690c574 | 1764 | #if defined(QUADSPI) |
AnnaBridge | 145:64910690c574 | 1765 | #define __HAL_RCC_QSPI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == RESET) |
AnnaBridge | 145:64910690c574 | 1766 | #endif /* QUADSPI */ |
AnnaBridge | 145:64910690c574 | 1767 | |
AnnaBridge | 145:64910690c574 | 1768 | /** |
AnnaBridge | 145:64910690c574 | 1769 | * @} |
AnnaBridge | 145:64910690c574 | 1770 | */ |
AnnaBridge | 145:64910690c574 | 1771 | |
AnnaBridge | 145:64910690c574 | 1772 | /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status |
AnnaBridge | 145:64910690c574 | 1773 | * @brief Check whether the APB1 peripheral clock is enabled or not. |
AnnaBridge | 145:64910690c574 | 1774 | * @note After reset, the peripheral clock (used for registers read/write access) |
AnnaBridge | 145:64910690c574 | 1775 | * is disabled and the application software has to enable this clock before |
AnnaBridge | 145:64910690c574 | 1776 | * using it. |
AnnaBridge | 145:64910690c574 | 1777 | * @{ |
AnnaBridge | 145:64910690c574 | 1778 | */ |
AnnaBridge | 145:64910690c574 | 1779 | |
AnnaBridge | 145:64910690c574 | 1780 | #define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != RESET) |
AnnaBridge | 145:64910690c574 | 1781 | |
AnnaBridge | 145:64910690c574 | 1782 | #if defined(TIM3) |
AnnaBridge | 145:64910690c574 | 1783 | #define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != RESET) |
AnnaBridge | 145:64910690c574 | 1784 | #endif /* TIM3 */ |
AnnaBridge | 145:64910690c574 | 1785 | |
AnnaBridge | 145:64910690c574 | 1786 | #if defined(TIM4) |
AnnaBridge | 145:64910690c574 | 1787 | #define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != RESET) |
AnnaBridge | 145:64910690c574 | 1788 | #endif /* TIM4 */ |
AnnaBridge | 145:64910690c574 | 1789 | |
AnnaBridge | 145:64910690c574 | 1790 | #if defined(TIM5) |
AnnaBridge | 145:64910690c574 | 1791 | #define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != RESET) |
AnnaBridge | 145:64910690c574 | 1792 | #endif /* TIM5 */ |
AnnaBridge | 145:64910690c574 | 1793 | |
AnnaBridge | 145:64910690c574 | 1794 | #define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != RESET) |
AnnaBridge | 145:64910690c574 | 1795 | |
AnnaBridge | 145:64910690c574 | 1796 | #define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != RESET) |
AnnaBridge | 145:64910690c574 | 1797 | |
AnnaBridge | 145:64910690c574 | 1798 | #if defined(LCD) |
AnnaBridge | 145:64910690c574 | 1799 | #define __HAL_RCC_LCD_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) != RESET) |
AnnaBridge | 145:64910690c574 | 1800 | #endif /* LCD */ |
AnnaBridge | 145:64910690c574 | 1801 | |
AnnaBridge | 145:64910690c574 | 1802 | #if defined(RCC_APB1ENR1_RTCAPBEN) |
AnnaBridge | 145:64910690c574 | 1803 | #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) != RESET) |
AnnaBridge | 145:64910690c574 | 1804 | #endif /* RCC_APB1ENR1_RTCAPBEN */ |
AnnaBridge | 145:64910690c574 | 1805 | |
AnnaBridge | 145:64910690c574 | 1806 | #define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != RESET) |
AnnaBridge | 145:64910690c574 | 1807 | |
AnnaBridge | 145:64910690c574 | 1808 | #if defined(SPI2) |
AnnaBridge | 145:64910690c574 | 1809 | #define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != RESET) |
AnnaBridge | 145:64910690c574 | 1810 | #endif /* SPI2 */ |
AnnaBridge | 145:64910690c574 | 1811 | |
AnnaBridge | 145:64910690c574 | 1812 | #define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != RESET) |
AnnaBridge | 145:64910690c574 | 1813 | |
AnnaBridge | 145:64910690c574 | 1814 | #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != RESET) |
AnnaBridge | 145:64910690c574 | 1815 | |
AnnaBridge | 145:64910690c574 | 1816 | #if defined(USART3) |
AnnaBridge | 145:64910690c574 | 1817 | #define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != RESET) |
AnnaBridge | 145:64910690c574 | 1818 | #endif /* USART3 */ |
AnnaBridge | 145:64910690c574 | 1819 | |
AnnaBridge | 145:64910690c574 | 1820 | #if defined(UART4) |
AnnaBridge | 145:64910690c574 | 1821 | #define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != RESET) |
AnnaBridge | 145:64910690c574 | 1822 | #endif /* UART4 */ |
AnnaBridge | 145:64910690c574 | 1823 | |
AnnaBridge | 145:64910690c574 | 1824 | #if defined(UART5) |
AnnaBridge | 145:64910690c574 | 1825 | #define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != RESET) |
AnnaBridge | 145:64910690c574 | 1826 | #endif /* UART5 */ |
AnnaBridge | 145:64910690c574 | 1827 | |
AnnaBridge | 145:64910690c574 | 1828 | #define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != RESET) |
AnnaBridge | 145:64910690c574 | 1829 | |
AnnaBridge | 145:64910690c574 | 1830 | #if defined(I2C2) |
AnnaBridge | 145:64910690c574 | 1831 | #define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != RESET) |
AnnaBridge | 145:64910690c574 | 1832 | #endif /* I2C2 */ |
AnnaBridge | 145:64910690c574 | 1833 | |
AnnaBridge | 145:64910690c574 | 1834 | #define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != RESET) |
AnnaBridge | 145:64910690c574 | 1835 | |
AnnaBridge | 145:64910690c574 | 1836 | #if defined(I2C4) |
AnnaBridge | 145:64910690c574 | 1837 | #define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != RESET) |
AnnaBridge | 145:64910690c574 | 1838 | #endif /* I2C4 */ |
AnnaBridge | 145:64910690c574 | 1839 | |
AnnaBridge | 145:64910690c574 | 1840 | #if defined(CRS) |
AnnaBridge | 145:64910690c574 | 1841 | #define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != RESET) |
AnnaBridge | 145:64910690c574 | 1842 | #endif /* CRS */ |
AnnaBridge | 145:64910690c574 | 1843 | |
AnnaBridge | 145:64910690c574 | 1844 | #define __HAL_RCC_CAN1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) != RESET) |
AnnaBridge | 145:64910690c574 | 1845 | |
AnnaBridge | 145:64910690c574 | 1846 | #if defined(CAN2) |
AnnaBridge | 145:64910690c574 | 1847 | #define __HAL_RCC_CAN2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) != RESET) |
AnnaBridge | 145:64910690c574 | 1848 | #endif /* CAN2 */ |
AnnaBridge | 145:64910690c574 | 1849 | |
AnnaBridge | 145:64910690c574 | 1850 | #if defined(USB) |
AnnaBridge | 145:64910690c574 | 1851 | #define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) != RESET) |
AnnaBridge | 145:64910690c574 | 1852 | #endif /* USB */ |
AnnaBridge | 145:64910690c574 | 1853 | |
AnnaBridge | 145:64910690c574 | 1854 | #define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != RESET) |
AnnaBridge | 145:64910690c574 | 1855 | |
AnnaBridge | 145:64910690c574 | 1856 | #define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) != RESET) |
AnnaBridge | 145:64910690c574 | 1857 | |
AnnaBridge | 145:64910690c574 | 1858 | #define __HAL_RCC_OPAMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) != RESET) |
AnnaBridge | 145:64910690c574 | 1859 | |
AnnaBridge | 145:64910690c574 | 1860 | #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != RESET) |
AnnaBridge | 145:64910690c574 | 1861 | |
AnnaBridge | 145:64910690c574 | 1862 | #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != RESET) |
AnnaBridge | 145:64910690c574 | 1863 | |
AnnaBridge | 145:64910690c574 | 1864 | #if defined(SWPMI1) |
AnnaBridge | 145:64910690c574 | 1865 | #define __HAL_RCC_SWPMI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) != RESET) |
AnnaBridge | 145:64910690c574 | 1866 | #endif /* SWPMI1 */ |
AnnaBridge | 145:64910690c574 | 1867 | |
AnnaBridge | 145:64910690c574 | 1868 | #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != RESET) |
AnnaBridge | 145:64910690c574 | 1869 | |
AnnaBridge | 145:64910690c574 | 1870 | |
AnnaBridge | 145:64910690c574 | 1871 | #define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == RESET) |
AnnaBridge | 145:64910690c574 | 1872 | |
AnnaBridge | 145:64910690c574 | 1873 | #if defined(TIM3) |
AnnaBridge | 145:64910690c574 | 1874 | #define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == RESET) |
AnnaBridge | 145:64910690c574 | 1875 | #endif /* TIM3 */ |
AnnaBridge | 145:64910690c574 | 1876 | |
AnnaBridge | 145:64910690c574 | 1877 | #if defined(TIM4) |
AnnaBridge | 145:64910690c574 | 1878 | #define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == RESET) |
AnnaBridge | 145:64910690c574 | 1879 | #endif /* TIM4 */ |
AnnaBridge | 145:64910690c574 | 1880 | |
AnnaBridge | 145:64910690c574 | 1881 | #if defined(TIM5) |
AnnaBridge | 145:64910690c574 | 1882 | #define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == RESET) |
AnnaBridge | 145:64910690c574 | 1883 | #endif /* TIM5 */ |
AnnaBridge | 145:64910690c574 | 1884 | |
AnnaBridge | 145:64910690c574 | 1885 | #define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == RESET) |
AnnaBridge | 145:64910690c574 | 1886 | |
AnnaBridge | 145:64910690c574 | 1887 | #define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == RESET) |
AnnaBridge | 145:64910690c574 | 1888 | |
AnnaBridge | 145:64910690c574 | 1889 | #if defined(LCD) |
AnnaBridge | 145:64910690c574 | 1890 | #define __HAL_RCC_LCD_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) == RESET) |
AnnaBridge | 145:64910690c574 | 1891 | #endif /* LCD */ |
AnnaBridge | 145:64910690c574 | 1892 | |
AnnaBridge | 145:64910690c574 | 1893 | #if defined(RCC_APB1ENR1_RTCAPBEN) |
AnnaBridge | 145:64910690c574 | 1894 | #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) == RESET) |
AnnaBridge | 145:64910690c574 | 1895 | #endif /* RCC_APB1ENR1_RTCAPBEN */ |
AnnaBridge | 145:64910690c574 | 1896 | |
AnnaBridge | 145:64910690c574 | 1897 | #define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == RESET) |
AnnaBridge | 145:64910690c574 | 1898 | |
AnnaBridge | 145:64910690c574 | 1899 | #if defined(SPI2) |
AnnaBridge | 145:64910690c574 | 1900 | #define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == RESET) |
AnnaBridge | 145:64910690c574 | 1901 | #endif /* SPI2 */ |
AnnaBridge | 145:64910690c574 | 1902 | |
AnnaBridge | 145:64910690c574 | 1903 | #define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == RESET) |
AnnaBridge | 145:64910690c574 | 1904 | |
AnnaBridge | 145:64910690c574 | 1905 | #define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == RESET) |
AnnaBridge | 145:64910690c574 | 1906 | |
AnnaBridge | 145:64910690c574 | 1907 | #if defined(USART3) |
AnnaBridge | 145:64910690c574 | 1908 | #define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == RESET) |
AnnaBridge | 145:64910690c574 | 1909 | #endif /* USART3 */ |
AnnaBridge | 145:64910690c574 | 1910 | |
AnnaBridge | 145:64910690c574 | 1911 | #if defined(UART4) |
AnnaBridge | 145:64910690c574 | 1912 | #define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == RESET) |
AnnaBridge | 145:64910690c574 | 1913 | #endif /* UART4 */ |
AnnaBridge | 145:64910690c574 | 1914 | |
AnnaBridge | 145:64910690c574 | 1915 | #if defined(UART5) |
AnnaBridge | 145:64910690c574 | 1916 | #define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == RESET) |
AnnaBridge | 145:64910690c574 | 1917 | #endif /* UART5 */ |
AnnaBridge | 145:64910690c574 | 1918 | |
AnnaBridge | 145:64910690c574 | 1919 | #define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == RESET) |
AnnaBridge | 145:64910690c574 | 1920 | |
AnnaBridge | 145:64910690c574 | 1921 | #if defined(I2C2) |
AnnaBridge | 145:64910690c574 | 1922 | #define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == RESET) |
AnnaBridge | 145:64910690c574 | 1923 | #endif /* I2C2 */ |
AnnaBridge | 145:64910690c574 | 1924 | |
AnnaBridge | 145:64910690c574 | 1925 | #define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == RESET) |
AnnaBridge | 145:64910690c574 | 1926 | |
AnnaBridge | 145:64910690c574 | 1927 | #if defined(I2C4) |
AnnaBridge | 145:64910690c574 | 1928 | #define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == RESET) |
AnnaBridge | 145:64910690c574 | 1929 | #endif /* I2C4 */ |
AnnaBridge | 145:64910690c574 | 1930 | |
AnnaBridge | 145:64910690c574 | 1931 | #if defined(CRS) |
AnnaBridge | 145:64910690c574 | 1932 | #define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == RESET) |
AnnaBridge | 145:64910690c574 | 1933 | #endif /* CRS */ |
AnnaBridge | 145:64910690c574 | 1934 | |
AnnaBridge | 145:64910690c574 | 1935 | #define __HAL_RCC_CAN1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) == RESET) |
AnnaBridge | 145:64910690c574 | 1936 | |
AnnaBridge | 145:64910690c574 | 1937 | #if defined(CAN2) |
AnnaBridge | 145:64910690c574 | 1938 | #define __HAL_RCC_CAN2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) == RESET) |
AnnaBridge | 145:64910690c574 | 1939 | #endif /* CAN2 */ |
AnnaBridge | 145:64910690c574 | 1940 | |
AnnaBridge | 145:64910690c574 | 1941 | #if defined(USB) |
AnnaBridge | 145:64910690c574 | 1942 | #define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) == RESET) |
AnnaBridge | 145:64910690c574 | 1943 | #endif /* USB */ |
AnnaBridge | 145:64910690c574 | 1944 | |
AnnaBridge | 145:64910690c574 | 1945 | #define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == RESET) |
AnnaBridge | 145:64910690c574 | 1946 | |
AnnaBridge | 145:64910690c574 | 1947 | #define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) == RESET) |
AnnaBridge | 145:64910690c574 | 1948 | |
AnnaBridge | 145:64910690c574 | 1949 | #define __HAL_RCC_OPAMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) == RESET) |
AnnaBridge | 145:64910690c574 | 1950 | |
AnnaBridge | 145:64910690c574 | 1951 | #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == RESET) |
AnnaBridge | 145:64910690c574 | 1952 | |
AnnaBridge | 145:64910690c574 | 1953 | #define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == RESET) |
AnnaBridge | 145:64910690c574 | 1954 | |
AnnaBridge | 145:64910690c574 | 1955 | #if defined(SWPMI1) |
AnnaBridge | 145:64910690c574 | 1956 | #define __HAL_RCC_SWPMI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) == RESET) |
AnnaBridge | 145:64910690c574 | 1957 | #endif /* SWPMI1 */ |
AnnaBridge | 145:64910690c574 | 1958 | |
AnnaBridge | 145:64910690c574 | 1959 | #define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) == RESET) |
AnnaBridge | 145:64910690c574 | 1960 | |
AnnaBridge | 145:64910690c574 | 1961 | /** |
AnnaBridge | 145:64910690c574 | 1962 | * @} |
AnnaBridge | 145:64910690c574 | 1963 | */ |
AnnaBridge | 145:64910690c574 | 1964 | |
AnnaBridge | 145:64910690c574 | 1965 | /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status |
AnnaBridge | 145:64910690c574 | 1966 | * @brief Check whether the APB2 peripheral clock is enabled or not. |
AnnaBridge | 145:64910690c574 | 1967 | * @note After reset, the peripheral clock (used for registers read/write access) |
AnnaBridge | 145:64910690c574 | 1968 | * is disabled and the application software has to enable this clock before |
AnnaBridge | 145:64910690c574 | 1969 | * using it. |
AnnaBridge | 145:64910690c574 | 1970 | * @{ |
AnnaBridge | 145:64910690c574 | 1971 | */ |
AnnaBridge | 145:64910690c574 | 1972 | |
AnnaBridge | 145:64910690c574 | 1973 | #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != RESET) |
AnnaBridge | 145:64910690c574 | 1974 | |
AnnaBridge | 145:64910690c574 | 1975 | #define __HAL_RCC_FIREWALL_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN) != RESET) |
AnnaBridge | 145:64910690c574 | 1976 | |
AnnaBridge | 161:aa5281ff4a02 | 1977 | #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) |
AnnaBridge | 145:64910690c574 | 1978 | #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) != RESET) |
AnnaBridge | 161:aa5281ff4a02 | 1979 | #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ |
AnnaBridge | 145:64910690c574 | 1980 | |
AnnaBridge | 145:64910690c574 | 1981 | #define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != RESET) |
AnnaBridge | 145:64910690c574 | 1982 | |
AnnaBridge | 145:64910690c574 | 1983 | #define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != RESET) |
AnnaBridge | 145:64910690c574 | 1984 | |
AnnaBridge | 145:64910690c574 | 1985 | #if defined(TIM8) |
AnnaBridge | 145:64910690c574 | 1986 | #define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != RESET) |
AnnaBridge | 145:64910690c574 | 1987 | #endif /* TIM8 */ |
AnnaBridge | 145:64910690c574 | 1988 | |
AnnaBridge | 145:64910690c574 | 1989 | #define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != RESET) |
AnnaBridge | 145:64910690c574 | 1990 | |
AnnaBridge | 145:64910690c574 | 1991 | #define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != RESET) |
AnnaBridge | 145:64910690c574 | 1992 | |
AnnaBridge | 145:64910690c574 | 1993 | #define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != RESET) |
AnnaBridge | 145:64910690c574 | 1994 | |
AnnaBridge | 145:64910690c574 | 1995 | #if defined(TIM17) |
AnnaBridge | 145:64910690c574 | 1996 | #define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != RESET) |
AnnaBridge | 145:64910690c574 | 1997 | #endif /* TIM17 */ |
AnnaBridge | 145:64910690c574 | 1998 | |
AnnaBridge | 145:64910690c574 | 1999 | #define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != RESET) |
AnnaBridge | 145:64910690c574 | 2000 | |
AnnaBridge | 145:64910690c574 | 2001 | #if defined(SAI2) |
AnnaBridge | 145:64910690c574 | 2002 | #define __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != RESET) |
AnnaBridge | 145:64910690c574 | 2003 | #endif /* SAI2 */ |
AnnaBridge | 145:64910690c574 | 2004 | |
AnnaBridge | 145:64910690c574 | 2005 | #if defined(DFSDM1_Filter0) |
AnnaBridge | 145:64910690c574 | 2006 | #define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) != RESET) |
AnnaBridge | 145:64910690c574 | 2007 | #endif /* DFSDM1_Filter0 */ |
AnnaBridge | 145:64910690c574 | 2008 | |
AnnaBridge | 161:aa5281ff4a02 | 2009 | #if defined(LTDC) |
AnnaBridge | 161:aa5281ff4a02 | 2010 | #define __HAL_RCC_LTDC_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) != RESET) |
AnnaBridge | 161:aa5281ff4a02 | 2011 | #endif /* LTDC */ |
AnnaBridge | 161:aa5281ff4a02 | 2012 | |
AnnaBridge | 161:aa5281ff4a02 | 2013 | #if defined(DSI) |
AnnaBridge | 161:aa5281ff4a02 | 2014 | #define __HAL_RCC_DSI_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) != RESET) |
AnnaBridge | 161:aa5281ff4a02 | 2015 | #endif /* DSI */ |
AnnaBridge | 161:aa5281ff4a02 | 2016 | |
AnnaBridge | 145:64910690c574 | 2017 | |
AnnaBridge | 145:64910690c574 | 2018 | #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == RESET) |
AnnaBridge | 145:64910690c574 | 2019 | |
AnnaBridge | 161:aa5281ff4a02 | 2020 | #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) |
AnnaBridge | 145:64910690c574 | 2021 | #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) == RESET) |
AnnaBridge | 161:aa5281ff4a02 | 2022 | #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ |
AnnaBridge | 145:64910690c574 | 2023 | |
AnnaBridge | 145:64910690c574 | 2024 | #define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == RESET) |
AnnaBridge | 145:64910690c574 | 2025 | |
AnnaBridge | 145:64910690c574 | 2026 | #define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == RESET) |
AnnaBridge | 145:64910690c574 | 2027 | |
AnnaBridge | 145:64910690c574 | 2028 | #if defined(TIM8) |
AnnaBridge | 145:64910690c574 | 2029 | #define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == RESET) |
AnnaBridge | 145:64910690c574 | 2030 | #endif /* TIM8 */ |
AnnaBridge | 145:64910690c574 | 2031 | |
AnnaBridge | 145:64910690c574 | 2032 | #define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == RESET) |
AnnaBridge | 145:64910690c574 | 2033 | |
AnnaBridge | 145:64910690c574 | 2034 | #define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == RESET) |
AnnaBridge | 145:64910690c574 | 2035 | |
AnnaBridge | 145:64910690c574 | 2036 | #define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == RESET) |
AnnaBridge | 145:64910690c574 | 2037 | |
AnnaBridge | 145:64910690c574 | 2038 | #if defined(TIM17) |
AnnaBridge | 145:64910690c574 | 2039 | #define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == RESET) |
AnnaBridge | 145:64910690c574 | 2040 | #endif /* TIM17 */ |
AnnaBridge | 145:64910690c574 | 2041 | |
AnnaBridge | 145:64910690c574 | 2042 | #define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == RESET) |
AnnaBridge | 145:64910690c574 | 2043 | |
AnnaBridge | 145:64910690c574 | 2044 | #if defined(SAI2) |
AnnaBridge | 145:64910690c574 | 2045 | #define __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == RESET) |
AnnaBridge | 145:64910690c574 | 2046 | #endif /* SAI2 */ |
AnnaBridge | 145:64910690c574 | 2047 | |
AnnaBridge | 145:64910690c574 | 2048 | #if defined(DFSDM1_Filter0) |
AnnaBridge | 145:64910690c574 | 2049 | #define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) == RESET) |
AnnaBridge | 145:64910690c574 | 2050 | #endif /* DFSDM1_Filter0 */ |
AnnaBridge | 145:64910690c574 | 2051 | |
AnnaBridge | 161:aa5281ff4a02 | 2052 | #if defined(LTDC) |
AnnaBridge | 161:aa5281ff4a02 | 2053 | #define __HAL_RCC_LTDC_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) == RESET) |
AnnaBridge | 161:aa5281ff4a02 | 2054 | #endif /* LTDC */ |
AnnaBridge | 161:aa5281ff4a02 | 2055 | |
AnnaBridge | 161:aa5281ff4a02 | 2056 | #if defined(DSI) |
AnnaBridge | 161:aa5281ff4a02 | 2057 | #define __HAL_RCC_DSI_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) == RESET) |
AnnaBridge | 161:aa5281ff4a02 | 2058 | #endif /* DSI */ |
AnnaBridge | 161:aa5281ff4a02 | 2059 | |
AnnaBridge | 145:64910690c574 | 2060 | /** |
AnnaBridge | 145:64910690c574 | 2061 | * @} |
AnnaBridge | 145:64910690c574 | 2062 | */ |
AnnaBridge | 145:64910690c574 | 2063 | |
AnnaBridge | 145:64910690c574 | 2064 | /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset |
AnnaBridge | 145:64910690c574 | 2065 | * @brief Force or release AHB1 peripheral reset. |
AnnaBridge | 145:64910690c574 | 2066 | * @{ |
AnnaBridge | 145:64910690c574 | 2067 | */ |
AnnaBridge | 145:64910690c574 | 2068 | #define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFU) |
AnnaBridge | 145:64910690c574 | 2069 | |
AnnaBridge | 145:64910690c574 | 2070 | #define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST) |
AnnaBridge | 145:64910690c574 | 2071 | |
AnnaBridge | 145:64910690c574 | 2072 | #define __HAL_RCC_DMA2_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST) |
AnnaBridge | 145:64910690c574 | 2073 | |
AnnaBridge | 161:aa5281ff4a02 | 2074 | #if defined(DMAMUX1) |
AnnaBridge | 161:aa5281ff4a02 | 2075 | #define __HAL_RCC_DMAMUX1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST) |
AnnaBridge | 161:aa5281ff4a02 | 2076 | #endif /* DMAMUX1 */ |
AnnaBridge | 161:aa5281ff4a02 | 2077 | |
AnnaBridge | 145:64910690c574 | 2078 | #define __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST) |
AnnaBridge | 145:64910690c574 | 2079 | |
AnnaBridge | 145:64910690c574 | 2080 | #define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) |
AnnaBridge | 145:64910690c574 | 2081 | |
AnnaBridge | 145:64910690c574 | 2082 | #define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) |
AnnaBridge | 145:64910690c574 | 2083 | |
AnnaBridge | 145:64910690c574 | 2084 | #if defined(DMA2D) |
AnnaBridge | 145:64910690c574 | 2085 | #define __HAL_RCC_DMA2D_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST) |
AnnaBridge | 145:64910690c574 | 2086 | #endif /* DMA2D */ |
AnnaBridge | 145:64910690c574 | 2087 | |
AnnaBridge | 161:aa5281ff4a02 | 2088 | #if defined(GFXMMU) |
AnnaBridge | 161:aa5281ff4a02 | 2089 | #define __HAL_RCC_GFXMMU_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GFXMMURST) |
AnnaBridge | 161:aa5281ff4a02 | 2090 | #endif /* GFXMMU */ |
AnnaBridge | 161:aa5281ff4a02 | 2091 | |
AnnaBridge | 145:64910690c574 | 2092 | |
AnnaBridge | 145:64910690c574 | 2093 | #define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U) |
AnnaBridge | 145:64910690c574 | 2094 | |
AnnaBridge | 145:64910690c574 | 2095 | #define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST) |
AnnaBridge | 145:64910690c574 | 2096 | |
AnnaBridge | 145:64910690c574 | 2097 | #define __HAL_RCC_DMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST) |
AnnaBridge | 145:64910690c574 | 2098 | |
AnnaBridge | 161:aa5281ff4a02 | 2099 | #if defined(DMAMUX1) |
AnnaBridge | 161:aa5281ff4a02 | 2100 | #define __HAL_RCC_DMAMUX1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST) |
AnnaBridge | 161:aa5281ff4a02 | 2101 | #endif /* DMAMUX1 */ |
AnnaBridge | 161:aa5281ff4a02 | 2102 | |
AnnaBridge | 145:64910690c574 | 2103 | #define __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST) |
AnnaBridge | 145:64910690c574 | 2104 | |
AnnaBridge | 145:64910690c574 | 2105 | #define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) |
AnnaBridge | 145:64910690c574 | 2106 | |
AnnaBridge | 145:64910690c574 | 2107 | #define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) |
AnnaBridge | 145:64910690c574 | 2108 | |
AnnaBridge | 145:64910690c574 | 2109 | #if defined(DMA2D) |
AnnaBridge | 145:64910690c574 | 2110 | #define __HAL_RCC_DMA2D_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST) |
AnnaBridge | 145:64910690c574 | 2111 | #endif /* DMA2D */ |
AnnaBridge | 145:64910690c574 | 2112 | |
AnnaBridge | 161:aa5281ff4a02 | 2113 | #if defined(GFXMMU) |
AnnaBridge | 161:aa5281ff4a02 | 2114 | #define __HAL_RCC_GFXMMU_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GFXMMURST) |
AnnaBridge | 161:aa5281ff4a02 | 2115 | #endif /* GFXMMU */ |
AnnaBridge | 161:aa5281ff4a02 | 2116 | |
AnnaBridge | 145:64910690c574 | 2117 | /** |
AnnaBridge | 145:64910690c574 | 2118 | * @} |
AnnaBridge | 145:64910690c574 | 2119 | */ |
AnnaBridge | 145:64910690c574 | 2120 | |
AnnaBridge | 145:64910690c574 | 2121 | /** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset |
AnnaBridge | 145:64910690c574 | 2122 | * @brief Force or release AHB2 peripheral reset. |
AnnaBridge | 145:64910690c574 | 2123 | * @{ |
AnnaBridge | 145:64910690c574 | 2124 | */ |
AnnaBridge | 145:64910690c574 | 2125 | #define __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFFU) |
AnnaBridge | 145:64910690c574 | 2126 | |
AnnaBridge | 145:64910690c574 | 2127 | #define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST) |
AnnaBridge | 145:64910690c574 | 2128 | |
AnnaBridge | 145:64910690c574 | 2129 | #define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST) |
AnnaBridge | 145:64910690c574 | 2130 | |
AnnaBridge | 145:64910690c574 | 2131 | #define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST) |
AnnaBridge | 145:64910690c574 | 2132 | |
AnnaBridge | 145:64910690c574 | 2133 | #if defined(GPIOD) |
AnnaBridge | 145:64910690c574 | 2134 | #define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST) |
AnnaBridge | 145:64910690c574 | 2135 | #endif /* GPIOD */ |
AnnaBridge | 145:64910690c574 | 2136 | |
AnnaBridge | 145:64910690c574 | 2137 | #if defined(GPIOE) |
AnnaBridge | 145:64910690c574 | 2138 | #define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST) |
AnnaBridge | 145:64910690c574 | 2139 | #endif /* GPIOE */ |
AnnaBridge | 145:64910690c574 | 2140 | |
AnnaBridge | 145:64910690c574 | 2141 | #if defined(GPIOF) |
AnnaBridge | 145:64910690c574 | 2142 | #define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST) |
AnnaBridge | 145:64910690c574 | 2143 | #endif /* GPIOF */ |
AnnaBridge | 145:64910690c574 | 2144 | |
AnnaBridge | 145:64910690c574 | 2145 | #if defined(GPIOG) |
AnnaBridge | 145:64910690c574 | 2146 | #define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST) |
AnnaBridge | 145:64910690c574 | 2147 | #endif /* GPIOG */ |
AnnaBridge | 145:64910690c574 | 2148 | |
AnnaBridge | 145:64910690c574 | 2149 | #define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST) |
AnnaBridge | 145:64910690c574 | 2150 | |
AnnaBridge | 145:64910690c574 | 2151 | #if defined(GPIOI) |
AnnaBridge | 145:64910690c574 | 2152 | #define __HAL_RCC_GPIOI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOIRST) |
AnnaBridge | 145:64910690c574 | 2153 | #endif /* GPIOI */ |
AnnaBridge | 145:64910690c574 | 2154 | |
AnnaBridge | 145:64910690c574 | 2155 | #if defined(USB_OTG_FS) |
AnnaBridge | 145:64910690c574 | 2156 | #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST) |
AnnaBridge | 145:64910690c574 | 2157 | #endif /* USB_OTG_FS */ |
AnnaBridge | 145:64910690c574 | 2158 | |
AnnaBridge | 145:64910690c574 | 2159 | #define __HAL_RCC_ADC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST) |
AnnaBridge | 145:64910690c574 | 2160 | |
AnnaBridge | 145:64910690c574 | 2161 | #if defined(DCMI) |
AnnaBridge | 145:64910690c574 | 2162 | #define __HAL_RCC_DCMI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DCMIRST) |
AnnaBridge | 145:64910690c574 | 2163 | #endif /* DCMI */ |
AnnaBridge | 145:64910690c574 | 2164 | |
AnnaBridge | 145:64910690c574 | 2165 | #if defined(AES) |
AnnaBridge | 145:64910690c574 | 2166 | #define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) |
AnnaBridge | 145:64910690c574 | 2167 | #endif /* AES */ |
AnnaBridge | 145:64910690c574 | 2168 | |
AnnaBridge | 145:64910690c574 | 2169 | #if defined(HASH) |
AnnaBridge | 145:64910690c574 | 2170 | #define __HAL_RCC_HASH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST) |
AnnaBridge | 145:64910690c574 | 2171 | #endif /* HASH */ |
AnnaBridge | 145:64910690c574 | 2172 | |
AnnaBridge | 145:64910690c574 | 2173 | #define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) |
AnnaBridge | 145:64910690c574 | 2174 | |
AnnaBridge | 161:aa5281ff4a02 | 2175 | #if defined(OCTOSPIM) |
AnnaBridge | 161:aa5281ff4a02 | 2176 | #define __HAL_RCC_OSPIM_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OSPIMRST) |
AnnaBridge | 161:aa5281ff4a02 | 2177 | #endif /* OCTOSPIM */ |
AnnaBridge | 161:aa5281ff4a02 | 2178 | |
AnnaBridge | 161:aa5281ff4a02 | 2179 | #if defined(SDMMC1) && defined(RCC_AHB2RSTR_SDMMC1RST) |
AnnaBridge | 161:aa5281ff4a02 | 2180 | #define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC1RST) |
AnnaBridge | 161:aa5281ff4a02 | 2181 | #endif /* SDMMC1 && RCC_AHB2RSTR_SDMMC1RST */ |
AnnaBridge | 161:aa5281ff4a02 | 2182 | |
AnnaBridge | 145:64910690c574 | 2183 | |
AnnaBridge | 145:64910690c574 | 2184 | #define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000U) |
AnnaBridge | 145:64910690c574 | 2185 | |
AnnaBridge | 145:64910690c574 | 2186 | #define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST) |
AnnaBridge | 145:64910690c574 | 2187 | |
AnnaBridge | 145:64910690c574 | 2188 | #define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST) |
AnnaBridge | 145:64910690c574 | 2189 | |
AnnaBridge | 145:64910690c574 | 2190 | #define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST) |
AnnaBridge | 145:64910690c574 | 2191 | |
AnnaBridge | 145:64910690c574 | 2192 | #if defined(GPIOD) |
AnnaBridge | 145:64910690c574 | 2193 | #define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST) |
AnnaBridge | 145:64910690c574 | 2194 | #endif /* GPIOD */ |
AnnaBridge | 145:64910690c574 | 2195 | |
AnnaBridge | 145:64910690c574 | 2196 | #if defined(GPIOE) |
AnnaBridge | 145:64910690c574 | 2197 | #define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST) |
AnnaBridge | 145:64910690c574 | 2198 | #endif /* GPIOE */ |
AnnaBridge | 145:64910690c574 | 2199 | |
AnnaBridge | 145:64910690c574 | 2200 | #if defined(GPIOF) |
AnnaBridge | 145:64910690c574 | 2201 | #define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST) |
AnnaBridge | 145:64910690c574 | 2202 | #endif /* GPIOF */ |
AnnaBridge | 145:64910690c574 | 2203 | |
AnnaBridge | 145:64910690c574 | 2204 | #if defined(GPIOG) |
AnnaBridge | 145:64910690c574 | 2205 | #define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST) |
AnnaBridge | 145:64910690c574 | 2206 | #endif /* GPIOG */ |
AnnaBridge | 145:64910690c574 | 2207 | |
AnnaBridge | 145:64910690c574 | 2208 | #define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST) |
AnnaBridge | 145:64910690c574 | 2209 | |
AnnaBridge | 145:64910690c574 | 2210 | #if defined(GPIOI) |
AnnaBridge | 145:64910690c574 | 2211 | #define __HAL_RCC_GPIOI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOIRST) |
AnnaBridge | 145:64910690c574 | 2212 | #endif /* GPIOI */ |
AnnaBridge | 145:64910690c574 | 2213 | |
AnnaBridge | 145:64910690c574 | 2214 | #if defined(USB_OTG_FS) |
AnnaBridge | 145:64910690c574 | 2215 | #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST) |
AnnaBridge | 145:64910690c574 | 2216 | #endif /* USB_OTG_FS */ |
AnnaBridge | 145:64910690c574 | 2217 | |
AnnaBridge | 145:64910690c574 | 2218 | #define __HAL_RCC_ADC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST) |
AnnaBridge | 145:64910690c574 | 2219 | |
AnnaBridge | 145:64910690c574 | 2220 | #if defined(DCMI) |
AnnaBridge | 145:64910690c574 | 2221 | #define __HAL_RCC_DCMI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DCMIRST) |
AnnaBridge | 145:64910690c574 | 2222 | #endif /* DCMI */ |
AnnaBridge | 145:64910690c574 | 2223 | |
AnnaBridge | 145:64910690c574 | 2224 | #if defined(AES) |
AnnaBridge | 145:64910690c574 | 2225 | #define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) |
AnnaBridge | 145:64910690c574 | 2226 | #endif /* AES */ |
AnnaBridge | 145:64910690c574 | 2227 | |
AnnaBridge | 145:64910690c574 | 2228 | #if defined(HASH) |
AnnaBridge | 145:64910690c574 | 2229 | #define __HAL_RCC_HASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST) |
AnnaBridge | 145:64910690c574 | 2230 | #endif /* HASH */ |
AnnaBridge | 145:64910690c574 | 2231 | |
AnnaBridge | 145:64910690c574 | 2232 | #define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) |
AnnaBridge | 145:64910690c574 | 2233 | |
AnnaBridge | 161:aa5281ff4a02 | 2234 | #if defined(OCTOSPIM) |
AnnaBridge | 161:aa5281ff4a02 | 2235 | #define __HAL_RCC_OSPIM_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OSPIMRST) |
AnnaBridge | 161:aa5281ff4a02 | 2236 | #endif /* OCTOSPIM */ |
AnnaBridge | 161:aa5281ff4a02 | 2237 | |
AnnaBridge | 161:aa5281ff4a02 | 2238 | #if defined(SDMMC1) && defined(RCC_AHB2RSTR_SDMMC1RST) |
AnnaBridge | 161:aa5281ff4a02 | 2239 | #define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC1RST) |
AnnaBridge | 161:aa5281ff4a02 | 2240 | #endif /* SDMMC1 && RCC_AHB2RSTR_SDMMC1RST */ |
AnnaBridge | 161:aa5281ff4a02 | 2241 | |
AnnaBridge | 145:64910690c574 | 2242 | /** |
AnnaBridge | 145:64910690c574 | 2243 | * @} |
AnnaBridge | 145:64910690c574 | 2244 | */ |
AnnaBridge | 145:64910690c574 | 2245 | |
AnnaBridge | 145:64910690c574 | 2246 | /** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset |
AnnaBridge | 145:64910690c574 | 2247 | * @brief Force or release AHB3 peripheral reset. |
AnnaBridge | 145:64910690c574 | 2248 | * @{ |
AnnaBridge | 145:64910690c574 | 2249 | */ |
AnnaBridge | 145:64910690c574 | 2250 | #define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFFU) |
AnnaBridge | 145:64910690c574 | 2251 | |
AnnaBridge | 145:64910690c574 | 2252 | #if defined(FMC_BANK1) |
AnnaBridge | 145:64910690c574 | 2253 | #define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST) |
AnnaBridge | 145:64910690c574 | 2254 | #endif /* FMC_BANK1 */ |
AnnaBridge | 145:64910690c574 | 2255 | |
AnnaBridge | 145:64910690c574 | 2256 | #if defined(QUADSPI) |
AnnaBridge | 145:64910690c574 | 2257 | #define __HAL_RCC_QSPI_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST) |
AnnaBridge | 145:64910690c574 | 2258 | #endif /* QUADSPI */ |
AnnaBridge | 145:64910690c574 | 2259 | |
AnnaBridge | 161:aa5281ff4a02 | 2260 | #if defined(OCTOSPI1) |
AnnaBridge | 161:aa5281ff4a02 | 2261 | #define __HAL_RCC_OSPI1_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI1RST) |
AnnaBridge | 161:aa5281ff4a02 | 2262 | #endif /* OCTOSPI1 */ |
AnnaBridge | 161:aa5281ff4a02 | 2263 | |
AnnaBridge | 161:aa5281ff4a02 | 2264 | #if defined(OCTOSPI2) |
AnnaBridge | 161:aa5281ff4a02 | 2265 | #define __HAL_RCC_OSPI2_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI2RST) |
AnnaBridge | 161:aa5281ff4a02 | 2266 | #endif /* OCTOSPI2 */ |
AnnaBridge | 161:aa5281ff4a02 | 2267 | |
AnnaBridge | 145:64910690c574 | 2268 | #define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000U) |
AnnaBridge | 145:64910690c574 | 2269 | |
AnnaBridge | 145:64910690c574 | 2270 | #if defined(FMC_BANK1) |
AnnaBridge | 145:64910690c574 | 2271 | #define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST) |
AnnaBridge | 145:64910690c574 | 2272 | #endif /* FMC_BANK1 */ |
AnnaBridge | 145:64910690c574 | 2273 | |
AnnaBridge | 145:64910690c574 | 2274 | #if defined(QUADSPI) |
AnnaBridge | 145:64910690c574 | 2275 | #define __HAL_RCC_QSPI_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST) |
AnnaBridge | 145:64910690c574 | 2276 | #endif /* QUADSPI */ |
AnnaBridge | 145:64910690c574 | 2277 | |
AnnaBridge | 161:aa5281ff4a02 | 2278 | #if defined(OCTOSPI1) |
AnnaBridge | 161:aa5281ff4a02 | 2279 | #define __HAL_RCC_OSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI1RST) |
AnnaBridge | 161:aa5281ff4a02 | 2280 | #endif /* OCTOSPI1 */ |
AnnaBridge | 161:aa5281ff4a02 | 2281 | |
AnnaBridge | 161:aa5281ff4a02 | 2282 | #if defined(OCTOSPI2) |
AnnaBridge | 161:aa5281ff4a02 | 2283 | #define __HAL_RCC_OSPI2_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI2RST) |
AnnaBridge | 161:aa5281ff4a02 | 2284 | #endif /* OCTOSPI2 */ |
AnnaBridge | 161:aa5281ff4a02 | 2285 | |
AnnaBridge | 145:64910690c574 | 2286 | /** |
AnnaBridge | 145:64910690c574 | 2287 | * @} |
AnnaBridge | 145:64910690c574 | 2288 | */ |
AnnaBridge | 145:64910690c574 | 2289 | |
AnnaBridge | 145:64910690c574 | 2290 | /** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset |
AnnaBridge | 145:64910690c574 | 2291 | * @brief Force or release APB1 peripheral reset. |
AnnaBridge | 145:64910690c574 | 2292 | * @{ |
AnnaBridge | 145:64910690c574 | 2293 | */ |
AnnaBridge | 145:64910690c574 | 2294 | #define __HAL_RCC_APB1_FORCE_RESET() WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFU) |
AnnaBridge | 145:64910690c574 | 2295 | |
AnnaBridge | 145:64910690c574 | 2296 | #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) |
AnnaBridge | 145:64910690c574 | 2297 | |
AnnaBridge | 145:64910690c574 | 2298 | #if defined(TIM3) |
AnnaBridge | 145:64910690c574 | 2299 | #define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) |
AnnaBridge | 145:64910690c574 | 2300 | #endif /* TIM3 */ |
AnnaBridge | 145:64910690c574 | 2301 | |
AnnaBridge | 145:64910690c574 | 2302 | #if defined(TIM4) |
AnnaBridge | 145:64910690c574 | 2303 | #define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST) |
AnnaBridge | 145:64910690c574 | 2304 | #endif /* TIM4 */ |
AnnaBridge | 145:64910690c574 | 2305 | |
AnnaBridge | 145:64910690c574 | 2306 | #if defined(TIM5) |
AnnaBridge | 145:64910690c574 | 2307 | #define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST) |
AnnaBridge | 145:64910690c574 | 2308 | #endif /* TIM5 */ |
AnnaBridge | 145:64910690c574 | 2309 | |
AnnaBridge | 145:64910690c574 | 2310 | #define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) |
AnnaBridge | 145:64910690c574 | 2311 | |
AnnaBridge | 145:64910690c574 | 2312 | #define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) |
AnnaBridge | 145:64910690c574 | 2313 | |
AnnaBridge | 145:64910690c574 | 2314 | #if defined(LCD) |
AnnaBridge | 145:64910690c574 | 2315 | #define __HAL_RCC_LCD_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST) |
AnnaBridge | 145:64910690c574 | 2316 | #endif /* LCD */ |
AnnaBridge | 145:64910690c574 | 2317 | |
AnnaBridge | 145:64910690c574 | 2318 | #if defined(SPI2) |
AnnaBridge | 145:64910690c574 | 2319 | #define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) |
AnnaBridge | 145:64910690c574 | 2320 | #endif /* SPI2 */ |
AnnaBridge | 145:64910690c574 | 2321 | |
AnnaBridge | 145:64910690c574 | 2322 | #define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST) |
AnnaBridge | 145:64910690c574 | 2323 | |
AnnaBridge | 145:64910690c574 | 2324 | #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) |
AnnaBridge | 145:64910690c574 | 2325 | |
AnnaBridge | 145:64910690c574 | 2326 | #if defined(USART3) |
AnnaBridge | 145:64910690c574 | 2327 | #define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) |
AnnaBridge | 145:64910690c574 | 2328 | #endif /* USART3 */ |
AnnaBridge | 145:64910690c574 | 2329 | |
AnnaBridge | 145:64910690c574 | 2330 | #if defined(UART4) |
AnnaBridge | 145:64910690c574 | 2331 | #define __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST) |
AnnaBridge | 145:64910690c574 | 2332 | #endif /* UART4 */ |
AnnaBridge | 145:64910690c574 | 2333 | |
AnnaBridge | 145:64910690c574 | 2334 | #if defined(UART5) |
AnnaBridge | 145:64910690c574 | 2335 | #define __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST) |
AnnaBridge | 145:64910690c574 | 2336 | #endif /* UART5 */ |
AnnaBridge | 145:64910690c574 | 2337 | |
AnnaBridge | 145:64910690c574 | 2338 | #define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) |
AnnaBridge | 145:64910690c574 | 2339 | |
AnnaBridge | 145:64910690c574 | 2340 | #if defined(I2C2) |
AnnaBridge | 145:64910690c574 | 2341 | #define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST) |
AnnaBridge | 145:64910690c574 | 2342 | #endif /* I2C2 */ |
AnnaBridge | 145:64910690c574 | 2343 | |
AnnaBridge | 145:64910690c574 | 2344 | #define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST) |
AnnaBridge | 145:64910690c574 | 2345 | |
AnnaBridge | 145:64910690c574 | 2346 | #if defined(I2C4) |
AnnaBridge | 145:64910690c574 | 2347 | #define __HAL_RCC_I2C4_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST) |
AnnaBridge | 145:64910690c574 | 2348 | #endif /* I2C4 */ |
AnnaBridge | 145:64910690c574 | 2349 | |
AnnaBridge | 145:64910690c574 | 2350 | #if defined(CRS) |
AnnaBridge | 145:64910690c574 | 2351 | #define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) |
AnnaBridge | 145:64910690c574 | 2352 | #endif /* CRS */ |
AnnaBridge | 145:64910690c574 | 2353 | |
AnnaBridge | 145:64910690c574 | 2354 | #define __HAL_RCC_CAN1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST) |
AnnaBridge | 145:64910690c574 | 2355 | |
AnnaBridge | 145:64910690c574 | 2356 | #if defined(CAN2) |
AnnaBridge | 145:64910690c574 | 2357 | #define __HAL_RCC_CAN2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN2RST) |
AnnaBridge | 145:64910690c574 | 2358 | #endif /* CAN2 */ |
AnnaBridge | 145:64910690c574 | 2359 | |
AnnaBridge | 145:64910690c574 | 2360 | #if defined(USB) |
AnnaBridge | 145:64910690c574 | 2361 | #define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBFSRST) |
AnnaBridge | 145:64910690c574 | 2362 | #endif /* USB */ |
AnnaBridge | 145:64910690c574 | 2363 | |
AnnaBridge | 145:64910690c574 | 2364 | #define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST) |
AnnaBridge | 145:64910690c574 | 2365 | |
AnnaBridge | 145:64910690c574 | 2366 | #define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST) |
AnnaBridge | 145:64910690c574 | 2367 | |
AnnaBridge | 145:64910690c574 | 2368 | #define __HAL_RCC_OPAMP_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST) |
AnnaBridge | 145:64910690c574 | 2369 | |
AnnaBridge | 145:64910690c574 | 2370 | #define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST) |
AnnaBridge | 145:64910690c574 | 2371 | |
AnnaBridge | 145:64910690c574 | 2372 | #define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST) |
AnnaBridge | 145:64910690c574 | 2373 | |
AnnaBridge | 145:64910690c574 | 2374 | #if defined(SWPMI1) |
AnnaBridge | 145:64910690c574 | 2375 | #define __HAL_RCC_SWPMI1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST) |
AnnaBridge | 145:64910690c574 | 2376 | #endif /* SWPMI1 */ |
AnnaBridge | 145:64910690c574 | 2377 | |
AnnaBridge | 145:64910690c574 | 2378 | #define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST) |
AnnaBridge | 145:64910690c574 | 2379 | |
AnnaBridge | 145:64910690c574 | 2380 | |
AnnaBridge | 145:64910690c574 | 2381 | #define __HAL_RCC_APB1_RELEASE_RESET() WRITE_REG(RCC->APB1RSTR1, 0x00000000U) |
AnnaBridge | 145:64910690c574 | 2382 | |
AnnaBridge | 145:64910690c574 | 2383 | #define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) |
AnnaBridge | 145:64910690c574 | 2384 | |
AnnaBridge | 145:64910690c574 | 2385 | #if defined(TIM3) |
AnnaBridge | 145:64910690c574 | 2386 | #define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) |
AnnaBridge | 145:64910690c574 | 2387 | #endif /* TIM3 */ |
AnnaBridge | 145:64910690c574 | 2388 | |
AnnaBridge | 145:64910690c574 | 2389 | #if defined(TIM4) |
AnnaBridge | 145:64910690c574 | 2390 | #define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST) |
AnnaBridge | 145:64910690c574 | 2391 | #endif /* TIM4 */ |
AnnaBridge | 145:64910690c574 | 2392 | |
AnnaBridge | 145:64910690c574 | 2393 | #if defined(TIM5) |
AnnaBridge | 145:64910690c574 | 2394 | #define __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST) |
AnnaBridge | 145:64910690c574 | 2395 | #endif /* TIM5 */ |
AnnaBridge | 145:64910690c574 | 2396 | |
AnnaBridge | 145:64910690c574 | 2397 | #define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) |
AnnaBridge | 145:64910690c574 | 2398 | |
AnnaBridge | 145:64910690c574 | 2399 | #define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) |
AnnaBridge | 145:64910690c574 | 2400 | |
AnnaBridge | 145:64910690c574 | 2401 | #if defined(LCD) |
AnnaBridge | 145:64910690c574 | 2402 | #define __HAL_RCC_LCD_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST) |
AnnaBridge | 145:64910690c574 | 2403 | #endif /* LCD */ |
AnnaBridge | 145:64910690c574 | 2404 | |
AnnaBridge | 145:64910690c574 | 2405 | #if defined(SPI2) |
AnnaBridge | 145:64910690c574 | 2406 | #define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) |
AnnaBridge | 145:64910690c574 | 2407 | #endif /* SPI2 */ |
AnnaBridge | 145:64910690c574 | 2408 | |
AnnaBridge | 145:64910690c574 | 2409 | #define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST) |
AnnaBridge | 145:64910690c574 | 2410 | |
AnnaBridge | 145:64910690c574 | 2411 | #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) |
AnnaBridge | 145:64910690c574 | 2412 | |
AnnaBridge | 145:64910690c574 | 2413 | #if defined(USART3) |
AnnaBridge | 145:64910690c574 | 2414 | #define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) |
AnnaBridge | 145:64910690c574 | 2415 | #endif /* USART3 */ |
AnnaBridge | 145:64910690c574 | 2416 | |
AnnaBridge | 145:64910690c574 | 2417 | #if defined(UART4) |
AnnaBridge | 145:64910690c574 | 2418 | #define __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST) |
AnnaBridge | 145:64910690c574 | 2419 | #endif /* UART4 */ |
AnnaBridge | 145:64910690c574 | 2420 | |
AnnaBridge | 145:64910690c574 | 2421 | #if defined(UART5) |
AnnaBridge | 145:64910690c574 | 2422 | #define __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST) |
AnnaBridge | 145:64910690c574 | 2423 | #endif /* UART5 */ |
AnnaBridge | 145:64910690c574 | 2424 | |
AnnaBridge | 145:64910690c574 | 2425 | #define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) |
AnnaBridge | 145:64910690c574 | 2426 | |
AnnaBridge | 145:64910690c574 | 2427 | #if defined(I2C2) |
AnnaBridge | 145:64910690c574 | 2428 | #define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST) |
AnnaBridge | 145:64910690c574 | 2429 | #endif /* I2C2 */ |
AnnaBridge | 145:64910690c574 | 2430 | |
AnnaBridge | 145:64910690c574 | 2431 | #define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST) |
AnnaBridge | 145:64910690c574 | 2432 | |
AnnaBridge | 145:64910690c574 | 2433 | #if defined(I2C4) |
AnnaBridge | 145:64910690c574 | 2434 | #define __HAL_RCC_I2C4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST) |
AnnaBridge | 145:64910690c574 | 2435 | #endif /* I2C4 */ |
AnnaBridge | 145:64910690c574 | 2436 | |
AnnaBridge | 145:64910690c574 | 2437 | #if defined(CRS) |
AnnaBridge | 145:64910690c574 | 2438 | #define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) |
AnnaBridge | 145:64910690c574 | 2439 | #endif /* CRS */ |
AnnaBridge | 145:64910690c574 | 2440 | |
AnnaBridge | 145:64910690c574 | 2441 | #define __HAL_RCC_CAN1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST) |
AnnaBridge | 145:64910690c574 | 2442 | |
AnnaBridge | 145:64910690c574 | 2443 | #if defined(CAN2) |
AnnaBridge | 145:64910690c574 | 2444 | #define __HAL_RCC_CAN2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN2RST) |
AnnaBridge | 145:64910690c574 | 2445 | #endif /* CAN2 */ |
AnnaBridge | 145:64910690c574 | 2446 | |
AnnaBridge | 145:64910690c574 | 2447 | #if defined(USB) |
AnnaBridge | 145:64910690c574 | 2448 | #define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBFSRST) |
AnnaBridge | 145:64910690c574 | 2449 | #endif /* USB */ |
AnnaBridge | 145:64910690c574 | 2450 | |
AnnaBridge | 145:64910690c574 | 2451 | #define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST) |
AnnaBridge | 145:64910690c574 | 2452 | |
AnnaBridge | 145:64910690c574 | 2453 | #define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST) |
AnnaBridge | 145:64910690c574 | 2454 | |
AnnaBridge | 145:64910690c574 | 2455 | #define __HAL_RCC_OPAMP_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST) |
AnnaBridge | 145:64910690c574 | 2456 | |
AnnaBridge | 145:64910690c574 | 2457 | #define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST) |
AnnaBridge | 145:64910690c574 | 2458 | |
AnnaBridge | 145:64910690c574 | 2459 | #define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST) |
AnnaBridge | 145:64910690c574 | 2460 | |
AnnaBridge | 145:64910690c574 | 2461 | #if defined(SWPMI1) |
AnnaBridge | 145:64910690c574 | 2462 | #define __HAL_RCC_SWPMI1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST) |
AnnaBridge | 145:64910690c574 | 2463 | #endif /* SWPMI1 */ |
AnnaBridge | 145:64910690c574 | 2464 | |
AnnaBridge | 145:64910690c574 | 2465 | #define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST) |
AnnaBridge | 145:64910690c574 | 2466 | |
AnnaBridge | 145:64910690c574 | 2467 | /** |
AnnaBridge | 145:64910690c574 | 2468 | * @} |
AnnaBridge | 145:64910690c574 | 2469 | */ |
AnnaBridge | 145:64910690c574 | 2470 | |
AnnaBridge | 145:64910690c574 | 2471 | /** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset |
AnnaBridge | 145:64910690c574 | 2472 | * @brief Force or release APB2 peripheral reset. |
AnnaBridge | 145:64910690c574 | 2473 | * @{ |
AnnaBridge | 145:64910690c574 | 2474 | */ |
AnnaBridge | 145:64910690c574 | 2475 | #define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFU) |
AnnaBridge | 145:64910690c574 | 2476 | |
AnnaBridge | 145:64910690c574 | 2477 | #define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST) |
AnnaBridge | 145:64910690c574 | 2478 | |
AnnaBridge | 161:aa5281ff4a02 | 2479 | #if defined(SDMMC1) && defined(RCC_APB2RSTR_SDMMC1RST) |
AnnaBridge | 145:64910690c574 | 2480 | #define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST) |
AnnaBridge | 161:aa5281ff4a02 | 2481 | #endif /* SDMMC1 && RCC_APB2RSTR_SDMMC1RST */ |
AnnaBridge | 145:64910690c574 | 2482 | |
AnnaBridge | 145:64910690c574 | 2483 | #define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) |
AnnaBridge | 145:64910690c574 | 2484 | |
AnnaBridge | 145:64910690c574 | 2485 | #define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) |
AnnaBridge | 145:64910690c574 | 2486 | |
AnnaBridge | 145:64910690c574 | 2487 | #if defined(TIM8) |
AnnaBridge | 145:64910690c574 | 2488 | #define __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) |
AnnaBridge | 145:64910690c574 | 2489 | #endif /* TIM8 */ |
AnnaBridge | 145:64910690c574 | 2490 | |
AnnaBridge | 145:64910690c574 | 2491 | #define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) |
AnnaBridge | 145:64910690c574 | 2492 | |
AnnaBridge | 145:64910690c574 | 2493 | #define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) |
AnnaBridge | 145:64910690c574 | 2494 | |
AnnaBridge | 145:64910690c574 | 2495 | #define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) |
AnnaBridge | 145:64910690c574 | 2496 | |
AnnaBridge | 145:64910690c574 | 2497 | #if defined(TIM17) |
AnnaBridge | 145:64910690c574 | 2498 | #define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) |
AnnaBridge | 145:64910690c574 | 2499 | #endif /* TIM17 */ |
AnnaBridge | 145:64910690c574 | 2500 | |
AnnaBridge | 145:64910690c574 | 2501 | #define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) |
AnnaBridge | 145:64910690c574 | 2502 | |
AnnaBridge | 145:64910690c574 | 2503 | #if defined(SAI2) |
AnnaBridge | 145:64910690c574 | 2504 | #define __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) |
AnnaBridge | 145:64910690c574 | 2505 | #endif /* SAI2 */ |
AnnaBridge | 145:64910690c574 | 2506 | |
AnnaBridge | 145:64910690c574 | 2507 | #if defined(DFSDM1_Filter0) |
AnnaBridge | 145:64910690c574 | 2508 | #define __HAL_RCC_DFSDM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST) |
AnnaBridge | 145:64910690c574 | 2509 | #endif /* DFSDM1_Filter0 */ |
AnnaBridge | 145:64910690c574 | 2510 | |
AnnaBridge | 161:aa5281ff4a02 | 2511 | #if defined(LTDC) |
AnnaBridge | 161:aa5281ff4a02 | 2512 | #define __HAL_RCC_LTDC_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST) |
AnnaBridge | 161:aa5281ff4a02 | 2513 | #endif /* LTDC */ |
AnnaBridge | 161:aa5281ff4a02 | 2514 | |
AnnaBridge | 161:aa5281ff4a02 | 2515 | #if defined(DSI) |
AnnaBridge | 161:aa5281ff4a02 | 2516 | #define __HAL_RCC_DSI_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DSIRST) |
AnnaBridge | 161:aa5281ff4a02 | 2517 | #endif /* DSI */ |
AnnaBridge | 161:aa5281ff4a02 | 2518 | |
AnnaBridge | 145:64910690c574 | 2519 | |
AnnaBridge | 145:64910690c574 | 2520 | #define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U) |
AnnaBridge | 145:64910690c574 | 2521 | |
AnnaBridge | 145:64910690c574 | 2522 | #define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST) |
AnnaBridge | 145:64910690c574 | 2523 | |
AnnaBridge | 161:aa5281ff4a02 | 2524 | #if defined(SDMMC1) && defined(RCC_APB2RSTR_SDMMC1RST) |
AnnaBridge | 145:64910690c574 | 2525 | #define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST) |
AnnaBridge | 161:aa5281ff4a02 | 2526 | #endif /* SDMMC1 && RCC_APB2RSTR_SDMMC1RST */ |
AnnaBridge | 145:64910690c574 | 2527 | |
AnnaBridge | 145:64910690c574 | 2528 | #define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) |
AnnaBridge | 145:64910690c574 | 2529 | |
AnnaBridge | 145:64910690c574 | 2530 | #define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) |
AnnaBridge | 145:64910690c574 | 2531 | |
AnnaBridge | 145:64910690c574 | 2532 | #if defined(TIM8) |
AnnaBridge | 145:64910690c574 | 2533 | #define __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) |
AnnaBridge | 145:64910690c574 | 2534 | #endif /* TIM8 */ |
AnnaBridge | 145:64910690c574 | 2535 | |
AnnaBridge | 145:64910690c574 | 2536 | #define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) |
AnnaBridge | 145:64910690c574 | 2537 | |
AnnaBridge | 145:64910690c574 | 2538 | #define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) |
AnnaBridge | 145:64910690c574 | 2539 | |
AnnaBridge | 145:64910690c574 | 2540 | #define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) |
AnnaBridge | 145:64910690c574 | 2541 | |
AnnaBridge | 145:64910690c574 | 2542 | #if defined(TIM17) |
AnnaBridge | 145:64910690c574 | 2543 | #define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) |
AnnaBridge | 145:64910690c574 | 2544 | #endif /* TIM17 */ |
AnnaBridge | 145:64910690c574 | 2545 | |
AnnaBridge | 145:64910690c574 | 2546 | #define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) |
AnnaBridge | 145:64910690c574 | 2547 | |
AnnaBridge | 145:64910690c574 | 2548 | #if defined(SAI2) |
AnnaBridge | 145:64910690c574 | 2549 | #define __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) |
AnnaBridge | 145:64910690c574 | 2550 | #endif /* SAI2 */ |
AnnaBridge | 145:64910690c574 | 2551 | |
AnnaBridge | 145:64910690c574 | 2552 | #if defined(DFSDM1_Filter0) |
AnnaBridge | 145:64910690c574 | 2553 | #define __HAL_RCC_DFSDM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST) |
AnnaBridge | 145:64910690c574 | 2554 | #endif /* DFSDM1_Filter0 */ |
AnnaBridge | 145:64910690c574 | 2555 | |
AnnaBridge | 161:aa5281ff4a02 | 2556 | #if defined(LTDC) |
AnnaBridge | 161:aa5281ff4a02 | 2557 | #define __HAL_RCC_LTDC_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST) |
AnnaBridge | 161:aa5281ff4a02 | 2558 | #endif /* LTDC */ |
AnnaBridge | 161:aa5281ff4a02 | 2559 | |
AnnaBridge | 161:aa5281ff4a02 | 2560 | #if defined(DSI) |
AnnaBridge | 161:aa5281ff4a02 | 2561 | #define __HAL_RCC_DSI_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DSIRST) |
AnnaBridge | 161:aa5281ff4a02 | 2562 | #endif /* DSI */ |
AnnaBridge | 161:aa5281ff4a02 | 2563 | |
AnnaBridge | 145:64910690c574 | 2564 | /** |
AnnaBridge | 145:64910690c574 | 2565 | * @} |
AnnaBridge | 145:64910690c574 | 2566 | */ |
AnnaBridge | 145:64910690c574 | 2567 | |
AnnaBridge | 145:64910690c574 | 2568 | /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable |
AnnaBridge | 145:64910690c574 | 2569 | * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. |
AnnaBridge | 145:64910690c574 | 2570 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
AnnaBridge | 145:64910690c574 | 2571 | * power consumption. |
AnnaBridge | 145:64910690c574 | 2572 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
AnnaBridge | 145:64910690c574 | 2573 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
AnnaBridge | 145:64910690c574 | 2574 | * @{ |
AnnaBridge | 145:64910690c574 | 2575 | */ |
AnnaBridge | 145:64910690c574 | 2576 | |
AnnaBridge | 145:64910690c574 | 2577 | #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) |
AnnaBridge | 145:64910690c574 | 2578 | |
AnnaBridge | 145:64910690c574 | 2579 | #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) |
AnnaBridge | 145:64910690c574 | 2580 | |
AnnaBridge | 161:aa5281ff4a02 | 2581 | #if defined(DMAMUX1) |
AnnaBridge | 161:aa5281ff4a02 | 2582 | #define __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) |
AnnaBridge | 161:aa5281ff4a02 | 2583 | #endif /* DMAMUX1 */ |
AnnaBridge | 161:aa5281ff4a02 | 2584 | |
AnnaBridge | 145:64910690c574 | 2585 | #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) |
AnnaBridge | 145:64910690c574 | 2586 | |
AnnaBridge | 145:64910690c574 | 2587 | #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) |
AnnaBridge | 145:64910690c574 | 2588 | |
AnnaBridge | 145:64910690c574 | 2589 | #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) |
AnnaBridge | 145:64910690c574 | 2590 | |
AnnaBridge | 145:64910690c574 | 2591 | #define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) |
AnnaBridge | 145:64910690c574 | 2592 | |
AnnaBridge | 145:64910690c574 | 2593 | #if defined(DMA2D) |
AnnaBridge | 145:64910690c574 | 2594 | #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) |
AnnaBridge | 145:64910690c574 | 2595 | #endif /* DMA2D */ |
AnnaBridge | 145:64910690c574 | 2596 | |
AnnaBridge | 161:aa5281ff4a02 | 2597 | #if defined(GFXMMU) |
AnnaBridge | 161:aa5281ff4a02 | 2598 | #define __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) |
AnnaBridge | 161:aa5281ff4a02 | 2599 | #endif /* GFXMMU */ |
AnnaBridge | 161:aa5281ff4a02 | 2600 | |
AnnaBridge | 145:64910690c574 | 2601 | |
AnnaBridge | 145:64910690c574 | 2602 | #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) |
AnnaBridge | 145:64910690c574 | 2603 | |
AnnaBridge | 145:64910690c574 | 2604 | #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) |
AnnaBridge | 145:64910690c574 | 2605 | |
AnnaBridge | 161:aa5281ff4a02 | 2606 | #if defined(DMAMUX1) |
AnnaBridge | 161:aa5281ff4a02 | 2607 | #define __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) |
AnnaBridge | 161:aa5281ff4a02 | 2608 | #endif /* DMAMUX1 */ |
AnnaBridge | 161:aa5281ff4a02 | 2609 | |
AnnaBridge | 145:64910690c574 | 2610 | #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) |
AnnaBridge | 145:64910690c574 | 2611 | |
AnnaBridge | 145:64910690c574 | 2612 | #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) |
AnnaBridge | 145:64910690c574 | 2613 | |
AnnaBridge | 145:64910690c574 | 2614 | #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) |
AnnaBridge | 145:64910690c574 | 2615 | |
AnnaBridge | 145:64910690c574 | 2616 | #define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) |
AnnaBridge | 145:64910690c574 | 2617 | |
AnnaBridge | 145:64910690c574 | 2618 | #if defined(DMA2D) |
AnnaBridge | 145:64910690c574 | 2619 | #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) |
AnnaBridge | 145:64910690c574 | 2620 | #endif /* DMA2D */ |
AnnaBridge | 145:64910690c574 | 2621 | |
AnnaBridge | 161:aa5281ff4a02 | 2622 | #if defined(GFXMMU) |
AnnaBridge | 161:aa5281ff4a02 | 2623 | #define __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) |
AnnaBridge | 161:aa5281ff4a02 | 2624 | #endif /* GFXMMU */ |
AnnaBridge | 161:aa5281ff4a02 | 2625 | |
AnnaBridge | 145:64910690c574 | 2626 | /** |
AnnaBridge | 145:64910690c574 | 2627 | * @} |
AnnaBridge | 145:64910690c574 | 2628 | */ |
AnnaBridge | 145:64910690c574 | 2629 | |
AnnaBridge | 145:64910690c574 | 2630 | /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable |
AnnaBridge | 145:64910690c574 | 2631 | * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. |
AnnaBridge | 145:64910690c574 | 2632 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
AnnaBridge | 145:64910690c574 | 2633 | * power consumption. |
AnnaBridge | 145:64910690c574 | 2634 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
AnnaBridge | 145:64910690c574 | 2635 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
AnnaBridge | 145:64910690c574 | 2636 | * @{ |
AnnaBridge | 145:64910690c574 | 2637 | */ |
AnnaBridge | 145:64910690c574 | 2638 | |
AnnaBridge | 145:64910690c574 | 2639 | #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) |
AnnaBridge | 145:64910690c574 | 2640 | |
AnnaBridge | 145:64910690c574 | 2641 | #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) |
AnnaBridge | 145:64910690c574 | 2642 | |
AnnaBridge | 145:64910690c574 | 2643 | #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) |
AnnaBridge | 145:64910690c574 | 2644 | |
AnnaBridge | 145:64910690c574 | 2645 | #if defined(GPIOD) |
AnnaBridge | 145:64910690c574 | 2646 | #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) |
AnnaBridge | 145:64910690c574 | 2647 | #endif /* GPIOD */ |
AnnaBridge | 145:64910690c574 | 2648 | |
AnnaBridge | 145:64910690c574 | 2649 | #if defined(GPIOE) |
AnnaBridge | 145:64910690c574 | 2650 | #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) |
AnnaBridge | 145:64910690c574 | 2651 | #endif /* GPIOE */ |
AnnaBridge | 145:64910690c574 | 2652 | |
AnnaBridge | 145:64910690c574 | 2653 | #if defined(GPIOF) |
AnnaBridge | 145:64910690c574 | 2654 | #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) |
AnnaBridge | 145:64910690c574 | 2655 | #endif /* GPIOF */ |
AnnaBridge | 145:64910690c574 | 2656 | |
AnnaBridge | 145:64910690c574 | 2657 | #if defined(GPIOG) |
AnnaBridge | 145:64910690c574 | 2658 | #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) |
AnnaBridge | 145:64910690c574 | 2659 | #endif /* GPIOG */ |
AnnaBridge | 145:64910690c574 | 2660 | |
AnnaBridge | 145:64910690c574 | 2661 | #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) |
AnnaBridge | 145:64910690c574 | 2662 | |
AnnaBridge | 145:64910690c574 | 2663 | #if defined(GPIOI) |
AnnaBridge | 145:64910690c574 | 2664 | #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) |
AnnaBridge | 145:64910690c574 | 2665 | #endif /* GPIOI */ |
AnnaBridge | 145:64910690c574 | 2666 | |
AnnaBridge | 145:64910690c574 | 2667 | #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) |
AnnaBridge | 145:64910690c574 | 2668 | |
AnnaBridge | 161:aa5281ff4a02 | 2669 | #if defined(SRAM3) |
AnnaBridge | 161:aa5281ff4a02 | 2670 | #define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) |
AnnaBridge | 161:aa5281ff4a02 | 2671 | #endif /* SRAM3 */ |
AnnaBridge | 161:aa5281ff4a02 | 2672 | |
AnnaBridge | 145:64910690c574 | 2673 | #if defined(USB_OTG_FS) |
AnnaBridge | 145:64910690c574 | 2674 | #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) |
AnnaBridge | 145:64910690c574 | 2675 | #endif /* USB_OTG_FS */ |
AnnaBridge | 145:64910690c574 | 2676 | |
AnnaBridge | 145:64910690c574 | 2677 | #define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) |
AnnaBridge | 145:64910690c574 | 2678 | |
AnnaBridge | 145:64910690c574 | 2679 | #if defined(DCMI) |
AnnaBridge | 145:64910690c574 | 2680 | #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) |
AnnaBridge | 145:64910690c574 | 2681 | #endif /* DCMI */ |
AnnaBridge | 145:64910690c574 | 2682 | |
AnnaBridge | 145:64910690c574 | 2683 | #if defined(AES) |
AnnaBridge | 145:64910690c574 | 2684 | #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) |
AnnaBridge | 145:64910690c574 | 2685 | #endif /* AES */ |
AnnaBridge | 145:64910690c574 | 2686 | |
AnnaBridge | 145:64910690c574 | 2687 | #if defined(HASH) |
AnnaBridge | 145:64910690c574 | 2688 | #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) |
AnnaBridge | 145:64910690c574 | 2689 | #endif /* HASH */ |
AnnaBridge | 145:64910690c574 | 2690 | |
AnnaBridge | 145:64910690c574 | 2691 | #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) |
AnnaBridge | 145:64910690c574 | 2692 | |
AnnaBridge | 161:aa5281ff4a02 | 2693 | #if defined(OCTOSPIM) |
AnnaBridge | 161:aa5281ff4a02 | 2694 | #define __HAL_RCC_OSPIM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) |
AnnaBridge | 161:aa5281ff4a02 | 2695 | #endif /* OCTOSPIM */ |
AnnaBridge | 161:aa5281ff4a02 | 2696 | |
AnnaBridge | 161:aa5281ff4a02 | 2697 | #if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN) |
AnnaBridge | 161:aa5281ff4a02 | 2698 | #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) |
AnnaBridge | 161:aa5281ff4a02 | 2699 | #endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */ |
AnnaBridge | 161:aa5281ff4a02 | 2700 | |
AnnaBridge | 145:64910690c574 | 2701 | |
AnnaBridge | 145:64910690c574 | 2702 | #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) |
AnnaBridge | 145:64910690c574 | 2703 | |
AnnaBridge | 145:64910690c574 | 2704 | #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) |
AnnaBridge | 145:64910690c574 | 2705 | |
AnnaBridge | 145:64910690c574 | 2706 | #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) |
AnnaBridge | 145:64910690c574 | 2707 | |
AnnaBridge | 145:64910690c574 | 2708 | #if defined(GPIOD) |
AnnaBridge | 145:64910690c574 | 2709 | #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) |
AnnaBridge | 145:64910690c574 | 2710 | #endif /* GPIOD */ |
AnnaBridge | 145:64910690c574 | 2711 | |
AnnaBridge | 145:64910690c574 | 2712 | #if defined(GPIOE) |
AnnaBridge | 145:64910690c574 | 2713 | #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) |
AnnaBridge | 145:64910690c574 | 2714 | #endif /* GPIOE */ |
AnnaBridge | 145:64910690c574 | 2715 | |
AnnaBridge | 145:64910690c574 | 2716 | #if defined(GPIOF) |
AnnaBridge | 145:64910690c574 | 2717 | #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) |
AnnaBridge | 145:64910690c574 | 2718 | #endif /* GPIOF */ |
AnnaBridge | 145:64910690c574 | 2719 | |
AnnaBridge | 145:64910690c574 | 2720 | #if defined(GPIOG) |
AnnaBridge | 145:64910690c574 | 2721 | #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) |
AnnaBridge | 145:64910690c574 | 2722 | #endif /* GPIOG */ |
AnnaBridge | 145:64910690c574 | 2723 | |
AnnaBridge | 145:64910690c574 | 2724 | #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) |
AnnaBridge | 145:64910690c574 | 2725 | |
AnnaBridge | 145:64910690c574 | 2726 | #if defined(GPIOI) |
AnnaBridge | 145:64910690c574 | 2727 | #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) |
AnnaBridge | 145:64910690c574 | 2728 | #endif /* GPIOI */ |
AnnaBridge | 145:64910690c574 | 2729 | |
AnnaBridge | 145:64910690c574 | 2730 | #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) |
AnnaBridge | 145:64910690c574 | 2731 | |
AnnaBridge | 161:aa5281ff4a02 | 2732 | #if defined(SRAM3) |
AnnaBridge | 161:aa5281ff4a02 | 2733 | #define __HAL_RCC_SRAM3_IS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) |
AnnaBridge | 161:aa5281ff4a02 | 2734 | #endif /* SRAM3 */ |
AnnaBridge | 161:aa5281ff4a02 | 2735 | |
AnnaBridge | 145:64910690c574 | 2736 | #if defined(USB_OTG_FS) |
AnnaBridge | 145:64910690c574 | 2737 | #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) |
AnnaBridge | 145:64910690c574 | 2738 | #endif /* USB_OTG_FS */ |
AnnaBridge | 145:64910690c574 | 2739 | |
AnnaBridge | 145:64910690c574 | 2740 | #define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) |
AnnaBridge | 145:64910690c574 | 2741 | |
AnnaBridge | 145:64910690c574 | 2742 | #if defined(DCMI) |
AnnaBridge | 145:64910690c574 | 2743 | #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) |
AnnaBridge | 145:64910690c574 | 2744 | #endif /* DCMI */ |
AnnaBridge | 145:64910690c574 | 2745 | |
AnnaBridge | 145:64910690c574 | 2746 | #if defined(AES) |
AnnaBridge | 145:64910690c574 | 2747 | #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) |
AnnaBridge | 145:64910690c574 | 2748 | #endif /* AES */ |
AnnaBridge | 145:64910690c574 | 2749 | |
AnnaBridge | 145:64910690c574 | 2750 | #if defined(HASH) |
AnnaBridge | 145:64910690c574 | 2751 | #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) |
AnnaBridge | 145:64910690c574 | 2752 | #endif /* HASH */ |
AnnaBridge | 145:64910690c574 | 2753 | |
AnnaBridge | 145:64910690c574 | 2754 | #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) |
AnnaBridge | 145:64910690c574 | 2755 | |
AnnaBridge | 161:aa5281ff4a02 | 2756 | #if defined(OCTOSPIM) |
AnnaBridge | 161:aa5281ff4a02 | 2757 | #define __HAL_RCC_OSPIM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) |
AnnaBridge | 161:aa5281ff4a02 | 2758 | #endif /* OCTOSPIM */ |
AnnaBridge | 161:aa5281ff4a02 | 2759 | |
AnnaBridge | 161:aa5281ff4a02 | 2760 | #if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN) |
AnnaBridge | 161:aa5281ff4a02 | 2761 | #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) |
AnnaBridge | 161:aa5281ff4a02 | 2762 | #endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */ |
AnnaBridge | 161:aa5281ff4a02 | 2763 | |
AnnaBridge | 145:64910690c574 | 2764 | /** |
AnnaBridge | 145:64910690c574 | 2765 | * @} |
AnnaBridge | 145:64910690c574 | 2766 | */ |
AnnaBridge | 145:64910690c574 | 2767 | |
AnnaBridge | 145:64910690c574 | 2768 | /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable |
AnnaBridge | 145:64910690c574 | 2769 | * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. |
AnnaBridge | 145:64910690c574 | 2770 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
AnnaBridge | 145:64910690c574 | 2771 | * power consumption. |
AnnaBridge | 145:64910690c574 | 2772 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
AnnaBridge | 145:64910690c574 | 2773 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
AnnaBridge | 145:64910690c574 | 2774 | * @{ |
AnnaBridge | 145:64910690c574 | 2775 | */ |
AnnaBridge | 145:64910690c574 | 2776 | |
AnnaBridge | 145:64910690c574 | 2777 | #if defined(QUADSPI) |
AnnaBridge | 145:64910690c574 | 2778 | #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) |
AnnaBridge | 145:64910690c574 | 2779 | #endif /* QUADSPI */ |
AnnaBridge | 145:64910690c574 | 2780 | |
AnnaBridge | 161:aa5281ff4a02 | 2781 | #if defined(OCTOSPI1) |
AnnaBridge | 161:aa5281ff4a02 | 2782 | #define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) |
AnnaBridge | 161:aa5281ff4a02 | 2783 | #endif /* OCTOSPI1 */ |
AnnaBridge | 161:aa5281ff4a02 | 2784 | |
AnnaBridge | 161:aa5281ff4a02 | 2785 | #if defined(OCTOSPI2) |
AnnaBridge | 161:aa5281ff4a02 | 2786 | #define __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) |
AnnaBridge | 161:aa5281ff4a02 | 2787 | #endif /* OCTOSPI2 */ |
AnnaBridge | 161:aa5281ff4a02 | 2788 | |
AnnaBridge | 145:64910690c574 | 2789 | #if defined(FMC_BANK1) |
AnnaBridge | 145:64910690c574 | 2790 | #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) |
AnnaBridge | 145:64910690c574 | 2791 | #endif /* FMC_BANK1 */ |
AnnaBridge | 145:64910690c574 | 2792 | |
AnnaBridge | 145:64910690c574 | 2793 | #if defined(QUADSPI) |
AnnaBridge | 145:64910690c574 | 2794 | #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) |
AnnaBridge | 145:64910690c574 | 2795 | #endif /* QUADSPI */ |
AnnaBridge | 145:64910690c574 | 2796 | |
AnnaBridge | 161:aa5281ff4a02 | 2797 | #if defined(OCTOSPI1) |
AnnaBridge | 161:aa5281ff4a02 | 2798 | #define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) |
AnnaBridge | 161:aa5281ff4a02 | 2799 | #endif /* OCTOSPI1 */ |
AnnaBridge | 161:aa5281ff4a02 | 2800 | |
AnnaBridge | 161:aa5281ff4a02 | 2801 | #if defined(OCTOSPI2) |
AnnaBridge | 161:aa5281ff4a02 | 2802 | #define __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) |
AnnaBridge | 161:aa5281ff4a02 | 2803 | #endif /* OCTOSPI2 */ |
AnnaBridge | 161:aa5281ff4a02 | 2804 | |
AnnaBridge | 145:64910690c574 | 2805 | #if defined(FMC_BANK1) |
AnnaBridge | 145:64910690c574 | 2806 | #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) |
AnnaBridge | 145:64910690c574 | 2807 | #endif /* FMC_BANK1 */ |
AnnaBridge | 145:64910690c574 | 2808 | |
AnnaBridge | 145:64910690c574 | 2809 | /** |
AnnaBridge | 145:64910690c574 | 2810 | * @} |
AnnaBridge | 145:64910690c574 | 2811 | */ |
AnnaBridge | 145:64910690c574 | 2812 | |
AnnaBridge | 145:64910690c574 | 2813 | /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable |
AnnaBridge | 145:64910690c574 | 2814 | * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. |
AnnaBridge | 145:64910690c574 | 2815 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
AnnaBridge | 145:64910690c574 | 2816 | * power consumption. |
AnnaBridge | 145:64910690c574 | 2817 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
AnnaBridge | 145:64910690c574 | 2818 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
AnnaBridge | 145:64910690c574 | 2819 | * @{ |
AnnaBridge | 145:64910690c574 | 2820 | */ |
AnnaBridge | 145:64910690c574 | 2821 | |
AnnaBridge | 145:64910690c574 | 2822 | #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) |
AnnaBridge | 145:64910690c574 | 2823 | |
AnnaBridge | 145:64910690c574 | 2824 | #if defined(TIM3) |
AnnaBridge | 145:64910690c574 | 2825 | #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) |
AnnaBridge | 145:64910690c574 | 2826 | #endif /* TIM3 */ |
AnnaBridge | 145:64910690c574 | 2827 | |
AnnaBridge | 145:64910690c574 | 2828 | #if defined(TIM4) |
AnnaBridge | 145:64910690c574 | 2829 | #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) |
AnnaBridge | 145:64910690c574 | 2830 | #endif /* TIM4 */ |
AnnaBridge | 145:64910690c574 | 2831 | |
AnnaBridge | 145:64910690c574 | 2832 | #if defined(TIM5) |
AnnaBridge | 145:64910690c574 | 2833 | #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) |
AnnaBridge | 145:64910690c574 | 2834 | #endif /* TIM5 */ |
AnnaBridge | 145:64910690c574 | 2835 | |
AnnaBridge | 145:64910690c574 | 2836 | #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) |
AnnaBridge | 145:64910690c574 | 2837 | |
AnnaBridge | 145:64910690c574 | 2838 | #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) |
AnnaBridge | 145:64910690c574 | 2839 | |
AnnaBridge | 145:64910690c574 | 2840 | #if defined(LCD) |
AnnaBridge | 145:64910690c574 | 2841 | #define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) |
AnnaBridge | 145:64910690c574 | 2842 | #endif /* LCD */ |
AnnaBridge | 145:64910690c574 | 2843 | |
AnnaBridge | 145:64910690c574 | 2844 | #if defined(RCC_APB1SMENR1_RTCAPBSMEN) |
AnnaBridge | 145:64910690c574 | 2845 | #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) |
AnnaBridge | 145:64910690c574 | 2846 | #endif /* RCC_APB1SMENR1_RTCAPBSMEN */ |
AnnaBridge | 145:64910690c574 | 2847 | |
AnnaBridge | 145:64910690c574 | 2848 | #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) |
AnnaBridge | 145:64910690c574 | 2849 | |
AnnaBridge | 145:64910690c574 | 2850 | #if defined(SPI2) |
AnnaBridge | 145:64910690c574 | 2851 | #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) |
AnnaBridge | 145:64910690c574 | 2852 | #endif /* SPI2 */ |
AnnaBridge | 145:64910690c574 | 2853 | |
AnnaBridge | 145:64910690c574 | 2854 | #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) |
AnnaBridge | 145:64910690c574 | 2855 | |
AnnaBridge | 145:64910690c574 | 2856 | #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) |
AnnaBridge | 145:64910690c574 | 2857 | |
AnnaBridge | 145:64910690c574 | 2858 | #if defined(USART3) |
AnnaBridge | 145:64910690c574 | 2859 | #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) |
AnnaBridge | 145:64910690c574 | 2860 | #endif /* USART3 */ |
AnnaBridge | 145:64910690c574 | 2861 | |
AnnaBridge | 145:64910690c574 | 2862 | #if defined(UART4) |
AnnaBridge | 145:64910690c574 | 2863 | #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) |
AnnaBridge | 145:64910690c574 | 2864 | #endif /* UART4 */ |
AnnaBridge | 145:64910690c574 | 2865 | |
AnnaBridge | 145:64910690c574 | 2866 | #if defined(UART5) |
AnnaBridge | 145:64910690c574 | 2867 | #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) |
AnnaBridge | 145:64910690c574 | 2868 | #endif /* UART5 */ |
AnnaBridge | 145:64910690c574 | 2869 | |
AnnaBridge | 145:64910690c574 | 2870 | #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) |
AnnaBridge | 145:64910690c574 | 2871 | |
AnnaBridge | 145:64910690c574 | 2872 | #if defined(I2C2) |
AnnaBridge | 145:64910690c574 | 2873 | #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) |
AnnaBridge | 145:64910690c574 | 2874 | #endif /* I2C2 */ |
AnnaBridge | 145:64910690c574 | 2875 | |
AnnaBridge | 145:64910690c574 | 2876 | #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) |
AnnaBridge | 145:64910690c574 | 2877 | |
AnnaBridge | 145:64910690c574 | 2878 | #if defined(I2C4) |
AnnaBridge | 145:64910690c574 | 2879 | #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) |
AnnaBridge | 145:64910690c574 | 2880 | #endif /* I2C4 */ |
AnnaBridge | 145:64910690c574 | 2881 | |
AnnaBridge | 145:64910690c574 | 2882 | #if defined(CRS) |
AnnaBridge | 145:64910690c574 | 2883 | #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) |
AnnaBridge | 145:64910690c574 | 2884 | #endif /* CRS */ |
AnnaBridge | 145:64910690c574 | 2885 | |
AnnaBridge | 145:64910690c574 | 2886 | #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) |
AnnaBridge | 145:64910690c574 | 2887 | |
AnnaBridge | 145:64910690c574 | 2888 | #if defined(CAN2) |
AnnaBridge | 145:64910690c574 | 2889 | #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) |
AnnaBridge | 145:64910690c574 | 2890 | #endif /* CAN2 */ |
AnnaBridge | 145:64910690c574 | 2891 | |
AnnaBridge | 145:64910690c574 | 2892 | #if defined(USB) |
AnnaBridge | 145:64910690c574 | 2893 | #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) |
AnnaBridge | 145:64910690c574 | 2894 | #endif /* USB */ |
AnnaBridge | 145:64910690c574 | 2895 | |
AnnaBridge | 145:64910690c574 | 2896 | #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) |
AnnaBridge | 145:64910690c574 | 2897 | |
AnnaBridge | 145:64910690c574 | 2898 | #define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) |
AnnaBridge | 145:64910690c574 | 2899 | |
AnnaBridge | 145:64910690c574 | 2900 | #define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) |
AnnaBridge | 145:64910690c574 | 2901 | |
AnnaBridge | 145:64910690c574 | 2902 | #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) |
AnnaBridge | 145:64910690c574 | 2903 | |
AnnaBridge | 145:64910690c574 | 2904 | #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) |
AnnaBridge | 145:64910690c574 | 2905 | |
AnnaBridge | 145:64910690c574 | 2906 | #if defined(SWPMI1) |
AnnaBridge | 145:64910690c574 | 2907 | #define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) |
AnnaBridge | 145:64910690c574 | 2908 | #endif /* SWPMI1 */ |
AnnaBridge | 145:64910690c574 | 2909 | |
AnnaBridge | 145:64910690c574 | 2910 | #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) |
AnnaBridge | 145:64910690c574 | 2911 | |
AnnaBridge | 145:64910690c574 | 2912 | |
AnnaBridge | 145:64910690c574 | 2913 | #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) |
AnnaBridge | 145:64910690c574 | 2914 | |
AnnaBridge | 145:64910690c574 | 2915 | #if defined(TIM3) |
AnnaBridge | 145:64910690c574 | 2916 | #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) |
AnnaBridge | 145:64910690c574 | 2917 | #endif /* TIM3 */ |
AnnaBridge | 145:64910690c574 | 2918 | |
AnnaBridge | 145:64910690c574 | 2919 | #if defined(TIM4) |
AnnaBridge | 145:64910690c574 | 2920 | #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) |
AnnaBridge | 145:64910690c574 | 2921 | #endif /* TIM4 */ |
AnnaBridge | 145:64910690c574 | 2922 | |
AnnaBridge | 145:64910690c574 | 2923 | #if defined(TIM5) |
AnnaBridge | 145:64910690c574 | 2924 | #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) |
AnnaBridge | 145:64910690c574 | 2925 | #endif /* TIM5 */ |
AnnaBridge | 145:64910690c574 | 2926 | |
AnnaBridge | 145:64910690c574 | 2927 | #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) |
AnnaBridge | 145:64910690c574 | 2928 | |
AnnaBridge | 145:64910690c574 | 2929 | #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) |
AnnaBridge | 145:64910690c574 | 2930 | |
AnnaBridge | 145:64910690c574 | 2931 | #if defined(LCD) |
AnnaBridge | 145:64910690c574 | 2932 | #define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) |
AnnaBridge | 145:64910690c574 | 2933 | #endif /* LCD */ |
AnnaBridge | 145:64910690c574 | 2934 | |
AnnaBridge | 145:64910690c574 | 2935 | #if defined(RCC_APB1SMENR1_RTCAPBSMEN) |
AnnaBridge | 145:64910690c574 | 2936 | #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) |
AnnaBridge | 145:64910690c574 | 2937 | #endif /* RCC_APB1SMENR1_RTCAPBSMEN */ |
AnnaBridge | 145:64910690c574 | 2938 | |
AnnaBridge | 145:64910690c574 | 2939 | #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) |
AnnaBridge | 145:64910690c574 | 2940 | |
AnnaBridge | 145:64910690c574 | 2941 | #if defined(SPI2) |
AnnaBridge | 145:64910690c574 | 2942 | #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) |
AnnaBridge | 145:64910690c574 | 2943 | #endif /* SPI2 */ |
AnnaBridge | 145:64910690c574 | 2944 | |
AnnaBridge | 145:64910690c574 | 2945 | #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) |
AnnaBridge | 145:64910690c574 | 2946 | |
AnnaBridge | 145:64910690c574 | 2947 | #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) |
AnnaBridge | 145:64910690c574 | 2948 | |
AnnaBridge | 145:64910690c574 | 2949 | #if defined(USART3) |
AnnaBridge | 145:64910690c574 | 2950 | #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) |
AnnaBridge | 145:64910690c574 | 2951 | #endif /* USART3 */ |
AnnaBridge | 145:64910690c574 | 2952 | |
AnnaBridge | 145:64910690c574 | 2953 | #if defined(UART4) |
AnnaBridge | 145:64910690c574 | 2954 | #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) |
AnnaBridge | 145:64910690c574 | 2955 | #endif /* UART4 */ |
AnnaBridge | 145:64910690c574 | 2956 | |
AnnaBridge | 145:64910690c574 | 2957 | #if defined(UART5) |
AnnaBridge | 145:64910690c574 | 2958 | #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) |
AnnaBridge | 145:64910690c574 | 2959 | #endif /* UART5 */ |
AnnaBridge | 145:64910690c574 | 2960 | |
AnnaBridge | 145:64910690c574 | 2961 | #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) |
AnnaBridge | 145:64910690c574 | 2962 | |
AnnaBridge | 145:64910690c574 | 2963 | #if defined(I2C2) |
AnnaBridge | 145:64910690c574 | 2964 | #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) |
AnnaBridge | 145:64910690c574 | 2965 | #endif /* I2C2 */ |
AnnaBridge | 145:64910690c574 | 2966 | |
AnnaBridge | 145:64910690c574 | 2967 | #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) |
AnnaBridge | 145:64910690c574 | 2968 | |
AnnaBridge | 145:64910690c574 | 2969 | #if defined(I2C4) |
AnnaBridge | 145:64910690c574 | 2970 | #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) |
AnnaBridge | 145:64910690c574 | 2971 | #endif /* I2C4 */ |
AnnaBridge | 145:64910690c574 | 2972 | |
AnnaBridge | 145:64910690c574 | 2973 | #if defined(CRS) |
AnnaBridge | 145:64910690c574 | 2974 | #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) |
AnnaBridge | 145:64910690c574 | 2975 | #endif /* CRS */ |
AnnaBridge | 145:64910690c574 | 2976 | |
AnnaBridge | 145:64910690c574 | 2977 | #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) |
AnnaBridge | 145:64910690c574 | 2978 | |
AnnaBridge | 145:64910690c574 | 2979 | #if defined(CAN2) |
AnnaBridge | 145:64910690c574 | 2980 | #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) |
AnnaBridge | 145:64910690c574 | 2981 | #endif /* CAN2 */ |
AnnaBridge | 145:64910690c574 | 2982 | |
AnnaBridge | 145:64910690c574 | 2983 | #if defined(USB) |
AnnaBridge | 145:64910690c574 | 2984 | #define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) |
AnnaBridge | 145:64910690c574 | 2985 | #endif /* USB */ |
AnnaBridge | 145:64910690c574 | 2986 | |
AnnaBridge | 145:64910690c574 | 2987 | #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) |
AnnaBridge | 145:64910690c574 | 2988 | |
AnnaBridge | 145:64910690c574 | 2989 | #define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) |
AnnaBridge | 145:64910690c574 | 2990 | |
AnnaBridge | 145:64910690c574 | 2991 | #define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) |
AnnaBridge | 145:64910690c574 | 2992 | |
AnnaBridge | 145:64910690c574 | 2993 | #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) |
AnnaBridge | 145:64910690c574 | 2994 | |
AnnaBridge | 145:64910690c574 | 2995 | #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) |
AnnaBridge | 145:64910690c574 | 2996 | |
AnnaBridge | 145:64910690c574 | 2997 | #if defined(SWPMI1) |
AnnaBridge | 145:64910690c574 | 2998 | #define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) |
AnnaBridge | 145:64910690c574 | 2999 | #endif /* SWPMI1 */ |
AnnaBridge | 145:64910690c574 | 3000 | |
AnnaBridge | 145:64910690c574 | 3001 | #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) |
AnnaBridge | 145:64910690c574 | 3002 | |
AnnaBridge | 145:64910690c574 | 3003 | /** |
AnnaBridge | 145:64910690c574 | 3004 | * @} |
AnnaBridge | 145:64910690c574 | 3005 | */ |
AnnaBridge | 145:64910690c574 | 3006 | |
AnnaBridge | 145:64910690c574 | 3007 | /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable |
AnnaBridge | 145:64910690c574 | 3008 | * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. |
AnnaBridge | 145:64910690c574 | 3009 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
AnnaBridge | 145:64910690c574 | 3010 | * power consumption. |
AnnaBridge | 145:64910690c574 | 3011 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
AnnaBridge | 145:64910690c574 | 3012 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
AnnaBridge | 145:64910690c574 | 3013 | * @{ |
AnnaBridge | 145:64910690c574 | 3014 | */ |
AnnaBridge | 145:64910690c574 | 3015 | |
AnnaBridge | 145:64910690c574 | 3016 | #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) |
AnnaBridge | 145:64910690c574 | 3017 | |
AnnaBridge | 161:aa5281ff4a02 | 3018 | #if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN) |
AnnaBridge | 145:64910690c574 | 3019 | #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) |
AnnaBridge | 161:aa5281ff4a02 | 3020 | #endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */ |
AnnaBridge | 145:64910690c574 | 3021 | |
AnnaBridge | 145:64910690c574 | 3022 | #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) |
AnnaBridge | 145:64910690c574 | 3023 | |
AnnaBridge | 145:64910690c574 | 3024 | #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) |
AnnaBridge | 145:64910690c574 | 3025 | |
AnnaBridge | 145:64910690c574 | 3026 | #if defined(TIM8) |
AnnaBridge | 145:64910690c574 | 3027 | #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) |
AnnaBridge | 145:64910690c574 | 3028 | #endif /* TIM8 */ |
AnnaBridge | 145:64910690c574 | 3029 | |
AnnaBridge | 145:64910690c574 | 3030 | #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) |
AnnaBridge | 145:64910690c574 | 3031 | |
AnnaBridge | 145:64910690c574 | 3032 | #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) |
AnnaBridge | 145:64910690c574 | 3033 | |
AnnaBridge | 145:64910690c574 | 3034 | #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) |
AnnaBridge | 145:64910690c574 | 3035 | |
AnnaBridge | 145:64910690c574 | 3036 | #if defined(TIM17) |
AnnaBridge | 145:64910690c574 | 3037 | #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) |
AnnaBridge | 145:64910690c574 | 3038 | #endif /* TIM17 */ |
AnnaBridge | 145:64910690c574 | 3039 | |
AnnaBridge | 145:64910690c574 | 3040 | #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) |
AnnaBridge | 145:64910690c574 | 3041 | |
AnnaBridge | 145:64910690c574 | 3042 | #if defined(SAI2) |
AnnaBridge | 145:64910690c574 | 3043 | #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) |
AnnaBridge | 145:64910690c574 | 3044 | #endif /* SAI2 */ |
AnnaBridge | 145:64910690c574 | 3045 | |
AnnaBridge | 145:64910690c574 | 3046 | #if defined(DFSDM1_Filter0) |
AnnaBridge | 145:64910690c574 | 3047 | #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) |
AnnaBridge | 145:64910690c574 | 3048 | #endif /* DFSDM1_Filter0 */ |
AnnaBridge | 145:64910690c574 | 3049 | |
AnnaBridge | 161:aa5281ff4a02 | 3050 | #if defined(LTDC) |
AnnaBridge | 161:aa5281ff4a02 | 3051 | #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) |
AnnaBridge | 161:aa5281ff4a02 | 3052 | #endif /* LTDC */ |
AnnaBridge | 161:aa5281ff4a02 | 3053 | |
AnnaBridge | 161:aa5281ff4a02 | 3054 | #if defined(DSI) |
AnnaBridge | 161:aa5281ff4a02 | 3055 | #define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) |
AnnaBridge | 161:aa5281ff4a02 | 3056 | #endif /* DSI */ |
AnnaBridge | 161:aa5281ff4a02 | 3057 | |
AnnaBridge | 145:64910690c574 | 3058 | |
AnnaBridge | 145:64910690c574 | 3059 | #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) |
AnnaBridge | 145:64910690c574 | 3060 | |
AnnaBridge | 161:aa5281ff4a02 | 3061 | #if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN) |
AnnaBridge | 145:64910690c574 | 3062 | #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) |
AnnaBridge | 161:aa5281ff4a02 | 3063 | #endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */ |
AnnaBridge | 145:64910690c574 | 3064 | |
AnnaBridge | 145:64910690c574 | 3065 | #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) |
AnnaBridge | 145:64910690c574 | 3066 | |
AnnaBridge | 145:64910690c574 | 3067 | #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) |
AnnaBridge | 145:64910690c574 | 3068 | |
AnnaBridge | 145:64910690c574 | 3069 | #if defined(TIM8) |
AnnaBridge | 145:64910690c574 | 3070 | #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) |
AnnaBridge | 145:64910690c574 | 3071 | #endif /* TIM8 */ |
AnnaBridge | 145:64910690c574 | 3072 | |
AnnaBridge | 145:64910690c574 | 3073 | #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) |
AnnaBridge | 145:64910690c574 | 3074 | |
AnnaBridge | 145:64910690c574 | 3075 | #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) |
AnnaBridge | 145:64910690c574 | 3076 | |
AnnaBridge | 145:64910690c574 | 3077 | #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) |
AnnaBridge | 145:64910690c574 | 3078 | |
AnnaBridge | 145:64910690c574 | 3079 | #if defined(TIM17) |
AnnaBridge | 145:64910690c574 | 3080 | #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) |
AnnaBridge | 145:64910690c574 | 3081 | #endif /* TIM17 */ |
AnnaBridge | 145:64910690c574 | 3082 | |
AnnaBridge | 145:64910690c574 | 3083 | #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) |
AnnaBridge | 145:64910690c574 | 3084 | |
AnnaBridge | 145:64910690c574 | 3085 | #if defined(SAI2) |
AnnaBridge | 145:64910690c574 | 3086 | #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) |
AnnaBridge | 145:64910690c574 | 3087 | #endif /* SAI2 */ |
AnnaBridge | 145:64910690c574 | 3088 | |
AnnaBridge | 145:64910690c574 | 3089 | #if defined(DFSDM1_Filter0) |
AnnaBridge | 145:64910690c574 | 3090 | #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) |
AnnaBridge | 145:64910690c574 | 3091 | #endif /* DFSDM1_Filter0 */ |
AnnaBridge | 145:64910690c574 | 3092 | |
AnnaBridge | 161:aa5281ff4a02 | 3093 | #if defined(LTDC) |
AnnaBridge | 161:aa5281ff4a02 | 3094 | #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) |
AnnaBridge | 161:aa5281ff4a02 | 3095 | #endif /* LTDC */ |
AnnaBridge | 161:aa5281ff4a02 | 3096 | |
AnnaBridge | 161:aa5281ff4a02 | 3097 | #if defined(DSI) |
AnnaBridge | 161:aa5281ff4a02 | 3098 | #define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) |
AnnaBridge | 161:aa5281ff4a02 | 3099 | #endif /* DSI */ |
AnnaBridge | 161:aa5281ff4a02 | 3100 | |
AnnaBridge | 145:64910690c574 | 3101 | /** |
AnnaBridge | 145:64910690c574 | 3102 | * @} |
AnnaBridge | 145:64910690c574 | 3103 | */ |
AnnaBridge | 145:64910690c574 | 3104 | |
AnnaBridge | 145:64910690c574 | 3105 | /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enabled or Disabled Status |
AnnaBridge | 145:64910690c574 | 3106 | * @brief Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not. |
AnnaBridge | 145:64910690c574 | 3107 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
AnnaBridge | 145:64910690c574 | 3108 | * power consumption. |
AnnaBridge | 145:64910690c574 | 3109 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
AnnaBridge | 145:64910690c574 | 3110 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
AnnaBridge | 145:64910690c574 | 3111 | * @{ |
AnnaBridge | 145:64910690c574 | 3112 | */ |
AnnaBridge | 145:64910690c574 | 3113 | |
AnnaBridge | 145:64910690c574 | 3114 | #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3115 | |
AnnaBridge | 145:64910690c574 | 3116 | #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3117 | |
AnnaBridge | 161:aa5281ff4a02 | 3118 | #if defined(DMAMUX1) |
AnnaBridge | 161:aa5281ff4a02 | 3119 | #define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) != RESET) |
AnnaBridge | 161:aa5281ff4a02 | 3120 | #endif /* DMAMUX1 */ |
AnnaBridge | 161:aa5281ff4a02 | 3121 | |
AnnaBridge | 145:64910690c574 | 3122 | #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3123 | |
AnnaBridge | 145:64910690c574 | 3124 | #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3125 | |
AnnaBridge | 145:64910690c574 | 3126 | #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3127 | |
AnnaBridge | 145:64910690c574 | 3128 | #define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3129 | |
AnnaBridge | 145:64910690c574 | 3130 | #if defined(DMA2D) |
AnnaBridge | 145:64910690c574 | 3131 | #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3132 | #endif /* DMA2D */ |
AnnaBridge | 145:64910690c574 | 3133 | |
AnnaBridge | 161:aa5281ff4a02 | 3134 | #if defined(GFXMMU) |
AnnaBridge | 161:aa5281ff4a02 | 3135 | #define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) != RESET) |
AnnaBridge | 161:aa5281ff4a02 | 3136 | #endif /* GFXMMU */ |
AnnaBridge | 161:aa5281ff4a02 | 3137 | |
AnnaBridge | 145:64910690c574 | 3138 | |
AnnaBridge | 145:64910690c574 | 3139 | #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3140 | |
AnnaBridge | 145:64910690c574 | 3141 | #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3142 | |
AnnaBridge | 161:aa5281ff4a02 | 3143 | #if defined(DMAMUX1) |
AnnaBridge | 161:aa5281ff4a02 | 3144 | #define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) == RESET) |
AnnaBridge | 161:aa5281ff4a02 | 3145 | #endif /* DMAMUX1 */ |
AnnaBridge | 161:aa5281ff4a02 | 3146 | |
AnnaBridge | 145:64910690c574 | 3147 | #define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3148 | |
AnnaBridge | 145:64910690c574 | 3149 | #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3150 | |
AnnaBridge | 145:64910690c574 | 3151 | #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3152 | |
AnnaBridge | 145:64910690c574 | 3153 | #define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3154 | |
AnnaBridge | 145:64910690c574 | 3155 | #if defined(DMA2D) |
AnnaBridge | 145:64910690c574 | 3156 | #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3157 | #endif /* DMA2D */ |
AnnaBridge | 145:64910690c574 | 3158 | |
AnnaBridge | 161:aa5281ff4a02 | 3159 | #if defined(GFXMMU) |
AnnaBridge | 161:aa5281ff4a02 | 3160 | #define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) == RESET) |
AnnaBridge | 161:aa5281ff4a02 | 3161 | #endif /* GFXMMU */ |
AnnaBridge | 161:aa5281ff4a02 | 3162 | |
AnnaBridge | 145:64910690c574 | 3163 | /** |
AnnaBridge | 145:64910690c574 | 3164 | * @} |
AnnaBridge | 145:64910690c574 | 3165 | */ |
AnnaBridge | 145:64910690c574 | 3166 | |
AnnaBridge | 145:64910690c574 | 3167 | /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enabled or Disabled Status |
AnnaBridge | 145:64910690c574 | 3168 | * @brief Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not. |
AnnaBridge | 145:64910690c574 | 3169 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
AnnaBridge | 145:64910690c574 | 3170 | * power consumption. |
AnnaBridge | 145:64910690c574 | 3171 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
AnnaBridge | 145:64910690c574 | 3172 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
AnnaBridge | 145:64910690c574 | 3173 | * @{ |
AnnaBridge | 145:64910690c574 | 3174 | */ |
AnnaBridge | 145:64910690c574 | 3175 | |
AnnaBridge | 145:64910690c574 | 3176 | #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3177 | |
AnnaBridge | 145:64910690c574 | 3178 | #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3179 | |
AnnaBridge | 145:64910690c574 | 3180 | #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3181 | |
AnnaBridge | 145:64910690c574 | 3182 | #if defined(GPIOD) |
AnnaBridge | 145:64910690c574 | 3183 | #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3184 | #endif /* GPIOD */ |
AnnaBridge | 145:64910690c574 | 3185 | |
AnnaBridge | 145:64910690c574 | 3186 | #if defined(GPIOE) |
AnnaBridge | 145:64910690c574 | 3187 | #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3188 | #endif /* GPIOE */ |
AnnaBridge | 145:64910690c574 | 3189 | |
AnnaBridge | 145:64910690c574 | 3190 | #if defined(GPIOF) |
AnnaBridge | 145:64910690c574 | 3191 | #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3192 | #endif /* GPIOF */ |
AnnaBridge | 145:64910690c574 | 3193 | |
AnnaBridge | 145:64910690c574 | 3194 | #if defined(GPIOG) |
AnnaBridge | 145:64910690c574 | 3195 | #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3196 | #endif /* GPIOG */ |
AnnaBridge | 145:64910690c574 | 3197 | |
AnnaBridge | 145:64910690c574 | 3198 | #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3199 | |
AnnaBridge | 145:64910690c574 | 3200 | #if defined(GPIOI) |
AnnaBridge | 145:64910690c574 | 3201 | #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3202 | #endif /* GPIOI */ |
AnnaBridge | 145:64910690c574 | 3203 | |
AnnaBridge | 145:64910690c574 | 3204 | #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3205 | |
AnnaBridge | 161:aa5281ff4a02 | 3206 | #if defined(SRAM3) |
AnnaBridge | 161:aa5281ff4a02 | 3207 | #define __HAL_RCC_SRAM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) != RESET) |
AnnaBridge | 161:aa5281ff4a02 | 3208 | #endif /* SRAM3 */ |
AnnaBridge | 161:aa5281ff4a02 | 3209 | |
AnnaBridge | 145:64910690c574 | 3210 | #if defined(USB_OTG_FS) |
AnnaBridge | 145:64910690c574 | 3211 | #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3212 | #endif /* USB_OTG_FS */ |
AnnaBridge | 145:64910690c574 | 3213 | |
AnnaBridge | 145:64910690c574 | 3214 | #define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3215 | |
AnnaBridge | 145:64910690c574 | 3216 | #if defined(DCMI) |
AnnaBridge | 145:64910690c574 | 3217 | #define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3218 | #endif /* DCMI */ |
AnnaBridge | 145:64910690c574 | 3219 | |
AnnaBridge | 145:64910690c574 | 3220 | #if defined(AES) |
AnnaBridge | 145:64910690c574 | 3221 | #define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3222 | #endif /* AES */ |
AnnaBridge | 145:64910690c574 | 3223 | |
AnnaBridge | 145:64910690c574 | 3224 | #if defined(HASH) |
AnnaBridge | 145:64910690c574 | 3225 | #define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3226 | #endif /* HASH */ |
AnnaBridge | 145:64910690c574 | 3227 | |
AnnaBridge | 145:64910690c574 | 3228 | #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3229 | |
AnnaBridge | 161:aa5281ff4a02 | 3230 | #if defined(OCTOSPIM) |
AnnaBridge | 161:aa5281ff4a02 | 3231 | #define __HAL_RCC_OSPIM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) != RESET) |
AnnaBridge | 161:aa5281ff4a02 | 3232 | #endif /* OCTOSPIM */ |
AnnaBridge | 161:aa5281ff4a02 | 3233 | |
AnnaBridge | 161:aa5281ff4a02 | 3234 | #if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN) |
AnnaBridge | 161:aa5281ff4a02 | 3235 | #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) != RESET) |
AnnaBridge | 161:aa5281ff4a02 | 3236 | #endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */ |
AnnaBridge | 161:aa5281ff4a02 | 3237 | |
AnnaBridge | 145:64910690c574 | 3238 | |
AnnaBridge | 145:64910690c574 | 3239 | #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3240 | |
AnnaBridge | 145:64910690c574 | 3241 | #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3242 | |
AnnaBridge | 145:64910690c574 | 3243 | #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3244 | |
AnnaBridge | 145:64910690c574 | 3245 | #if defined(GPIOD) |
AnnaBridge | 145:64910690c574 | 3246 | #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3247 | #endif /* GPIOD */ |
AnnaBridge | 145:64910690c574 | 3248 | |
AnnaBridge | 145:64910690c574 | 3249 | #if defined(GPIOE) |
AnnaBridge | 145:64910690c574 | 3250 | #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3251 | #endif /* GPIOE */ |
AnnaBridge | 145:64910690c574 | 3252 | |
AnnaBridge | 145:64910690c574 | 3253 | #if defined(GPIOF) |
AnnaBridge | 145:64910690c574 | 3254 | #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3255 | #endif /* GPIOF */ |
AnnaBridge | 145:64910690c574 | 3256 | |
AnnaBridge | 145:64910690c574 | 3257 | #if defined(GPIOG) |
AnnaBridge | 145:64910690c574 | 3258 | #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3259 | #endif /* GPIOG */ |
AnnaBridge | 145:64910690c574 | 3260 | |
AnnaBridge | 145:64910690c574 | 3261 | #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3262 | |
AnnaBridge | 145:64910690c574 | 3263 | #if defined(GPIOI) |
AnnaBridge | 145:64910690c574 | 3264 | #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3265 | #endif /* GPIOI */ |
AnnaBridge | 145:64910690c574 | 3266 | |
AnnaBridge | 145:64910690c574 | 3267 | #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3268 | |
AnnaBridge | 161:aa5281ff4a02 | 3269 | #if defined(SRAM3) |
AnnaBridge | 161:aa5281ff4a02 | 3270 | #define __HAL_RCC_SRAM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) == RESET) |
AnnaBridge | 161:aa5281ff4a02 | 3271 | #endif /* SRAM3 */ |
AnnaBridge | 161:aa5281ff4a02 | 3272 | |
AnnaBridge | 145:64910690c574 | 3273 | #if defined(USB_OTG_FS) |
AnnaBridge | 145:64910690c574 | 3274 | #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3275 | #endif /* USB_OTG_FS */ |
AnnaBridge | 145:64910690c574 | 3276 | |
AnnaBridge | 145:64910690c574 | 3277 | #define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3278 | |
AnnaBridge | 145:64910690c574 | 3279 | #if defined(DCMI) |
AnnaBridge | 145:64910690c574 | 3280 | #define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3281 | #endif /* DCMI */ |
AnnaBridge | 145:64910690c574 | 3282 | |
AnnaBridge | 145:64910690c574 | 3283 | #if defined(AES) |
AnnaBridge | 145:64910690c574 | 3284 | #define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3285 | #endif /* AES */ |
AnnaBridge | 145:64910690c574 | 3286 | |
AnnaBridge | 145:64910690c574 | 3287 | #if defined(HASH) |
AnnaBridge | 145:64910690c574 | 3288 | #define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3289 | #endif /* HASH */ |
AnnaBridge | 145:64910690c574 | 3290 | |
AnnaBridge | 145:64910690c574 | 3291 | #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3292 | |
AnnaBridge | 161:aa5281ff4a02 | 3293 | #if defined(OCTOSPIM) |
AnnaBridge | 161:aa5281ff4a02 | 3294 | #define __HAL_RCC_OSPIM_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) == RESET) |
AnnaBridge | 161:aa5281ff4a02 | 3295 | #endif /* OCTOSPIM */ |
AnnaBridge | 161:aa5281ff4a02 | 3296 | |
AnnaBridge | 161:aa5281ff4a02 | 3297 | #if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN) |
AnnaBridge | 161:aa5281ff4a02 | 3298 | #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) == RESET) |
AnnaBridge | 161:aa5281ff4a02 | 3299 | #endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */ |
AnnaBridge | 161:aa5281ff4a02 | 3300 | |
AnnaBridge | 145:64910690c574 | 3301 | /** |
AnnaBridge | 145:64910690c574 | 3302 | * @} |
AnnaBridge | 145:64910690c574 | 3303 | */ |
AnnaBridge | 145:64910690c574 | 3304 | |
AnnaBridge | 145:64910690c574 | 3305 | /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock Sleep Enabled or Disabled Status |
AnnaBridge | 145:64910690c574 | 3306 | * @brief Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not. |
AnnaBridge | 145:64910690c574 | 3307 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
AnnaBridge | 145:64910690c574 | 3308 | * power consumption. |
AnnaBridge | 145:64910690c574 | 3309 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
AnnaBridge | 145:64910690c574 | 3310 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
AnnaBridge | 145:64910690c574 | 3311 | * @{ |
AnnaBridge | 145:64910690c574 | 3312 | */ |
AnnaBridge | 145:64910690c574 | 3313 | |
AnnaBridge | 145:64910690c574 | 3314 | #if defined(QUADSPI) |
AnnaBridge | 145:64910690c574 | 3315 | #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3316 | #endif /* QUADSPI */ |
AnnaBridge | 145:64910690c574 | 3317 | |
AnnaBridge | 161:aa5281ff4a02 | 3318 | #if defined(OCTOSPI1) |
AnnaBridge | 161:aa5281ff4a02 | 3319 | #define __HAL_RCC_OSPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) != RESET) |
AnnaBridge | 161:aa5281ff4a02 | 3320 | #endif /* OCTOSPI1 */ |
AnnaBridge | 161:aa5281ff4a02 | 3321 | |
AnnaBridge | 161:aa5281ff4a02 | 3322 | #if defined(OCTOSPI2) |
AnnaBridge | 161:aa5281ff4a02 | 3323 | #define __HAL_RCC_OSPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) != RESET) |
AnnaBridge | 161:aa5281ff4a02 | 3324 | #endif /* OCTOSPI2 */ |
AnnaBridge | 161:aa5281ff4a02 | 3325 | |
AnnaBridge | 145:64910690c574 | 3326 | #if defined(FMC_BANK1) |
AnnaBridge | 145:64910690c574 | 3327 | #define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3328 | #endif /* FMC_BANK1 */ |
AnnaBridge | 145:64910690c574 | 3329 | |
AnnaBridge | 161:aa5281ff4a02 | 3330 | |
AnnaBridge | 145:64910690c574 | 3331 | #if defined(QUADSPI) |
AnnaBridge | 145:64910690c574 | 3332 | #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3333 | #endif /* QUADSPI */ |
AnnaBridge | 145:64910690c574 | 3334 | |
AnnaBridge | 161:aa5281ff4a02 | 3335 | #if defined(OCTOSPI1) |
AnnaBridge | 161:aa5281ff4a02 | 3336 | #define __HAL_RCC_OSPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) == RESET) |
AnnaBridge | 161:aa5281ff4a02 | 3337 | #endif /* OCTOSPI1 */ |
AnnaBridge | 161:aa5281ff4a02 | 3338 | |
AnnaBridge | 161:aa5281ff4a02 | 3339 | #if defined(OCTOSPI2) |
AnnaBridge | 161:aa5281ff4a02 | 3340 | #define __HAL_RCC_OSPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) == RESET) |
AnnaBridge | 161:aa5281ff4a02 | 3341 | #endif /* OCTOSPI2 */ |
AnnaBridge | 161:aa5281ff4a02 | 3342 | |
AnnaBridge | 145:64910690c574 | 3343 | #if defined(FMC_BANK1) |
AnnaBridge | 145:64910690c574 | 3344 | #define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3345 | #endif /* FMC_BANK1 */ |
AnnaBridge | 145:64910690c574 | 3346 | |
AnnaBridge | 145:64910690c574 | 3347 | /** |
AnnaBridge | 145:64910690c574 | 3348 | * @} |
AnnaBridge | 145:64910690c574 | 3349 | */ |
AnnaBridge | 145:64910690c574 | 3350 | |
AnnaBridge | 145:64910690c574 | 3351 | /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status |
AnnaBridge | 145:64910690c574 | 3352 | * @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not. |
AnnaBridge | 145:64910690c574 | 3353 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
AnnaBridge | 145:64910690c574 | 3354 | * power consumption. |
AnnaBridge | 145:64910690c574 | 3355 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
AnnaBridge | 145:64910690c574 | 3356 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
AnnaBridge | 145:64910690c574 | 3357 | * @{ |
AnnaBridge | 145:64910690c574 | 3358 | */ |
AnnaBridge | 145:64910690c574 | 3359 | |
AnnaBridge | 145:64910690c574 | 3360 | #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3361 | |
AnnaBridge | 145:64910690c574 | 3362 | #if defined(TIM3) |
AnnaBridge | 145:64910690c574 | 3363 | #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3364 | #endif /* TIM3 */ |
AnnaBridge | 145:64910690c574 | 3365 | |
AnnaBridge | 145:64910690c574 | 3366 | #if defined(TIM4) |
AnnaBridge | 145:64910690c574 | 3367 | #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3368 | #endif /* TIM4 */ |
AnnaBridge | 145:64910690c574 | 3369 | |
AnnaBridge | 145:64910690c574 | 3370 | #if defined(TIM5) |
AnnaBridge | 145:64910690c574 | 3371 | #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3372 | #endif /* TIM5 */ |
AnnaBridge | 145:64910690c574 | 3373 | |
AnnaBridge | 145:64910690c574 | 3374 | #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3375 | |
AnnaBridge | 145:64910690c574 | 3376 | #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3377 | |
AnnaBridge | 145:64910690c574 | 3378 | #if defined(LCD) |
AnnaBridge | 145:64910690c574 | 3379 | #define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3380 | #endif /* LCD */ |
AnnaBridge | 145:64910690c574 | 3381 | |
AnnaBridge | 145:64910690c574 | 3382 | #if defined(RCC_APB1SMENR1_RTCAPBSMEN) |
AnnaBridge | 145:64910690c574 | 3383 | #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3384 | #endif /* RCC_APB1SMENR1_RTCAPBSMEN */ |
AnnaBridge | 145:64910690c574 | 3385 | |
AnnaBridge | 145:64910690c574 | 3386 | #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3387 | |
AnnaBridge | 145:64910690c574 | 3388 | #if defined(SPI2) |
AnnaBridge | 145:64910690c574 | 3389 | #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3390 | #endif /* SPI2 */ |
AnnaBridge | 145:64910690c574 | 3391 | |
AnnaBridge | 145:64910690c574 | 3392 | #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3393 | |
AnnaBridge | 145:64910690c574 | 3394 | #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3395 | |
AnnaBridge | 145:64910690c574 | 3396 | #if defined(USART3) |
AnnaBridge | 145:64910690c574 | 3397 | #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3398 | #endif /* USART3 */ |
AnnaBridge | 145:64910690c574 | 3399 | |
AnnaBridge | 145:64910690c574 | 3400 | #if defined(UART4) |
AnnaBridge | 145:64910690c574 | 3401 | #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3402 | #endif /* UART4 */ |
AnnaBridge | 145:64910690c574 | 3403 | |
AnnaBridge | 145:64910690c574 | 3404 | #if defined(UART5) |
AnnaBridge | 145:64910690c574 | 3405 | #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3406 | #endif /* UART5 */ |
AnnaBridge | 145:64910690c574 | 3407 | |
AnnaBridge | 145:64910690c574 | 3408 | #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3409 | |
AnnaBridge | 145:64910690c574 | 3410 | #if defined(I2C2) |
AnnaBridge | 145:64910690c574 | 3411 | #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3412 | #endif /* I2C2 */ |
AnnaBridge | 145:64910690c574 | 3413 | |
AnnaBridge | 145:64910690c574 | 3414 | #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3415 | |
AnnaBridge | 145:64910690c574 | 3416 | #if defined(I2C4) |
AnnaBridge | 145:64910690c574 | 3417 | #define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3418 | #endif /* I2C4 */ |
AnnaBridge | 145:64910690c574 | 3419 | |
AnnaBridge | 145:64910690c574 | 3420 | #if defined(CRS) |
AnnaBridge | 145:64910690c574 | 3421 | #define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3422 | #endif /* CRS */ |
AnnaBridge | 145:64910690c574 | 3423 | |
AnnaBridge | 145:64910690c574 | 3424 | #define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3425 | |
AnnaBridge | 145:64910690c574 | 3426 | #if defined(CAN2) |
AnnaBridge | 145:64910690c574 | 3427 | #define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3428 | #endif /* CAN2 */ |
AnnaBridge | 145:64910690c574 | 3429 | |
AnnaBridge | 145:64910690c574 | 3430 | #if defined(USB) |
AnnaBridge | 145:64910690c574 | 3431 | #define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3432 | #endif /* USB */ |
AnnaBridge | 145:64910690c574 | 3433 | |
AnnaBridge | 145:64910690c574 | 3434 | #define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3435 | |
AnnaBridge | 145:64910690c574 | 3436 | #define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3437 | |
AnnaBridge | 145:64910690c574 | 3438 | #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3439 | |
AnnaBridge | 145:64910690c574 | 3440 | #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3441 | |
AnnaBridge | 145:64910690c574 | 3442 | #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3443 | |
AnnaBridge | 145:64910690c574 | 3444 | #if defined(SWPMI1) |
AnnaBridge | 145:64910690c574 | 3445 | #define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3446 | #endif /* SWPMI1 */ |
AnnaBridge | 145:64910690c574 | 3447 | |
AnnaBridge | 145:64910690c574 | 3448 | #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3449 | |
AnnaBridge | 145:64910690c574 | 3450 | |
AnnaBridge | 145:64910690c574 | 3451 | #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3452 | |
AnnaBridge | 145:64910690c574 | 3453 | #if defined(TIM3) |
AnnaBridge | 145:64910690c574 | 3454 | #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3455 | #endif /* TIM3 */ |
AnnaBridge | 145:64910690c574 | 3456 | |
AnnaBridge | 145:64910690c574 | 3457 | #if defined(TIM4) |
AnnaBridge | 145:64910690c574 | 3458 | #define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3459 | #endif /* TIM4 */ |
AnnaBridge | 145:64910690c574 | 3460 | |
AnnaBridge | 145:64910690c574 | 3461 | #if defined(TIM5) |
AnnaBridge | 145:64910690c574 | 3462 | #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3463 | #endif /* TIM5 */ |
AnnaBridge | 145:64910690c574 | 3464 | |
AnnaBridge | 145:64910690c574 | 3465 | #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3466 | |
AnnaBridge | 145:64910690c574 | 3467 | #define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3468 | |
AnnaBridge | 145:64910690c574 | 3469 | #if defined(LCD) |
AnnaBridge | 145:64910690c574 | 3470 | #define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3471 | #endif /* LCD */ |
AnnaBridge | 145:64910690c574 | 3472 | |
AnnaBridge | 145:64910690c574 | 3473 | #if defined(RCC_APB1SMENR1_RTCAPBSMEN) |
AnnaBridge | 145:64910690c574 | 3474 | #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3475 | #endif /* RCC_APB1SMENR1_RTCAPBSMEN */ |
AnnaBridge | 145:64910690c574 | 3476 | |
AnnaBridge | 145:64910690c574 | 3477 | #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3478 | |
AnnaBridge | 145:64910690c574 | 3479 | #if defined(SPI2) |
AnnaBridge | 145:64910690c574 | 3480 | #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3481 | #endif /* SPI2 */ |
AnnaBridge | 145:64910690c574 | 3482 | |
AnnaBridge | 145:64910690c574 | 3483 | #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3484 | |
AnnaBridge | 145:64910690c574 | 3485 | #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3486 | |
AnnaBridge | 145:64910690c574 | 3487 | #if defined(USART3) |
AnnaBridge | 145:64910690c574 | 3488 | #define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3489 | #endif /* USART3 */ |
AnnaBridge | 145:64910690c574 | 3490 | |
AnnaBridge | 145:64910690c574 | 3491 | #if defined(UART4) |
AnnaBridge | 145:64910690c574 | 3492 | #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3493 | #endif /* UART4 */ |
AnnaBridge | 145:64910690c574 | 3494 | |
AnnaBridge | 145:64910690c574 | 3495 | #if defined(UART5) |
AnnaBridge | 145:64910690c574 | 3496 | #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3497 | #endif /* UART5 */ |
AnnaBridge | 145:64910690c574 | 3498 | |
AnnaBridge | 145:64910690c574 | 3499 | #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3500 | |
AnnaBridge | 145:64910690c574 | 3501 | #if defined(I2C2) |
AnnaBridge | 145:64910690c574 | 3502 | #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3503 | #endif /* I2C2 */ |
AnnaBridge | 145:64910690c574 | 3504 | |
AnnaBridge | 145:64910690c574 | 3505 | #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3506 | |
AnnaBridge | 145:64910690c574 | 3507 | #if defined(I2C4) |
AnnaBridge | 145:64910690c574 | 3508 | #define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3509 | #endif /* I2C4 */ |
AnnaBridge | 145:64910690c574 | 3510 | |
AnnaBridge | 145:64910690c574 | 3511 | #if defined(CRS) |
AnnaBridge | 145:64910690c574 | 3512 | #define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3513 | #endif /* CRS */ |
AnnaBridge | 145:64910690c574 | 3514 | |
AnnaBridge | 145:64910690c574 | 3515 | #define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3516 | |
AnnaBridge | 145:64910690c574 | 3517 | #if defined(CAN2) |
AnnaBridge | 145:64910690c574 | 3518 | #define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3519 | #endif /* CAN2 */ |
AnnaBridge | 145:64910690c574 | 3520 | |
AnnaBridge | 145:64910690c574 | 3521 | #if defined(USB) |
AnnaBridge | 145:64910690c574 | 3522 | #define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3523 | #endif /* USB */ |
AnnaBridge | 145:64910690c574 | 3524 | |
AnnaBridge | 145:64910690c574 | 3525 | #define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3526 | |
AnnaBridge | 145:64910690c574 | 3527 | #define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3528 | |
AnnaBridge | 145:64910690c574 | 3529 | #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3530 | |
AnnaBridge | 145:64910690c574 | 3531 | #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3532 | |
AnnaBridge | 145:64910690c574 | 3533 | #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3534 | |
AnnaBridge | 145:64910690c574 | 3535 | #if defined(SWPMI1) |
AnnaBridge | 145:64910690c574 | 3536 | #define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3537 | #endif /* SWPMI1 */ |
AnnaBridge | 145:64910690c574 | 3538 | |
AnnaBridge | 145:64910690c574 | 3539 | #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3540 | |
AnnaBridge | 145:64910690c574 | 3541 | /** |
AnnaBridge | 145:64910690c574 | 3542 | * @} |
AnnaBridge | 145:64910690c574 | 3543 | */ |
AnnaBridge | 145:64910690c574 | 3544 | |
AnnaBridge | 145:64910690c574 | 3545 | /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status |
AnnaBridge | 145:64910690c574 | 3546 | * @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not. |
AnnaBridge | 145:64910690c574 | 3547 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
AnnaBridge | 145:64910690c574 | 3548 | * power consumption. |
AnnaBridge | 145:64910690c574 | 3549 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
AnnaBridge | 145:64910690c574 | 3550 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
AnnaBridge | 145:64910690c574 | 3551 | * @{ |
AnnaBridge | 145:64910690c574 | 3552 | */ |
AnnaBridge | 145:64910690c574 | 3553 | |
AnnaBridge | 145:64910690c574 | 3554 | #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3555 | |
AnnaBridge | 161:aa5281ff4a02 | 3556 | #if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN) |
AnnaBridge | 145:64910690c574 | 3557 | #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) != RESET) |
AnnaBridge | 161:aa5281ff4a02 | 3558 | #endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */ |
AnnaBridge | 145:64910690c574 | 3559 | |
AnnaBridge | 145:64910690c574 | 3560 | #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3561 | |
AnnaBridge | 145:64910690c574 | 3562 | #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3563 | |
AnnaBridge | 145:64910690c574 | 3564 | #if defined(TIM8) |
AnnaBridge | 145:64910690c574 | 3565 | #define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3566 | #endif /* TIM8 */ |
AnnaBridge | 145:64910690c574 | 3567 | |
AnnaBridge | 145:64910690c574 | 3568 | #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3569 | |
AnnaBridge | 145:64910690c574 | 3570 | #define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3571 | |
AnnaBridge | 145:64910690c574 | 3572 | #define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3573 | |
AnnaBridge | 145:64910690c574 | 3574 | #if defined(TIM17) |
AnnaBridge | 145:64910690c574 | 3575 | #define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3576 | #endif /* TIM17 */ |
AnnaBridge | 145:64910690c574 | 3577 | |
AnnaBridge | 145:64910690c574 | 3578 | #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3579 | |
AnnaBridge | 145:64910690c574 | 3580 | #if defined(SAI2) |
AnnaBridge | 145:64910690c574 | 3581 | #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3582 | #endif /* SAI2 */ |
AnnaBridge | 145:64910690c574 | 3583 | |
AnnaBridge | 145:64910690c574 | 3584 | #if defined(DFSDM1_Filter0) |
AnnaBridge | 145:64910690c574 | 3585 | #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) != RESET) |
AnnaBridge | 145:64910690c574 | 3586 | #endif /* DFSDM1_Filter0 */ |
AnnaBridge | 145:64910690c574 | 3587 | |
AnnaBridge | 161:aa5281ff4a02 | 3588 | #if defined(LTDC) |
AnnaBridge | 161:aa5281ff4a02 | 3589 | #define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) != RESET) |
AnnaBridge | 161:aa5281ff4a02 | 3590 | #endif /* LTDC */ |
AnnaBridge | 161:aa5281ff4a02 | 3591 | |
AnnaBridge | 161:aa5281ff4a02 | 3592 | #if defined(DSI) |
AnnaBridge | 161:aa5281ff4a02 | 3593 | #define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) != RESET) |
AnnaBridge | 161:aa5281ff4a02 | 3594 | #endif /* DSI */ |
AnnaBridge | 161:aa5281ff4a02 | 3595 | |
AnnaBridge | 145:64910690c574 | 3596 | |
AnnaBridge | 145:64910690c574 | 3597 | #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3598 | |
AnnaBridge | 161:aa5281ff4a02 | 3599 | #if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN) |
AnnaBridge | 145:64910690c574 | 3600 | #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) == RESET) |
AnnaBridge | 161:aa5281ff4a02 | 3601 | #endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */ |
AnnaBridge | 145:64910690c574 | 3602 | |
AnnaBridge | 145:64910690c574 | 3603 | #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3604 | |
AnnaBridge | 145:64910690c574 | 3605 | #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3606 | |
AnnaBridge | 145:64910690c574 | 3607 | #if defined(TIM8) |
AnnaBridge | 145:64910690c574 | 3608 | #define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3609 | #endif /* TIM8 */ |
AnnaBridge | 145:64910690c574 | 3610 | |
AnnaBridge | 145:64910690c574 | 3611 | #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3612 | |
AnnaBridge | 145:64910690c574 | 3613 | #define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3614 | |
AnnaBridge | 145:64910690c574 | 3615 | #define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3616 | |
AnnaBridge | 145:64910690c574 | 3617 | #if defined(TIM17) |
AnnaBridge | 145:64910690c574 | 3618 | #define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3619 | #endif /* TIM17 */ |
AnnaBridge | 145:64910690c574 | 3620 | |
AnnaBridge | 145:64910690c574 | 3621 | #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3622 | |
AnnaBridge | 145:64910690c574 | 3623 | #if defined(SAI2) |
AnnaBridge | 145:64910690c574 | 3624 | #define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3625 | #endif /* SAI2 */ |
AnnaBridge | 145:64910690c574 | 3626 | |
AnnaBridge | 145:64910690c574 | 3627 | #if defined(DFSDM1_Filter0) |
AnnaBridge | 145:64910690c574 | 3628 | #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) == RESET) |
AnnaBridge | 145:64910690c574 | 3629 | #endif /* DFSDM1_Filter0 */ |
AnnaBridge | 145:64910690c574 | 3630 | |
AnnaBridge | 161:aa5281ff4a02 | 3631 | #if defined(LTDC) |
AnnaBridge | 161:aa5281ff4a02 | 3632 | #define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) == RESET) |
AnnaBridge | 161:aa5281ff4a02 | 3633 | #endif /* LTDC */ |
AnnaBridge | 161:aa5281ff4a02 | 3634 | |
AnnaBridge | 161:aa5281ff4a02 | 3635 | #if defined(DSI) |
AnnaBridge | 161:aa5281ff4a02 | 3636 | #define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) == RESET) |
AnnaBridge | 161:aa5281ff4a02 | 3637 | #endif /* DSI */ |
AnnaBridge | 161:aa5281ff4a02 | 3638 | |
AnnaBridge | 145:64910690c574 | 3639 | /** |
AnnaBridge | 145:64910690c574 | 3640 | * @} |
AnnaBridge | 145:64910690c574 | 3641 | */ |
AnnaBridge | 145:64910690c574 | 3642 | |
AnnaBridge | 145:64910690c574 | 3643 | /** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset |
AnnaBridge | 161:aa5281ff4a02 | 3644 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 3645 | */ |
AnnaBridge | 145:64910690c574 | 3646 | |
AnnaBridge | 145:64910690c574 | 3647 | /** @brief Macros to force or release the Backup domain reset. |
AnnaBridge | 145:64910690c574 | 3648 | * @note This function resets the RTC peripheral (including the backup registers) |
AnnaBridge | 145:64910690c574 | 3649 | * and the RTC clock source selection in RCC_CSR register. |
AnnaBridge | 145:64910690c574 | 3650 | * @note The BKPSRAM is not affected by this reset. |
AnnaBridge | 145:64910690c574 | 3651 | * @retval None |
AnnaBridge | 145:64910690c574 | 3652 | */ |
AnnaBridge | 145:64910690c574 | 3653 | #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST) |
AnnaBridge | 145:64910690c574 | 3654 | |
AnnaBridge | 145:64910690c574 | 3655 | #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST) |
AnnaBridge | 145:64910690c574 | 3656 | |
AnnaBridge | 145:64910690c574 | 3657 | /** |
AnnaBridge | 145:64910690c574 | 3658 | * @} |
AnnaBridge | 145:64910690c574 | 3659 | */ |
AnnaBridge | 145:64910690c574 | 3660 | |
AnnaBridge | 145:64910690c574 | 3661 | /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration |
AnnaBridge | 161:aa5281ff4a02 | 3662 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 3663 | */ |
AnnaBridge | 145:64910690c574 | 3664 | |
AnnaBridge | 145:64910690c574 | 3665 | /** @brief Macros to enable or disable the RTC clock. |
AnnaBridge | 145:64910690c574 | 3666 | * @note As the RTC is in the Backup domain and write access is denied to |
AnnaBridge | 145:64910690c574 | 3667 | * this domain after reset, you have to enable write access using |
AnnaBridge | 145:64910690c574 | 3668 | * HAL_PWR_EnableBkUpAccess() function before to configure the RTC |
AnnaBridge | 145:64910690c574 | 3669 | * (to be done once after reset). |
AnnaBridge | 145:64910690c574 | 3670 | * @note These macros must be used after the RTC clock source was selected. |
AnnaBridge | 145:64910690c574 | 3671 | * @retval None |
AnnaBridge | 145:64910690c574 | 3672 | */ |
AnnaBridge | 145:64910690c574 | 3673 | #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) |
AnnaBridge | 145:64910690c574 | 3674 | |
AnnaBridge | 145:64910690c574 | 3675 | #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) |
AnnaBridge | 145:64910690c574 | 3676 | |
AnnaBridge | 145:64910690c574 | 3677 | /** |
AnnaBridge | 145:64910690c574 | 3678 | * @} |
AnnaBridge | 145:64910690c574 | 3679 | */ |
AnnaBridge | 145:64910690c574 | 3680 | |
AnnaBridge | 145:64910690c574 | 3681 | /** @brief Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI). |
AnnaBridge | 145:64910690c574 | 3682 | * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. |
AnnaBridge | 145:64910690c574 | 3683 | * It is used (enabled by hardware) as system clock source after startup |
AnnaBridge | 145:64910690c574 | 3684 | * from Reset, wakeup from STOP and STANDBY mode, or in case of failure |
AnnaBridge | 145:64910690c574 | 3685 | * of the HSE used directly or indirectly as system clock (if the Clock |
AnnaBridge | 145:64910690c574 | 3686 | * Security System CSS is enabled). |
AnnaBridge | 145:64910690c574 | 3687 | * @note HSI can not be stopped if it is used as system clock source. In this case, |
AnnaBridge | 145:64910690c574 | 3688 | * you have to select another source of the system clock then stop the HSI. |
AnnaBridge | 145:64910690c574 | 3689 | * @note After enabling the HSI, the application software should wait on HSIRDY |
AnnaBridge | 145:64910690c574 | 3690 | * flag to be set indicating that HSI clock is stable and can be used as |
AnnaBridge | 145:64910690c574 | 3691 | * system clock source. |
AnnaBridge | 145:64910690c574 | 3692 | * This parameter can be: ENABLE or DISABLE. |
AnnaBridge | 145:64910690c574 | 3693 | * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator |
AnnaBridge | 145:64910690c574 | 3694 | * clock cycles. |
AnnaBridge | 145:64910690c574 | 3695 | * @retval None |
AnnaBridge | 145:64910690c574 | 3696 | */ |
AnnaBridge | 145:64910690c574 | 3697 | #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) |
AnnaBridge | 145:64910690c574 | 3698 | |
AnnaBridge | 145:64910690c574 | 3699 | #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) |
AnnaBridge | 145:64910690c574 | 3700 | |
AnnaBridge | 145:64910690c574 | 3701 | /** @brief Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value. |
AnnaBridge | 145:64910690c574 | 3702 | * @note The calibration is used to compensate for the variations in voltage |
AnnaBridge | 145:64910690c574 | 3703 | * and temperature that influence the frequency of the internal HSI RC. |
AnnaBridge | 161:aa5281ff4a02 | 3704 | * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value |
AnnaBridge | 145:64910690c574 | 3705 | * (default is RCC_HSICALIBRATION_DEFAULT). |
AnnaBridge | 145:64910690c574 | 3706 | * This parameter must be a number between 0 and 0x1F (STM32L43x/STM32L44x/STM32L47x/STM32L48x) or 0x7F (for other devices). |
AnnaBridge | 145:64910690c574 | 3707 | * @retval None |
AnnaBridge | 145:64910690c574 | 3708 | */ |
AnnaBridge | 145:64910690c574 | 3709 | #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \ |
AnnaBridge | 161:aa5281ff4a02 | 3710 | MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos) |
AnnaBridge | 145:64910690c574 | 3711 | |
AnnaBridge | 145:64910690c574 | 3712 | /** |
AnnaBridge | 145:64910690c574 | 3713 | * @brief Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI) |
AnnaBridge | 145:64910690c574 | 3714 | * in parallel to the Internal Multi Speed oscillator (MSI) used at system wakeup. |
AnnaBridge | 145:64910690c574 | 3715 | * @note The enable of this function has not effect on the HSION bit. |
AnnaBridge | 145:64910690c574 | 3716 | * This parameter can be: ENABLE or DISABLE. |
AnnaBridge | 145:64910690c574 | 3717 | * @retval None |
AnnaBridge | 145:64910690c574 | 3718 | */ |
AnnaBridge | 145:64910690c574 | 3719 | #define __HAL_RCC_HSIAUTOMATIC_START_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIASFS) |
AnnaBridge | 145:64910690c574 | 3720 | |
AnnaBridge | 145:64910690c574 | 3721 | #define __HAL_RCC_HSIAUTOMATIC_START_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS) |
AnnaBridge | 145:64910690c574 | 3722 | |
AnnaBridge | 145:64910690c574 | 3723 | /** |
AnnaBridge | 145:64910690c574 | 3724 | * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) |
AnnaBridge | 145:64910690c574 | 3725 | * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs. |
AnnaBridge | 145:64910690c574 | 3726 | * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication |
AnnaBridge | 145:64910690c574 | 3727 | * speed because of the HSI startup time. |
AnnaBridge | 145:64910690c574 | 3728 | * @note The enable of this function has not effect on the HSION bit. |
AnnaBridge | 145:64910690c574 | 3729 | * This parameter can be: ENABLE or DISABLE. |
AnnaBridge | 145:64910690c574 | 3730 | * @retval None |
AnnaBridge | 145:64910690c574 | 3731 | */ |
AnnaBridge | 145:64910690c574 | 3732 | #define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON) |
AnnaBridge | 145:64910690c574 | 3733 | |
AnnaBridge | 145:64910690c574 | 3734 | #define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON) |
AnnaBridge | 145:64910690c574 | 3735 | |
AnnaBridge | 145:64910690c574 | 3736 | /** |
AnnaBridge | 145:64910690c574 | 3737 | * @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI). |
AnnaBridge | 145:64910690c574 | 3738 | * @note The MSI is stopped by hardware when entering STOP and STANDBY modes. |
AnnaBridge | 145:64910690c574 | 3739 | * It is used (enabled by hardware) as system clock source after |
AnnaBridge | 145:64910690c574 | 3740 | * startup from Reset, wakeup from STOP and STANDBY mode, or in case |
AnnaBridge | 145:64910690c574 | 3741 | * of failure of the HSE used directly or indirectly as system clock |
AnnaBridge | 145:64910690c574 | 3742 | * (if the Clock Security System CSS is enabled). |
AnnaBridge | 145:64910690c574 | 3743 | * @note MSI can not be stopped if it is used as system clock source. |
AnnaBridge | 145:64910690c574 | 3744 | * In this case, you have to select another source of the system |
AnnaBridge | 145:64910690c574 | 3745 | * clock then stop the MSI. |
AnnaBridge | 145:64910690c574 | 3746 | * @note After enabling the MSI, the application software should wait on |
AnnaBridge | 145:64910690c574 | 3747 | * MSIRDY flag to be set indicating that MSI clock is stable and can |
AnnaBridge | 145:64910690c574 | 3748 | * be used as system clock source. |
AnnaBridge | 145:64910690c574 | 3749 | * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator |
AnnaBridge | 145:64910690c574 | 3750 | * clock cycles. |
AnnaBridge | 145:64910690c574 | 3751 | * @retval None |
AnnaBridge | 145:64910690c574 | 3752 | */ |
AnnaBridge | 145:64910690c574 | 3753 | #define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSION) |
AnnaBridge | 145:64910690c574 | 3754 | |
AnnaBridge | 145:64910690c574 | 3755 | #define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION) |
AnnaBridge | 145:64910690c574 | 3756 | |
AnnaBridge | 145:64910690c574 | 3757 | /** @brief Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value. |
AnnaBridge | 145:64910690c574 | 3758 | * @note The calibration is used to compensate for the variations in voltage |
AnnaBridge | 145:64910690c574 | 3759 | * and temperature that influence the frequency of the internal MSI RC. |
AnnaBridge | 145:64910690c574 | 3760 | * Refer to the Application Note AN3300 for more details on how to |
AnnaBridge | 145:64910690c574 | 3761 | * calibrate the MSI. |
AnnaBridge | 161:aa5281ff4a02 | 3762 | * @param __MSICALIBRATIONVALUE__ specifies the calibration trimming value |
AnnaBridge | 145:64910690c574 | 3763 | * (default is RCC_MSICALIBRATION_DEFAULT). |
AnnaBridge | 145:64910690c574 | 3764 | * This parameter must be a number between 0 and 255. |
AnnaBridge | 145:64910690c574 | 3765 | * @retval None |
AnnaBridge | 145:64910690c574 | 3766 | */ |
AnnaBridge | 145:64910690c574 | 3767 | #define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) \ |
AnnaBridge | 161:aa5281ff4a02 | 3768 | MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (__MSICALIBRATIONVALUE__) << RCC_ICSCR_MSITRIM_Pos) |
AnnaBridge | 145:64910690c574 | 3769 | |
AnnaBridge | 145:64910690c574 | 3770 | /** |
AnnaBridge | 145:64910690c574 | 3771 | * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode |
AnnaBridge | 145:64910690c574 | 3772 | * @note After restart from Reset , the MSI clock is around 4 MHz. |
AnnaBridge | 145:64910690c574 | 3773 | * After stop the startup clock can be MSI (at any of its possible |
AnnaBridge | 145:64910690c574 | 3774 | * frequencies, the one that was used before entering stop mode) or HSI. |
AnnaBridge | 145:64910690c574 | 3775 | * After Standby its frequency can be selected between 4 possible values |
AnnaBridge | 145:64910690c574 | 3776 | * (1, 2, 4 or 8 MHz). |
AnnaBridge | 145:64910690c574 | 3777 | * @note MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready |
AnnaBridge | 145:64910690c574 | 3778 | * (MSIRDY=1). |
AnnaBridge | 145:64910690c574 | 3779 | * @note The MSI clock range after reset can be modified on the fly. |
AnnaBridge | 161:aa5281ff4a02 | 3780 | * @param __MSIRANGEVALUE__ specifies the MSI clock range. |
AnnaBridge | 145:64910690c574 | 3781 | * This parameter must be one of the following values: |
AnnaBridge | 145:64910690c574 | 3782 | * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz |
AnnaBridge | 145:64910690c574 | 3783 | * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz |
AnnaBridge | 145:64910690c574 | 3784 | * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz |
AnnaBridge | 145:64910690c574 | 3785 | * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz |
AnnaBridge | 145:64910690c574 | 3786 | * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz |
AnnaBridge | 145:64910690c574 | 3787 | * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz |
AnnaBridge | 145:64910690c574 | 3788 | * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset) |
AnnaBridge | 145:64910690c574 | 3789 | * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz |
AnnaBridge | 145:64910690c574 | 3790 | * @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz |
AnnaBridge | 145:64910690c574 | 3791 | * @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz |
AnnaBridge | 145:64910690c574 | 3792 | * @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz |
AnnaBridge | 145:64910690c574 | 3793 | * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz |
AnnaBridge | 145:64910690c574 | 3794 | * @retval None |
AnnaBridge | 145:64910690c574 | 3795 | */ |
AnnaBridge | 145:64910690c574 | 3796 | #define __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__) \ |
AnnaBridge | 145:64910690c574 | 3797 | do { \ |
AnnaBridge | 145:64910690c574 | 3798 | SET_BIT(RCC->CR, RCC_CR_MSIRGSEL); \ |
AnnaBridge | 145:64910690c574 | 3799 | MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, (__MSIRANGEVALUE__)); \ |
AnnaBridge | 145:64910690c574 | 3800 | } while(0) |
AnnaBridge | 145:64910690c574 | 3801 | |
AnnaBridge | 145:64910690c574 | 3802 | /** |
AnnaBridge | 145:64910690c574 | 3803 | * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode |
AnnaBridge | 145:64910690c574 | 3804 | * After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz). |
AnnaBridge | 161:aa5281ff4a02 | 3805 | * @param __MSIRANGEVALUE__ specifies the MSI clock range. |
AnnaBridge | 145:64910690c574 | 3806 | * This parameter must be one of the following values: |
AnnaBridge | 145:64910690c574 | 3807 | * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz |
AnnaBridge | 145:64910690c574 | 3808 | * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz |
AnnaBridge | 145:64910690c574 | 3809 | * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset) |
AnnaBridge | 145:64910690c574 | 3810 | * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz |
AnnaBridge | 145:64910690c574 | 3811 | * @retval None |
AnnaBridge | 145:64910690c574 | 3812 | */ |
AnnaBridge | 145:64910690c574 | 3813 | #define __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) \ |
AnnaBridge | 145:64910690c574 | 3814 | MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, (__MSIRANGEVALUE__) << 4U) |
AnnaBridge | 145:64910690c574 | 3815 | |
AnnaBridge | 145:64910690c574 | 3816 | /** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode |
AnnaBridge | 145:64910690c574 | 3817 | * @retval MSI clock range. |
AnnaBridge | 145:64910690c574 | 3818 | * This parameter must be one of the following values: |
AnnaBridge | 145:64910690c574 | 3819 | * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz |
AnnaBridge | 145:64910690c574 | 3820 | * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz |
AnnaBridge | 145:64910690c574 | 3821 | * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz |
AnnaBridge | 145:64910690c574 | 3822 | * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz |
AnnaBridge | 145:64910690c574 | 3823 | * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz |
AnnaBridge | 145:64910690c574 | 3824 | * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz |
AnnaBridge | 145:64910690c574 | 3825 | * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset) |
AnnaBridge | 145:64910690c574 | 3826 | * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz |
AnnaBridge | 145:64910690c574 | 3827 | * @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz |
AnnaBridge | 145:64910690c574 | 3828 | * @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz |
AnnaBridge | 145:64910690c574 | 3829 | * @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz |
AnnaBridge | 145:64910690c574 | 3830 | * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz |
AnnaBridge | 145:64910690c574 | 3831 | */ |
AnnaBridge | 145:64910690c574 | 3832 | #define __HAL_RCC_GET_MSI_RANGE() \ |
AnnaBridge | 145:64910690c574 | 3833 | ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != RESET) ? \ |
AnnaBridge | 161:aa5281ff4a02 | 3834 | READ_BIT(RCC->CR, RCC_CR_MSIRANGE) : \ |
AnnaBridge | 161:aa5281ff4a02 | 3835 | READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4U) |
AnnaBridge | 145:64910690c574 | 3836 | |
AnnaBridge | 145:64910690c574 | 3837 | /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). |
AnnaBridge | 145:64910690c574 | 3838 | * @note After enabling the LSI, the application software should wait on |
AnnaBridge | 145:64910690c574 | 3839 | * LSIRDY flag to be set indicating that LSI clock is stable and can |
AnnaBridge | 145:64910690c574 | 3840 | * be used to clock the IWDG and/or the RTC. |
AnnaBridge | 145:64910690c574 | 3841 | * @note LSI can not be disabled if the IWDG is running. |
AnnaBridge | 145:64910690c574 | 3842 | * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator |
AnnaBridge | 145:64910690c574 | 3843 | * clock cycles. |
AnnaBridge | 145:64910690c574 | 3844 | * @retval None |
AnnaBridge | 145:64910690c574 | 3845 | */ |
AnnaBridge | 145:64910690c574 | 3846 | #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION) |
AnnaBridge | 145:64910690c574 | 3847 | |
AnnaBridge | 145:64910690c574 | 3848 | #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION) |
AnnaBridge | 145:64910690c574 | 3849 | |
AnnaBridge | 145:64910690c574 | 3850 | /** |
AnnaBridge | 145:64910690c574 | 3851 | * @brief Macro to configure the External High Speed oscillator (HSE). |
AnnaBridge | 145:64910690c574 | 3852 | * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not |
AnnaBridge | 145:64910690c574 | 3853 | * supported by this macro. User should request a transition to HSE Off |
AnnaBridge | 145:64910690c574 | 3854 | * first and then HSE On or HSE Bypass. |
AnnaBridge | 145:64910690c574 | 3855 | * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application |
AnnaBridge | 145:64910690c574 | 3856 | * software should wait on HSERDY flag to be set indicating that HSE clock |
AnnaBridge | 145:64910690c574 | 3857 | * is stable and can be used to clock the PLL and/or system clock. |
AnnaBridge | 145:64910690c574 | 3858 | * @note HSE state can not be changed if it is used directly or through the |
AnnaBridge | 145:64910690c574 | 3859 | * PLL as system clock. In this case, you have to select another source |
AnnaBridge | 145:64910690c574 | 3860 | * of the system clock then change the HSE state (ex. disable it). |
AnnaBridge | 145:64910690c574 | 3861 | * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. |
AnnaBridge | 145:64910690c574 | 3862 | * @note This function reset the CSSON bit, so if the clock security system(CSS) |
AnnaBridge | 145:64910690c574 | 3863 | * was previously enabled you have to enable it again after calling this |
AnnaBridge | 145:64910690c574 | 3864 | * function. |
AnnaBridge | 161:aa5281ff4a02 | 3865 | * @param __STATE__ specifies the new state of the HSE. |
AnnaBridge | 145:64910690c574 | 3866 | * This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 3867 | * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after |
AnnaBridge | 145:64910690c574 | 3868 | * 6 HSE oscillator clock cycles. |
AnnaBridge | 145:64910690c574 | 3869 | * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator. |
AnnaBridge | 145:64910690c574 | 3870 | * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock. |
AnnaBridge | 145:64910690c574 | 3871 | * @retval None |
AnnaBridge | 145:64910690c574 | 3872 | */ |
AnnaBridge | 145:64910690c574 | 3873 | #define __HAL_RCC_HSE_CONFIG(__STATE__) \ |
AnnaBridge | 145:64910690c574 | 3874 | do { \ |
AnnaBridge | 145:64910690c574 | 3875 | if((__STATE__) == RCC_HSE_ON) \ |
AnnaBridge | 145:64910690c574 | 3876 | { \ |
AnnaBridge | 145:64910690c574 | 3877 | SET_BIT(RCC->CR, RCC_CR_HSEON); \ |
AnnaBridge | 145:64910690c574 | 3878 | } \ |
AnnaBridge | 145:64910690c574 | 3879 | else if((__STATE__) == RCC_HSE_BYPASS) \ |
AnnaBridge | 145:64910690c574 | 3880 | { \ |
AnnaBridge | 145:64910690c574 | 3881 | SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ |
AnnaBridge | 145:64910690c574 | 3882 | SET_BIT(RCC->CR, RCC_CR_HSEON); \ |
AnnaBridge | 145:64910690c574 | 3883 | } \ |
AnnaBridge | 145:64910690c574 | 3884 | else \ |
AnnaBridge | 145:64910690c574 | 3885 | { \ |
AnnaBridge | 145:64910690c574 | 3886 | CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ |
AnnaBridge | 145:64910690c574 | 3887 | CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ |
AnnaBridge | 145:64910690c574 | 3888 | } \ |
AnnaBridge | 145:64910690c574 | 3889 | } while(0) |
AnnaBridge | 145:64910690c574 | 3890 | |
AnnaBridge | 145:64910690c574 | 3891 | /** |
AnnaBridge | 145:64910690c574 | 3892 | * @brief Macro to configure the External Low Speed oscillator (LSE). |
AnnaBridge | 145:64910690c574 | 3893 | * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not |
AnnaBridge | 161:aa5281ff4a02 | 3894 | * supported by this macro. User should request a transition to LSE Off |
AnnaBridge | 161:aa5281ff4a02 | 3895 | * first and then LSE On or LSE Bypass. |
AnnaBridge | 145:64910690c574 | 3896 | * @note As the LSE is in the Backup domain and write access is denied to |
AnnaBridge | 145:64910690c574 | 3897 | * this domain after reset, you have to enable write access using |
AnnaBridge | 145:64910690c574 | 3898 | * HAL_PWR_EnableBkUpAccess() function before to configure the LSE |
AnnaBridge | 145:64910690c574 | 3899 | * (to be done once after reset). |
AnnaBridge | 145:64910690c574 | 3900 | * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application |
AnnaBridge | 145:64910690c574 | 3901 | * software should wait on LSERDY flag to be set indicating that LSE clock |
AnnaBridge | 145:64910690c574 | 3902 | * is stable and can be used to clock the RTC. |
AnnaBridge | 161:aa5281ff4a02 | 3903 | * @param __STATE__ specifies the new state of the LSE. |
AnnaBridge | 145:64910690c574 | 3904 | * This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 3905 | * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after |
AnnaBridge | 145:64910690c574 | 3906 | * 6 LSE oscillator clock cycles. |
AnnaBridge | 145:64910690c574 | 3907 | * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator. |
AnnaBridge | 145:64910690c574 | 3908 | * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. |
AnnaBridge | 145:64910690c574 | 3909 | * @retval None |
AnnaBridge | 145:64910690c574 | 3910 | */ |
AnnaBridge | 145:64910690c574 | 3911 | #define __HAL_RCC_LSE_CONFIG(__STATE__) \ |
AnnaBridge | 145:64910690c574 | 3912 | do { \ |
AnnaBridge | 145:64910690c574 | 3913 | if((__STATE__) == RCC_LSE_ON) \ |
AnnaBridge | 145:64910690c574 | 3914 | { \ |
AnnaBridge | 145:64910690c574 | 3915 | SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ |
AnnaBridge | 145:64910690c574 | 3916 | } \ |
AnnaBridge | 145:64910690c574 | 3917 | else if((__STATE__) == RCC_LSE_BYPASS) \ |
AnnaBridge | 145:64910690c574 | 3918 | { \ |
AnnaBridge | 145:64910690c574 | 3919 | SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ |
AnnaBridge | 145:64910690c574 | 3920 | SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ |
AnnaBridge | 145:64910690c574 | 3921 | } \ |
AnnaBridge | 145:64910690c574 | 3922 | else \ |
AnnaBridge | 145:64910690c574 | 3923 | { \ |
AnnaBridge | 145:64910690c574 | 3924 | CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ |
AnnaBridge | 145:64910690c574 | 3925 | CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ |
AnnaBridge | 145:64910690c574 | 3926 | } \ |
AnnaBridge | 145:64910690c574 | 3927 | } while(0) |
AnnaBridge | 145:64910690c574 | 3928 | |
AnnaBridge | 145:64910690c574 | 3929 | #if defined(RCC_HSI48_SUPPORT) |
AnnaBridge | 145:64910690c574 | 3930 | |
AnnaBridge | 145:64910690c574 | 3931 | /** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48). |
AnnaBridge | 145:64910690c574 | 3932 | * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. |
AnnaBridge | 145:64910690c574 | 3933 | * @note After enabling the HSI48, the application software should wait on HSI48RDY |
AnnaBridge | 145:64910690c574 | 3934 | * flag to be set indicating that HSI48 clock is stable. |
AnnaBridge | 145:64910690c574 | 3935 | * This parameter can be: ENABLE or DISABLE. |
AnnaBridge | 145:64910690c574 | 3936 | * @retval None |
AnnaBridge | 145:64910690c574 | 3937 | */ |
AnnaBridge | 145:64910690c574 | 3938 | #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) |
AnnaBridge | 145:64910690c574 | 3939 | |
AnnaBridge | 145:64910690c574 | 3940 | #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) |
AnnaBridge | 145:64910690c574 | 3941 | |
AnnaBridge | 145:64910690c574 | 3942 | #endif /* RCC_HSI48_SUPPORT */ |
AnnaBridge | 145:64910690c574 | 3943 | |
AnnaBridge | 145:64910690c574 | 3944 | /** @brief Macros to configure the RTC clock (RTCCLK). |
AnnaBridge | 145:64910690c574 | 3945 | * @note As the RTC clock configuration bits are in the Backup domain and write |
AnnaBridge | 145:64910690c574 | 3946 | * access is denied to this domain after reset, you have to enable write |
AnnaBridge | 145:64910690c574 | 3947 | * access using the Power Backup Access macro before to configure |
AnnaBridge | 145:64910690c574 | 3948 | * the RTC clock source (to be done once after reset). |
AnnaBridge | 145:64910690c574 | 3949 | * @note Once the RTC clock is configured it cannot be changed unless the |
AnnaBridge | 145:64910690c574 | 3950 | * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by |
AnnaBridge | 145:64910690c574 | 3951 | * a Power On Reset (POR). |
AnnaBridge | 145:64910690c574 | 3952 | * |
AnnaBridge | 161:aa5281ff4a02 | 3953 | * @param __RTC_CLKSOURCE__ specifies the RTC clock source. |
AnnaBridge | 145:64910690c574 | 3954 | * This parameter can be one of the following values: |
AnnaBridge | 161:aa5281ff4a02 | 3955 | * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. |
AnnaBridge | 145:64910690c574 | 3956 | * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. |
AnnaBridge | 145:64910690c574 | 3957 | * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. |
AnnaBridge | 145:64910690c574 | 3958 | * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected |
AnnaBridge | 145:64910690c574 | 3959 | * |
AnnaBridge | 145:64910690c574 | 3960 | * @note If the LSE or LSI is used as RTC clock source, the RTC continues to |
AnnaBridge | 145:64910690c574 | 3961 | * work in STOP and STANDBY modes, and can be used as wakeup source. |
AnnaBridge | 145:64910690c574 | 3962 | * However, when the HSE clock is used as RTC clock source, the RTC |
AnnaBridge | 145:64910690c574 | 3963 | * cannot be used in STOP and STANDBY modes. |
AnnaBridge | 145:64910690c574 | 3964 | * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as |
AnnaBridge | 145:64910690c574 | 3965 | * RTC clock source). |
AnnaBridge | 145:64910690c574 | 3966 | * @retval None |
AnnaBridge | 145:64910690c574 | 3967 | */ |
AnnaBridge | 145:64910690c574 | 3968 | #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \ |
AnnaBridge | 145:64910690c574 | 3969 | MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) |
AnnaBridge | 145:64910690c574 | 3970 | |
AnnaBridge | 145:64910690c574 | 3971 | |
AnnaBridge | 145:64910690c574 | 3972 | /** @brief Macro to get the RTC clock source. |
AnnaBridge | 145:64910690c574 | 3973 | * @retval The returned value can be one of the following: |
AnnaBridge | 161:aa5281ff4a02 | 3974 | * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. |
AnnaBridge | 145:64910690c574 | 3975 | * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. |
AnnaBridge | 145:64910690c574 | 3976 | * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. |
AnnaBridge | 145:64910690c574 | 3977 | * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected |
AnnaBridge | 145:64910690c574 | 3978 | */ |
AnnaBridge | 161:aa5281ff4a02 | 3979 | #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) |
AnnaBridge | 145:64910690c574 | 3980 | |
AnnaBridge | 145:64910690c574 | 3981 | /** @brief Macros to enable or disable the main PLL. |
AnnaBridge | 145:64910690c574 | 3982 | * @note After enabling the main PLL, the application software should wait on |
AnnaBridge | 145:64910690c574 | 3983 | * PLLRDY flag to be set indicating that PLL clock is stable and can |
AnnaBridge | 145:64910690c574 | 3984 | * be used as system clock source. |
AnnaBridge | 145:64910690c574 | 3985 | * @note The main PLL can not be disabled if it is used as system clock source |
AnnaBridge | 145:64910690c574 | 3986 | * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. |
AnnaBridge | 145:64910690c574 | 3987 | * @retval None |
AnnaBridge | 145:64910690c574 | 3988 | */ |
AnnaBridge | 145:64910690c574 | 3989 | #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON) |
AnnaBridge | 145:64910690c574 | 3990 | |
AnnaBridge | 145:64910690c574 | 3991 | #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON) |
AnnaBridge | 145:64910690c574 | 3992 | |
AnnaBridge | 145:64910690c574 | 3993 | /** @brief Macro to configure the PLL clock source. |
AnnaBridge | 145:64910690c574 | 3994 | * @note This function must be used only when the main PLL is disabled. |
AnnaBridge | 161:aa5281ff4a02 | 3995 | * @param __PLLSOURCE__ specifies the PLL entry clock source. |
AnnaBridge | 145:64910690c574 | 3996 | * This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 3997 | * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry |
AnnaBridge | 145:64910690c574 | 3998 | * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry |
AnnaBridge | 145:64910690c574 | 3999 | * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry |
AnnaBridge | 145:64910690c574 | 4000 | * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry |
AnnaBridge | 145:64910690c574 | 4001 | * @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2). |
AnnaBridge | 145:64910690c574 | 4002 | * @retval None |
AnnaBridge | 161:aa5281ff4a02 | 4003 | * |
AnnaBridge | 145:64910690c574 | 4004 | */ |
AnnaBridge | 145:64910690c574 | 4005 | #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \ |
AnnaBridge | 145:64910690c574 | 4006 | MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) |
AnnaBridge | 145:64910690c574 | 4007 | |
AnnaBridge | 145:64910690c574 | 4008 | /** @brief Macro to configure the PLL source division factor M. |
AnnaBridge | 145:64910690c574 | 4009 | * @note This function must be used only when the main PLL is disabled. |
AnnaBridge | 161:aa5281ff4a02 | 4010 | * @param __PLLM__ specifies the division factor for PLL VCO input clock |
AnnaBridge | 161:aa5281ff4a02 | 4011 | * This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices. |
AnnaBridge | 161:aa5281ff4a02 | 4012 | * This parameter must be a number between Min_Data = 1 and Max_Data = 8 on other devices. |
AnnaBridge | 145:64910690c574 | 4013 | * @note You have to set the PLLM parameter correctly to ensure that the VCO input |
AnnaBridge | 145:64910690c574 | 4014 | * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency |
AnnaBridge | 145:64910690c574 | 4015 | * of 16 MHz to limit PLL jitter. |
AnnaBridge | 145:64910690c574 | 4016 | * @retval None |
AnnaBridge | 161:aa5281ff4a02 | 4017 | * |
AnnaBridge | 145:64910690c574 | 4018 | */ |
AnnaBridge | 145:64910690c574 | 4019 | #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \ |
AnnaBridge | 145:64910690c574 | 4020 | MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << 4U) |
AnnaBridge | 145:64910690c574 | 4021 | |
AnnaBridge | 145:64910690c574 | 4022 | /** |
AnnaBridge | 145:64910690c574 | 4023 | * @brief Macro to configure the main PLL clock source, multiplication and division factors. |
AnnaBridge | 145:64910690c574 | 4024 | * @note This function must be used only when the main PLL is disabled. |
AnnaBridge | 145:64910690c574 | 4025 | * |
AnnaBridge | 161:aa5281ff4a02 | 4026 | * @param __PLLSOURCE__ specifies the PLL entry clock source. |
AnnaBridge | 145:64910690c574 | 4027 | * This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 4028 | * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry |
AnnaBridge | 145:64910690c574 | 4029 | * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry |
AnnaBridge | 145:64910690c574 | 4030 | * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry |
AnnaBridge | 145:64910690c574 | 4031 | * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry |
AnnaBridge | 145:64910690c574 | 4032 | * @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2). |
AnnaBridge | 145:64910690c574 | 4033 | * |
AnnaBridge | 161:aa5281ff4a02 | 4034 | * @param __PLLM__ specifies the division factor for PLL VCO input clock. |
AnnaBridge | 161:aa5281ff4a02 | 4035 | * This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices. |
AnnaBridge | 161:aa5281ff4a02 | 4036 | * This parameter must be a number between Min_Data = 1 and Max_Data = 8 on other devices. |
AnnaBridge | 145:64910690c574 | 4037 | * @note You have to set the PLLM parameter correctly to ensure that the VCO input |
AnnaBridge | 145:64910690c574 | 4038 | * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency |
AnnaBridge | 145:64910690c574 | 4039 | * of 16 MHz to limit PLL jitter. |
AnnaBridge | 145:64910690c574 | 4040 | * |
AnnaBridge | 161:aa5281ff4a02 | 4041 | * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock. |
AnnaBridge | 145:64910690c574 | 4042 | * This parameter must be a number between 8 and 86. |
AnnaBridge | 145:64910690c574 | 4043 | * @note You have to set the PLLN parameter correctly to ensure that the VCO |
AnnaBridge | 145:64910690c574 | 4044 | * output frequency is between 64 and 344 MHz. |
AnnaBridge | 145:64910690c574 | 4045 | * |
AnnaBridge | 161:aa5281ff4a02 | 4046 | * @param __PLLP__ specifies the division factor for SAI clock. |
AnnaBridge | 145:64910690c574 | 4047 | * This parameter must be a number in the range (7 or 17) for STM32L47x/STM32L48x |
AnnaBridge | 145:64910690c574 | 4048 | * else (2 to 31). |
AnnaBridge | 145:64910690c574 | 4049 | * |
AnnaBridge | 161:aa5281ff4a02 | 4050 | * @param __PLLQ__ specifies the division factor for OTG FS, SDMMC1 and RNG clocks. |
AnnaBridge | 145:64910690c574 | 4051 | * This parameter must be in the range (2, 4, 6 or 8). |
AnnaBridge | 145:64910690c574 | 4052 | * @note If the USB OTG FS is used in your application, you have to set the |
AnnaBridge | 145:64910690c574 | 4053 | * PLLQ parameter correctly to have 48 MHz clock for the USB. However, |
AnnaBridge | 145:64910690c574 | 4054 | * the SDMMC1 and RNG need a frequency lower than or equal to 48 MHz to work |
AnnaBridge | 145:64910690c574 | 4055 | * correctly. |
AnnaBridge | 161:aa5281ff4a02 | 4056 | * @param __PLLR__ specifies the division factor for the main system clock. |
AnnaBridge | 145:64910690c574 | 4057 | * @note You have to set the PLLR parameter correctly to not exceed 80MHZ. |
AnnaBridge | 145:64910690c574 | 4058 | * This parameter must be in the range (2, 4, 6 or 8). |
AnnaBridge | 145:64910690c574 | 4059 | * @retval None |
AnnaBridge | 145:64910690c574 | 4060 | */ |
AnnaBridge | 145:64910690c574 | 4061 | #if defined(RCC_PLLP_DIV_2_31_SUPPORT) |
AnnaBridge | 145:64910690c574 | 4062 | |
AnnaBridge | 145:64910690c574 | 4063 | #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \ |
AnnaBridge | 145:64910690c574 | 4064 | (RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) | (uint32_t)((__PLLN__) << 8U) | \ |
AnnaBridge | 161:aa5281ff4a02 | 4065 | (__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U) | \ |
AnnaBridge | 161:aa5281ff4a02 | 4066 | ((uint32_t)(__PLLP__) << 27U)) |
AnnaBridge | 145:64910690c574 | 4067 | #else |
AnnaBridge | 161:aa5281ff4a02 | 4068 | |
AnnaBridge | 145:64910690c574 | 4069 | #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \ |
AnnaBridge | 161:aa5281ff4a02 | 4070 | (RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) | (uint32_t)((__PLLN__) << 8U) | \ |
AnnaBridge | 161:aa5281ff4a02 | 4071 | (uint32_t)(((__PLLP__) >> 4U ) << 17U) | \ |
AnnaBridge | 161:aa5281ff4a02 | 4072 | (__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U)) |
AnnaBridge | 145:64910690c574 | 4073 | |
AnnaBridge | 145:64910690c574 | 4074 | #endif /* RCC_PLLP_DIV_2_31_SUPPORT */ |
AnnaBridge | 145:64910690c574 | 4075 | |
AnnaBridge | 145:64910690c574 | 4076 | /** @brief Macro to get the oscillator used as PLL clock source. |
AnnaBridge | 145:64910690c574 | 4077 | * @retval The oscillator used as PLL clock source. The returned value can be one |
AnnaBridge | 145:64910690c574 | 4078 | * of the following: |
AnnaBridge | 145:64910690c574 | 4079 | * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source. |
AnnaBridge | 145:64910690c574 | 4080 | * - RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source. |
AnnaBridge | 145:64910690c574 | 4081 | * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. |
AnnaBridge | 145:64910690c574 | 4082 | * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. |
AnnaBridge | 145:64910690c574 | 4083 | */ |
AnnaBridge | 161:aa5281ff4a02 | 4084 | #define __HAL_RCC_GET_PLL_OSCSOURCE() (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)) |
AnnaBridge | 145:64910690c574 | 4085 | |
AnnaBridge | 145:64910690c574 | 4086 | /** |
AnnaBridge | 145:64910690c574 | 4087 | * @brief Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK) |
AnnaBridge | 161:aa5281ff4a02 | 4088 | * @note Enabling/disabling clock outputs RCC_PLL_SAI3CLK and RCC_PLL_48M1CLK can be done at anytime |
AnnaBridge | 161:aa5281ff4a02 | 4089 | * without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot |
AnnaBridge | 145:64910690c574 | 4090 | * be stopped if used as System Clock. |
AnnaBridge | 161:aa5281ff4a02 | 4091 | * @param __PLLCLOCKOUT__ specifies the PLL clock to be output. |
AnnaBridge | 145:64910690c574 | 4092 | * This parameter can be one or a combination of the following values: |
AnnaBridge | 145:64910690c574 | 4093 | * @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve |
AnnaBridge | 145:64910690c574 | 4094 | * high-quality audio performance on SAI interface in case. |
AnnaBridge | 145:64910690c574 | 4095 | * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB OTG FS (48 MHz), |
AnnaBridge | 145:64910690c574 | 4096 | * the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz). |
AnnaBridge | 145:64910690c574 | 4097 | * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 80MHz) |
AnnaBridge | 145:64910690c574 | 4098 | * @retval None |
AnnaBridge | 145:64910690c574 | 4099 | */ |
AnnaBridge | 145:64910690c574 | 4100 | #define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) |
AnnaBridge | 145:64910690c574 | 4101 | |
AnnaBridge | 145:64910690c574 | 4102 | #define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) |
AnnaBridge | 145:64910690c574 | 4103 | |
AnnaBridge | 145:64910690c574 | 4104 | /** |
AnnaBridge | 145:64910690c574 | 4105 | * @brief Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK) |
AnnaBridge | 161:aa5281ff4a02 | 4106 | * @param __PLLCLOCKOUT__ specifies the output PLL clock to be checked. |
AnnaBridge | 145:64910690c574 | 4107 | * This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 4108 | * @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve |
AnnaBridge | 145:64910690c574 | 4109 | * high-quality audio performance on SAI interface in case. |
AnnaBridge | 145:64910690c574 | 4110 | * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB OTG FS (48 MHz), |
AnnaBridge | 145:64910690c574 | 4111 | * the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz). |
AnnaBridge | 145:64910690c574 | 4112 | * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 80MHz) |
AnnaBridge | 145:64910690c574 | 4113 | * @retval SET / RESET |
AnnaBridge | 145:64910690c574 | 4114 | */ |
AnnaBridge | 145:64910690c574 | 4115 | #define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) |
AnnaBridge | 145:64910690c574 | 4116 | |
AnnaBridge | 145:64910690c574 | 4117 | /** |
AnnaBridge | 145:64910690c574 | 4118 | * @brief Macro to configure the system clock source. |
AnnaBridge | 161:aa5281ff4a02 | 4119 | * @param __SYSCLKSOURCE__ specifies the system clock source. |
AnnaBridge | 145:64910690c574 | 4120 | * This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 4121 | * - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source. |
AnnaBridge | 145:64910690c574 | 4122 | * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. |
AnnaBridge | 145:64910690c574 | 4123 | * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. |
AnnaBridge | 145:64910690c574 | 4124 | * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source. |
AnnaBridge | 145:64910690c574 | 4125 | * @retval None |
AnnaBridge | 145:64910690c574 | 4126 | */ |
AnnaBridge | 145:64910690c574 | 4127 | #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ |
AnnaBridge | 145:64910690c574 | 4128 | MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) |
AnnaBridge | 145:64910690c574 | 4129 | |
AnnaBridge | 145:64910690c574 | 4130 | /** @brief Macro to get the clock source used as system clock. |
AnnaBridge | 145:64910690c574 | 4131 | * @retval The clock source used as system clock. The returned value can be one |
AnnaBridge | 145:64910690c574 | 4132 | * of the following: |
AnnaBridge | 145:64910690c574 | 4133 | * - RCC_SYSCLKSOURCE_STATUS_MSI: MSI used as system clock. |
AnnaBridge | 145:64910690c574 | 4134 | * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock. |
AnnaBridge | 145:64910690c574 | 4135 | * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock. |
AnnaBridge | 145:64910690c574 | 4136 | * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock. |
AnnaBridge | 145:64910690c574 | 4137 | */ |
AnnaBridge | 161:aa5281ff4a02 | 4138 | #define __HAL_RCC_GET_SYSCLK_SOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_SWS)) |
AnnaBridge | 145:64910690c574 | 4139 | |
AnnaBridge | 145:64910690c574 | 4140 | /** |
AnnaBridge | 145:64910690c574 | 4141 | * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. |
AnnaBridge | 145:64910690c574 | 4142 | * @note As the LSE is in the Backup domain and write access is denied to |
AnnaBridge | 145:64910690c574 | 4143 | * this domain after reset, you have to enable write access using |
AnnaBridge | 145:64910690c574 | 4144 | * HAL_PWR_EnableBkUpAccess() function before to configure the LSE |
AnnaBridge | 145:64910690c574 | 4145 | * (to be done once after reset). |
AnnaBridge | 161:aa5281ff4a02 | 4146 | * @param __LSEDRIVE__ specifies the new state of the LSE drive capability. |
AnnaBridge | 145:64910690c574 | 4147 | * This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 4148 | * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. |
AnnaBridge | 145:64910690c574 | 4149 | * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. |
AnnaBridge | 145:64910690c574 | 4150 | * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. |
AnnaBridge | 145:64910690c574 | 4151 | * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. |
AnnaBridge | 145:64910690c574 | 4152 | * @retval None |
AnnaBridge | 145:64910690c574 | 4153 | */ |
AnnaBridge | 145:64910690c574 | 4154 | #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ |
AnnaBridge | 161:aa5281ff4a02 | 4155 | MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (__LSEDRIVE__)) |
AnnaBridge | 145:64910690c574 | 4156 | |
AnnaBridge | 145:64910690c574 | 4157 | /** |
AnnaBridge | 145:64910690c574 | 4158 | * @brief Macro to configure the wake up from stop clock. |
AnnaBridge | 161:aa5281ff4a02 | 4159 | * @param __STOPWUCLK__ specifies the clock source used after wake up from stop. |
AnnaBridge | 145:64910690c574 | 4160 | * This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 4161 | * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source |
AnnaBridge | 145:64910690c574 | 4162 | * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source |
AnnaBridge | 145:64910690c574 | 4163 | * @retval None |
AnnaBridge | 145:64910690c574 | 4164 | */ |
AnnaBridge | 145:64910690c574 | 4165 | #define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) \ |
AnnaBridge | 145:64910690c574 | 4166 | MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__STOPWUCLK__)) |
AnnaBridge | 145:64910690c574 | 4167 | |
AnnaBridge | 145:64910690c574 | 4168 | |
AnnaBridge | 145:64910690c574 | 4169 | /** @brief Macro to configure the MCO clock. |
AnnaBridge | 145:64910690c574 | 4170 | * @param __MCOCLKSOURCE__ specifies the MCO clock source. |
AnnaBridge | 145:64910690c574 | 4171 | * This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 4172 | * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled |
AnnaBridge | 145:64910690c574 | 4173 | * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source |
AnnaBridge | 145:64910690c574 | 4174 | * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source |
AnnaBridge | 145:64910690c574 | 4175 | * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source |
AnnaBridge | 145:64910690c574 | 4176 | * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee |
AnnaBridge | 145:64910690c574 | 4177 | * @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source |
AnnaBridge | 145:64910690c574 | 4178 | * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source |
AnnaBridge | 145:64910690c574 | 4179 | * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source |
AnnaBridge | 145:64910690c574 | 4180 | @if STM32L443xx |
AnnaBridge | 145:64910690c574 | 4181 | * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 |
AnnaBridge | 145:64910690c574 | 4182 | @endif |
AnnaBridge | 145:64910690c574 | 4183 | @if STM32L4A6xx |
AnnaBridge | 145:64910690c574 | 4184 | * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 |
AnnaBridge | 145:64910690c574 | 4185 | @endif |
AnnaBridge | 145:64910690c574 | 4186 | * @param __MCODIV__ specifies the MCO clock prescaler. |
AnnaBridge | 145:64910690c574 | 4187 | * This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 4188 | * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 |
AnnaBridge | 145:64910690c574 | 4189 | * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 |
AnnaBridge | 145:64910690c574 | 4190 | * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 |
AnnaBridge | 145:64910690c574 | 4191 | * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 |
AnnaBridge | 145:64910690c574 | 4192 | * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 |
AnnaBridge | 145:64910690c574 | 4193 | */ |
AnnaBridge | 145:64910690c574 | 4194 | #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ |
AnnaBridge | 145:64910690c574 | 4195 | MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) |
AnnaBridge | 145:64910690c574 | 4196 | |
AnnaBridge | 145:64910690c574 | 4197 | /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management |
AnnaBridge | 145:64910690c574 | 4198 | * @brief macros to manage the specified RCC Flags and interrupts. |
AnnaBridge | 145:64910690c574 | 4199 | * @{ |
AnnaBridge | 145:64910690c574 | 4200 | */ |
AnnaBridge | 145:64910690c574 | 4201 | |
AnnaBridge | 161:aa5281ff4a02 | 4202 | /** @brief Enable RCC interrupt(s). |
AnnaBridge | 161:aa5281ff4a02 | 4203 | * @param __INTERRUPT__ specifies the RCC interrupt source(s) to be enabled. |
AnnaBridge | 145:64910690c574 | 4204 | * This parameter can be any combination of the following values: |
AnnaBridge | 145:64910690c574 | 4205 | * @arg @ref RCC_IT_LSIRDY LSI ready interrupt |
AnnaBridge | 145:64910690c574 | 4206 | * @arg @ref RCC_IT_LSERDY LSE ready interrupt |
AnnaBridge | 145:64910690c574 | 4207 | * @arg @ref RCC_IT_MSIRDY HSI ready interrupt |
AnnaBridge | 145:64910690c574 | 4208 | * @arg @ref RCC_IT_HSIRDY HSI ready interrupt |
AnnaBridge | 145:64910690c574 | 4209 | * @arg @ref RCC_IT_HSERDY HSE ready interrupt |
AnnaBridge | 145:64910690c574 | 4210 | * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt |
AnnaBridge | 145:64910690c574 | 4211 | * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt |
AnnaBridge | 145:64910690c574 | 4212 | * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2 |
AnnaBridge | 145:64910690c574 | 4213 | * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt |
AnnaBridge | 145:64910690c574 | 4214 | @if STM32L443xx |
AnnaBridge | 145:64910690c574 | 4215 | * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 |
AnnaBridge | 145:64910690c574 | 4216 | @endif |
AnnaBridge | 145:64910690c574 | 4217 | @if STM32L4A6xx |
AnnaBridge | 145:64910690c574 | 4218 | * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 |
AnnaBridge | 145:64910690c574 | 4219 | @endif |
AnnaBridge | 145:64910690c574 | 4220 | * @retval None |
AnnaBridge | 145:64910690c574 | 4221 | */ |
AnnaBridge | 145:64910690c574 | 4222 | #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) |
AnnaBridge | 145:64910690c574 | 4223 | |
AnnaBridge | 161:aa5281ff4a02 | 4224 | /** @brief Disable RCC interrupt(s). |
AnnaBridge | 161:aa5281ff4a02 | 4225 | * @param __INTERRUPT__ specifies the RCC interrupt source(s) to be disabled. |
AnnaBridge | 145:64910690c574 | 4226 | * This parameter can be any combination of the following values: |
AnnaBridge | 145:64910690c574 | 4227 | * @arg @ref RCC_IT_LSIRDY LSI ready interrupt |
AnnaBridge | 145:64910690c574 | 4228 | * @arg @ref RCC_IT_LSERDY LSE ready interrupt |
AnnaBridge | 145:64910690c574 | 4229 | * @arg @ref RCC_IT_MSIRDY HSI ready interrupt |
AnnaBridge | 145:64910690c574 | 4230 | * @arg @ref RCC_IT_HSIRDY HSI ready interrupt |
AnnaBridge | 145:64910690c574 | 4231 | * @arg @ref RCC_IT_HSERDY HSE ready interrupt |
AnnaBridge | 145:64910690c574 | 4232 | * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt |
AnnaBridge | 145:64910690c574 | 4233 | * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt |
AnnaBridge | 145:64910690c574 | 4234 | * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2 |
AnnaBridge | 145:64910690c574 | 4235 | * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt |
AnnaBridge | 145:64910690c574 | 4236 | @if STM32L443xx |
AnnaBridge | 145:64910690c574 | 4237 | * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 |
AnnaBridge | 145:64910690c574 | 4238 | @endif |
AnnaBridge | 145:64910690c574 | 4239 | @if STM32L4A6xx |
AnnaBridge | 145:64910690c574 | 4240 | * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 |
AnnaBridge | 145:64910690c574 | 4241 | @endif |
AnnaBridge | 145:64910690c574 | 4242 | * @retval None |
AnnaBridge | 145:64910690c574 | 4243 | */ |
AnnaBridge | 145:64910690c574 | 4244 | #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) |
AnnaBridge | 145:64910690c574 | 4245 | |
AnnaBridge | 161:aa5281ff4a02 | 4246 | /** @brief Clear the RCC's interrupt pending bits. |
AnnaBridge | 161:aa5281ff4a02 | 4247 | * @param __INTERRUPT__ specifies the interrupt pending bit to clear. |
AnnaBridge | 145:64910690c574 | 4248 | * This parameter can be any combination of the following values: |
AnnaBridge | 145:64910690c574 | 4249 | * @arg @ref RCC_IT_LSIRDY LSI ready interrupt |
AnnaBridge | 145:64910690c574 | 4250 | * @arg @ref RCC_IT_LSERDY LSE ready interrupt |
AnnaBridge | 145:64910690c574 | 4251 | * @arg @ref RCC_IT_MSIRDY MSI ready interrupt |
AnnaBridge | 145:64910690c574 | 4252 | * @arg @ref RCC_IT_HSIRDY HSI ready interrupt |
AnnaBridge | 145:64910690c574 | 4253 | * @arg @ref RCC_IT_HSERDY HSE ready interrupt |
AnnaBridge | 145:64910690c574 | 4254 | * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt |
AnnaBridge | 145:64910690c574 | 4255 | * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt |
AnnaBridge | 145:64910690c574 | 4256 | * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2 |
AnnaBridge | 145:64910690c574 | 4257 | * @arg @ref RCC_IT_CSS HSE Clock security system interrupt |
AnnaBridge | 145:64910690c574 | 4258 | * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt |
AnnaBridge | 145:64910690c574 | 4259 | @if STM32L443xx |
AnnaBridge | 145:64910690c574 | 4260 | * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 |
AnnaBridge | 145:64910690c574 | 4261 | @endif |
AnnaBridge | 145:64910690c574 | 4262 | @if STM32L4A6xx |
AnnaBridge | 145:64910690c574 | 4263 | * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 |
AnnaBridge | 145:64910690c574 | 4264 | @endif |
AnnaBridge | 145:64910690c574 | 4265 | * @retval None |
AnnaBridge | 145:64910690c574 | 4266 | */ |
AnnaBridge | 161:aa5281ff4a02 | 4267 | #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) WRITE_REG(RCC->CICR, (__INTERRUPT__)) |
AnnaBridge | 145:64910690c574 | 4268 | |
AnnaBridge | 145:64910690c574 | 4269 | /** @brief Check whether the RCC interrupt has occurred or not. |
AnnaBridge | 161:aa5281ff4a02 | 4270 | * @param __INTERRUPT__ specifies the RCC interrupt source to check. |
AnnaBridge | 145:64910690c574 | 4271 | * This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 4272 | * @arg @ref RCC_IT_LSIRDY LSI ready interrupt |
AnnaBridge | 145:64910690c574 | 4273 | * @arg @ref RCC_IT_LSERDY LSE ready interrupt |
AnnaBridge | 145:64910690c574 | 4274 | * @arg @ref RCC_IT_MSIRDY MSI ready interrupt |
AnnaBridge | 145:64910690c574 | 4275 | * @arg @ref RCC_IT_HSIRDY HSI ready interrupt |
AnnaBridge | 145:64910690c574 | 4276 | * @arg @ref RCC_IT_HSERDY HSE ready interrupt |
AnnaBridge | 145:64910690c574 | 4277 | * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt |
AnnaBridge | 145:64910690c574 | 4278 | * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt |
AnnaBridge | 145:64910690c574 | 4279 | * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2 |
AnnaBridge | 145:64910690c574 | 4280 | * @arg @ref RCC_IT_CSS HSE Clock security system interrupt |
AnnaBridge | 145:64910690c574 | 4281 | * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt |
AnnaBridge | 145:64910690c574 | 4282 | @if STM32L443xx |
AnnaBridge | 145:64910690c574 | 4283 | * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 |
AnnaBridge | 145:64910690c574 | 4284 | @endif |
AnnaBridge | 145:64910690c574 | 4285 | @if STM32L4A6xx |
AnnaBridge | 145:64910690c574 | 4286 | * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 |
AnnaBridge | 145:64910690c574 | 4287 | @endif |
AnnaBridge | 145:64910690c574 | 4288 | * @retval The new state of __INTERRUPT__ (TRUE or FALSE). |
AnnaBridge | 145:64910690c574 | 4289 | */ |
AnnaBridge | 161:aa5281ff4a02 | 4290 | #define __HAL_RCC_GET_IT(__INTERRUPT__) (READ_BIT(RCC->CIFR, (__INTERRUPT__)) == (__INTERRUPT__)) |
AnnaBridge | 145:64910690c574 | 4291 | |
AnnaBridge | 145:64910690c574 | 4292 | /** @brief Set RMVF bit to clear the reset flags. |
AnnaBridge | 145:64910690c574 | 4293 | * The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST, |
AnnaBridge | 145:64910690c574 | 4294 | * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. |
AnnaBridge | 145:64910690c574 | 4295 | * @retval None |
AnnaBridge | 145:64910690c574 | 4296 | */ |
AnnaBridge | 161:aa5281ff4a02 | 4297 | #define __HAL_RCC_CLEAR_RESET_FLAGS() SET_BIT(RCC->CSR, RCC_CSR_RMVF) |
AnnaBridge | 145:64910690c574 | 4298 | |
AnnaBridge | 145:64910690c574 | 4299 | /** @brief Check whether the selected RCC flag is set or not. |
AnnaBridge | 161:aa5281ff4a02 | 4300 | * @param __FLAG__ specifies the flag to check. |
AnnaBridge | 145:64910690c574 | 4301 | * This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 4302 | * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready |
AnnaBridge | 145:64910690c574 | 4303 | * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready |
AnnaBridge | 145:64910690c574 | 4304 | * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready |
AnnaBridge | 145:64910690c574 | 4305 | * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready |
AnnaBridge | 145:64910690c574 | 4306 | * @arg @ref RCC_FLAG_PLLSAI1RDY PLLSAI1 clock ready |
AnnaBridge | 145:64910690c574 | 4307 | * @arg @ref RCC_FLAG_PLLSAI2RDY PLLSAI2 clock ready for devices with PLLSAI2 |
AnnaBridge | 145:64910690c574 | 4308 | @if STM32L443xx |
AnnaBridge | 145:64910690c574 | 4309 | * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48 |
AnnaBridge | 145:64910690c574 | 4310 | @endif |
AnnaBridge | 145:64910690c574 | 4311 | @if STM32L4A6xx |
AnnaBridge | 145:64910690c574 | 4312 | * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48 |
AnnaBridge | 145:64910690c574 | 4313 | @endif |
AnnaBridge | 145:64910690c574 | 4314 | * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready |
AnnaBridge | 145:64910690c574 | 4315 | * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection |
AnnaBridge | 145:64910690c574 | 4316 | * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready |
AnnaBridge | 145:64910690c574 | 4317 | * @arg @ref RCC_FLAG_BORRST BOR reset |
AnnaBridge | 145:64910690c574 | 4318 | * @arg @ref RCC_FLAG_OBLRST OBLRST reset |
AnnaBridge | 145:64910690c574 | 4319 | * @arg @ref RCC_FLAG_PINRST Pin reset |
AnnaBridge | 145:64910690c574 | 4320 | * @arg @ref RCC_FLAG_FWRST FIREWALL reset |
AnnaBridge | 145:64910690c574 | 4321 | * @arg @ref RCC_FLAG_RMVF Remove reset Flag |
AnnaBridge | 145:64910690c574 | 4322 | * @arg @ref RCC_FLAG_SFTRST Software reset |
AnnaBridge | 145:64910690c574 | 4323 | * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset |
AnnaBridge | 145:64910690c574 | 4324 | * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset |
AnnaBridge | 145:64910690c574 | 4325 | * @arg @ref RCC_FLAG_LPWRRST Low Power reset |
AnnaBridge | 145:64910690c574 | 4326 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
AnnaBridge | 145:64910690c574 | 4327 | */ |
AnnaBridge | 145:64910690c574 | 4328 | #if defined(RCC_HSI48_SUPPORT) |
AnnaBridge | 161:aa5281ff4a02 | 4329 | #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ |
AnnaBridge | 161:aa5281ff4a02 | 4330 | ((((__FLAG__) >> 5U) == 4U) ? RCC->CRRCR : \ |
AnnaBridge | 161:aa5281ff4a02 | 4331 | ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ |
AnnaBridge | 161:aa5281ff4a02 | 4332 | ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \ |
AnnaBridge | 161:aa5281ff4a02 | 4333 | (1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) ? 1U : 0U) |
AnnaBridge | 145:64910690c574 | 4334 | #else |
AnnaBridge | 145:64910690c574 | 4335 | #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ |
AnnaBridge | 145:64910690c574 | 4336 | ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ |
AnnaBridge | 145:64910690c574 | 4337 | ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR))) & \ |
AnnaBridge | 161:aa5281ff4a02 | 4338 | (1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) ? 1U : 0U) |
AnnaBridge | 145:64910690c574 | 4339 | #endif /* RCC_HSI48_SUPPORT */ |
AnnaBridge | 145:64910690c574 | 4340 | |
AnnaBridge | 145:64910690c574 | 4341 | /** |
AnnaBridge | 145:64910690c574 | 4342 | * @} |
AnnaBridge | 145:64910690c574 | 4343 | */ |
AnnaBridge | 145:64910690c574 | 4344 | |
AnnaBridge | 145:64910690c574 | 4345 | /** |
AnnaBridge | 145:64910690c574 | 4346 | * @} |
AnnaBridge | 145:64910690c574 | 4347 | */ |
AnnaBridge | 161:aa5281ff4a02 | 4348 | |
AnnaBridge | 145:64910690c574 | 4349 | /* Private constants ---------------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 4350 | /** @defgroup RCC_Private_Constants RCC Private Constants |
AnnaBridge | 145:64910690c574 | 4351 | * @{ |
AnnaBridge | 145:64910690c574 | 4352 | */ |
AnnaBridge | 145:64910690c574 | 4353 | /* Defines used for Flags */ |
AnnaBridge | 161:aa5281ff4a02 | 4354 | #define CR_REG_INDEX 1U |
AnnaBridge | 161:aa5281ff4a02 | 4355 | #define BDCR_REG_INDEX 2U |
AnnaBridge | 161:aa5281ff4a02 | 4356 | #define CSR_REG_INDEX 3U |
AnnaBridge | 145:64910690c574 | 4357 | #if defined(RCC_HSI48_SUPPORT) |
AnnaBridge | 161:aa5281ff4a02 | 4358 | #define CRRCR_REG_INDEX 4U |
AnnaBridge | 145:64910690c574 | 4359 | #endif /* RCC_HSI48_SUPPORT */ |
AnnaBridge | 145:64910690c574 | 4360 | |
AnnaBridge | 161:aa5281ff4a02 | 4361 | #define RCC_FLAG_MASK 0x1FU |
AnnaBridge | 145:64910690c574 | 4362 | /** |
AnnaBridge | 145:64910690c574 | 4363 | * @} |
AnnaBridge | 145:64910690c574 | 4364 | */ |
AnnaBridge | 145:64910690c574 | 4365 | |
AnnaBridge | 145:64910690c574 | 4366 | /* Private macros ------------------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 4367 | /** @addtogroup RCC_Private_Macros |
AnnaBridge | 145:64910690c574 | 4368 | * @{ |
AnnaBridge | 145:64910690c574 | 4369 | */ |
AnnaBridge | 145:64910690c574 | 4370 | |
AnnaBridge | 145:64910690c574 | 4371 | #if defined(RCC_HSI48_SUPPORT) |
AnnaBridge | 145:64910690c574 | 4372 | #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ |
AnnaBridge | 145:64910690c574 | 4373 | (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ |
AnnaBridge | 145:64910690c574 | 4374 | (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ |
AnnaBridge | 145:64910690c574 | 4375 | (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \ |
AnnaBridge | 145:64910690c574 | 4376 | (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \ |
AnnaBridge | 145:64910690c574 | 4377 | (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ |
AnnaBridge | 145:64910690c574 | 4378 | (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) |
AnnaBridge | 145:64910690c574 | 4379 | #else |
AnnaBridge | 145:64910690c574 | 4380 | #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ |
AnnaBridge | 145:64910690c574 | 4381 | (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ |
AnnaBridge | 145:64910690c574 | 4382 | (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ |
AnnaBridge | 145:64910690c574 | 4383 | (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \ |
AnnaBridge | 145:64910690c574 | 4384 | (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ |
AnnaBridge | 145:64910690c574 | 4385 | (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) |
AnnaBridge | 145:64910690c574 | 4386 | #endif /* RCC_HSI48_SUPPORT */ |
AnnaBridge | 145:64910690c574 | 4387 | |
AnnaBridge | 145:64910690c574 | 4388 | #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ |
AnnaBridge | 145:64910690c574 | 4389 | ((__HSE__) == RCC_HSE_BYPASS)) |
AnnaBridge | 145:64910690c574 | 4390 | |
AnnaBridge | 145:64910690c574 | 4391 | #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ |
AnnaBridge | 145:64910690c574 | 4392 | ((__LSE__) == RCC_LSE_BYPASS)) |
AnnaBridge | 145:64910690c574 | 4393 | |
AnnaBridge | 145:64910690c574 | 4394 | #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) |
AnnaBridge | 145:64910690c574 | 4395 | |
AnnaBridge | 161:aa5281ff4a02 | 4396 | #define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (RCC_ICSCR_HSITRIM >> RCC_ICSCR_HSITRIM_Pos)) |
AnnaBridge | 145:64910690c574 | 4397 | |
AnnaBridge | 145:64910690c574 | 4398 | #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) |
AnnaBridge | 145:64910690c574 | 4399 | |
AnnaBridge | 145:64910690c574 | 4400 | #define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON)) |
AnnaBridge | 145:64910690c574 | 4401 | |
AnnaBridge | 161:aa5281ff4a02 | 4402 | #define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 255U) |
AnnaBridge | 145:64910690c574 | 4403 | |
AnnaBridge | 145:64910690c574 | 4404 | #if defined(RCC_HSI48_SUPPORT) |
AnnaBridge | 145:64910690c574 | 4405 | #define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON)) |
AnnaBridge | 145:64910690c574 | 4406 | #endif /* RCC_HSI48_SUPPORT */ |
AnnaBridge | 145:64910690c574 | 4407 | |
AnnaBridge | 145:64910690c574 | 4408 | #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \ |
AnnaBridge | 145:64910690c574 | 4409 | ((__PLL__) == RCC_PLL_ON)) |
AnnaBridge | 145:64910690c574 | 4410 | |
AnnaBridge | 145:64910690c574 | 4411 | #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) || \ |
AnnaBridge | 145:64910690c574 | 4412 | ((__SOURCE__) == RCC_PLLSOURCE_MSI) || \ |
AnnaBridge | 145:64910690c574 | 4413 | ((__SOURCE__) == RCC_PLLSOURCE_HSI) || \ |
AnnaBridge | 145:64910690c574 | 4414 | ((__SOURCE__) == RCC_PLLSOURCE_HSE)) |
AnnaBridge | 145:64910690c574 | 4415 | |
AnnaBridge | 161:aa5281ff4a02 | 4416 | #if defined(RCC_PLLM_DIV_1_16_SUPPORT) |
AnnaBridge | 161:aa5281ff4a02 | 4417 | #define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U)) |
AnnaBridge | 161:aa5281ff4a02 | 4418 | #else |
AnnaBridge | 145:64910690c574 | 4419 | #define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U)) |
AnnaBridge | 161:aa5281ff4a02 | 4420 | #endif /*RCC_PLLM_DIV_1_16_SUPPORT */ |
AnnaBridge | 145:64910690c574 | 4421 | |
AnnaBridge | 145:64910690c574 | 4422 | #define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U)) |
AnnaBridge | 145:64910690c574 | 4423 | |
AnnaBridge | 145:64910690c574 | 4424 | #if defined(RCC_PLLP_DIV_2_31_SUPPORT) |
AnnaBridge | 145:64910690c574 | 4425 | #define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U)) |
AnnaBridge | 145:64910690c574 | 4426 | #else |
AnnaBridge | 145:64910690c574 | 4427 | #define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U)) |
AnnaBridge | 145:64910690c574 | 4428 | #endif /*RCC_PLLP_DIV_2_31_SUPPORT */ |
AnnaBridge | 145:64910690c574 | 4429 | |
AnnaBridge | 145:64910690c574 | 4430 | #define IS_RCC_PLLQ_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ |
AnnaBridge | 145:64910690c574 | 4431 | ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) |
AnnaBridge | 145:64910690c574 | 4432 | |
AnnaBridge | 145:64910690c574 | 4433 | #define IS_RCC_PLLR_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ |
AnnaBridge | 145:64910690c574 | 4434 | ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) |
AnnaBridge | 145:64910690c574 | 4435 | |
AnnaBridge | 145:64910690c574 | 4436 | #define IS_RCC_PLLSAI1CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI1_SAI1CLK) == RCC_PLLSAI1_SAI1CLK) || \ |
AnnaBridge | 145:64910690c574 | 4437 | (((__VALUE__) & RCC_PLLSAI1_48M2CLK) == RCC_PLLSAI1_48M2CLK) || \ |
AnnaBridge | 145:64910690c574 | 4438 | (((__VALUE__) & RCC_PLLSAI1_ADC1CLK) == RCC_PLLSAI1_ADC1CLK)) && \ |
AnnaBridge | 145:64910690c574 | 4439 | (((__VALUE__) & ~(RCC_PLLSAI1_SAI1CLK|RCC_PLLSAI1_48M2CLK|RCC_PLLSAI1_ADC1CLK)) == 0U)) |
AnnaBridge | 145:64910690c574 | 4440 | |
AnnaBridge | 145:64910690c574 | 4441 | #if defined(RCC_PLLSAI2_SUPPORT) |
AnnaBridge | 161:aa5281ff4a02 | 4442 | #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) |
AnnaBridge | 145:64910690c574 | 4443 | #define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK) || \ |
AnnaBridge | 145:64910690c574 | 4444 | (((__VALUE__) & RCC_PLLSAI2_ADC2CLK) == RCC_PLLSAI2_ADC2CLK)) && \ |
AnnaBridge | 161:aa5281ff4a02 | 4445 | (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK|RCC_PLLSAI2_ADC2CLK)) == 0U)) |
AnnaBridge | 161:aa5281ff4a02 | 4446 | #elif defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) |
AnnaBridge | 161:aa5281ff4a02 | 4447 | #define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK) || \ |
AnnaBridge | 161:aa5281ff4a02 | 4448 | (((__VALUE__) & RCC_PLLSAI2_DSICLK) == RCC_PLLSAI2_DSICLK) || \ |
AnnaBridge | 161:aa5281ff4a02 | 4449 | (((__VALUE__) & RCC_PLLSAI2_LTDCCLK) == RCC_PLLSAI2_LTDCCLK)) && \ |
AnnaBridge | 161:aa5281ff4a02 | 4450 | (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK|RCC_PLLSAI2_DSICLK|RCC_PLLSAI2_LTDCCLK)) == 0U)) |
AnnaBridge | 161:aa5281ff4a02 | 4451 | #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ |
AnnaBridge | 145:64910690c574 | 4452 | #endif /* RCC_PLLSAI2_SUPPORT */ |
AnnaBridge | 145:64910690c574 | 4453 | |
AnnaBridge | 145:64910690c574 | 4454 | #define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \ |
AnnaBridge | 145:64910690c574 | 4455 | ((__RANGE__) == RCC_MSIRANGE_1) || \ |
AnnaBridge | 145:64910690c574 | 4456 | ((__RANGE__) == RCC_MSIRANGE_2) || \ |
AnnaBridge | 145:64910690c574 | 4457 | ((__RANGE__) == RCC_MSIRANGE_3) || \ |
AnnaBridge | 145:64910690c574 | 4458 | ((__RANGE__) == RCC_MSIRANGE_4) || \ |
AnnaBridge | 145:64910690c574 | 4459 | ((__RANGE__) == RCC_MSIRANGE_5) || \ |
AnnaBridge | 145:64910690c574 | 4460 | ((__RANGE__) == RCC_MSIRANGE_6) || \ |
AnnaBridge | 145:64910690c574 | 4461 | ((__RANGE__) == RCC_MSIRANGE_7) || \ |
AnnaBridge | 145:64910690c574 | 4462 | ((__RANGE__) == RCC_MSIRANGE_8) || \ |
AnnaBridge | 145:64910690c574 | 4463 | ((__RANGE__) == RCC_MSIRANGE_9) || \ |
AnnaBridge | 145:64910690c574 | 4464 | ((__RANGE__) == RCC_MSIRANGE_10) || \ |
AnnaBridge | 145:64910690c574 | 4465 | ((__RANGE__) == RCC_MSIRANGE_11)) |
AnnaBridge | 145:64910690c574 | 4466 | |
AnnaBridge | 145:64910690c574 | 4467 | #define IS_RCC_MSI_STANDBY_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_4) || \ |
AnnaBridge | 145:64910690c574 | 4468 | ((__RANGE__) == RCC_MSIRANGE_5) || \ |
AnnaBridge | 145:64910690c574 | 4469 | ((__RANGE__) == RCC_MSIRANGE_6) || \ |
AnnaBridge | 145:64910690c574 | 4470 | ((__RANGE__) == RCC_MSIRANGE_7)) |
AnnaBridge | 145:64910690c574 | 4471 | |
AnnaBridge | 145:64910690c574 | 4472 | #define IS_RCC_CLOCKTYPE(__CLK__) ((1U <= (__CLK__)) && ((__CLK__) <= 15U)) |
AnnaBridge | 145:64910690c574 | 4473 | |
AnnaBridge | 145:64910690c574 | 4474 | #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \ |
AnnaBridge | 145:64910690c574 | 4475 | ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ |
AnnaBridge | 145:64910690c574 | 4476 | ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ |
AnnaBridge | 145:64910690c574 | 4477 | ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) |
AnnaBridge | 145:64910690c574 | 4478 | |
AnnaBridge | 145:64910690c574 | 4479 | #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ |
AnnaBridge | 145:64910690c574 | 4480 | ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ |
AnnaBridge | 145:64910690c574 | 4481 | ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ |
AnnaBridge | 145:64910690c574 | 4482 | ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ |
AnnaBridge | 145:64910690c574 | 4483 | ((__HCLK__) == RCC_SYSCLK_DIV512)) |
AnnaBridge | 145:64910690c574 | 4484 | |
AnnaBridge | 145:64910690c574 | 4485 | #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ |
AnnaBridge | 145:64910690c574 | 4486 | ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ |
AnnaBridge | 145:64910690c574 | 4487 | ((__PCLK__) == RCC_HCLK_DIV16)) |
AnnaBridge | 145:64910690c574 | 4488 | |
AnnaBridge | 161:aa5281ff4a02 | 4489 | #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE) || \ |
AnnaBridge | 145:64910690c574 | 4490 | ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ |
AnnaBridge | 145:64910690c574 | 4491 | ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ |
AnnaBridge | 145:64910690c574 | 4492 | ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) |
AnnaBridge | 145:64910690c574 | 4493 | |
AnnaBridge | 145:64910690c574 | 4494 | #define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1) |
AnnaBridge | 145:64910690c574 | 4495 | |
AnnaBridge | 145:64910690c574 | 4496 | #if defined(RCC_HSI48_SUPPORT) |
AnnaBridge | 145:64910690c574 | 4497 | #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ |
AnnaBridge | 145:64910690c574 | 4498 | ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ |
AnnaBridge | 145:64910690c574 | 4499 | ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \ |
AnnaBridge | 145:64910690c574 | 4500 | ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ |
AnnaBridge | 145:64910690c574 | 4501 | ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ |
AnnaBridge | 145:64910690c574 | 4502 | ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ |
AnnaBridge | 145:64910690c574 | 4503 | ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \ |
AnnaBridge | 145:64910690c574 | 4504 | ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \ |
AnnaBridge | 145:64910690c574 | 4505 | ((__SOURCE__) == RCC_MCO1SOURCE_HSI48)) |
AnnaBridge | 145:64910690c574 | 4506 | #else |
AnnaBridge | 145:64910690c574 | 4507 | #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ |
AnnaBridge | 145:64910690c574 | 4508 | ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ |
AnnaBridge | 145:64910690c574 | 4509 | ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \ |
AnnaBridge | 145:64910690c574 | 4510 | ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ |
AnnaBridge | 145:64910690c574 | 4511 | ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ |
AnnaBridge | 145:64910690c574 | 4512 | ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ |
AnnaBridge | 145:64910690c574 | 4513 | ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \ |
AnnaBridge | 145:64910690c574 | 4514 | ((__SOURCE__) == RCC_MCO1SOURCE_LSE)) |
AnnaBridge | 145:64910690c574 | 4515 | #endif /* RCC_HSI48_SUPPORT */ |
AnnaBridge | 145:64910690c574 | 4516 | |
AnnaBridge | 145:64910690c574 | 4517 | #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \ |
AnnaBridge | 145:64910690c574 | 4518 | ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \ |
AnnaBridge | 145:64910690c574 | 4519 | ((__DIV__) == RCC_MCODIV_16)) |
AnnaBridge | 145:64910690c574 | 4520 | |
AnnaBridge | 145:64910690c574 | 4521 | #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \ |
AnnaBridge | 145:64910690c574 | 4522 | ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ |
AnnaBridge | 145:64910690c574 | 4523 | ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ |
AnnaBridge | 145:64910690c574 | 4524 | ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) |
AnnaBridge | 145:64910690c574 | 4525 | |
AnnaBridge | 145:64910690c574 | 4526 | #define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) || \ |
AnnaBridge | 145:64910690c574 | 4527 | ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI)) |
AnnaBridge | 145:64910690c574 | 4528 | /** |
AnnaBridge | 145:64910690c574 | 4529 | * @} |
AnnaBridge | 145:64910690c574 | 4530 | */ |
AnnaBridge | 145:64910690c574 | 4531 | |
AnnaBridge | 145:64910690c574 | 4532 | /* Include RCC HAL Extended module */ |
AnnaBridge | 145:64910690c574 | 4533 | #include "stm32l4xx_hal_rcc_ex.h" |
AnnaBridge | 145:64910690c574 | 4534 | |
AnnaBridge | 145:64910690c574 | 4535 | /* Exported functions --------------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 4536 | /** @addtogroup RCC_Exported_Functions |
AnnaBridge | 145:64910690c574 | 4537 | * @{ |
AnnaBridge | 145:64910690c574 | 4538 | */ |
AnnaBridge | 145:64910690c574 | 4539 | |
AnnaBridge | 145:64910690c574 | 4540 | |
AnnaBridge | 145:64910690c574 | 4541 | /** @addtogroup RCC_Exported_Functions_Group1 |
AnnaBridge | 145:64910690c574 | 4542 | * @{ |
AnnaBridge | 145:64910690c574 | 4543 | */ |
AnnaBridge | 145:64910690c574 | 4544 | |
AnnaBridge | 145:64910690c574 | 4545 | /* Initialization and de-initialization functions ******************************/ |
AnnaBridge | 161:aa5281ff4a02 | 4546 | HAL_StatusTypeDef HAL_RCC_DeInit(void); |
AnnaBridge | 145:64910690c574 | 4547 | HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); |
AnnaBridge | 145:64910690c574 | 4548 | HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); |
AnnaBridge | 145:64910690c574 | 4549 | |
AnnaBridge | 145:64910690c574 | 4550 | /** |
AnnaBridge | 145:64910690c574 | 4551 | * @} |
AnnaBridge | 145:64910690c574 | 4552 | */ |
AnnaBridge | 145:64910690c574 | 4553 | |
AnnaBridge | 145:64910690c574 | 4554 | /** @addtogroup RCC_Exported_Functions_Group2 |
AnnaBridge | 145:64910690c574 | 4555 | * @{ |
AnnaBridge | 145:64910690c574 | 4556 | */ |
AnnaBridge | 145:64910690c574 | 4557 | |
AnnaBridge | 145:64910690c574 | 4558 | /* Peripheral Control functions ************************************************/ |
AnnaBridge | 145:64910690c574 | 4559 | void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); |
AnnaBridge | 145:64910690c574 | 4560 | void HAL_RCC_EnableCSS(void); |
AnnaBridge | 145:64910690c574 | 4561 | uint32_t HAL_RCC_GetSysClockFreq(void); |
AnnaBridge | 145:64910690c574 | 4562 | uint32_t HAL_RCC_GetHCLKFreq(void); |
AnnaBridge | 145:64910690c574 | 4563 | uint32_t HAL_RCC_GetPCLK1Freq(void); |
AnnaBridge | 145:64910690c574 | 4564 | uint32_t HAL_RCC_GetPCLK2Freq(void); |
AnnaBridge | 145:64910690c574 | 4565 | void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); |
AnnaBridge | 145:64910690c574 | 4566 | void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); |
AnnaBridge | 145:64910690c574 | 4567 | /* CSS NMI IRQ handler */ |
AnnaBridge | 145:64910690c574 | 4568 | void HAL_RCC_NMI_IRQHandler(void); |
AnnaBridge | 145:64910690c574 | 4569 | /* User Callbacks in non blocking mode (IT mode) */ |
AnnaBridge | 145:64910690c574 | 4570 | void HAL_RCC_CSSCallback(void); |
AnnaBridge | 145:64910690c574 | 4571 | |
AnnaBridge | 145:64910690c574 | 4572 | /** |
AnnaBridge | 145:64910690c574 | 4573 | * @} |
AnnaBridge | 145:64910690c574 | 4574 | */ |
AnnaBridge | 145:64910690c574 | 4575 | |
AnnaBridge | 145:64910690c574 | 4576 | /** |
AnnaBridge | 145:64910690c574 | 4577 | * @} |
AnnaBridge | 145:64910690c574 | 4578 | */ |
AnnaBridge | 145:64910690c574 | 4579 | |
AnnaBridge | 145:64910690c574 | 4580 | /** |
AnnaBridge | 145:64910690c574 | 4581 | * @} |
AnnaBridge | 145:64910690c574 | 4582 | */ |
AnnaBridge | 145:64910690c574 | 4583 | |
AnnaBridge | 145:64910690c574 | 4584 | /** |
AnnaBridge | 145:64910690c574 | 4585 | * @} |
AnnaBridge | 145:64910690c574 | 4586 | */ |
AnnaBridge | 145:64910690c574 | 4587 | |
AnnaBridge | 145:64910690c574 | 4588 | #ifdef __cplusplus |
AnnaBridge | 145:64910690c574 | 4589 | } |
AnnaBridge | 145:64910690c574 | 4590 | #endif |
AnnaBridge | 145:64910690c574 | 4591 | |
AnnaBridge | 145:64910690c574 | 4592 | #endif /* __STM32L4xx_HAL_RCC_H */ |
AnnaBridge | 145:64910690c574 | 4593 | |
AnnaBridge | 145:64910690c574 | 4594 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |