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Diff: TARGET_NUCLEO_F334R8/stm32f3xx_hal_opamp.h
- Revision:
- 122:f9eeca106725
- Parent:
- 92:4fc01daae5a5
- Child:
- 123:b0220dba8be7
--- a/TARGET_NUCLEO_F334R8/stm32f3xx_hal_opamp.h Wed May 25 16:44:06 2016 +0100
+++ b/TARGET_NUCLEO_F334R8/stm32f3xx_hal_opamp.h Thu Jul 07 14:34:11 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f3xx_hal_opamp.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 12-Sept-2014
+ * @version V1.2.1
+ * @date 29-April-2015
* @brief Header file of OPAMP HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -173,14 +173,14 @@
* @{
*/
-/** @defgroup CSR_INIT CSR init register Mask
+/** @defgroup OPAMP_CSR_INIT OPAMP CSR init register Mask
* @{
*/
/* Used for Init phase */
#define OPAMP_CSR_UPDATE_PARAMETERS_INIT_MASK (OPAMP_CSR_TRIMOFFSETN | OPAMP_CSR_TRIMOFFSETP \
| OPAMP_CSR_USERTRIM | OPAMP_CSR_PGGAIN | OPAMP_CSR_VPSSEL \
| OPAMP_CSR_VMSSEL | OPAMP_CSR_TCMEN | OPAMP_CSR_VPSEL \
- | OPAMP_CSR_VPSEL | OPAMP_CSR_FORCEVP)
+ | OPAMP_CSR_VMSEL | OPAMP_CSR_FORCEVP)
/**
* @}
@@ -206,19 +206,19 @@
* @{
*/
-#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_CSR_VPSEL /*!< VP0 (PA1 for OPAMP1, PA7 for OPAMP2, PB0 for OPAMP3, PB13 for OPAMP4)
+#define OPAMP_NONINVERTINGINPUT_IO0 OPAMP_CSR_VPSEL /*!< VP0 (PA1 for OPAMP1, VP0 PA7 for OPAMP2, VP0 PB0 for OPAMP3, VP0 PB13 for OPAMP4)
connected to OPAMPx non inverting input */
-#define OPAMP_NONINVERTINGINPUT_VP1 ((uint32_t)0x00000000) /*!< VP1 (PA7 for OPAMP1, PD14 for OPAMP2, PB13 for OPAMP3, PD11 for OPAMP4)
+#define OPAMP_NONINVERTINGINPUT_IO1 ((uint32_t)0x00000000) /*!< VP1 (PA7 for OPAMP1, VP3 PD14 for OPAMP2, VP1 PB13 for OPAMP3, VP1 PD11 for OPAMP4)
connected to OPAMPx non inverting input */
-#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_CSR_VPSEL_1 /*!< VP2 (PA3 for OPAMP1, PB0 for OPAMP2, PA1 for OPAMP3, PA4 for OPAMP4)
+#define OPAMP_NONINVERTINGINPUT_IO2 OPAMP_CSR_VPSEL_1 /*!< VP2 (PA3 for OPAMP1, VP2 PB0 for OPAMP2, VP2 PA1 for OPAMP3, VP3 PA4 for OPAMP4)
connected to OPAMPx non inverting input */
-#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_CSR_VPSEL_0 /*!< vp3 (PA5 for OPAMP1, PB14 for OPAMP2, PA5 for OPAMP3, PB11 for OPAMP4)
+#define OPAMP_NONINVERTINGINPUT_IO3 OPAMP_CSR_VPSEL_0 /*!< VP3 (PA5 for OPAMP1, VP1 PB14 for OPAMP2, VP3 PA5 for OPAMP3, VP2 PB11 for OPAMP4)
connected to OPAMPx non inverting input */
-#define IS_OPAMP_NONINVERTING_INPUT(INPUT) (((INPUT) == OPAMP_NONINVERTINGINPUT_VP0) || \
- ((INPUT) == OPAMP_NONINVERTINGINPUT_VP1) || \
- ((INPUT) == OPAMP_NONINVERTINGINPUT_VP2) || \
- ((INPUT) == OPAMP_NONINVERTINGINPUT_VP3))
+#define IS_OPAMP_NONINVERTING_INPUT(INPUT) (((INPUT) == OPAMP_NONINVERTINGINPUT_IO0) || \
+ ((INPUT) == OPAMP_NONINVERTINGINPUT_IO1) || \
+ ((INPUT) == OPAMP_NONINVERTINGINPUT_IO2) || \
+ ((INPUT) == OPAMP_NONINVERTINGINPUT_IO3))
/**
* @}
@@ -228,11 +228,11 @@
* @{
*/
-#define IOPAMP_INVERTINGINPUT_VM0 ((uint32_t)0x00000000) /*!< inverting input connected to VM0 */
-#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_CSR_VMSEL_0 /*!< inverting input connected to VM1 */
+#define OPAMP_INVERTINGINPUT_IO0 ((uint32_t)0x00000000) /*!< inverting input connected to VM0 */
+#define OPAMP_INVERTINGINPUT_IO1 OPAMP_CSR_VMSEL_0 /*!< inverting input connected to VM1 */
-#define IS_OPAMP_INVERTING_INPUT(INPUT) (((INPUT) == IOPAMP_INVERTINGINPUT_VM0) || \
- ((INPUT) == IOPAMP_INVERTINGINPUT_VM1))
+#define IS_OPAMP_INVERTING_INPUT(INPUT) (((INPUT) == OPAMP_INVERTINGINPUT_IO0) || \
+ ((INPUT) == OPAMP_INVERTINGINPUT_IO1))
/**
* @}
@@ -254,19 +254,19 @@
* @{
*/
-#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_CSR_VPSSEL /*!< VP0 (PA1 for OPAMP1, PA7 for OPAMP2, PB0 for OPAMP3, PB13 for OPAMP4)
+#define OPAMP_SEC_NONINVERTINGINPUT_IO0 OPAMP_CSR_VPSSEL /*!< VP0 (PA1 for OPAMP1, PA7 for OPAMP2, PB0 for OPAMP3, PB13 for OPAMP4)
connected to OPAMPx non inverting input */
-#define OPAMP_SEC_NONINVERTINGINPUT_VP1 ((uint32_t)0x00000000) /*!< VP1 (PA7 for OPAMP1, PD14 for OPAMP2, PB13 for OPAMP3, PD11 for OPAMP4)
+#define OPAMP_SEC_NONINVERTINGINPUT_IO1 ((uint32_t)0x00000000) /*!< VP1 (PA7 for OPAMP1, PD14 for OPAMP2, PB13 for OPAMP3, PD11 for OPAMP4)
connected to OPAMPx non inverting input */
-#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_CSR_VPSSEL_1 /*!< VP2 (PA3 for OPAMP1, PB0 for OPAMP2, PA1 for OPAMP3, PA4 for OPAMP4)
+#define OPAMP_SEC_NONINVERTINGINPUT_IO2 OPAMP_CSR_VPSSEL_1 /*!< VP2 (PA3 for OPAMP1, PB0 for OPAMP2, PA1 for OPAMP3, PA4 for OPAMP4)
connected to OPAMPx non inverting input */
-#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_CSR_VPSSEL_0 /*!< VP3 (PA5 for OPAMP1, PB14 for OPAMP2, PA5 for OPAMP3, PB11 for OPAMP4)
+#define OPAMP_SEC_NONINVERTINGINPUT_IO3 OPAMP_CSR_VPSSEL_0 /*!< VP3 (PA5 for OPAMP1, PB14 for OPAMP2, PA5 for OPAMP3, PB11 for OPAMP4)
connected to OPAMPx non inverting input */
-#define IS_OPAMP_SEC_NONINVERTINGINPUT(INPUT) (((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_VP0) || \
- ((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_VP1) || \
- ((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_VP2) || \
- ((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_VP3))
+#define IS_OPAMP_SEC_NONINVERTINGINPUT(INPUT) (((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_IO0) || \
+ ((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_IO1) || \
+ ((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_IO2) || \
+ ((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_IO3))
/**
* @}
@@ -276,13 +276,13 @@
* @{
*/
-#define OPAMP_SEC_INVERTINGINPUT_VM0 ((uint32_t)0x00000000) /*!< VM0 (PC5 for OPAMP1 and OPAMP2, PB10 for OPAMP3 and OPAMP4)
+#define OPAMP_SEC_INVERTINGINPUT_IO0 ((uint32_t)0x00000000) /*!< VM0 (PC5 for OPAMP1 and OPAMP2, PB10 for OPAMP3 and OPAMP4)
connected to OPAMPx inverting input */
-#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_CSR_VMSSEL /*!< VM1 (PA3 for OPAMP1, PA5 for OPAMP2, PB2 for OPAMP3, PD8 for OPAMP4)
+#define OPAMP_SEC_INVERTINGINPUT_IO1 OPAMP_CSR_VMSSEL /*!< VM1 (PA3 for OPAMP1, PA5 for OPAMP2, PB2 for OPAMP3, PD8 for OPAMP4)
connected to OPAMPx inverting input */
-#define IS_OPAMP_SEC_INVERTINGINPUT(INPUT) (((INPUT) == OPAMP_SEC_INVERTINGINPUT_VM0) || \
- ((INPUT) == OPAMP_SEC_INVERTINGINPUT_VM1))
+#define IS_OPAMP_SEC_INVERTINGINPUT(INPUT) (((INPUT) == OPAMP_SEC_INVERTINGINPUT_IO0) || \
+ ((INPUT) == OPAMP_SEC_INVERTINGINPUT_IO1))
/**
* @}
@@ -292,13 +292,13 @@
* @{
*/
-#define OPAMP_PGACONNECT_NO ((uint32_t)0x00000000) /*!< In PGA mode, the non inverting input is not connected */
-#define OPAMP_PGACONNECT_VM0 OPAMP_CSR_PGGAIN_3 /*!< In PGA mode, the non inverting input is connected to VM0 */
-#define OPAMP_PGACONNECT_VM1 (OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_PGGAIN_3) /*!< In PGA mode, the non inverting input is connected to VM1 */
+#define OPAMP_PGA_CONNECT_INVERTINGINPUT_NO ((uint32_t)0x00000000) /*!< In PGA mode, the non inverting input is not connected */
+#define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 OPAMP_CSR_PGGAIN_3 /*!< In PGA mode, the non inverting input is connected to VM0 */
+#define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 (OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_PGGAIN_3) /*!< In PGA mode, the non inverting input is connected to VM1 */
-#define IS_OPAMP_PGACONNECT(CONNECT) (((CONNECT) == OPAMP_PGACONNECT_NO) || \
- ((CONNECT) == OPAMP_PGACONNECT_VM0) || \
- ((CONNECT) == OPAMP_PGACONNECT_VM1))
+#define IS_OPAMP_PGACONNECT(CONNECT) (((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_NO) || \
+ ((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0) || \
+ ((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1))
/**
* @}
*/
@@ -335,7 +335,7 @@
* @{
*/
-#define OPAMP_FACTORYTRIMMING_DUMMY ((uint32_t)0xFFFFFFFF) /*!< Dummy trimming value */
+#define OPAMP_FACTORYTRIMMING_DUMMY ((uint32_t)0xFFFFFFFFU) /*!< Dummy trimming value */
#define OPAMP_FACTORYTRIMMING_N ((uint32_t)0x00000000) /*!< Offset trimming N */
#define OPAMP_FACTORYTRIMMING_P ((uint32_t)0x00000001) /*!< Offset trimming P */
