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Diff: TARGET_MTS_MDOT_F405RG/stm32f4xx_hal_dac.h
- Revision:
- 122:f9eeca106725
- Parent:
- 110:165afa46840b
--- a/TARGET_MTS_MDOT_F405RG/stm32f4xx_hal_dac.h Wed May 25 16:44:06 2016 +0100 +++ b/TARGET_MTS_MDOT_F405RG/stm32f4xx_hal_dac.h Thu Jul 07 14:34:11 2016 +0100 @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f4xx_hal_dac.h * @author MCD Application Team - * @version V1.4.1 - * @date 09-October-2015 + * @version V1.5.0 + * @date 06-May-2016 * @brief Header file of DAC HAL module. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -69,11 +69,11 @@ */ typedef enum { - HAL_DAC_STATE_RESET = 0x00, /*!< DAC not yet initialized or disabled */ - HAL_DAC_STATE_READY = 0x01, /*!< DAC initialized and ready for use */ - HAL_DAC_STATE_BUSY = 0x02, /*!< DAC internal processing is ongoing */ - HAL_DAC_STATE_TIMEOUT = 0x03, /*!< DAC timeout state */ - HAL_DAC_STATE_ERROR = 0x04 /*!< DAC error state */ + HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */ + HAL_DAC_STATE_READY = 0x01U, /*!< DAC initialized and ready for use */ + HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */ + HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */ + HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */ }HAL_DAC_StateTypeDef; /** @@ -118,10 +118,10 @@ /** @defgroup DAC_Error_Code DAC Error Code * @{ */ -#define HAL_DAC_ERROR_NONE 0x00 /*!< No error */ -#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01 /*!< DAC channel1 DAM underrun error */ -#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02 /*!< DAC channel2 DAM underrun error */ -#define HAL_DAC_ERROR_DMA 0x04 /*!< DMA error */ +#define HAL_DAC_ERROR_NONE 0x00U /*!< No error */ +#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DAM underrun error */ +#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DAM underrun error */ +#define HAL_DAC_ERROR_DMA 0x04U /*!< DMA error */ /** * @} */ @@ -130,7 +130,7 @@ * @{ */ -#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register +#define DAC_TRIGGER_NONE ((uint32_t)0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register has been loaded, and not by external trigger */ #define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ @@ -148,7 +148,7 @@ /** @defgroup DAC_output_buffer DAC Output Buffer * @{ */ -#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000) +#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000U) #define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1) /** * @} @@ -157,8 +157,8 @@ /** @defgroup DAC_Channel_selection DAC Channel Selection * @{ */ -#define DAC_CHANNEL_1 ((uint32_t)0x00000000) -#define DAC_CHANNEL_2 ((uint32_t)0x00000010) +#define DAC_CHANNEL_1 ((uint32_t)0x00000000U) +#define DAC_CHANNEL_2 ((uint32_t)0x00000010U) /** * @} */ @@ -166,9 +166,9 @@ /** @defgroup DAC_data_alignment DAC Data Alignment * @{ */ -#define DAC_ALIGN_12B_R ((uint32_t)0x00000000) -#define DAC_ALIGN_12B_L ((uint32_t)0x00000004) -#define DAC_ALIGN_8B_R ((uint32_t)0x00000008) +#define DAC_ALIGN_12B_R ((uint32_t)0x00000000U) +#define DAC_ALIGN_12B_L ((uint32_t)0x00000004U) +#define DAC_ALIGN_8B_R ((uint32_t)0x00000008U) /** * @} */ @@ -344,7 +344,7 @@ /** @defgroup DAC_Private_Macros DAC Private Macros * @{ */ -#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) +#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U) #define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \ ((ALIGN) == DAC_ALIGN_12B_L) || \ ((ALIGN) == DAC_ALIGN_8B_R)) @@ -367,19 +367,19 @@ * @param __ALIGNMENT__: specifies the DAC alignment * @retval None */ -#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008) + (__ALIGNMENT__)) +#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008U) + (__ALIGNMENT__)) /** @brief Set DHR12R2 alignment * @param __ALIGNMENT__: specifies the DAC alignment * @retval None */ -#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014) + (__ALIGNMENT__)) +#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014U) + (__ALIGNMENT__)) /** @brief Set DHR12RD alignment * @param __ALIGNMENT__: specifies the DAC alignment * @retval None */ -#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020) + (__ALIGNMENT__)) +#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020U) + (__ALIGNMENT__)) /** * @}