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Diff: TARGET_B96B_F446VE/TARGET_STM/mbed_rtx.h
- Revision:
- 163:e59c8e839560
- Parent:
- 161:aa5281ff4a02
- Child:
- 165:d1b4690b3f8b
--- a/TARGET_B96B_F446VE/TARGET_STM/mbed_rtx.h Mon Mar 19 15:30:13 2018 +0000
+++ b/TARGET_B96B_F446VE/TARGET_STM/mbed_rtx.h Tue Mar 20 13:30:58 2018 +0000
@@ -19,7 +19,21 @@
#ifndef INITIAL_SP
-#if (defined(TARGET_STM32F051R8) ||\
+#if (defined(TARGET_STM32L475VG) ||\
+ defined(TARGET_STM32L476RG) ||\
+ defined(TARGET_STM32L476JG) ||\
+ defined(TARGET_STM32L476VG) ||\
+ defined(TARGET_STM32L486RG))
+/* only GCC_ARM and IAR toolchains have the stack on SRAM2 */
+#if (((defined(__GNUC__) && !defined(__CC_ARM)) ||\
+ defined(__IAR_SYSTEMS_ICC__ )) &&\
+ defined(TWO_RAM_REGIONS))
+#define INITIAL_SP (0x10008000UL)
+#else
+#define INITIAL_SP (0x20018000UL)
+#endif /* toolchains */
+
+#elif (defined(TARGET_STM32F051R8) ||\
defined(TARGET_STM32F100RB) ||\
defined(TARGET_STM32L031K6) ||\
defined(TARGET_STM32L053C8) ||\
@@ -69,11 +83,7 @@
#define INITIAL_SP (0x20014000UL)
#elif (defined(TARGET_STM32F401RE) ||\
- defined(TARGET_STM32L475VG) ||\
- defined(TARGET_STM32L476RG) ||\
- defined(TARGET_STM32L476JG) ||\
- defined(TARGET_STM32L476VG) ||\
- defined(TARGET_STM32L486RG))
+ defined(TARGET_STM32F401VE))
#define INITIAL_SP (0x20018000UL)
#elif (defined(TARGET_STM32F207ZG) ||\
@@ -110,5 +120,15 @@
#endif
#endif // INITIAL_SP
+#if (defined(__GNUC__) && !defined(__CC_ARM) && defined(TWO_RAM_REGIONS))
+ extern uint32_t __StackLimit[];
+ extern uint32_t __StackTop[];
+ extern uint32_t __end__[];
+ extern uint32_t __HeapLimit[];
+ #define HEAP_START ((unsigned char*)__end__)
+ #define HEAP_SIZE ((uint32_t)((uint32_t)__HeapLimit - (uint32_t)HEAP_START))
+ #define ISR_STACK_START ((unsigned char*)__StackLimit)
+ #define ISR_STACK_SIZE ((uint32_t)((uint32_t)__StackTop - (uint32_t)__StackLimit))
+#endif
#endif // MBED_MBED_RTX_H
