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Diff: TARGET_DISCO_L475VG_IOT01A/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h
- Revision:
- 161:aa5281ff4a02
- Parent:
- 145:64910690c574
--- a/TARGET_DISCO_L475VG_IOT01A/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h Wed Jan 17 16:13:02 2018 +0000 +++ b/TARGET_DISCO_L475VG_IOT01A/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h Fri Feb 16 16:16:41 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_tim_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of TIM HAL Extended module. ****************************************************************************** * @attention @@ -59,28 +57,28 @@ * @{ */ -/** - * @brief TIM Hall sensor Configuration Structure definition +/** + * @brief TIM Hall sensor Configuration Structure definition */ typedef struct { - + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - + uint32_t IC1Filter; /*!< Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ } TIM_HallSensor_InitTypeDef; -/** - * @brief TIM Break/Break2 input configuration +/** + * @brief TIM Break/Break2 input configuration */ typedef struct { uint32_t Source; /*!< Specifies the source of the timer break input. @@ -119,15 +117,18 @@ /* STM32L496xx || STM32L4A6xx */ #define TIM_TIM1_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM1 TI1 is connected to GPIO */ #define TIM_TIM1_TI1_COMP1 (TIM1_OR1_TI1_RMP) /* !< TIM1 TI1 is connected to COMP1 */ +#define TIM_TIM1_ETR_GPIO ((uint32_t)(0x00000000)) /* !< TIM1_ETR is connected to GPIO */ #define TIM_TIM1_ETR_COMP1 (TIM1_OR2_ETRSEL_0) /* !< TIM1_ETR is connected to COMP1 output */ #define TIM_TIM1_ETR_COMP2 (TIM1_OR2_ETRSEL_1) /* !< TIM1_ETR is connected to COMP2 output */ #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define TIM_TIM2_ITR1_TIM8_TRGO ((uint32_t)(0x00000000)) /* !< TIM2_ITR1 is connected to TIM8_TRGO */ #define TIM_TIM2_ITR1_OTG_FS_SOF (TIM2_OR1_ITR1_RMP) /* !< TIM2_ITR1 is connected to OTG_FS SOF */ #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) #define TIM_TIM2_ITR1_NONE ((uint32_t)(0x00000000)) /* !< No internal trigger on TIM2_ITR1 */ @@ -145,7 +146,8 @@ #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define TIM_TIM3_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM3 TI1 is connected to GPIO */ #define TIM_TIM3_TI1_COMP1 (TIM3_OR1_TI1_RMP_0) /* !< TIM3 TI1 is connected to COMP1 output */ #define TIM_TIM3_TI1_COMP2 (TIM3_OR1_TI1_RMP_1) /* !< TIM3 TI1 is connected to COMP2 output */ @@ -154,7 +156,8 @@ #define TIM_TIM3_ETR_COMP1 (TIM3_OR2_ETRSEL_0) /* !< TIM3_ETR is connected to COMP1 output */ #endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ defined (STM32L496xx) || defined (STM32L4A6xx) @@ -166,12 +169,19 @@ #define TIM_TIM8_ETR_ADC3_AWD1 (TIM8_OR1_ETR_ADC3_RMP_0) /* !< TIM8_ETR is connected to ADC3 AWD1 */ #define TIM_TIM8_ETR_ADC3_AWD2 (TIM8_OR1_ETR_ADC3_RMP_1) /* !< TIM8_ETR is connected to ADC3 AWD2 */ #define TIM_TIM8_ETR_ADC3_AWD3 (TIM8_OR1_ETR_ADC3_RMP_1 | TIM8_OR1_ETR_ADC3_RMP_0) /* !< TIM8_ETR is connected to ADC3 AWD3 */ +#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ + /* STM32L496xx || STM32L4A6xx */ +#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#define TIM_TIM8_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM8 TI1 is connected to GPIO */ +#define TIM_TIM8_TI1_COMP2 (TIM8_OR1_TI1_RMP) /* !< TIM8 TI1 is connected to COMP1 */ +#define TIM_TIM8_ETR_GPIO ((uint32_t)(0x00000000)) /* !< TIM8_ETR is connected to GPIO */ #define TIM_TIM8_ETR_COMP1 (TIM8_OR2_ETRSEL_0) /* !< TIM8_ETR is connected to COMP1 output */ #define TIM_TIM8_ETR_COMP2 (TIM8_OR2_ETRSEL_1) /* !< TIM8_ETR is connected to COMP2 output */ -#define TIM_TIM8_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM8 TI1 is connected to GPIO */ -#define TIM_TIM8_TI1_COMP2 (TIM8_OR1_TI1_RMP) /* !< TIM8 TI1 is connected to COMP1 */ #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #define TIM_TIM15_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM15 TI1 is connected to GPIO */ #define TIM_TIM15_TI1_LSE (TIM15_OR1_TI1_RMP) /* !< TIM15 TI1 is connected to LSE */ @@ -179,16 +189,20 @@ #define TIM_TIM15_ENCODERMODE_TIM2 (TIM15_OR1_ENCODER_MODE_0) /* !< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define TIM_TIM15_ENCODERMODE_TIM3 (TIM15_OR1_ENCODER_MODE_1) /* !< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ #endif /* STM32L451xx || STM32L452xx || STM32L462xx */ /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define TIM_TIM15_ENCODERMODE_TIM4 (TIM15_OR1_ENCODER_MODE_1 | TIM15_OR1_ENCODER_MODE_0) /* !< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #define TIM_TIM16_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM16 TI1 is connected to GPIO */ #define TIM_TIM16_TI1_LSI (TIM16_OR1_TI1_RMP_0) /* !< TIM16 TI1 is connected to LSI */ @@ -205,13 +219,15 @@ /* STM32L496xx || STM32L4A6xx */ #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define TIM_TIM17_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM17 TI1 is connected to GPIO */ #define TIM_TIM17_TI1_MSI (TIM17_OR1_TI1_RMP_0) /* !< TIM17 TI1 is connected to MSI */ #define TIM_TIM17_TI1_HSE_32 (TIM17_OR1_TI1_RMP_1) /* !< TIM17 TI1 is connected to HSE div 32 */ #define TIM_TIM17_TI1_MCO (TIM17_OR1_TI1_RMP_1 | TIM17_OR1_TI1_RMP_0) /* !< TIM17 TI1 is connected to MCO */ #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** * @} */ @@ -233,11 +249,13 @@ #define TIM_BREAKINPUTSOURCE_COMP2 ((uint32_t)(0x00000004)) /* !< The COMP2 output is connected to the break input */ #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define TIM_BREAKINPUTSOURCE_DFSDM1 ((uint32_t)(0x00000008)) /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */ #endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** * @} */ @@ -259,7 +277,7 @@ /** * @} */ - + /** * @} */ @@ -286,7 +304,8 @@ #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \ @@ -295,7 +314,9 @@ #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2)) -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ +#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \ ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE)) @@ -312,7 +333,7 @@ * @{ */ -/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions +/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions * @brief Timer Hall Sensor functions * @{ */ @@ -409,7 +430,7 @@ * @} */ -/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions +/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions * @brief Extended Callbacks functions * @{ */ @@ -420,7 +441,7 @@ * @} */ -/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions +/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions * @brief Extended Peripheral State functions * @{ */ @@ -452,7 +473,7 @@ /** * @} */ - + #ifdef __cplusplus } #endif