mbed official
The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.
Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more
mbed 2
This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.
Diff: TARGET_NUCLEO_F756ZG/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_sdmmc.h
- Revision:
- 139:856d2700e60b
- Parent:
- 135:176b8275d35d
- Child:
- 146:22da6e220af6
--- a/TARGET_NUCLEO_F756ZG/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_sdmmc.h Tue Mar 14 16:20:51 2017 +0000
+++ b/TARGET_NUCLEO_F756ZG/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_sdmmc.h Thu Mar 30 13:26:47 2017 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_ll_sdmmc.h
* @author MCD Application Team
- * @version V1.1.2
- * @date 23-September-2016
+ * @version V1.2.0
+ * @date 30-December-2016
* @brief Header file of SDMMC HAL module.
******************************************************************************
* @attention
@@ -145,6 +145,196 @@
/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
* @{
*/
+#define SDMMC_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
+#define SDMMC_ERROR_CMD_CRC_FAIL ((uint32_t)0x00000001U) /*!< Command response received (but CRC check failed) */
+#define SDMMC_ERROR_DATA_CRC_FAIL ((uint32_t)0x00000002U) /*!< Data block sent/received (CRC check failed) */
+#define SDMMC_ERROR_CMD_RSP_TIMEOUT ((uint32_t)0x00000004U) /*!< Command response timeout */
+#define SDMMC_ERROR_DATA_TIMEOUT ((uint32_t)0x00000008U) /*!< Data timeout */
+#define SDMMC_ERROR_TX_UNDERRUN ((uint32_t)0x00000010U) /*!< Transmit FIFO underrun */
+#define SDMMC_ERROR_RX_OVERRUN ((uint32_t)0x00000020U) /*!< Receive FIFO overrun */
+#define SDMMC_ERROR_ADDR_MISALIGNED ((uint32_t)0x00000040U) /*!< Misaligned address */
+#define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the
+ number of transferred bytes does not match the block length */
+#define SDMMC_ERROR_ERASE_SEQ_ERR ((uint32_t)0x00000100U) /*!< An error in the sequence of erase command occurs */
+#define SDMMC_ERROR_BAD_ERASE_PARAM ((uint32_t)0x00000200U) /*!< An invalid selection for erase groups */
+#define SDMMC_ERROR_WRITE_PROT_VIOLATION ((uint32_t)0x00000400U) /*!< Attempt to program a write protect block */
+#define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock
+ command or if there was an attempt to access a locked card */
+#define SDMMC_ERROR_COM_CRC_FAILED ((uint32_t)0x00001000U) /*!< CRC check of the previous command failed */
+#define SDMMC_ERROR_ILLEGAL_CMD ((uint32_t)0x00002000U) /*!< Command is not legal for the card state */
+#define SDMMC_ERROR_CARD_ECC_FAILED ((uint32_t)0x00004000U) /*!< Card internal ECC was applied but failed to correct the data */
+#define SDMMC_ERROR_CC_ERR ((uint32_t)0x00008000U) /*!< Internal card controller error */
+#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR ((uint32_t)0x00010000U) /*!< General or unknown error */
+#define SDMMC_ERROR_STREAM_READ_UNDERRUN ((uint32_t)0x00020000U) /*!< The card could not sustain data reading in stream rmode */
+#define SDMMC_ERROR_STREAM_WRITE_OVERRUN ((uint32_t)0x00040000U) /*!< The card could not sustain data programming in stream mode */
+#define SDMMC_ERROR_CID_CSD_OVERWRITE ((uint32_t)0x00080000U) /*!< CID/CSD overwrite error */
+#define SDMMC_ERROR_WP_ERASE_SKIP ((uint32_t)0x00100000U) /*!< Only partial address space was erased */
+#define SDMMC_ERROR_CARD_ECC_DISABLED ((uint32_t)0x00200000U) /*!< Command has been executed without using internal ECC */
+#define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out
+ of erase sequence command was received */
+#define SDMMC_ERROR_AKE_SEQ_ERR ((uint32_t)0x00800000U) /*!< Error in sequence of authentication */
+#define SDMMC_ERROR_INVALID_VOLTRANGE ((uint32_t)0x01000000U) /*!< Error in case of invalid voltage range */
+#define SDMMC_ERROR_ADDR_OUT_OF_RANGE ((uint32_t)0x02000000U) /*!< Error when addressed block is out of range */
+#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE ((uint32_t)0x04000000U) /*!< Error when command request is not applicable */
+#define SDMMC_ERROR_INVALID_PARAMETER ((uint32_t)0x08000000U) /*!< the used parameter is not valid */
+#define SDMMC_ERROR_UNSUPPORTED_FEATURE ((uint32_t)0x10000000U) /*!< Error when feature is not insupported */
+#define SDMMC_ERROR_BUSY ((uint32_t)0x20000000U) /*!< Error when transfer process is busy */
+#define SDMMC_ERROR_DMA ((uint32_t)0x40000000U) /*!< Error while DMA transfer */
+#define SDMMC_ERROR_TIMEOUT ((uint32_t)0x80000000U) /*!< Timeout error */
+
+/**
+ * @brief SDMMC Commands Index
+ */
+#define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0U) /*!< Resets the SD memory card. */
+#define SDMMC_CMD_SEND_OP_COND ((uint8_t)1U) /*!< Sends host capacity support information and activates the card's initialization process. */
+#define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */
+#define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3U) /*!< Asks the card to publish a new relative address (RCA). */
+#define SDMMC_CMD_SET_DSR ((uint8_t)4U) /*!< Programs the DSR of all cards. */
+#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
+ operating condition register (OCR) content in the response on the CMD line. */
+#define SDMMC_CMD_HS_SWITCH ((uint8_t)6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */
+#define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7U) /*!< Selects the card by its own relative address and gets deselected by any other address */
+#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
+ and asks the card whether card supports voltage. */
+#define SDMMC_CMD_SEND_CSD ((uint8_t)9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */
+#define SDMMC_CMD_SEND_CID ((uint8_t)10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */
+#define SDMMC_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11U) /*!< SD card doesn't support it. */
+#define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12U) /*!< Forces the card to stop transmission. */
+#define SDMMC_CMD_SEND_STATUS ((uint8_t)13U) /*!< Addressed card sends its status register. */
+#define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U) /*!< Reserved */
+#define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /*!< Sends an addressed card into the inactive state. */
+#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands
+ (read, write, lock). Default block length is fixed to 512 Bytes. Not effective
+ for SDHS and SDXC. */
+#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
+ fixed 512 bytes in case of SDHC and SDXC. */
+#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by
+ STOP_TRANSMISSION command. */
+#define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */
+#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /*!< Speed class control command. */
+#define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /*!< Specify block count for CMD18 and CMD25. */
+#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
+ fixed 512 bytes in case of SDHC and SDXC. */
+#define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */
+#define SDMMC_CMD_PROG_CID ((uint8_t)26U) /*!< Reserved for manufacturers. */
+#define SDMMC_CMD_PROG_CSD ((uint8_t)27U) /*!< Programming of the programmable bits of the CSD. */
+#define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28U) /*!< Sets the write protection bit of the addressed group. */
+#define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29U) /*!< Clears the write protection bit of the addressed group. */
+#define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30U) /*!< Asks the card to send the status of the write protection bits. */
+#define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */
+#define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /*!< Sets the address of the last write block of the continuous range to be erased. */
+#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command
+ system set by switch function command (CMD6). */
+#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased.
+ Reserved for each command system set by switch function command (CMD6). */
+#define SDMMC_CMD_ERASE ((uint8_t)38U) /*!< Reserved for SD security applications. */
+#define SDMMC_CMD_FAST_IO ((uint8_t)39U) /*!< SD card doesn't support it (Reserved). */
+#define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40U) /*!< SD card doesn't support it (Reserved). */
+#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
+ the SET_BLOCK_LEN command. */
+#define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather
+ than a standard command. */
+#define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card
+ for general purpose/application specific commands. */
+#define SDMMC_CMD_NO_CMD ((uint8_t)64U) /*!< No command */
+
+/**
+ * @brief Following commands are SD Card Specific commands.
+ * SDMMC_APP_CMD should be sent before sending these commands.
+ */
+#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
+ widths are given in SCR register. */
+#define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13U) /*!< (ACMD13) Sends the SD status. */
+#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
+ 32bit+CRC data block. */
+#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
+ send its operating condition register (OCR) content in the response on the CMD line. */
+#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */
+#define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /*!< Reads the SD Configuration Register (SCR). */
+#define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /*!< For SD I/O card only, reserved for security specification. */
+#define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /*!< For SD I/O card only, reserved for security specification. */
+
+/**
+ * @brief Following commands are SD Card Specific security commands.
+ * SDMMC_CMD_APP_CMD should be sent before sending these commands.
+ */
+#define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43U)
+#define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44U)
+#define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45U)
+#define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46U)
+#define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47U)
+#define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48U)
+#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18U)
+#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25U)
+#define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38U)
+#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49U)
+#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48U)
+
+/**
+ * @brief Masks for errors Card Status R1 (OCR Register)
+ */
+#define SDMMC_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000U)
+#define SDMMC_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000U)
+#define SDMMC_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000U)
+#define SDMMC_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000U)
+#define SDMMC_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000U)
+#define SDMMC_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000U)
+#define SDMMC_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000U)
+#define SDMMC_OCR_COM_CRC_FAILED ((uint32_t)0x00800000U)
+#define SDMMC_OCR_ILLEGAL_CMD ((uint32_t)0x00400000U)
+#define SDMMC_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000U)
+#define SDMMC_OCR_CC_ERROR ((uint32_t)0x00100000U)
+#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000U)
+#define SDMMC_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000U)
+#define SDMMC_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000U)
+#define SDMMC_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000U)
+#define SDMMC_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000U)
+#define SDMMC_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000U)
+#define SDMMC_OCR_ERASE_RESET ((uint32_t)0x00002000U)
+#define SDMMC_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008U)
+#define SDMMC_OCR_ERRORBITS ((uint32_t)0xFDFFE008U)
+
+/**
+ * @brief Masks for R6 Response
+ */
+#define SDMMC_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000U)
+#define SDMMC_R6_ILLEGAL_CMD ((uint32_t)0x00004000U)
+#define SDMMC_R6_COM_CRC_FAILED ((uint32_t)0x00008000U)
+
+#define SDMMC_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000U)
+#define SDMMC_HIGH_CAPACITY ((uint32_t)0x40000000U)
+#define SDMMC_STD_CAPACITY ((uint32_t)0x00000000U)
+#define SDMMC_CHECK_PATTERN ((uint32_t)0x000001AAU)
+
+#define SDMMC_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFFU)
+
+#define SDMMC_MAX_TRIAL ((uint32_t)0x0000FFFFU)
+
+#define SDMMC_ALLZERO ((uint32_t)0x00000000U)
+
+#define SDMMC_WIDE_BUS_SUPPORT ((uint32_t)0x00040000U)
+#define SDMMC_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U)
+#define SDMMC_CARD_LOCKED ((uint32_t)0x02000000U)
+
+#define SDMMC_DATATIMEOUT ((uint32_t)0x00100000U)
+
+#define SDMMC_0TO7BITS ((uint32_t)0x000000FFU)
+#define SDMMC_8TO15BITS ((uint32_t)0x0000FF00U)
+#define SDMMC_16TO23BITS ((uint32_t)0x00FF0000U)
+#define SDMMC_24TO31BITS ((uint32_t)0xFF000000U)
+#define SDMMC_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFFU)
+
+#define SDMMC_HALFFIFO ((uint32_t)0x00000008U)
+#define SDMMC_HALFFIFOBYTES ((uint32_t)0x00000020U)
+
+/**
+ * @brief Command Class supported
+ */
+#define SDMMC_CCCC_ERASE ((uint32_t)0x00000020U)
+
+#define SDMMC_CMDTIMEOUT ((uint32_t)5000U) /* Command send and response timeout */
+#define SDMMC_MAXERASETIMEOUT ((uint32_t)63000U) /* Max erase Timeout 63 s */
+
/** @defgroup SDMMC_LL_Clock_Edge Clock Edge
* @{
@@ -153,7 +343,7 @@
#define SDMMC_CLOCK_EDGE_FALLING SDMMC_CLKCR_NEGEDGE
#define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \
- ((EDGE) == SDMMC_CLOCK_EDGE_FALLING))
+ ((EDGE) == SDMMC_CLOCK_EDGE_FALLING))
/**
* @}
*/
@@ -165,7 +355,7 @@
#define SDMMC_CLOCK_BYPASS_ENABLE SDMMC_CLKCR_BYPASS
#define IS_SDMMC_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDMMC_CLOCK_BYPASS_DISABLE) || \
- ((BYPASS) == SDMMC_CLOCK_BYPASS_ENABLE))
+ ((BYPASS) == SDMMC_CLOCK_BYPASS_ENABLE))
/**
* @}
*/
@@ -177,7 +367,7 @@
#define SDMMC_CLOCK_POWER_SAVE_ENABLE SDMMC_CLKCR_PWRSAV
#define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \
- ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE))
+ ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE))
/**
* @}
*/
@@ -190,8 +380,8 @@
#define SDMMC_BUS_WIDE_8B SDMMC_CLKCR_WIDBUS_1
#define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \
- ((WIDE) == SDMMC_BUS_WIDE_4B) || \
- ((WIDE) == SDMMC_BUS_WIDE_8B))
+ ((WIDE) == SDMMC_BUS_WIDE_4B) || \
+ ((WIDE) == SDMMC_BUS_WIDE_8B))
/**
* @}
*/
@@ -203,7 +393,7 @@
#define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE SDMMC_CLKCR_HWFC_EN
#define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \
- ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE))
+ ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE))
/**
* @}
*/
@@ -232,8 +422,8 @@
#define SDMMC_RESPONSE_LONG SDMMC_CMD_WAITRESP
#define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO) || \
- ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \
- ((RESPONSE) == SDMMC_RESPONSE_LONG))
+ ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \
+ ((RESPONSE) == SDMMC_RESPONSE_LONG))
/**
* @}
*/
@@ -246,8 +436,8 @@
#define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND
#define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \
- ((WAIT) == SDMMC_WAIT_IT) || \
- ((WAIT) == SDMMC_WAIT_PEND))
+ ((WAIT) == SDMMC_WAIT_IT) || \
+ ((WAIT) == SDMMC_WAIT_PEND))
/**
* @}
*/
@@ -259,7 +449,7 @@
#define SDMMC_CPSM_ENABLE SDMMC_CMD_CPSMEN
#define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \
- ((CPSM) == SDMMC_CPSM_ENABLE))
+ ((CPSM) == SDMMC_CPSM_ENABLE))
/**
* @}
*/
@@ -273,9 +463,9 @@
#define SDMMC_RESP4 ((uint32_t)0x0000000C)
#define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \
- ((RESP) == SDMMC_RESP2) || \
- ((RESP) == SDMMC_RESP3) || \
- ((RESP) == SDMMC_RESP4))
+ ((RESP) == SDMMC_RESP2) || \
+ ((RESP) == SDMMC_RESP3) || \
+ ((RESP) == SDMMC_RESP4))
/**
* @}
*/
@@ -308,20 +498,20 @@
#define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
#define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) || \
- ((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || \
- ((SIZE) == SDMMC_DATABLOCK_SIZE_4B) || \
- ((SIZE) == SDMMC_DATABLOCK_SIZE_8B) || \
- ((SIZE) == SDMMC_DATABLOCK_SIZE_16B) || \
- ((SIZE) == SDMMC_DATABLOCK_SIZE_32B) || \
- ((SIZE) == SDMMC_DATABLOCK_SIZE_64B) || \
- ((SIZE) == SDMMC_DATABLOCK_SIZE_128B) || \
- ((SIZE) == SDMMC_DATABLOCK_SIZE_256B) || \
- ((SIZE) == SDMMC_DATABLOCK_SIZE_512B) || \
- ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \
- ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \
- ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \
- ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \
- ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B))
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || \
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_4B) || \
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_8B) || \
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_16B) || \
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_32B) || \
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_64B) || \
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_128B) || \
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_256B) || \
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_512B) || \
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B))
/**
* @}
*/
@@ -333,7 +523,7 @@
#define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR
#define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \
- ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC))
+ ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC))
/**
* @}
*/
@@ -345,7 +535,7 @@
#define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE
#define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \
- ((MODE) == SDMMC_TRANSFER_MODE_STREAM))
+ ((MODE) == SDMMC_TRANSFER_MODE_STREAM))
/**
* @}
*/
@@ -357,7 +547,7 @@
#define SDMMC_DPSM_ENABLE SDMMC_DCTRL_DTEN
#define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\
- ((DPSM) == SDMMC_DPSM_ENABLE))
+ ((DPSM) == SDMMC_DPSM_ENABLE))
/**
* @}
*/
@@ -369,7 +559,7 @@
#define SDMMC_READ_WAIT_MODE_CLK (SDMMC_DCTRL_RWMOD)
#define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \
- ((MODE) == SDMMC_READ_WAIT_MODE_DATA2))
+ ((MODE) == SDMMC_READ_WAIT_MODE_DATA2))
/**
* @}
*/
@@ -428,6 +618,10 @@
#define SDMMC_FLAG_TXDAVL SDMMC_STA_TXDAVL
#define SDMMC_FLAG_RXDAVL SDMMC_STA_RXDAVL
#define SDMMC_FLAG_SDIOIT SDMMC_STA_SDIOIT
+#define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\
+ SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\
+ SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\
+ SDMMC_FLAG_DBCKEND))
/**
* @}
*/
@@ -464,7 +658,7 @@
SDMMC_CMD_CPSMEN | SDMMC_CMD_SDIOSUSPEND))
/* SDMMC Initialization Frequency (400KHz max) */
-#define SDMMC_INIT_CLK_DIV ((uint8_t)0x76)
+#define SDMMC_INIT_CLK_DIV ((uint8_t)0x76)
/* SDMMC Data Transfer Frequency (25MHz max) */
#define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0)
@@ -751,7 +945,6 @@
/** @addtogroup HAL_SDMMC_LL_Group2
* @{
*/
-/* Blocking mode: Polling */
uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx);
HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData);
/**
@@ -772,13 +965,40 @@
uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response);
/* Data path state machine (DPSM) management functions */
-HAL_StatusTypeDef SDMMC_DataConfig(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data);
+HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data);
uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx);
uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx);
/* SDMMC Cards mode management functions */
HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode);
+/* SDMMC Commands management functions */
+uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize);
+uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd);
+uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd);
+uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd);
+uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd);
+uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd);
+uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd);
+uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd);
+uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd);
+uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr);
+uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
+uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t SdType);
+uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth);
+uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
+uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA);
+uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
+uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
+uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
+
/**
* @}
*/
