Diff: TARGET_DISCO_L072CZ_LRWAN1/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_ll_utils.h

Revision:

167:84c0a372a020

Parent:

143:86740a56073b

--- a/TARGET_DISCO_L072CZ_LRWAN1/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_ll_utils.h	Fri Apr 20 11:08:29 2018 +0100
+++ b/TARGET_DISCO_L072CZ_LRWAN1/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_ll_utils.h	Fri May 11 16:51:14 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l0xx_ll_utils.h
   * @author  MCD Application Team
-  * @version V1.7.0
-  * @date    31-May-2016
   * @brief   Header file of UTILS LL module.
   @verbatim
   ==============================================================================
@@ -75,7 +73,7 @@
   */
 
 /* Max delay can be used in LL_mDelay */
-#define LL_MAX_DELAY                  (uint32_t)0xFFFFFFFFU
+#define LL_MAX_DELAY                  0xFFFFFFFFU
 
 /**
  * @brief Unique device ID register base address
@@ -87,6 +85,7 @@
  */
 #define FLASHSIZE_BASE_ADDRESS        FLASHSIZE_BASE
 
+
 /**
   * @}
   */
@@ -157,12 +156,13 @@
 /** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
   * @{
   */
-#define LL_UTILS_HSEBYPASS_OFF        (uint32_t)0x00000000U       /*!< HSE Bypass is not enabled                */
-#define LL_UTILS_HSEBYPASS_ON         (uint32_t)0x00000001U       /*!< HSE Bypass is enabled                    */
+#define LL_UTILS_HSEBYPASS_OFF        0x00000000U       /*!< HSE Bypass is not enabled                */
+#define LL_UTILS_HSEBYPASS_ON         0x00000001U       /*!< HSE Bypass is enabled                    */
 /**
   * @}
   */
 
+
 /**
   * @}
   */
@@ -216,6 +216,7 @@
   return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));
 }
 
+
 /**
   * @}
   */