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Diff: TARGET_DISCO_L072CZ_LRWAN1/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_ll_system.h
- Revision:
- 167:84c0a372a020
- Parent:
- 143:86740a56073b
--- a/TARGET_DISCO_L072CZ_LRWAN1/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_ll_system.h Fri Apr 20 11:08:29 2018 +0100
+++ b/TARGET_DISCO_L072CZ_LRWAN1/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_ll_system.h Fri May 11 16:51:14 2018 +0100
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_ll_system.h
* @author MCD Application Team
- * @version V1.7.0
- * @date 31-May-2016
* @brief Header file of SYSTEM LL module.
@verbatim
==============================================================================
@@ -230,41 +228,41 @@
-/** @defgroup SYSTEM_LL_EC_ABP1_GRP1_STOP_IP DBGMCU ABP1 GRP1 STOP IP
+/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
* @{
*/
-#define LL_DBGMCU_ABP1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */
#if defined(TIM3)
-#define LL_DBGMCU_ABP1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */
#endif /*TIM3*/
#if defined(TIM6)
-#define LL_DBGMCU_ABP1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */
#endif /*TIM6*/
#if defined(TIM7)
-#define LL_DBGMCU_ABP1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */
#endif /*TIM7*/
-#define LL_DBGMCU_ABP1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /*!< RTC Calendar frozen when core is halted */
-#define LL_DBGMCU_ABP1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */
-#define LL_DBGMCU_ABP1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */
-#define LL_DBGMCU_ABP1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_STOP /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /*!< RTC Calendar frozen when core is halted */
+#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */
+#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */
+#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_STOP /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
#if defined(I2C2)
-#define LL_DBGMCU_ABP1_GRP1_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_STOP /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
+#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_STOP /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
#endif /*I2C2*/
#if defined(I2C3)
-#define LL_DBGMCU_ABP1_GRP1_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_STOP /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
+#define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_STOP /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
#endif /*I2C3*/
-#define LL_DBGMCU_ABP1_GRP1_LPTIM1_STOP DBGMCU_APB1_FZ_DBG_LPTIMER_STOP /*!< LPTIM1 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1_FZ_DBG_LPTIMER_STOP /*!< LPTIM1 counter stopped when core is halted */
/**
* @}
*/
-/** @defgroup SYSTEM_LL_EC_ABP2_GRP1_STOP_IP DBGMCU ABP2 GRP1 STOP IP
+/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
* @{
*/
#if defined(TIM22)
-#define LL_DBGMCU_ABP2_GRP1_TIM22_STOP DBGMCU_APB2_FZ_DBG_TIM22_STOP /*!< TIM22 counter stopped when core is halted */
+#define LL_DBGMCU_APB2_GRP1_TIM22_STOP DBGMCU_APB2_FZ_DBG_TIM22_STOP /*!< TIM22 counter stopped when core is halted */
#endif /*TIM22*/
-#define LL_DBGMCU_ABP2_GRP1_TIM21_STOP DBGMCU_APB2_FZ_DBG_TIM21_STOP /*!< TIM21 counter stopped when core is halted */
+#define LL_DBGMCU_APB2_GRP1_TIM21_STOP DBGMCU_APB2_FZ_DBG_TIM21_STOP /*!< TIM21 counter stopped when core is halted */
/**
* @}
*/
@@ -816,100 +814,100 @@
/**
* @brief Freeze APB1 peripherals (group1 peripherals)
- * @rmtoll APB1FZ DBG_TIM2_STOP LL_DBGMCU_ABP1_GRP1_FreezePeriph\n
- * APB1FZ DBG_TIM3_STOP LL_DBGMCU_ABP1_GRP1_FreezePeriph\n
- * APB1FZ DBG_TIM6_STOP LL_DBGMCU_ABP1_GRP1_FreezePeriph\n
- * APB1FZ DBG_TIM7_STOP LL_DBGMCU_ABP1_GRP1_FreezePeriph\n
- * APB1FZ DBG_RTC_STOP LL_DBGMCU_ABP1_GRP1_FreezePeriph\n
- * APB1FZ DBG_WWDG_STOP LL_DBGMCU_ABP1_GRP1_FreezePeriph\n
- * APB1FZ DBG_IWDG_STOP LL_DBGMCU_ABP1_GRP1_FreezePeriph\n
- * APB1FZ DBG_I2C1_STOP LL_DBGMCU_ABP1_GRP1_FreezePeriph\n
- * APB1FZ DBG_I2C2_STOP LL_DBGMCU_ABP1_GRP1_FreezePeriph\n
- * APB1FZ DBG_I2C3_STOP LL_DBGMCU_ABP1_GRP1_FreezePeriph\n
- * APB1FZ DBG_LPTIMER_STOP LL_DBGMCU_ABP1_GRP1_FreezePeriph
+ * @rmtoll APB1FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * APB1FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * APB1FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * APB1FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * APB1FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * APB1FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * APB1FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * APB1FZ DBG_I2C1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * APB1FZ DBG_I2C2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * APB1FZ DBG_I2C3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * APB1FZ DBG_LPTIMER_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
* @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_DBGMCU_ABP1_GRP1_TIM2_STOP
- * @arg @ref LL_DBGMCU_ABP1_GRP1_TIM3_STOP (*)
- * @arg @ref LL_DBGMCU_ABP1_GRP1_TIM6_STOP (*)
- * @arg @ref LL_DBGMCU_ABP1_GRP1_TIM7_STOP (*)
- * @arg @ref LL_DBGMCU_ABP1_GRP1_RTC_STOP
- * @arg @ref LL_DBGMCU_ABP1_GRP1_WWDG_STOP
- * @arg @ref LL_DBGMCU_ABP1_GRP1_IWDG_STOP
- * @arg @ref LL_DBGMCU_ABP1_GRP1_I2C1_STOP
- * @arg @ref LL_DBGMCU_ABP1_GRP1_I2C2_STOP (*)
- * @arg @ref LL_DBGMCU_ABP1_GRP1_I2C3_STOP (*)
- * @arg @ref LL_DBGMCU_ABP1_GRP1_LPTIM1_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
*
* (*) value not defined in all devices
* @retval None
*/
-__STATIC_INLINE void LL_DBGMCU_ABP1_GRP1_FreezePeriph(uint32_t Periphs)
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
{
SET_BIT(DBGMCU->APB1FZ, Periphs);
}
/**
* @brief Unfreeze APB1 peripherals (group1 peripherals)
- * @rmtoll APB1FZ DBG_TIM2_STOP LL_DBGMCU_ABP1_GRP1_UnFreezePeriph\n
- * APB1FZ DBG_TIM3_STOP LL_DBGMCU_ABP1_GRP1_UnFreezePeriph\n
- * APB1FZ DBG_TIM6_STOP LL_DBGMCU_ABP1_GRP1_UnFreezePeriph\n
- * APB1FZ DBG_TIM7_STOP LL_DBGMCU_ABP1_GRP1_UnFreezePeriph\n
- * APB1FZ DBG_RTC_STOP LL_DBGMCU_ABP1_GRP1_UnFreezePeriph\n
- * APB1FZ DBG_WWDG_STOP LL_DBGMCU_ABP1_GRP1_UnFreezePeriph\n
- * APB1FZ DBG_IWDG_STOP LL_DBGMCU_ABP1_GRP1_UnFreezePeriph\n
- * APB1FZ DBG_I2C1_STOP LL_DBGMCU_ABP1_GRP1_UnFreezePeriph\n
- * APB1FZ DBG_I2C2_STOP LL_DBGMCU_ABP1_GRP1_UnFreezePeriph\n
- * APB1FZ DBG_I2C3_STOP LL_DBGMCU_ABP1_GRP1_UnFreezePeriph\n
- * APB1FZ DBG_LPTIMER_STOP LL_DBGMCU_ABP1_GRP1_UnFreezePeriph
+ * @rmtoll APB1FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * APB1FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * APB1FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * APB1FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * APB1FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * APB1FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * APB1FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * APB1FZ DBG_I2C1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * APB1FZ DBG_I2C2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * APB1FZ DBG_I2C3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * APB1FZ DBG_LPTIMER_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
* @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_DBGMCU_ABP1_GRP1_TIM2_STOP
- * @arg @ref LL_DBGMCU_ABP1_GRP1_TIM3_STOP (*)
- * @arg @ref LL_DBGMCU_ABP1_GRP1_TIM6_STOP (*)
- * @arg @ref LL_DBGMCU_ABP1_GRP1_TIM7_STOP (*)
- * @arg @ref LL_DBGMCU_ABP1_GRP1_RTC_STOP
- * @arg @ref LL_DBGMCU_ABP1_GRP1_WWDG_STOP
- * @arg @ref LL_DBGMCU_ABP1_GRP1_IWDG_STOP
- * @arg @ref LL_DBGMCU_ABP1_GRP1_I2C1_STOP
- * @arg @ref LL_DBGMCU_ABP1_GRP1_I2C2_STOP (*)
- * @arg @ref LL_DBGMCU_ABP1_GRP1_I2C3_STOP (*)
- * @arg @ref LL_DBGMCU_ABP1_GRP1_LPTIM1_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
*
* (*) value not defined in all devices
* @retval None
*/
-__STATIC_INLINE void LL_DBGMCU_ABP1_GRP1_UnFreezePeriph(uint32_t Periphs)
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
{
CLEAR_BIT(DBGMCU->APB1FZ, Periphs);
}
/**
* @brief Freeze APB2 peripherals
- * @rmtoll APB2FZ DBG_TIM22_STOP LL_DBGMCU_ABP2_GRP1_FreezePeriph\n
- * APB2FZ DBG_TIM21_STOP LL_DBGMCU_ABP2_GRP1_FreezePeriph
+ * @rmtoll APB2FZ DBG_TIM22_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ * APB2FZ DBG_TIM21_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
* @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_DBGMCU_ABP2_GRP1_TIM22_STOP (*)
- * @arg @ref LL_DBGMCU_ABP2_GRP1_TIM21_STOP
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM22_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM21_STOP
*
* (*) value not defined in all devices
* @retval None
*/
-__STATIC_INLINE void LL_DBGMCU_ABP2_GRP1_FreezePeriph(uint32_t Periphs)
+__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
{
SET_BIT(DBGMCU->APB2FZ, Periphs);
}
/**
* @brief Unfreeze APB2 peripherals
- * @rmtoll APB2FZ DBG_TIM22_STOP LL_DBGMCU_ABP2_GRP1_UnFreezePeriph\n
- * APB2FZ DBG_TIM21_STOP LL_DBGMCU_ABP2_GRP1_UnFreezePeriph
+ * @rmtoll APB2FZ DBG_TIM22_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
+ * APB2FZ DBG_TIM21_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
* @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_DBGMCU_ABP2_GRP1_TIM22_STOP (*)
- * @arg @ref LL_DBGMCU_ABP2_GRP1_TIM21_STOP
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM22_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM21_STOP
*
* (*) value not defined in all devices
* @retval None
*/
-__STATIC_INLINE void LL_DBGMCU_ABP2_GRP1_UnFreezePeriph(uint32_t Periphs)
+__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
{
CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
}
