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Diff: TARGET_DISCO_L072CZ_LRWAN1/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_ll_i2c.h
- Revision:
- 167:84c0a372a020
- Parent:
- 143:86740a56073b
--- a/TARGET_DISCO_L072CZ_LRWAN1/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_ll_i2c.h Fri Apr 20 11:08:29 2018 +0100
+++ b/TARGET_DISCO_L072CZ_LRWAN1/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_ll_i2c.h Fri May 11 16:51:14 2018 +0100
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_ll_i2c.h
* @author MCD Application Team
- * @version V1.7.0
- * @date 31-May-2016
* @brief Header file of I2C LL module.
******************************************************************************
* @attention
@@ -63,16 +61,6 @@
/** @defgroup I2C_LL_Private_Constants I2C Private Constants
* @{
*/
-/* Defines used for the bit position in the register and perform offsets */
-#define I2C_POSITION_CR1_DNF (uint32_t)8U
-#define I2C_POSITION_CR2_NBYTES (uint32_t)16U
-#define I2C_POSITION_TIMINGR_PRESC (uint32_t)28U
-#define I2C_POSITION_TIMINGR_SCLDEL (uint32_t)20U
-#define I2C_POSITION_TIMINGR_SDADEL (uint32_t)16U
-#define I2C_POSITION_TIMINGR_SCLH (uint32_t)8U
-#define I2C_POSITION_TIMINGR_SCLL (uint32_t)0U
-#define I2C_POSITION_ISR_ADDCODE (uint32_t)17U
-#define I2C_POSITION_TIMEOUTR_TIMEOUTB (uint32_t)16U
/**
* @}
*/
@@ -198,9 +186,9 @@
/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
* @{
*/
-#define LL_I2C_MODE_I2C ((uint32_t)0x00000000U) /*!< I2C Master or Slave mode */
+#define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */
#define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */
-#define LL_I2C_MODE_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus Device default mode (Default address not acknowledge) */
+#define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode (Default address not acknowledge) */
#define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */
/**
* @}
@@ -209,7 +197,7 @@
/** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
* @{
*/
-#define LL_I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000U) /*!< Analog filter is enabled. */
+#define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. */
#define LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /*!< Analog filter is disabled. */
/**
* @}
@@ -218,7 +206,7 @@
/** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
* @{
*/
-#define LL_I2C_ADDRESSING_MODE_7BIT ((uint32_t) 0x00000000U) /*!< Master operates in 7-bit addressing mode. */
+#define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U /*!< Master operates in 7-bit addressing mode. */
#define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10 /*!< Master operates in 10-bit addressing mode.*/
/**
* @}
@@ -227,7 +215,7 @@
/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
* @{
*/
-#define LL_I2C_OWNADDRESS1_7BIT ((uint32_t)0x00000000U) /*!< Own address 1 is a 7-bit address. */
+#define LL_I2C_OWNADDRESS1_7BIT 0x00000000U /*!< Own address 1 is a 7-bit address. */
#define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE /*!< Own address 1 is a 10-bit address.*/
/**
* @}
@@ -251,7 +239,7 @@
/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
* @{
*/
-#define LL_I2C_ACK ((uint32_t) 0x00000000U) /*!< ACK is sent after current received byte. */
+#define LL_I2C_ACK 0x00000000U /*!< ACK is sent after current received byte. */
#define LL_I2C_NACK I2C_CR2_NACK /*!< NACK is sent after current received byte.*/
/**
* @}
@@ -260,7 +248,7 @@
/** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length
* @{
*/
-#define LL_I2C_ADDRSLAVE_7BIT ((uint32_t)0x00000000U) /*!< Slave Address in 7-bit. */
+#define LL_I2C_ADDRSLAVE_7BIT 0x00000000U /*!< Slave Address in 7-bit. */
#define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10 /*!< Slave Address in 10-bit.*/
/**
* @}
@@ -269,7 +257,7 @@
/** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction
* @{
*/
-#define LL_I2C_REQUEST_WRITE ((uint32_t)0x00000000U) /*!< Master request a write transfer. */
+#define LL_I2C_REQUEST_WRITE 0x00000000U /*!< Master request a write transfer. */
#define LL_I2C_REQUEST_READ I2C_CR2_RD_WRN /*!< Master request a read transfer. */
/**
* @}
@@ -280,7 +268,7 @@
*/
#define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /*!< Enable I2C Reload mode. */
#define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /*!< Enable I2C Automatic end mode with no HW PEC comparison. */
-#define LL_I2C_MODE_SOFTEND ((uint32_t)0x00000000U) /*!< Enable I2C Software end mode with no HW PEC comparison. */
+#define LL_I2C_MODE_SOFTEND 0x00000000U /*!< Enable I2C Software end mode with no HW PEC comparison. */
#define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode with HW PEC comparison. */
@@ -293,14 +281,14 @@
/** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
* @{
*/
-#define LL_I2C_GENERATE_NOSTARTSTOP ((uint32_t)0x00000000U) /*!< Don't Generate Stop and Start condition. */
-#define LL_I2C_GENERATE_STOP I2C_CR2_STOP /*!< Generate Stop condition (Size should be set to 0). */
-#define LL_I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Start for read request. */
-#define LL_I2C_GENERATE_START_WRITE I2C_CR2_START /*!< Generate Start for write request. */
-#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Restart for read request, slave 7Bit address. */
-#define LL_I2C_GENERATE_RESTART_7BIT_WRITE I2C_CR2_START /*!< Generate Restart for write request, slave 7Bit address. */
-#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */
-#define LL_I2C_GENERATE_RESTART_10BIT_WRITE I2C_CR2_START /*!< Generate Restart for write request, slave 10Bit address.*/
+#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U /*!< Don't Generate Stop and Start condition. */
+#define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) /*!< Generate Stop condition (Size should be set to 0). */
+#define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Start for read request. */
+#define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Start for write request. */
+#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Restart for read request, slave 7Bit address. */
+#define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Restart for write request, slave 7Bit address. */
+#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */
+#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Restart for write request, slave 10Bit address.*/
/**
* @}
*/
@@ -308,7 +296,7 @@
/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
* @{
*/
-#define LL_I2C_DIRECTION_WRITE ((uint32_t)0x00000000U) /*!< Write transfer request by master, slave enters receiver mode. */
+#define LL_I2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master, slave enters receiver mode. */
#define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by master, slave enters transmitter mode.*/
/**
* @}
@@ -317,8 +305,8 @@
/** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data
* @{
*/
-#define LL_I2C_DMA_REG_DATA_TRANSMIT ((uint32_t)0x00000000U) /*!< Get address of data register used for transmission */
-#define LL_I2C_DMA_REG_DATA_RECEIVE ((uint32_t)0x00000001U) /*!< Get address of data register used for reception */
+#define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */
+#define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */
/**
* @}
*/
@@ -326,7 +314,7 @@
/** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
* @{
*/
-#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW ((uint32_t) 0x00000000U) /*!< TimeoutA is used to detect SCL low level timeout. */
+#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect SCL low level timeout. */
#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect both SCL and SDA high level timeout.*/
/**
* @}
@@ -380,19 +368,19 @@
*/
/**
* @brief Configure the SDA setup, hold time and the SCL high, low period.
- * @param __PRESCALER__ This parameter must be a value between 0 and 0xF.
- * @param __DATA_SETUP_TIME__ This parameter must be a value between 0 and 0xF. (tscldel = (SCLDEL+1)xtpresc)
- * @param __DATA_HOLD_TIME__ This parameter must be a value between 0 and 0xF. (tsdadel = SDADELxtpresc)
- * @param __CLOCK_HIGH_PERIOD__ This parameter must be a value between 0 and 0xFF. (tsclh = (SCLH+1)xtpresc)
- * @param __CLOCK_LOW_PERIOD__ This parameter must be a value between 0 and 0xFF. (tscll = (SCLL+1)xtpresc)
- * @retval Value between 0 and 0xFFFFFFFF
+ * @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
+ * @param __DATA_SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tscldel = (SCLDEL+1)xtpresc)
+ * @param __DATA_HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tsdadel = SDADELxtpresc)
+ * @param __CLOCK_HIGH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tsclh = (SCLH+1)xtpresc)
+ * @param __CLOCK_LOW_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tscll = (SCLL+1)xtpresc)
+ * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
*/
#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__) \
- ((((uint32_t)(__PRESCALER__) << I2C_POSITION_TIMINGR_PRESC) & I2C_TIMINGR_PRESC) | \
- (((uint32_t)(__DATA_SETUP_TIME__) << I2C_POSITION_TIMINGR_SCLDEL) & I2C_TIMINGR_SCLDEL) | \
- (((uint32_t)(__DATA_HOLD_TIME__) << I2C_POSITION_TIMINGR_SDADEL) & I2C_TIMINGR_SDADEL) | \
- (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_POSITION_TIMINGR_SCLH) & I2C_TIMINGR_SCLH) | \
- (((uint32_t)(__CLOCK_LOW_PERIOD__) << I2C_POSITION_TIMINGR_SCLL) & I2C_TIMINGR_SCLL))
+ ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \
+ (((uint32_t)(__DATA_SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \
+ (((uint32_t)(__DATA_HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \
+ (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \
+ (((uint32_t)(__CLOCK_LOW_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL))
/**
* @}
*/
@@ -456,14 +444,14 @@
* @param AnalogFilter This parameter can be one of the following values:
* @arg @ref LL_I2C_ANALOGFILTER_ENABLE
* @arg @ref LL_I2C_ANALOGFILTER_DISABLE
- * @param DigitalFilter This parameter must be a value between 0x00 (Digital filter disabled) and 0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
+ * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
* This parameter is used to configure the digital noise filter on SDA and SCL input.
* The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
* @retval None
*/
__STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
{
- MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_POSITION_CR1_DNF));
+ MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos));
}
/**
@@ -472,14 +460,14 @@
* This filter can only be programmed when the I2C is disabled (PE = 0).
* @rmtoll CR1 DNF LL_I2C_SetDigitalFilter
* @param I2Cx I2C Instance.
- * @param DigitalFilter This parameter must be a value between 0x00 (Digital filter disabled) and 0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
+ * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
* This parameter is used to configure the digital noise filter on SDA and SCL input.
* The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
* @retval None
*/
__STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
{
- MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_POSITION_CR1_DNF);
+ MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos);
}
/**
@@ -490,7 +478,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
{
- return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_POSITION_CR1_DNF);
+ return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);
}
/**
@@ -798,7 +786,7 @@
* @rmtoll OAR1 OA1 LL_I2C_SetOwnAddress1\n
* OAR1 OA1MODE LL_I2C_SetOwnAddress1
* @param I2Cx I2C Instance.
- * @param OwnAddress1 This parameter must be a value between 0 and 0x3FF.
+ * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
* @param OwnAddrSize This parameter can be one of the following values:
* @arg @ref LL_I2C_OWNADDRESS1_7BIT
* @arg @ref LL_I2C_OWNADDRESS1_10BIT
@@ -848,7 +836,7 @@
* @rmtoll OAR2 OA2 LL_I2C_SetOwnAddress2\n
* OAR2 OA2MSK LL_I2C_SetOwnAddress2
* @param I2Cx I2C Instance.
- * @param OwnAddress2 Value between 0 and 0x7F.
+ * @param OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F.
* @param OwnAddrMask This parameter can be one of the following values:
* @arg @ref LL_I2C_OWNADDRESS2_NOMASK
* @arg @ref LL_I2C_OWNADDRESS2_MASK01
@@ -903,7 +891,7 @@
* @note This bit can only be programmed when the I2C is disabled (PE = 0).
* @rmtoll TIMINGR TIMINGR LL_I2C_SetTiming
* @param I2Cx I2C Instance.
- * @param Timing This parameter must be a value between 0 and 0xFFFFFFFF.
+ * @param Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
* @note This parameter is computed with the STM32CubeMX Tool.
* @retval None
*/
@@ -920,7 +908,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
{
- return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_POSITION_TIMINGR_PRESC);
+ return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);
}
/**
@@ -931,7 +919,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
{
- return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_POSITION_TIMINGR_SCLL);
+ return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);
}
/**
@@ -942,7 +930,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
{
- return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_POSITION_TIMINGR_SCLH);
+ return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);
}
/**
@@ -953,7 +941,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
{
- return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_POSITION_TIMINGR_SDADEL);
+ return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);
}
/**
@@ -964,7 +952,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx)
{
- return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_POSITION_TIMINGR_SCLDEL);
+ return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);
}
/**
@@ -1106,14 +1094,13 @@
* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
* @param TimeoutB
- * @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
* @retval None
*/
__STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,
- uint32_t TimeoutB)
+ uint32_t TimeoutB)
{
MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB,
- TimeoutA | TimeoutAMode | (TimeoutB << I2C_POSITION_TIMEOUTR_TIMEOUTB));
+ TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos));
}
/**
@@ -1188,7 +1175,7 @@
*/
__STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB)
{
- WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_POSITION_TIMEOUTR_TIMEOUTB);
+ WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos);
}
/**
@@ -1201,7 +1188,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx)
{
- return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_POSITION_TIMEOUTR_TIMEOUTB);
+ return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos);
}
/**
@@ -1472,6 +1459,8 @@
/**
* @brief Enable Error interrupts.
+ * @note Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
* @note Any of these errors will generate interrupt :
* Arbitration Loss (ARLO)
* Bus Error detection (BERR)
@@ -1479,8 +1468,6 @@
* SMBus Timeout detection (TIMEOUT)
* SMBus PEC error detection (PECERR)
* SMBus Alert pin event detection (ALERT)
- * @note Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR1 ERRIE LL_I2C_EnableIT_ERR
* @param I2Cx I2C Instance.
* @retval None
@@ -1492,6 +1479,8 @@
/**
* @brief Disable Error interrupts.
+ * @note Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
* @note Any of these errors will generate interrupt :
* Arbitration Loss (ARLO)
* Bus Error detection (BERR)
@@ -1499,8 +1488,6 @@
* SMBus Timeout detection (TIMEOUT)
* SMBus PEC error detection (PECERR)
* SMBus Alert pin event detection (ALERT)
- * @note Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR1 ERRIE LL_I2C_DisableIT_ERR
* @param I2Cx I2C Instance.
* @retval None
@@ -1511,7 +1498,7 @@
}
/**
- * @brief Check if Error interrupts is enabled of disabled.
+ * @brief Check if Error interrupts are enabled or disabled.
* @rmtoll CR1 ERRIE LL_I2C_IsEnabledIT_ERR
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
@@ -1673,6 +1660,52 @@
}
/**
+ * @brief Indicate the status of SMBus PEC error flag in reception.
+ * @note Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note RESET: Clear default value.
+ * SET: When the received PEC does not match with the PEC register content.
+ * @rmtoll ISR PECERR LL_I2C_IsActiveSMBusFlag_PECERR
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR));
+}
+
+/**
+ * @brief Indicate the status of SMBus Timeout detection flag.
+ * @note Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note RESET: Clear default value.
+ * SET: When a timeout or extended clock timeout occurs.
+ * @rmtoll ISR TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT));
+}
+
+/**
+ * @brief Indicate the status of SMBus alert flag.
+ * @note Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note RESET: Clear default value.
+ * SET: When SMBus host configuration, SMBus alert enabled and
+ * a falling edge event occurs on SMBA pin.
+ * @rmtoll ISR ALERT LL_I2C_IsActiveSMBusFlag_ALERT
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT));
+}
+
+/**
* @brief Indicate the status of Bus Busy flag.
* @note RESET: Clear default value.
* SET: When a Start condition is detected.
@@ -1764,52 +1797,6 @@
}
/**
- * @brief Indicate the status of SMBus PEC error flag in reception.
- * @note Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @note RESET: Clear default value.
- * SET: When the received PEC does not match with the PEC register content.
- * @rmtoll ISR PECERR LL_I2C_IsActiveSMBusFlag_PECERR
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR));
-}
-
-/**
- * @brief Indicate the status of SMBus Timeout detection flag.
- * @note Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @note RESET: Clear default value.
- * SET: When a timeout or extended clock timeout occurs.
- * @rmtoll ISR TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT));
-}
-
-/**
- * @brief Indicate the status of SMBus alert flag.
- * @note Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @note RESET: Clear default value.
- * SET: When SMBus host configuration, SMBus alert enabled and
- * a falling edge event occurs on SMBA pin.
- * @rmtoll ISR ALERT LL_I2C_IsActiveSMBusFlag_ALERT
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT));
-}
-
-/**
* @brief Clear SMBus PEC error flag.
* @note Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
@@ -1937,7 +1924,7 @@
*/
__STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize)
{
- MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_POSITION_CR2_NBYTES);
+ MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos);
}
/**
@@ -1948,7 +1935,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx)
{
- return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_POSITION_CR2_NBYTES);
+ return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);
}
/**
@@ -1967,17 +1954,6 @@
}
/**
- * @brief Generate a STOP condition after the current byte transfer (master mode).
- * @rmtoll CR2 STOP LL_I2C_GenerateStopCondition
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR2, I2C_CR2_STOP);
-}
-
-/**
* @brief Generate a START or RESTART condition
* @note The START bit can be set even if bus is BUSY or I2C is in slave mode.
* This action has no effect when RELOAD is set.
@@ -1991,6 +1967,17 @@
}
/**
+ * @brief Generate a STOP condition after the current byte transfer (master mode).
+ * @rmtoll CR2 STOP LL_I2C_GenerateStopCondition
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR2, I2C_CR2_STOP);
+}
+
+/**
* @brief Enable automatic RESTART Read request condition for 10bit address header (master mode).
* @note The master sends the complete 10bit slave address read sequence :
* Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address in Read direction.
@@ -2095,7 +2082,7 @@
* @arg @ref LL_I2C_ADDRSLAVE_7BIT
* @arg @ref LL_I2C_ADDRSLAVE_10BIT
* @param TransferSize Specifies the number of bytes to be programmed.
- * This parameter must be a value between 0 and 255.
+ * This parameter must be a value between Min_Data=0 and Max_Data=255.
* @param EndMode This parameter can be one of the following values:
* @arg @ref LL_I2C_MODE_RELOAD
* @arg @ref LL_I2C_MODE_AUTOEND
@@ -2117,11 +2104,11 @@
* @retval None
*/
__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
- uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
+ uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
{
- MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
+ MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
- SlaveAddr | SlaveAddrSize | TransferSize << I2C_POSITION_CR2_NBYTES | EndMode | Request);
+ SlaveAddr | SlaveAddrSize | TransferSize << I2C_CR2_NBYTES_Pos | EndMode | Request);
}
/**
@@ -2147,11 +2134,11 @@
*/
__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx)
{
- return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_POSITION_ISR_ADDCODE << 1);
+ return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);
}
/**
- * @brief Enable internal comparison of Packet Error byte (transmission or reception mode).
+ * @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
* @note Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received.
@@ -2167,7 +2154,7 @@
}
/**
- * @brief Check if Packet Error byte internal comparison is requested or not.
+ * @brief Check if the SMBus Packet Error byte internal comparison is requested or not.
* @note Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare
@@ -2180,7 +2167,7 @@
}
/**
- * @brief Get the Packet Error byte calculated.
+ * @brief Get the SMBus Packet Error byte calculated.
* @note Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll PECR PEC LL_I2C_GetSMBusPEC
