Diff: TARGET_WIO_3G/TOOLCHAIN_ARM_MICRO/stm32f439xx.sct

Revision:

172:65be27845400

Parent:

171:3a7713b1edbc

--- a/TARGET_WIO_3G/TOOLCHAIN_ARM_MICRO/stm32f439xx.sct	Thu Nov 08 11:45:42 2018 +0000
+++ b/TARGET_WIO_3G/TOOLCHAIN_ARM_MICRO/stm32f439xx.sct	Wed Feb 20 20:53:29 2019 +0000
@@ -36,6 +36,15 @@
   #define MBED_APP_SIZE 0x200000
 #endif
 
+#define MBED_RAM_START              0x20000000
+#define MBED_RAM_SIZE               0x30000
+#define MBED_VECTTABLE_RAM_START    (MBED_RAM_START)
+#define MBED_VECTTABLE_RAM_SIZE     0x1B0
+#define MBED_CRASH_REPORT_RAM_START (MBED_VECTTABLE_RAM_START + MBED_VECTTABLE_RAM_SIZE)
+#define MBED_CRASH_REPORT_RAM_SIZE  0x100
+#define MBED_RAM0_START             (MBED_CRASH_REPORT_RAM_START + MBED_CRASH_REPORT_RAM_SIZE)
+#define MBED_RAM0_SIZE              (MBED_RAM_SIZE - MBED_VECTTABLE_RAM_SIZE - MBED_CRASH_REPORT_RAM_SIZE)
+
 ; STM32F439xI: 2048 KB FLASH (0x200000) + 256 KB SRAM (0x30000 + 0x10000)
 LR_IROM1 MBED_APP_START MBED_APP_SIZE  {    ; load region size_region
 
@@ -44,10 +53,13 @@
    *(InRoot$$Sections)
    .ANY (+RO)
   }
+  
+  RW_m_crash_data MBED_CRASH_REPORT_RAM_START EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data
+  }
 
   ; Total: 107 vectors = 428 bytes (0x1AC) 8-byte aligned = 0x1B0 (0x1AC + 0x4) to be used
   ; should match ER_IROM1::RESET/4 and cmsis_nvic.h::NVIC_NUM_VECTORS
-  RW_IRAM1 (0x20000000 + 0x1B0) (0x30000 - 0x1B0)  {  ; RW data
+  RW_IRAM1 (MBED_RAM0_START) (MBED_RAM0_SIZE)  {  ; RW data
    .ANY (+RW +ZI)
   }
   RW_IRAM2 (0x10000000) 0x10000 {