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Diff: TARGET_NUCLEO_L432KC/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h
- Revision:
- 145:64910690c574
- Parent:
- 128:9bcdf88f62b0
--- a/TARGET_NUCLEO_L432KC/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h Thu Jun 08 14:53:05 2017 +0100 +++ b/TARGET_NUCLEO_L432KC/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h Wed Jun 21 17:31:38 2017 +0100 @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l4xx_hal_dfsdm.h * @author MCD Application Team - * @version V1.5.1 - * @date 31-May-2016 + * @version V1.7.1 + * @date 21-April-2017 * @brief Header file of DFSDM HAL module. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -43,7 +43,9 @@ extern "C" { #endif -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) +#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ + defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ + defined(STM32L496xx) || defined(STM32L4A6xx) /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" @@ -87,7 +89,9 @@ */ typedef struct { - uint32_t Multiplexer; /*!< Input is external serial inputs or internal register. + uint32_t Multiplexer; /*!< Input is external serial inputs, internal register or ADC output. + ADC output is available only on STM32L451xx, STM32L452xx, STM32L462xx, + STM32L496xx, STM32L4A6xx products. This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */ uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register. This parameter can be a value of @ref DFSDM_Channel_DataPacking */ @@ -266,6 +270,10 @@ * @{ */ #define DFSDM_CHANNEL_EXTERNAL_INPUTS ((uint32_t)0x00000000U) /*!< Data are taken from external inputs */ +#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ + defined(STM32L496xx) || defined(STM32L4A6xx) +#define DFSDM_CHANNEL_ADC_OUTPUT DFSDM_CHCFGR1_DATMPX_0 /*!< Data are taken from ADC output */ +#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx */ #define DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1 /*!< Data are taken from internal register */ /** * @} @@ -336,6 +344,15 @@ /** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger * @{ */ +#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) +#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000U) /*!< For DFSDM filter 0, 1, 2 and 3 */ +#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For DFSDM filter 0, 1, 2 and 3 */ +#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For DFSDM filter 0, 1, 2 and 3 */ +#define DFSDM_FILTER_EXT_TRIG_TIM16_OC1 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 0, 1 and 2 */ +#define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0 and 1 */ +#define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */ +#define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL /*!< For DFSDM filter 0, 1, 2 and 3 */ +#else #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000U) /*!< For DFSDM filter 0, 1, 2 and 3 */ #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For DFSDM filter 0, 1, 2 and 3 */ #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For DFSDM filter 0, 1, 2 and 3 */ @@ -347,6 +364,7 @@ #define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 2 and 3 */ #define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */ #define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL /*!< For DFSDM filter 0, 1, 2 and 3 */ +#endif /* STM32L451xx || STM32L452xx || STM32L462xx */ /** * @} */ @@ -417,6 +435,12 @@ - the channel mask is 0x00000020 (bit 5 is set) - the channel number 5 is 0x00050000 --> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */ +#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) +#define DFSDM_CHANNEL_0 ((uint32_t)0x00000001U) +#define DFSDM_CHANNEL_1 ((uint32_t)0x00010002U) +#define DFSDM_CHANNEL_2 ((uint32_t)0x00020004U) +#define DFSDM_CHANNEL_3 ((uint32_t)0x00030008U) +#else /* STM32L451xx || STM32L452xx || STM32L462xx */ #define DFSDM_CHANNEL_0 ((uint32_t)0x00000001U) #define DFSDM_CHANNEL_1 ((uint32_t)0x00010002U) #define DFSDM_CHANNEL_2 ((uint32_t)0x00020004U) @@ -425,6 +449,7 @@ #define DFSDM_CHANNEL_5 ((uint32_t)0x00050020U) #define DFSDM_CHANNEL_6 ((uint32_t)0x00060040U) #define DFSDM_CHANNEL_7 ((uint32_t)0x00070080U) +#endif /* STM32L451xx || STM32L452xx || STM32L462xx */ /** * @} */ @@ -618,8 +643,15 @@ #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK) (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \ ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO)) #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2 <= (DIVIDER)) && ((DIVIDER) <= 256)) +#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ + defined(STM32L496xx) || defined(STM32L4A6xx) +#define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \ + ((INPUT) == DFSDM_CHANNEL_ADC_OUTPUT) || \ + ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER)) +#else #define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \ ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER)) +#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx */ #define IS_DFSDM_CHANNEL_DATA_PACKING(MODE) (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \ ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \ ((MODE) == DFSDM_CHANNEL_DUAL_MODE)) @@ -646,6 +678,15 @@ #define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \ ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \ ((TRIG) == DFSDM_FILTER_EXT_TRIGGER)) +#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) +#define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \ + ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \ + ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \ + ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \ + ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \ + ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \ + ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15)) +#else #define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \ ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \ ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \ @@ -657,6 +698,7 @@ ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \ ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \ ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15)) +#endif /* STM32L451xx || STM32L452xx || STM32L462xx */ #define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE) (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE) || \ ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE) || \ ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES)) @@ -672,6 +714,13 @@ ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA)) #define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607)) #define IS_DFSDM_BREAK_SIGNALS(VALUE) ((VALUE) <= 0xFU) +#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) +#define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \ + ((CHANNEL) == DFSDM_CHANNEL_1) || \ + ((CHANNEL) == DFSDM_CHANNEL_2) || \ + ((CHANNEL) == DFSDM_CHANNEL_3)) +#define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) <= 0x0003000FU)) +#else /* STM32L451xx || STM32L452xx || STM32L462xx */ #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \ ((CHANNEL) == DFSDM_CHANNEL_1) || \ ((CHANNEL) == DFSDM_CHANNEL_2) || \ @@ -681,6 +730,7 @@ ((CHANNEL) == DFSDM_CHANNEL_6) || \ ((CHANNEL) == DFSDM_CHANNEL_7)) #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) <= 0x000F00FFU)) +#endif /* STM32L451xx || STM32L452xx || STM32L462xx */ #define IS_DFSDM_CONTINUOUS_MODE(MODE) (((MODE) == DFSDM_CONTINUOUS_CONV_OFF) || \ ((MODE) == DFSDM_CONTINUOUS_CONV_ON)) /** @@ -695,7 +745,7 @@ /** * @} */ -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ +#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ #ifdef __cplusplus } #endif