Diff: TARGET_NUCLEO_F446ZE/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_spi.h

Revision:

145:64910690c574

Parent:

128:9bcdf88f62b0

--- a/TARGET_NUCLEO_F446ZE/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_spi.h	Thu Jun 08 14:53:05 2017 +0100
+++ b/TARGET_NUCLEO_F446ZE/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_spi.h	Wed Jun 21 17:31:38 2017 +0100
@@ -2,13 +2,13 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_spi.h
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    06-May-2016
+  * @version V1.7.1
+  * @date    14-April-2017
   * @brief   Header file of SPI HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -165,13 +165,13 @@
 /** @defgroup SPI_Error_Code SPI Error Code
   * @{
   */
-#define HAL_SPI_ERROR_NONE              ((uint32_t)0x00000000U)   /*!< No error             */
-#define HAL_SPI_ERROR_MODF              ((uint32_t)0x00000001U)   /*!< MODF error           */
-#define HAL_SPI_ERROR_CRC               ((uint32_t)0x00000002U)   /*!< CRC error            */
-#define HAL_SPI_ERROR_OVR               ((uint32_t)0x00000004U)   /*!< OVR error            */
-#define HAL_SPI_ERROR_FRE               ((uint32_t)0x00000008U)   /*!< FRE error            */
-#define HAL_SPI_ERROR_DMA               ((uint32_t)0x00000010U)   /*!< DMA transfer error   */
-#define HAL_SPI_ERROR_FLAG              ((uint32_t)0x00000020U)   /*!< Flag: RXNE,TXE, BSY  */
+#define HAL_SPI_ERROR_NONE              0x00000000U   /*!< No error             */
+#define HAL_SPI_ERROR_MODF              0x00000001U   /*!< MODF error           */
+#define HAL_SPI_ERROR_CRC               0x00000002U   /*!< CRC error            */
+#define HAL_SPI_ERROR_OVR               0x00000004U   /*!< OVR error            */
+#define HAL_SPI_ERROR_FRE               0x00000008U   /*!< FRE error            */
+#define HAL_SPI_ERROR_DMA               0x00000010U   /*!< DMA transfer error   */
+#define HAL_SPI_ERROR_FLAG              0x00000020U   /*!< Flag: RXNE,TXE, BSY  */
 /**
   * @}
   */
@@ -179,7 +179,7 @@
 /** @defgroup SPI_Mode SPI Mode
   * @{
   */
-#define SPI_MODE_SLAVE                  ((uint32_t)0x00000000U)
+#define SPI_MODE_SLAVE                  0x00000000U
 #define SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)
 /**
   * @}
@@ -188,7 +188,7 @@
 /** @defgroup SPI_Direction SPI Direction Mode
   * @{
   */
-#define SPI_DIRECTION_2LINES            ((uint32_t)0x00000000U)
+#define SPI_DIRECTION_2LINES            0x00000000U
 #define SPI_DIRECTION_2LINES_RXONLY     SPI_CR1_RXONLY
 #define SPI_DIRECTION_1LINE             SPI_CR1_BIDIMODE
 /**
@@ -198,7 +198,7 @@
 /** @defgroup SPI_Data_Size SPI Data Size
   * @{
   */
-#define SPI_DATASIZE_8BIT               ((uint32_t)0x00000000U)
+#define SPI_DATASIZE_8BIT               0x00000000U
 #define SPI_DATASIZE_16BIT              SPI_CR1_DFF
 /**
   * @}
@@ -207,7 +207,7 @@
 /** @defgroup SPI_Clock_Polarity SPI Clock Polarity
   * @{
   */
-#define SPI_POLARITY_LOW                ((uint32_t)0x00000000U)
+#define SPI_POLARITY_LOW                0x00000000U
 #define SPI_POLARITY_HIGH               SPI_CR1_CPOL
 /**
   * @}
@@ -216,7 +216,7 @@
 /** @defgroup SPI_Clock_Phase SPI Clock Phase
   * @{
   */
-#define SPI_PHASE_1EDGE                 ((uint32_t)0x00000000U)
+#define SPI_PHASE_1EDGE                 0x00000000U
 #define SPI_PHASE_2EDGE                 SPI_CR1_CPHA
 /**
   * @}
@@ -226,8 +226,8 @@
   * @{
   */
 #define SPI_NSS_SOFT                    SPI_CR1_SSM
-#define SPI_NSS_HARD_INPUT              ((uint32_t)0x00000000U)
-#define SPI_NSS_HARD_OUTPUT             ((uint32_t)0x00040000U)
+#define SPI_NSS_HARD_INPUT              0x00000000U
+#define SPI_NSS_HARD_OUTPUT             0x00040000U
 /**
   * @}
   */
@@ -235,14 +235,14 @@
 /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
   * @{
   */
-#define SPI_BAUDRATEPRESCALER_2         ((uint32_t)0x00000000U)
-#define SPI_BAUDRATEPRESCALER_4         ((uint32_t)0x00000008U)
-#define SPI_BAUDRATEPRESCALER_8         ((uint32_t)0x00000010U)
-#define SPI_BAUDRATEPRESCALER_16        ((uint32_t)0x00000018U)
-#define SPI_BAUDRATEPRESCALER_32        ((uint32_t)0x00000020U)
-#define SPI_BAUDRATEPRESCALER_64        ((uint32_t)0x00000028U)
-#define SPI_BAUDRATEPRESCALER_128       ((uint32_t)0x00000030U)
-#define SPI_BAUDRATEPRESCALER_256       ((uint32_t)0x00000038U)
+#define SPI_BAUDRATEPRESCALER_2         0x00000000U
+#define SPI_BAUDRATEPRESCALER_4         0x00000008U
+#define SPI_BAUDRATEPRESCALER_8         0x00000010U
+#define SPI_BAUDRATEPRESCALER_16        0x00000018U
+#define SPI_BAUDRATEPRESCALER_32        0x00000020U
+#define SPI_BAUDRATEPRESCALER_64        0x00000028U
+#define SPI_BAUDRATEPRESCALER_128       0x00000030U
+#define SPI_BAUDRATEPRESCALER_256       0x00000038U
 /**
   * @}
   */
@@ -250,7 +250,7 @@
 /** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
   * @{
   */
-#define SPI_FIRSTBIT_MSB                ((uint32_t)0x00000000U)
+#define SPI_FIRSTBIT_MSB                0x00000000U
 #define SPI_FIRSTBIT_LSB                SPI_CR1_LSBFIRST
 /**
   * @}
@@ -259,7 +259,7 @@
 /** @defgroup SPI_TI_mode SPI TI Mode
   * @{
   */
-#define SPI_TIMODE_DISABLE             ((uint32_t)0x00000000U)
+#define SPI_TIMODE_DISABLE             0x00000000U
 #define SPI_TIMODE_ENABLE              SPI_CR2_FRF
 /**
   * @}
@@ -268,7 +268,7 @@
 /** @defgroup SPI_CRC_Calculation SPI CRC Calculation
   * @{
   */
-#define SPI_CRCCALCULATION_DISABLE     ((uint32_t)0x00000000U)
+#define SPI_CRCCALCULATION_DISABLE     0x00000000U
 #define SPI_CRCCALCULATION_ENABLE      SPI_CR1_CRCEN
 /**
   * @}
@@ -373,7 +373,7 @@
     tmpreg_modf = (__HANDLE__)->Instance->SR;      \
     (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
     UNUSED(tmpreg_modf);                           \
-  } while(0)
+  } while(0U)
 
 /** @brief  Clear the SPI OVR pending flag.
   * @param  __HANDLE__: specifies the SPI Handle.
@@ -386,7 +386,7 @@
     tmpreg_ovr = (__HANDLE__)->Instance->DR;       \
     tmpreg_ovr = (__HANDLE__)->Instance->SR;       \
     UNUSED(tmpreg_ovr);                            \
-  } while(0)
+  } while(0U)
 
 /** @brief  Clear the SPI FRE pending flag.
   * @param  __HANDLE__: specifies the SPI Handle.
@@ -398,7 +398,7 @@
   __IO uint32_t tmpreg_fre = 0x00U;                \
   tmpreg_fre = (__HANDLE__)->Instance->SR;         \
   UNUSED(tmpreg_fre);                              \
-  }while(0)
+  }while(0U)
 
 /** @brief  Enable the SPI peripheral.
   * @param  __HANDLE__: specifies the SPI Handle.
@@ -450,6 +450,9 @@
 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
 
 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
@@ -459,6 +462,7 @@
 void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
 void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
 void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
 /**
   * @}
   */
@@ -506,7 +510,7 @@
   * @retval None
   */
 #define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\
-                                     (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)
+                                     (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0U)
 
 #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
                            ((MODE) == SPI_MODE_MASTER))