Diff: TARGET_NUCLEO_L496ZG_P/TOOLCHAIN_ARM_MICRO/stm32l496xx.sct

Revision:

171:3a7713b1edbc

Parent:

170:e95d10626187

--- a/TARGET_NUCLEO_L496ZG_P/TOOLCHAIN_ARM_MICRO/stm32l496xx.sct	Thu Sep 06 13:39:34 2018 +0100
+++ b/TARGET_NUCLEO_L496ZG_P/TOOLCHAIN_ARM_MICRO/stm32l496xx.sct	Thu Nov 08 11:45:42 2018 +0000
@@ -1,3 +1,4 @@
+#! armcc -E
 ; Scatter-Loading Description File
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ; Copyright (c) 2018, STMicroelectronics
@@ -27,17 +28,25 @@
 ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE 0x100000
+#endif
+
 ; 1MB FLASH (0x100000) + 320KB SRAM (0x50000)
-LR_IROM1 0x08000000 0x100000  {    ; load region size_region
+LR_IROM1 MBED_APP_START MBED_APP_SIZE  {    ; load region size_region
 
-  ER_IROM1 0x08000000 0x100000  {  ; load address = execution address
+  ER_IROM1 MBED_APP_START MBED_APP_SIZE  {  ; load address = execution address
    *.o (RESET, +First)
    *(InRoot$$Sections)
    .ANY (+RO)
   }
 
-  ; Total: 107 vectors = 428 bytes (0x1AC) to be reserved in RAM
-  RW_IRAM1 (0x20000000+0x1AC) (0x50000-0x1AC)  { ; RW data 320k L4-SRAM1
+  ; Total: 107 vectors = 428 bytes (0x1AC) 8-byte aligned = 0x1B0 (0x1AC + 0x4) to be reserved in RAM
+  RW_IRAM1 (0x20000000+0x1B0) (0x50000-0x1B0)  { ; RW data 320k L4-SRAM1
    .ANY (+RW +ZI)
   }
 }