Diff: TARGET_NUCLEO_F207ZG/TOOLCHAIN_ARM_STD/stm32f207xx.sct

Revision:

171:3a7713b1edbc

Parent:

123:b0220dba8be7

--- a/TARGET_NUCLEO_F207ZG/TOOLCHAIN_ARM_STD/stm32f207xx.sct	Thu Sep 06 13:39:34 2018 +0100
+++ b/TARGET_NUCLEO_F207ZG/TOOLCHAIN_ARM_STD/stm32f207xx.sct	Thu Nov 08 11:45:42 2018 +0000
@@ -1,3 +1,4 @@
+#! armcc -E
 ; Scatter-Loading Description File
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ; Copyright (c) 2016, STMicroelectronics
@@ -27,15 +28,23 @@
 ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
-LR_IROM1 0x08000000 0x00100000  {    ; load region size_region
-  ER_IROM1 0x08000000 0x00100000  {  ; load address = execution address
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE 0x100000
+#endif
+
+LR_IROM1 MBED_APP_START MBED_APP_SIZE  {    ; load region size_region
+  ER_IROM1 MBED_APP_START MBED_APP_SIZE  {  ; load address = execution address
    *.o (RESET, +First)
    *(InRoot$$Sections)
    .ANY (+RO)
   }
 
-  ; 97 vectors * 4 bytes = 388 bytes to reserve (0x184)
-  RW_IRAM1 (0x20000000+0x184) (0x00020000-0x184)  {  ; RW data
+  ; 97 vectors * 4 bytes = 388 bytes to reserve (0x184) 8-byte aligned = 0x188 (0x184 + 0x4)
+  RW_IRAM1 (0x20000000+0x188) (0x00020000-0x188)  {  ; RW data
    .ANY (+RW +ZI)
   }
 }