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TARGET_NUCLEO_L432KC/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_spi.h@156:ff21514d8981, 2017-11-08 (annotated)

Committer:: AnnaBridge
Date:: Wed Nov 08 17:18:06 2017 +0000
Revision:: 156:ff21514d8981
Child:: 161:aa5281ff4a02

Reverting back to release 154 of the mbed library

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	156:ff21514d8981	1	/**
AnnaBridge	156:ff21514d8981	2	******************************************************************************
AnnaBridge	156:ff21514d8981	3	* @file stm32l4xx_ll_spi.h
AnnaBridge	156:ff21514d8981	4	* @author MCD Application Team
AnnaBridge	156:ff21514d8981	5	* @version V1.7.1
AnnaBridge	156:ff21514d8981	6	* @date 21-April-2017
AnnaBridge	156:ff21514d8981	7	* @brief Header file of SPI LL module.
AnnaBridge	156:ff21514d8981	8	******************************************************************************
AnnaBridge	156:ff21514d8981	9	* @attention
AnnaBridge	156:ff21514d8981	10	*
AnnaBridge	156:ff21514d8981	11	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	156:ff21514d8981	12	*
AnnaBridge	156:ff21514d8981	13	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	156:ff21514d8981	14	* are permitted provided that the following conditions are met:
AnnaBridge	156:ff21514d8981	15	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	156:ff21514d8981	16	* this list of conditions and the following disclaimer.
AnnaBridge	156:ff21514d8981	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	156:ff21514d8981	18	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	156:ff21514d8981	19	* and/or other materials provided with the distribution.
AnnaBridge	156:ff21514d8981	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	156:ff21514d8981	21	* may be used to endorse or promote products derived from this software
AnnaBridge	156:ff21514d8981	22	* without specific prior written permission.
AnnaBridge	156:ff21514d8981	23	*
AnnaBridge	156:ff21514d8981	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	156:ff21514d8981	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	156:ff21514d8981	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	156:ff21514d8981	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	156:ff21514d8981	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	156:ff21514d8981	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	156:ff21514d8981	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	156:ff21514d8981	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	156:ff21514d8981	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	156:ff21514d8981	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	156:ff21514d8981	34	*
AnnaBridge	156:ff21514d8981	35	******************************************************************************
AnnaBridge	156:ff21514d8981	36	*/
AnnaBridge	156:ff21514d8981	37
AnnaBridge	156:ff21514d8981	38	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	156:ff21514d8981	39	#ifndef __STM32L4xx_LL_SPI_H
AnnaBridge	156:ff21514d8981	40	#define __STM32L4xx_LL_SPI_H
AnnaBridge	156:ff21514d8981	41
AnnaBridge	156:ff21514d8981	42	#ifdef __cplusplus
AnnaBridge	156:ff21514d8981	43	extern "C" {
AnnaBridge	156:ff21514d8981	44	#endif
AnnaBridge	156:ff21514d8981	45
AnnaBridge	156:ff21514d8981	46	/* Includes ------------------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	47	#include "stm32l4xx.h"
AnnaBridge	156:ff21514d8981	48
AnnaBridge	156:ff21514d8981	49	/** @addtogroup STM32L4xx_LL_Driver
AnnaBridge	156:ff21514d8981	50	* @{
AnnaBridge	156:ff21514d8981	51	*/
AnnaBridge	156:ff21514d8981	52
AnnaBridge	156:ff21514d8981	53	#if defined (SPI1) \|\| defined (SPI2) \|\| defined (SPI3)
AnnaBridge	156:ff21514d8981	54
AnnaBridge	156:ff21514d8981	55	/** @defgroup SPI_LL SPI
AnnaBridge	156:ff21514d8981	56	* @{
AnnaBridge	156:ff21514d8981	57	*/
AnnaBridge	156:ff21514d8981	58
AnnaBridge	156:ff21514d8981	59	/* Private types -------------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	60	/* Private variables ---------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	61	/* Private macros ------------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	62
AnnaBridge	156:ff21514d8981	63	/* Exported types ------------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	64	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	156:ff21514d8981	65	/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
AnnaBridge	156:ff21514d8981	66	* @{
AnnaBridge	156:ff21514d8981	67	*/
AnnaBridge	156:ff21514d8981	68
AnnaBridge	156:ff21514d8981	69	/**
AnnaBridge	156:ff21514d8981	70	* @brief SPI Init structures definition
AnnaBridge	156:ff21514d8981	71	*/
AnnaBridge	156:ff21514d8981	72	typedef struct
AnnaBridge	156:ff21514d8981	73	{
AnnaBridge	156:ff21514d8981	74	uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
AnnaBridge	156:ff21514d8981	75	This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
AnnaBridge	156:ff21514d8981	76
AnnaBridge	156:ff21514d8981	77	This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
AnnaBridge	156:ff21514d8981	78
AnnaBridge	156:ff21514d8981	79	uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
AnnaBridge	156:ff21514d8981	80	This parameter can be a value of @ref SPI_LL_EC_MODE.
AnnaBridge	156:ff21514d8981	81
AnnaBridge	156:ff21514d8981	82	This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
AnnaBridge	156:ff21514d8981	83
AnnaBridge	156:ff21514d8981	84	uint32_t DataWidth; /*!< Specifies the SPI data width.
AnnaBridge	156:ff21514d8981	85	This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
AnnaBridge	156:ff21514d8981	86
AnnaBridge	156:ff21514d8981	87	This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
AnnaBridge	156:ff21514d8981	88
AnnaBridge	156:ff21514d8981	89	uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
AnnaBridge	156:ff21514d8981	90	This parameter can be a value of @ref SPI_LL_EC_POLARITY.
AnnaBridge	156:ff21514d8981	91
AnnaBridge	156:ff21514d8981	92	This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
AnnaBridge	156:ff21514d8981	93
AnnaBridge	156:ff21514d8981	94	uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
AnnaBridge	156:ff21514d8981	95	This parameter can be a value of @ref SPI_LL_EC_PHASE.
AnnaBridge	156:ff21514d8981	96
AnnaBridge	156:ff21514d8981	97	This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
AnnaBridge	156:ff21514d8981	98
AnnaBridge	156:ff21514d8981	99	uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
AnnaBridge	156:ff21514d8981	100	This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
AnnaBridge	156:ff21514d8981	101
AnnaBridge	156:ff21514d8981	102	This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
AnnaBridge	156:ff21514d8981	103
AnnaBridge	156:ff21514d8981	104	uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
AnnaBridge	156:ff21514d8981	105	This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
AnnaBridge	156:ff21514d8981	106	@note The communication clock is derived from the master clock. The slave clock does not need to be set.
AnnaBridge	156:ff21514d8981	107
AnnaBridge	156:ff21514d8981	108	This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
AnnaBridge	156:ff21514d8981	109
AnnaBridge	156:ff21514d8981	110	uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
AnnaBridge	156:ff21514d8981	111	This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
AnnaBridge	156:ff21514d8981	112
AnnaBridge	156:ff21514d8981	113	This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
AnnaBridge	156:ff21514d8981	114
AnnaBridge	156:ff21514d8981	115	uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
AnnaBridge	156:ff21514d8981	116	This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
AnnaBridge	156:ff21514d8981	117
AnnaBridge	156:ff21514d8981	118	This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
AnnaBridge	156:ff21514d8981	119
AnnaBridge	156:ff21514d8981	120	uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
AnnaBridge	156:ff21514d8981	121	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
AnnaBridge	156:ff21514d8981	122
AnnaBridge	156:ff21514d8981	123	This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
AnnaBridge	156:ff21514d8981	124
AnnaBridge	156:ff21514d8981	125	} LL_SPI_InitTypeDef;
AnnaBridge	156:ff21514d8981	126
AnnaBridge	156:ff21514d8981	127	/**
AnnaBridge	156:ff21514d8981	128	* @}
AnnaBridge	156:ff21514d8981	129	*/
AnnaBridge	156:ff21514d8981	130	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	156:ff21514d8981	131
AnnaBridge	156:ff21514d8981	132	/* Exported constants --------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	133	/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
AnnaBridge	156:ff21514d8981	134	* @{
AnnaBridge	156:ff21514d8981	135	*/
AnnaBridge	156:ff21514d8981	136
AnnaBridge	156:ff21514d8981	137	/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	156:ff21514d8981	138	* @brief Flags defines which can be used with LL_SPI_ReadReg function
AnnaBridge	156:ff21514d8981	139	* @{
AnnaBridge	156:ff21514d8981	140	*/
AnnaBridge	156:ff21514d8981	141	#define LL_SPI_SR_RXNE SPI_SR_RXNE /!< Rx buffer not empty flag /
AnnaBridge	156:ff21514d8981	142	#define LL_SPI_SR_TXE SPI_SR_TXE /!< Tx buffer empty flag /
AnnaBridge	156:ff21514d8981	143	#define LL_SPI_SR_BSY SPI_SR_BSY /!< Busy flag /
AnnaBridge	156:ff21514d8981	144	#define LL_SPI_SR_CRCERR SPI_SR_CRCERR /!< CRC error flag /
AnnaBridge	156:ff21514d8981	145	#define LL_SPI_SR_MODF SPI_SR_MODF /!< Mode fault flag /
AnnaBridge	156:ff21514d8981	146	#define LL_SPI_SR_OVR SPI_SR_OVR /!< Overrun flag /
AnnaBridge	156:ff21514d8981	147	#define LL_SPI_SR_FRE SPI_SR_FRE /!< TI mode frame format error flag /
AnnaBridge	156:ff21514d8981	148	/**
AnnaBridge	156:ff21514d8981	149	* @}
AnnaBridge	156:ff21514d8981	150	*/
AnnaBridge	156:ff21514d8981	151
AnnaBridge	156:ff21514d8981	152	/** @defgroup SPI_LL_EC_IT IT Defines
AnnaBridge	156:ff21514d8981	153	* @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
AnnaBridge	156:ff21514d8981	154	* @{
AnnaBridge	156:ff21514d8981	155	*/
AnnaBridge	156:ff21514d8981	156	#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /!< Rx buffer not empty interrupt enable /
AnnaBridge	156:ff21514d8981	157	#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /!< Tx buffer empty interrupt enable /
AnnaBridge	156:ff21514d8981	158	#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /!< Error interrupt enable /
AnnaBridge	156:ff21514d8981	159	/**
AnnaBridge	156:ff21514d8981	160	* @}
AnnaBridge	156:ff21514d8981	161	*/
AnnaBridge	156:ff21514d8981	162
AnnaBridge	156:ff21514d8981	163	/** @defgroup SPI_LL_EC_MODE Operation Mode
AnnaBridge	156:ff21514d8981	164	* @{
AnnaBridge	156:ff21514d8981	165	*/
AnnaBridge	156:ff21514d8981	166	#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR \| SPI_CR1_SSI) /!< Master configuration /
AnnaBridge	156:ff21514d8981	167	#define LL_SPI_MODE_SLAVE 0x00000000U /!< Slave configuration /
AnnaBridge	156:ff21514d8981	168	/**
AnnaBridge	156:ff21514d8981	169	* @}
AnnaBridge	156:ff21514d8981	170	*/
AnnaBridge	156:ff21514d8981	171
AnnaBridge	156:ff21514d8981	172	/** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
AnnaBridge	156:ff21514d8981	173	* @{
AnnaBridge	156:ff21514d8981	174	*/
AnnaBridge	156:ff21514d8981	175	#define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /!< Motorola mode. Used as default value /
AnnaBridge	156:ff21514d8981	176	#define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /!< TI mode /
AnnaBridge	156:ff21514d8981	177	/**
AnnaBridge	156:ff21514d8981	178	* @}
AnnaBridge	156:ff21514d8981	179	*/
AnnaBridge	156:ff21514d8981	180
AnnaBridge	156:ff21514d8981	181	/** @defgroup SPI_LL_EC_PHASE Clock Phase
AnnaBridge	156:ff21514d8981	182	* @{
AnnaBridge	156:ff21514d8981	183	*/
AnnaBridge	156:ff21514d8981	184	#define LL_SPI_PHASE_1EDGE 0x00000000U /!< First clock transition is the first data capture edge /
AnnaBridge	156:ff21514d8981	185	#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /!< Second clock transition is the first data capture edge /
AnnaBridge	156:ff21514d8981	186	/**
AnnaBridge	156:ff21514d8981	187	* @}
AnnaBridge	156:ff21514d8981	188	*/
AnnaBridge	156:ff21514d8981	189
AnnaBridge	156:ff21514d8981	190	/** @defgroup SPI_LL_EC_POLARITY Clock Polarity
AnnaBridge	156:ff21514d8981	191	* @{
AnnaBridge	156:ff21514d8981	192	*/
AnnaBridge	156:ff21514d8981	193	#define LL_SPI_POLARITY_LOW 0x00000000U /!< Clock to 0 when idle /
AnnaBridge	156:ff21514d8981	194	#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /!< Clock to 1 when idle /
AnnaBridge	156:ff21514d8981	195	/**
AnnaBridge	156:ff21514d8981	196	* @}
AnnaBridge	156:ff21514d8981	197	*/
AnnaBridge	156:ff21514d8981	198
AnnaBridge	156:ff21514d8981	199	/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
AnnaBridge	156:ff21514d8981	200	* @{
AnnaBridge	156:ff21514d8981	201	*/
AnnaBridge	156:ff21514d8981	202	#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /!< BaudRate control equal to fPCLK/2 /
AnnaBridge	156:ff21514d8981	203	#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/4 /
AnnaBridge	156:ff21514d8981	204	#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /!< BaudRate control equal to fPCLK/8 /
AnnaBridge	156:ff21514d8981	205	#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/16 /
AnnaBridge	156:ff21514d8981	206	#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /!< BaudRate control equal to fPCLK/32 /
AnnaBridge	156:ff21514d8981	207	#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/64 /
AnnaBridge	156:ff21514d8981	208	#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 \| SPI_CR1_BR_1) /!< BaudRate control equal to fPCLK/128 /
AnnaBridge	156:ff21514d8981	209	#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 \| SPI_CR1_BR_1 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/256 /
AnnaBridge	156:ff21514d8981	210	/**
AnnaBridge	156:ff21514d8981	211	* @}
AnnaBridge	156:ff21514d8981	212	*/
AnnaBridge	156:ff21514d8981	213
AnnaBridge	156:ff21514d8981	214	/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
AnnaBridge	156:ff21514d8981	215	* @{
AnnaBridge	156:ff21514d8981	216	*/
AnnaBridge	156:ff21514d8981	217	#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /!< Data is transmitted/received with the LSB first /
AnnaBridge	156:ff21514d8981	218	#define LL_SPI_MSB_FIRST 0x00000000U /!< Data is transmitted/received with the MSB first /
AnnaBridge	156:ff21514d8981	219	/**
AnnaBridge	156:ff21514d8981	220	* @}
AnnaBridge	156:ff21514d8981	221	*/
AnnaBridge	156:ff21514d8981	222
AnnaBridge	156:ff21514d8981	223	/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
AnnaBridge	156:ff21514d8981	224	* @{
AnnaBridge	156:ff21514d8981	225	*/
AnnaBridge	156:ff21514d8981	226	#define LL_SPI_FULL_DUPLEX 0x00000000U /!< Full-Duplex mode. Rx and Tx transfer on 2 lines /
AnnaBridge	156:ff21514d8981	227	#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /!< Simplex Rx mode. Rx transfer only on 1 line /
AnnaBridge	156:ff21514d8981	228	#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /!< Half-Duplex Rx mode. Rx transfer on 1 line /
AnnaBridge	156:ff21514d8981	229	#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE) /!< Half-Duplex Tx mode. Tx transfer on 1 line /
AnnaBridge	156:ff21514d8981	230	/**
AnnaBridge	156:ff21514d8981	231	* @}
AnnaBridge	156:ff21514d8981	232	*/
AnnaBridge	156:ff21514d8981	233
AnnaBridge	156:ff21514d8981	234	/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
AnnaBridge	156:ff21514d8981	235	* @{
AnnaBridge	156:ff21514d8981	236	*/
AnnaBridge	156:ff21514d8981	237	#define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /!< NSS managed internally. NSS pin not used and free /
AnnaBridge	156:ff21514d8981	238	#define LL_SPI_NSS_HARD_INPUT 0x00000000U /!< NSS pin used in Input. Only used in Master mode /
AnnaBridge	156:ff21514d8981	239	#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /!< NSS pin used in Output. Only used in Slave mode as chip select /
AnnaBridge	156:ff21514d8981	240	/**
AnnaBridge	156:ff21514d8981	241	* @}
AnnaBridge	156:ff21514d8981	242	*/
AnnaBridge	156:ff21514d8981	243
AnnaBridge	156:ff21514d8981	244	/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
AnnaBridge	156:ff21514d8981	245	* @{
AnnaBridge	156:ff21514d8981	246	*/
AnnaBridge	156:ff21514d8981	247	#define LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 \| SPI_CR2_DS_1) /!< Data length for SPI transfer: 4 bits /
AnnaBridge	156:ff21514d8981	248	#define LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2) /!< Data length for SPI transfer: 5 bits /
AnnaBridge	156:ff21514d8981	249	#define LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 6 bits /
AnnaBridge	156:ff21514d8981	250	#define LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 \| SPI_CR2_DS_1) /!< Data length for SPI transfer: 7 bits /
AnnaBridge	156:ff21514d8981	251	#define LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 \| SPI_CR2_DS_1 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 8 bits /
AnnaBridge	156:ff21514d8981	252	#define LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3) /!< Data length for SPI transfer: 9 bits /
AnnaBridge	156:ff21514d8981	253	#define LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 10 bits /
AnnaBridge	156:ff21514d8981	254	#define LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_1) /!< Data length for SPI transfer: 11 bits /
AnnaBridge	156:ff21514d8981	255	#define LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_1 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 12 bits /
AnnaBridge	156:ff21514d8981	256	#define LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_2) /!< Data length for SPI transfer: 13 bits /
AnnaBridge	156:ff21514d8981	257	#define LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_2 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 14 bits /
AnnaBridge	156:ff21514d8981	258	#define LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_2 \| SPI_CR2_DS_1) /!< Data length for SPI transfer: 15 bits /
AnnaBridge	156:ff21514d8981	259	#define LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_2 \| SPI_CR2_DS_1 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 16 bits /
AnnaBridge	156:ff21514d8981	260	/**
AnnaBridge	156:ff21514d8981	261	* @}
AnnaBridge	156:ff21514d8981	262	*/
AnnaBridge	156:ff21514d8981	263	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	156:ff21514d8981	264
AnnaBridge	156:ff21514d8981	265	/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
AnnaBridge	156:ff21514d8981	266	* @{
AnnaBridge	156:ff21514d8981	267	*/
AnnaBridge	156:ff21514d8981	268	#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /!< CRC calculation disabled /
AnnaBridge	156:ff21514d8981	269	#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /!< CRC calculation enabled /
AnnaBridge	156:ff21514d8981	270	/**
AnnaBridge	156:ff21514d8981	271	* @}
AnnaBridge	156:ff21514d8981	272	*/
AnnaBridge	156:ff21514d8981	273	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	156:ff21514d8981	274
AnnaBridge	156:ff21514d8981	275	/** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length
AnnaBridge	156:ff21514d8981	276	* @{
AnnaBridge	156:ff21514d8981	277	*/
AnnaBridge	156:ff21514d8981	278	#define LL_SPI_CRC_8BIT 0x00000000U /!< 8-bit CRC length /
AnnaBridge	156:ff21514d8981	279	#define LL_SPI_CRC_16BIT (SPI_CR1_CRCL) /!< 16-bit CRC length /
AnnaBridge	156:ff21514d8981	280	/**
AnnaBridge	156:ff21514d8981	281	* @}
AnnaBridge	156:ff21514d8981	282	*/
AnnaBridge	156:ff21514d8981	283
AnnaBridge	156:ff21514d8981	284	/** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold
AnnaBridge	156:ff21514d8981	285	* @{
AnnaBridge	156:ff21514d8981	286	*/
AnnaBridge	156:ff21514d8981	287	#define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /!< RXNE event is generated if FIFO level is greater than or equel to 1/2 (16-bit) /
AnnaBridge	156:ff21514d8981	288	#define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /!< RXNE event is generated if FIFO level is greater than or equel to 1/4 (8-bit) /
AnnaBridge	156:ff21514d8981	289	/**
AnnaBridge	156:ff21514d8981	290	* @}
AnnaBridge	156:ff21514d8981	291	*/
AnnaBridge	156:ff21514d8981	292
AnnaBridge	156:ff21514d8981	293	/** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level
AnnaBridge	156:ff21514d8981	294	* @{
AnnaBridge	156:ff21514d8981	295	*/
AnnaBridge	156:ff21514d8981	296	#define LL_SPI_RX_FIFO_EMPTY 0x00000000U /!< FIFO reception empty /
AnnaBridge	156:ff21514d8981	297	#define LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0) /!< FIFO reception 1/4 /
AnnaBridge	156:ff21514d8981	298	#define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1) /!< FIFO reception 1/2 /
AnnaBridge	156:ff21514d8981	299	#define LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 \| SPI_SR_FRLVL_0) /!< FIFO reception full /
AnnaBridge	156:ff21514d8981	300	/**
AnnaBridge	156:ff21514d8981	301	* @}
AnnaBridge	156:ff21514d8981	302	*/
AnnaBridge	156:ff21514d8981	303
AnnaBridge	156:ff21514d8981	304	/** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level
AnnaBridge	156:ff21514d8981	305	* @{
AnnaBridge	156:ff21514d8981	306	*/
AnnaBridge	156:ff21514d8981	307	#define LL_SPI_TX_FIFO_EMPTY 0x00000000U /!< FIFO transmission empty /
AnnaBridge	156:ff21514d8981	308	#define LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0) /!< FIFO transmission 1/4 /
AnnaBridge	156:ff21514d8981	309	#define LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1) /!< FIFO transmission 1/2 /
AnnaBridge	156:ff21514d8981	310	#define LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 \| SPI_SR_FTLVL_0) /!< FIFO transmission full /
AnnaBridge	156:ff21514d8981	311	/**
AnnaBridge	156:ff21514d8981	312	* @}
AnnaBridge	156:ff21514d8981	313	*/
AnnaBridge	156:ff21514d8981	314
AnnaBridge	156:ff21514d8981	315	/** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity
AnnaBridge	156:ff21514d8981	316	* @{
AnnaBridge	156:ff21514d8981	317	*/
AnnaBridge	156:ff21514d8981	318	#define LL_SPI_DMA_PARITY_EVEN 0x00000000U /!< Select DMA parity Even /
AnnaBridge	156:ff21514d8981	319	#define LL_SPI_DMA_PARITY_ODD 0x00000001U /!< Select DMA parity Odd /
AnnaBridge	156:ff21514d8981	320
AnnaBridge	156:ff21514d8981	321	/**
AnnaBridge	156:ff21514d8981	322	* @}
AnnaBridge	156:ff21514d8981	323	*/
AnnaBridge	156:ff21514d8981	324
AnnaBridge	156:ff21514d8981	325	/**
AnnaBridge	156:ff21514d8981	326	* @}
AnnaBridge	156:ff21514d8981	327	*/
AnnaBridge	156:ff21514d8981	328
AnnaBridge	156:ff21514d8981	329	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	330	/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
AnnaBridge	156:ff21514d8981	331	* @{
AnnaBridge	156:ff21514d8981	332	*/
AnnaBridge	156:ff21514d8981	333
AnnaBridge	156:ff21514d8981	334	/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge	156:ff21514d8981	335	* @{
AnnaBridge	156:ff21514d8981	336	*/
AnnaBridge	156:ff21514d8981	337
AnnaBridge	156:ff21514d8981	338	/**
AnnaBridge	156:ff21514d8981	339	* @brief Write a value in SPI register
AnnaBridge	156:ff21514d8981	340	* @param __INSTANCE__ SPI Instance
AnnaBridge	156:ff21514d8981	341	* @param __REG__ Register to be written
AnnaBridge	156:ff21514d8981	342	* @param __VALUE__ Value to be written in the register
AnnaBridge	156:ff21514d8981	343	* @retval None
AnnaBridge	156:ff21514d8981	344	*/
AnnaBridge	156:ff21514d8981	345	#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge	156:ff21514d8981	346
AnnaBridge	156:ff21514d8981	347	/**
AnnaBridge	156:ff21514d8981	348	* @brief Read a value in SPI register
AnnaBridge	156:ff21514d8981	349	* @param __INSTANCE__ SPI Instance
AnnaBridge	156:ff21514d8981	350	* @param __REG__ Register to be read
AnnaBridge	156:ff21514d8981	351	* @retval Register value
AnnaBridge	156:ff21514d8981	352	*/
AnnaBridge	156:ff21514d8981	353	#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	156:ff21514d8981	354	/**
AnnaBridge	156:ff21514d8981	355	* @}
AnnaBridge	156:ff21514d8981	356	*/
AnnaBridge	156:ff21514d8981	357
AnnaBridge	156:ff21514d8981	358	/**
AnnaBridge	156:ff21514d8981	359	* @}
AnnaBridge	156:ff21514d8981	360	*/
AnnaBridge	156:ff21514d8981	361
AnnaBridge	156:ff21514d8981	362	/* Exported functions --------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	363	/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
AnnaBridge	156:ff21514d8981	364	* @{
AnnaBridge	156:ff21514d8981	365	*/
AnnaBridge	156:ff21514d8981	366
AnnaBridge	156:ff21514d8981	367	/** @defgroup SPI_LL_EF_Configuration Configuration
AnnaBridge	156:ff21514d8981	368	* @{
AnnaBridge	156:ff21514d8981	369	*/
AnnaBridge	156:ff21514d8981	370
AnnaBridge	156:ff21514d8981	371	/**
AnnaBridge	156:ff21514d8981	372	* @brief Enable SPI peripheral
AnnaBridge	156:ff21514d8981	373	* @rmtoll CR1 SPE LL_SPI_Enable
AnnaBridge	156:ff21514d8981	374	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	375	* @retval None
AnnaBridge	156:ff21514d8981	376	*/
AnnaBridge	156:ff21514d8981	377	__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	378	{
AnnaBridge	156:ff21514d8981	379	SET_BIT(SPIx->CR1, SPI_CR1_SPE);
AnnaBridge	156:ff21514d8981	380	}
AnnaBridge	156:ff21514d8981	381
AnnaBridge	156:ff21514d8981	382	/**
AnnaBridge	156:ff21514d8981	383	* @brief Disable SPI peripheral
AnnaBridge	156:ff21514d8981	384	* @note When disabling the SPI, follow the procedure described in the Reference Manual.
AnnaBridge	156:ff21514d8981	385	* @rmtoll CR1 SPE LL_SPI_Disable
AnnaBridge	156:ff21514d8981	386	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	387	* @retval None
AnnaBridge	156:ff21514d8981	388	*/
AnnaBridge	156:ff21514d8981	389	__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	390	{
AnnaBridge	156:ff21514d8981	391	CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
AnnaBridge	156:ff21514d8981	392	}
AnnaBridge	156:ff21514d8981	393
AnnaBridge	156:ff21514d8981	394	/**
AnnaBridge	156:ff21514d8981	395	* @brief Check if SPI peripheral is enabled
AnnaBridge	156:ff21514d8981	396	* @rmtoll CR1 SPE LL_SPI_IsEnabled
AnnaBridge	156:ff21514d8981	397	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	398	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	399	*/
AnnaBridge	156:ff21514d8981	400	__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	401	{
AnnaBridge	156:ff21514d8981	402	return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE));
AnnaBridge	156:ff21514d8981	403	}
AnnaBridge	156:ff21514d8981	404
AnnaBridge	156:ff21514d8981	405	/**
AnnaBridge	156:ff21514d8981	406	* @brief Set SPI operation mode to Master or Slave
AnnaBridge	156:ff21514d8981	407	* @note This bit should not be changed when communication is ongoing.
AnnaBridge	156:ff21514d8981	408	* @rmtoll CR1 MSTR LL_SPI_SetMode\n
AnnaBridge	156:ff21514d8981	409	* CR1 SSI LL_SPI_SetMode
AnnaBridge	156:ff21514d8981	410	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	411	* @param Mode This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	412	* @arg @ref LL_SPI_MODE_MASTER
AnnaBridge	156:ff21514d8981	413	* @arg @ref LL_SPI_MODE_SLAVE
AnnaBridge	156:ff21514d8981	414	* @retval None
AnnaBridge	156:ff21514d8981	415	*/
AnnaBridge	156:ff21514d8981	416	__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
AnnaBridge	156:ff21514d8981	417	{
AnnaBridge	156:ff21514d8981	418	MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR \| SPI_CR1_SSI, Mode);
AnnaBridge	156:ff21514d8981	419	}
AnnaBridge	156:ff21514d8981	420
AnnaBridge	156:ff21514d8981	421	/**
AnnaBridge	156:ff21514d8981	422	* @brief Get SPI operation mode (Master or Slave)
AnnaBridge	156:ff21514d8981	423	* @rmtoll CR1 MSTR LL_SPI_GetMode\n
AnnaBridge	156:ff21514d8981	424	* CR1 SSI LL_SPI_GetMode
AnnaBridge	156:ff21514d8981	425	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	426	* @retval Returned value can be one of the following values:
AnnaBridge	156:ff21514d8981	427	* @arg @ref LL_SPI_MODE_MASTER
AnnaBridge	156:ff21514d8981	428	* @arg @ref LL_SPI_MODE_SLAVE
AnnaBridge	156:ff21514d8981	429	*/
AnnaBridge	156:ff21514d8981	430	__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	431	{
AnnaBridge	156:ff21514d8981	432	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR \| SPI_CR1_SSI));
AnnaBridge	156:ff21514d8981	433	}
AnnaBridge	156:ff21514d8981	434
AnnaBridge	156:ff21514d8981	435	/**
AnnaBridge	156:ff21514d8981	436	* @brief Set serial protocol used
AnnaBridge	156:ff21514d8981	437	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge	156:ff21514d8981	438	* @rmtoll CR2 FRF LL_SPI_SetStandard
AnnaBridge	156:ff21514d8981	439	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	440	* @param Standard This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	441	* @arg @ref LL_SPI_PROTOCOL_MOTOROLA
AnnaBridge	156:ff21514d8981	442	* @arg @ref LL_SPI_PROTOCOL_TI
AnnaBridge	156:ff21514d8981	443	* @retval None
AnnaBridge	156:ff21514d8981	444	*/
AnnaBridge	156:ff21514d8981	445	__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
AnnaBridge	156:ff21514d8981	446	{
AnnaBridge	156:ff21514d8981	447	MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
AnnaBridge	156:ff21514d8981	448	}
AnnaBridge	156:ff21514d8981	449
AnnaBridge	156:ff21514d8981	450	/**
AnnaBridge	156:ff21514d8981	451	* @brief Get serial protocol used
AnnaBridge	156:ff21514d8981	452	* @rmtoll CR2 FRF LL_SPI_GetStandard
AnnaBridge	156:ff21514d8981	453	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	454	* @retval Returned value can be one of the following values:
AnnaBridge	156:ff21514d8981	455	* @arg @ref LL_SPI_PROTOCOL_MOTOROLA
AnnaBridge	156:ff21514d8981	456	* @arg @ref LL_SPI_PROTOCOL_TI
AnnaBridge	156:ff21514d8981	457	*/
AnnaBridge	156:ff21514d8981	458	__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	459	{
AnnaBridge	156:ff21514d8981	460	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
AnnaBridge	156:ff21514d8981	461	}
AnnaBridge	156:ff21514d8981	462
AnnaBridge	156:ff21514d8981	463	/**
AnnaBridge	156:ff21514d8981	464	* @brief Set clock phase
AnnaBridge	156:ff21514d8981	465	* @note This bit should not be changed when communication is ongoing.
AnnaBridge	156:ff21514d8981	466	* This bit is not used in SPI TI mode.
AnnaBridge	156:ff21514d8981	467	* @rmtoll CR1 CPHA LL_SPI_SetClockPhase
AnnaBridge	156:ff21514d8981	468	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	469	* @param ClockPhase This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	470	* @arg @ref LL_SPI_PHASE_1EDGE
AnnaBridge	156:ff21514d8981	471	* @arg @ref LL_SPI_PHASE_2EDGE
AnnaBridge	156:ff21514d8981	472	* @retval None
AnnaBridge	156:ff21514d8981	473	*/
AnnaBridge	156:ff21514d8981	474	__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
AnnaBridge	156:ff21514d8981	475	{
AnnaBridge	156:ff21514d8981	476	MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
AnnaBridge	156:ff21514d8981	477	}
AnnaBridge	156:ff21514d8981	478
AnnaBridge	156:ff21514d8981	479	/**
AnnaBridge	156:ff21514d8981	480	* @brief Get clock phase
AnnaBridge	156:ff21514d8981	481	* @rmtoll CR1 CPHA LL_SPI_GetClockPhase
AnnaBridge	156:ff21514d8981	482	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	483	* @retval Returned value can be one of the following values:
AnnaBridge	156:ff21514d8981	484	* @arg @ref LL_SPI_PHASE_1EDGE
AnnaBridge	156:ff21514d8981	485	* @arg @ref LL_SPI_PHASE_2EDGE
AnnaBridge	156:ff21514d8981	486	*/
AnnaBridge	156:ff21514d8981	487	__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	488	{
AnnaBridge	156:ff21514d8981	489	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
AnnaBridge	156:ff21514d8981	490	}
AnnaBridge	156:ff21514d8981	491
AnnaBridge	156:ff21514d8981	492	/**
AnnaBridge	156:ff21514d8981	493	* @brief Set clock polarity
AnnaBridge	156:ff21514d8981	494	* @note This bit should not be changed when communication is ongoing.
AnnaBridge	156:ff21514d8981	495	* This bit is not used in SPI TI mode.
AnnaBridge	156:ff21514d8981	496	* @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
AnnaBridge	156:ff21514d8981	497	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	498	* @param ClockPolarity This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	499	* @arg @ref LL_SPI_POLARITY_LOW
AnnaBridge	156:ff21514d8981	500	* @arg @ref LL_SPI_POLARITY_HIGH
AnnaBridge	156:ff21514d8981	501	* @retval None
AnnaBridge	156:ff21514d8981	502	*/
AnnaBridge	156:ff21514d8981	503	__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
AnnaBridge	156:ff21514d8981	504	{
AnnaBridge	156:ff21514d8981	505	MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
AnnaBridge	156:ff21514d8981	506	}
AnnaBridge	156:ff21514d8981	507
AnnaBridge	156:ff21514d8981	508	/**
AnnaBridge	156:ff21514d8981	509	* @brief Get clock polarity
AnnaBridge	156:ff21514d8981	510	* @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
AnnaBridge	156:ff21514d8981	511	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	512	* @retval Returned value can be one of the following values:
AnnaBridge	156:ff21514d8981	513	* @arg @ref LL_SPI_POLARITY_LOW
AnnaBridge	156:ff21514d8981	514	* @arg @ref LL_SPI_POLARITY_HIGH
AnnaBridge	156:ff21514d8981	515	*/
AnnaBridge	156:ff21514d8981	516	__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	517	{
AnnaBridge	156:ff21514d8981	518	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
AnnaBridge	156:ff21514d8981	519	}
AnnaBridge	156:ff21514d8981	520
AnnaBridge	156:ff21514d8981	521	/**
AnnaBridge	156:ff21514d8981	522	* @brief Set baud rate prescaler
AnnaBridge	156:ff21514d8981	523	* @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
AnnaBridge	156:ff21514d8981	524	* @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
AnnaBridge	156:ff21514d8981	525	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	526	* @param BaudRate This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	527	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
AnnaBridge	156:ff21514d8981	528	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
AnnaBridge	156:ff21514d8981	529	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
AnnaBridge	156:ff21514d8981	530	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
AnnaBridge	156:ff21514d8981	531	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
AnnaBridge	156:ff21514d8981	532	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
AnnaBridge	156:ff21514d8981	533	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
AnnaBridge	156:ff21514d8981	534	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
AnnaBridge	156:ff21514d8981	535	* @retval None
AnnaBridge	156:ff21514d8981	536	*/
AnnaBridge	156:ff21514d8981	537	__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
AnnaBridge	156:ff21514d8981	538	{
AnnaBridge	156:ff21514d8981	539	MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
AnnaBridge	156:ff21514d8981	540	}
AnnaBridge	156:ff21514d8981	541
AnnaBridge	156:ff21514d8981	542	/**
AnnaBridge	156:ff21514d8981	543	* @brief Get baud rate prescaler
AnnaBridge	156:ff21514d8981	544	* @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
AnnaBridge	156:ff21514d8981	545	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	546	* @retval Returned value can be one of the following values:
AnnaBridge	156:ff21514d8981	547	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
AnnaBridge	156:ff21514d8981	548	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
AnnaBridge	156:ff21514d8981	549	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
AnnaBridge	156:ff21514d8981	550	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
AnnaBridge	156:ff21514d8981	551	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
AnnaBridge	156:ff21514d8981	552	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
AnnaBridge	156:ff21514d8981	553	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
AnnaBridge	156:ff21514d8981	554	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
AnnaBridge	156:ff21514d8981	555	*/
AnnaBridge	156:ff21514d8981	556	__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	557	{
AnnaBridge	156:ff21514d8981	558	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
AnnaBridge	156:ff21514d8981	559	}
AnnaBridge	156:ff21514d8981	560
AnnaBridge	156:ff21514d8981	561	/**
AnnaBridge	156:ff21514d8981	562	* @brief Set transfer bit order
AnnaBridge	156:ff21514d8981	563	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
AnnaBridge	156:ff21514d8981	564	* @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
AnnaBridge	156:ff21514d8981	565	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	566	* @param BitOrder This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	567	* @arg @ref LL_SPI_LSB_FIRST
AnnaBridge	156:ff21514d8981	568	* @arg @ref LL_SPI_MSB_FIRST
AnnaBridge	156:ff21514d8981	569	* @retval None
AnnaBridge	156:ff21514d8981	570	*/
AnnaBridge	156:ff21514d8981	571	__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
AnnaBridge	156:ff21514d8981	572	{
AnnaBridge	156:ff21514d8981	573	MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
AnnaBridge	156:ff21514d8981	574	}
AnnaBridge	156:ff21514d8981	575
AnnaBridge	156:ff21514d8981	576	/**
AnnaBridge	156:ff21514d8981	577	* @brief Get transfer bit order
AnnaBridge	156:ff21514d8981	578	* @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
AnnaBridge	156:ff21514d8981	579	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	580	* @retval Returned value can be one of the following values:
AnnaBridge	156:ff21514d8981	581	* @arg @ref LL_SPI_LSB_FIRST
AnnaBridge	156:ff21514d8981	582	* @arg @ref LL_SPI_MSB_FIRST
AnnaBridge	156:ff21514d8981	583	*/
AnnaBridge	156:ff21514d8981	584	__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	585	{
AnnaBridge	156:ff21514d8981	586	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
AnnaBridge	156:ff21514d8981	587	}
AnnaBridge	156:ff21514d8981	588
AnnaBridge	156:ff21514d8981	589	/**
AnnaBridge	156:ff21514d8981	590	* @brief Set transfer direction mode
AnnaBridge	156:ff21514d8981	591	* @note For Half-Duplex mode, Rx Direction is set by default.
AnnaBridge	156:ff21514d8981	592	* In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
AnnaBridge	156:ff21514d8981	593	* @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
AnnaBridge	156:ff21514d8981	594	* CR1 BIDIMODE LL_SPI_SetTransferDirection\n
AnnaBridge	156:ff21514d8981	595	* CR1 BIDIOE LL_SPI_SetTransferDirection
AnnaBridge	156:ff21514d8981	596	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	597	* @param TransferDirection This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	598	* @arg @ref LL_SPI_FULL_DUPLEX
AnnaBridge	156:ff21514d8981	599	* @arg @ref LL_SPI_SIMPLEX_RX
AnnaBridge	156:ff21514d8981	600	* @arg @ref LL_SPI_HALF_DUPLEX_RX
AnnaBridge	156:ff21514d8981	601	* @arg @ref LL_SPI_HALF_DUPLEX_TX
AnnaBridge	156:ff21514d8981	602	* @retval None
AnnaBridge	156:ff21514d8981	603	*/
AnnaBridge	156:ff21514d8981	604	__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
AnnaBridge	156:ff21514d8981	605	{
AnnaBridge	156:ff21514d8981	606	MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY \| SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE, TransferDirection);
AnnaBridge	156:ff21514d8981	607	}
AnnaBridge	156:ff21514d8981	608
AnnaBridge	156:ff21514d8981	609	/**
AnnaBridge	156:ff21514d8981	610	* @brief Get transfer direction mode
AnnaBridge	156:ff21514d8981	611	* @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
AnnaBridge	156:ff21514d8981	612	* CR1 BIDIMODE LL_SPI_GetTransferDirection\n
AnnaBridge	156:ff21514d8981	613	* CR1 BIDIOE LL_SPI_GetTransferDirection
AnnaBridge	156:ff21514d8981	614	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	615	* @retval Returned value can be one of the following values:
AnnaBridge	156:ff21514d8981	616	* @arg @ref LL_SPI_FULL_DUPLEX
AnnaBridge	156:ff21514d8981	617	* @arg @ref LL_SPI_SIMPLEX_RX
AnnaBridge	156:ff21514d8981	618	* @arg @ref LL_SPI_HALF_DUPLEX_RX
AnnaBridge	156:ff21514d8981	619	* @arg @ref LL_SPI_HALF_DUPLEX_TX
AnnaBridge	156:ff21514d8981	620	*/
AnnaBridge	156:ff21514d8981	621	__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	622	{
AnnaBridge	156:ff21514d8981	623	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY \| SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE));
AnnaBridge	156:ff21514d8981	624	}
AnnaBridge	156:ff21514d8981	625
AnnaBridge	156:ff21514d8981	626	/**
AnnaBridge	156:ff21514d8981	627	* @brief Set frame data width
AnnaBridge	156:ff21514d8981	628	* @rmtoll CR2 DS LL_SPI_SetDataWidth
AnnaBridge	156:ff21514d8981	629	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	630	* @param DataWidth This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	631	* @arg @ref LL_SPI_DATAWIDTH_4BIT
AnnaBridge	156:ff21514d8981	632	* @arg @ref LL_SPI_DATAWIDTH_5BIT
AnnaBridge	156:ff21514d8981	633	* @arg @ref LL_SPI_DATAWIDTH_6BIT
AnnaBridge	156:ff21514d8981	634	* @arg @ref LL_SPI_DATAWIDTH_7BIT
AnnaBridge	156:ff21514d8981	635	* @arg @ref LL_SPI_DATAWIDTH_8BIT
AnnaBridge	156:ff21514d8981	636	* @arg @ref LL_SPI_DATAWIDTH_9BIT
AnnaBridge	156:ff21514d8981	637	* @arg @ref LL_SPI_DATAWIDTH_10BIT
AnnaBridge	156:ff21514d8981	638	* @arg @ref LL_SPI_DATAWIDTH_11BIT
AnnaBridge	156:ff21514d8981	639	* @arg @ref LL_SPI_DATAWIDTH_12BIT
AnnaBridge	156:ff21514d8981	640	* @arg @ref LL_SPI_DATAWIDTH_13BIT
AnnaBridge	156:ff21514d8981	641	* @arg @ref LL_SPI_DATAWIDTH_14BIT
AnnaBridge	156:ff21514d8981	642	* @arg @ref LL_SPI_DATAWIDTH_15BIT
AnnaBridge	156:ff21514d8981	643	* @arg @ref LL_SPI_DATAWIDTH_16BIT
AnnaBridge	156:ff21514d8981	644	* @retval None
AnnaBridge	156:ff21514d8981	645	*/
AnnaBridge	156:ff21514d8981	646	__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
AnnaBridge	156:ff21514d8981	647	{
AnnaBridge	156:ff21514d8981	648	MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth);
AnnaBridge	156:ff21514d8981	649	}
AnnaBridge	156:ff21514d8981	650
AnnaBridge	156:ff21514d8981	651	/**
AnnaBridge	156:ff21514d8981	652	* @brief Get frame data width
AnnaBridge	156:ff21514d8981	653	* @rmtoll CR2 DS LL_SPI_GetDataWidth
AnnaBridge	156:ff21514d8981	654	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	655	* @retval Returned value can be one of the following values:
AnnaBridge	156:ff21514d8981	656	* @arg @ref LL_SPI_DATAWIDTH_4BIT
AnnaBridge	156:ff21514d8981	657	* @arg @ref LL_SPI_DATAWIDTH_5BIT
AnnaBridge	156:ff21514d8981	658	* @arg @ref LL_SPI_DATAWIDTH_6BIT
AnnaBridge	156:ff21514d8981	659	* @arg @ref LL_SPI_DATAWIDTH_7BIT
AnnaBridge	156:ff21514d8981	660	* @arg @ref LL_SPI_DATAWIDTH_8BIT
AnnaBridge	156:ff21514d8981	661	* @arg @ref LL_SPI_DATAWIDTH_9BIT
AnnaBridge	156:ff21514d8981	662	* @arg @ref LL_SPI_DATAWIDTH_10BIT
AnnaBridge	156:ff21514d8981	663	* @arg @ref LL_SPI_DATAWIDTH_11BIT
AnnaBridge	156:ff21514d8981	664	* @arg @ref LL_SPI_DATAWIDTH_12BIT
AnnaBridge	156:ff21514d8981	665	* @arg @ref LL_SPI_DATAWIDTH_13BIT
AnnaBridge	156:ff21514d8981	666	* @arg @ref LL_SPI_DATAWIDTH_14BIT
AnnaBridge	156:ff21514d8981	667	* @arg @ref LL_SPI_DATAWIDTH_15BIT
AnnaBridge	156:ff21514d8981	668	* @arg @ref LL_SPI_DATAWIDTH_16BIT
AnnaBridge	156:ff21514d8981	669	*/
AnnaBridge	156:ff21514d8981	670	__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	671	{
AnnaBridge	156:ff21514d8981	672	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS));
AnnaBridge	156:ff21514d8981	673	}
AnnaBridge	156:ff21514d8981	674
AnnaBridge	156:ff21514d8981	675	/**
AnnaBridge	156:ff21514d8981	676	* @brief Set threshold of RXFIFO that triggers an RXNE event
AnnaBridge	156:ff21514d8981	677	* @rmtoll CR2 FRXTH LL_SPI_SetRxFIFOThreshold
AnnaBridge	156:ff21514d8981	678	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	679	* @param Threshold This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	680	* @arg @ref LL_SPI_RX_FIFO_TH_HALF
AnnaBridge	156:ff21514d8981	681	* @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
AnnaBridge	156:ff21514d8981	682	* @retval None
AnnaBridge	156:ff21514d8981	683	*/
AnnaBridge	156:ff21514d8981	684	__STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
AnnaBridge	156:ff21514d8981	685	{
AnnaBridge	156:ff21514d8981	686	MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold);
AnnaBridge	156:ff21514d8981	687	}
AnnaBridge	156:ff21514d8981	688
AnnaBridge	156:ff21514d8981	689	/**
AnnaBridge	156:ff21514d8981	690	* @brief Get threshold of RXFIFO that triggers an RXNE event
AnnaBridge	156:ff21514d8981	691	* @rmtoll CR2 FRXTH LL_SPI_GetRxFIFOThreshold
AnnaBridge	156:ff21514d8981	692	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	693	* @retval Returned value can be one of the following values:
AnnaBridge	156:ff21514d8981	694	* @arg @ref LL_SPI_RX_FIFO_TH_HALF
AnnaBridge	156:ff21514d8981	695	* @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
AnnaBridge	156:ff21514d8981	696	*/
AnnaBridge	156:ff21514d8981	697	__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	698	{
AnnaBridge	156:ff21514d8981	699	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH));
AnnaBridge	156:ff21514d8981	700	}
AnnaBridge	156:ff21514d8981	701
AnnaBridge	156:ff21514d8981	702	/**
AnnaBridge	156:ff21514d8981	703	* @}
AnnaBridge	156:ff21514d8981	704	*/
AnnaBridge	156:ff21514d8981	705
AnnaBridge	156:ff21514d8981	706	/** @defgroup SPI_LL_EF_CRC_Management CRC Management
AnnaBridge	156:ff21514d8981	707	* @{
AnnaBridge	156:ff21514d8981	708	*/
AnnaBridge	156:ff21514d8981	709
AnnaBridge	156:ff21514d8981	710	/**
AnnaBridge	156:ff21514d8981	711	* @brief Enable CRC
AnnaBridge	156:ff21514d8981	712	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge	156:ff21514d8981	713	* @rmtoll CR1 CRCEN LL_SPI_EnableCRC
AnnaBridge	156:ff21514d8981	714	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	715	* @retval None
AnnaBridge	156:ff21514d8981	716	*/
AnnaBridge	156:ff21514d8981	717	__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	718	{
AnnaBridge	156:ff21514d8981	719	SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
AnnaBridge	156:ff21514d8981	720	}
AnnaBridge	156:ff21514d8981	721
AnnaBridge	156:ff21514d8981	722	/**
AnnaBridge	156:ff21514d8981	723	* @brief Disable CRC
AnnaBridge	156:ff21514d8981	724	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge	156:ff21514d8981	725	* @rmtoll CR1 CRCEN LL_SPI_DisableCRC
AnnaBridge	156:ff21514d8981	726	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	727	* @retval None
AnnaBridge	156:ff21514d8981	728	*/
AnnaBridge	156:ff21514d8981	729	__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	730	{
AnnaBridge	156:ff21514d8981	731	CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
AnnaBridge	156:ff21514d8981	732	}
AnnaBridge	156:ff21514d8981	733
AnnaBridge	156:ff21514d8981	734	/**
AnnaBridge	156:ff21514d8981	735	* @brief Check if CRC is enabled
AnnaBridge	156:ff21514d8981	736	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge	156:ff21514d8981	737	* @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
AnnaBridge	156:ff21514d8981	738	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	739	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	740	*/
AnnaBridge	156:ff21514d8981	741	__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	742	{
AnnaBridge	156:ff21514d8981	743	return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN));
AnnaBridge	156:ff21514d8981	744	}
AnnaBridge	156:ff21514d8981	745
AnnaBridge	156:ff21514d8981	746	/**
AnnaBridge	156:ff21514d8981	747	* @brief Set CRC Length
AnnaBridge	156:ff21514d8981	748	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge	156:ff21514d8981	749	* @rmtoll CR1 CRCL LL_SPI_SetCRCWidth
AnnaBridge	156:ff21514d8981	750	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	751	* @param CRCLength This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	752	* @arg @ref LL_SPI_CRC_8BIT
AnnaBridge	156:ff21514d8981	753	* @arg @ref LL_SPI_CRC_16BIT
AnnaBridge	156:ff21514d8981	754	* @retval None
AnnaBridge	156:ff21514d8981	755	*/
AnnaBridge	156:ff21514d8981	756	__STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
AnnaBridge	156:ff21514d8981	757	{
AnnaBridge	156:ff21514d8981	758	MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength);
AnnaBridge	156:ff21514d8981	759	}
AnnaBridge	156:ff21514d8981	760
AnnaBridge	156:ff21514d8981	761	/**
AnnaBridge	156:ff21514d8981	762	* @brief Get CRC Length
AnnaBridge	156:ff21514d8981	763	* @rmtoll CR1 CRCL LL_SPI_GetCRCWidth
AnnaBridge	156:ff21514d8981	764	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	765	* @retval Returned value can be one of the following values:
AnnaBridge	156:ff21514d8981	766	* @arg @ref LL_SPI_CRC_8BIT
AnnaBridge	156:ff21514d8981	767	* @arg @ref LL_SPI_CRC_16BIT
AnnaBridge	156:ff21514d8981	768	*/
AnnaBridge	156:ff21514d8981	769	__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	770	{
AnnaBridge	156:ff21514d8981	771	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL));
AnnaBridge	156:ff21514d8981	772	}
AnnaBridge	156:ff21514d8981	773
AnnaBridge	156:ff21514d8981	774	/**
AnnaBridge	156:ff21514d8981	775	* @brief Set CRCNext to transfer CRC on the line
AnnaBridge	156:ff21514d8981	776	* @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
AnnaBridge	156:ff21514d8981	777	* @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
AnnaBridge	156:ff21514d8981	778	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	779	* @retval None
AnnaBridge	156:ff21514d8981	780	*/
AnnaBridge	156:ff21514d8981	781	__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	782	{
AnnaBridge	156:ff21514d8981	783	SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
AnnaBridge	156:ff21514d8981	784	}
AnnaBridge	156:ff21514d8981	785
AnnaBridge	156:ff21514d8981	786	/**
AnnaBridge	156:ff21514d8981	787	* @brief Set polynomial for CRC calculation
AnnaBridge	156:ff21514d8981	788	* @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
AnnaBridge	156:ff21514d8981	789	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	790	* @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
AnnaBridge	156:ff21514d8981	791	* @retval None
AnnaBridge	156:ff21514d8981	792	*/
AnnaBridge	156:ff21514d8981	793	__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
AnnaBridge	156:ff21514d8981	794	{
AnnaBridge	156:ff21514d8981	795	WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
AnnaBridge	156:ff21514d8981	796	}
AnnaBridge	156:ff21514d8981	797
AnnaBridge	156:ff21514d8981	798	/**
AnnaBridge	156:ff21514d8981	799	* @brief Get polynomial for CRC calculation
AnnaBridge	156:ff21514d8981	800	* @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
AnnaBridge	156:ff21514d8981	801	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	802	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
AnnaBridge	156:ff21514d8981	803	*/
AnnaBridge	156:ff21514d8981	804	__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	805	{
AnnaBridge	156:ff21514d8981	806	return (uint32_t)(READ_REG(SPIx->CRCPR));
AnnaBridge	156:ff21514d8981	807	}
AnnaBridge	156:ff21514d8981	808
AnnaBridge	156:ff21514d8981	809	/**
AnnaBridge	156:ff21514d8981	810	* @brief Get Rx CRC
AnnaBridge	156:ff21514d8981	811	* @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
AnnaBridge	156:ff21514d8981	812	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	813	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
AnnaBridge	156:ff21514d8981	814	*/
AnnaBridge	156:ff21514d8981	815	__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	816	{
AnnaBridge	156:ff21514d8981	817	return (uint32_t)(READ_REG(SPIx->RXCRCR));
AnnaBridge	156:ff21514d8981	818	}
AnnaBridge	156:ff21514d8981	819
AnnaBridge	156:ff21514d8981	820	/**
AnnaBridge	156:ff21514d8981	821	* @brief Get Tx CRC
AnnaBridge	156:ff21514d8981	822	* @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
AnnaBridge	156:ff21514d8981	823	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	824	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
AnnaBridge	156:ff21514d8981	825	*/
AnnaBridge	156:ff21514d8981	826	__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	827	{
AnnaBridge	156:ff21514d8981	828	return (uint32_t)(READ_REG(SPIx->TXCRCR));
AnnaBridge	156:ff21514d8981	829	}
AnnaBridge	156:ff21514d8981	830
AnnaBridge	156:ff21514d8981	831	/**
AnnaBridge	156:ff21514d8981	832	* @}
AnnaBridge	156:ff21514d8981	833	*/
AnnaBridge	156:ff21514d8981	834
AnnaBridge	156:ff21514d8981	835	/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
AnnaBridge	156:ff21514d8981	836	* @{
AnnaBridge	156:ff21514d8981	837	*/
AnnaBridge	156:ff21514d8981	838
AnnaBridge	156:ff21514d8981	839	/**
AnnaBridge	156:ff21514d8981	840	* @brief Set NSS mode
AnnaBridge	156:ff21514d8981	841	* @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
AnnaBridge	156:ff21514d8981	842	* @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
AnnaBridge	156:ff21514d8981	843	* @rmtoll CR2 SSOE LL_SPI_SetNSSMode
AnnaBridge	156:ff21514d8981	844	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	845	* @param NSS This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	846	* @arg @ref LL_SPI_NSS_SOFT
AnnaBridge	156:ff21514d8981	847	* @arg @ref LL_SPI_NSS_HARD_INPUT
AnnaBridge	156:ff21514d8981	848	* @arg @ref LL_SPI_NSS_HARD_OUTPUT
AnnaBridge	156:ff21514d8981	849	* @retval None
AnnaBridge	156:ff21514d8981	850	*/
AnnaBridge	156:ff21514d8981	851	__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
AnnaBridge	156:ff21514d8981	852	{
AnnaBridge	156:ff21514d8981	853	MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
AnnaBridge	156:ff21514d8981	854	MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
AnnaBridge	156:ff21514d8981	855	}
AnnaBridge	156:ff21514d8981	856
AnnaBridge	156:ff21514d8981	857	/**
AnnaBridge	156:ff21514d8981	858	* @brief Get NSS mode
AnnaBridge	156:ff21514d8981	859	* @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
AnnaBridge	156:ff21514d8981	860	* @rmtoll CR2 SSOE LL_SPI_GetNSSMode
AnnaBridge	156:ff21514d8981	861	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	862	* @retval Returned value can be one of the following values:
AnnaBridge	156:ff21514d8981	863	* @arg @ref LL_SPI_NSS_SOFT
AnnaBridge	156:ff21514d8981	864	* @arg @ref LL_SPI_NSS_HARD_INPUT
AnnaBridge	156:ff21514d8981	865	* @arg @ref LL_SPI_NSS_HARD_OUTPUT
AnnaBridge	156:ff21514d8981	866	*/
AnnaBridge	156:ff21514d8981	867	__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	868	{
AnnaBridge	156:ff21514d8981	869	register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
AnnaBridge	156:ff21514d8981	870	register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
AnnaBridge	156:ff21514d8981	871	return (Ssm \| Ssoe);
AnnaBridge	156:ff21514d8981	872	}
AnnaBridge	156:ff21514d8981	873
AnnaBridge	156:ff21514d8981	874	/**
AnnaBridge	156:ff21514d8981	875	* @brief Enable NSS pulse management
AnnaBridge	156:ff21514d8981	876	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
AnnaBridge	156:ff21514d8981	877	* @rmtoll CR2 NSSP LL_SPI_EnableNSSPulseMgt
AnnaBridge	156:ff21514d8981	878	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	879	* @retval None
AnnaBridge	156:ff21514d8981	880	*/
AnnaBridge	156:ff21514d8981	881	__STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	882	{
AnnaBridge	156:ff21514d8981	883	SET_BIT(SPIx->CR2, SPI_CR2_NSSP);
AnnaBridge	156:ff21514d8981	884	}
AnnaBridge	156:ff21514d8981	885
AnnaBridge	156:ff21514d8981	886	/**
AnnaBridge	156:ff21514d8981	887	* @brief Disable NSS pulse management
AnnaBridge	156:ff21514d8981	888	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
AnnaBridge	156:ff21514d8981	889	* @rmtoll CR2 NSSP LL_SPI_DisableNSSPulseMgt
AnnaBridge	156:ff21514d8981	890	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	891	* @retval None
AnnaBridge	156:ff21514d8981	892	*/
AnnaBridge	156:ff21514d8981	893	__STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	894	{
AnnaBridge	156:ff21514d8981	895	CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP);
AnnaBridge	156:ff21514d8981	896	}
AnnaBridge	156:ff21514d8981	897
AnnaBridge	156:ff21514d8981	898	/**
AnnaBridge	156:ff21514d8981	899	* @brief Check if NSS pulse is enabled
AnnaBridge	156:ff21514d8981	900	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
AnnaBridge	156:ff21514d8981	901	* @rmtoll CR2 NSSP LL_SPI_IsEnabledNSSPulse
AnnaBridge	156:ff21514d8981	902	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	903	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	904	*/
AnnaBridge	156:ff21514d8981	905	__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	906	{
AnnaBridge	156:ff21514d8981	907	return (READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP));
AnnaBridge	156:ff21514d8981	908	}
AnnaBridge	156:ff21514d8981	909
AnnaBridge	156:ff21514d8981	910	/**
AnnaBridge	156:ff21514d8981	911	* @}
AnnaBridge	156:ff21514d8981	912	*/
AnnaBridge	156:ff21514d8981	913
AnnaBridge	156:ff21514d8981	914	/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
AnnaBridge	156:ff21514d8981	915	* @{
AnnaBridge	156:ff21514d8981	916	*/
AnnaBridge	156:ff21514d8981	917
AnnaBridge	156:ff21514d8981	918	/**
AnnaBridge	156:ff21514d8981	919	* @brief Check if Rx buffer is not empty
AnnaBridge	156:ff21514d8981	920	* @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
AnnaBridge	156:ff21514d8981	921	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	922	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	923	*/
AnnaBridge	156:ff21514d8981	924	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	925	{
AnnaBridge	156:ff21514d8981	926	return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE));
AnnaBridge	156:ff21514d8981	927	}
AnnaBridge	156:ff21514d8981	928
AnnaBridge	156:ff21514d8981	929	/**
AnnaBridge	156:ff21514d8981	930	* @brief Check if Tx buffer is empty
AnnaBridge	156:ff21514d8981	931	* @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
AnnaBridge	156:ff21514d8981	932	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	933	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	934	*/
AnnaBridge	156:ff21514d8981	935	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	936	{
AnnaBridge	156:ff21514d8981	937	return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE));
AnnaBridge	156:ff21514d8981	938	}
AnnaBridge	156:ff21514d8981	939
AnnaBridge	156:ff21514d8981	940	/**
AnnaBridge	156:ff21514d8981	941	* @brief Get CRC error flag
AnnaBridge	156:ff21514d8981	942	* @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
AnnaBridge	156:ff21514d8981	943	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	944	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	945	*/
AnnaBridge	156:ff21514d8981	946	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	947	{
AnnaBridge	156:ff21514d8981	948	return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR));
AnnaBridge	156:ff21514d8981	949	}
AnnaBridge	156:ff21514d8981	950
AnnaBridge	156:ff21514d8981	951	/**
AnnaBridge	156:ff21514d8981	952	* @brief Get mode fault error flag
AnnaBridge	156:ff21514d8981	953	* @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
AnnaBridge	156:ff21514d8981	954	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	955	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	956	*/
AnnaBridge	156:ff21514d8981	957	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	958	{
AnnaBridge	156:ff21514d8981	959	return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF));
AnnaBridge	156:ff21514d8981	960	}
AnnaBridge	156:ff21514d8981	961
AnnaBridge	156:ff21514d8981	962	/**
AnnaBridge	156:ff21514d8981	963	* @brief Get overrun error flag
AnnaBridge	156:ff21514d8981	964	* @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
AnnaBridge	156:ff21514d8981	965	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	966	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	967	*/
AnnaBridge	156:ff21514d8981	968	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	969	{
AnnaBridge	156:ff21514d8981	970	return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR));
AnnaBridge	156:ff21514d8981	971	}
AnnaBridge	156:ff21514d8981	972
AnnaBridge	156:ff21514d8981	973	/**
AnnaBridge	156:ff21514d8981	974	* @brief Get busy flag
AnnaBridge	156:ff21514d8981	975	* @note The BSY flag is cleared under any one of the following conditions:
AnnaBridge	156:ff21514d8981	976	* -When the SPI is correctly disabled
AnnaBridge	156:ff21514d8981	977	* -When a fault is detected in Master mode (MODF bit set to 1)
AnnaBridge	156:ff21514d8981	978	* -In Master mode, when it finishes a data transmission and no new data is ready to be
AnnaBridge	156:ff21514d8981	979	* sent
AnnaBridge	156:ff21514d8981	980	* -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
AnnaBridge	156:ff21514d8981	981	* each data transfer.
AnnaBridge	156:ff21514d8981	982	* @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
AnnaBridge	156:ff21514d8981	983	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	984	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	985	*/
AnnaBridge	156:ff21514d8981	986	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	987	{
AnnaBridge	156:ff21514d8981	988	return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY));
AnnaBridge	156:ff21514d8981	989	}
AnnaBridge	156:ff21514d8981	990
AnnaBridge	156:ff21514d8981	991	/**
AnnaBridge	156:ff21514d8981	992	* @brief Get frame format error flag
AnnaBridge	156:ff21514d8981	993	* @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE
AnnaBridge	156:ff21514d8981	994	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	995	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	996	*/
AnnaBridge	156:ff21514d8981	997	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	998	{
AnnaBridge	156:ff21514d8981	999	return (READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE));
AnnaBridge	156:ff21514d8981	1000	}
AnnaBridge	156:ff21514d8981	1001
AnnaBridge	156:ff21514d8981	1002	/**
AnnaBridge	156:ff21514d8981	1003	* @brief Get FIFO reception Level
AnnaBridge	156:ff21514d8981	1004	* @rmtoll SR FRLVL LL_SPI_GetRxFIFOLevel
AnnaBridge	156:ff21514d8981	1005	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	1006	* @retval Returned value can be one of the following values:
AnnaBridge	156:ff21514d8981	1007	* @arg @ref LL_SPI_RX_FIFO_EMPTY
AnnaBridge	156:ff21514d8981	1008	* @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL
AnnaBridge	156:ff21514d8981	1009	* @arg @ref LL_SPI_RX_FIFO_HALF_FULL
AnnaBridge	156:ff21514d8981	1010	* @arg @ref LL_SPI_RX_FIFO_FULL
AnnaBridge	156:ff21514d8981	1011	*/
AnnaBridge	156:ff21514d8981	1012	__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	1013	{
AnnaBridge	156:ff21514d8981	1014	return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL));
AnnaBridge	156:ff21514d8981	1015	}
AnnaBridge	156:ff21514d8981	1016
AnnaBridge	156:ff21514d8981	1017	/**
AnnaBridge	156:ff21514d8981	1018	* @brief Get FIFO Transmission Level
AnnaBridge	156:ff21514d8981	1019	* @rmtoll SR FTLVL LL_SPI_GetTxFIFOLevel
AnnaBridge	156:ff21514d8981	1020	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	1021	* @retval Returned value can be one of the following values:
AnnaBridge	156:ff21514d8981	1022	* @arg @ref LL_SPI_TX_FIFO_EMPTY
AnnaBridge	156:ff21514d8981	1023	* @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL
AnnaBridge	156:ff21514d8981	1024	* @arg @ref LL_SPI_TX_FIFO_HALF_FULL
AnnaBridge	156:ff21514d8981	1025	* @arg @ref LL_SPI_TX_FIFO_FULL
AnnaBridge	156:ff21514d8981	1026	*/
AnnaBridge	156:ff21514d8981	1027	__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	1028	{
AnnaBridge	156:ff21514d8981	1029	return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL));
AnnaBridge	156:ff21514d8981	1030	}
AnnaBridge	156:ff21514d8981	1031
AnnaBridge	156:ff21514d8981	1032	/**
AnnaBridge	156:ff21514d8981	1033	* @brief Clear CRC error flag
AnnaBridge	156:ff21514d8981	1034	* @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
AnnaBridge	156:ff21514d8981	1035	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	1036	* @retval None
AnnaBridge	156:ff21514d8981	1037	*/
AnnaBridge	156:ff21514d8981	1038	__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	1039	{
AnnaBridge	156:ff21514d8981	1040	CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
AnnaBridge	156:ff21514d8981	1041	}
AnnaBridge	156:ff21514d8981	1042
AnnaBridge	156:ff21514d8981	1043	/**
AnnaBridge	156:ff21514d8981	1044	* @brief Clear mode fault error flag
AnnaBridge	156:ff21514d8981	1045	* @note Clearing this flag is done by a read access to the SPIx_SR
AnnaBridge	156:ff21514d8981	1046	* register followed by a write access to the SPIx_CR1 register
AnnaBridge	156:ff21514d8981	1047	* @rmtoll SR MODF LL_SPI_ClearFlag_MODF
AnnaBridge	156:ff21514d8981	1048	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	1049	* @retval None
AnnaBridge	156:ff21514d8981	1050	*/
AnnaBridge	156:ff21514d8981	1051	__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	1052	{
AnnaBridge	156:ff21514d8981	1053	__IO uint32_t tmpreg;
AnnaBridge	156:ff21514d8981	1054	tmpreg = SPIx->SR;
AnnaBridge	156:ff21514d8981	1055	(void) tmpreg;
AnnaBridge	156:ff21514d8981	1056	tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
AnnaBridge	156:ff21514d8981	1057	(void) tmpreg;
AnnaBridge	156:ff21514d8981	1058	}
AnnaBridge	156:ff21514d8981	1059
AnnaBridge	156:ff21514d8981	1060	/**
AnnaBridge	156:ff21514d8981	1061	* @brief Clear overrun error flag
AnnaBridge	156:ff21514d8981	1062	* @note Clearing this flag is done by a read access to the SPIx_DR
AnnaBridge	156:ff21514d8981	1063	* register followed by a read access to the SPIx_SR register
AnnaBridge	156:ff21514d8981	1064	* @rmtoll SR OVR LL_SPI_ClearFlag_OVR
AnnaBridge	156:ff21514d8981	1065	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	1066	* @retval None
AnnaBridge	156:ff21514d8981	1067	*/
AnnaBridge	156:ff21514d8981	1068	__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	1069	{
AnnaBridge	156:ff21514d8981	1070	__IO uint32_t tmpreg;
AnnaBridge	156:ff21514d8981	1071	tmpreg = SPIx->DR;
AnnaBridge	156:ff21514d8981	1072	(void) tmpreg;
AnnaBridge	156:ff21514d8981	1073	tmpreg = SPIx->SR;
AnnaBridge	156:ff21514d8981	1074	(void) tmpreg;
AnnaBridge	156:ff21514d8981	1075	}
AnnaBridge	156:ff21514d8981	1076
AnnaBridge	156:ff21514d8981	1077	/**
AnnaBridge	156:ff21514d8981	1078	* @brief Clear frame format error flag
AnnaBridge	156:ff21514d8981	1079	* @note Clearing this flag is done by reading SPIx_SR register
AnnaBridge	156:ff21514d8981	1080	* @rmtoll SR FRE LL_SPI_ClearFlag_FRE
AnnaBridge	156:ff21514d8981	1081	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	1082	* @retval None
AnnaBridge	156:ff21514d8981	1083	*/
AnnaBridge	156:ff21514d8981	1084	__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	1085	{
AnnaBridge	156:ff21514d8981	1086	__IO uint32_t tmpreg;
AnnaBridge	156:ff21514d8981	1087	tmpreg = SPIx->SR;
AnnaBridge	156:ff21514d8981	1088	(void) tmpreg;
AnnaBridge	156:ff21514d8981	1089	}
AnnaBridge	156:ff21514d8981	1090
AnnaBridge	156:ff21514d8981	1091	/**
AnnaBridge	156:ff21514d8981	1092	* @}
AnnaBridge	156:ff21514d8981	1093	*/
AnnaBridge	156:ff21514d8981	1094
AnnaBridge	156:ff21514d8981	1095	/** @defgroup SPI_LL_EF_IT_Management Interrupt Management
AnnaBridge	156:ff21514d8981	1096	* @{
AnnaBridge	156:ff21514d8981	1097	*/
AnnaBridge	156:ff21514d8981	1098
AnnaBridge	156:ff21514d8981	1099	/**
AnnaBridge	156:ff21514d8981	1100	* @brief Enable error interrupt
AnnaBridge	156:ff21514d8981	1101	* @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
AnnaBridge	156:ff21514d8981	1102	* @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
AnnaBridge	156:ff21514d8981	1103	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	1104	* @retval None
AnnaBridge	156:ff21514d8981	1105	*/
AnnaBridge	156:ff21514d8981	1106	__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	1107	{
AnnaBridge	156:ff21514d8981	1108	SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
AnnaBridge	156:ff21514d8981	1109	}
AnnaBridge	156:ff21514d8981	1110
AnnaBridge	156:ff21514d8981	1111	/**
AnnaBridge	156:ff21514d8981	1112	* @brief Enable Rx buffer not empty interrupt
AnnaBridge	156:ff21514d8981	1113	* @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
AnnaBridge	156:ff21514d8981	1114	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	1115	* @retval None
AnnaBridge	156:ff21514d8981	1116	*/
AnnaBridge	156:ff21514d8981	1117	__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	1118	{
AnnaBridge	156:ff21514d8981	1119	SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
AnnaBridge	156:ff21514d8981	1120	}
AnnaBridge	156:ff21514d8981	1121
AnnaBridge	156:ff21514d8981	1122	/**
AnnaBridge	156:ff21514d8981	1123	* @brief Enable Tx buffer empty interrupt
AnnaBridge	156:ff21514d8981	1124	* @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
AnnaBridge	156:ff21514d8981	1125	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	1126	* @retval None
AnnaBridge	156:ff21514d8981	1127	*/
AnnaBridge	156:ff21514d8981	1128	__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	1129	{
AnnaBridge	156:ff21514d8981	1130	SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
AnnaBridge	156:ff21514d8981	1131	}
AnnaBridge	156:ff21514d8981	1132
AnnaBridge	156:ff21514d8981	1133	/**
AnnaBridge	156:ff21514d8981	1134	* @brief Disable error interrupt
AnnaBridge	156:ff21514d8981	1135	* @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
AnnaBridge	156:ff21514d8981	1136	* @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
AnnaBridge	156:ff21514d8981	1137	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	1138	* @retval None
AnnaBridge	156:ff21514d8981	1139	*/
AnnaBridge	156:ff21514d8981	1140	__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	1141	{
AnnaBridge	156:ff21514d8981	1142	CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
AnnaBridge	156:ff21514d8981	1143	}
AnnaBridge	156:ff21514d8981	1144
AnnaBridge	156:ff21514d8981	1145	/**
AnnaBridge	156:ff21514d8981	1146	* @brief Disable Rx buffer not empty interrupt
AnnaBridge	156:ff21514d8981	1147	* @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
AnnaBridge	156:ff21514d8981	1148	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	1149	* @retval None
AnnaBridge	156:ff21514d8981	1150	*/
AnnaBridge	156:ff21514d8981	1151	__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	1152	{
AnnaBridge	156:ff21514d8981	1153	CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
AnnaBridge	156:ff21514d8981	1154	}
AnnaBridge	156:ff21514d8981	1155
AnnaBridge	156:ff21514d8981	1156	/**
AnnaBridge	156:ff21514d8981	1157	* @brief Disable Tx buffer empty interrupt
AnnaBridge	156:ff21514d8981	1158	* @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
AnnaBridge	156:ff21514d8981	1159	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	1160	* @retval None
AnnaBridge	156:ff21514d8981	1161	*/
AnnaBridge	156:ff21514d8981	1162	__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	1163	{
AnnaBridge	156:ff21514d8981	1164	CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
AnnaBridge	156:ff21514d8981	1165	}
AnnaBridge	156:ff21514d8981	1166
AnnaBridge	156:ff21514d8981	1167	/**
AnnaBridge	156:ff21514d8981	1168	* @brief Check if error interrupt is enabled
AnnaBridge	156:ff21514d8981	1169	* @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
AnnaBridge	156:ff21514d8981	1170	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	1171	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1172	*/
AnnaBridge	156:ff21514d8981	1173	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	1174	{
AnnaBridge	156:ff21514d8981	1175	return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE));
AnnaBridge	156:ff21514d8981	1176	}
AnnaBridge	156:ff21514d8981	1177
AnnaBridge	156:ff21514d8981	1178	/**
AnnaBridge	156:ff21514d8981	1179	* @brief Check if Rx buffer not empty interrupt is enabled
AnnaBridge	156:ff21514d8981	1180	* @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
AnnaBridge	156:ff21514d8981	1181	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	1182	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1183	*/
AnnaBridge	156:ff21514d8981	1184	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	1185	{
AnnaBridge	156:ff21514d8981	1186	return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE));
AnnaBridge	156:ff21514d8981	1187	}
AnnaBridge	156:ff21514d8981	1188
AnnaBridge	156:ff21514d8981	1189	/**
AnnaBridge	156:ff21514d8981	1190	* @brief Check if Tx buffer empty interrupt
AnnaBridge	156:ff21514d8981	1191	* @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
AnnaBridge	156:ff21514d8981	1192	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	1193	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1194	*/
AnnaBridge	156:ff21514d8981	1195	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	1196	{
AnnaBridge	156:ff21514d8981	1197	return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE));
AnnaBridge	156:ff21514d8981	1198	}
AnnaBridge	156:ff21514d8981	1199
AnnaBridge	156:ff21514d8981	1200	/**
AnnaBridge	156:ff21514d8981	1201	* @}
AnnaBridge	156:ff21514d8981	1202	*/
AnnaBridge	156:ff21514d8981	1203
AnnaBridge	156:ff21514d8981	1204	/** @defgroup SPI_LL_EF_DMA_Management DMA Management
AnnaBridge	156:ff21514d8981	1205	* @{
AnnaBridge	156:ff21514d8981	1206	*/
AnnaBridge	156:ff21514d8981	1207
AnnaBridge	156:ff21514d8981	1208	/**
AnnaBridge	156:ff21514d8981	1209	* @brief Enable DMA Rx
AnnaBridge	156:ff21514d8981	1210	* @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
AnnaBridge	156:ff21514d8981	1211	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	1212	* @retval None
AnnaBridge	156:ff21514d8981	1213	*/
AnnaBridge	156:ff21514d8981	1214	__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	1215	{
AnnaBridge	156:ff21514d8981	1216	SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
AnnaBridge	156:ff21514d8981	1217	}
AnnaBridge	156:ff21514d8981	1218
AnnaBridge	156:ff21514d8981	1219	/**
AnnaBridge	156:ff21514d8981	1220	* @brief Disable DMA Rx
AnnaBridge	156:ff21514d8981	1221	* @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
AnnaBridge	156:ff21514d8981	1222	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	1223	* @retval None
AnnaBridge	156:ff21514d8981	1224	*/
AnnaBridge	156:ff21514d8981	1225	__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	1226	{
AnnaBridge	156:ff21514d8981	1227	CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
AnnaBridge	156:ff21514d8981	1228	}
AnnaBridge	156:ff21514d8981	1229
AnnaBridge	156:ff21514d8981	1230	/**
AnnaBridge	156:ff21514d8981	1231	* @brief Check if DMA Rx is enabled
AnnaBridge	156:ff21514d8981	1232	* @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
AnnaBridge	156:ff21514d8981	1233	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	1234	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1235	*/
AnnaBridge	156:ff21514d8981	1236	__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	1237	{
AnnaBridge	156:ff21514d8981	1238	return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN));
AnnaBridge	156:ff21514d8981	1239	}
AnnaBridge	156:ff21514d8981	1240
AnnaBridge	156:ff21514d8981	1241	/**
AnnaBridge	156:ff21514d8981	1242	* @brief Enable DMA Tx
AnnaBridge	156:ff21514d8981	1243	* @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
AnnaBridge	156:ff21514d8981	1244	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	1245	* @retval None
AnnaBridge	156:ff21514d8981	1246	*/
AnnaBridge	156:ff21514d8981	1247	__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	1248	{
AnnaBridge	156:ff21514d8981	1249	SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
AnnaBridge	156:ff21514d8981	1250	}
AnnaBridge	156:ff21514d8981	1251
AnnaBridge	156:ff21514d8981	1252	/**
AnnaBridge	156:ff21514d8981	1253	* @brief Disable DMA Tx
AnnaBridge	156:ff21514d8981	1254	* @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
AnnaBridge	156:ff21514d8981	1255	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	1256	* @retval None
AnnaBridge	156:ff21514d8981	1257	*/
AnnaBridge	156:ff21514d8981	1258	__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	1259	{
AnnaBridge	156:ff21514d8981	1260	CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
AnnaBridge	156:ff21514d8981	1261	}
AnnaBridge	156:ff21514d8981	1262
AnnaBridge	156:ff21514d8981	1263	/**
AnnaBridge	156:ff21514d8981	1264	* @brief Check if DMA Tx is enabled
AnnaBridge	156:ff21514d8981	1265	* @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
AnnaBridge	156:ff21514d8981	1266	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	1267	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1268	*/
AnnaBridge	156:ff21514d8981	1269	__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	1270	{
AnnaBridge	156:ff21514d8981	1271	return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN));
AnnaBridge	156:ff21514d8981	1272	}
AnnaBridge	156:ff21514d8981	1273
AnnaBridge	156:ff21514d8981	1274	/**
AnnaBridge	156:ff21514d8981	1275	* @brief Set parity of Last DMA reception
AnnaBridge	156:ff21514d8981	1276	* @rmtoll CR2 LDMARX LL_SPI_SetDMAParity_RX
AnnaBridge	156:ff21514d8981	1277	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	1278	* @param Parity This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	1279	* @arg @ref LL_SPI_DMA_PARITY_ODD
AnnaBridge	156:ff21514d8981	1280	* @arg @ref LL_SPI_DMA_PARITY_EVEN
AnnaBridge	156:ff21514d8981	1281	* @retval None
AnnaBridge	156:ff21514d8981	1282	*/
AnnaBridge	156:ff21514d8981	1283	__STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity)
AnnaBridge	156:ff21514d8981	1284	{
AnnaBridge	156:ff21514d8981	1285	MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << SPI_CR2_LDMARX_Pos));
AnnaBridge	156:ff21514d8981	1286	}
AnnaBridge	156:ff21514d8981	1287
AnnaBridge	156:ff21514d8981	1288	/**
AnnaBridge	156:ff21514d8981	1289	* @brief Get parity configuration for Last DMA reception
AnnaBridge	156:ff21514d8981	1290	* @rmtoll CR2 LDMARX LL_SPI_GetDMAParity_RX
AnnaBridge	156:ff21514d8981	1291	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	1292	* @retval Returned value can be one of the following values:
AnnaBridge	156:ff21514d8981	1293	* @arg @ref LL_SPI_DMA_PARITY_ODD
AnnaBridge	156:ff21514d8981	1294	* @arg @ref LL_SPI_DMA_PARITY_EVEN
AnnaBridge	156:ff21514d8981	1295	*/
AnnaBridge	156:ff21514d8981	1296	__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	1297	{
AnnaBridge	156:ff21514d8981	1298	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos);
AnnaBridge	156:ff21514d8981	1299	}
AnnaBridge	156:ff21514d8981	1300
AnnaBridge	156:ff21514d8981	1301	/**
AnnaBridge	156:ff21514d8981	1302	* @brief Set parity of Last DMA transmission
AnnaBridge	156:ff21514d8981	1303	* @rmtoll CR2 LDMATX LL_SPI_SetDMAParity_TX
AnnaBridge	156:ff21514d8981	1304	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	1305	* @param Parity This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	1306	* @arg @ref LL_SPI_DMA_PARITY_ODD
AnnaBridge	156:ff21514d8981	1307	* @arg @ref LL_SPI_DMA_PARITY_EVEN
AnnaBridge	156:ff21514d8981	1308	* @retval None
AnnaBridge	156:ff21514d8981	1309	*/
AnnaBridge	156:ff21514d8981	1310	__STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity)
AnnaBridge	156:ff21514d8981	1311	{
AnnaBridge	156:ff21514d8981	1312	MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << SPI_CR2_LDMATX_Pos));
AnnaBridge	156:ff21514d8981	1313	}
AnnaBridge	156:ff21514d8981	1314
AnnaBridge	156:ff21514d8981	1315	/**
AnnaBridge	156:ff21514d8981	1316	* @brief Get parity configuration for Last DMA transmission
AnnaBridge	156:ff21514d8981	1317	* @rmtoll CR2 LDMATX LL_SPI_GetDMAParity_TX
AnnaBridge	156:ff21514d8981	1318	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	1319	* @retval Returned value can be one of the following values:
AnnaBridge	156:ff21514d8981	1320	* @arg @ref LL_SPI_DMA_PARITY_ODD
AnnaBridge	156:ff21514d8981	1321	* @arg @ref LL_SPI_DMA_PARITY_EVEN
AnnaBridge	156:ff21514d8981	1322	*/
AnnaBridge	156:ff21514d8981	1323	__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	1324	{
AnnaBridge	156:ff21514d8981	1325	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos);
AnnaBridge	156:ff21514d8981	1326	}
AnnaBridge	156:ff21514d8981	1327
AnnaBridge	156:ff21514d8981	1328	/**
AnnaBridge	156:ff21514d8981	1329	* @brief Get the data register address used for DMA transfer
AnnaBridge	156:ff21514d8981	1330	* @rmtoll DR DR LL_SPI_DMA_GetRegAddr
AnnaBridge	156:ff21514d8981	1331	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	1332	* @retval Address of data register
AnnaBridge	156:ff21514d8981	1333	*/
AnnaBridge	156:ff21514d8981	1334	__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	1335	{
AnnaBridge	156:ff21514d8981	1336	return (uint32_t) & (SPIx->DR);
AnnaBridge	156:ff21514d8981	1337	}
AnnaBridge	156:ff21514d8981	1338
AnnaBridge	156:ff21514d8981	1339	/**
AnnaBridge	156:ff21514d8981	1340	* @}
AnnaBridge	156:ff21514d8981	1341	*/
AnnaBridge	156:ff21514d8981	1342
AnnaBridge	156:ff21514d8981	1343	/** @defgroup SPI_LL_EF_DATA_Management DATA Management
AnnaBridge	156:ff21514d8981	1344	* @{
AnnaBridge	156:ff21514d8981	1345	*/
AnnaBridge	156:ff21514d8981	1346
AnnaBridge	156:ff21514d8981	1347	/**
AnnaBridge	156:ff21514d8981	1348	* @brief Read 8-Bits in the data register
AnnaBridge	156:ff21514d8981	1349	* @rmtoll DR DR LL_SPI_ReceiveData8
AnnaBridge	156:ff21514d8981	1350	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	1351	* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	156:ff21514d8981	1352	*/
AnnaBridge	156:ff21514d8981	1353	__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	1354	{
AnnaBridge	156:ff21514d8981	1355	return (uint8_t)(READ_REG(SPIx->DR));
AnnaBridge	156:ff21514d8981	1356	}
AnnaBridge	156:ff21514d8981	1357
AnnaBridge	156:ff21514d8981	1358	/**
AnnaBridge	156:ff21514d8981	1359	* @brief Read 16-Bits in the data register
AnnaBridge	156:ff21514d8981	1360	* @rmtoll DR DR LL_SPI_ReceiveData16
AnnaBridge	156:ff21514d8981	1361	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	1362	* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
AnnaBridge	156:ff21514d8981	1363	*/
AnnaBridge	156:ff21514d8981	1364	__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
AnnaBridge	156:ff21514d8981	1365	{
AnnaBridge	156:ff21514d8981	1366	return (uint16_t)(READ_REG(SPIx->DR));
AnnaBridge	156:ff21514d8981	1367	}
AnnaBridge	156:ff21514d8981	1368
AnnaBridge	156:ff21514d8981	1369	/**
AnnaBridge	156:ff21514d8981	1370	* @brief Write 8-Bits in the data register
AnnaBridge	156:ff21514d8981	1371	* @rmtoll DR DR LL_SPI_TransmitData8
AnnaBridge	156:ff21514d8981	1372	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	1373	* @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	156:ff21514d8981	1374	* @retval None
AnnaBridge	156:ff21514d8981	1375	*/
AnnaBridge	156:ff21514d8981	1376	__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
AnnaBridge	156:ff21514d8981	1377	{
AnnaBridge	156:ff21514d8981	1378	((__IO uint8_t )&SPIx->DR) = TxData;
AnnaBridge	156:ff21514d8981	1379	}
AnnaBridge	156:ff21514d8981	1380
AnnaBridge	156:ff21514d8981	1381	/**
AnnaBridge	156:ff21514d8981	1382	* @brief Write 16-Bits in the data register
AnnaBridge	156:ff21514d8981	1383	* @rmtoll DR DR LL_SPI_TransmitData16
AnnaBridge	156:ff21514d8981	1384	* @param SPIx SPI Instance
AnnaBridge	156:ff21514d8981	1385	* @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
AnnaBridge	156:ff21514d8981	1386	* @retval None
AnnaBridge	156:ff21514d8981	1387	*/
AnnaBridge	156:ff21514d8981	1388	__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
AnnaBridge	156:ff21514d8981	1389	{
AnnaBridge	156:ff21514d8981	1390	((__IO uint16_t )&SPIx->DR) = TxData;
AnnaBridge	156:ff21514d8981	1391	}
AnnaBridge	156:ff21514d8981	1392
AnnaBridge	156:ff21514d8981	1393	/**
AnnaBridge	156:ff21514d8981	1394	* @}
AnnaBridge	156:ff21514d8981	1395	*/
AnnaBridge	156:ff21514d8981	1396	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	156:ff21514d8981	1397	/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
AnnaBridge	156:ff21514d8981	1398	* @{
AnnaBridge	156:ff21514d8981	1399	*/
AnnaBridge	156:ff21514d8981	1400
AnnaBridge	156:ff21514d8981	1401	ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
AnnaBridge	156:ff21514d8981	1402	ErrorStatus LL_SPI_Init(SPI_TypeDef SPIx, LL_SPI_InitTypeDef SPI_InitStruct);
AnnaBridge	156:ff21514d8981	1403	void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
AnnaBridge	156:ff21514d8981	1404
AnnaBridge	156:ff21514d8981	1405	/**
AnnaBridge	156:ff21514d8981	1406	* @}
AnnaBridge	156:ff21514d8981	1407	*/
AnnaBridge	156:ff21514d8981	1408	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	156:ff21514d8981	1409	/**
AnnaBridge	156:ff21514d8981	1410	* @}
AnnaBridge	156:ff21514d8981	1411	*/
AnnaBridge	156:ff21514d8981	1412
AnnaBridge	156:ff21514d8981	1413	/**
AnnaBridge	156:ff21514d8981	1414	* @}
AnnaBridge	156:ff21514d8981	1415	*/
AnnaBridge	156:ff21514d8981	1416
AnnaBridge	156:ff21514d8981	1417	#endif /* defined (SPI1) \|\| defined (SPI2) \|\| defined (SPI3) */
AnnaBridge	156:ff21514d8981	1418
AnnaBridge	156:ff21514d8981	1419	/**
AnnaBridge	156:ff21514d8981	1420	* @}
AnnaBridge	156:ff21514d8981	1421	*/
AnnaBridge	156:ff21514d8981	1422
AnnaBridge	156:ff21514d8981	1423	#ifdef __cplusplus
AnnaBridge	156:ff21514d8981	1424	}
AnnaBridge	156:ff21514d8981	1425	#endif
AnnaBridge	156:ff21514d8981	1426
AnnaBridge	156:ff21514d8981	1427	#endif /* __STM32L4xx_LL_SPI_H */
AnnaBridge	156:ff21514d8981	1428
AnnaBridge	156:ff21514d8981	1429	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/