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TARGET_NUCLEO_L432KC/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h@156:ff21514d8981, 2017-11-08 (annotated)

Committer:
AnnaBridge
Date:
Wed Nov 08 17:18:06 2017 +0000
Revision:
156:ff21514d8981
Child:
161:aa5281ff4a02
Reverting back to release 154 of the mbed library

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 156:ff21514d8981 1 /**
AnnaBridge 156:ff21514d8981 2 ******************************************************************************
AnnaBridge 156:ff21514d8981 3 * @file stm32l4xx_hal_nor.h
AnnaBridge 156:ff21514d8981 4 * @author MCD Application Team
AnnaBridge 156:ff21514d8981 5 * @version V1.7.1
AnnaBridge 156:ff21514d8981 6 * @date 21-April-2017
AnnaBridge 156:ff21514d8981 7 * @brief Header file of NOR HAL module.
AnnaBridge 156:ff21514d8981 8 ******************************************************************************
AnnaBridge 156:ff21514d8981 9 * @attention
AnnaBridge 156:ff21514d8981 10 *
AnnaBridge 156:ff21514d8981 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 156:ff21514d8981 12 *
AnnaBridge 156:ff21514d8981 13 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 156:ff21514d8981 14 * are permitted provided that the following conditions are met:
AnnaBridge 156:ff21514d8981 15 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 156:ff21514d8981 16 * this list of conditions and the following disclaimer.
AnnaBridge 156:ff21514d8981 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 156:ff21514d8981 18 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 156:ff21514d8981 19 * and/or other materials provided with the distribution.
AnnaBridge 156:ff21514d8981 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 156:ff21514d8981 21 * may be used to endorse or promote products derived from this software
AnnaBridge 156:ff21514d8981 22 * without specific prior written permission.
AnnaBridge 156:ff21514d8981 23 *
AnnaBridge 156:ff21514d8981 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 156:ff21514d8981 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 156:ff21514d8981 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 156:ff21514d8981 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 156:ff21514d8981 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 156:ff21514d8981 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 156:ff21514d8981 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 156:ff21514d8981 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 156:ff21514d8981 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 156:ff21514d8981 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 156:ff21514d8981 34 *
AnnaBridge 156:ff21514d8981 35 ******************************************************************************
AnnaBridge 156:ff21514d8981 36 */
AnnaBridge 156:ff21514d8981 37
AnnaBridge 156:ff21514d8981 38 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 156:ff21514d8981 39 #ifndef __STM32L4xx_HAL_NOR_H
AnnaBridge 156:ff21514d8981 40 #define __STM32L4xx_HAL_NOR_H
AnnaBridge 156:ff21514d8981 41
AnnaBridge 156:ff21514d8981 42 #ifdef __cplusplus
AnnaBridge 156:ff21514d8981 43 extern "C" {
AnnaBridge 156:ff21514d8981 44 #endif
AnnaBridge 156:ff21514d8981 45
AnnaBridge 156:ff21514d8981 46 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
AnnaBridge 156:ff21514d8981 47 defined(STM32L496xx) || defined(STM32L4A6xx)
AnnaBridge 156:ff21514d8981 48
AnnaBridge 156:ff21514d8981 49 /* Includes ------------------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 50 #include "stm32l4xx_ll_fmc.h"
AnnaBridge 156:ff21514d8981 51
AnnaBridge 156:ff21514d8981 52
AnnaBridge 156:ff21514d8981 53 /** @addtogroup STM32L4xx_HAL_Driver
AnnaBridge 156:ff21514d8981 54 * @{
AnnaBridge 156:ff21514d8981 55 */
AnnaBridge 156:ff21514d8981 56
AnnaBridge 156:ff21514d8981 57 /** @addtogroup NOR
AnnaBridge 156:ff21514d8981 58 * @{
AnnaBridge 156:ff21514d8981 59 */
AnnaBridge 156:ff21514d8981 60
AnnaBridge 156:ff21514d8981 61 /** @addtogroup NOR_Private_Constants
AnnaBridge 156:ff21514d8981 62 * @{
AnnaBridge 156:ff21514d8981 63 */
AnnaBridge 156:ff21514d8981 64
AnnaBridge 156:ff21514d8981 65 /* NOR device IDs addresses */
AnnaBridge 156:ff21514d8981 66 #define MC_ADDRESS ((uint16_t)0x0000)
AnnaBridge 156:ff21514d8981 67 #define DEVICE_CODE1_ADDR ((uint16_t)0x0001)
AnnaBridge 156:ff21514d8981 68 #define DEVICE_CODE2_ADDR ((uint16_t)0x000E)
AnnaBridge 156:ff21514d8981 69 #define DEVICE_CODE3_ADDR ((uint16_t)0x000F)
AnnaBridge 156:ff21514d8981 70
AnnaBridge 156:ff21514d8981 71 /* NOR CFI IDs addresses */
AnnaBridge 156:ff21514d8981 72 #define CFI1_ADDRESS ((uint16_t)0x10)
AnnaBridge 156:ff21514d8981 73 #define CFI2_ADDRESS ((uint16_t)0x11)
AnnaBridge 156:ff21514d8981 74 #define CFI3_ADDRESS ((uint16_t)0x12)
AnnaBridge 156:ff21514d8981 75 #define CFI4_ADDRESS ((uint16_t)0x13)
AnnaBridge 156:ff21514d8981 76
AnnaBridge 156:ff21514d8981 77 /* NOR memory data width */
AnnaBridge 156:ff21514d8981 78 #define NOR_MEMORY_8B ((uint8_t)0x0)
AnnaBridge 156:ff21514d8981 79 #define NOR_MEMORY_16B ((uint8_t)0x1)
AnnaBridge 156:ff21514d8981 80
AnnaBridge 156:ff21514d8981 81 /* NOR memory device read/write start address */
AnnaBridge 156:ff21514d8981 82 #define NOR_MEMORY_ADRESS1 FMC_BANK1_1
AnnaBridge 156:ff21514d8981 83 #define NOR_MEMORY_ADRESS2 FMC_BANK1_2
AnnaBridge 156:ff21514d8981 84 #define NOR_MEMORY_ADRESS3 FMC_BANK1_3
AnnaBridge 156:ff21514d8981 85 #define NOR_MEMORY_ADRESS4 FMC_BANK1_4
AnnaBridge 156:ff21514d8981 86
AnnaBridge 156:ff21514d8981 87 /**
AnnaBridge 156:ff21514d8981 88 * @}
AnnaBridge 156:ff21514d8981 89 */
AnnaBridge 156:ff21514d8981 90
AnnaBridge 156:ff21514d8981 91 /** @addtogroup NOR_Private_Macros
AnnaBridge 156:ff21514d8981 92 * @{
AnnaBridge 156:ff21514d8981 93 */
AnnaBridge 156:ff21514d8981 94
AnnaBridge 156:ff21514d8981 95 /**
AnnaBridge 156:ff21514d8981 96 * @brief NOR memory address shifting.
AnnaBridge 156:ff21514d8981 97 * @param __NOR_ADDRESS: NOR base address
AnnaBridge 156:ff21514d8981 98 * @param __NOR_MEMORY_WIDTH_: NOR memory width
AnnaBridge 156:ff21514d8981 99 * @param __ADDRESS__: NOR memory address
AnnaBridge 156:ff21514d8981 100 * @retval NOR shifted address value
AnnaBridge 156:ff21514d8981 101 */
AnnaBridge 156:ff21514d8981 102 #define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \
AnnaBridge 156:ff21514d8981 103 ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \
AnnaBridge 156:ff21514d8981 104 ((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))): \
AnnaBridge 156:ff21514d8981 105 ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
AnnaBridge 156:ff21514d8981 106
AnnaBridge 156:ff21514d8981 107 /**
AnnaBridge 156:ff21514d8981 108 * @brief NOR memory write data to specified address.
AnnaBridge 156:ff21514d8981 109 * @param __ADDRESS__: NOR memory address
AnnaBridge 156:ff21514d8981 110 * @param __DATA__: Data to write
AnnaBridge 156:ff21514d8981 111 * @retval None
AnnaBridge 156:ff21514d8981 112 */
AnnaBridge 156:ff21514d8981 113 #define NOR_WRITE(__ADDRESS__, __DATA__) (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__))
AnnaBridge 156:ff21514d8981 114
AnnaBridge 156:ff21514d8981 115 /**
AnnaBridge 156:ff21514d8981 116 * @}
AnnaBridge 156:ff21514d8981 117 */
AnnaBridge 156:ff21514d8981 118
AnnaBridge 156:ff21514d8981 119 /* Exported typedef ----------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 120 /** @defgroup NOR_Exported_Types NOR Exported Types
AnnaBridge 156:ff21514d8981 121 * @{
AnnaBridge 156:ff21514d8981 122 */
AnnaBridge 156:ff21514d8981 123
AnnaBridge 156:ff21514d8981 124 /**
AnnaBridge 156:ff21514d8981 125 * @brief HAL SRAM State structures definition
AnnaBridge 156:ff21514d8981 126 */
AnnaBridge 156:ff21514d8981 127 typedef enum
AnnaBridge 156:ff21514d8981 128 {
AnnaBridge 156:ff21514d8981 129 HAL_NOR_STATE_RESET = 0x00, /*!< NOR not yet initialized or disabled */
AnnaBridge 156:ff21514d8981 130 HAL_NOR_STATE_READY = 0x01, /*!< NOR initialized and ready for use */
AnnaBridge 156:ff21514d8981 131 HAL_NOR_STATE_BUSY = 0x02, /*!< NOR internal processing is ongoing */
AnnaBridge 156:ff21514d8981 132 HAL_NOR_STATE_ERROR = 0x03, /*!< NOR error state */
AnnaBridge 156:ff21514d8981 133 HAL_NOR_STATE_PROTECTED = 0x04 /*!< NOR NORSRAM device write protected */
AnnaBridge 156:ff21514d8981 134 }HAL_NOR_StateTypeDef;
AnnaBridge 156:ff21514d8981 135
AnnaBridge 156:ff21514d8981 136 /**
AnnaBridge 156:ff21514d8981 137 * @brief FMC NOR Status typedef
AnnaBridge 156:ff21514d8981 138 */
AnnaBridge 156:ff21514d8981 139 typedef enum
AnnaBridge 156:ff21514d8981 140 {
AnnaBridge 156:ff21514d8981 141 HAL_NOR_STATUS_SUCCESS = 0,
AnnaBridge 156:ff21514d8981 142 HAL_NOR_STATUS_ONGOING,
AnnaBridge 156:ff21514d8981 143 HAL_NOR_STATUS_ERROR,
AnnaBridge 156:ff21514d8981 144 HAL_NOR_STATUS_TIMEOUT
AnnaBridge 156:ff21514d8981 145 }HAL_NOR_StatusTypeDef;
AnnaBridge 156:ff21514d8981 146
AnnaBridge 156:ff21514d8981 147 /**
AnnaBridge 156:ff21514d8981 148 * @brief FMC NOR ID typedef
AnnaBridge 156:ff21514d8981 149 */
AnnaBridge 156:ff21514d8981 150 typedef struct
AnnaBridge 156:ff21514d8981 151 {
AnnaBridge 156:ff21514d8981 152 uint16_t Manufacturer_Code; /*!< Defines the device's manufacturer code used to identify the memory */
AnnaBridge 156:ff21514d8981 153
AnnaBridge 156:ff21514d8981 154 uint16_t Device_Code1;
AnnaBridge 156:ff21514d8981 155
AnnaBridge 156:ff21514d8981 156 uint16_t Device_Code2;
AnnaBridge 156:ff21514d8981 157
AnnaBridge 156:ff21514d8981 158 uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory.
AnnaBridge 156:ff21514d8981 159 These codes can be accessed by performing read operations with specific
AnnaBridge 156:ff21514d8981 160 control signals and addresses set.They can also be accessed by issuing
AnnaBridge 156:ff21514d8981 161 an Auto Select command. */
AnnaBridge 156:ff21514d8981 162 }NOR_IDTypeDef;
AnnaBridge 156:ff21514d8981 163
AnnaBridge 156:ff21514d8981 164 /**
AnnaBridge 156:ff21514d8981 165 * @brief FMC NOR CFI typedef
AnnaBridge 156:ff21514d8981 166 */
AnnaBridge 156:ff21514d8981 167 typedef struct
AnnaBridge 156:ff21514d8981 168 {
AnnaBridge 156:ff21514d8981 169 uint16_t CFI_1;
AnnaBridge 156:ff21514d8981 170
AnnaBridge 156:ff21514d8981 171 uint16_t CFI_2;
AnnaBridge 156:ff21514d8981 172
AnnaBridge 156:ff21514d8981 173 uint16_t CFI_3;
AnnaBridge 156:ff21514d8981 174
AnnaBridge 156:ff21514d8981 175 uint16_t CFI_4; /*!< Defines the information stored in the memory's Common flash interface
AnnaBridge 156:ff21514d8981 176 which contains a description of various electrical and timing parameters,
AnnaBridge 156:ff21514d8981 177 density information and functions supported by the memory. */
AnnaBridge 156:ff21514d8981 178 }NOR_CFITypeDef;
AnnaBridge 156:ff21514d8981 179
AnnaBridge 156:ff21514d8981 180 /**
AnnaBridge 156:ff21514d8981 181 * @brief NOR handle Structure definition
AnnaBridge 156:ff21514d8981 182 */
AnnaBridge 156:ff21514d8981 183 typedef struct
AnnaBridge 156:ff21514d8981 184 {
AnnaBridge 156:ff21514d8981 185 FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
AnnaBridge 156:ff21514d8981 186
AnnaBridge 156:ff21514d8981 187 FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
AnnaBridge 156:ff21514d8981 188
AnnaBridge 156:ff21514d8981 189 FMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */
AnnaBridge 156:ff21514d8981 190
AnnaBridge 156:ff21514d8981 191 HAL_LockTypeDef Lock; /*!< NOR locking object */
AnnaBridge 156:ff21514d8981 192
AnnaBridge 156:ff21514d8981 193 __IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */
AnnaBridge 156:ff21514d8981 194
AnnaBridge 156:ff21514d8981 195 }NOR_HandleTypeDef;
AnnaBridge 156:ff21514d8981 196
AnnaBridge 156:ff21514d8981 197 /**
AnnaBridge 156:ff21514d8981 198 * @}
AnnaBridge 156:ff21514d8981 199 */
AnnaBridge 156:ff21514d8981 200
AnnaBridge 156:ff21514d8981 201 /* Exported constants --------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 202 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 203 /** @defgroup NOR_Exported_Macros NOR Exported Macros
AnnaBridge 156:ff21514d8981 204 * @{
AnnaBridge 156:ff21514d8981 205 */
AnnaBridge 156:ff21514d8981 206
AnnaBridge 156:ff21514d8981 207 /** @brief Reset NOR handle state.
AnnaBridge 156:ff21514d8981 208 * @param __HANDLE__: NOR handle
AnnaBridge 156:ff21514d8981 209 * @retval None
AnnaBridge 156:ff21514d8981 210 */
AnnaBridge 156:ff21514d8981 211 #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
AnnaBridge 156:ff21514d8981 212
AnnaBridge 156:ff21514d8981 213 /**
AnnaBridge 156:ff21514d8981 214 * @}
AnnaBridge 156:ff21514d8981 215 */
AnnaBridge 156:ff21514d8981 216
AnnaBridge 156:ff21514d8981 217 /* Exported functions --------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 218 /** @addtogroup NOR_Exported_Functions NOR Exported Functions
AnnaBridge 156:ff21514d8981 219 * @{
AnnaBridge 156:ff21514d8981 220 */
AnnaBridge 156:ff21514d8981 221
AnnaBridge 156:ff21514d8981 222 /** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
AnnaBridge 156:ff21514d8981 223 * @{
AnnaBridge 156:ff21514d8981 224 */
AnnaBridge 156:ff21514d8981 225
AnnaBridge 156:ff21514d8981 226 /* Initialization/de-initialization functions ********************************/
AnnaBridge 156:ff21514d8981 227 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
AnnaBridge 156:ff21514d8981 228 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
AnnaBridge 156:ff21514d8981 229 void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
AnnaBridge 156:ff21514d8981 230 void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
AnnaBridge 156:ff21514d8981 231 void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
AnnaBridge 156:ff21514d8981 232
AnnaBridge 156:ff21514d8981 233 /**
AnnaBridge 156:ff21514d8981 234 * @}
AnnaBridge 156:ff21514d8981 235 */
AnnaBridge 156:ff21514d8981 236
AnnaBridge 156:ff21514d8981 237 /** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions
AnnaBridge 156:ff21514d8981 238 * @{
AnnaBridge 156:ff21514d8981 239 */
AnnaBridge 156:ff21514d8981 240
AnnaBridge 156:ff21514d8981 241 /* I/O operation functions ***************************************************/
AnnaBridge 156:ff21514d8981 242 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
AnnaBridge 156:ff21514d8981 243 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
AnnaBridge 156:ff21514d8981 244 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
AnnaBridge 156:ff21514d8981 245 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
AnnaBridge 156:ff21514d8981 246
AnnaBridge 156:ff21514d8981 247 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
AnnaBridge 156:ff21514d8981 248 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
AnnaBridge 156:ff21514d8981 249
AnnaBridge 156:ff21514d8981 250 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
AnnaBridge 156:ff21514d8981 251 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
AnnaBridge 156:ff21514d8981 252 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
AnnaBridge 156:ff21514d8981 253
AnnaBridge 156:ff21514d8981 254 /**
AnnaBridge 156:ff21514d8981 255 * @}
AnnaBridge 156:ff21514d8981 256 */
AnnaBridge 156:ff21514d8981 257
AnnaBridge 156:ff21514d8981 258 /** @addtogroup NOR_Exported_Functions_Group3 Peripheral Control functions
AnnaBridge 156:ff21514d8981 259 * @{
AnnaBridge 156:ff21514d8981 260 */
AnnaBridge 156:ff21514d8981 261
AnnaBridge 156:ff21514d8981 262 /* NOR Control functions *****************************************************/
AnnaBridge 156:ff21514d8981 263 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
AnnaBridge 156:ff21514d8981 264 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
AnnaBridge 156:ff21514d8981 265
AnnaBridge 156:ff21514d8981 266 /**
AnnaBridge 156:ff21514d8981 267 * @}
AnnaBridge 156:ff21514d8981 268 */
AnnaBridge 156:ff21514d8981 269
AnnaBridge 156:ff21514d8981 270 /** @addtogroup NOR_Exported_Functions_Group4 Peripheral State functions
AnnaBridge 156:ff21514d8981 271 * @{
AnnaBridge 156:ff21514d8981 272 */
AnnaBridge 156:ff21514d8981 273
AnnaBridge 156:ff21514d8981 274 /* NOR State functions ********************************************************/
AnnaBridge 156:ff21514d8981 275 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
AnnaBridge 156:ff21514d8981 276 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
AnnaBridge 156:ff21514d8981 277
AnnaBridge 156:ff21514d8981 278 /**
AnnaBridge 156:ff21514d8981 279 * @}
AnnaBridge 156:ff21514d8981 280 */
AnnaBridge 156:ff21514d8981 281
AnnaBridge 156:ff21514d8981 282 /**
AnnaBridge 156:ff21514d8981 283 * @}
AnnaBridge 156:ff21514d8981 284 */
AnnaBridge 156:ff21514d8981 285
AnnaBridge 156:ff21514d8981 286 /**
AnnaBridge 156:ff21514d8981 287 * @}
AnnaBridge 156:ff21514d8981 288 */
AnnaBridge 156:ff21514d8981 289
AnnaBridge 156:ff21514d8981 290 /**
AnnaBridge 156:ff21514d8981 291 * @}
AnnaBridge 156:ff21514d8981 292 */
AnnaBridge 156:ff21514d8981 293
AnnaBridge 156:ff21514d8981 294 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
AnnaBridge 156:ff21514d8981 295 /* STM32L496xx || STM32L4A6xx || */
AnnaBridge 156:ff21514d8981 296
AnnaBridge 156:ff21514d8981 297 #ifdef __cplusplus
AnnaBridge 156:ff21514d8981 298 }
AnnaBridge 156:ff21514d8981 299 #endif
AnnaBridge 156:ff21514d8981 300
AnnaBridge 156:ff21514d8981 301 #endif /* __STM32L4xx_HAL_NOR_H */
AnnaBridge 156:ff21514d8981 302
AnnaBridge 156:ff21514d8981 303 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/