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mbed 2

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TARGET_EFM32LG_STK3600/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_rtc.h@156:ff21514d8981, 2017-11-08 (annotated)

Committer:
AnnaBridge
Date:
Wed Nov 08 17:18:06 2017 +0000
Revision:
156:ff21514d8981
Reverting back to release 154 of the mbed library

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 156:ff21514d8981 1 /**************************************************************************//**
AnnaBridge 156:ff21514d8981 2 * @file efm32lg_rtc.h
AnnaBridge 156:ff21514d8981 3 * @brief EFM32LG_RTC register and bit field definitions
AnnaBridge 156:ff21514d8981 4 * @version 5.1.2
AnnaBridge 156:ff21514d8981 5 ******************************************************************************
AnnaBridge 156:ff21514d8981 6 * @section License
AnnaBridge 156:ff21514d8981 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
AnnaBridge 156:ff21514d8981 8 ******************************************************************************
AnnaBridge 156:ff21514d8981 9 *
AnnaBridge 156:ff21514d8981 10 * Permission is granted to anyone to use this software for any purpose,
AnnaBridge 156:ff21514d8981 11 * including commercial applications, and to alter it and redistribute it
AnnaBridge 156:ff21514d8981 12 * freely, subject to the following restrictions:
AnnaBridge 156:ff21514d8981 13 *
AnnaBridge 156:ff21514d8981 14 * 1. The origin of this software must not be misrepresented; you must not
AnnaBridge 156:ff21514d8981 15 * claim that you wrote the original software.@n
AnnaBridge 156:ff21514d8981 16 * 2. Altered source versions must be plainly marked as such, and must not be
AnnaBridge 156:ff21514d8981 17 * misrepresented as being the original software.@n
AnnaBridge 156:ff21514d8981 18 * 3. This notice may not be removed or altered from any source distribution.
AnnaBridge 156:ff21514d8981 19 *
AnnaBridge 156:ff21514d8981 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
AnnaBridge 156:ff21514d8981 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
AnnaBridge 156:ff21514d8981 22 * providing the Software "AS IS", with no express or implied warranties of any
AnnaBridge 156:ff21514d8981 23 * kind, including, but not limited to, any implied warranties of
AnnaBridge 156:ff21514d8981 24 * merchantability or fitness for any particular purpose or warranties against
AnnaBridge 156:ff21514d8981 25 * infringement of any proprietary rights of a third party.
AnnaBridge 156:ff21514d8981 26 *
AnnaBridge 156:ff21514d8981 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
AnnaBridge 156:ff21514d8981 28 * incidental, or special damages, or any other relief, or for any claim by
AnnaBridge 156:ff21514d8981 29 * any third party, arising from your use of this Software.
AnnaBridge 156:ff21514d8981 30 *
AnnaBridge 156:ff21514d8981 31 *****************************************************************************/
AnnaBridge 156:ff21514d8981 32 /**************************************************************************//**
AnnaBridge 156:ff21514d8981 33 * @addtogroup Parts
AnnaBridge 156:ff21514d8981 34 * @{
AnnaBridge 156:ff21514d8981 35 ******************************************************************************/
AnnaBridge 156:ff21514d8981 36 /**************************************************************************//**
AnnaBridge 156:ff21514d8981 37 * @defgroup EFM32LG_RTC
AnnaBridge 156:ff21514d8981 38 * @{
AnnaBridge 156:ff21514d8981 39 * @brief EFM32LG_RTC Register Declaration
AnnaBridge 156:ff21514d8981 40 *****************************************************************************/
AnnaBridge 156:ff21514d8981 41 typedef struct
AnnaBridge 156:ff21514d8981 42 {
AnnaBridge 156:ff21514d8981 43 __IOM uint32_t CTRL; /**< Control Register */
AnnaBridge 156:ff21514d8981 44 __IOM uint32_t CNT; /**< Counter Value Register */
AnnaBridge 156:ff21514d8981 45 __IOM uint32_t COMP0; /**< Compare Value Register 0 */
AnnaBridge 156:ff21514d8981 46 __IOM uint32_t COMP1; /**< Compare Value Register 1 */
AnnaBridge 156:ff21514d8981 47 __IM uint32_t IF; /**< Interrupt Flag Register */
AnnaBridge 156:ff21514d8981 48 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
AnnaBridge 156:ff21514d8981 49 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
AnnaBridge 156:ff21514d8981 50 __IOM uint32_t IEN; /**< Interrupt Enable Register */
AnnaBridge 156:ff21514d8981 51
AnnaBridge 156:ff21514d8981 52 __IOM uint32_t FREEZE; /**< Freeze Register */
AnnaBridge 156:ff21514d8981 53 __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
AnnaBridge 156:ff21514d8981 54 } RTC_TypeDef; /** @} */
AnnaBridge 156:ff21514d8981 55
AnnaBridge 156:ff21514d8981 56 /**************************************************************************//**
AnnaBridge 156:ff21514d8981 57 * @defgroup EFM32LG_RTC_BitFields
AnnaBridge 156:ff21514d8981 58 * @{
AnnaBridge 156:ff21514d8981 59 *****************************************************************************/
AnnaBridge 156:ff21514d8981 60
AnnaBridge 156:ff21514d8981 61 /* Bit fields for RTC CTRL */
AnnaBridge 156:ff21514d8981 62 #define _RTC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTC_CTRL */
AnnaBridge 156:ff21514d8981 63 #define _RTC_CTRL_MASK 0x00000007UL /**< Mask for RTC_CTRL */
AnnaBridge 156:ff21514d8981 64 #define RTC_CTRL_EN (0x1UL << 0) /**< RTC Enable */
AnnaBridge 156:ff21514d8981 65 #define _RTC_CTRL_EN_SHIFT 0 /**< Shift value for RTC_EN */
AnnaBridge 156:ff21514d8981 66 #define _RTC_CTRL_EN_MASK 0x1UL /**< Bit mask for RTC_EN */
AnnaBridge 156:ff21514d8981 67 #define _RTC_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CTRL */
AnnaBridge 156:ff21514d8981 68 #define RTC_CTRL_EN_DEFAULT (_RTC_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_CTRL */
AnnaBridge 156:ff21514d8981 69 #define RTC_CTRL_DEBUGRUN (0x1UL << 1) /**< Debug Mode Run Enable */
AnnaBridge 156:ff21514d8981 70 #define _RTC_CTRL_DEBUGRUN_SHIFT 1 /**< Shift value for RTC_DEBUGRUN */
AnnaBridge 156:ff21514d8981 71 #define _RTC_CTRL_DEBUGRUN_MASK 0x2UL /**< Bit mask for RTC_DEBUGRUN */
AnnaBridge 156:ff21514d8981 72 #define _RTC_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CTRL */
AnnaBridge 156:ff21514d8981 73 #define RTC_CTRL_DEBUGRUN_DEFAULT (_RTC_CTRL_DEBUGRUN_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_CTRL */
AnnaBridge 156:ff21514d8981 74 #define RTC_CTRL_COMP0TOP (0x1UL << 2) /**< Compare Channel 0 is Top Value */
AnnaBridge 156:ff21514d8981 75 #define _RTC_CTRL_COMP0TOP_SHIFT 2 /**< Shift value for RTC_COMP0TOP */
AnnaBridge 156:ff21514d8981 76 #define _RTC_CTRL_COMP0TOP_MASK 0x4UL /**< Bit mask for RTC_COMP0TOP */
AnnaBridge 156:ff21514d8981 77 #define _RTC_CTRL_COMP0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CTRL */
AnnaBridge 156:ff21514d8981 78 #define _RTC_CTRL_COMP0TOP_DISABLE 0x00000000UL /**< Mode DISABLE for RTC_CTRL */
AnnaBridge 156:ff21514d8981 79 #define _RTC_CTRL_COMP0TOP_ENABLE 0x00000001UL /**< Mode ENABLE for RTC_CTRL */
AnnaBridge 156:ff21514d8981 80 #define RTC_CTRL_COMP0TOP_DEFAULT (_RTC_CTRL_COMP0TOP_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_CTRL */
AnnaBridge 156:ff21514d8981 81 #define RTC_CTRL_COMP0TOP_DISABLE (_RTC_CTRL_COMP0TOP_DISABLE << 2) /**< Shifted mode DISABLE for RTC_CTRL */
AnnaBridge 156:ff21514d8981 82 #define RTC_CTRL_COMP0TOP_ENABLE (_RTC_CTRL_COMP0TOP_ENABLE << 2) /**< Shifted mode ENABLE for RTC_CTRL */
AnnaBridge 156:ff21514d8981 83
AnnaBridge 156:ff21514d8981 84 /* Bit fields for RTC CNT */
AnnaBridge 156:ff21514d8981 85 #define _RTC_CNT_RESETVALUE 0x00000000UL /**< Default value for RTC_CNT */
AnnaBridge 156:ff21514d8981 86 #define _RTC_CNT_MASK 0x00FFFFFFUL /**< Mask for RTC_CNT */
AnnaBridge 156:ff21514d8981 87 #define _RTC_CNT_CNT_SHIFT 0 /**< Shift value for RTC_CNT */
AnnaBridge 156:ff21514d8981 88 #define _RTC_CNT_CNT_MASK 0xFFFFFFUL /**< Bit mask for RTC_CNT */
AnnaBridge 156:ff21514d8981 89 #define _RTC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CNT */
AnnaBridge 156:ff21514d8981 90 #define RTC_CNT_CNT_DEFAULT (_RTC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_CNT */
AnnaBridge 156:ff21514d8981 91
AnnaBridge 156:ff21514d8981 92 /* Bit fields for RTC COMP0 */
AnnaBridge 156:ff21514d8981 93 #define _RTC_COMP0_RESETVALUE 0x00000000UL /**< Default value for RTC_COMP0 */
AnnaBridge 156:ff21514d8981 94 #define _RTC_COMP0_MASK 0x00FFFFFFUL /**< Mask for RTC_COMP0 */
AnnaBridge 156:ff21514d8981 95 #define _RTC_COMP0_COMP0_SHIFT 0 /**< Shift value for RTC_COMP0 */
AnnaBridge 156:ff21514d8981 96 #define _RTC_COMP0_COMP0_MASK 0xFFFFFFUL /**< Bit mask for RTC_COMP0 */
AnnaBridge 156:ff21514d8981 97 #define _RTC_COMP0_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_COMP0 */
AnnaBridge 156:ff21514d8981 98 #define RTC_COMP0_COMP0_DEFAULT (_RTC_COMP0_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_COMP0 */
AnnaBridge 156:ff21514d8981 99
AnnaBridge 156:ff21514d8981 100 /* Bit fields for RTC COMP1 */
AnnaBridge 156:ff21514d8981 101 #define _RTC_COMP1_RESETVALUE 0x00000000UL /**< Default value for RTC_COMP1 */
AnnaBridge 156:ff21514d8981 102 #define _RTC_COMP1_MASK 0x00FFFFFFUL /**< Mask for RTC_COMP1 */
AnnaBridge 156:ff21514d8981 103 #define _RTC_COMP1_COMP1_SHIFT 0 /**< Shift value for RTC_COMP1 */
AnnaBridge 156:ff21514d8981 104 #define _RTC_COMP1_COMP1_MASK 0xFFFFFFUL /**< Bit mask for RTC_COMP1 */
AnnaBridge 156:ff21514d8981 105 #define _RTC_COMP1_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_COMP1 */
AnnaBridge 156:ff21514d8981 106 #define RTC_COMP1_COMP1_DEFAULT (_RTC_COMP1_COMP1_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_COMP1 */
AnnaBridge 156:ff21514d8981 107
AnnaBridge 156:ff21514d8981 108 /* Bit fields for RTC IF */
AnnaBridge 156:ff21514d8981 109 #define _RTC_IF_RESETVALUE 0x00000000UL /**< Default value for RTC_IF */
AnnaBridge 156:ff21514d8981 110 #define _RTC_IF_MASK 0x00000007UL /**< Mask for RTC_IF */
AnnaBridge 156:ff21514d8981 111 #define RTC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */
AnnaBridge 156:ff21514d8981 112 #define _RTC_IF_OF_SHIFT 0 /**< Shift value for RTC_OF */
AnnaBridge 156:ff21514d8981 113 #define _RTC_IF_OF_MASK 0x1UL /**< Bit mask for RTC_OF */
AnnaBridge 156:ff21514d8981 114 #define _RTC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IF */
AnnaBridge 156:ff21514d8981 115 #define RTC_IF_OF_DEFAULT (_RTC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_IF */
AnnaBridge 156:ff21514d8981 116 #define RTC_IF_COMP0 (0x1UL << 1) /**< Compare Match 0 Interrupt Flag */
AnnaBridge 156:ff21514d8981 117 #define _RTC_IF_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */
AnnaBridge 156:ff21514d8981 118 #define _RTC_IF_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */
AnnaBridge 156:ff21514d8981 119 #define _RTC_IF_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IF */
AnnaBridge 156:ff21514d8981 120 #define RTC_IF_COMP0_DEFAULT (_RTC_IF_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IF */
AnnaBridge 156:ff21514d8981 121 #define RTC_IF_COMP1 (0x1UL << 2) /**< Compare Match 1 Interrupt Flag */
AnnaBridge 156:ff21514d8981 122 #define _RTC_IF_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */
AnnaBridge 156:ff21514d8981 123 #define _RTC_IF_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */
AnnaBridge 156:ff21514d8981 124 #define _RTC_IF_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IF */
AnnaBridge 156:ff21514d8981 125 #define RTC_IF_COMP1_DEFAULT (_RTC_IF_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_IF */
AnnaBridge 156:ff21514d8981 126
AnnaBridge 156:ff21514d8981 127 /* Bit fields for RTC IFS */
AnnaBridge 156:ff21514d8981 128 #define _RTC_IFS_RESETVALUE 0x00000000UL /**< Default value for RTC_IFS */
AnnaBridge 156:ff21514d8981 129 #define _RTC_IFS_MASK 0x00000007UL /**< Mask for RTC_IFS */
AnnaBridge 156:ff21514d8981 130 #define RTC_IFS_OF (0x1UL << 0) /**< Set Overflow Interrupt Flag */
AnnaBridge 156:ff21514d8981 131 #define _RTC_IFS_OF_SHIFT 0 /**< Shift value for RTC_OF */
AnnaBridge 156:ff21514d8981 132 #define _RTC_IFS_OF_MASK 0x1UL /**< Bit mask for RTC_OF */
AnnaBridge 156:ff21514d8981 133 #define _RTC_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFS */
AnnaBridge 156:ff21514d8981 134 #define RTC_IFS_OF_DEFAULT (_RTC_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_IFS */
AnnaBridge 156:ff21514d8981 135 #define RTC_IFS_COMP0 (0x1UL << 1) /**< Set Compare match 0 Interrupt Flag */
AnnaBridge 156:ff21514d8981 136 #define _RTC_IFS_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */
AnnaBridge 156:ff21514d8981 137 #define _RTC_IFS_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */
AnnaBridge 156:ff21514d8981 138 #define _RTC_IFS_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFS */
AnnaBridge 156:ff21514d8981 139 #define RTC_IFS_COMP0_DEFAULT (_RTC_IFS_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IFS */
AnnaBridge 156:ff21514d8981 140 #define RTC_IFS_COMP1 (0x1UL << 2) /**< Set Compare match 1 Interrupt Flag */
AnnaBridge 156:ff21514d8981 141 #define _RTC_IFS_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */
AnnaBridge 156:ff21514d8981 142 #define _RTC_IFS_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */
AnnaBridge 156:ff21514d8981 143 #define _RTC_IFS_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFS */
AnnaBridge 156:ff21514d8981 144 #define RTC_IFS_COMP1_DEFAULT (_RTC_IFS_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_IFS */
AnnaBridge 156:ff21514d8981 145
AnnaBridge 156:ff21514d8981 146 /* Bit fields for RTC IFC */
AnnaBridge 156:ff21514d8981 147 #define _RTC_IFC_RESETVALUE 0x00000000UL /**< Default value for RTC_IFC */
AnnaBridge 156:ff21514d8981 148 #define _RTC_IFC_MASK 0x00000007UL /**< Mask for RTC_IFC */
AnnaBridge 156:ff21514d8981 149 #define RTC_IFC_OF (0x1UL << 0) /**< Clear Overflow Interrupt Flag */
AnnaBridge 156:ff21514d8981 150 #define _RTC_IFC_OF_SHIFT 0 /**< Shift value for RTC_OF */
AnnaBridge 156:ff21514d8981 151 #define _RTC_IFC_OF_MASK 0x1UL /**< Bit mask for RTC_OF */
AnnaBridge 156:ff21514d8981 152 #define _RTC_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFC */
AnnaBridge 156:ff21514d8981 153 #define RTC_IFC_OF_DEFAULT (_RTC_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_IFC */
AnnaBridge 156:ff21514d8981 154 #define RTC_IFC_COMP0 (0x1UL << 1) /**< Clear Compare match 0 Interrupt Flag */
AnnaBridge 156:ff21514d8981 155 #define _RTC_IFC_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */
AnnaBridge 156:ff21514d8981 156 #define _RTC_IFC_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */
AnnaBridge 156:ff21514d8981 157 #define _RTC_IFC_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFC */
AnnaBridge 156:ff21514d8981 158 #define RTC_IFC_COMP0_DEFAULT (_RTC_IFC_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IFC */
AnnaBridge 156:ff21514d8981 159 #define RTC_IFC_COMP1 (0x1UL << 2) /**< Clear Compare match 1 Interrupt Flag */
AnnaBridge 156:ff21514d8981 160 #define _RTC_IFC_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */
AnnaBridge 156:ff21514d8981 161 #define _RTC_IFC_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */
AnnaBridge 156:ff21514d8981 162 #define _RTC_IFC_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFC */
AnnaBridge 156:ff21514d8981 163 #define RTC_IFC_COMP1_DEFAULT (_RTC_IFC_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_IFC */
AnnaBridge 156:ff21514d8981 164
AnnaBridge 156:ff21514d8981 165 /* Bit fields for RTC IEN */
AnnaBridge 156:ff21514d8981 166 #define _RTC_IEN_RESETVALUE 0x00000000UL /**< Default value for RTC_IEN */
AnnaBridge 156:ff21514d8981 167 #define _RTC_IEN_MASK 0x00000007UL /**< Mask for RTC_IEN */
AnnaBridge 156:ff21514d8981 168 #define RTC_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Enable */
AnnaBridge 156:ff21514d8981 169 #define _RTC_IEN_OF_SHIFT 0 /**< Shift value for RTC_OF */
AnnaBridge 156:ff21514d8981 170 #define _RTC_IEN_OF_MASK 0x1UL /**< Bit mask for RTC_OF */
AnnaBridge 156:ff21514d8981 171 #define _RTC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IEN */
AnnaBridge 156:ff21514d8981 172 #define RTC_IEN_OF_DEFAULT (_RTC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_IEN */
AnnaBridge 156:ff21514d8981 173 #define RTC_IEN_COMP0 (0x1UL << 1) /**< Compare Match 0 Interrupt Enable */
AnnaBridge 156:ff21514d8981 174 #define _RTC_IEN_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */
AnnaBridge 156:ff21514d8981 175 #define _RTC_IEN_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */
AnnaBridge 156:ff21514d8981 176 #define _RTC_IEN_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IEN */
AnnaBridge 156:ff21514d8981 177 #define RTC_IEN_COMP0_DEFAULT (_RTC_IEN_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IEN */
AnnaBridge 156:ff21514d8981 178 #define RTC_IEN_COMP1 (0x1UL << 2) /**< Compare Match 1 Interrupt Enable */
AnnaBridge 156:ff21514d8981 179 #define _RTC_IEN_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */
AnnaBridge 156:ff21514d8981 180 #define _RTC_IEN_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */
AnnaBridge 156:ff21514d8981 181 #define _RTC_IEN_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IEN */
AnnaBridge 156:ff21514d8981 182 #define RTC_IEN_COMP1_DEFAULT (_RTC_IEN_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_IEN */
AnnaBridge 156:ff21514d8981 183
AnnaBridge 156:ff21514d8981 184 /* Bit fields for RTC FREEZE */
AnnaBridge 156:ff21514d8981 185 #define _RTC_FREEZE_RESETVALUE 0x00000000UL /**< Default value for RTC_FREEZE */
AnnaBridge 156:ff21514d8981 186 #define _RTC_FREEZE_MASK 0x00000001UL /**< Mask for RTC_FREEZE */
AnnaBridge 156:ff21514d8981 187 #define RTC_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */
AnnaBridge 156:ff21514d8981 188 #define _RTC_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for RTC_REGFREEZE */
AnnaBridge 156:ff21514d8981 189 #define _RTC_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for RTC_REGFREEZE */
AnnaBridge 156:ff21514d8981 190 #define _RTC_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_FREEZE */
AnnaBridge 156:ff21514d8981 191 #define _RTC_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for RTC_FREEZE */
AnnaBridge 156:ff21514d8981 192 #define _RTC_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for RTC_FREEZE */
AnnaBridge 156:ff21514d8981 193 #define RTC_FREEZE_REGFREEZE_DEFAULT (_RTC_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_FREEZE */
AnnaBridge 156:ff21514d8981 194 #define RTC_FREEZE_REGFREEZE_UPDATE (_RTC_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for RTC_FREEZE */
AnnaBridge 156:ff21514d8981 195 #define RTC_FREEZE_REGFREEZE_FREEZE (_RTC_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for RTC_FREEZE */
AnnaBridge 156:ff21514d8981 196
AnnaBridge 156:ff21514d8981 197 /* Bit fields for RTC SYNCBUSY */
AnnaBridge 156:ff21514d8981 198 #define _RTC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for RTC_SYNCBUSY */
AnnaBridge 156:ff21514d8981 199 #define _RTC_SYNCBUSY_MASK 0x00000007UL /**< Mask for RTC_SYNCBUSY */
AnnaBridge 156:ff21514d8981 200 #define RTC_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */
AnnaBridge 156:ff21514d8981 201 #define _RTC_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for RTC_CTRL */
AnnaBridge 156:ff21514d8981 202 #define _RTC_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for RTC_CTRL */
AnnaBridge 156:ff21514d8981 203 #define _RTC_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_SYNCBUSY */
AnnaBridge 156:ff21514d8981 204 #define RTC_SYNCBUSY_CTRL_DEFAULT (_RTC_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_SYNCBUSY */
AnnaBridge 156:ff21514d8981 205 #define RTC_SYNCBUSY_COMP0 (0x1UL << 1) /**< COMP0 Register Busy */
AnnaBridge 156:ff21514d8981 206 #define _RTC_SYNCBUSY_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */
AnnaBridge 156:ff21514d8981 207 #define _RTC_SYNCBUSY_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */
AnnaBridge 156:ff21514d8981 208 #define _RTC_SYNCBUSY_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_SYNCBUSY */
AnnaBridge 156:ff21514d8981 209 #define RTC_SYNCBUSY_COMP0_DEFAULT (_RTC_SYNCBUSY_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_SYNCBUSY */
AnnaBridge 156:ff21514d8981 210 #define RTC_SYNCBUSY_COMP1 (0x1UL << 2) /**< COMP1 Register Busy */
AnnaBridge 156:ff21514d8981 211 #define _RTC_SYNCBUSY_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */
AnnaBridge 156:ff21514d8981 212 #define _RTC_SYNCBUSY_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */
AnnaBridge 156:ff21514d8981 213 #define _RTC_SYNCBUSY_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_SYNCBUSY */
AnnaBridge 156:ff21514d8981 214 #define RTC_SYNCBUSY_COMP1_DEFAULT (_RTC_SYNCBUSY_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_SYNCBUSY */
AnnaBridge 156:ff21514d8981 215
AnnaBridge 156:ff21514d8981 216 /** @} End of group EFM32LG_RTC */
AnnaBridge 156:ff21514d8981 217 /** @} End of group Parts */
AnnaBridge 156:ff21514d8981 218