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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_EFM32LG_STK3600/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dmareq.h@156:ff21514d8981, 2017-11-08 (annotated)

Committer:
AnnaBridge
Date:
Wed Nov 08 17:18:06 2017 +0000
Revision:
156:ff21514d8981
Reverting back to release 154 of the mbed library

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 156:ff21514d8981 1 /**************************************************************************//**
AnnaBridge 156:ff21514d8981 2 * @file efm32lg_dmareq.h
AnnaBridge 156:ff21514d8981 3 * @brief EFM32LG_DMAREQ register and bit field definitions
AnnaBridge 156:ff21514d8981 4 * @version 5.1.2
AnnaBridge 156:ff21514d8981 5 ******************************************************************************
AnnaBridge 156:ff21514d8981 6 * @section License
AnnaBridge 156:ff21514d8981 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
AnnaBridge 156:ff21514d8981 8 ******************************************************************************
AnnaBridge 156:ff21514d8981 9 *
AnnaBridge 156:ff21514d8981 10 * Permission is granted to anyone to use this software for any purpose,
AnnaBridge 156:ff21514d8981 11 * including commercial applications, and to alter it and redistribute it
AnnaBridge 156:ff21514d8981 12 * freely, subject to the following restrictions:
AnnaBridge 156:ff21514d8981 13 *
AnnaBridge 156:ff21514d8981 14 * 1. The origin of this software must not be misrepresented; you must not
AnnaBridge 156:ff21514d8981 15 * claim that you wrote the original software.@n
AnnaBridge 156:ff21514d8981 16 * 2. Altered source versions must be plainly marked as such, and must not be
AnnaBridge 156:ff21514d8981 17 * misrepresented as being the original software.@n
AnnaBridge 156:ff21514d8981 18 * 3. This notice may not be removed or altered from any source distribution.
AnnaBridge 156:ff21514d8981 19 *
AnnaBridge 156:ff21514d8981 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
AnnaBridge 156:ff21514d8981 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
AnnaBridge 156:ff21514d8981 22 * providing the Software "AS IS", with no express or implied warranties of any
AnnaBridge 156:ff21514d8981 23 * kind, including, but not limited to, any implied warranties of
AnnaBridge 156:ff21514d8981 24 * merchantability or fitness for any particular purpose or warranties against
AnnaBridge 156:ff21514d8981 25 * infringement of any proprietary rights of a third party.
AnnaBridge 156:ff21514d8981 26 *
AnnaBridge 156:ff21514d8981 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
AnnaBridge 156:ff21514d8981 28 * incidental, or special damages, or any other relief, or for any claim by
AnnaBridge 156:ff21514d8981 29 * any third party, arising from your use of this Software.
AnnaBridge 156:ff21514d8981 30 *
AnnaBridge 156:ff21514d8981 31 *****************************************************************************/
AnnaBridge 156:ff21514d8981 32 /**************************************************************************//**
AnnaBridge 156:ff21514d8981 33 * @addtogroup Parts
AnnaBridge 156:ff21514d8981 34 * @{
AnnaBridge 156:ff21514d8981 35 ******************************************************************************/
AnnaBridge 156:ff21514d8981 36
AnnaBridge 156:ff21514d8981 37 /**************************************************************************//**
AnnaBridge 156:ff21514d8981 38 * @defgroup EFM32LG_DMAREQ_BitFields
AnnaBridge 156:ff21514d8981 39 * @{
AnnaBridge 156:ff21514d8981 40 *****************************************************************************/
AnnaBridge 156:ff21514d8981 41 #define DMAREQ_ADC0_SINGLE ((8 << 16) + 0) /**< DMA channel select for ADC0_SINGLE */
AnnaBridge 156:ff21514d8981 42 #define DMAREQ_ADC0_SCAN ((8 << 16) + 1) /**< DMA channel select for ADC0_SCAN */
AnnaBridge 156:ff21514d8981 43 #define DMAREQ_DAC0_CH0 ((10 << 16) + 0) /**< DMA channel select for DAC0_CH0 */
AnnaBridge 156:ff21514d8981 44 #define DMAREQ_DAC0_CH1 ((10 << 16) + 1) /**< DMA channel select for DAC0_CH1 */
AnnaBridge 156:ff21514d8981 45 #define DMAREQ_USART0_RXDATAV ((12 << 16) + 0) /**< DMA channel select for USART0_RXDATAV */
AnnaBridge 156:ff21514d8981 46 #define DMAREQ_USART0_TXBL ((12 << 16) + 1) /**< DMA channel select for USART0_TXBL */
AnnaBridge 156:ff21514d8981 47 #define DMAREQ_USART0_TXEMPTY ((12 << 16) + 2) /**< DMA channel select for USART0_TXEMPTY */
AnnaBridge 156:ff21514d8981 48 #define DMAREQ_USART1_RXDATAV ((13 << 16) + 0) /**< DMA channel select for USART1_RXDATAV */
AnnaBridge 156:ff21514d8981 49 #define DMAREQ_USART1_TXBL ((13 << 16) + 1) /**< DMA channel select for USART1_TXBL */
AnnaBridge 156:ff21514d8981 50 #define DMAREQ_USART1_TXEMPTY ((13 << 16) + 2) /**< DMA channel select for USART1_TXEMPTY */
AnnaBridge 156:ff21514d8981 51 #define DMAREQ_USART1_RXDATAVRIGHT ((13 << 16) + 3) /**< DMA channel select for USART1_RXDATAVRIGHT */
AnnaBridge 156:ff21514d8981 52 #define DMAREQ_USART1_TXBLRIGHT ((13 << 16) + 4) /**< DMA channel select for USART1_TXBLRIGHT */
AnnaBridge 156:ff21514d8981 53 #define DMAREQ_USART2_RXDATAV ((14 << 16) + 0) /**< DMA channel select for USART2_RXDATAV */
AnnaBridge 156:ff21514d8981 54 #define DMAREQ_USART2_TXBL ((14 << 16) + 1) /**< DMA channel select for USART2_TXBL */
AnnaBridge 156:ff21514d8981 55 #define DMAREQ_USART2_TXEMPTY ((14 << 16) + 2) /**< DMA channel select for USART2_TXEMPTY */
AnnaBridge 156:ff21514d8981 56 #define DMAREQ_USART2_RXDATAVRIGHT ((14 << 16) + 3) /**< DMA channel select for USART2_RXDATAVRIGHT */
AnnaBridge 156:ff21514d8981 57 #define DMAREQ_USART2_TXBLRIGHT ((14 << 16) + 4) /**< DMA channel select for USART2_TXBLRIGHT */
AnnaBridge 156:ff21514d8981 58 #define DMAREQ_LEUART0_RXDATAV ((16 << 16) + 0) /**< DMA channel select for LEUART0_RXDATAV */
AnnaBridge 156:ff21514d8981 59 #define DMAREQ_LEUART0_TXBL ((16 << 16) + 1) /**< DMA channel select for LEUART0_TXBL */
AnnaBridge 156:ff21514d8981 60 #define DMAREQ_LEUART0_TXEMPTY ((16 << 16) + 2) /**< DMA channel select for LEUART0_TXEMPTY */
AnnaBridge 156:ff21514d8981 61 #define DMAREQ_LEUART1_RXDATAV ((17 << 16) + 0) /**< DMA channel select for LEUART1_RXDATAV */
AnnaBridge 156:ff21514d8981 62 #define DMAREQ_LEUART1_TXBL ((17 << 16) + 1) /**< DMA channel select for LEUART1_TXBL */
AnnaBridge 156:ff21514d8981 63 #define DMAREQ_LEUART1_TXEMPTY ((17 << 16) + 2) /**< DMA channel select for LEUART1_TXEMPTY */
AnnaBridge 156:ff21514d8981 64 #define DMAREQ_I2C0_RXDATAV ((20 << 16) + 0) /**< DMA channel select for I2C0_RXDATAV */
AnnaBridge 156:ff21514d8981 65 #define DMAREQ_I2C0_TXBL ((20 << 16) + 1) /**< DMA channel select for I2C0_TXBL */
AnnaBridge 156:ff21514d8981 66 #define DMAREQ_I2C1_RXDATAV ((21 << 16) + 0) /**< DMA channel select for I2C1_RXDATAV */
AnnaBridge 156:ff21514d8981 67 #define DMAREQ_I2C1_TXBL ((21 << 16) + 1) /**< DMA channel select for I2C1_TXBL */
AnnaBridge 156:ff21514d8981 68 #define DMAREQ_TIMER0_UFOF ((24 << 16) + 0) /**< DMA channel select for TIMER0_UFOF */
AnnaBridge 156:ff21514d8981 69 #define DMAREQ_TIMER0_CC0 ((24 << 16) + 1) /**< DMA channel select for TIMER0_CC0 */
AnnaBridge 156:ff21514d8981 70 #define DMAREQ_TIMER0_CC1 ((24 << 16) + 2) /**< DMA channel select for TIMER0_CC1 */
AnnaBridge 156:ff21514d8981 71 #define DMAREQ_TIMER0_CC2 ((24 << 16) + 3) /**< DMA channel select for TIMER0_CC2 */
AnnaBridge 156:ff21514d8981 72 #define DMAREQ_TIMER1_UFOF ((25 << 16) + 0) /**< DMA channel select for TIMER1_UFOF */
AnnaBridge 156:ff21514d8981 73 #define DMAREQ_TIMER1_CC0 ((25 << 16) + 1) /**< DMA channel select for TIMER1_CC0 */
AnnaBridge 156:ff21514d8981 74 #define DMAREQ_TIMER1_CC1 ((25 << 16) + 2) /**< DMA channel select for TIMER1_CC1 */
AnnaBridge 156:ff21514d8981 75 #define DMAREQ_TIMER1_CC2 ((25 << 16) + 3) /**< DMA channel select for TIMER1_CC2 */
AnnaBridge 156:ff21514d8981 76 #define DMAREQ_TIMER2_UFOF ((26 << 16) + 0) /**< DMA channel select for TIMER2_UFOF */
AnnaBridge 156:ff21514d8981 77 #define DMAREQ_TIMER2_CC0 ((26 << 16) + 1) /**< DMA channel select for TIMER2_CC0 */
AnnaBridge 156:ff21514d8981 78 #define DMAREQ_TIMER2_CC1 ((26 << 16) + 2) /**< DMA channel select for TIMER2_CC1 */
AnnaBridge 156:ff21514d8981 79 #define DMAREQ_TIMER2_CC2 ((26 << 16) + 3) /**< DMA channel select for TIMER2_CC2 */
AnnaBridge 156:ff21514d8981 80 #define DMAREQ_TIMER3_UFOF ((27 << 16) + 0) /**< DMA channel select for TIMER3_UFOF */
AnnaBridge 156:ff21514d8981 81 #define DMAREQ_TIMER3_CC0 ((27 << 16) + 1) /**< DMA channel select for TIMER3_CC0 */
AnnaBridge 156:ff21514d8981 82 #define DMAREQ_TIMER3_CC1 ((27 << 16) + 2) /**< DMA channel select for TIMER3_CC1 */
AnnaBridge 156:ff21514d8981 83 #define DMAREQ_TIMER3_CC2 ((27 << 16) + 3) /**< DMA channel select for TIMER3_CC2 */
AnnaBridge 156:ff21514d8981 84 #define DMAREQ_UART0_RXDATAV ((44 << 16) + 0) /**< DMA channel select for UART0_RXDATAV */
AnnaBridge 156:ff21514d8981 85 #define DMAREQ_UART0_TXBL ((44 << 16) + 1) /**< DMA channel select for UART0_TXBL */
AnnaBridge 156:ff21514d8981 86 #define DMAREQ_UART0_TXEMPTY ((44 << 16) + 2) /**< DMA channel select for UART0_TXEMPTY */
AnnaBridge 156:ff21514d8981 87 #define DMAREQ_UART1_RXDATAV ((45 << 16) + 0) /**< DMA channel select for UART1_RXDATAV */
AnnaBridge 156:ff21514d8981 88 #define DMAREQ_UART1_TXBL ((45 << 16) + 1) /**< DMA channel select for UART1_TXBL */
AnnaBridge 156:ff21514d8981 89 #define DMAREQ_UART1_TXEMPTY ((45 << 16) + 2) /**< DMA channel select for UART1_TXEMPTY */
AnnaBridge 156:ff21514d8981 90 #define DMAREQ_MSC_WDATA ((48 << 16) + 0) /**< DMA channel select for MSC_WDATA */
AnnaBridge 156:ff21514d8981 91 #define DMAREQ_AES_DATAWR ((49 << 16) + 0) /**< DMA channel select for AES_DATAWR */
AnnaBridge 156:ff21514d8981 92 #define DMAREQ_AES_XORDATAWR ((49 << 16) + 1) /**< DMA channel select for AES_XORDATAWR */
AnnaBridge 156:ff21514d8981 93 #define DMAREQ_AES_DATARD ((49 << 16) + 2) /**< DMA channel select for AES_DATARD */
AnnaBridge 156:ff21514d8981 94 #define DMAREQ_AES_KEYWR ((49 << 16) + 3) /**< DMA channel select for AES_KEYWR */
AnnaBridge 156:ff21514d8981 95 #define DMAREQ_LESENSE_BUFDATAV ((50 << 16) + 0) /**< DMA channel select for LESENSE_BUFDATAV */
AnnaBridge 156:ff21514d8981 96 #define DMAREQ_EBI_PXL0EMPTY ((51 << 16) + 0) /**< DMA channel select for EBI_PXL0EMPTY */
AnnaBridge 156:ff21514d8981 97 #define DMAREQ_EBI_PXL1EMPTY ((51 << 16) + 1) /**< DMA channel select for EBI_PXL1EMPTY */
AnnaBridge 156:ff21514d8981 98 #define DMAREQ_EBI_PXLFULL ((51 << 16) + 2) /**< DMA channel select for EBI_PXLFULL */
AnnaBridge 156:ff21514d8981 99 #define DMAREQ_EBI_DDEMPTY ((51 << 16) + 3) /**< DMA channel select for EBI_DDEMPTY */
AnnaBridge 156:ff21514d8981 100
AnnaBridge 156:ff21514d8981 101 /** @} End of group EFM32LG_DMAREQ */
AnnaBridge 156:ff21514d8981 102 /** @} End of group Parts */
AnnaBridge 156:ff21514d8981 103