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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_EFM32LG_STK3600/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_devinfo.h@156:ff21514d8981, 2017-11-08 (annotated)

Committer:
AnnaBridge
Date:
Wed Nov 08 17:18:06 2017 +0000
Revision:
156:ff21514d8981
Reverting back to release 154 of the mbed library

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 156:ff21514d8981 1 /**************************************************************************//**
AnnaBridge 156:ff21514d8981 2 * @file efm32lg_devinfo.h
AnnaBridge 156:ff21514d8981 3 * @brief EFM32LG_DEVINFO register and bit field definitions
AnnaBridge 156:ff21514d8981 4 * @version 5.1.2
AnnaBridge 156:ff21514d8981 5 ******************************************************************************
AnnaBridge 156:ff21514d8981 6 * @section License
AnnaBridge 156:ff21514d8981 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
AnnaBridge 156:ff21514d8981 8 ******************************************************************************
AnnaBridge 156:ff21514d8981 9 *
AnnaBridge 156:ff21514d8981 10 * Permission is granted to anyone to use this software for any purpose,
AnnaBridge 156:ff21514d8981 11 * including commercial applications, and to alter it and redistribute it
AnnaBridge 156:ff21514d8981 12 * freely, subject to the following restrictions:
AnnaBridge 156:ff21514d8981 13 *
AnnaBridge 156:ff21514d8981 14 * 1. The origin of this software must not be misrepresented; you must not
AnnaBridge 156:ff21514d8981 15 * claim that you wrote the original software.@n
AnnaBridge 156:ff21514d8981 16 * 2. Altered source versions must be plainly marked as such, and must not be
AnnaBridge 156:ff21514d8981 17 * misrepresented as being the original software.@n
AnnaBridge 156:ff21514d8981 18 * 3. This notice may not be removed or altered from any source distribution.
AnnaBridge 156:ff21514d8981 19 *
AnnaBridge 156:ff21514d8981 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
AnnaBridge 156:ff21514d8981 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
AnnaBridge 156:ff21514d8981 22 * providing the Software "AS IS", with no express or implied warranties of any
AnnaBridge 156:ff21514d8981 23 * kind, including, but not limited to, any implied warranties of
AnnaBridge 156:ff21514d8981 24 * merchantability or fitness for any particular purpose or warranties against
AnnaBridge 156:ff21514d8981 25 * infringement of any proprietary rights of a third party.
AnnaBridge 156:ff21514d8981 26 *
AnnaBridge 156:ff21514d8981 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
AnnaBridge 156:ff21514d8981 28 * incidental, or special damages, or any other relief, or for any claim by
AnnaBridge 156:ff21514d8981 29 * any third party, arising from your use of this Software.
AnnaBridge 156:ff21514d8981 30 *
AnnaBridge 156:ff21514d8981 31 *****************************************************************************/
AnnaBridge 156:ff21514d8981 32 /**************************************************************************//**
AnnaBridge 156:ff21514d8981 33 * @addtogroup Parts
AnnaBridge 156:ff21514d8981 34 * @{
AnnaBridge 156:ff21514d8981 35 ******************************************************************************/
AnnaBridge 156:ff21514d8981 36 /**************************************************************************//**
AnnaBridge 156:ff21514d8981 37 * @defgroup EFM32LG_DEVINFO
AnnaBridge 156:ff21514d8981 38 * @{
AnnaBridge 156:ff21514d8981 39 *****************************************************************************/
AnnaBridge 156:ff21514d8981 40 typedef struct
AnnaBridge 156:ff21514d8981 41 {
AnnaBridge 156:ff21514d8981 42 __IM uint32_t CAL; /**< Calibration temperature and checksum */
AnnaBridge 156:ff21514d8981 43 __IM uint32_t ADC0CAL0; /**< ADC0 Calibration register 0 */
AnnaBridge 156:ff21514d8981 44 __IM uint32_t ADC0CAL1; /**< ADC0 Calibration register 1 */
AnnaBridge 156:ff21514d8981 45 __IM uint32_t ADC0CAL2; /**< ADC0 Calibration register 2 */
AnnaBridge 156:ff21514d8981 46 uint32_t RESERVED0[2]; /**< Reserved */
AnnaBridge 156:ff21514d8981 47 __IM uint32_t DAC0CAL0; /**< DAC calibrartion register 0 */
AnnaBridge 156:ff21514d8981 48 __IM uint32_t DAC0CAL1; /**< DAC calibrartion register 1 */
AnnaBridge 156:ff21514d8981 49 __IM uint32_t DAC0CAL2; /**< DAC calibrartion register 2 */
AnnaBridge 156:ff21514d8981 50 __IM uint32_t AUXHFRCOCAL0; /**< AUXHFRCO calibration register 0 */
AnnaBridge 156:ff21514d8981 51 __IM uint32_t AUXHFRCOCAL1; /**< AUXHFRCO calibration register 1 */
AnnaBridge 156:ff21514d8981 52 __IM uint32_t HFRCOCAL0; /**< HFRCO calibration register 0 */
AnnaBridge 156:ff21514d8981 53 __IM uint32_t HFRCOCAL1; /**< HFRCO calibration register 1 */
AnnaBridge 156:ff21514d8981 54 __IM uint32_t MEMINFO; /**< Memory information */
AnnaBridge 156:ff21514d8981 55 uint32_t RESERVED2[2]; /**< Reserved */
AnnaBridge 156:ff21514d8981 56 __IM uint32_t UNIQUEL; /**< Low 32 bits of device unique number */
AnnaBridge 156:ff21514d8981 57 __IM uint32_t UNIQUEH; /**< High 32 bits of device unique number */
AnnaBridge 156:ff21514d8981 58 __IM uint32_t MSIZE; /**< Flash and SRAM Memory size in KiloBytes */
AnnaBridge 156:ff21514d8981 59 __IM uint32_t PART; /**< Part description */
AnnaBridge 156:ff21514d8981 60 } DEVINFO_TypeDef; /** @} */
AnnaBridge 156:ff21514d8981 61
AnnaBridge 156:ff21514d8981 62 /**************************************************************************//**
AnnaBridge 156:ff21514d8981 63 * @defgroup EFM32LG_DEVINFO_BitFields
AnnaBridge 156:ff21514d8981 64 * @{
AnnaBridge 156:ff21514d8981 65 *****************************************************************************/
AnnaBridge 156:ff21514d8981 66 /* Bit fields for EFM32LG_DEVINFO */
AnnaBridge 156:ff21514d8981 67 #define _DEVINFO_CAL_CRC_MASK 0x0000FFFFUL /**< Integrity CRC checksum mask */
AnnaBridge 156:ff21514d8981 68 #define _DEVINFO_CAL_CRC_SHIFT 0 /**< Integrity CRC checksum shift */
AnnaBridge 156:ff21514d8981 69 #define _DEVINFO_CAL_TEMP_MASK 0x00FF0000UL /**< Calibration temperature, DegC, mask */
AnnaBridge 156:ff21514d8981 70 #define _DEVINFO_CAL_TEMP_SHIFT 16 /**< Calibration temperature shift */
AnnaBridge 156:ff21514d8981 71 #define _DEVINFO_ADC0CAL0_1V25_GAIN_MASK 0x00007F00UL /**< Gain for 1V25 reference, mask */
AnnaBridge 156:ff21514d8981 72 #define _DEVINFO_ADC0CAL0_1V25_GAIN_SHIFT 8 /**< Gain for 1V25 reference, shift */
AnnaBridge 156:ff21514d8981 73 #define _DEVINFO_ADC0CAL0_1V25_OFFSET_MASK 0x0000007FUL /**< Offset for 1V25 reference, mask */
AnnaBridge 156:ff21514d8981 74 #define _DEVINFO_ADC0CAL0_1V25_OFFSET_SHIFT 0 /**< Offset for 1V25 reference, shift */
AnnaBridge 156:ff21514d8981 75 #define _DEVINFO_ADC0CAL0_2V5_GAIN_MASK 0x7F000000UL /**< Gain for 2V5 reference, mask */
AnnaBridge 156:ff21514d8981 76 #define _DEVINFO_ADC0CAL0_2V5_GAIN_SHIFT 24 /**< Gain for 2V5 reference, shift */
AnnaBridge 156:ff21514d8981 77 #define _DEVINFO_ADC0CAL0_2V5_OFFSET_MASK 0x007F0000UL /**< Offset for 2V5 reference, mask */
AnnaBridge 156:ff21514d8981 78 #define _DEVINFO_ADC0CAL0_2V5_OFFSET_SHIFT 16 /**< Offset for 2V5 reference, shift */
AnnaBridge 156:ff21514d8981 79 #define _DEVINFO_ADC0CAL1_VDD_GAIN_MASK 0x00007F00UL /**< Gain for VDD reference, mask */
AnnaBridge 156:ff21514d8981 80 #define _DEVINFO_ADC0CAL1_VDD_GAIN_SHIFT 8 /**< Gain for VDD reference, shift */
AnnaBridge 156:ff21514d8981 81 #define _DEVINFO_ADC0CAL1_VDD_OFFSET_MASK 0x0000007FUL /**< Offset for VDD reference, mask */
AnnaBridge 156:ff21514d8981 82 #define _DEVINFO_ADC0CAL1_VDD_OFFSET_SHIFT 0 /**< Offset for VDD reference, shift */
AnnaBridge 156:ff21514d8981 83 #define _DEVINFO_ADC0CAL1_5VDIFF_GAIN_MASK 0x7F000000UL /**< Gain 5VDIFF for 5VDIFF reference, mask */
AnnaBridge 156:ff21514d8981 84 #define _DEVINFO_ADC0CAL1_5VDIFF_GAIN_SHIFT 24 /**< Gain for 5VDIFF reference, mask */
AnnaBridge 156:ff21514d8981 85 #define _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_MASK 0x007F0000UL /**< Offset for 5VDIFF reference, mask */
AnnaBridge 156:ff21514d8981 86 #define _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_SHIFT 16 /**< Offset for 5VDIFF reference, shift */
AnnaBridge 156:ff21514d8981 87 #define _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_MASK 0x0000007FUL /**< Offset for 2XVDDVSS reference, mask */
AnnaBridge 156:ff21514d8981 88 #define _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_SHIFT 0 /**< Offset for 2XVDDVSS reference, shift */
AnnaBridge 156:ff21514d8981 89 #define _DEVINFO_ADC0CAL2_TEMP1V25_MASK 0xFFF00000UL /**< Temperature reading at 1V25 reference, mask */
AnnaBridge 156:ff21514d8981 90 #define _DEVINFO_ADC0CAL2_TEMP1V25_SHIFT 20 /**< Temperature reading at 1V25 reference, DegC */
AnnaBridge 156:ff21514d8981 91 #define _DEVINFO_DAC0CAL0_1V25_GAIN_MASK 0x007F0000UL /**< Gain for 1V25 reference, mask */
AnnaBridge 156:ff21514d8981 92 #define _DEVINFO_DAC0CAL0_1V25_GAIN_SHIFT 16 /**< Gain for 1V25 reference, shift */
AnnaBridge 156:ff21514d8981 93 #define _DEVINFO_DAC0CAL0_1V25_CH1_OFFSET_MASK 0x00003F00UL /**< Channel 1 offset for 1V25 reference, mask */
AnnaBridge 156:ff21514d8981 94 #define _DEVINFO_DAC0CAL0_1V25_CH1_OFFSET_SHIFT 8 /**< Channel 1 offset for 1V25 reference, shift */
AnnaBridge 156:ff21514d8981 95 #define _DEVINFO_DAC0CAL0_1V25_CH0_OFFSET_MASK 0x0000003FUL /**< Channel 0 offset for 1V25 reference, mask */
AnnaBridge 156:ff21514d8981 96 #define _DEVINFO_DAC0CAL0_1V25_CH0_OFFSET_SHIFT 0 /**< Channel 0 offset for 1V25 reference, shift */
AnnaBridge 156:ff21514d8981 97 #define _DEVINFO_DAC0CAL1_2V5_GAIN_MASK 0x007F0000UL /**< Gain for 2V5 reference, mask */
AnnaBridge 156:ff21514d8981 98 #define _DEVINFO_DAC0CAL1_2V5_GAIN_SHIFT 16 /**< Gain for 2V5 reference, shift */
AnnaBridge 156:ff21514d8981 99 #define _DEVINFO_DAC0CAL1_2V5_CH1_OFFSET_MASK 0x00003F00UL /**< Channel 1 offset for 2V5 reference, mask */
AnnaBridge 156:ff21514d8981 100 #define _DEVINFO_DAC0CAL1_2V5_CH1_OFFSET_SHIFT 8 /**< Channel 1 offset for 2V5 reference, shift */
AnnaBridge 156:ff21514d8981 101 #define _DEVINFO_DAC0CAL1_2V5_CH0_OFFSET_MASK 0x0000003FUL /**< Channel 0 offset for 2V5 reference, mask */
AnnaBridge 156:ff21514d8981 102 #define _DEVINFO_DAC0CAL1_2V5_CH0_OFFSET_SHIFT 0 /**< Channel 0 offset for 2V5 reference, shift */
AnnaBridge 156:ff21514d8981 103 #define _DEVINFO_DAC0CAL2_VDD_GAIN_MASK 0x007F0000UL /**< Gain for VDD reference, mask */
AnnaBridge 156:ff21514d8981 104 #define _DEVINFO_DAC0CAL2_VDD_GAIN_SHIFT 16 /**< Gain for VDD reference, shift */
AnnaBridge 156:ff21514d8981 105 #define _DEVINFO_DAC0CAL2_VDD_CH1_OFFSET_MASK 0x00003F00UL /**< Channel 1 offset for VDD reference, mask */
AnnaBridge 156:ff21514d8981 106 #define _DEVINFO_DAC0CAL2_VDD_CH1_OFFSET_SHIFT 8 /**< Channel 1 offset for VDD reference, shift */
AnnaBridge 156:ff21514d8981 107 #define _DEVINFO_DAC0CAL2_VDD_CH0_OFFSET_MASK 0x0000003FUL /**< Channel 0 offset for VDD reference, mask */
AnnaBridge 156:ff21514d8981 108 #define _DEVINFO_DAC0CAL2_VDD_CH0_OFFSET_SHIFT 0 /**< Channel 0 offset for VDD reference, shift*/
AnnaBridge 156:ff21514d8981 109 #define _DEVINFO_AUXHFRCOCAL0_BAND1_MASK 0x000000FFUL /**< 1MHz tuning value for AUXHFRCO, mask */
AnnaBridge 156:ff21514d8981 110 #define _DEVINFO_AUXHFRCOCAL0_BAND1_SHIFT 0 /**< 1MHz tuning value for AUXHFRCO, shift */
AnnaBridge 156:ff21514d8981 111 #define _DEVINFO_AUXHFRCOCAL0_BAND7_MASK 0x0000FF00UL /**< 7MHz tuning value for AUXHFRCO, mask */
AnnaBridge 156:ff21514d8981 112 #define _DEVINFO_AUXHFRCOCAL0_BAND7_SHIFT 8 /**< 7MHz tuning value for AUXHFRCO, shift */
AnnaBridge 156:ff21514d8981 113 #define _DEVINFO_AUXHFRCOCAL0_BAND11_MASK 0x00FF0000UL /**< 11MHz tuning value for AUXHFRCO, mask */
AnnaBridge 156:ff21514d8981 114 #define _DEVINFO_AUXHFRCOCAL0_BAND11_SHIFT 16 /**< 11MHz tuning value for AUXHFRCO, shift */
AnnaBridge 156:ff21514d8981 115 #define _DEVINFO_AUXHFRCOCAL0_BAND14_MASK 0xFF000000UL /**< 14MHz tuning value for AUXHFRCO, mask */
AnnaBridge 156:ff21514d8981 116 #define _DEVINFO_AUXHFRCOCAL0_BAND14_SHIFT 24 /**< 14MHz tuning value for AUXHFRCO, shift */
AnnaBridge 156:ff21514d8981 117 #define _DEVINFO_AUXHFRCOCAL1_BAND21_MASK 0x000000FFUL /**< 21MHz tuning value for AUXHFRCO, mask */
AnnaBridge 156:ff21514d8981 118 #define _DEVINFO_AUXHFRCOCAL1_BAND21_SHIFT 0 /**< 21MHz tuning value for AUXHFRCO, shift */
AnnaBridge 156:ff21514d8981 119 #define _DEVINFO_AUXHFRCOCAL1_BAND28_MASK 0x0000FF00UL /**< 28MHz tuning value for AUXHFRCO, shift */
AnnaBridge 156:ff21514d8981 120 #define _DEVINFO_AUXHFRCOCAL1_BAND28_SHIFT 8 /**< 28MHz tuning value for AUXHFRCO, mask */
AnnaBridge 156:ff21514d8981 121 #define _DEVINFO_HFRCOCAL0_BAND1_MASK 0x000000FFUL /**< 1MHz tuning value for HFRCO, mask */
AnnaBridge 156:ff21514d8981 122 #define _DEVINFO_HFRCOCAL0_BAND1_SHIFT 0 /**< 1MHz tuning value for HFRCO, shift */
AnnaBridge 156:ff21514d8981 123 #define _DEVINFO_HFRCOCAL0_BAND7_MASK 0x0000FF00UL /**< 7MHz tuning value for HFRCO, mask */
AnnaBridge 156:ff21514d8981 124 #define _DEVINFO_HFRCOCAL0_BAND7_SHIFT 8 /**< 7MHz tuning value for HFRCO, shift */
AnnaBridge 156:ff21514d8981 125 #define _DEVINFO_HFRCOCAL0_BAND11_MASK 0x00FF0000UL /**< 11MHz tuning value for HFRCO, mask */
AnnaBridge 156:ff21514d8981 126 #define _DEVINFO_HFRCOCAL0_BAND11_SHIFT 16 /**< 11MHz tuning value for HFRCO, shift */
AnnaBridge 156:ff21514d8981 127 #define _DEVINFO_HFRCOCAL0_BAND14_MASK 0xFF000000UL /**< 14MHz tuning value for HFRCO, mask */
AnnaBridge 156:ff21514d8981 128 #define _DEVINFO_HFRCOCAL0_BAND14_SHIFT 24 /**< 14MHz tuning value for HFRCO, shift */
AnnaBridge 156:ff21514d8981 129 #define _DEVINFO_HFRCOCAL1_BAND21_MASK 0x000000FFUL /**< 21MHz tuning value for HFRCO, mask */
AnnaBridge 156:ff21514d8981 130 #define _DEVINFO_HFRCOCAL1_BAND21_SHIFT 0 /**< 21MHz tuning value for HFRCO, shift */
AnnaBridge 156:ff21514d8981 131 #define _DEVINFO_HFRCOCAL1_BAND28_MASK 0x0000FF00UL /**< 28MHz tuning value for HFRCO, shift */
AnnaBridge 156:ff21514d8981 132 #define _DEVINFO_HFRCOCAL1_BAND28_SHIFT 8 /**< 28MHz tuning value for HFRCO, mask */
AnnaBridge 156:ff21514d8981 133 #define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK 0xFF000000UL /**< Flash page size (refer to ref.man for encoding) mask */
AnnaBridge 156:ff21514d8981 134 #define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT 24 /**< Flash page size shift */
AnnaBridge 156:ff21514d8981 135 #define _DEVINFO_UNIQUEL_MASK 0xFFFFFFFFUL /**< Lower part of 64-bit device unique number */
AnnaBridge 156:ff21514d8981 136 #define _DEVINFO_UNIQUEL_SHIFT 0 /**< Unique Low 32-bit shift */
AnnaBridge 156:ff21514d8981 137 #define _DEVINFO_UNIQUEH_MASK 0xFFFFFFFFUL /**< High part of 64-bit device unique number */
AnnaBridge 156:ff21514d8981 138 #define _DEVINFO_UNIQUEH_SHIFT 0 /**< Unique High 32-bit shift */
AnnaBridge 156:ff21514d8981 139 #define _DEVINFO_MSIZE_SRAM_MASK 0xFFFF0000UL /**< Flash size in kilobytes */
AnnaBridge 156:ff21514d8981 140 #define _DEVINFO_MSIZE_SRAM_SHIFT 16 /**< Bit position for flash size */
AnnaBridge 156:ff21514d8981 141 #define _DEVINFO_MSIZE_FLASH_MASK 0x0000FFFFUL /**< SRAM size in kilobytes */
AnnaBridge 156:ff21514d8981 142 #define _DEVINFO_MSIZE_FLASH_SHIFT 0 /**< Bit position for SRAM size */
AnnaBridge 156:ff21514d8981 143 #define _DEVINFO_PART_PROD_REV_MASK 0xFF000000UL /**< Production revision */
AnnaBridge 156:ff21514d8981 144 #define _DEVINFO_PART_PROD_REV_SHIFT 24 /**< Bit position for production revision */
AnnaBridge 156:ff21514d8981 145 #define _DEVINFO_PART_DEVICE_FAMILY_MASK 0x00FF0000UL /**< Device Family, 0x47 for Gecko */
AnnaBridge 156:ff21514d8981 146 #define _DEVINFO_PART_DEVICE_FAMILY_SHIFT 16 /**< Bit position for device family */
AnnaBridge 156:ff21514d8981 147 /* Legacy family #defines */
AnnaBridge 156:ff21514d8981 148 #define _DEVINFO_PART_DEVICE_FAMILY_G 71 /**< Gecko Device Family */
AnnaBridge 156:ff21514d8981 149 #define _DEVINFO_PART_DEVICE_FAMILY_GG 72 /**< Giant Gecko Device Family */
AnnaBridge 156:ff21514d8981 150 #define _DEVINFO_PART_DEVICE_FAMILY_TG 73 /**< Tiny Gecko Device Family */
AnnaBridge 156:ff21514d8981 151 #define _DEVINFO_PART_DEVICE_FAMILY_LG 74 /**< Leopard Gecko Device Family */
AnnaBridge 156:ff21514d8981 152 #define _DEVINFO_PART_DEVICE_FAMILY_WG 75 /**< Wonder Gecko Device Family */
AnnaBridge 156:ff21514d8981 153 #define _DEVINFO_PART_DEVICE_FAMILY_ZG 76 /**< Zero Gecko Device Family */
AnnaBridge 156:ff21514d8981 154 #define _DEVINFO_PART_DEVICE_FAMILY_HG 77 /**< Happy Gecko Device Family */
AnnaBridge 156:ff21514d8981 155 /* New style family #defines */
AnnaBridge 156:ff21514d8981 156 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32G 71 /**< Gecko Device Family */
AnnaBridge 156:ff21514d8981 157 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG 72 /**< Giant Gecko Device Family */
AnnaBridge 156:ff21514d8981 158 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG 73 /**< Tiny Gecko Device Family */
AnnaBridge 156:ff21514d8981 159 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG 74 /**< Leopard Gecko Device Family */
AnnaBridge 156:ff21514d8981 160 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG 75 /**< Wonder Gecko Device Family */
AnnaBridge 156:ff21514d8981 161 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG 76 /**< Zero Gecko Device Family */
AnnaBridge 156:ff21514d8981 162 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG 77 /**< Happy Gecko Device Family */
AnnaBridge 156:ff21514d8981 163 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32WG 120 /**< EZR Wonder Gecko Device Family */
AnnaBridge 156:ff21514d8981 164 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32LG 121 /**< EZR Leopard Gecko Device Family */
AnnaBridge 156:ff21514d8981 165 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32HG 122 /**< EZR Happy Gecko Device Family */
AnnaBridge 156:ff21514d8981 166 #define _DEVINFO_PART_DEVICE_NUMBER_MASK 0x0000FFFFUL /**< Device number */
AnnaBridge 156:ff21514d8981 167 #define _DEVINFO_PART_DEVICE_NUMBER_SHIFT 0 /**< Bit position for device number */
AnnaBridge 156:ff21514d8981 168
AnnaBridge 156:ff21514d8981 169 /** @} End of group EFM32LG_DEVINFO */
AnnaBridge 156:ff21514d8981 170 /** @} End of group Parts */
AnnaBridge 156:ff21514d8981 171