mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_F767ZI/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_fmc.h@136:ef9c61f8c49f, 2017-02-14 (annotated)

Committer:
Kojto
Date:
Tue Feb 14 11:24:20 2017 +0000
Revision:
136:ef9c61f8c49f
Parent:
135:176b8275d35d
Child:
139:856d2700e60b
Release 136 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3432: Target STM USBHOST support https://github.com/ARMmbed/mbed-os/pull/3432

3181: NUCLEO_F207ZG extending PeripheralPins.c: all available alternate functions can be used now https://github.com/ARMmbed/mbed-os/pull/3181

3626: NUCLEO_F412ZG : Add USB Device +Host https://github.com/ARMmbed/mbed-os/pull/3626

3628: Fix warnings https://github.com/ARMmbed/mbed-os/pull/3628

3629: STM32: L0 LL layer https://github.com/ARMmbed/mbed-os/pull/3629

3632: IDE Export support for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3632

3642: Missing IRQ pin fix for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3642

3664: Fix ncs36510 sleep definitions https://github.com/ARMmbed/mbed-os/pull/3664

3655: [STM32F4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3655

3657: [STM32L4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3657

3658: [STM32F3] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3658

3685: STM32: I2C: reset state machine https://github.com/ARMmbed/mbed-os/pull/3685

3692: uVisor: Standardize available legacy heap and stack https://github.com/ARMmbed/mbed-os/pull/3692

3621: Fix for #2884, LPC824: export to LPCXpresso, target running with wron https://github.com/ARMmbed/mbed-os/pull/3621

3649: [STM32F7] Modify folder structure  https://github.com/ARMmbed/mbed-os/pull/3649

3695: Enforce device_name is valid in targets.json https://github.com/ARMmbed/mbed-os/pull/3695

3723: NCS36510: spi_format function bug fix https://github.com/ARMmbed/mbed-os/pull/3723

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 126:abea610beb85 1 /**
AnnaBridge 126:abea610beb85 2 ******************************************************************************
AnnaBridge 126:abea610beb85 3 * @file stm32f7xx_ll_fmc.h
AnnaBridge 126:abea610beb85 4 * @author MCD Application Team
<> 135:176b8275d35d 5 * @version V1.1.2
<> 135:176b8275d35d 6 * @date 23-September-2016
AnnaBridge 126:abea610beb85 7 * @brief Header file of FMC HAL module.
AnnaBridge 126:abea610beb85 8 ******************************************************************************
AnnaBridge 126:abea610beb85 9 * @attention
AnnaBridge 126:abea610beb85 10 *
AnnaBridge 126:abea610beb85 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge 126:abea610beb85 12 *
AnnaBridge 126:abea610beb85 13 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 126:abea610beb85 14 * are permitted provided that the following conditions are met:
AnnaBridge 126:abea610beb85 15 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 126:abea610beb85 16 * this list of conditions and the following disclaimer.
AnnaBridge 126:abea610beb85 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 126:abea610beb85 18 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 126:abea610beb85 19 * and/or other materials provided with the distribution.
AnnaBridge 126:abea610beb85 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 126:abea610beb85 21 * may be used to endorse or promote products derived from this software
AnnaBridge 126:abea610beb85 22 * without specific prior written permission.
AnnaBridge 126:abea610beb85 23 *
AnnaBridge 126:abea610beb85 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 126:abea610beb85 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 126:abea610beb85 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 126:abea610beb85 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 126:abea610beb85 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 126:abea610beb85 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 126:abea610beb85 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 126:abea610beb85 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 126:abea610beb85 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 126:abea610beb85 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 126:abea610beb85 34 *
AnnaBridge 126:abea610beb85 35 ******************************************************************************
AnnaBridge 126:abea610beb85 36 */
AnnaBridge 126:abea610beb85 37
AnnaBridge 126:abea610beb85 38 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 126:abea610beb85 39 #ifndef __STM32F7xx_LL_FMC_H
AnnaBridge 126:abea610beb85 40 #define __STM32F7xx_LL_FMC_H
AnnaBridge 126:abea610beb85 41
AnnaBridge 126:abea610beb85 42 #ifdef __cplusplus
AnnaBridge 126:abea610beb85 43 extern "C" {
AnnaBridge 126:abea610beb85 44 #endif
AnnaBridge 126:abea610beb85 45
AnnaBridge 126:abea610beb85 46 /* Includes ------------------------------------------------------------------*/
AnnaBridge 126:abea610beb85 47 #include "stm32f7xx_hal_def.h"
AnnaBridge 126:abea610beb85 48
AnnaBridge 126:abea610beb85 49 /** @addtogroup STM32F7xx_HAL_Driver
AnnaBridge 126:abea610beb85 50 * @{
AnnaBridge 126:abea610beb85 51 */
AnnaBridge 126:abea610beb85 52
AnnaBridge 126:abea610beb85 53 /** @addtogroup FMC_LL
AnnaBridge 126:abea610beb85 54 * @{
AnnaBridge 126:abea610beb85 55 */
AnnaBridge 126:abea610beb85 56
AnnaBridge 126:abea610beb85 57 /** @addtogroup FMC_LL_Private_Macros
AnnaBridge 126:abea610beb85 58 * @{
AnnaBridge 126:abea610beb85 59 */
AnnaBridge 126:abea610beb85 60 #define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) || \
AnnaBridge 126:abea610beb85 61 ((BANK) == FMC_NORSRAM_BANK2) || \
AnnaBridge 126:abea610beb85 62 ((BANK) == FMC_NORSRAM_BANK3) || \
AnnaBridge 126:abea610beb85 63 ((BANK) == FMC_NORSRAM_BANK4))
AnnaBridge 126:abea610beb85 64
AnnaBridge 126:abea610beb85 65 #define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
AnnaBridge 126:abea610beb85 66 ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
AnnaBridge 126:abea610beb85 67
AnnaBridge 126:abea610beb85 68 #define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \
AnnaBridge 126:abea610beb85 69 ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \
AnnaBridge 126:abea610beb85 70 ((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
AnnaBridge 126:abea610beb85 71
AnnaBridge 126:abea610beb85 72 #define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \
AnnaBridge 126:abea610beb85 73 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
AnnaBridge 126:abea610beb85 74 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
AnnaBridge 126:abea610beb85 75
AnnaBridge 126:abea610beb85 76 #define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \
AnnaBridge 126:abea610beb85 77 ((__MODE__) == FMC_ACCESS_MODE_B) || \
AnnaBridge 126:abea610beb85 78 ((__MODE__) == FMC_ACCESS_MODE_C) || \
AnnaBridge 126:abea610beb85 79 ((__MODE__) == FMC_ACCESS_MODE_D))
AnnaBridge 126:abea610beb85 80
AnnaBridge 126:abea610beb85 81 #define IS_FMC_NAND_BANK(BANK) ((BANK) == FMC_NAND_BANK3)
AnnaBridge 126:abea610beb85 82
AnnaBridge 126:abea610beb85 83 #define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_WAIT_FEATURE_DISABLE) || \
AnnaBridge 126:abea610beb85 84 ((FEATURE) == FMC_NAND_WAIT_FEATURE_ENABLE))
AnnaBridge 126:abea610beb85 85
AnnaBridge 126:abea610beb85 86 #define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_MEM_BUS_WIDTH_8) || \
AnnaBridge 126:abea610beb85 87 ((WIDTH) == FMC_NAND_MEM_BUS_WIDTH_16))
AnnaBridge 126:abea610beb85 88
AnnaBridge 126:abea610beb85 89 #define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) || \
AnnaBridge 126:abea610beb85 90 ((STATE) == FMC_NAND_ECC_ENABLE))
AnnaBridge 126:abea610beb85 91
AnnaBridge 126:abea610beb85 92 #define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
AnnaBridge 126:abea610beb85 93 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
AnnaBridge 126:abea610beb85 94 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
AnnaBridge 126:abea610beb85 95 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
AnnaBridge 126:abea610beb85 96 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
AnnaBridge 126:abea610beb85 97 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
AnnaBridge 126:abea610beb85 98
AnnaBridge 126:abea610beb85 99 #define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \
AnnaBridge 126:abea610beb85 100 ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \
AnnaBridge 126:abea610beb85 101 ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
AnnaBridge 126:abea610beb85 102
AnnaBridge 126:abea610beb85 103 #define IS_FMC_WRITE_PROTECTION(__WRITE__) (((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \
AnnaBridge 126:abea610beb85 104 ((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
AnnaBridge 126:abea610beb85 105
AnnaBridge 126:abea610beb85 106 #define IS_FMC_SDCLOCK_PERIOD(__PERIOD__) (((__PERIOD__) == FMC_SDRAM_CLOCK_DISABLE) || \
AnnaBridge 126:abea610beb85 107 ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_2) || \
AnnaBridge 126:abea610beb85 108 ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_3))
AnnaBridge 126:abea610beb85 109
AnnaBridge 126:abea610beb85 110 #define IS_FMC_READ_BURST(__RBURST__) (((__RBURST__) == FMC_SDRAM_RBURST_DISABLE) || \
AnnaBridge 126:abea610beb85 111 ((__RBURST__) == FMC_SDRAM_RBURST_ENABLE))
AnnaBridge 126:abea610beb85 112
AnnaBridge 126:abea610beb85 113 #define IS_FMC_READPIPE_DELAY(__DELAY__) (((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_0) || \
AnnaBridge 126:abea610beb85 114 ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_1) || \
AnnaBridge 126:abea610beb85 115 ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_2))
AnnaBridge 126:abea610beb85 116
AnnaBridge 126:abea610beb85 117 #define IS_FMC_COMMAND_MODE(__COMMAND__) (((__COMMAND__) == FMC_SDRAM_CMD_NORMAL_MODE) || \
AnnaBridge 126:abea610beb85 118 ((__COMMAND__) == FMC_SDRAM_CMD_CLK_ENABLE) || \
AnnaBridge 126:abea610beb85 119 ((__COMMAND__) == FMC_SDRAM_CMD_PALL) || \
AnnaBridge 126:abea610beb85 120 ((__COMMAND__) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \
AnnaBridge 126:abea610beb85 121 ((__COMMAND__) == FMC_SDRAM_CMD_LOAD_MODE) || \
AnnaBridge 126:abea610beb85 122 ((__COMMAND__) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \
AnnaBridge 126:abea610beb85 123 ((__COMMAND__) == FMC_SDRAM_CMD_POWERDOWN_MODE))
AnnaBridge 126:abea610beb85 124
AnnaBridge 126:abea610beb85 125 #define IS_FMC_COMMAND_TARGET(__TARGET__) (((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1) || \
AnnaBridge 126:abea610beb85 126 ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK2) || \
AnnaBridge 126:abea610beb85 127 ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1_2))
AnnaBridge 126:abea610beb85 128
AnnaBridge 126:abea610beb85 129 /** @defgroup FMC_TCLR_Setup_Time FMC TCLR Setup Time
AnnaBridge 126:abea610beb85 130 * @{
AnnaBridge 126:abea610beb85 131 */
AnnaBridge 126:abea610beb85 132 #define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255)
AnnaBridge 126:abea610beb85 133 /**
AnnaBridge 126:abea610beb85 134 * @}
AnnaBridge 126:abea610beb85 135 */
AnnaBridge 126:abea610beb85 136
AnnaBridge 126:abea610beb85 137 /** @defgroup FMC_TAR_Setup_Time FMC TAR Setup Time
AnnaBridge 126:abea610beb85 138 * @{
AnnaBridge 126:abea610beb85 139 */
AnnaBridge 126:abea610beb85 140 #define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
AnnaBridge 126:abea610beb85 141 /**
AnnaBridge 126:abea610beb85 142 * @}
AnnaBridge 126:abea610beb85 143 */
AnnaBridge 126:abea610beb85 144
AnnaBridge 126:abea610beb85 145 /** @defgroup FMC_Setup_Time FMC Setup Time
AnnaBridge 126:abea610beb85 146 * @{
AnnaBridge 126:abea610beb85 147 */
AnnaBridge 126:abea610beb85 148 #define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 254)
AnnaBridge 126:abea610beb85 149 /**
AnnaBridge 126:abea610beb85 150 * @}
AnnaBridge 126:abea610beb85 151 */
AnnaBridge 126:abea610beb85 152
AnnaBridge 126:abea610beb85 153 /** @defgroup FMC_Wait_Setup_Time FMC Wait Setup Time
AnnaBridge 126:abea610beb85 154 * @{
AnnaBridge 126:abea610beb85 155 */
AnnaBridge 126:abea610beb85 156 #define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 254)
AnnaBridge 126:abea610beb85 157 /**
AnnaBridge 126:abea610beb85 158 * @}
AnnaBridge 126:abea610beb85 159 */
AnnaBridge 126:abea610beb85 160
AnnaBridge 126:abea610beb85 161 /** @defgroup FMC_Hold_Setup_Time FMC Hold Setup Time
AnnaBridge 126:abea610beb85 162 * @{
AnnaBridge 126:abea610beb85 163 */
AnnaBridge 126:abea610beb85 164 #define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 254)
AnnaBridge 126:abea610beb85 165 /**
AnnaBridge 126:abea610beb85 166 * @}
AnnaBridge 126:abea610beb85 167 */
AnnaBridge 126:abea610beb85 168
AnnaBridge 126:abea610beb85 169 /** @defgroup FMC_HiZ_Setup_Time FMC HiZ Setup Time
AnnaBridge 126:abea610beb85 170 * @{
AnnaBridge 126:abea610beb85 171 */
AnnaBridge 126:abea610beb85 172 #define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 254)
AnnaBridge 126:abea610beb85 173 /**
AnnaBridge 126:abea610beb85 174 * @}
AnnaBridge 126:abea610beb85 175 */
AnnaBridge 126:abea610beb85 176
AnnaBridge 126:abea610beb85 177 #define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \
AnnaBridge 126:abea610beb85 178 ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
AnnaBridge 126:abea610beb85 179
AnnaBridge 126:abea610beb85 180 #define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
AnnaBridge 126:abea610beb85 181 ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
AnnaBridge 126:abea610beb85 182
AnnaBridge 126:abea610beb85 183 #define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \
AnnaBridge 126:abea610beb85 184 ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
AnnaBridge 126:abea610beb85 185
AnnaBridge 126:abea610beb85 186 #define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \
AnnaBridge 126:abea610beb85 187 ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
AnnaBridge 126:abea610beb85 188
AnnaBridge 126:abea610beb85 189 #define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \
AnnaBridge 126:abea610beb85 190 ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
AnnaBridge 126:abea610beb85 191
AnnaBridge 126:abea610beb85 192 #define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \
AnnaBridge 126:abea610beb85 193 ((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
AnnaBridge 126:abea610beb85 194
AnnaBridge 126:abea610beb85 195 #define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
AnnaBridge 126:abea610beb85 196 ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
AnnaBridge 126:abea610beb85 197
AnnaBridge 126:abea610beb85 198 /** @defgroup FMC_Data_Latency FMC Data Latency
AnnaBridge 126:abea610beb85 199 * @{
AnnaBridge 126:abea610beb85 200 */
AnnaBridge 126:abea610beb85 201 #define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
AnnaBridge 126:abea610beb85 202 /**
AnnaBridge 126:abea610beb85 203 * @}
AnnaBridge 126:abea610beb85 204 */
AnnaBridge 126:abea610beb85 205
AnnaBridge 126:abea610beb85 206 #define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \
AnnaBridge 126:abea610beb85 207 ((__BURST__) == FMC_WRITE_BURST_ENABLE))
AnnaBridge 126:abea610beb85 208
AnnaBridge 126:abea610beb85 209 #define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
AnnaBridge 126:abea610beb85 210 ((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
AnnaBridge 126:abea610beb85 211
AnnaBridge 126:abea610beb85 212
AnnaBridge 126:abea610beb85 213 /** @defgroup FMC_Address_Setup_Time FMC Address Setup Time
AnnaBridge 126:abea610beb85 214 * @{
AnnaBridge 126:abea610beb85 215 */
AnnaBridge 126:abea610beb85 216 #define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
AnnaBridge 126:abea610beb85 217 /**
AnnaBridge 126:abea610beb85 218 * @}
AnnaBridge 126:abea610beb85 219 */
AnnaBridge 126:abea610beb85 220
AnnaBridge 126:abea610beb85 221 /** @defgroup FMC_Address_Hold_Time FMC Address Hold Time
AnnaBridge 126:abea610beb85 222 * @{
AnnaBridge 126:abea610beb85 223 */
AnnaBridge 126:abea610beb85 224 #define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
AnnaBridge 126:abea610beb85 225 /**
AnnaBridge 126:abea610beb85 226 * @}
AnnaBridge 126:abea610beb85 227 */
AnnaBridge 126:abea610beb85 228
AnnaBridge 126:abea610beb85 229 /** @defgroup FMC_Data_Setup_Time FMC Data Setup Time
AnnaBridge 126:abea610beb85 230 * @{
AnnaBridge 126:abea610beb85 231 */
AnnaBridge 126:abea610beb85 232 #define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
AnnaBridge 126:abea610beb85 233 /**
AnnaBridge 126:abea610beb85 234 * @}
AnnaBridge 126:abea610beb85 235 */
AnnaBridge 126:abea610beb85 236
AnnaBridge 126:abea610beb85 237 /** @defgroup FMC_Bus_Turn_around_Duration FMC Bus Turn around Duration
AnnaBridge 126:abea610beb85 238 * @{
AnnaBridge 126:abea610beb85 239 */
AnnaBridge 126:abea610beb85 240 #define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
AnnaBridge 126:abea610beb85 241 /**
AnnaBridge 126:abea610beb85 242 * @}
AnnaBridge 126:abea610beb85 243 */
AnnaBridge 126:abea610beb85 244
AnnaBridge 126:abea610beb85 245 /** @defgroup FMC_CLK_Division FMC CLK Division
AnnaBridge 126:abea610beb85 246 * @{
AnnaBridge 126:abea610beb85 247 */
AnnaBridge 126:abea610beb85 248 #define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
AnnaBridge 126:abea610beb85 249 /**
AnnaBridge 126:abea610beb85 250 * @}
AnnaBridge 126:abea610beb85 251 */
AnnaBridge 126:abea610beb85 252
AnnaBridge 126:abea610beb85 253 /** @defgroup FMC_SDRAM_LoadToActive_Delay FMC SDRAM LoadToActive Delay
AnnaBridge 126:abea610beb85 254 * @{
AnnaBridge 126:abea610beb85 255 */
AnnaBridge 126:abea610beb85 256 #define IS_FMC_LOADTOACTIVE_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
AnnaBridge 126:abea610beb85 257 /**
AnnaBridge 126:abea610beb85 258 * @}
AnnaBridge 126:abea610beb85 259 */
AnnaBridge 126:abea610beb85 260
AnnaBridge 126:abea610beb85 261 /** @defgroup FMC_SDRAM_ExitSelfRefresh_Delay FMC SDRAM ExitSelfRefresh Delay
AnnaBridge 126:abea610beb85 262 * @{
AnnaBridge 126:abea610beb85 263 */
AnnaBridge 126:abea610beb85 264 #define IS_FMC_EXITSELFREFRESH_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
AnnaBridge 126:abea610beb85 265 /**
AnnaBridge 126:abea610beb85 266 * @}
AnnaBridge 126:abea610beb85 267 */
AnnaBridge 126:abea610beb85 268
AnnaBridge 126:abea610beb85 269 /** @defgroup FMC_SDRAM_SelfRefresh_Time FMC SDRAM SelfRefresh Time
AnnaBridge 126:abea610beb85 270 * @{
AnnaBridge 126:abea610beb85 271 */
AnnaBridge 126:abea610beb85 272 #define IS_FMC_SELFREFRESH_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 16))
AnnaBridge 126:abea610beb85 273 /**
AnnaBridge 126:abea610beb85 274 * @}
AnnaBridge 126:abea610beb85 275 */
AnnaBridge 126:abea610beb85 276
AnnaBridge 126:abea610beb85 277 /** @defgroup FMC_SDRAM_RowCycle_Delay FMC SDRAM RowCycle Delay
AnnaBridge 126:abea610beb85 278 * @{
AnnaBridge 126:abea610beb85 279 */
AnnaBridge 126:abea610beb85 280 #define IS_FMC_ROWCYCLE_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
AnnaBridge 126:abea610beb85 281 /**
AnnaBridge 126:abea610beb85 282 * @}
AnnaBridge 126:abea610beb85 283 */
AnnaBridge 126:abea610beb85 284
AnnaBridge 126:abea610beb85 285 /** @defgroup FMC_SDRAM_Write_Recovery_Time FMC SDRAM Write Recovery Time
AnnaBridge 126:abea610beb85 286 * @{
AnnaBridge 126:abea610beb85 287 */
AnnaBridge 126:abea610beb85 288 #define IS_FMC_WRITE_RECOVERY_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 16))
AnnaBridge 126:abea610beb85 289 /**
AnnaBridge 126:abea610beb85 290 * @}
AnnaBridge 126:abea610beb85 291 */
AnnaBridge 126:abea610beb85 292
AnnaBridge 126:abea610beb85 293 /** @defgroup FMC_SDRAM_RP_Delay FMC SDRAM RP Delay
AnnaBridge 126:abea610beb85 294 * @{
AnnaBridge 126:abea610beb85 295 */
AnnaBridge 126:abea610beb85 296 #define IS_FMC_RP_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
AnnaBridge 126:abea610beb85 297 /**
AnnaBridge 126:abea610beb85 298 * @}
AnnaBridge 126:abea610beb85 299 */
AnnaBridge 126:abea610beb85 300
AnnaBridge 126:abea610beb85 301 /** @defgroup FMC_SDRAM_RCD_Delay FMC SDRAM RCD Delay
AnnaBridge 126:abea610beb85 302 * @{
AnnaBridge 126:abea610beb85 303 */
AnnaBridge 126:abea610beb85 304 #define IS_FMC_RCD_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
AnnaBridge 126:abea610beb85 305 /**
AnnaBridge 126:abea610beb85 306 * @}
AnnaBridge 126:abea610beb85 307 */
AnnaBridge 126:abea610beb85 308
AnnaBridge 126:abea610beb85 309 /** @defgroup FMC_SDRAM_AutoRefresh_Number FMC SDRAM AutoRefresh Number
AnnaBridge 126:abea610beb85 310 * @{
AnnaBridge 126:abea610beb85 311 */
AnnaBridge 126:abea610beb85 312 #define IS_FMC_AUTOREFRESH_NUMBER(__NUMBER__) (((__NUMBER__) > 0) && ((__NUMBER__) <= 16))
AnnaBridge 126:abea610beb85 313 /**
AnnaBridge 126:abea610beb85 314 * @}
AnnaBridge 126:abea610beb85 315 */
AnnaBridge 126:abea610beb85 316
AnnaBridge 126:abea610beb85 317 /** @defgroup FMC_SDRAM_ModeRegister_Definition FMC SDRAM ModeRegister Definition
AnnaBridge 126:abea610beb85 318 * @{
AnnaBridge 126:abea610beb85 319 */
AnnaBridge 126:abea610beb85 320 #define IS_FMC_MODE_REGISTER(__CONTENT__) ((__CONTENT__) <= 8191)
AnnaBridge 126:abea610beb85 321 /**
AnnaBridge 126:abea610beb85 322 * @}
AnnaBridge 126:abea610beb85 323 */
AnnaBridge 126:abea610beb85 324
AnnaBridge 126:abea610beb85 325 /** @defgroup FMC_SDRAM_Refresh_rate FMC SDRAM Refresh rate
AnnaBridge 126:abea610beb85 326 * @{
AnnaBridge 126:abea610beb85 327 */
AnnaBridge 126:abea610beb85 328 #define IS_FMC_REFRESH_RATE(__RATE__) ((__RATE__) <= 8191)
AnnaBridge 126:abea610beb85 329 /**
AnnaBridge 126:abea610beb85 330 * @}
AnnaBridge 126:abea610beb85 331 */
AnnaBridge 126:abea610beb85 332
AnnaBridge 126:abea610beb85 333 /** @defgroup FMC_NORSRAM_Device_Instance FMC NORSRAM Device Instance
AnnaBridge 126:abea610beb85 334 * @{
AnnaBridge 126:abea610beb85 335 */
AnnaBridge 126:abea610beb85 336 #define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
AnnaBridge 126:abea610beb85 337 /**
AnnaBridge 126:abea610beb85 338 * @}
AnnaBridge 126:abea610beb85 339 */
AnnaBridge 126:abea610beb85 340
AnnaBridge 126:abea610beb85 341 /** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance FMC NORSRAM EXTENDED Device Instance
AnnaBridge 126:abea610beb85 342 * @{
AnnaBridge 126:abea610beb85 343 */
AnnaBridge 126:abea610beb85 344 #define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
AnnaBridge 126:abea610beb85 345 /**
AnnaBridge 126:abea610beb85 346 * @}
AnnaBridge 126:abea610beb85 347 */
AnnaBridge 126:abea610beb85 348
AnnaBridge 126:abea610beb85 349 /** @defgroup FMC_NAND_Device_Instance FMC NAND Device Instance
AnnaBridge 126:abea610beb85 350 * @{
AnnaBridge 126:abea610beb85 351 */
AnnaBridge 126:abea610beb85 352 #define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
AnnaBridge 126:abea610beb85 353 /**
AnnaBridge 126:abea610beb85 354 * @}
AnnaBridge 126:abea610beb85 355 */
AnnaBridge 126:abea610beb85 356
AnnaBridge 126:abea610beb85 357 /** @defgroup FMC_SDRAM_Device_Instance FMC SDRAM Device Instance
AnnaBridge 126:abea610beb85 358 * @{
AnnaBridge 126:abea610beb85 359 */
AnnaBridge 126:abea610beb85 360 #define IS_FMC_SDRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_SDRAM_DEVICE)
AnnaBridge 126:abea610beb85 361 /**
AnnaBridge 126:abea610beb85 362 * @}
AnnaBridge 126:abea610beb85 363 */
AnnaBridge 126:abea610beb85 364
AnnaBridge 126:abea610beb85 365 #define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) || \
AnnaBridge 126:abea610beb85 366 ((BANK) == FMC_SDRAM_BANK2))
AnnaBridge 126:abea610beb85 367
AnnaBridge 126:abea610beb85 368 #define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \
AnnaBridge 126:abea610beb85 369 ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \
AnnaBridge 126:abea610beb85 370 ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \
AnnaBridge 126:abea610beb85 371 ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
AnnaBridge 126:abea610beb85 372
AnnaBridge 126:abea610beb85 373 #define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) || \
AnnaBridge 126:abea610beb85 374 ((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) || \
AnnaBridge 126:abea610beb85 375 ((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
AnnaBridge 126:abea610beb85 376
AnnaBridge 126:abea610beb85 377 #define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \
AnnaBridge 126:abea610beb85 378 ((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
AnnaBridge 126:abea610beb85 379
AnnaBridge 126:abea610beb85 380
AnnaBridge 126:abea610beb85 381 #define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) || \
AnnaBridge 126:abea610beb85 382 ((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) || \
AnnaBridge 126:abea610beb85 383 ((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
AnnaBridge 126:abea610beb85 384
AnnaBridge 126:abea610beb85 385 #define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \
AnnaBridge 126:abea610beb85 386 ((__SIZE__) == FMC_PAGE_SIZE_128) || \
AnnaBridge 126:abea610beb85 387 ((__SIZE__) == FMC_PAGE_SIZE_256) || \
AnnaBridge 126:abea610beb85 388 ((__SIZE__) == FMC_PAGE_SIZE_512) || \
AnnaBridge 126:abea610beb85 389 ((__SIZE__) == FMC_PAGE_SIZE_1024))
AnnaBridge 126:abea610beb85 390
AnnaBridge 126:abea610beb85 391 #define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \
AnnaBridge 126:abea610beb85 392 ((__FIFO__) == FMC_WRITE_FIFO_ENABLE))
AnnaBridge 126:abea610beb85 393 /**
AnnaBridge 126:abea610beb85 394 * @}
AnnaBridge 126:abea610beb85 395 */
AnnaBridge 126:abea610beb85 396
AnnaBridge 126:abea610beb85 397 /* Exported typedef ----------------------------------------------------------*/
AnnaBridge 126:abea610beb85 398 /** @defgroup FMC_Exported_typedef FMC Low Layer Exported Types
AnnaBridge 126:abea610beb85 399 * @{
AnnaBridge 126:abea610beb85 400 */
AnnaBridge 126:abea610beb85 401 #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
AnnaBridge 126:abea610beb85 402 #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
AnnaBridge 126:abea610beb85 403 #define FMC_NAND_TypeDef FMC_Bank3_TypeDef
AnnaBridge 126:abea610beb85 404 #define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
AnnaBridge 126:abea610beb85 405
AnnaBridge 126:abea610beb85 406 #define FMC_NORSRAM_DEVICE FMC_Bank1
AnnaBridge 126:abea610beb85 407 #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
AnnaBridge 126:abea610beb85 408 #define FMC_NAND_DEVICE FMC_Bank3
AnnaBridge 126:abea610beb85 409 #define FMC_SDRAM_DEVICE FMC_Bank5_6
AnnaBridge 126:abea610beb85 410
AnnaBridge 126:abea610beb85 411 /**
AnnaBridge 126:abea610beb85 412 * @brief FMC NORSRAM Configuration Structure definition
AnnaBridge 126:abea610beb85 413 */
AnnaBridge 126:abea610beb85 414 typedef struct
AnnaBridge 126:abea610beb85 415 {
AnnaBridge 126:abea610beb85 416 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
AnnaBridge 126:abea610beb85 417 This parameter can be a value of @ref FMC_NORSRAM_Bank */
AnnaBridge 126:abea610beb85 418
AnnaBridge 126:abea610beb85 419 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
AnnaBridge 126:abea610beb85 420 multiplexed on the data bus or not.
AnnaBridge 126:abea610beb85 421 This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
AnnaBridge 126:abea610beb85 422
AnnaBridge 126:abea610beb85 423 uint32_t MemoryType; /*!< Specifies the type of external memory attached to
AnnaBridge 126:abea610beb85 424 the corresponding memory device.
AnnaBridge 126:abea610beb85 425 This parameter can be a value of @ref FMC_Memory_Type */
AnnaBridge 126:abea610beb85 426
AnnaBridge 126:abea610beb85 427 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
AnnaBridge 126:abea610beb85 428 This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
AnnaBridge 126:abea610beb85 429
AnnaBridge 126:abea610beb85 430 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
AnnaBridge 126:abea610beb85 431 valid only with synchronous burst Flash memories.
AnnaBridge 126:abea610beb85 432 This parameter can be a value of @ref FMC_Burst_Access_Mode */
AnnaBridge 126:abea610beb85 433
AnnaBridge 126:abea610beb85 434 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
AnnaBridge 126:abea610beb85 435 the Flash memory in burst mode.
AnnaBridge 126:abea610beb85 436 This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
AnnaBridge 126:abea610beb85 437
AnnaBridge 126:abea610beb85 438 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
AnnaBridge 126:abea610beb85 439 clock cycle before the wait state or during the wait state,
AnnaBridge 126:abea610beb85 440 valid only when accessing memories in burst mode.
AnnaBridge 126:abea610beb85 441 This parameter can be a value of @ref FMC_Wait_Timing */
AnnaBridge 126:abea610beb85 442
AnnaBridge 126:abea610beb85 443 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
AnnaBridge 126:abea610beb85 444 This parameter can be a value of @ref FMC_Write_Operation */
AnnaBridge 126:abea610beb85 445
AnnaBridge 126:abea610beb85 446 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
AnnaBridge 126:abea610beb85 447 signal, valid for Flash memory access in burst mode.
AnnaBridge 126:abea610beb85 448 This parameter can be a value of @ref FMC_Wait_Signal */
AnnaBridge 126:abea610beb85 449
AnnaBridge 126:abea610beb85 450 uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
AnnaBridge 126:abea610beb85 451 This parameter can be a value of @ref FMC_Extended_Mode */
AnnaBridge 126:abea610beb85 452
AnnaBridge 126:abea610beb85 453 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
AnnaBridge 126:abea610beb85 454 valid only with asynchronous Flash memories.
AnnaBridge 126:abea610beb85 455 This parameter can be a value of @ref FMC_AsynchronousWait */
AnnaBridge 126:abea610beb85 456
AnnaBridge 126:abea610beb85 457 uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
AnnaBridge 126:abea610beb85 458 This parameter can be a value of @ref FMC_Write_Burst */
AnnaBridge 126:abea610beb85 459
AnnaBridge 126:abea610beb85 460 uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
AnnaBridge 126:abea610beb85 461 This parameter is only enabled through the FMC_BCR1 register, and don't care
AnnaBridge 126:abea610beb85 462 through FMC_BCR2..4 registers.
AnnaBridge 126:abea610beb85 463 This parameter can be a value of @ref FMC_Continous_Clock */
AnnaBridge 126:abea610beb85 464
AnnaBridge 126:abea610beb85 465 uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
AnnaBridge 126:abea610beb85 466 This parameter is only enabled through the FMC_BCR1 register, and don't care
AnnaBridge 126:abea610beb85 467 through FMC_BCR2..4 registers.
AnnaBridge 126:abea610beb85 468 This parameter can be a value of @ref FMC_Write_FIFO */
AnnaBridge 126:abea610beb85 469
AnnaBridge 126:abea610beb85 470 uint32_t PageSize; /*!< Specifies the memory page size.
AnnaBridge 126:abea610beb85 471 This parameter can be a value of @ref FMC_Page_Size */
AnnaBridge 126:abea610beb85 472
AnnaBridge 126:abea610beb85 473 }FMC_NORSRAM_InitTypeDef;
AnnaBridge 126:abea610beb85 474
AnnaBridge 126:abea610beb85 475 /**
AnnaBridge 126:abea610beb85 476 * @brief FMC NORSRAM Timing parameters structure definition
AnnaBridge 126:abea610beb85 477 */
AnnaBridge 126:abea610beb85 478 typedef struct
AnnaBridge 126:abea610beb85 479 {
AnnaBridge 126:abea610beb85 480 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
AnnaBridge 126:abea610beb85 481 the duration of the address setup time.
AnnaBridge 126:abea610beb85 482 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
AnnaBridge 126:abea610beb85 483 @note This parameter is not used with synchronous NOR Flash memories. */
AnnaBridge 126:abea610beb85 484
AnnaBridge 126:abea610beb85 485 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
AnnaBridge 126:abea610beb85 486 the duration of the address hold time.
AnnaBridge 126:abea610beb85 487 This parameter can be a value between Min_Data = 1 and Max_Data = 15.
AnnaBridge 126:abea610beb85 488 @note This parameter is not used with synchronous NOR Flash memories. */
AnnaBridge 126:abea610beb85 489
AnnaBridge 126:abea610beb85 490 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
AnnaBridge 126:abea610beb85 491 the duration of the data setup time.
AnnaBridge 126:abea610beb85 492 This parameter can be a value between Min_Data = 1 and Max_Data = 255.
AnnaBridge 126:abea610beb85 493 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
AnnaBridge 126:abea610beb85 494 NOR Flash memories. */
AnnaBridge 126:abea610beb85 495
AnnaBridge 126:abea610beb85 496 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
AnnaBridge 126:abea610beb85 497 the duration of the bus turnaround.
AnnaBridge 126:abea610beb85 498 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
AnnaBridge 126:abea610beb85 499 @note This parameter is only used for multiplexed NOR Flash memories. */
AnnaBridge 126:abea610beb85 500
AnnaBridge 126:abea610beb85 501 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
AnnaBridge 126:abea610beb85 502 HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
AnnaBridge 126:abea610beb85 503 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
AnnaBridge 126:abea610beb85 504 accesses. */
AnnaBridge 126:abea610beb85 505
AnnaBridge 126:abea610beb85 506 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
AnnaBridge 126:abea610beb85 507 to the memory before getting the first data.
AnnaBridge 126:abea610beb85 508 The parameter value depends on the memory type as shown below:
AnnaBridge 126:abea610beb85 509 - It must be set to 0 in case of a CRAM
AnnaBridge 126:abea610beb85 510 - It is don't care in asynchronous NOR, SRAM or ROM accesses
AnnaBridge 126:abea610beb85 511 - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
AnnaBridge 126:abea610beb85 512 with synchronous burst mode enable */
AnnaBridge 126:abea610beb85 513
AnnaBridge 126:abea610beb85 514 uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
AnnaBridge 126:abea610beb85 515 This parameter can be a value of @ref FMC_Access_Mode */
AnnaBridge 126:abea610beb85 516 }FMC_NORSRAM_TimingTypeDef;
AnnaBridge 126:abea610beb85 517
AnnaBridge 126:abea610beb85 518 /**
AnnaBridge 126:abea610beb85 519 * @brief FMC NAND Configuration Structure definition
AnnaBridge 126:abea610beb85 520 */
AnnaBridge 126:abea610beb85 521 typedef struct
AnnaBridge 126:abea610beb85 522 {
AnnaBridge 126:abea610beb85 523 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
AnnaBridge 126:abea610beb85 524 This parameter can be a value of @ref FMC_NAND_Bank */
AnnaBridge 126:abea610beb85 525
AnnaBridge 126:abea610beb85 526 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
AnnaBridge 126:abea610beb85 527 This parameter can be any value of @ref FMC_Wait_feature */
AnnaBridge 126:abea610beb85 528
AnnaBridge 126:abea610beb85 529 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
AnnaBridge 126:abea610beb85 530 This parameter can be any value of @ref FMC_NAND_Data_Width */
AnnaBridge 126:abea610beb85 531
AnnaBridge 126:abea610beb85 532 uint32_t EccComputation; /*!< Enables or disables the ECC computation.
AnnaBridge 126:abea610beb85 533 This parameter can be any value of @ref FMC_ECC */
AnnaBridge 126:abea610beb85 534
AnnaBridge 126:abea610beb85 535 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
AnnaBridge 126:abea610beb85 536 This parameter can be any value of @ref FMC_ECC_Page_Size */
AnnaBridge 126:abea610beb85 537
AnnaBridge 126:abea610beb85 538 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
AnnaBridge 126:abea610beb85 539 delay between CLE low and RE low.
AnnaBridge 126:abea610beb85 540 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
AnnaBridge 126:abea610beb85 541
AnnaBridge 126:abea610beb85 542 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
AnnaBridge 126:abea610beb85 543 delay between ALE low and RE low.
AnnaBridge 126:abea610beb85 544 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
AnnaBridge 126:abea610beb85 545 }FMC_NAND_InitTypeDef;
AnnaBridge 126:abea610beb85 546
AnnaBridge 126:abea610beb85 547 /**
AnnaBridge 126:abea610beb85 548 * @brief FMC NAND Timing parameters structure definition
AnnaBridge 126:abea610beb85 549 */
AnnaBridge 126:abea610beb85 550 typedef struct
AnnaBridge 126:abea610beb85 551 {
AnnaBridge 126:abea610beb85 552 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
AnnaBridge 126:abea610beb85 553 the command assertion for NAND-Flash read or write access
AnnaBridge 126:abea610beb85 554 to common/Attribute or I/O memory space (depending on
AnnaBridge 126:abea610beb85 555 the memory space timing to be configured).
AnnaBridge 126:abea610beb85 556 This parameter can be a value between Min_Data = 0 and Max_Data = 254 */
AnnaBridge 126:abea610beb85 557
AnnaBridge 126:abea610beb85 558 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
AnnaBridge 126:abea610beb85 559 command for NAND-Flash read or write access to
AnnaBridge 126:abea610beb85 560 common/Attribute or I/O memory space (depending on the
AnnaBridge 126:abea610beb85 561 memory space timing to be configured).
AnnaBridge 126:abea610beb85 562 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
AnnaBridge 126:abea610beb85 563
AnnaBridge 126:abea610beb85 564 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
AnnaBridge 126:abea610beb85 565 (and data for write access) after the command de-assertion
AnnaBridge 126:abea610beb85 566 for NAND-Flash read or write access to common/Attribute
AnnaBridge 126:abea610beb85 567 or I/O memory space (depending on the memory space timing
AnnaBridge 126:abea610beb85 568 to be configured).
AnnaBridge 126:abea610beb85 569 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
AnnaBridge 126:abea610beb85 570
AnnaBridge 126:abea610beb85 571 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
AnnaBridge 126:abea610beb85 572 data bus is kept in HiZ after the start of a NAND-Flash
AnnaBridge 126:abea610beb85 573 write access to common/Attribute or I/O memory space (depending
AnnaBridge 126:abea610beb85 574 on the memory space timing to be configured).
AnnaBridge 126:abea610beb85 575 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
AnnaBridge 126:abea610beb85 576 }FMC_NAND_PCC_TimingTypeDef;
AnnaBridge 126:abea610beb85 577
AnnaBridge 126:abea610beb85 578 /**
AnnaBridge 126:abea610beb85 579 * @brief FMC SDRAM Configuration Structure definition
AnnaBridge 126:abea610beb85 580 */
AnnaBridge 126:abea610beb85 581 typedef struct
AnnaBridge 126:abea610beb85 582 {
AnnaBridge 126:abea610beb85 583 uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.
AnnaBridge 126:abea610beb85 584 This parameter can be a value of @ref FMC_SDRAM_Bank */
AnnaBridge 126:abea610beb85 585
AnnaBridge 126:abea610beb85 586 uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.
AnnaBridge 126:abea610beb85 587 This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
AnnaBridge 126:abea610beb85 588
AnnaBridge 126:abea610beb85 589 uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.
AnnaBridge 126:abea610beb85 590 This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */
AnnaBridge 126:abea610beb85 591
AnnaBridge 126:abea610beb85 592 uint32_t MemoryDataWidth; /*!< Defines the memory device width.
AnnaBridge 126:abea610beb85 593 This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */
AnnaBridge 126:abea610beb85 594
AnnaBridge 126:abea610beb85 595 uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.
AnnaBridge 126:abea610beb85 596 This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */
AnnaBridge 126:abea610beb85 597
AnnaBridge 126:abea610beb85 598 uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
AnnaBridge 126:abea610beb85 599 This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */
AnnaBridge 126:abea610beb85 600
AnnaBridge 126:abea610beb85 601 uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.
AnnaBridge 126:abea610beb85 602 This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */
AnnaBridge 126:abea610beb85 603
AnnaBridge 126:abea610beb85 604 uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
AnnaBridge 126:abea610beb85 605 to disable the clock before changing frequency.
AnnaBridge 126:abea610beb85 606 This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */
AnnaBridge 126:abea610beb85 607
AnnaBridge 126:abea610beb85 608 uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read
AnnaBridge 126:abea610beb85 609 commands during the CAS latency and stores data in the Read FIFO.
AnnaBridge 126:abea610beb85 610 This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */
AnnaBridge 126:abea610beb85 611
AnnaBridge 126:abea610beb85 612 uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
AnnaBridge 126:abea610beb85 613 This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
AnnaBridge 126:abea610beb85 614 }FMC_SDRAM_InitTypeDef;
AnnaBridge 126:abea610beb85 615
AnnaBridge 126:abea610beb85 616 /**
AnnaBridge 126:abea610beb85 617 * @brief FMC SDRAM Timing parameters structure definition
AnnaBridge 126:abea610beb85 618 */
AnnaBridge 126:abea610beb85 619 typedef struct
AnnaBridge 126:abea610beb85 620 {
AnnaBridge 126:abea610beb85 621 uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
AnnaBridge 126:abea610beb85 622 an active or Refresh command in number of memory clock cycles.
AnnaBridge 126:abea610beb85 623 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
AnnaBridge 126:abea610beb85 624
AnnaBridge 126:abea610beb85 625 uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
AnnaBridge 126:abea610beb85 626 issuing the Activate command in number of memory clock cycles.
AnnaBridge 126:abea610beb85 627 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
AnnaBridge 126:abea610beb85 628
AnnaBridge 126:abea610beb85 629 uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
AnnaBridge 126:abea610beb85 630 cycles.
AnnaBridge 126:abea610beb85 631 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
AnnaBridge 126:abea610beb85 632
AnnaBridge 126:abea610beb85 633 uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
AnnaBridge 126:abea610beb85 634 and the delay between two consecutive Refresh commands in number of
AnnaBridge 126:abea610beb85 635 memory clock cycles.
AnnaBridge 126:abea610beb85 636 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
AnnaBridge 126:abea610beb85 637
AnnaBridge 126:abea610beb85 638 uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
AnnaBridge 126:abea610beb85 639 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
AnnaBridge 126:abea610beb85 640
AnnaBridge 126:abea610beb85 641 uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command
AnnaBridge 126:abea610beb85 642 in number of memory clock cycles.
AnnaBridge 126:abea610beb85 643 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
AnnaBridge 126:abea610beb85 644
AnnaBridge 126:abea610beb85 645 uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
AnnaBridge 126:abea610beb85 646 command in number of memory clock cycles.
AnnaBridge 126:abea610beb85 647 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
AnnaBridge 126:abea610beb85 648 }FMC_SDRAM_TimingTypeDef;
AnnaBridge 126:abea610beb85 649
AnnaBridge 126:abea610beb85 650 /**
AnnaBridge 126:abea610beb85 651 * @brief SDRAM command parameters structure definition
AnnaBridge 126:abea610beb85 652 */
AnnaBridge 126:abea610beb85 653 typedef struct
AnnaBridge 126:abea610beb85 654 {
AnnaBridge 126:abea610beb85 655 uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.
AnnaBridge 126:abea610beb85 656 This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
AnnaBridge 126:abea610beb85 657
AnnaBridge 126:abea610beb85 658 uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.
AnnaBridge 126:abea610beb85 659 This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
AnnaBridge 126:abea610beb85 660
AnnaBridge 126:abea610beb85 661 uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
AnnaBridge 126:abea610beb85 662 in auto refresh mode.
AnnaBridge 126:abea610beb85 663 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
AnnaBridge 126:abea610beb85 664 uint32_t ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */
AnnaBridge 126:abea610beb85 665 }FMC_SDRAM_CommandTypeDef;
AnnaBridge 126:abea610beb85 666 /**
AnnaBridge 126:abea610beb85 667 * @}
AnnaBridge 126:abea610beb85 668 */
AnnaBridge 126:abea610beb85 669
AnnaBridge 126:abea610beb85 670 /* Exported constants --------------------------------------------------------*/
AnnaBridge 126:abea610beb85 671 /** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants
AnnaBridge 126:abea610beb85 672 * @{
AnnaBridge 126:abea610beb85 673 */
AnnaBridge 126:abea610beb85 674
AnnaBridge 126:abea610beb85 675 /** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller
AnnaBridge 126:abea610beb85 676 * @{
AnnaBridge 126:abea610beb85 677 */
AnnaBridge 126:abea610beb85 678
AnnaBridge 126:abea610beb85 679 /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
AnnaBridge 126:abea610beb85 680 * @{
AnnaBridge 126:abea610beb85 681 */
AnnaBridge 126:abea610beb85 682 #define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 683 #define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002U)
AnnaBridge 126:abea610beb85 684 #define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004U)
AnnaBridge 126:abea610beb85 685 #define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006U)
AnnaBridge 126:abea610beb85 686 /**
AnnaBridge 126:abea610beb85 687 * @}
AnnaBridge 126:abea610beb85 688 */
AnnaBridge 126:abea610beb85 689
AnnaBridge 126:abea610beb85 690 /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
AnnaBridge 126:abea610beb85 691 * @{
AnnaBridge 126:abea610beb85 692 */
AnnaBridge 126:abea610beb85 693 #define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 694 #define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002U)
AnnaBridge 126:abea610beb85 695 /**
AnnaBridge 126:abea610beb85 696 * @}
AnnaBridge 126:abea610beb85 697 */
AnnaBridge 126:abea610beb85 698
AnnaBridge 126:abea610beb85 699 /** @defgroup FMC_Memory_Type FMC Memory Type
AnnaBridge 126:abea610beb85 700 * @{
AnnaBridge 126:abea610beb85 701 */
AnnaBridge 126:abea610beb85 702 #define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 703 #define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004U)
AnnaBridge 126:abea610beb85 704 #define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008U)
AnnaBridge 126:abea610beb85 705 /**
AnnaBridge 126:abea610beb85 706 * @}
AnnaBridge 126:abea610beb85 707 */
AnnaBridge 126:abea610beb85 708
AnnaBridge 126:abea610beb85 709 /** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
AnnaBridge 126:abea610beb85 710 * @{
AnnaBridge 126:abea610beb85 711 */
AnnaBridge 126:abea610beb85 712 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 713 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
AnnaBridge 126:abea610beb85 714 #define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U)
AnnaBridge 126:abea610beb85 715 /**
AnnaBridge 126:abea610beb85 716 * @}
AnnaBridge 126:abea610beb85 717 */
AnnaBridge 126:abea610beb85 718
AnnaBridge 126:abea610beb85 719 /** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
AnnaBridge 126:abea610beb85 720 * @{
AnnaBridge 126:abea610beb85 721 */
AnnaBridge 126:abea610beb85 722 #define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040U)
AnnaBridge 126:abea610beb85 723 #define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 724 /**
AnnaBridge 126:abea610beb85 725 * @}
AnnaBridge 126:abea610beb85 726 */
AnnaBridge 126:abea610beb85 727
AnnaBridge 126:abea610beb85 728 /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
AnnaBridge 126:abea610beb85 729 * @{
AnnaBridge 126:abea610beb85 730 */
AnnaBridge 126:abea610beb85 731 #define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 732 #define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100U)
AnnaBridge 126:abea610beb85 733 /**
AnnaBridge 126:abea610beb85 734 * @}
AnnaBridge 126:abea610beb85 735 */
AnnaBridge 126:abea610beb85 736
AnnaBridge 126:abea610beb85 737 /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
AnnaBridge 126:abea610beb85 738 * @{
AnnaBridge 126:abea610beb85 739 */
AnnaBridge 126:abea610beb85 740 #define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 741 #define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200U)
AnnaBridge 126:abea610beb85 742 /**
AnnaBridge 126:abea610beb85 743 * @}
AnnaBridge 126:abea610beb85 744 */
AnnaBridge 126:abea610beb85 745
AnnaBridge 126:abea610beb85 746 /** @defgroup FMC_Wait_Timing FMC Wait Timing
AnnaBridge 126:abea610beb85 747 * @{
AnnaBridge 126:abea610beb85 748 */
AnnaBridge 126:abea610beb85 749 #define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 750 #define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800U)
AnnaBridge 126:abea610beb85 751 /**
AnnaBridge 126:abea610beb85 752 * @}
AnnaBridge 126:abea610beb85 753 */
AnnaBridge 126:abea610beb85 754
AnnaBridge 126:abea610beb85 755 /** @defgroup FMC_Write_Operation FMC Write Operation
AnnaBridge 126:abea610beb85 756 * @{
AnnaBridge 126:abea610beb85 757 */
AnnaBridge 126:abea610beb85 758 #define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 759 #define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000U)
AnnaBridge 126:abea610beb85 760 /**
AnnaBridge 126:abea610beb85 761 * @}
AnnaBridge 126:abea610beb85 762 */
AnnaBridge 126:abea610beb85 763
AnnaBridge 126:abea610beb85 764 /** @defgroup FMC_Wait_Signal FMC Wait Signal
AnnaBridge 126:abea610beb85 765 * @{
AnnaBridge 126:abea610beb85 766 */
AnnaBridge 126:abea610beb85 767 #define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 768 #define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000U)
AnnaBridge 126:abea610beb85 769 /**
AnnaBridge 126:abea610beb85 770 * @}
AnnaBridge 126:abea610beb85 771 */
AnnaBridge 126:abea610beb85 772
AnnaBridge 126:abea610beb85 773 /** @defgroup FMC_Extended_Mode FMC Extended Mode
AnnaBridge 126:abea610beb85 774 * @{
AnnaBridge 126:abea610beb85 775 */
AnnaBridge 126:abea610beb85 776 #define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 777 #define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000U)
AnnaBridge 126:abea610beb85 778 /**
AnnaBridge 126:abea610beb85 779 * @}
AnnaBridge 126:abea610beb85 780 */
AnnaBridge 126:abea610beb85 781
AnnaBridge 126:abea610beb85 782 /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
AnnaBridge 126:abea610beb85 783 * @{
AnnaBridge 126:abea610beb85 784 */
AnnaBridge 126:abea610beb85 785 #define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 786 #define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000U)
AnnaBridge 126:abea610beb85 787 /**
AnnaBridge 126:abea610beb85 788 * @}
AnnaBridge 126:abea610beb85 789 */
AnnaBridge 126:abea610beb85 790
AnnaBridge 126:abea610beb85 791 /** @defgroup FMC_Page_Size FMC Page Size
AnnaBridge 126:abea610beb85 792 * @{
AnnaBridge 126:abea610beb85 793 */
AnnaBridge 126:abea610beb85 794 #define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 795 #define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCR1_CPSIZE_0)
AnnaBridge 126:abea610beb85 796 #define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCR1_CPSIZE_1)
AnnaBridge 126:abea610beb85 797 #define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCR1_CPSIZE_0 | FMC_BCR1_CPSIZE_1))
AnnaBridge 126:abea610beb85 798 #define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCR1_CPSIZE_2)
AnnaBridge 126:abea610beb85 799 /**
AnnaBridge 126:abea610beb85 800 * @}
AnnaBridge 126:abea610beb85 801 */
AnnaBridge 126:abea610beb85 802
AnnaBridge 126:abea610beb85 803 /** @defgroup FMC_Write_Burst FMC Write Burst
AnnaBridge 126:abea610beb85 804 * @{
AnnaBridge 126:abea610beb85 805 */
AnnaBridge 126:abea610beb85 806 #define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 807 #define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000U)
AnnaBridge 126:abea610beb85 808 /**
AnnaBridge 126:abea610beb85 809 * @}
AnnaBridge 126:abea610beb85 810 */
AnnaBridge 126:abea610beb85 811
AnnaBridge 126:abea610beb85 812 /** @defgroup FMC_Continous_Clock FMC Continuous Clock
AnnaBridge 126:abea610beb85 813 * @{
AnnaBridge 126:abea610beb85 814 */
AnnaBridge 126:abea610beb85 815 #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 816 #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000U)
AnnaBridge 126:abea610beb85 817 /**
AnnaBridge 126:abea610beb85 818 * @}
AnnaBridge 126:abea610beb85 819 */
AnnaBridge 126:abea610beb85 820
AnnaBridge 126:abea610beb85 821 /** @defgroup FMC_Write_FIFO FMC Write FIFO
AnnaBridge 126:abea610beb85 822 * @{
AnnaBridge 126:abea610beb85 823 */
AnnaBridge 126:abea610beb85 824 #define FMC_WRITE_FIFO_DISABLE ((uint32_t)FMC_BCR1_WFDIS)
AnnaBridge 126:abea610beb85 825 #define FMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 826 /**
AnnaBridge 126:abea610beb85 827 * @}
AnnaBridge 126:abea610beb85 828 */
AnnaBridge 126:abea610beb85 829
AnnaBridge 126:abea610beb85 830 /** @defgroup FMC_Access_Mode FMC Access Mode
AnnaBridge 126:abea610beb85 831 * @{
AnnaBridge 126:abea610beb85 832 */
AnnaBridge 126:abea610beb85 833 #define FMC_ACCESS_MODE_A ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 834 #define FMC_ACCESS_MODE_B ((uint32_t)0x10000000U)
AnnaBridge 126:abea610beb85 835 #define FMC_ACCESS_MODE_C ((uint32_t)0x20000000U)
AnnaBridge 126:abea610beb85 836 #define FMC_ACCESS_MODE_D ((uint32_t)0x30000000)
AnnaBridge 126:abea610beb85 837 /**
AnnaBridge 126:abea610beb85 838 * @}
AnnaBridge 126:abea610beb85 839 */
AnnaBridge 126:abea610beb85 840
AnnaBridge 126:abea610beb85 841 /**
AnnaBridge 126:abea610beb85 842 * @}
AnnaBridge 126:abea610beb85 843 */
AnnaBridge 126:abea610beb85 844
AnnaBridge 126:abea610beb85 845 /** @defgroup FMC_LL_NAND_Controller FMC NAND Controller
AnnaBridge 126:abea610beb85 846 * @{
AnnaBridge 126:abea610beb85 847 */
AnnaBridge 126:abea610beb85 848 /** @defgroup FMC_NAND_Bank FMC NAND Bank
AnnaBridge 126:abea610beb85 849 * @{
AnnaBridge 126:abea610beb85 850 */
AnnaBridge 126:abea610beb85 851 #define FMC_NAND_BANK3 ((uint32_t)0x00000100U)
AnnaBridge 126:abea610beb85 852 /**
AnnaBridge 126:abea610beb85 853 * @}
AnnaBridge 126:abea610beb85 854 */
AnnaBridge 126:abea610beb85 855
AnnaBridge 126:abea610beb85 856 /** @defgroup FMC_Wait_feature FMC Wait feature
AnnaBridge 126:abea610beb85 857 * @{
AnnaBridge 126:abea610beb85 858 */
AnnaBridge 126:abea610beb85 859 #define FMC_NAND_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 860 #define FMC_NAND_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002U)
AnnaBridge 126:abea610beb85 861 /**
AnnaBridge 126:abea610beb85 862 * @}
AnnaBridge 126:abea610beb85 863 */
AnnaBridge 126:abea610beb85 864
AnnaBridge 126:abea610beb85 865 /** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
AnnaBridge 126:abea610beb85 866 * @{
AnnaBridge 126:abea610beb85 867 */
AnnaBridge 126:abea610beb85 868 #define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008U)
AnnaBridge 126:abea610beb85 869 /**
AnnaBridge 126:abea610beb85 870 * @}
AnnaBridge 126:abea610beb85 871 */
AnnaBridge 126:abea610beb85 872
AnnaBridge 126:abea610beb85 873 /** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
AnnaBridge 126:abea610beb85 874 * @{
AnnaBridge 126:abea610beb85 875 */
AnnaBridge 126:abea610beb85 876 #define FMC_NAND_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 877 #define FMC_NAND_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
AnnaBridge 126:abea610beb85 878 /**
AnnaBridge 126:abea610beb85 879 * @}
AnnaBridge 126:abea610beb85 880 */
AnnaBridge 126:abea610beb85 881
AnnaBridge 126:abea610beb85 882 /** @defgroup FMC_ECC FMC ECC
AnnaBridge 126:abea610beb85 883 * @{
AnnaBridge 126:abea610beb85 884 */
AnnaBridge 126:abea610beb85 885 #define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 886 #define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040U)
AnnaBridge 126:abea610beb85 887 /**
AnnaBridge 126:abea610beb85 888 * @}
AnnaBridge 126:abea610beb85 889 */
AnnaBridge 126:abea610beb85 890
AnnaBridge 126:abea610beb85 891 /** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
AnnaBridge 126:abea610beb85 892 * @{
AnnaBridge 126:abea610beb85 893 */
AnnaBridge 126:abea610beb85 894 #define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 895 #define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000U)
AnnaBridge 126:abea610beb85 896 #define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000U)
AnnaBridge 126:abea610beb85 897 #define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000U)
AnnaBridge 126:abea610beb85 898 #define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000U)
AnnaBridge 126:abea610beb85 899 #define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000U)
AnnaBridge 126:abea610beb85 900 /**
AnnaBridge 126:abea610beb85 901 * @}
AnnaBridge 126:abea610beb85 902 */
AnnaBridge 126:abea610beb85 903
AnnaBridge 126:abea610beb85 904 /**
AnnaBridge 126:abea610beb85 905 * @}
AnnaBridge 126:abea610beb85 906 */
AnnaBridge 126:abea610beb85 907
AnnaBridge 126:abea610beb85 908 /** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller
AnnaBridge 126:abea610beb85 909 * @{
AnnaBridge 126:abea610beb85 910 */
AnnaBridge 126:abea610beb85 911 /** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank
AnnaBridge 126:abea610beb85 912 * @{
AnnaBridge 126:abea610beb85 913 */
AnnaBridge 126:abea610beb85 914 #define FMC_SDRAM_BANK1 ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 915 #define FMC_SDRAM_BANK2 ((uint32_t)0x00000001U)
AnnaBridge 126:abea610beb85 916 /**
AnnaBridge 126:abea610beb85 917 * @}
AnnaBridge 126:abea610beb85 918 */
AnnaBridge 126:abea610beb85 919
AnnaBridge 126:abea610beb85 920 /** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number
AnnaBridge 126:abea610beb85 921 * @{
AnnaBridge 126:abea610beb85 922 */
AnnaBridge 126:abea610beb85 923 #define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 924 #define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001U)
AnnaBridge 126:abea610beb85 925 #define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002U)
AnnaBridge 126:abea610beb85 926 #define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003U)
AnnaBridge 126:abea610beb85 927 /**
AnnaBridge 126:abea610beb85 928 * @}
AnnaBridge 126:abea610beb85 929 */
AnnaBridge 126:abea610beb85 930
AnnaBridge 126:abea610beb85 931 /** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number
AnnaBridge 126:abea610beb85 932 * @{
AnnaBridge 126:abea610beb85 933 */
AnnaBridge 126:abea610beb85 934 #define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 935 #define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004U)
AnnaBridge 126:abea610beb85 936 #define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008U)
AnnaBridge 126:abea610beb85 937 /**
AnnaBridge 126:abea610beb85 938 * @}
AnnaBridge 126:abea610beb85 939 */
AnnaBridge 126:abea610beb85 940
AnnaBridge 126:abea610beb85 941 /** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width
AnnaBridge 126:abea610beb85 942 * @{
AnnaBridge 126:abea610beb85 943 */
AnnaBridge 126:abea610beb85 944 #define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 945 #define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
AnnaBridge 126:abea610beb85 946 #define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U)
AnnaBridge 126:abea610beb85 947 /**
AnnaBridge 126:abea610beb85 948 * @}
AnnaBridge 126:abea610beb85 949 */
AnnaBridge 126:abea610beb85 950
AnnaBridge 126:abea610beb85 951 /** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number
AnnaBridge 126:abea610beb85 952 * @{
AnnaBridge 126:abea610beb85 953 */
AnnaBridge 126:abea610beb85 954 #define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 955 #define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040U)
AnnaBridge 126:abea610beb85 956 /**
AnnaBridge 126:abea610beb85 957 * @}
AnnaBridge 126:abea610beb85 958 */
AnnaBridge 126:abea610beb85 959
AnnaBridge 126:abea610beb85 960 /** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency
AnnaBridge 126:abea610beb85 961 * @{
AnnaBridge 126:abea610beb85 962 */
AnnaBridge 126:abea610beb85 963 #define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080U)
AnnaBridge 126:abea610beb85 964 #define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100U)
AnnaBridge 126:abea610beb85 965 #define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180)
AnnaBridge 126:abea610beb85 966 /**
AnnaBridge 126:abea610beb85 967 * @}
AnnaBridge 126:abea610beb85 968 */
AnnaBridge 126:abea610beb85 969
AnnaBridge 126:abea610beb85 970 /** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection
AnnaBridge 126:abea610beb85 971 * @{
AnnaBridge 126:abea610beb85 972 */
AnnaBridge 126:abea610beb85 973 #define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 974 #define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200U)
AnnaBridge 126:abea610beb85 975 /**
AnnaBridge 126:abea610beb85 976 * @}
AnnaBridge 126:abea610beb85 977 */
AnnaBridge 126:abea610beb85 978
AnnaBridge 126:abea610beb85 979 /** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period
AnnaBridge 126:abea610beb85 980 * @{
AnnaBridge 126:abea610beb85 981 */
AnnaBridge 126:abea610beb85 982 #define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 983 #define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800U)
AnnaBridge 126:abea610beb85 984 #define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00)
AnnaBridge 126:abea610beb85 985 /**
AnnaBridge 126:abea610beb85 986 * @}
AnnaBridge 126:abea610beb85 987 */
AnnaBridge 126:abea610beb85 988
AnnaBridge 126:abea610beb85 989 /** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst
AnnaBridge 126:abea610beb85 990 * @{
AnnaBridge 126:abea610beb85 991 */
AnnaBridge 126:abea610beb85 992 #define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 993 #define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000U)
AnnaBridge 126:abea610beb85 994 /**
AnnaBridge 126:abea610beb85 995 * @}
AnnaBridge 126:abea610beb85 996 */
AnnaBridge 126:abea610beb85 997
AnnaBridge 126:abea610beb85 998 /** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay
AnnaBridge 126:abea610beb85 999 * @{
AnnaBridge 126:abea610beb85 1000 */
AnnaBridge 126:abea610beb85 1001 #define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 1002 #define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000U)
AnnaBridge 126:abea610beb85 1003 #define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000U)
AnnaBridge 126:abea610beb85 1004 /**
AnnaBridge 126:abea610beb85 1005 * @}
AnnaBridge 126:abea610beb85 1006 */
AnnaBridge 126:abea610beb85 1007
AnnaBridge 126:abea610beb85 1008 /** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode
AnnaBridge 126:abea610beb85 1009 * @{
AnnaBridge 126:abea610beb85 1010 */
AnnaBridge 126:abea610beb85 1011 #define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 1012 #define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001U)
AnnaBridge 126:abea610beb85 1013 #define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002U)
AnnaBridge 126:abea610beb85 1014 #define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003U)
AnnaBridge 126:abea610beb85 1015 #define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004U)
AnnaBridge 126:abea610beb85 1016 #define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005U)
AnnaBridge 126:abea610beb85 1017 #define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006U)
AnnaBridge 126:abea610beb85 1018 /**
AnnaBridge 126:abea610beb85 1019 * @}
AnnaBridge 126:abea610beb85 1020 */
AnnaBridge 126:abea610beb85 1021
AnnaBridge 126:abea610beb85 1022 /** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target
AnnaBridge 126:abea610beb85 1023 * @{
AnnaBridge 126:abea610beb85 1024 */
AnnaBridge 126:abea610beb85 1025 #define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
AnnaBridge 126:abea610beb85 1026 #define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
AnnaBridge 126:abea610beb85 1027 #define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018U)
AnnaBridge 126:abea610beb85 1028 /**
AnnaBridge 126:abea610beb85 1029 * @}
AnnaBridge 126:abea610beb85 1030 */
AnnaBridge 126:abea610beb85 1031
AnnaBridge 126:abea610beb85 1032 /** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status
AnnaBridge 126:abea610beb85 1033 * @{
AnnaBridge 126:abea610beb85 1034 */
AnnaBridge 126:abea610beb85 1035 #define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 1036 #define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
AnnaBridge 126:abea610beb85 1037 #define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
AnnaBridge 126:abea610beb85 1038 /**
AnnaBridge 126:abea610beb85 1039 * @}
AnnaBridge 126:abea610beb85 1040 */
AnnaBridge 126:abea610beb85 1041
AnnaBridge 126:abea610beb85 1042 /**
AnnaBridge 126:abea610beb85 1043 * @}
AnnaBridge 126:abea610beb85 1044 */
AnnaBridge 126:abea610beb85 1045
AnnaBridge 126:abea610beb85 1046 /** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition
AnnaBridge 126:abea610beb85 1047 * @{
AnnaBridge 126:abea610beb85 1048 */
AnnaBridge 126:abea610beb85 1049 #define FMC_IT_RISING_EDGE ((uint32_t)0x00000008U)
AnnaBridge 126:abea610beb85 1050 #define FMC_IT_LEVEL ((uint32_t)0x00000010U)
AnnaBridge 126:abea610beb85 1051 #define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020U)
AnnaBridge 126:abea610beb85 1052 #define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000U)
AnnaBridge 126:abea610beb85 1053 /**
AnnaBridge 126:abea610beb85 1054 * @}
AnnaBridge 126:abea610beb85 1055 */
AnnaBridge 126:abea610beb85 1056
AnnaBridge 126:abea610beb85 1057 /** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition
AnnaBridge 126:abea610beb85 1058 * @{
AnnaBridge 126:abea610beb85 1059 */
AnnaBridge 126:abea610beb85 1060 #define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001U)
AnnaBridge 126:abea610beb85 1061 #define FMC_FLAG_LEVEL ((uint32_t)0x00000002U)
AnnaBridge 126:abea610beb85 1062 #define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004U)
AnnaBridge 126:abea610beb85 1063 #define FMC_FLAG_FEMPT ((uint32_t)0x00000040U)
AnnaBridge 126:abea610beb85 1064 #define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
AnnaBridge 126:abea610beb85 1065 #define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
AnnaBridge 126:abea610beb85 1066 #define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
AnnaBridge 126:abea610beb85 1067 /**
AnnaBridge 126:abea610beb85 1068 * @}
AnnaBridge 126:abea610beb85 1069 */
AnnaBridge 126:abea610beb85 1070 /**
AnnaBridge 126:abea610beb85 1071 * @}
AnnaBridge 126:abea610beb85 1072 */
AnnaBridge 126:abea610beb85 1073
AnnaBridge 126:abea610beb85 1074 /**
AnnaBridge 126:abea610beb85 1075 * @}
AnnaBridge 126:abea610beb85 1076 */
AnnaBridge 126:abea610beb85 1077
AnnaBridge 126:abea610beb85 1078 /* Private macro -------------------------------------------------------------*/
AnnaBridge 126:abea610beb85 1079 /** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros
AnnaBridge 126:abea610beb85 1080 * @{
AnnaBridge 126:abea610beb85 1081 */
AnnaBridge 126:abea610beb85 1082
AnnaBridge 126:abea610beb85 1083 /** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros
AnnaBridge 126:abea610beb85 1084 * @brief macros to handle NOR device enable/disable and read/write operations
AnnaBridge 126:abea610beb85 1085 * @{
AnnaBridge 126:abea610beb85 1086 */
AnnaBridge 126:abea610beb85 1087
AnnaBridge 126:abea610beb85 1088 /**
AnnaBridge 126:abea610beb85 1089 * @brief Enable the NORSRAM device access.
AnnaBridge 126:abea610beb85 1090 * @param __INSTANCE__: FMC_NORSRAM Instance
AnnaBridge 126:abea610beb85 1091 * @param __BANK__: FMC_NORSRAM Bank
AnnaBridge 126:abea610beb85 1092 * @retval None
AnnaBridge 126:abea610beb85 1093 */
AnnaBridge 126:abea610beb85 1094 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCR1_MBKEN)
AnnaBridge 126:abea610beb85 1095
AnnaBridge 126:abea610beb85 1096 /**
AnnaBridge 126:abea610beb85 1097 * @brief Disable the NORSRAM device access.
AnnaBridge 126:abea610beb85 1098 * @param __INSTANCE__: FMC_NORSRAM Instance
AnnaBridge 126:abea610beb85 1099 * @param __BANK__: FMC_NORSRAM Bank
AnnaBridge 126:abea610beb85 1100 * @retval None
AnnaBridge 126:abea610beb85 1101 */
AnnaBridge 126:abea610beb85 1102 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
AnnaBridge 126:abea610beb85 1103
AnnaBridge 126:abea610beb85 1104 /**
AnnaBridge 126:abea610beb85 1105 * @}
AnnaBridge 126:abea610beb85 1106 */
AnnaBridge 126:abea610beb85 1107
AnnaBridge 126:abea610beb85 1108 /** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
AnnaBridge 126:abea610beb85 1109 * @brief macros to handle NAND device enable/disable
AnnaBridge 126:abea610beb85 1110 * @{
AnnaBridge 126:abea610beb85 1111 */
AnnaBridge 126:abea610beb85 1112
AnnaBridge 126:abea610beb85 1113 /**
AnnaBridge 126:abea610beb85 1114 * @brief Enable the NAND device access.
AnnaBridge 126:abea610beb85 1115 * @param __INSTANCE__: FMC_NAND Instance
AnnaBridge 126:abea610beb85 1116 * @retval None
AnnaBridge 126:abea610beb85 1117 */
AnnaBridge 126:abea610beb85 1118 #define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN)
AnnaBridge 126:abea610beb85 1119
AnnaBridge 126:abea610beb85 1120 /**
AnnaBridge 126:abea610beb85 1121 * @brief Disable the NAND device access.
AnnaBridge 126:abea610beb85 1122 * @param __INSTANCE__: FMC_NAND Instance
AnnaBridge 126:abea610beb85 1123 * @retval None
AnnaBridge 126:abea610beb85 1124 */
AnnaBridge 126:abea610beb85 1125 #define __FMC_NAND_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN)
AnnaBridge 126:abea610beb85 1126
AnnaBridge 126:abea610beb85 1127 /**
AnnaBridge 126:abea610beb85 1128 * @}
AnnaBridge 126:abea610beb85 1129 */
AnnaBridge 126:abea610beb85 1130
AnnaBridge 126:abea610beb85 1131 /** @defgroup FMC_Interrupt FMC Interrupt
AnnaBridge 126:abea610beb85 1132 * @brief macros to handle FMC interrupts
AnnaBridge 126:abea610beb85 1133 * @{
AnnaBridge 126:abea610beb85 1134 */
AnnaBridge 126:abea610beb85 1135
AnnaBridge 126:abea610beb85 1136 /**
AnnaBridge 126:abea610beb85 1137 * @brief Enable the NAND device interrupt.
AnnaBridge 126:abea610beb85 1138 * @param __INSTANCE__: FMC_NAND instance
AnnaBridge 126:abea610beb85 1139 * @param __INTERRUPT__: FMC_NAND interrupt
AnnaBridge 126:abea610beb85 1140 * This parameter can be any combination of the following values:
AnnaBridge 126:abea610beb85 1141 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
AnnaBridge 126:abea610beb85 1142 * @arg FMC_IT_LEVEL: Interrupt level.
AnnaBridge 126:abea610beb85 1143 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
AnnaBridge 126:abea610beb85 1144 * @retval None
AnnaBridge 126:abea610beb85 1145 */
AnnaBridge 126:abea610beb85 1146 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__))
AnnaBridge 126:abea610beb85 1147
AnnaBridge 126:abea610beb85 1148 /**
AnnaBridge 126:abea610beb85 1149 * @brief Disable the NAND device interrupt.
AnnaBridge 126:abea610beb85 1150 * @param __INSTANCE__: FMC_NAND Instance
AnnaBridge 126:abea610beb85 1151 * @param __INTERRUPT__: FMC_NAND interrupt
AnnaBridge 126:abea610beb85 1152 * This parameter can be any combination of the following values:
AnnaBridge 126:abea610beb85 1153 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
AnnaBridge 126:abea610beb85 1154 * @arg FMC_IT_LEVEL: Interrupt level.
AnnaBridge 126:abea610beb85 1155 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
AnnaBridge 126:abea610beb85 1156 * @retval None
AnnaBridge 126:abea610beb85 1157 */
AnnaBridge 126:abea610beb85 1158 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
AnnaBridge 126:abea610beb85 1159
AnnaBridge 126:abea610beb85 1160 /**
AnnaBridge 126:abea610beb85 1161 * @brief Get flag status of the NAND device.
AnnaBridge 126:abea610beb85 1162 * @param __INSTANCE__: FMC_NAND Instance
AnnaBridge 126:abea610beb85 1163 * @param __BANK__: FMC_NAND Bank
AnnaBridge 126:abea610beb85 1164 * @param __FLAG__: FMC_NAND flag
AnnaBridge 126:abea610beb85 1165 * This parameter can be any combination of the following values:
AnnaBridge 126:abea610beb85 1166 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
AnnaBridge 126:abea610beb85 1167 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
AnnaBridge 126:abea610beb85 1168 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
AnnaBridge 126:abea610beb85 1169 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
AnnaBridge 126:abea610beb85 1170 * @retval The state of FLAG (SET or RESET).
AnnaBridge 126:abea610beb85 1171 */
AnnaBridge 126:abea610beb85 1172 #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
AnnaBridge 126:abea610beb85 1173
AnnaBridge 126:abea610beb85 1174 /**
AnnaBridge 126:abea610beb85 1175 * @brief Clear flag status of the NAND device.
AnnaBridge 126:abea610beb85 1176 * @param __INSTANCE__: FMC_NAND Instance
AnnaBridge 126:abea610beb85 1177 * @param __FLAG__: FMC_NAND flag
AnnaBridge 126:abea610beb85 1178 * This parameter can be any combination of the following values:
AnnaBridge 126:abea610beb85 1179 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
AnnaBridge 126:abea610beb85 1180 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
AnnaBridge 126:abea610beb85 1181 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
AnnaBridge 126:abea610beb85 1182 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
AnnaBridge 126:abea610beb85 1183 * @retval None
AnnaBridge 126:abea610beb85 1184 */
AnnaBridge 126:abea610beb85 1185 #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__))
AnnaBridge 126:abea610beb85 1186
AnnaBridge 126:abea610beb85 1187 /**
AnnaBridge 126:abea610beb85 1188 * @brief Enable the SDRAM device interrupt.
AnnaBridge 126:abea610beb85 1189 * @param __INSTANCE__: FMC_SDRAM instance
AnnaBridge 126:abea610beb85 1190 * @param __INTERRUPT__: FMC_SDRAM interrupt
AnnaBridge 126:abea610beb85 1191 * This parameter can be any combination of the following values:
AnnaBridge 126:abea610beb85 1192 * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
AnnaBridge 126:abea610beb85 1193 * @retval None
AnnaBridge 126:abea610beb85 1194 */
AnnaBridge 126:abea610beb85 1195 #define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR |= (__INTERRUPT__))
AnnaBridge 126:abea610beb85 1196
AnnaBridge 126:abea610beb85 1197 /**
AnnaBridge 126:abea610beb85 1198 * @brief Disable the SDRAM device interrupt.
AnnaBridge 126:abea610beb85 1199 * @param __INSTANCE__: FMC_SDRAM instance
AnnaBridge 126:abea610beb85 1200 * @param __INTERRUPT__: FMC_SDRAM interrupt
AnnaBridge 126:abea610beb85 1201 * This parameter can be any combination of the following values:
AnnaBridge 126:abea610beb85 1202 * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
AnnaBridge 126:abea610beb85 1203 * @retval None
AnnaBridge 126:abea610beb85 1204 */
AnnaBridge 126:abea610beb85 1205 #define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
AnnaBridge 126:abea610beb85 1206
AnnaBridge 126:abea610beb85 1207 /**
AnnaBridge 126:abea610beb85 1208 * @brief Get flag status of the SDRAM device.
AnnaBridge 126:abea610beb85 1209 * @param __INSTANCE__: FMC_SDRAM instance
AnnaBridge 126:abea610beb85 1210 * @param __FLAG__: FMC_SDRAM flag
AnnaBridge 126:abea610beb85 1211 * This parameter can be any combination of the following values:
AnnaBridge 126:abea610beb85 1212 * @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
AnnaBridge 126:abea610beb85 1213 * @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
AnnaBridge 126:abea610beb85 1214 * @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
AnnaBridge 126:abea610beb85 1215 * @retval The state of FLAG (SET or RESET).
AnnaBridge 126:abea610beb85 1216 */
AnnaBridge 126:abea610beb85 1217 #define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
AnnaBridge 126:abea610beb85 1218
AnnaBridge 126:abea610beb85 1219 /**
AnnaBridge 126:abea610beb85 1220 * @brief Clear flag status of the SDRAM device.
AnnaBridge 126:abea610beb85 1221 * @param __INSTANCE__: FMC_SDRAM instance
AnnaBridge 126:abea610beb85 1222 * @param __FLAG__: FMC_SDRAM flag
AnnaBridge 126:abea610beb85 1223 * This parameter can be any combination of the following values:
AnnaBridge 126:abea610beb85 1224 * @arg FMC_SDRAM_FLAG_REFRESH_ERROR
AnnaBridge 126:abea610beb85 1225 * @retval None
AnnaBridge 126:abea610beb85 1226 */
AnnaBridge 126:abea610beb85 1227 #define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR |= (__FLAG__))
AnnaBridge 126:abea610beb85 1228 /**
AnnaBridge 126:abea610beb85 1229 * @}
AnnaBridge 126:abea610beb85 1230 */
AnnaBridge 126:abea610beb85 1231
AnnaBridge 126:abea610beb85 1232 /**
AnnaBridge 126:abea610beb85 1233 * @}
AnnaBridge 126:abea610beb85 1234 */
AnnaBridge 126:abea610beb85 1235
AnnaBridge 126:abea610beb85 1236 /* Private functions ---------------------------------------------------------*/
AnnaBridge 126:abea610beb85 1237 /** @defgroup FMC_LL_Private_Functions FMC LL Private Functions
AnnaBridge 126:abea610beb85 1238 * @{
AnnaBridge 126:abea610beb85 1239 */
AnnaBridge 126:abea610beb85 1240
AnnaBridge 126:abea610beb85 1241 /** @defgroup FMC_LL_NORSRAM NOR SRAM
AnnaBridge 126:abea610beb85 1242 * @{
AnnaBridge 126:abea610beb85 1243 */
AnnaBridge 126:abea610beb85 1244 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
AnnaBridge 126:abea610beb85 1245 * @{
AnnaBridge 126:abea610beb85 1246 */
AnnaBridge 126:abea610beb85 1247 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init);
AnnaBridge 126:abea610beb85 1248 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
AnnaBridge 126:abea610beb85 1249 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
AnnaBridge 126:abea610beb85 1250 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
AnnaBridge 126:abea610beb85 1251 /**
AnnaBridge 126:abea610beb85 1252 * @}
AnnaBridge 126:abea610beb85 1253 */
AnnaBridge 126:abea610beb85 1254
AnnaBridge 126:abea610beb85 1255 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
AnnaBridge 126:abea610beb85 1256 * @{
AnnaBridge 126:abea610beb85 1257 */
AnnaBridge 126:abea610beb85 1258 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
AnnaBridge 126:abea610beb85 1259 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
AnnaBridge 126:abea610beb85 1260 /**
AnnaBridge 126:abea610beb85 1261 * @}
AnnaBridge 126:abea610beb85 1262 */
AnnaBridge 126:abea610beb85 1263 /**
AnnaBridge 126:abea610beb85 1264 * @}
AnnaBridge 126:abea610beb85 1265 */
AnnaBridge 126:abea610beb85 1266
AnnaBridge 126:abea610beb85 1267 /** @defgroup FMC_LL_NAND NAND
AnnaBridge 126:abea610beb85 1268 * @{
AnnaBridge 126:abea610beb85 1269 */
AnnaBridge 126:abea610beb85 1270 /** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
AnnaBridge 126:abea610beb85 1271 * @{
AnnaBridge 126:abea610beb85 1272 */
AnnaBridge 126:abea610beb85 1273 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
AnnaBridge 126:abea610beb85 1274 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
AnnaBridge 126:abea610beb85 1275 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
AnnaBridge 126:abea610beb85 1276 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
AnnaBridge 126:abea610beb85 1277 /**
AnnaBridge 126:abea610beb85 1278 * @}
AnnaBridge 126:abea610beb85 1279 */
AnnaBridge 126:abea610beb85 1280
AnnaBridge 126:abea610beb85 1281 /** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions
AnnaBridge 126:abea610beb85 1282 * @{
AnnaBridge 126:abea610beb85 1283 */
AnnaBridge 126:abea610beb85 1284 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
AnnaBridge 126:abea610beb85 1285 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
AnnaBridge 126:abea610beb85 1286 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
AnnaBridge 126:abea610beb85 1287 /**
AnnaBridge 126:abea610beb85 1288 * @}
AnnaBridge 126:abea610beb85 1289 */
AnnaBridge 126:abea610beb85 1290
AnnaBridge 126:abea610beb85 1291 /** @defgroup FMC_LL_SDRAM SDRAM
AnnaBridge 126:abea610beb85 1292 * @{
AnnaBridge 126:abea610beb85 1293 */
AnnaBridge 126:abea610beb85 1294 /** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions
AnnaBridge 126:abea610beb85 1295 * @{
AnnaBridge 126:abea610beb85 1296 */
AnnaBridge 126:abea610beb85 1297 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init);
AnnaBridge 126:abea610beb85 1298 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank);
AnnaBridge 126:abea610beb85 1299 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
AnnaBridge 126:abea610beb85 1300
AnnaBridge 126:abea610beb85 1301 /**
AnnaBridge 126:abea610beb85 1302 * @}
AnnaBridge 126:abea610beb85 1303 */
AnnaBridge 126:abea610beb85 1304
AnnaBridge 126:abea610beb85 1305 /** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions
AnnaBridge 126:abea610beb85 1306 * @{
AnnaBridge 126:abea610beb85 1307 */
AnnaBridge 126:abea610beb85 1308 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
AnnaBridge 126:abea610beb85 1309 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
AnnaBridge 126:abea610beb85 1310 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
AnnaBridge 126:abea610beb85 1311 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
AnnaBridge 126:abea610beb85 1312 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
AnnaBridge 126:abea610beb85 1313 uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
AnnaBridge 126:abea610beb85 1314 /**
AnnaBridge 126:abea610beb85 1315 * @}
AnnaBridge 126:abea610beb85 1316 */
AnnaBridge 126:abea610beb85 1317
AnnaBridge 126:abea610beb85 1318 /**
AnnaBridge 126:abea610beb85 1319 * @}
AnnaBridge 126:abea610beb85 1320 */
AnnaBridge 126:abea610beb85 1321
AnnaBridge 126:abea610beb85 1322 /**
AnnaBridge 126:abea610beb85 1323 * @}
AnnaBridge 126:abea610beb85 1324 */
AnnaBridge 126:abea610beb85 1325
AnnaBridge 126:abea610beb85 1326 /**
AnnaBridge 126:abea610beb85 1327 * @}
AnnaBridge 126:abea610beb85 1328 */
AnnaBridge 126:abea610beb85 1329
AnnaBridge 126:abea610beb85 1330 /**
AnnaBridge 126:abea610beb85 1331 * @}
AnnaBridge 126:abea610beb85 1332 */
AnnaBridge 126:abea610beb85 1333 #ifdef __cplusplus
AnnaBridge 126:abea610beb85 1334 }
AnnaBridge 126:abea610beb85 1335 #endif
AnnaBridge 126:abea610beb85 1336
AnnaBridge 126:abea610beb85 1337 #endif /* __STM32F7xx_LL_FMC_H */
AnnaBridge 126:abea610beb85 1338
AnnaBridge 126:abea610beb85 1339 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/