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TARGET_NUCLEO_F767ZI/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rcc_ex.h@136:ef9c61f8c49f, 2017-02-14 (annotated)

Committer:: Kojto
Date:: Tue Feb 14 11:24:20 2017 +0000
Revision:: 136:ef9c61f8c49f
Parent:: 135:176b8275d35d
Child:: 139:856d2700e60b

Release 136 of the mbed library

Ports for Upcoming Targets

Fixes and Changes

3432: Target STM USBHOST support https://github.com/ARMmbed/mbed-os/pull/3432

3181: NUCLEO_F207ZG extending PeripheralPins.c: all available alternate functions can be used now https://github.com/ARMmbed/mbed-os/pull/3181

3626: NUCLEO_F412ZG : Add USB Device +Host https://github.com/ARMmbed/mbed-os/pull/3626

3628: Fix warnings https://github.com/ARMmbed/mbed-os/pull/3628

3629: STM32: L0 LL layer https://github.com/ARMmbed/mbed-os/pull/3629

3632: IDE Export support for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3632

3642: Missing IRQ pin fix for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3642

3664: Fix ncs36510 sleep definitions https://github.com/ARMmbed/mbed-os/pull/3664

3655: [STM32F4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3655

3657: [STM32L4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3657

3658: [STM32F3] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3658

3685: STM32: I2C: reset state machine https://github.com/ARMmbed/mbed-os/pull/3685

3692: uVisor: Standardize available legacy heap and stack https://github.com/ARMmbed/mbed-os/pull/3692

3621: Fix for #2884, LPC824: export to LPCXpresso, target running with wron https://github.com/ARMmbed/mbed-os/pull/3621

3649: [STM32F7] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3649

3695: Enforce device_name is valid in targets.json https://github.com/ARMmbed/mbed-os/pull/3695

3723: NCS36510: spi_format function bug fix https://github.com/ARMmbed/mbed-os/pull/3723

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	126:abea610beb85	1	/**
AnnaBridge	126:abea610beb85	2	******************************************************************************
AnnaBridge	126:abea610beb85	3	* @file stm32f7xx_hal_rcc_ex.h
AnnaBridge	126:abea610beb85	4	* @author MCD Application Team
<>	135:176b8275d35d	5	* @version V1.1.2
<>	135:176b8275d35d	6	* @date 23-September-2016
AnnaBridge	126:abea610beb85	7	* @brief Header file of RCC HAL Extension module.
AnnaBridge	126:abea610beb85	8	******************************************************************************
AnnaBridge	126:abea610beb85	9	* @attention
AnnaBridge	126:abea610beb85	10	*
AnnaBridge	126:abea610beb85	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge	126:abea610beb85	12	*
AnnaBridge	126:abea610beb85	13	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	126:abea610beb85	14	* are permitted provided that the following conditions are met:
AnnaBridge	126:abea610beb85	15	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	126:abea610beb85	16	* this list of conditions and the following disclaimer.
AnnaBridge	126:abea610beb85	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	126:abea610beb85	18	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	126:abea610beb85	19	* and/or other materials provided with the distribution.
AnnaBridge	126:abea610beb85	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	126:abea610beb85	21	* may be used to endorse or promote products derived from this software
AnnaBridge	126:abea610beb85	22	* without specific prior written permission.
AnnaBridge	126:abea610beb85	23	*
AnnaBridge	126:abea610beb85	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	126:abea610beb85	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	126:abea610beb85	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	126:abea610beb85	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	126:abea610beb85	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	126:abea610beb85	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	126:abea610beb85	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	126:abea610beb85	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	126:abea610beb85	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	126:abea610beb85	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	126:abea610beb85	34	*
AnnaBridge	126:abea610beb85	35	******************************************************************************
AnnaBridge	126:abea610beb85	36	*/
AnnaBridge	126:abea610beb85	37
AnnaBridge	126:abea610beb85	38	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	126:abea610beb85	39	#ifndef __STM32F7xx_HAL_RCC_EX_H
AnnaBridge	126:abea610beb85	40	#define __STM32F7xx_HAL_RCC_EX_H
AnnaBridge	126:abea610beb85	41
AnnaBridge	126:abea610beb85	42	#ifdef __cplusplus
AnnaBridge	126:abea610beb85	43	extern "C" {
AnnaBridge	126:abea610beb85	44	#endif
AnnaBridge	126:abea610beb85	45
AnnaBridge	126:abea610beb85	46	/* Includes ------------------------------------------------------------------*/
AnnaBridge	126:abea610beb85	47	#include "stm32f7xx_hal_def.h"
AnnaBridge	126:abea610beb85	48
AnnaBridge	126:abea610beb85	49	/** @addtogroup STM32F7xx_HAL_Driver
AnnaBridge	126:abea610beb85	50	* @{
AnnaBridge	126:abea610beb85	51	*/
AnnaBridge	126:abea610beb85	52
AnnaBridge	126:abea610beb85	53	/** @addtogroup RCCEx
AnnaBridge	126:abea610beb85	54	* @{
AnnaBridge	126:abea610beb85	55	*/
AnnaBridge	126:abea610beb85	56
AnnaBridge	126:abea610beb85	57	/* Exported types ------------------------------------------------------------*/
AnnaBridge	126:abea610beb85	58	/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
AnnaBridge	126:abea610beb85	59	* @{
AnnaBridge	126:abea610beb85	60	*/
AnnaBridge	126:abea610beb85	61
AnnaBridge	126:abea610beb85	62	/**
AnnaBridge	126:abea610beb85	63	* @brief RCC PLL configuration structure definition
AnnaBridge	126:abea610beb85	64	*/
AnnaBridge	126:abea610beb85	65	typedef struct
AnnaBridge	126:abea610beb85	66	{
AnnaBridge	126:abea610beb85	67	uint32_t PLLState; /*!< The new state of the PLL.
AnnaBridge	126:abea610beb85	68	This parameter can be a value of @ref RCC_PLL_Config */
AnnaBridge	126:abea610beb85	69
AnnaBridge	126:abea610beb85	70	uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
AnnaBridge	126:abea610beb85	71	This parameter must be a value of @ref RCC_PLL_Clock_Source */
AnnaBridge	126:abea610beb85	72
AnnaBridge	126:abea610beb85	73	uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
AnnaBridge	126:abea610beb85	74	This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
AnnaBridge	126:abea610beb85	75
AnnaBridge	126:abea610beb85	76	uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
AnnaBridge	126:abea610beb85	77	This parameter must be a number between Min_Data = 50 and Max_Data = 432 */
AnnaBridge	126:abea610beb85	78
AnnaBridge	126:abea610beb85	79	uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).
AnnaBridge	126:abea610beb85	80	This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
AnnaBridge	126:abea610beb85	81
AnnaBridge	126:abea610beb85	82	uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDMMC and RNG clocks.
AnnaBridge	126:abea610beb85	83	This parameter must be a number between Min_Data = 2 and Max_Data = 15 */
AnnaBridge	126:abea610beb85	84	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	85	uint32_t PLLR; /*!< PLLR: Division factor for DSI clock.
AnnaBridge	126:abea610beb85	86	This parameter must be a number between Min_Data = 2 and Max_Data = 7 */
AnnaBridge	126:abea610beb85	87	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	88
AnnaBridge	126:abea610beb85	89	}RCC_PLLInitTypeDef;
AnnaBridge	126:abea610beb85	90
AnnaBridge	126:abea610beb85	91	/**
AnnaBridge	126:abea610beb85	92	* @brief PLLI2S Clock structure definition
AnnaBridge	126:abea610beb85	93	*/
AnnaBridge	126:abea610beb85	94	typedef struct
AnnaBridge	126:abea610beb85	95	{
AnnaBridge	126:abea610beb85	96	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
AnnaBridge	126:abea610beb85	97	This parameter must be a number between Min_Data = 50 and Max_Data = 432.
AnnaBridge	126:abea610beb85	98	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
AnnaBridge	126:abea610beb85	99
AnnaBridge	126:abea610beb85	100	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
AnnaBridge	126:abea610beb85	101	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
AnnaBridge	126:abea610beb85	102	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
AnnaBridge	126:abea610beb85	103
AnnaBridge	126:abea610beb85	104	uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock.
AnnaBridge	126:abea610beb85	105	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
AnnaBridge	126:abea610beb85	106	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
AnnaBridge	126:abea610beb85	107
<>	135:176b8275d35d	108	#if defined (STM32F745xx) \|\| defined (STM32F746xx) \|\| defined (STM32F756xx) \|\| defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| \
<>	135:176b8275d35d	109	defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	110	uint32_t PLLI2SP; /*!< Specifies the division factor for SPDIF-RX clock.
AnnaBridge	126:abea610beb85	111	This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider.
AnnaBridge	126:abea610beb85	112	This parameter will be used only when PLLI2S is selected as Clock Source SPDIF-RX */
<>	135:176b8275d35d	113	#endif /* STM32F745xx \|\| STM32F746xx \|\| STM32F756xx \|\| STM32F765xx \|\| STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	114	}RCC_PLLI2SInitTypeDef;
AnnaBridge	126:abea610beb85	115
AnnaBridge	126:abea610beb85	116	/**
AnnaBridge	126:abea610beb85	117	* @brief PLLSAI Clock structure definition
AnnaBridge	126:abea610beb85	118	*/
AnnaBridge	126:abea610beb85	119	typedef struct
AnnaBridge	126:abea610beb85	120	{
AnnaBridge	126:abea610beb85	121	uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
AnnaBridge	126:abea610beb85	122	This parameter must be a number between Min_Data = 50 and Max_Data = 432.
AnnaBridge	126:abea610beb85	123	This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
AnnaBridge	126:abea610beb85	124
AnnaBridge	126:abea610beb85	125	uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.
AnnaBridge	126:abea610beb85	126	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
AnnaBridge	126:abea610beb85	127	This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
<>	135:176b8275d35d	128
<>	135:176b8275d35d	129	#if defined (STM32F745xx) \|\| defined (STM32F746xx) \|\| defined (STM32F756xx) \|\| defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| \
<>	135:176b8275d35d	130	defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	131	uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock
AnnaBridge	126:abea610beb85	132	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
AnnaBridge	126:abea610beb85	133	This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
<>	135:176b8275d35d	134	#endif /* STM32F745xx \|\| STM32F746xx \|\| STM32F756xx \|\| STM32F765xx \|\| STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	135:176b8275d35d	135
AnnaBridge	126:abea610beb85	136	uint32_t PLLSAIP; /*!< Specifies the division factor for 48MHz clock.
AnnaBridge	126:abea610beb85	137	This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider
AnnaBridge	126:abea610beb85	138	This parameter will be used only when PLLSAI is disabled */
AnnaBridge	126:abea610beb85	139	}RCC_PLLSAIInitTypeDef;
AnnaBridge	126:abea610beb85	140
AnnaBridge	126:abea610beb85	141	/**
AnnaBridge	126:abea610beb85	142	* @brief RCC extended clocks structure definition
AnnaBridge	126:abea610beb85	143	*/
AnnaBridge	126:abea610beb85	144	typedef struct
AnnaBridge	126:abea610beb85	145	{
AnnaBridge	126:abea610beb85	146	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge	126:abea610beb85	147	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge	126:abea610beb85	148
AnnaBridge	126:abea610beb85	149	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
AnnaBridge	126:abea610beb85	150	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
AnnaBridge	126:abea610beb85	151
AnnaBridge	126:abea610beb85	152	RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
AnnaBridge	126:abea610beb85	153	This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
AnnaBridge	126:abea610beb85	154
AnnaBridge	126:abea610beb85	155	uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
AnnaBridge	126:abea610beb85	156	This parameter must be a number between Min_Data = 1 and Max_Data = 32
AnnaBridge	126:abea610beb85	157	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
AnnaBridge	126:abea610beb85	158
AnnaBridge	126:abea610beb85	159	uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
AnnaBridge	126:abea610beb85	160	This parameter must be a number between Min_Data = 1 and Max_Data = 32
AnnaBridge	126:abea610beb85	161	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
AnnaBridge	126:abea610beb85	162
AnnaBridge	126:abea610beb85	163	uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock.
AnnaBridge	126:abea610beb85	164	This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
AnnaBridge	126:abea610beb85	165
AnnaBridge	126:abea610beb85	166	uint32_t RTCClockSelection; /*!< Specifies RTC Clock source Selection.
AnnaBridge	126:abea610beb85	167	This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge	126:abea610beb85	168
AnnaBridge	126:abea610beb85	169	uint32_t I2sClockSelection; /*!< Specifies I2S Clock source Selection.
AnnaBridge	126:abea610beb85	170	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
AnnaBridge	126:abea610beb85	171
AnnaBridge	126:abea610beb85	172	uint32_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
AnnaBridge	126:abea610beb85	173	This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */
AnnaBridge	126:abea610beb85	174
AnnaBridge	126:abea610beb85	175	uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Prescalers Selection
AnnaBridge	126:abea610beb85	176	This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
AnnaBridge	126:abea610beb85	177
AnnaBridge	126:abea610beb85	178	uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Prescalers Selection
AnnaBridge	126:abea610beb85	179	This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
AnnaBridge	126:abea610beb85	180
AnnaBridge	126:abea610beb85	181	uint32_t Usart1ClockSelection; /*!< USART1 clock source
AnnaBridge	126:abea610beb85	182	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
AnnaBridge	126:abea610beb85	183
AnnaBridge	126:abea610beb85	184	uint32_t Usart2ClockSelection; /*!< USART2 clock source
AnnaBridge	126:abea610beb85	185	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
AnnaBridge	126:abea610beb85	186
AnnaBridge	126:abea610beb85	187	uint32_t Usart3ClockSelection; /*!< USART3 clock source
AnnaBridge	126:abea610beb85	188	This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
AnnaBridge	126:abea610beb85	189
AnnaBridge	126:abea610beb85	190	uint32_t Uart4ClockSelection; /*!< UART4 clock source
AnnaBridge	126:abea610beb85	191	This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
AnnaBridge	126:abea610beb85	192
AnnaBridge	126:abea610beb85	193	uint32_t Uart5ClockSelection; /*!< UART5 clock source
AnnaBridge	126:abea610beb85	194	This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
AnnaBridge	126:abea610beb85	195
AnnaBridge	126:abea610beb85	196	uint32_t Usart6ClockSelection; /*!< USART6 clock source
AnnaBridge	126:abea610beb85	197	This parameter can be a value of @ref RCCEx_USART6_Clock_Source */
AnnaBridge	126:abea610beb85	198
AnnaBridge	126:abea610beb85	199	uint32_t Uart7ClockSelection; /*!< UART7 clock source
AnnaBridge	126:abea610beb85	200	This parameter can be a value of @ref RCCEx_UART7_Clock_Source */
AnnaBridge	126:abea610beb85	201
AnnaBridge	126:abea610beb85	202	uint32_t Uart8ClockSelection; /*!< UART8 clock source
AnnaBridge	126:abea610beb85	203	This parameter can be a value of @ref RCCEx_UART8_Clock_Source */
AnnaBridge	126:abea610beb85	204
AnnaBridge	126:abea610beb85	205	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
AnnaBridge	126:abea610beb85	206	This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
AnnaBridge	126:abea610beb85	207
AnnaBridge	126:abea610beb85	208	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
AnnaBridge	126:abea610beb85	209	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
AnnaBridge	126:abea610beb85	210
AnnaBridge	126:abea610beb85	211	uint32_t I2c3ClockSelection; /*!< I2C3 clock source
AnnaBridge	126:abea610beb85	212	This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
AnnaBridge	126:abea610beb85	213
AnnaBridge	126:abea610beb85	214	uint32_t I2c4ClockSelection; /*!< I2C4 clock source
AnnaBridge	126:abea610beb85	215	This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */
AnnaBridge	126:abea610beb85	216
AnnaBridge	126:abea610beb85	217	uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source
AnnaBridge	126:abea610beb85	218	This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
AnnaBridge	126:abea610beb85	219
AnnaBridge	126:abea610beb85	220	uint32_t CecClockSelection; /*!< CEC clock source
AnnaBridge	126:abea610beb85	221	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
AnnaBridge	126:abea610beb85	222
AnnaBridge	126:abea610beb85	223	uint32_t Clk48ClockSelection; /*!< Specifies 48Mhz clock source used by USB OTG FS, RNG and SDMMC
AnnaBridge	126:abea610beb85	224	This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
AnnaBridge	126:abea610beb85	225
AnnaBridge	126:abea610beb85	226	uint32_t Sdmmc1ClockSelection; /*!< SDMMC1 clock source
AnnaBridge	126:abea610beb85	227	This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */
AnnaBridge	126:abea610beb85	228
AnnaBridge	126:abea610beb85	229	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	230	uint32_t Sdmmc2ClockSelection; /*!< SDMMC2 clock source
AnnaBridge	126:abea610beb85	231	This parameter can be a value of @ref RCCEx_SDMMC2_Clock_Source */
AnnaBridge	126:abea610beb85	232
AnnaBridge	126:abea610beb85	233	uint32_t Dfsdm1ClockSelection; /*!< DFSDM1 clock source
AnnaBridge	126:abea610beb85	234	This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */
AnnaBridge	126:abea610beb85	235
AnnaBridge	126:abea610beb85	236	uint32_t Dfsdm1AudioClockSelection; /*!< DFSDM1 clock source
AnnaBridge	126:abea610beb85	237	This parameter can be a value of @ref RCCEx_DFSDM1_AUDIO_Clock_Source */
AnnaBridge	126:abea610beb85	238	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	239	}RCC_PeriphCLKInitTypeDef;
AnnaBridge	126:abea610beb85	240	/**
AnnaBridge	126:abea610beb85	241	* @}
AnnaBridge	126:abea610beb85	242	*/
AnnaBridge	126:abea610beb85	243
AnnaBridge	126:abea610beb85	244	/* Exported constants --------------------------------------------------------*/
AnnaBridge	126:abea610beb85	245	/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
AnnaBridge	126:abea610beb85	246	* @{
AnnaBridge	126:abea610beb85	247	*/
AnnaBridge	126:abea610beb85	248
AnnaBridge	126:abea610beb85	249	/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
AnnaBridge	126:abea610beb85	250	* @{
AnnaBridge	126:abea610beb85	251	*/
AnnaBridge	126:abea610beb85	252	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001U)
AnnaBridge	126:abea610beb85	253	#if defined(STM32F746xx) \|\| defined(STM32F756xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	254	#define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008U)
AnnaBridge	126:abea610beb85	255	#endif /* STM32F746xx \|\| STM32F756xx \|\| STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	256	#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010U)
AnnaBridge	126:abea610beb85	257	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020U)
AnnaBridge	126:abea610beb85	258	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000040U)
AnnaBridge	126:abea610beb85	259	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000080U)
AnnaBridge	126:abea610beb85	260	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000100U)
AnnaBridge	126:abea610beb85	261	#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000200U)
AnnaBridge	126:abea610beb85	262	#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000400U)
AnnaBridge	126:abea610beb85	263	#define RCC_PERIPHCLK_USART6 ((uint32_t)0x00000800U)
AnnaBridge	126:abea610beb85	264	#define RCC_PERIPHCLK_UART7 ((uint32_t)0x00001000U)
AnnaBridge	126:abea610beb85	265	#define RCC_PERIPHCLK_UART8 ((uint32_t)0x00002000U)
AnnaBridge	126:abea610beb85	266	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00004000U)
AnnaBridge	126:abea610beb85	267	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00008000U)
AnnaBridge	126:abea610beb85	268	#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00010000U)
AnnaBridge	126:abea610beb85	269	#define RCC_PERIPHCLK_I2C4 ((uint32_t)0x00020000U)
AnnaBridge	126:abea610beb85	270	#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00040000U)
AnnaBridge	126:abea610beb85	271	#define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00080000U)
AnnaBridge	126:abea610beb85	272	#define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00100000U)
AnnaBridge	126:abea610beb85	273	#define RCC_PERIPHCLK_CLK48 ((uint32_t)0x00200000U)
AnnaBridge	126:abea610beb85	274	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00400000U)
AnnaBridge	126:abea610beb85	275	#define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00800000U)
AnnaBridge	126:abea610beb85	276	#define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x01000000U)
AnnaBridge	126:abea610beb85	277	#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x02000000U)
AnnaBridge	126:abea610beb85	278	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	279	#define RCC_PERIPHCLK_SDMMC2 ((uint32_t)0x04000000U)
AnnaBridge	126:abea610beb85	280	#define RCC_PERIPHCLK_DFSDM1 ((uint32_t)0x08000000U)
AnnaBridge	126:abea610beb85	281	#define RCC_PERIPHCLK_DFSDM1_AUDIO ((uint32_t)0x10000000U)
<>	135:176b8275d35d	282	#endif /* STM32F765xx \|\| STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	283
AnnaBridge	126:abea610beb85	284	/**
AnnaBridge	126:abea610beb85	285	* @}
AnnaBridge	126:abea610beb85	286	*/
AnnaBridge	126:abea610beb85	287
<>	135:176b8275d35d	288	#if defined (STM32F745xx) \|\| defined (STM32F746xx) \|\| defined (STM32F756xx) \|\| defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| \
<>	135:176b8275d35d	289	defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	290	/** @defgroup RCCEx_PLLI2SP_Clock_Divider RCCEx PLLI2SP Clock Divider
AnnaBridge	126:abea610beb85	291	* @{
AnnaBridge	126:abea610beb85	292	*/
AnnaBridge	126:abea610beb85	293	#define RCC_PLLI2SP_DIV2 ((uint32_t)0x00000000U)
AnnaBridge	126:abea610beb85	294	#define RCC_PLLI2SP_DIV4 ((uint32_t)0x00000001U)
AnnaBridge	126:abea610beb85	295	#define RCC_PLLI2SP_DIV6 ((uint32_t)0x00000002U)
AnnaBridge	126:abea610beb85	296	#define RCC_PLLI2SP_DIV8 ((uint32_t)0x00000003U)
AnnaBridge	126:abea610beb85	297	/**
AnnaBridge	126:abea610beb85	298	* @}
AnnaBridge	126:abea610beb85	299	*/
<>	135:176b8275d35d	300	#endif /* STM32F745xx \|\| STM32F746xx \|\| STM32F756xx \|\| STM32F765xx \|\| STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	301
AnnaBridge	126:abea610beb85	302	/** @defgroup RCCEx_PLLSAIP_Clock_Divider RCCEx PLLSAIP Clock Divider
AnnaBridge	126:abea610beb85	303	* @{
AnnaBridge	126:abea610beb85	304	*/
AnnaBridge	126:abea610beb85	305	#define RCC_PLLSAIP_DIV2 ((uint32_t)0x00000000U)
AnnaBridge	126:abea610beb85	306	#define RCC_PLLSAIP_DIV4 ((uint32_t)0x00000001U)
AnnaBridge	126:abea610beb85	307	#define RCC_PLLSAIP_DIV6 ((uint32_t)0x00000002U)
AnnaBridge	126:abea610beb85	308	#define RCC_PLLSAIP_DIV8 ((uint32_t)0x00000003U)
AnnaBridge	126:abea610beb85	309	/**
AnnaBridge	126:abea610beb85	310	* @}
AnnaBridge	126:abea610beb85	311	*/
AnnaBridge	126:abea610beb85	312
AnnaBridge	126:abea610beb85	313	/** @defgroup RCCEx_PLLSAI_DIVR RCCEx PLLSAI DIVR
AnnaBridge	126:abea610beb85	314	* @{
AnnaBridge	126:abea610beb85	315	*/
AnnaBridge	126:abea610beb85	316	#define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000U)
AnnaBridge	126:abea610beb85	317	#define RCC_PLLSAIDIVR_4 RCC_DCKCFGR1_PLLSAIDIVR_0
AnnaBridge	126:abea610beb85	318	#define RCC_PLLSAIDIVR_8 RCC_DCKCFGR1_PLLSAIDIVR_1
AnnaBridge	126:abea610beb85	319	#define RCC_PLLSAIDIVR_16 RCC_DCKCFGR1_PLLSAIDIVR
AnnaBridge	126:abea610beb85	320	/**
AnnaBridge	126:abea610beb85	321	* @}
AnnaBridge	126:abea610beb85	322	*/
AnnaBridge	126:abea610beb85	323
AnnaBridge	126:abea610beb85	324	/** @defgroup RCCEx_I2S_Clock_Source RCCEx I2S Clock Source
AnnaBridge	126:abea610beb85	325	* @{
AnnaBridge	126:abea610beb85	326	*/
AnnaBridge	126:abea610beb85	327	#define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000U)
AnnaBridge	126:abea610beb85	328	#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC
AnnaBridge	126:abea610beb85	329
AnnaBridge	126:abea610beb85	330	/**
AnnaBridge	126:abea610beb85	331	* @}
AnnaBridge	126:abea610beb85	332	*/
AnnaBridge	126:abea610beb85	333
AnnaBridge	126:abea610beb85	334
AnnaBridge	126:abea610beb85	335	/** @defgroup RCCEx_SAI1_Clock_Source RCCEx SAI1 Clock Source
AnnaBridge	126:abea610beb85	336	* @{
AnnaBridge	126:abea610beb85	337	*/
AnnaBridge	126:abea610beb85	338	#define RCC_SAI1CLKSOURCE_PLLSAI ((uint32_t)0x00000000U)
AnnaBridge	126:abea610beb85	339	#define RCC_SAI1CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI1SEL_0
AnnaBridge	126:abea610beb85	340	#define RCC_SAI1CLKSOURCE_PIN RCC_DCKCFGR1_SAI1SEL_1
AnnaBridge	126:abea610beb85	341	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	342	#define RCC_SAI1CLKSOURCE_PLLSRC RCC_DCKCFGR1_SAI1SEL
AnnaBridge	126:abea610beb85	343	#endif /* STM32F765xx \|\| STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	344	/**
AnnaBridge	126:abea610beb85	345	* @}
AnnaBridge	126:abea610beb85	346	*/
AnnaBridge	126:abea610beb85	347
AnnaBridge	126:abea610beb85	348	/** @defgroup RCCEx_SAI2_Clock_Source RCCEx SAI2 Clock Source
AnnaBridge	126:abea610beb85	349	* @{
AnnaBridge	126:abea610beb85	350	*/
AnnaBridge	126:abea610beb85	351	#define RCC_SAI2CLKSOURCE_PLLSAI ((uint32_t)0x00000000U)
AnnaBridge	126:abea610beb85	352	#define RCC_SAI2CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI2SEL_0
AnnaBridge	126:abea610beb85	353	#define RCC_SAI2CLKSOURCE_PIN RCC_DCKCFGR1_SAI2SEL_1
AnnaBridge	126:abea610beb85	354	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	355	#define RCC_SAI2CLKSOURCE_PLLSRC RCC_DCKCFGR1_SAI2SEL
AnnaBridge	126:abea610beb85	356	#endif /* STM32F765xx \|\| STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	357	/**
AnnaBridge	126:abea610beb85	358	* @}
AnnaBridge	126:abea610beb85	359	*/
AnnaBridge	126:abea610beb85	360
AnnaBridge	126:abea610beb85	361	/** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source
AnnaBridge	126:abea610beb85	362	* @{
AnnaBridge	126:abea610beb85	363	*/
AnnaBridge	126:abea610beb85	364	#define RCC_CECCLKSOURCE_LSE ((uint32_t)0x00000000U)
AnnaBridge	126:abea610beb85	365	#define RCC_CECCLKSOURCE_HSI RCC_DCKCFGR2_CECSEL /* CEC clock is HSI/488*/
AnnaBridge	126:abea610beb85	366	/**
AnnaBridge	126:abea610beb85	367	* @}
AnnaBridge	126:abea610beb85	368	*/
AnnaBridge	126:abea610beb85	369
AnnaBridge	126:abea610beb85	370	/** @defgroup RCCEx_USART1_Clock_Source RCCEx USART1 Clock Source
AnnaBridge	126:abea610beb85	371	* @{
AnnaBridge	126:abea610beb85	372	*/
AnnaBridge	126:abea610beb85	373	#define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U)
AnnaBridge	126:abea610beb85	374	#define RCC_USART1CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART1SEL_0
AnnaBridge	126:abea610beb85	375	#define RCC_USART1CLKSOURCE_HSI RCC_DCKCFGR2_USART1SEL_1
AnnaBridge	126:abea610beb85	376	#define RCC_USART1CLKSOURCE_LSE RCC_DCKCFGR2_USART1SEL
AnnaBridge	126:abea610beb85	377	/**
AnnaBridge	126:abea610beb85	378	* @}
AnnaBridge	126:abea610beb85	379	*/
AnnaBridge	126:abea610beb85	380
AnnaBridge	126:abea610beb85	381	/** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source
AnnaBridge	126:abea610beb85	382	* @{
AnnaBridge	126:abea610beb85	383	*/
AnnaBridge	126:abea610beb85	384	#define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
AnnaBridge	126:abea610beb85	385	#define RCC_USART2CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART2SEL_0
AnnaBridge	126:abea610beb85	386	#define RCC_USART2CLKSOURCE_HSI RCC_DCKCFGR2_USART2SEL_1
AnnaBridge	126:abea610beb85	387	#define RCC_USART2CLKSOURCE_LSE RCC_DCKCFGR2_USART2SEL
AnnaBridge	126:abea610beb85	388	/**
AnnaBridge	126:abea610beb85	389	* @}
AnnaBridge	126:abea610beb85	390	*/
AnnaBridge	126:abea610beb85	391
AnnaBridge	126:abea610beb85	392	/** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source
AnnaBridge	126:abea610beb85	393	* @{
AnnaBridge	126:abea610beb85	394	*/
AnnaBridge	126:abea610beb85	395	#define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
AnnaBridge	126:abea610beb85	396	#define RCC_USART3CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART3SEL_0
AnnaBridge	126:abea610beb85	397	#define RCC_USART3CLKSOURCE_HSI RCC_DCKCFGR2_USART3SEL_1
AnnaBridge	126:abea610beb85	398	#define RCC_USART3CLKSOURCE_LSE RCC_DCKCFGR2_USART3SEL
AnnaBridge	126:abea610beb85	399	/**
AnnaBridge	126:abea610beb85	400	* @}
AnnaBridge	126:abea610beb85	401	*/
AnnaBridge	126:abea610beb85	402
AnnaBridge	126:abea610beb85	403	/** @defgroup RCCEx_UART4_Clock_Source RCCEx UART4 Clock Source
AnnaBridge	126:abea610beb85	404	* @{
AnnaBridge	126:abea610beb85	405	*/
AnnaBridge	126:abea610beb85	406	#define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
AnnaBridge	126:abea610beb85	407	#define RCC_UART4CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART4SEL_0
AnnaBridge	126:abea610beb85	408	#define RCC_UART4CLKSOURCE_HSI RCC_DCKCFGR2_UART4SEL_1
AnnaBridge	126:abea610beb85	409	#define RCC_UART4CLKSOURCE_LSE RCC_DCKCFGR2_UART4SEL
AnnaBridge	126:abea610beb85	410	/**
AnnaBridge	126:abea610beb85	411	* @}
AnnaBridge	126:abea610beb85	412	*/
AnnaBridge	126:abea610beb85	413
AnnaBridge	126:abea610beb85	414	/** @defgroup RCCEx_UART5_Clock_Source RCCEx UART5 Clock Source
AnnaBridge	126:abea610beb85	415	* @{
AnnaBridge	126:abea610beb85	416	*/
AnnaBridge	126:abea610beb85	417	#define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
AnnaBridge	126:abea610beb85	418	#define RCC_UART5CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART5SEL_0
AnnaBridge	126:abea610beb85	419	#define RCC_UART5CLKSOURCE_HSI RCC_DCKCFGR2_UART5SEL_1
AnnaBridge	126:abea610beb85	420	#define RCC_UART5CLKSOURCE_LSE RCC_DCKCFGR2_UART5SEL
AnnaBridge	126:abea610beb85	421	/**
AnnaBridge	126:abea610beb85	422	* @}
AnnaBridge	126:abea610beb85	423	*/
AnnaBridge	126:abea610beb85	424
AnnaBridge	126:abea610beb85	425	/** @defgroup RCCEx_USART6_Clock_Source RCCEx USART6 Clock Source
AnnaBridge	126:abea610beb85	426	* @{
AnnaBridge	126:abea610beb85	427	*/
AnnaBridge	126:abea610beb85	428	#define RCC_USART6CLKSOURCE_PCLK2 ((uint32_t)0x00000000U)
AnnaBridge	126:abea610beb85	429	#define RCC_USART6CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART6SEL_0
AnnaBridge	126:abea610beb85	430	#define RCC_USART6CLKSOURCE_HSI RCC_DCKCFGR2_USART6SEL_1
AnnaBridge	126:abea610beb85	431	#define RCC_USART6CLKSOURCE_LSE RCC_DCKCFGR2_USART6SEL
AnnaBridge	126:abea610beb85	432	/**
AnnaBridge	126:abea610beb85	433	* @}
AnnaBridge	126:abea610beb85	434	*/
AnnaBridge	126:abea610beb85	435
AnnaBridge	126:abea610beb85	436	/** @defgroup RCCEx_UART7_Clock_Source RCCEx UART7 Clock Source
AnnaBridge	126:abea610beb85	437	* @{
AnnaBridge	126:abea610beb85	438	*/
AnnaBridge	126:abea610beb85	439	#define RCC_UART7CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
AnnaBridge	126:abea610beb85	440	#define RCC_UART7CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART7SEL_0
AnnaBridge	126:abea610beb85	441	#define RCC_UART7CLKSOURCE_HSI RCC_DCKCFGR2_UART7SEL_1
AnnaBridge	126:abea610beb85	442	#define RCC_UART7CLKSOURCE_LSE RCC_DCKCFGR2_UART7SEL
AnnaBridge	126:abea610beb85	443	/**
AnnaBridge	126:abea610beb85	444	* @}
AnnaBridge	126:abea610beb85	445	*/
AnnaBridge	126:abea610beb85	446
AnnaBridge	126:abea610beb85	447	/** @defgroup RCCEx_UART8_Clock_Source RCCEx UART8 Clock Source
AnnaBridge	126:abea610beb85	448	* @{
AnnaBridge	126:abea610beb85	449	*/
AnnaBridge	126:abea610beb85	450	#define RCC_UART8CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
AnnaBridge	126:abea610beb85	451	#define RCC_UART8CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART8SEL_0
AnnaBridge	126:abea610beb85	452	#define RCC_UART8CLKSOURCE_HSI RCC_DCKCFGR2_UART8SEL_1
AnnaBridge	126:abea610beb85	453	#define RCC_UART8CLKSOURCE_LSE RCC_DCKCFGR2_UART8SEL
AnnaBridge	126:abea610beb85	454	/**
AnnaBridge	126:abea610beb85	455	* @}
AnnaBridge	126:abea610beb85	456	*/
AnnaBridge	126:abea610beb85	457
AnnaBridge	126:abea610beb85	458	/** @defgroup RCCEx_I2C1_Clock_Source RCCEx I2C1 Clock Source
AnnaBridge	126:abea610beb85	459	* @{
AnnaBridge	126:abea610beb85	460	*/
AnnaBridge	126:abea610beb85	461	#define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
AnnaBridge	126:abea610beb85	462	#define RCC_I2C1CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C1SEL_0
AnnaBridge	126:abea610beb85	463	#define RCC_I2C1CLKSOURCE_HSI RCC_DCKCFGR2_I2C1SEL_1
AnnaBridge	126:abea610beb85	464	/**
AnnaBridge	126:abea610beb85	465	* @}
AnnaBridge	126:abea610beb85	466	*/
AnnaBridge	126:abea610beb85	467
AnnaBridge	126:abea610beb85	468	/** @defgroup RCCEx_I2C2_Clock_Source RCCEx I2C2 Clock Source
AnnaBridge	126:abea610beb85	469	* @{
AnnaBridge	126:abea610beb85	470	*/
AnnaBridge	126:abea610beb85	471	#define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
AnnaBridge	126:abea610beb85	472	#define RCC_I2C2CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C2SEL_0
AnnaBridge	126:abea610beb85	473	#define RCC_I2C2CLKSOURCE_HSI RCC_DCKCFGR2_I2C2SEL_1
AnnaBridge	126:abea610beb85	474
AnnaBridge	126:abea610beb85	475	/**
AnnaBridge	126:abea610beb85	476	* @}
AnnaBridge	126:abea610beb85	477	*/
AnnaBridge	126:abea610beb85	478
AnnaBridge	126:abea610beb85	479	/** @defgroup RCCEx_I2C3_Clock_Source RCCEx I2C3 Clock Source
AnnaBridge	126:abea610beb85	480	* @{
AnnaBridge	126:abea610beb85	481	*/
AnnaBridge	126:abea610beb85	482	#define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
AnnaBridge	126:abea610beb85	483	#define RCC_I2C3CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C3SEL_0
AnnaBridge	126:abea610beb85	484	#define RCC_I2C3CLKSOURCE_HSI RCC_DCKCFGR2_I2C3SEL_1
AnnaBridge	126:abea610beb85	485	/**
AnnaBridge	126:abea610beb85	486	* @}
AnnaBridge	126:abea610beb85	487	*/
AnnaBridge	126:abea610beb85	488
AnnaBridge	126:abea610beb85	489	/** @defgroup RCCEx_I2C4_Clock_Source RCCEx I2C4 Clock Source
AnnaBridge	126:abea610beb85	490	* @{
AnnaBridge	126:abea610beb85	491	*/
AnnaBridge	126:abea610beb85	492	#define RCC_I2C4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
AnnaBridge	126:abea610beb85	493	#define RCC_I2C4CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C4SEL_0
AnnaBridge	126:abea610beb85	494	#define RCC_I2C4CLKSOURCE_HSI RCC_DCKCFGR2_I2C4SEL_1
AnnaBridge	126:abea610beb85	495	/**
AnnaBridge	126:abea610beb85	496	* @}
AnnaBridge	126:abea610beb85	497	*/
AnnaBridge	126:abea610beb85	498
AnnaBridge	126:abea610beb85	499	/** @defgroup RCCEx_LPTIM1_Clock_Source RCCEx LPTIM1 Clock Source
AnnaBridge	126:abea610beb85	500	* @{
AnnaBridge	126:abea610beb85	501	*/
AnnaBridge	126:abea610beb85	502	#define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000U)
AnnaBridge	126:abea610beb85	503	#define RCC_LPTIM1CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_0
AnnaBridge	126:abea610beb85	504	#define RCC_LPTIM1CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_1
AnnaBridge	126:abea610beb85	505	#define RCC_LPTIM1CLKSOURCE_LSE RCC_DCKCFGR2_LPTIM1SEL
AnnaBridge	126:abea610beb85	506
AnnaBridge	126:abea610beb85	507	/**
AnnaBridge	126:abea610beb85	508	* @}
AnnaBridge	126:abea610beb85	509	*/
AnnaBridge	126:abea610beb85	510
AnnaBridge	126:abea610beb85	511	/** @defgroup RCCEx_CLK48_Clock_Source RCCEx CLK48 Clock Source
AnnaBridge	126:abea610beb85	512	* @{
AnnaBridge	126:abea610beb85	513	*/
AnnaBridge	126:abea610beb85	514	#define RCC_CLK48SOURCE_PLL ((uint32_t)0x00000000U)
AnnaBridge	126:abea610beb85	515	#define RCC_CLK48SOURCE_PLLSAIP RCC_DCKCFGR2_CK48MSEL
AnnaBridge	126:abea610beb85	516	/**
AnnaBridge	126:abea610beb85	517	* @}
AnnaBridge	126:abea610beb85	518	*/
AnnaBridge	126:abea610beb85	519
AnnaBridge	126:abea610beb85	520	/** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection
AnnaBridge	126:abea610beb85	521	* @{
AnnaBridge	126:abea610beb85	522	*/
AnnaBridge	126:abea610beb85	523	#define RCC_TIMPRES_DESACTIVATED ((uint32_t)0x00000000U)
AnnaBridge	126:abea610beb85	524	#define RCC_TIMPRES_ACTIVATED RCC_DCKCFGR1_TIMPRE
AnnaBridge	126:abea610beb85	525	/**
AnnaBridge	126:abea610beb85	526	* @}
AnnaBridge	126:abea610beb85	527	*/
AnnaBridge	126:abea610beb85	528
AnnaBridge	126:abea610beb85	529	/** @defgroup RCCEx_SDMMC1_Clock_Source RCCEx SDMMC1 Clock Source
AnnaBridge	126:abea610beb85	530	* @{
AnnaBridge	126:abea610beb85	531	*/
AnnaBridge	126:abea610beb85	532	#define RCC_SDMMC1CLKSOURCE_CLK48 ((uint32_t)0x00000000U)
AnnaBridge	126:abea610beb85	533	#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC1SEL
AnnaBridge	126:abea610beb85	534	/**
AnnaBridge	126:abea610beb85	535	* @}
AnnaBridge	126:abea610beb85	536	*/
AnnaBridge	126:abea610beb85	537
AnnaBridge	126:abea610beb85	538	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	539	/** @defgroup RCCEx_SDMMC2_Clock_Source RCCEx SDMMC2 Clock Source
AnnaBridge	126:abea610beb85	540	* @{
AnnaBridge	126:abea610beb85	541	*/
AnnaBridge	126:abea610beb85	542	#define RCC_SDMMC2CLKSOURCE_CLK48 ((uint32_t)0x00000000U)
AnnaBridge	126:abea610beb85	543	#define RCC_SDMMC2CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC2SEL
AnnaBridge	126:abea610beb85	544	/**
AnnaBridge	126:abea610beb85	545	* @}
AnnaBridge	126:abea610beb85	546	*/
AnnaBridge	126:abea610beb85	547
AnnaBridge	126:abea610beb85	548	/** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source RCCEx DFSDM1 Kernel Clock Source
AnnaBridge	126:abea610beb85	549	* @{
AnnaBridge	126:abea610beb85	550	*/
AnnaBridge	126:abea610beb85	551	#define RCC_DFSDM1CLKSOURCE_PCLK ((uint32_t)0x00000000U)
AnnaBridge	126:abea610beb85	552	#define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_DCKCFGR1_DFSDM1SEL
AnnaBridge	126:abea610beb85	553	/**
AnnaBridge	126:abea610beb85	554	* @}
AnnaBridge	126:abea610beb85	555	*/
AnnaBridge	126:abea610beb85	556
AnnaBridge	126:abea610beb85	557	/** @defgroup RCCEx_DFSDM1_AUDIO_Clock_Source RCCEx DFSDM1 AUDIO Clock Source
AnnaBridge	126:abea610beb85	558	* @{
AnnaBridge	126:abea610beb85	559	*/
AnnaBridge	126:abea610beb85	560	#define RCC_DFSDM1AUDIOCLKSOURCE_SAI1 ((uint32_t)0x00000000U)
AnnaBridge	126:abea610beb85	561	#define RCC_DFSDM1AUDIOCLKSOURCE_SAI2 RCC_DCKCFGR1_ADFSDM1SEL
AnnaBridge	126:abea610beb85	562	/**
AnnaBridge	126:abea610beb85	563	* @}
AnnaBridge	126:abea610beb85	564	*/
AnnaBridge	126:abea610beb85	565	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	566
AnnaBridge	126:abea610beb85	567	#if defined (STM32F769xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	568	/** @defgroup RCCEx_DSI_Clock_Source RCC DSI Clock Source
AnnaBridge	126:abea610beb85	569	* @{
AnnaBridge	126:abea610beb85	570	*/
AnnaBridge	126:abea610beb85	571	#define RCC_DSICLKSOURCE_DSIPHY ((uint32_t)0x00000000U)
AnnaBridge	126:abea610beb85	572	#define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR2_DSISEL)
AnnaBridge	126:abea610beb85	573	/**
AnnaBridge	126:abea610beb85	574	* @}
AnnaBridge	126:abea610beb85	575	*/
AnnaBridge	126:abea610beb85	576	#endif /* STM32F769xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	577
AnnaBridge	126:abea610beb85	578	/**
AnnaBridge	126:abea610beb85	579	* @}
AnnaBridge	126:abea610beb85	580	*/
AnnaBridge	126:abea610beb85	581
AnnaBridge	126:abea610beb85	582	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	126:abea610beb85	583	/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
AnnaBridge	126:abea610beb85	584	* @{
AnnaBridge	126:abea610beb85	585	*/
AnnaBridge	126:abea610beb85	586	/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable
AnnaBridge	126:abea610beb85	587	* @brief Enables or disables the AHB/APB peripheral clock.
AnnaBridge	126:abea610beb85	588	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	126:abea610beb85	589	* is disabled and the application software has to enable this clock before
AnnaBridge	126:abea610beb85	590	* using it.
AnnaBridge	126:abea610beb85	591	* @{
AnnaBridge	126:abea610beb85	592	*/
AnnaBridge	126:abea610beb85	593
AnnaBridge	126:abea610beb85	594	/** @brief Enables or disables the AHB1 peripheral clock.
AnnaBridge	126:abea610beb85	595	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	126:abea610beb85	596	* is disabled and the application software has to enable this clock before
AnnaBridge	126:abea610beb85	597	* using it.
AnnaBridge	126:abea610beb85	598	*/
AnnaBridge	126:abea610beb85	599	#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	600	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	601	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
AnnaBridge	126:abea610beb85	602	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	603	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
AnnaBridge	126:abea610beb85	604	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	605	} while(0)
AnnaBridge	126:abea610beb85	606
AnnaBridge	126:abea610beb85	607	#define __HAL_RCC_DTCMRAMEN_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	608	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	609	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\
AnnaBridge	126:abea610beb85	610	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	611	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\
AnnaBridge	126:abea610beb85	612	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	613	} while(0)
AnnaBridge	126:abea610beb85	614
AnnaBridge	126:abea610beb85	615	#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	616	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	617	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
AnnaBridge	126:abea610beb85	618	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	619	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
AnnaBridge	126:abea610beb85	620	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	621	} while(0)
AnnaBridge	126:abea610beb85	622
AnnaBridge	126:abea610beb85	623	#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	624	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	625	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
AnnaBridge	126:abea610beb85	626	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	627	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
AnnaBridge	126:abea610beb85	628	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	629	} while(0)
AnnaBridge	126:abea610beb85	630
AnnaBridge	126:abea610beb85	631	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	632	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	633	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
AnnaBridge	126:abea610beb85	634	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	635	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
AnnaBridge	126:abea610beb85	636	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	637	} while(0)
AnnaBridge	126:abea610beb85	638
AnnaBridge	126:abea610beb85	639	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	640	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	641	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
AnnaBridge	126:abea610beb85	642	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	643	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
AnnaBridge	126:abea610beb85	644	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	645	} while(0)
AnnaBridge	126:abea610beb85	646
AnnaBridge	126:abea610beb85	647	#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	648	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	649	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
AnnaBridge	126:abea610beb85	650	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	651	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
AnnaBridge	126:abea610beb85	652	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	653	} while(0)
AnnaBridge	126:abea610beb85	654
AnnaBridge	126:abea610beb85	655	#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	656	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	657	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
AnnaBridge	126:abea610beb85	658	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	659	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
AnnaBridge	126:abea610beb85	660	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	661	} while(0)
AnnaBridge	126:abea610beb85	662
AnnaBridge	126:abea610beb85	663	#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	664	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	665	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
AnnaBridge	126:abea610beb85	666	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	667	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
AnnaBridge	126:abea610beb85	668	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	669	} while(0)
AnnaBridge	126:abea610beb85	670
AnnaBridge	126:abea610beb85	671	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	672	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	673	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
AnnaBridge	126:abea610beb85	674	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	675	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
AnnaBridge	126:abea610beb85	676	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	677	} while(0)
AnnaBridge	126:abea610beb85	678
AnnaBridge	126:abea610beb85	679	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	680	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	681	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
AnnaBridge	126:abea610beb85	682	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	683	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
AnnaBridge	126:abea610beb85	684	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	685	} while(0)
AnnaBridge	126:abea610beb85	686
AnnaBridge	126:abea610beb85	687	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	688	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	689	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
AnnaBridge	126:abea610beb85	690	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	691	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
AnnaBridge	126:abea610beb85	692	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	693	} while(0)
AnnaBridge	126:abea610beb85	694
AnnaBridge	126:abea610beb85	695	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	696	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	697	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
AnnaBridge	126:abea610beb85	698	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	699	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
AnnaBridge	126:abea610beb85	700	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	701	} while(0)
AnnaBridge	126:abea610beb85	702
AnnaBridge	126:abea610beb85	703	#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	704	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	705	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
AnnaBridge	126:abea610beb85	706	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	707	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
AnnaBridge	126:abea610beb85	708	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	709	} while(0)
AnnaBridge	126:abea610beb85	710
AnnaBridge	126:abea610beb85	711	#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	712	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	713	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
AnnaBridge	126:abea610beb85	714	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	715	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
AnnaBridge	126:abea610beb85	716	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	717	} while(0)
AnnaBridge	126:abea610beb85	718
AnnaBridge	126:abea610beb85	719	#define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	720	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	721	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
AnnaBridge	126:abea610beb85	722	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	723	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
AnnaBridge	126:abea610beb85	724	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	725	} while(0)
AnnaBridge	126:abea610beb85	726
AnnaBridge	126:abea610beb85	727	#define __HAL_RCC_GPIOK_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	728	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	729	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
AnnaBridge	126:abea610beb85	730	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	731	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
AnnaBridge	126:abea610beb85	732	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	733	} while(0)
AnnaBridge	126:abea610beb85	734
AnnaBridge	126:abea610beb85	735	#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
AnnaBridge	126:abea610beb85	736	#define __HAL_RCC_DTCMRAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DTCMRAMEN))
AnnaBridge	126:abea610beb85	737	#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
AnnaBridge	126:abea610beb85	738	#define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
AnnaBridge	126:abea610beb85	739	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
AnnaBridge	126:abea610beb85	740	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
AnnaBridge	126:abea610beb85	741	#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
AnnaBridge	126:abea610beb85	742	#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
AnnaBridge	126:abea610beb85	743	#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
AnnaBridge	126:abea610beb85	744	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
AnnaBridge	126:abea610beb85	745	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
AnnaBridge	126:abea610beb85	746	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
AnnaBridge	126:abea610beb85	747	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
AnnaBridge	126:abea610beb85	748	#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
AnnaBridge	126:abea610beb85	749	#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
AnnaBridge	126:abea610beb85	750	#define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
AnnaBridge	126:abea610beb85	751	#define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
AnnaBridge	126:abea610beb85	752	/**
AnnaBridge	126:abea610beb85	753	* @brief Enable ETHERNET clock.
AnnaBridge	126:abea610beb85	754	*/
AnnaBridge	126:abea610beb85	755	#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	756	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	757	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
AnnaBridge	126:abea610beb85	758	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	759	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
AnnaBridge	126:abea610beb85	760	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	761	} while(0)
AnnaBridge	126:abea610beb85	762
AnnaBridge	126:abea610beb85	763	#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	764	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	765	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
AnnaBridge	126:abea610beb85	766	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	767	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
AnnaBridge	126:abea610beb85	768	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	769	} while(0)
AnnaBridge	126:abea610beb85	770
AnnaBridge	126:abea610beb85	771	#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	772	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	773	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
AnnaBridge	126:abea610beb85	774	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	775	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
AnnaBridge	126:abea610beb85	776	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	777	} while(0)
AnnaBridge	126:abea610beb85	778
AnnaBridge	126:abea610beb85	779	#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	780	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	781	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
AnnaBridge	126:abea610beb85	782	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	783	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
AnnaBridge	126:abea610beb85	784	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	785	} while(0)
AnnaBridge	126:abea610beb85	786
AnnaBridge	126:abea610beb85	787	#define __HAL_RCC_ETH_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	788	__HAL_RCC_ETHMAC_CLK_ENABLE(); \
AnnaBridge	126:abea610beb85	789	__HAL_RCC_ETHMACTX_CLK_ENABLE(); \
AnnaBridge	126:abea610beb85	790	__HAL_RCC_ETHMACRX_CLK_ENABLE(); \
AnnaBridge	126:abea610beb85	791	} while(0)
AnnaBridge	126:abea610beb85	792	/**
AnnaBridge	126:abea610beb85	793	* @brief Disable ETHERNET clock.
AnnaBridge	126:abea610beb85	794	*/
AnnaBridge	126:abea610beb85	795	#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
AnnaBridge	126:abea610beb85	796	#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
AnnaBridge	126:abea610beb85	797	#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
AnnaBridge	126:abea610beb85	798	#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
AnnaBridge	126:abea610beb85	799	#define __HAL_RCC_ETH_CLK_DISABLE() do { \
AnnaBridge	126:abea610beb85	800	__HAL_RCC_ETHMACTX_CLK_DISABLE(); \
AnnaBridge	126:abea610beb85	801	__HAL_RCC_ETHMACRX_CLK_DISABLE(); \
AnnaBridge	126:abea610beb85	802	__HAL_RCC_ETHMAC_CLK_DISABLE(); \
AnnaBridge	126:abea610beb85	803	} while(0)
AnnaBridge	126:abea610beb85	804
AnnaBridge	126:abea610beb85	805	/** @brief Enable or disable the AHB2 peripheral clock.
AnnaBridge	126:abea610beb85	806	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	126:abea610beb85	807	* is disabled and the application software has to enable this clock before
AnnaBridge	126:abea610beb85	808	* using it.
AnnaBridge	126:abea610beb85	809	*/
AnnaBridge	126:abea610beb85	810	#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	811	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	812	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
AnnaBridge	126:abea610beb85	813	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	814	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
AnnaBridge	126:abea610beb85	815	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	816	} while(0)
AnnaBridge	126:abea610beb85	817
AnnaBridge	126:abea610beb85	818	#if defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	819	#define __HAL_RCC_JPEG_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	820	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	821	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\
AnnaBridge	126:abea610beb85	822	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	823	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\
AnnaBridge	126:abea610beb85	824	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	825	} while(0)
AnnaBridge	126:abea610beb85	826	#define __HAL_RCC_JPEG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_JPEGEN))
AnnaBridge	126:abea610beb85	827	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	828
AnnaBridge	126:abea610beb85	829	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	830	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	831	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
AnnaBridge	126:abea610beb85	832	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	833	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
AnnaBridge	126:abea610beb85	834	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	835	} while(0)
AnnaBridge	126:abea610beb85	836
AnnaBridge	126:abea610beb85	837	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	838	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	839	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\
AnnaBridge	126:abea610beb85	840	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	841	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\
AnnaBridge	126:abea610beb85	842	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	843	__HAL_RCC_SYSCFG_CLK_ENABLE();\
AnnaBridge	126:abea610beb85	844	} while(0)
AnnaBridge	126:abea610beb85	845
AnnaBridge	126:abea610beb85	846	#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
AnnaBridge	126:abea610beb85	847	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
AnnaBridge	126:abea610beb85	848
AnnaBridge	126:abea610beb85	849	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
AnnaBridge	126:abea610beb85	850	#if defined(STM32F756xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	851	#define __HAL_RCC_CRYP_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	852	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	853	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
AnnaBridge	126:abea610beb85	854	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	855	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
AnnaBridge	126:abea610beb85	856	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	857	} while(0)
AnnaBridge	126:abea610beb85	858
AnnaBridge	126:abea610beb85	859	#define __HAL_RCC_HASH_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	860	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	861	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
AnnaBridge	126:abea610beb85	862	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	863	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
AnnaBridge	126:abea610beb85	864	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	865	} while(0)
AnnaBridge	126:abea610beb85	866
AnnaBridge	126:abea610beb85	867	#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
AnnaBridge	126:abea610beb85	868	#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
AnnaBridge	126:abea610beb85	869	#endif /* STM32F756x \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	870
AnnaBridge	126:abea610beb85	871	/** @brief Enables or disables the AHB3 peripheral clock.
AnnaBridge	126:abea610beb85	872	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	126:abea610beb85	873	* is disabled and the application software has to enable this clock before
AnnaBridge	126:abea610beb85	874	* using it.
AnnaBridge	126:abea610beb85	875	*/
AnnaBridge	126:abea610beb85	876	#define __HAL_RCC_FMC_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	877	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	878	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
AnnaBridge	126:abea610beb85	879	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	880	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
AnnaBridge	126:abea610beb85	881	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	882	} while(0)
AnnaBridge	126:abea610beb85	883
AnnaBridge	126:abea610beb85	884	#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	885	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	886	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
AnnaBridge	126:abea610beb85	887	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	888	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
AnnaBridge	126:abea610beb85	889	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	890	} while(0)
AnnaBridge	126:abea610beb85	891
AnnaBridge	126:abea610beb85	892	#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
AnnaBridge	126:abea610beb85	893	#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
AnnaBridge	126:abea610beb85	894
AnnaBridge	126:abea610beb85	895	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
AnnaBridge	126:abea610beb85	896	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	126:abea610beb85	897	* is disabled and the application software has to enable this clock before
AnnaBridge	126:abea610beb85	898	* using it.
AnnaBridge	126:abea610beb85	899	*/
AnnaBridge	126:abea610beb85	900	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	901	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	902	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
AnnaBridge	126:abea610beb85	903	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	904	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
AnnaBridge	126:abea610beb85	905	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	906	} while(0)
AnnaBridge	126:abea610beb85	907
AnnaBridge	126:abea610beb85	908	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	909	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	910	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
AnnaBridge	126:abea610beb85	911	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	912	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
AnnaBridge	126:abea610beb85	913	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	914	} while(0)
AnnaBridge	126:abea610beb85	915
AnnaBridge	126:abea610beb85	916	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	917	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	918	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
AnnaBridge	126:abea610beb85	919	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	920	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
AnnaBridge	126:abea610beb85	921	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	922	} while(0)
AnnaBridge	126:abea610beb85	923
AnnaBridge	126:abea610beb85	924	#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	925	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	926	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
AnnaBridge	126:abea610beb85	927	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	928	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
AnnaBridge	126:abea610beb85	929	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	930	} while(0)
AnnaBridge	126:abea610beb85	931
AnnaBridge	126:abea610beb85	932	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	933	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	934	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
AnnaBridge	126:abea610beb85	935	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	936	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
AnnaBridge	126:abea610beb85	937	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	938	} while(0)
AnnaBridge	126:abea610beb85	939
AnnaBridge	126:abea610beb85	940	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	941	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	942	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
AnnaBridge	126:abea610beb85	943	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	944	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
AnnaBridge	126:abea610beb85	945	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	946	} while(0)
AnnaBridge	126:abea610beb85	947
AnnaBridge	126:abea610beb85	948	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	949	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	950	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
AnnaBridge	126:abea610beb85	951	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	952	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
AnnaBridge	126:abea610beb85	953	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	954	} while(0)
AnnaBridge	126:abea610beb85	955
AnnaBridge	126:abea610beb85	956	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	957	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	958	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
AnnaBridge	126:abea610beb85	959	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	960	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
AnnaBridge	126:abea610beb85	961	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	962	} while(0)
AnnaBridge	126:abea610beb85	963
AnnaBridge	126:abea610beb85	964	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	965	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	966	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
AnnaBridge	126:abea610beb85	967	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	968	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
AnnaBridge	126:abea610beb85	969	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	970	} while(0)
AnnaBridge	126:abea610beb85	971
AnnaBridge	126:abea610beb85	972	#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	973	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	974	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
AnnaBridge	126:abea610beb85	975	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	976	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
AnnaBridge	126:abea610beb85	977	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	978	} while(0)
AnnaBridge	126:abea610beb85	979
AnnaBridge	126:abea610beb85	980	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	981	#define __HAL_RCC_RTC_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	982	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	983	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\
AnnaBridge	126:abea610beb85	984	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	985	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\
AnnaBridge	126:abea610beb85	986	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	987	} while(0)
AnnaBridge	126:abea610beb85	988
AnnaBridge	126:abea610beb85	989	#define __HAL_RCC_CAN3_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	990	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	991	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\
AnnaBridge	126:abea610beb85	992	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	993	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\
AnnaBridge	126:abea610beb85	994	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	995	} while(0)
AnnaBridge	126:abea610beb85	996	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	997
AnnaBridge	126:abea610beb85	998	#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	999	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	1000	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
AnnaBridge	126:abea610beb85	1001	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	1002	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
AnnaBridge	126:abea610beb85	1003	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	1004	} while(0)
AnnaBridge	126:abea610beb85	1005
AnnaBridge	126:abea610beb85	1006	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	1007	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	1008	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
AnnaBridge	126:abea610beb85	1009	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	1010	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
AnnaBridge	126:abea610beb85	1011	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	1012	} while(0)
AnnaBridge	126:abea610beb85	1013
AnnaBridge	126:abea610beb85	1014	#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	1015	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	1016	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
AnnaBridge	126:abea610beb85	1017	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	1018	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
AnnaBridge	126:abea610beb85	1019	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	1020	} while(0)
AnnaBridge	126:abea610beb85	1021
AnnaBridge	126:abea610beb85	1022	#define __HAL_RCC_USART2_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	1023	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	1024	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
AnnaBridge	126:abea610beb85	1025	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	1026	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
AnnaBridge	126:abea610beb85	1027	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	1028	} while(0)
AnnaBridge	126:abea610beb85	1029
AnnaBridge	126:abea610beb85	1030	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	1031	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	1032	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
AnnaBridge	126:abea610beb85	1033	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	1034	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
AnnaBridge	126:abea610beb85	1035	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	1036	} while(0)
AnnaBridge	126:abea610beb85	1037
AnnaBridge	126:abea610beb85	1038	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	1039	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	1040	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
AnnaBridge	126:abea610beb85	1041	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	1042	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
AnnaBridge	126:abea610beb85	1043	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	1044	} while(0)
AnnaBridge	126:abea610beb85	1045
AnnaBridge	126:abea610beb85	1046	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	1047	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	1048	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
AnnaBridge	126:abea610beb85	1049	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	1050	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
AnnaBridge	126:abea610beb85	1051	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	1052	} while(0)
AnnaBridge	126:abea610beb85	1053
AnnaBridge	126:abea610beb85	1054	#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	1055	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	1056	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
AnnaBridge	126:abea610beb85	1057	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	1058	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
AnnaBridge	126:abea610beb85	1059	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	1060	} while(0)
AnnaBridge	126:abea610beb85	1061
AnnaBridge	126:abea610beb85	1062	#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	1063	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	1064	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
AnnaBridge	126:abea610beb85	1065	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	1066	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
AnnaBridge	126:abea610beb85	1067	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	1068	} while(0)
AnnaBridge	126:abea610beb85	1069
AnnaBridge	126:abea610beb85	1070	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	1071	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	1072	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
AnnaBridge	126:abea610beb85	1073	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	1074	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
AnnaBridge	126:abea610beb85	1075	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	1076	} while(0)
AnnaBridge	126:abea610beb85	1077
AnnaBridge	126:abea610beb85	1078	#define __HAL_RCC_I2C4_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	1079	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	1080	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\
AnnaBridge	126:abea610beb85	1081	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	1082	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\
AnnaBridge	126:abea610beb85	1083	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	1084	} while(0)
AnnaBridge	126:abea610beb85	1085
AnnaBridge	126:abea610beb85	1086	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	1087	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	1088	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
AnnaBridge	126:abea610beb85	1089	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	1090	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
AnnaBridge	126:abea610beb85	1091	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	1092	} while(0)
AnnaBridge	126:abea610beb85	1093
AnnaBridge	126:abea610beb85	1094	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	1095	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	1096	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
AnnaBridge	126:abea610beb85	1097	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	1098	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
AnnaBridge	126:abea610beb85	1099	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	1100	} while(0)
AnnaBridge	126:abea610beb85	1101
AnnaBridge	126:abea610beb85	1102	#define __HAL_RCC_CEC_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	1103	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	1104	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
AnnaBridge	126:abea610beb85	1105	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	1106	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
AnnaBridge	126:abea610beb85	1107	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	1108	} while(0)
AnnaBridge	126:abea610beb85	1109
AnnaBridge	126:abea610beb85	1110	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	1111	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	1112	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
AnnaBridge	126:abea610beb85	1113	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	1114	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
AnnaBridge	126:abea610beb85	1115	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	1116	} while(0)
AnnaBridge	126:abea610beb85	1117
AnnaBridge	126:abea610beb85	1118	#define __HAL_RCC_UART7_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	1119	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	1120	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
AnnaBridge	126:abea610beb85	1121	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	1122	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
AnnaBridge	126:abea610beb85	1123	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	1124	} while(0)
AnnaBridge	126:abea610beb85	1125
AnnaBridge	126:abea610beb85	1126	#define __HAL_RCC_UART8_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	1127	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	1128	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
AnnaBridge	126:abea610beb85	1129	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	1130	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
AnnaBridge	126:abea610beb85	1131	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	1132	} while(0)
AnnaBridge	126:abea610beb85	1133
AnnaBridge	126:abea610beb85	1134	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
AnnaBridge	126:abea610beb85	1135	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
AnnaBridge	126:abea610beb85	1136	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
AnnaBridge	126:abea610beb85	1137	#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
AnnaBridge	126:abea610beb85	1138	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
AnnaBridge	126:abea610beb85	1139	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
AnnaBridge	126:abea610beb85	1140	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
AnnaBridge	126:abea610beb85	1141	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
AnnaBridge	126:abea610beb85	1142	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
AnnaBridge	126:abea610beb85	1143	#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
AnnaBridge	126:abea610beb85	1144	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	1145	#define __HAL_RCC_RTC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCEN))
AnnaBridge	126:abea610beb85	1146	#define __HAL_RCC_CAN3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN))
AnnaBridge	126:abea610beb85	1147	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	1148	#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
AnnaBridge	126:abea610beb85	1149	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
AnnaBridge	126:abea610beb85	1150	#define __HAL_RCC_SPDIFRX_CLK_DISABLE()(RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))
AnnaBridge	126:abea610beb85	1151	#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
AnnaBridge	126:abea610beb85	1152	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
AnnaBridge	126:abea610beb85	1153	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
AnnaBridge	126:abea610beb85	1154	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
AnnaBridge	126:abea610beb85	1155	#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
AnnaBridge	126:abea610beb85	1156	#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
AnnaBridge	126:abea610beb85	1157	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
AnnaBridge	126:abea610beb85	1158	#define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C4EN))
AnnaBridge	126:abea610beb85	1159	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
AnnaBridge	126:abea610beb85	1160	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
AnnaBridge	126:abea610beb85	1161	#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
AnnaBridge	126:abea610beb85	1162	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
AnnaBridge	126:abea610beb85	1163	#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
AnnaBridge	126:abea610beb85	1164	#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
AnnaBridge	126:abea610beb85	1165
AnnaBridge	126:abea610beb85	1166	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
AnnaBridge	126:abea610beb85	1167	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	126:abea610beb85	1168	* is disabled and the application software has to enable this clock before
AnnaBridge	126:abea610beb85	1169	* using it.
AnnaBridge	126:abea610beb85	1170	*/
AnnaBridge	126:abea610beb85	1171	#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	1172	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	1173	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
AnnaBridge	126:abea610beb85	1174	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	1175	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
AnnaBridge	126:abea610beb85	1176	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	1177	} while(0)
AnnaBridge	126:abea610beb85	1178
AnnaBridge	126:abea610beb85	1179	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	1180	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	1181	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
AnnaBridge	126:abea610beb85	1182	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	1183	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
AnnaBridge	126:abea610beb85	1184	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	1185	} while(0)
AnnaBridge	126:abea610beb85	1186
AnnaBridge	126:abea610beb85	1187	#define __HAL_RCC_USART1_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	1188	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	1189	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
AnnaBridge	126:abea610beb85	1190	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	1191	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
AnnaBridge	126:abea610beb85	1192	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	1193	} while(0)
AnnaBridge	126:abea610beb85	1194
AnnaBridge	126:abea610beb85	1195	#define __HAL_RCC_USART6_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	1196	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	1197	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
AnnaBridge	126:abea610beb85	1198	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	1199	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
AnnaBridge	126:abea610beb85	1200	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	1201	} while(0)
AnnaBridge	126:abea610beb85	1202
AnnaBridge	126:abea610beb85	1203	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	1204	#define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	1205	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	1206	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\
AnnaBridge	126:abea610beb85	1207	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	1208	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\
AnnaBridge	126:abea610beb85	1209	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	1210	} while(0)
AnnaBridge	126:abea610beb85	1211	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	1212
AnnaBridge	126:abea610beb85	1213	#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	1214	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	1215	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
AnnaBridge	126:abea610beb85	1216	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	1217	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
AnnaBridge	126:abea610beb85	1218	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	1219	} while(0)
AnnaBridge	126:abea610beb85	1220
AnnaBridge	126:abea610beb85	1221	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	1222	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	1223	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
AnnaBridge	126:abea610beb85	1224	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	1225	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
AnnaBridge	126:abea610beb85	1226	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	1227	} while(0)
AnnaBridge	126:abea610beb85	1228
AnnaBridge	126:abea610beb85	1229	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	1230	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	1231	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
AnnaBridge	126:abea610beb85	1232	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	1233	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
AnnaBridge	126:abea610beb85	1234	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	1235	} while(0)
AnnaBridge	126:abea610beb85	1236
AnnaBridge	126:abea610beb85	1237	#define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	1238	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	1239	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\
AnnaBridge	126:abea610beb85	1240	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	1241	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\
AnnaBridge	126:abea610beb85	1242	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	1243	} while(0)
AnnaBridge	126:abea610beb85	1244
AnnaBridge	126:abea610beb85	1245	#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	1246	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	1247	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
AnnaBridge	126:abea610beb85	1248	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	1249	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
AnnaBridge	126:abea610beb85	1250	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	1251	} while(0)
AnnaBridge	126:abea610beb85	1252
AnnaBridge	126:abea610beb85	1253	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	1254	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	1255	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
AnnaBridge	126:abea610beb85	1256	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	1257	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
AnnaBridge	126:abea610beb85	1258	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	1259	} while(0)
AnnaBridge	126:abea610beb85	1260
AnnaBridge	126:abea610beb85	1261	#define __HAL_RCC_TIM9_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	1262	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	1263	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
AnnaBridge	126:abea610beb85	1264	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	1265	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
AnnaBridge	126:abea610beb85	1266	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	1267	} while(0)
AnnaBridge	126:abea610beb85	1268
AnnaBridge	126:abea610beb85	1269	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	1270	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	1271	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
AnnaBridge	126:abea610beb85	1272	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	1273	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
AnnaBridge	126:abea610beb85	1274	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	1275	} while(0)
AnnaBridge	126:abea610beb85	1276
AnnaBridge	126:abea610beb85	1277	#define __HAL_RCC_TIM11_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	1278	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	1279	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
AnnaBridge	126:abea610beb85	1280	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	1281	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
AnnaBridge	126:abea610beb85	1282	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	1283	} while(0)
AnnaBridge	126:abea610beb85	1284
AnnaBridge	126:abea610beb85	1285	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	1286	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	1287	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
AnnaBridge	126:abea610beb85	1288	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	1289	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
AnnaBridge	126:abea610beb85	1290	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	1291	} while(0)
AnnaBridge	126:abea610beb85	1292
AnnaBridge	126:abea610beb85	1293	#define __HAL_RCC_SPI6_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	1294	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	1295	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
AnnaBridge	126:abea610beb85	1296	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	1297	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
AnnaBridge	126:abea610beb85	1298	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	1299	} while(0)
AnnaBridge	126:abea610beb85	1300
AnnaBridge	126:abea610beb85	1301	#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	1302	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	1303	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
AnnaBridge	126:abea610beb85	1304	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	1305	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
AnnaBridge	126:abea610beb85	1306	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	1307	} while(0)
AnnaBridge	126:abea610beb85	1308
AnnaBridge	126:abea610beb85	1309	#define __HAL_RCC_SAI2_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	1310	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	1311	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
AnnaBridge	126:abea610beb85	1312	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	1313	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
AnnaBridge	126:abea610beb85	1314	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	1315	} while(0)
AnnaBridge	126:abea610beb85	1316
AnnaBridge	126:abea610beb85	1317	#if defined (STM32F746xx) \|\| defined (STM32F756xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	1318	#define __HAL_RCC_LTDC_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	1319	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	1320	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
AnnaBridge	126:abea610beb85	1321	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	1322	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
AnnaBridge	126:abea610beb85	1323	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	1324	} while(0)
AnnaBridge	126:abea610beb85	1325	#endif /* STM32F746xx \|\| STM32F756xx \|\| STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	1326
AnnaBridge	126:abea610beb85	1327	#if defined (STM32F769xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	1328	#define __HAL_RCC_DSI_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	1329	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	1330	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
AnnaBridge	126:abea610beb85	1331	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	1332	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
AnnaBridge	126:abea610beb85	1333	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	1334	} while(0)
AnnaBridge	126:abea610beb85	1335	#endif /* STM32F769xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	1336
AnnaBridge	126:abea610beb85	1337	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	1338	#define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	1339	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	1340	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
AnnaBridge	126:abea610beb85	1341	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	1342	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
AnnaBridge	126:abea610beb85	1343	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	1344	} while(0)
AnnaBridge	126:abea610beb85	1345
AnnaBridge	126:abea610beb85	1346	#define __HAL_RCC_MDIO_CLK_ENABLE() do { \
AnnaBridge	126:abea610beb85	1347	__IO uint32_t tmpreg; \
AnnaBridge	126:abea610beb85	1348	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\
AnnaBridge	126:abea610beb85	1349	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	126:abea610beb85	1350	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\
AnnaBridge	126:abea610beb85	1351	UNUSED(tmpreg); \
AnnaBridge	126:abea610beb85	1352	} while(0)
AnnaBridge	126:abea610beb85	1353	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	1354
AnnaBridge	126:abea610beb85	1355	#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
AnnaBridge	126:abea610beb85	1356	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
AnnaBridge	126:abea610beb85	1357	#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
AnnaBridge	126:abea610beb85	1358	#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
AnnaBridge	126:abea610beb85	1359	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	1360	#define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC2EN))
AnnaBridge	126:abea610beb85	1361	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	1362	#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
AnnaBridge	126:abea610beb85	1363	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
AnnaBridge	126:abea610beb85	1364	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
AnnaBridge	126:abea610beb85	1365	#define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC1EN))
AnnaBridge	126:abea610beb85	1366	#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
AnnaBridge	126:abea610beb85	1367	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
AnnaBridge	126:abea610beb85	1368	#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
AnnaBridge	126:abea610beb85	1369	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
AnnaBridge	126:abea610beb85	1370	#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
AnnaBridge	126:abea610beb85	1371	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
AnnaBridge	126:abea610beb85	1372	#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
AnnaBridge	126:abea610beb85	1373	#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
AnnaBridge	126:abea610beb85	1374	#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
AnnaBridge	126:abea610beb85	1375	#if defined (STM32F746xx) \|\| defined (STM32F756xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	1376	#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
AnnaBridge	126:abea610beb85	1377	#endif /* STM32F746xx \|\| STM32F756xx \|\| STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	1378	#if defined (STM32F769xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	1379	#define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN))
AnnaBridge	126:abea610beb85	1380	#endif /* STM32F769xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	1381	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	1382	#define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN))
AnnaBridge	126:abea610beb85	1383	#define __HAL_RCC_MDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_MDIOEN))
AnnaBridge	126:abea610beb85	1384	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	1385
AnnaBridge	126:abea610beb85	1386	/**
AnnaBridge	126:abea610beb85	1387	* @}
AnnaBridge	126:abea610beb85	1388	*/
AnnaBridge	126:abea610beb85	1389
AnnaBridge	126:abea610beb85	1390
AnnaBridge	126:abea610beb85	1391	/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status
AnnaBridge	126:abea610beb85	1392	* @brief Get the enable or disable status of the AHB/APB peripheral clock.
AnnaBridge	126:abea610beb85	1393	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	126:abea610beb85	1394	* is disabled and the application software has to enable this clock before
AnnaBridge	126:abea610beb85	1395	* using it.
AnnaBridge	126:abea610beb85	1396	* @{
AnnaBridge	126:abea610beb85	1397	*/
AnnaBridge	126:abea610beb85	1398
AnnaBridge	126:abea610beb85	1399	/** @brief Get the enable or disable status of the AHB1 peripheral clock.
AnnaBridge	126:abea610beb85	1400	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	126:abea610beb85	1401	* is disabled and the application software has to enable this clock before
AnnaBridge	126:abea610beb85	1402	* using it.
AnnaBridge	126:abea610beb85	1403	*/
AnnaBridge	126:abea610beb85	1404	#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
AnnaBridge	126:abea610beb85	1405	#define __HAL_RCC_DTCMRAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) != RESET)
AnnaBridge	126:abea610beb85	1406	#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) != RESET)
AnnaBridge	126:abea610beb85	1407	#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET)
AnnaBridge	126:abea610beb85	1408	#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
AnnaBridge	126:abea610beb85	1409	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
AnnaBridge	126:abea610beb85	1410	#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) != RESET)
AnnaBridge	126:abea610beb85	1411	#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) != RESET)
AnnaBridge	126:abea610beb85	1412	#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) != RESET)
AnnaBridge	126:abea610beb85	1413	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
AnnaBridge	126:abea610beb85	1414	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
AnnaBridge	126:abea610beb85	1415	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
AnnaBridge	126:abea610beb85	1416	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
AnnaBridge	126:abea610beb85	1417	#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) != RESET)
AnnaBridge	126:abea610beb85	1418	#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
AnnaBridge	126:abea610beb85	1419	#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET)
AnnaBridge	126:abea610beb85	1420	#define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET)
AnnaBridge	126:abea610beb85	1421
AnnaBridge	126:abea610beb85	1422	#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
AnnaBridge	126:abea610beb85	1423	#define __HAL_RCC_DTCMRAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) == RESET)
AnnaBridge	126:abea610beb85	1424	#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) == RESET)
AnnaBridge	126:abea610beb85	1425	#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET)
AnnaBridge	126:abea610beb85	1426	#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
AnnaBridge	126:abea610beb85	1427	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
AnnaBridge	126:abea610beb85	1428	#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) == RESET)
AnnaBridge	126:abea610beb85	1429	#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) == RESET)
AnnaBridge	126:abea610beb85	1430	#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) == RESET)
AnnaBridge	126:abea610beb85	1431	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
AnnaBridge	126:abea610beb85	1432	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
AnnaBridge	126:abea610beb85	1433	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
AnnaBridge	126:abea610beb85	1434	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
AnnaBridge	126:abea610beb85	1435	#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) == RESET)
AnnaBridge	126:abea610beb85	1436	#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
AnnaBridge	126:abea610beb85	1437	#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET)
AnnaBridge	126:abea610beb85	1438	#define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET)
AnnaBridge	126:abea610beb85	1439	/**
AnnaBridge	126:abea610beb85	1440	* @brief Enable ETHERNET clock.
AnnaBridge	126:abea610beb85	1441	*/
AnnaBridge	126:abea610beb85	1442	#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
AnnaBridge	126:abea610beb85	1443	#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
AnnaBridge	126:abea610beb85	1444	#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
AnnaBridge	126:abea610beb85	1445	#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
AnnaBridge	126:abea610beb85	1446	#define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \
AnnaBridge	126:abea610beb85	1447	__HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
AnnaBridge	126:abea610beb85	1448	__HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
AnnaBridge	126:abea610beb85	1449
AnnaBridge	126:abea610beb85	1450	/**
AnnaBridge	126:abea610beb85	1451	* @brief Disable ETHERNET clock.
AnnaBridge	126:abea610beb85	1452	*/
AnnaBridge	126:abea610beb85	1453	#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
AnnaBridge	126:abea610beb85	1454	#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
AnnaBridge	126:abea610beb85	1455	#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
AnnaBridge	126:abea610beb85	1456	#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
AnnaBridge	126:abea610beb85	1457	#define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \
AnnaBridge	126:abea610beb85	1458	__HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
AnnaBridge	126:abea610beb85	1459	__HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
AnnaBridge	126:abea610beb85	1460
AnnaBridge	126:abea610beb85	1461	/** @brief Get the enable or disable status of the AHB2 peripheral clock.
AnnaBridge	126:abea610beb85	1462	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	126:abea610beb85	1463	* is disabled and the application software has to enable this clock before
AnnaBridge	126:abea610beb85	1464	* using it.
AnnaBridge	126:abea610beb85	1465	*/
AnnaBridge	126:abea610beb85	1466	#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
AnnaBridge	126:abea610beb85	1467	#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
AnnaBridge	126:abea610beb85	1468	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
AnnaBridge	126:abea610beb85	1469
AnnaBridge	126:abea610beb85	1470	#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
AnnaBridge	126:abea610beb85	1471	#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
AnnaBridge	126:abea610beb85	1472	#define __HAL_RCC_USB_IS_OTG_FS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
AnnaBridge	126:abea610beb85	1473
AnnaBridge	126:abea610beb85	1474	#if defined(STM32F756xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	1475	#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)
AnnaBridge	126:abea610beb85	1476	#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)
AnnaBridge	126:abea610beb85	1477	#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)
AnnaBridge	126:abea610beb85	1478	#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)
AnnaBridge	126:abea610beb85	1479	#endif /* STM32F756xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	1480
AnnaBridge	126:abea610beb85	1481	#if defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	1482	#define __HAL_RCC_JPEG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) != RESET)
AnnaBridge	126:abea610beb85	1483	#define __HAL_RCC_JPEG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) == RESET)
AnnaBridge	126:abea610beb85	1484	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	1485
AnnaBridge	126:abea610beb85	1486	/** @brief Get the enable or disable status of the AHB3 peripheral clock.
AnnaBridge	126:abea610beb85	1487	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	126:abea610beb85	1488	* is disabled and the application software has to enable this clock before
AnnaBridge	126:abea610beb85	1489	* using it.
AnnaBridge	126:abea610beb85	1490	*/
AnnaBridge	126:abea610beb85	1491	#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
AnnaBridge	126:abea610beb85	1492	#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
AnnaBridge	126:abea610beb85	1493
AnnaBridge	126:abea610beb85	1494	#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
AnnaBridge	126:abea610beb85	1495	#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
AnnaBridge	126:abea610beb85	1496
AnnaBridge	126:abea610beb85	1497	/** @brief Get the enable or disable status of the APB1 peripheral clock.
AnnaBridge	126:abea610beb85	1498	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	126:abea610beb85	1499	* is disabled and the application software has to enable this clock before
AnnaBridge	126:abea610beb85	1500	* using it.
AnnaBridge	126:abea610beb85	1501	*/
AnnaBridge	126:abea610beb85	1502	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
AnnaBridge	126:abea610beb85	1503	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
AnnaBridge	126:abea610beb85	1504	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
AnnaBridge	126:abea610beb85	1505	#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
AnnaBridge	126:abea610beb85	1506	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
AnnaBridge	126:abea610beb85	1507	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
AnnaBridge	126:abea610beb85	1508	#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
AnnaBridge	126:abea610beb85	1509	#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
AnnaBridge	126:abea610beb85	1510	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
AnnaBridge	126:abea610beb85	1511	#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)
AnnaBridge	126:abea610beb85	1512	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	1513	#define __HAL_RCC_RTC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) != RESET)
AnnaBridge	126:abea610beb85	1514	#define __HAL_RCC_CAN3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET)
AnnaBridge	126:abea610beb85	1515	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	1516	#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
AnnaBridge	126:abea610beb85	1517	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
AnnaBridge	126:abea610beb85	1518	#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET)
AnnaBridge	126:abea610beb85	1519	#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
AnnaBridge	126:abea610beb85	1520	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
AnnaBridge	126:abea610beb85	1521	#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
AnnaBridge	126:abea610beb85	1522	#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
AnnaBridge	126:abea610beb85	1523	#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
AnnaBridge	126:abea610beb85	1524	#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
AnnaBridge	126:abea610beb85	1525	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
AnnaBridge	126:abea610beb85	1526	#define __HAL_RCC_I2C4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) != RESET)
AnnaBridge	126:abea610beb85	1527	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
AnnaBridge	126:abea610beb85	1528	#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
AnnaBridge	126:abea610beb85	1529	#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
AnnaBridge	126:abea610beb85	1530	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
AnnaBridge	126:abea610beb85	1531	#define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
AnnaBridge	126:abea610beb85	1532	#define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)
AnnaBridge	126:abea610beb85	1533
AnnaBridge	126:abea610beb85	1534	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
AnnaBridge	126:abea610beb85	1535	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
AnnaBridge	126:abea610beb85	1536	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
AnnaBridge	126:abea610beb85	1537	#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
AnnaBridge	126:abea610beb85	1538	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
AnnaBridge	126:abea610beb85	1539	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
AnnaBridge	126:abea610beb85	1540	#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
AnnaBridge	126:abea610beb85	1541	#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
AnnaBridge	126:abea610beb85	1542	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
AnnaBridge	126:abea610beb85	1543	#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)
AnnaBridge	126:abea610beb85	1544	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	1545	#define __HAL_RCC_RTC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) == RESET)
AnnaBridge	126:abea610beb85	1546	#define __HAL_RCC_CAN3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET)
AnnaBridge	126:abea610beb85	1547	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	1548	#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
AnnaBridge	126:abea610beb85	1549	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
AnnaBridge	126:abea610beb85	1550	#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED()((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET)
AnnaBridge	126:abea610beb85	1551	#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
AnnaBridge	126:abea610beb85	1552	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
AnnaBridge	126:abea610beb85	1553	#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
AnnaBridge	126:abea610beb85	1554	#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
AnnaBridge	126:abea610beb85	1555	#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
AnnaBridge	126:abea610beb85	1556	#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
AnnaBridge	126:abea610beb85	1557	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
AnnaBridge	126:abea610beb85	1558	#define __HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) == RESET)
AnnaBridge	126:abea610beb85	1559	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
AnnaBridge	126:abea610beb85	1560	#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
AnnaBridge	126:abea610beb85	1561	#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
AnnaBridge	126:abea610beb85	1562	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
AnnaBridge	126:abea610beb85	1563	#define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
AnnaBridge	126:abea610beb85	1564	#define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)
AnnaBridge	126:abea610beb85	1565
AnnaBridge	126:abea610beb85	1566	/** @brief Get the enable or disable status of the APB2 peripheral clock.
AnnaBridge	126:abea610beb85	1567	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	126:abea610beb85	1568	* is disabled and the application software has to enable this clock before
AnnaBridge	126:abea610beb85	1569	* using it.
AnnaBridge	126:abea610beb85	1570	*/
AnnaBridge	126:abea610beb85	1571	#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
AnnaBridge	126:abea610beb85	1572	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
AnnaBridge	126:abea610beb85	1573	#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
AnnaBridge	126:abea610beb85	1574	#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
AnnaBridge	126:abea610beb85	1575	#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
AnnaBridge	126:abea610beb85	1576	#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
AnnaBridge	126:abea610beb85	1577	#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
AnnaBridge	126:abea610beb85	1578	#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) != RESET)
AnnaBridge	126:abea610beb85	1579	#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
AnnaBridge	126:abea610beb85	1580	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
AnnaBridge	126:abea610beb85	1581	#define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
AnnaBridge	126:abea610beb85	1582	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
AnnaBridge	126:abea610beb85	1583	#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
AnnaBridge	126:abea610beb85	1584	#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
AnnaBridge	126:abea610beb85	1585	#define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET)
AnnaBridge	126:abea610beb85	1586	#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
AnnaBridge	126:abea610beb85	1587	#define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)
AnnaBridge	126:abea610beb85	1588	#if defined (STM32F746xx) \|\| defined (STM32F756xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	1589	#define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET)
AnnaBridge	126:abea610beb85	1590	#endif /* STM32F746xx \|\| STM32F756xx \|\| STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	1591	#if defined (STM32F769xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	1592	#define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET)
AnnaBridge	126:abea610beb85	1593	#endif /* STM32F769xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	1594	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	1595	#define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) != RESET)
AnnaBridge	126:abea610beb85	1596	#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET)
AnnaBridge	126:abea610beb85	1597	#define __HAL_RCC_MDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) != RESET)
AnnaBridge	126:abea610beb85	1598	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	1599	#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
AnnaBridge	126:abea610beb85	1600	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
AnnaBridge	126:abea610beb85	1601	#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
AnnaBridge	126:abea610beb85	1602	#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
AnnaBridge	126:abea610beb85	1603	#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
AnnaBridge	126:abea610beb85	1604	#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
AnnaBridge	126:abea610beb85	1605	#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
AnnaBridge	126:abea610beb85	1606	#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) == RESET)
AnnaBridge	126:abea610beb85	1607	#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
AnnaBridge	126:abea610beb85	1608	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
AnnaBridge	126:abea610beb85	1609	#define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
AnnaBridge	126:abea610beb85	1610	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
AnnaBridge	126:abea610beb85	1611	#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
AnnaBridge	126:abea610beb85	1612	#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
AnnaBridge	126:abea610beb85	1613	#define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)
AnnaBridge	126:abea610beb85	1614	#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
AnnaBridge	126:abea610beb85	1615	#define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET)
AnnaBridge	126:abea610beb85	1616	#if defined (STM32F746xx) \|\| defined (STM32F756xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	1617	#define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET)
AnnaBridge	126:abea610beb85	1618	#endif /* STM32F746xx \|\| STM32F756xx \|\| STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	1619	#if defined (STM32F769xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	1620	#define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET)
AnnaBridge	126:abea610beb85	1621	#endif /* STM32F769xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	1622	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	1623	#define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) == RESET)
AnnaBridge	126:abea610beb85	1624	#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET)
AnnaBridge	126:abea610beb85	1625	#define __HAL_RCC_MDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) == RESET)
AnnaBridge	126:abea610beb85	1626	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	1627	/**
AnnaBridge	126:abea610beb85	1628	* @}
AnnaBridge	126:abea610beb85	1629	*/
AnnaBridge	126:abea610beb85	1630
AnnaBridge	126:abea610beb85	1631	/** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset
AnnaBridge	126:abea610beb85	1632	* @brief Forces or releases AHB/APB peripheral reset.
AnnaBridge	126:abea610beb85	1633	* @{
AnnaBridge	126:abea610beb85	1634	*/
AnnaBridge	126:abea610beb85	1635
AnnaBridge	126:abea610beb85	1636	/** @brief Force or release AHB1 peripheral reset.
AnnaBridge	126:abea610beb85	1637	*/
AnnaBridge	126:abea610beb85	1638	#define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA2RST))
AnnaBridge	126:abea610beb85	1639	#define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA2DRST))
AnnaBridge	126:abea610beb85	1640	#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_ETHMACRST))
AnnaBridge	126:abea610beb85	1641	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
AnnaBridge	126:abea610beb85	1642	#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOARST))
AnnaBridge	126:abea610beb85	1643	#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOBRST))
AnnaBridge	126:abea610beb85	1644	#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOCRST))
AnnaBridge	126:abea610beb85	1645	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
AnnaBridge	126:abea610beb85	1646	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
AnnaBridge	126:abea610beb85	1647	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
AnnaBridge	126:abea610beb85	1648	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
AnnaBridge	126:abea610beb85	1649	#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOHRST))
AnnaBridge	126:abea610beb85	1650	#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOIRST))
AnnaBridge	126:abea610beb85	1651	#define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOJRST))
AnnaBridge	126:abea610beb85	1652	#define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOKRST))
AnnaBridge	126:abea610beb85	1653
AnnaBridge	126:abea610beb85	1654	#define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
AnnaBridge	126:abea610beb85	1655	#define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
AnnaBridge	126:abea610beb85	1656	#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
AnnaBridge	126:abea610beb85	1657	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
AnnaBridge	126:abea610beb85	1658	#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
AnnaBridge	126:abea610beb85	1659	#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
AnnaBridge	126:abea610beb85	1660	#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
AnnaBridge	126:abea610beb85	1661	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
AnnaBridge	126:abea610beb85	1662	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
AnnaBridge	126:abea610beb85	1663	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
AnnaBridge	126:abea610beb85	1664	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
AnnaBridge	126:abea610beb85	1665	#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
AnnaBridge	126:abea610beb85	1666	#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
AnnaBridge	126:abea610beb85	1667	#define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
AnnaBridge	126:abea610beb85	1668	#define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
AnnaBridge	126:abea610beb85	1669
AnnaBridge	126:abea610beb85	1670	/** @brief Force or release AHB2 peripheral reset.
AnnaBridge	126:abea610beb85	1671	*/
AnnaBridge	126:abea610beb85	1672	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
AnnaBridge	126:abea610beb85	1673	#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
AnnaBridge	126:abea610beb85	1674	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
AnnaBridge	126:abea610beb85	1675	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
AnnaBridge	126:abea610beb85	1676
AnnaBridge	126:abea610beb85	1677	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
AnnaBridge	126:abea610beb85	1678	#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
AnnaBridge	126:abea610beb85	1679	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
AnnaBridge	126:abea610beb85	1680	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
AnnaBridge	126:abea610beb85	1681
AnnaBridge	126:abea610beb85	1682	#if defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	1683	#define __HAL_RCC_JPEG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_JPEGRST))
AnnaBridge	126:abea610beb85	1684	#define __HAL_RCC_JPEG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_JPEGRST))
AnnaBridge	126:abea610beb85	1685	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	1686
AnnaBridge	126:abea610beb85	1687	#if defined(STM32F756xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	1688	#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_CRYPRST))
AnnaBridge	126:abea610beb85	1689	#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_HASHRST))
AnnaBridge	126:abea610beb85	1690	#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
AnnaBridge	126:abea610beb85	1691	#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
AnnaBridge	126:abea610beb85	1692	#endif /* STM32F756xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	1693
AnnaBridge	126:abea610beb85	1694	/** @brief Force or release AHB3 peripheral reset
AnnaBridge	126:abea610beb85	1695	*/
AnnaBridge	126:abea610beb85	1696	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
AnnaBridge	126:abea610beb85	1697	#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FMCRST))
AnnaBridge	126:abea610beb85	1698	#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_QSPIRST))
AnnaBridge	126:abea610beb85	1699
AnnaBridge	126:abea610beb85	1700	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
AnnaBridge	126:abea610beb85	1701	#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
AnnaBridge	126:abea610beb85	1702	#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
AnnaBridge	126:abea610beb85	1703
AnnaBridge	126:abea610beb85	1704	/** @brief Force or release APB1 peripheral reset.
AnnaBridge	126:abea610beb85	1705	*/
AnnaBridge	126:abea610beb85	1706	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
AnnaBridge	126:abea610beb85	1707	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
AnnaBridge	126:abea610beb85	1708	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
AnnaBridge	126:abea610beb85	1709	#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM5RST))
AnnaBridge	126:abea610beb85	1710	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
AnnaBridge	126:abea610beb85	1711	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
AnnaBridge	126:abea610beb85	1712	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
AnnaBridge	126:abea610beb85	1713	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
AnnaBridge	126:abea610beb85	1714	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
AnnaBridge	126:abea610beb85	1715	#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_LPTIM1RST))
AnnaBridge	126:abea610beb85	1716	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	1717	#define __HAL_RCC_CAN3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN3RST))
AnnaBridge	126:abea610beb85	1718	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	1719	#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
AnnaBridge	126:abea610beb85	1720	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
AnnaBridge	126:abea610beb85	1721	#define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPDIFRXRST))
AnnaBridge	126:abea610beb85	1722	#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
AnnaBridge	126:abea610beb85	1723	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
AnnaBridge	126:abea610beb85	1724	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
AnnaBridge	126:abea610beb85	1725	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
AnnaBridge	126:abea610beb85	1726	#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
AnnaBridge	126:abea610beb85	1727	#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
AnnaBridge	126:abea610beb85	1728	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
AnnaBridge	126:abea610beb85	1729	#define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C4RST))
AnnaBridge	126:abea610beb85	1730	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
AnnaBridge	126:abea610beb85	1731	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
AnnaBridge	126:abea610beb85	1732	#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CECRST))
AnnaBridge	126:abea610beb85	1733	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
AnnaBridge	126:abea610beb85	1734	#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART7RST))
AnnaBridge	126:abea610beb85	1735	#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART8RST))
AnnaBridge	126:abea610beb85	1736
AnnaBridge	126:abea610beb85	1737	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
AnnaBridge	126:abea610beb85	1738	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
AnnaBridge	126:abea610beb85	1739	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
AnnaBridge	126:abea610beb85	1740	#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
AnnaBridge	126:abea610beb85	1741	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
AnnaBridge	126:abea610beb85	1742	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
AnnaBridge	126:abea610beb85	1743	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
AnnaBridge	126:abea610beb85	1744	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
AnnaBridge	126:abea610beb85	1745	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
AnnaBridge	126:abea610beb85	1746	#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
AnnaBridge	126:abea610beb85	1747	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	1748	#define __HAL_RCC_CAN3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN3RST))
AnnaBridge	126:abea610beb85	1749	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	1750	#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
AnnaBridge	126:abea610beb85	1751	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
AnnaBridge	126:abea610beb85	1752	#define __HAL_RCC_SPDIFRX_RELEASE_RESET()(RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))
AnnaBridge	126:abea610beb85	1753	#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
AnnaBridge	126:abea610beb85	1754	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
AnnaBridge	126:abea610beb85	1755	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
AnnaBridge	126:abea610beb85	1756	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
AnnaBridge	126:abea610beb85	1757	#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
AnnaBridge	126:abea610beb85	1758	#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
AnnaBridge	126:abea610beb85	1759	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
AnnaBridge	126:abea610beb85	1760	#define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C4RST))
AnnaBridge	126:abea610beb85	1761	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
AnnaBridge	126:abea610beb85	1762	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
AnnaBridge	126:abea610beb85	1763	#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
AnnaBridge	126:abea610beb85	1764	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
AnnaBridge	126:abea610beb85	1765	#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
AnnaBridge	126:abea610beb85	1766	#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
AnnaBridge	126:abea610beb85	1767
AnnaBridge	126:abea610beb85	1768	/** @brief Force or release APB2 peripheral reset.
AnnaBridge	126:abea610beb85	1769	*/
AnnaBridge	126:abea610beb85	1770	#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM1RST))
AnnaBridge	126:abea610beb85	1771	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
AnnaBridge	126:abea610beb85	1772	#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART1RST))
AnnaBridge	126:abea610beb85	1773	#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART6RST))
AnnaBridge	126:abea610beb85	1774	#define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADCRST))
AnnaBridge	126:abea610beb85	1775	#define __HAL_RCC_SDMMC1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDMMC1RST))
AnnaBridge	126:abea610beb85	1776	#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
AnnaBridge	126:abea610beb85	1777	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
AnnaBridge	126:abea610beb85	1778	#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM9RST))
AnnaBridge	126:abea610beb85	1779	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
AnnaBridge	126:abea610beb85	1780	#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM11RST))
AnnaBridge	126:abea610beb85	1781	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
AnnaBridge	126:abea610beb85	1782	#define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI6RST))
AnnaBridge	126:abea610beb85	1783	#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI1RST))
AnnaBridge	126:abea610beb85	1784	#define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI2RST))
AnnaBridge	126:abea610beb85	1785	#if defined (STM32F746xx) \|\| defined (STM32F756xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	1786	#define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_LTDCRST))
AnnaBridge	126:abea610beb85	1787	#endif /* STM32F746xx \|\| STM32F756xx \|\| STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	1788
AnnaBridge	126:abea610beb85	1789	#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
AnnaBridge	126:abea610beb85	1790	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
AnnaBridge	126:abea610beb85	1791	#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
AnnaBridge	126:abea610beb85	1792	#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
AnnaBridge	126:abea610beb85	1793	#define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
AnnaBridge	126:abea610beb85	1794	#define __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC1RST))
AnnaBridge	126:abea610beb85	1795	#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
AnnaBridge	126:abea610beb85	1796	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
AnnaBridge	126:abea610beb85	1797	#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
AnnaBridge	126:abea610beb85	1798	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
AnnaBridge	126:abea610beb85	1799	#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
AnnaBridge	126:abea610beb85	1800	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
AnnaBridge	126:abea610beb85	1801	#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
AnnaBridge	126:abea610beb85	1802	#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
AnnaBridge	126:abea610beb85	1803	#define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))
AnnaBridge	126:abea610beb85	1804	#if defined (STM32F746xx) \|\| defined (STM32F756xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	1805	#define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
AnnaBridge	126:abea610beb85	1806	#endif /* STM32F746xx \|\| STM32F756xx \|\| STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	1807
AnnaBridge	126:abea610beb85	1808	#if defined (STM32F769xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	1809	#define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_DSIRST))
AnnaBridge	126:abea610beb85	1810	#define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST))
AnnaBridge	126:abea610beb85	1811	#endif /* STM32F769xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	1812
AnnaBridge	126:abea610beb85	1813	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	1814	#define __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDMMC2RST))
AnnaBridge	126:abea610beb85	1815	#define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_DFSDM1RST))
AnnaBridge	126:abea610beb85	1816	#define __HAL_RCC_MDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_MDIORST))
AnnaBridge	126:abea610beb85	1817
AnnaBridge	126:abea610beb85	1818	#define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC2RST))
AnnaBridge	126:abea610beb85	1819	#define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST))
AnnaBridge	126:abea610beb85	1820	#define __HAL_RCC_MDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_MDIORST))
AnnaBridge	126:abea610beb85	1821	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	1822	/**
AnnaBridge	126:abea610beb85	1823	* @}
AnnaBridge	126:abea610beb85	1824	*/
AnnaBridge	126:abea610beb85	1825
AnnaBridge	126:abea610beb85	1826	/** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable RCCEx Peripheral Clock Sleep Enable Disable
AnnaBridge	126:abea610beb85	1827	* @brief Enables or disables the AHB/APB peripheral clock during Low Power (Sleep) mode.
AnnaBridge	126:abea610beb85	1828	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	126:abea610beb85	1829	* power consumption.
AnnaBridge	126:abea610beb85	1830	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	126:abea610beb85	1831	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	126:abea610beb85	1832	* @{
AnnaBridge	126:abea610beb85	1833	*/
AnnaBridge	126:abea610beb85	1834
AnnaBridge	126:abea610beb85	1835	/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	126:abea610beb85	1836	*/
AnnaBridge	126:abea610beb85	1837	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
AnnaBridge	126:abea610beb85	1838	#define __HAL_RCC_AXI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_AXILPEN))
AnnaBridge	126:abea610beb85	1839	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
AnnaBridge	126:abea610beb85	1840	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
AnnaBridge	126:abea610beb85	1841	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_BKPSRAMLPEN))
AnnaBridge	126:abea610beb85	1842	#define __HAL_RCC_DTCM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DTCMLPEN))
AnnaBridge	126:abea610beb85	1843	#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA2LPEN))
AnnaBridge	126:abea610beb85	1844	#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA2DLPEN))
AnnaBridge	126:abea610beb85	1845	#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACLPEN))
AnnaBridge	126:abea610beb85	1846	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACTXLPEN))
AnnaBridge	126:abea610beb85	1847	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACRXLPEN))
AnnaBridge	126:abea610beb85	1848	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACPTPLPEN))
AnnaBridge	126:abea610beb85	1849	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
AnnaBridge	126:abea610beb85	1850	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
AnnaBridge	126:abea610beb85	1851	#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOALPEN))
AnnaBridge	126:abea610beb85	1852	#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOBLPEN))
AnnaBridge	126:abea610beb85	1853	#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOCLPEN))
AnnaBridge	126:abea610beb85	1854	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
AnnaBridge	126:abea610beb85	1855	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
AnnaBridge	126:abea610beb85	1856	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
AnnaBridge	126:abea610beb85	1857	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
AnnaBridge	126:abea610beb85	1858	#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOHLPEN))
AnnaBridge	126:abea610beb85	1859	#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOILPEN))
AnnaBridge	126:abea610beb85	1860	#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOJLPEN))
AnnaBridge	126:abea610beb85	1861	#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOKLPEN))
AnnaBridge	126:abea610beb85	1862
AnnaBridge	126:abea610beb85	1863	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
AnnaBridge	126:abea610beb85	1864	#define __HAL_RCC_AXI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_AXILPEN))
AnnaBridge	126:abea610beb85	1865	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
AnnaBridge	126:abea610beb85	1866	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
AnnaBridge	126:abea610beb85	1867	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
AnnaBridge	126:abea610beb85	1868	#define __HAL_RCC_DTCM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DTCMLPEN))
AnnaBridge	126:abea610beb85	1869	#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
AnnaBridge	126:abea610beb85	1870	#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
AnnaBridge	126:abea610beb85	1871	#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
AnnaBridge	126:abea610beb85	1872	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
AnnaBridge	126:abea610beb85	1873	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
AnnaBridge	126:abea610beb85	1874	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
AnnaBridge	126:abea610beb85	1875	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
AnnaBridge	126:abea610beb85	1876	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
AnnaBridge	126:abea610beb85	1877	#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
AnnaBridge	126:abea610beb85	1878	#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
AnnaBridge	126:abea610beb85	1879	#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
AnnaBridge	126:abea610beb85	1880	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
AnnaBridge	126:abea610beb85	1881	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
AnnaBridge	126:abea610beb85	1882	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
AnnaBridge	126:abea610beb85	1883	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
AnnaBridge	126:abea610beb85	1884	#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
AnnaBridge	126:abea610beb85	1885	#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
AnnaBridge	126:abea610beb85	1886	#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
AnnaBridge	126:abea610beb85	1887	#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
AnnaBridge	126:abea610beb85	1888
AnnaBridge	126:abea610beb85	1889	/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	126:abea610beb85	1890	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	126:abea610beb85	1891	* power consumption.
AnnaBridge	126:abea610beb85	1892	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	126:abea610beb85	1893	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	126:abea610beb85	1894	*/
AnnaBridge	126:abea610beb85	1895	#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
AnnaBridge	126:abea610beb85	1896	#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
AnnaBridge	126:abea610beb85	1897
AnnaBridge	126:abea610beb85	1898	#if defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	1899	#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_JPEGLPEN))
AnnaBridge	126:abea610beb85	1900	#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_JPEGLPEN))
AnnaBridge	126:abea610beb85	1901	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	1902
AnnaBridge	126:abea610beb85	1903	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
AnnaBridge	126:abea610beb85	1904	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
AnnaBridge	126:abea610beb85	1905
AnnaBridge	126:abea610beb85	1906	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
AnnaBridge	126:abea610beb85	1907	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
AnnaBridge	126:abea610beb85	1908
AnnaBridge	126:abea610beb85	1909	#if defined(STM32F756xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	1910	#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_CRYPLPEN))
AnnaBridge	126:abea610beb85	1911	#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_HASHLPEN))
AnnaBridge	126:abea610beb85	1912
AnnaBridge	126:abea610beb85	1913	#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
AnnaBridge	126:abea610beb85	1914	#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
AnnaBridge	126:abea610beb85	1915	#endif /* STM32F756xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	1916
AnnaBridge	126:abea610beb85	1917	/** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	126:abea610beb85	1918	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	126:abea610beb85	1919	* power consumption.
AnnaBridge	126:abea610beb85	1920	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	126:abea610beb85	1921	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	126:abea610beb85	1922	*/
AnnaBridge	126:abea610beb85	1923	#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FMCLPEN))
AnnaBridge	126:abea610beb85	1924	#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
AnnaBridge	126:abea610beb85	1925
AnnaBridge	126:abea610beb85	1926	#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_QSPILPEN))
AnnaBridge	126:abea610beb85	1927	#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
AnnaBridge	126:abea610beb85	1928
AnnaBridge	126:abea610beb85	1929	/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	126:abea610beb85	1930	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	126:abea610beb85	1931	* power consumption.
AnnaBridge	126:abea610beb85	1932	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	126:abea610beb85	1933	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	126:abea610beb85	1934	*/
AnnaBridge	126:abea610beb85	1935	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
AnnaBridge	126:abea610beb85	1936	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
AnnaBridge	126:abea610beb85	1937	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
AnnaBridge	126:abea610beb85	1938	#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM5LPEN))
AnnaBridge	126:abea610beb85	1939	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
AnnaBridge	126:abea610beb85	1940	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
AnnaBridge	126:abea610beb85	1941	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
AnnaBridge	126:abea610beb85	1942	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
AnnaBridge	126:abea610beb85	1943	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
AnnaBridge	126:abea610beb85	1944	#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_LPTIM1LPEN))
AnnaBridge	126:abea610beb85	1945	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	1946	#define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_RTCLPEN))
AnnaBridge	126:abea610beb85	1947	#define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN3LPEN))
AnnaBridge	126:abea610beb85	1948	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	1949	#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI2LPEN))
AnnaBridge	126:abea610beb85	1950	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
AnnaBridge	126:abea610beb85	1951	#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPDIFRXLPEN))
AnnaBridge	126:abea610beb85	1952	#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART2LPEN))
AnnaBridge	126:abea610beb85	1953	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
AnnaBridge	126:abea610beb85	1954	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
AnnaBridge	126:abea610beb85	1955	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
AnnaBridge	126:abea610beb85	1956	#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C1LPEN))
AnnaBridge	126:abea610beb85	1957	#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C2LPEN))
AnnaBridge	126:abea610beb85	1958	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
AnnaBridge	126:abea610beb85	1959	#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C4LPEN))
AnnaBridge	126:abea610beb85	1960	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
AnnaBridge	126:abea610beb85	1961	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
AnnaBridge	126:abea610beb85	1962	#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CECLPEN))
AnnaBridge	126:abea610beb85	1963	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
AnnaBridge	126:abea610beb85	1964	#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART7LPEN))
AnnaBridge	126:abea610beb85	1965	#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART8LPEN))
AnnaBridge	126:abea610beb85	1966
AnnaBridge	126:abea610beb85	1967	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
AnnaBridge	126:abea610beb85	1968	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
AnnaBridge	126:abea610beb85	1969	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
AnnaBridge	126:abea610beb85	1970	#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
AnnaBridge	126:abea610beb85	1971	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
AnnaBridge	126:abea610beb85	1972	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
AnnaBridge	126:abea610beb85	1973	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
AnnaBridge	126:abea610beb85	1974	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
AnnaBridge	126:abea610beb85	1975	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
AnnaBridge	126:abea610beb85	1976	#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
AnnaBridge	126:abea610beb85	1977	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	1978	#define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCLPEN))
AnnaBridge	126:abea610beb85	1979	#define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN))
AnnaBridge	126:abea610beb85	1980	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	1981	#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
AnnaBridge	126:abea610beb85	1982	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
AnnaBridge	126:abea610beb85	1983	#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))
AnnaBridge	126:abea610beb85	1984	#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
AnnaBridge	126:abea610beb85	1985	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
AnnaBridge	126:abea610beb85	1986	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
AnnaBridge	126:abea610beb85	1987	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
AnnaBridge	126:abea610beb85	1988	#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
AnnaBridge	126:abea610beb85	1989	#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
AnnaBridge	126:abea610beb85	1990	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
AnnaBridge	126:abea610beb85	1991	#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C4LPEN))
AnnaBridge	126:abea610beb85	1992	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
AnnaBridge	126:abea610beb85	1993	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
AnnaBridge	126:abea610beb85	1994	#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))
AnnaBridge	126:abea610beb85	1995	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
AnnaBridge	126:abea610beb85	1996	#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
AnnaBridge	126:abea610beb85	1997	#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
AnnaBridge	126:abea610beb85	1998
AnnaBridge	126:abea610beb85	1999	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	126:abea610beb85	2000	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	126:abea610beb85	2001	* power consumption.
AnnaBridge	126:abea610beb85	2002	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	126:abea610beb85	2003	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	126:abea610beb85	2004	*/
AnnaBridge	126:abea610beb85	2005	#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM1LPEN))
AnnaBridge	126:abea610beb85	2006	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
AnnaBridge	126:abea610beb85	2007	#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_USART1LPEN))
AnnaBridge	126:abea610beb85	2008	#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_USART6LPEN))
AnnaBridge	126:abea610beb85	2009	#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC1LPEN))
AnnaBridge	126:abea610beb85	2010	#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
AnnaBridge	126:abea610beb85	2011	#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
AnnaBridge	126:abea610beb85	2012	#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDMMC1LPEN))
AnnaBridge	126:abea610beb85	2013	#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI1LPEN))
AnnaBridge	126:abea610beb85	2014	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
AnnaBridge	126:abea610beb85	2015	#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM9LPEN))
AnnaBridge	126:abea610beb85	2016	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
AnnaBridge	126:abea610beb85	2017	#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM11LPEN))
AnnaBridge	126:abea610beb85	2018	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
AnnaBridge	126:abea610beb85	2019	#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI6LPEN))
AnnaBridge	126:abea610beb85	2020	#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI1LPEN))
AnnaBridge	126:abea610beb85	2021	#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI2LPEN))
AnnaBridge	126:abea610beb85	2022	#if defined (STM32F746xx) \|\| defined (STM32F756xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	2023	#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_LTDCLPEN))
AnnaBridge	126:abea610beb85	2024	#endif /* STM32F746xx \|\| STM32F756xx \|\| STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	2025
AnnaBridge	126:abea610beb85	2026	#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
AnnaBridge	126:abea610beb85	2027	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
AnnaBridge	126:abea610beb85	2028	#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
AnnaBridge	126:abea610beb85	2029	#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
AnnaBridge	126:abea610beb85	2030	#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
AnnaBridge	126:abea610beb85	2031	#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
AnnaBridge	126:abea610beb85	2032	#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
AnnaBridge	126:abea610beb85	2033	#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC1LPEN))
AnnaBridge	126:abea610beb85	2034	#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
AnnaBridge	126:abea610beb85	2035	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
AnnaBridge	126:abea610beb85	2036	#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
AnnaBridge	126:abea610beb85	2037	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
AnnaBridge	126:abea610beb85	2038	#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
AnnaBridge	126:abea610beb85	2039	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
AnnaBridge	126:abea610beb85	2040	#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
AnnaBridge	126:abea610beb85	2041	#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
AnnaBridge	126:abea610beb85	2042	#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))
AnnaBridge	126:abea610beb85	2043	#if defined (STM32F746xx) \|\| defined (STM32F756xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	2044	#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
AnnaBridge	126:abea610beb85	2045	#endif /* STM32F746xx \|\| STM32F756xx \|\| STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	2046	#if defined (STM32F769xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	2047	#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_DSILPEN))
AnnaBridge	126:abea610beb85	2048	#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN))
AnnaBridge	126:abea610beb85	2049	#endif /* STM32F769xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	2050	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	2051	#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDMMC2LPEN))
AnnaBridge	126:abea610beb85	2052	#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_DFSDM1LPEN))
AnnaBridge	126:abea610beb85	2053	#define __HAL_RCC_MDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_MDIOLPEN))
AnnaBridge	126:abea610beb85	2054
AnnaBridge	126:abea610beb85	2055	#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC2LPEN))
AnnaBridge	126:abea610beb85	2056	#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN))
AnnaBridge	126:abea610beb85	2057	#define __HAL_RCC_MDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_MDIOLPEN))
AnnaBridge	126:abea610beb85	2058	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	2059	/**
AnnaBridge	126:abea610beb85	2060	* @}
AnnaBridge	126:abea610beb85	2061	*/
AnnaBridge	126:abea610beb85	2062
AnnaBridge	126:abea610beb85	2063	/** @defgroup RCC_Clock_Sleep_Enable_Disable_Status AHB/APB Peripheral Clock Sleep Enable Disable Status
AnnaBridge	126:abea610beb85	2064	* @brief Get the enable or disable status of the AHB/APB peripheral clock during Low Power (Sleep) mode.
AnnaBridge	126:abea610beb85	2065	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	126:abea610beb85	2066	* power consumption.
AnnaBridge	126:abea610beb85	2067	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	126:abea610beb85	2068	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	126:abea610beb85	2069	* @{
AnnaBridge	126:abea610beb85	2070	*/
AnnaBridge	126:abea610beb85	2071
AnnaBridge	126:abea610beb85	2072	/** @brief Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	126:abea610beb85	2073	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	126:abea610beb85	2074	* power consumption.
AnnaBridge	126:abea610beb85	2075	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	126:abea610beb85	2076	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	126:abea610beb85	2077	*/
AnnaBridge	126:abea610beb85	2078	#define __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) != RESET)
AnnaBridge	126:abea610beb85	2079	#define __HAL_RCC_AXI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) != RESET)
AnnaBridge	126:abea610beb85	2080	#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) != RESET)
AnnaBridge	126:abea610beb85	2081	#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) != RESET)
AnnaBridge	126:abea610beb85	2082	#define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) != RESET)
AnnaBridge	126:abea610beb85	2083	#define __HAL_RCC_DTCM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) != RESET)
AnnaBridge	126:abea610beb85	2084	#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != RESET)
AnnaBridge	126:abea610beb85	2085	#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) != RESET)
AnnaBridge	126:abea610beb85	2086	#define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) != RESET)
AnnaBridge	126:abea610beb85	2087	#define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) != RESET)
AnnaBridge	126:abea610beb85	2088	#define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) != RESET)
AnnaBridge	126:abea610beb85	2089	#define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) != RESET)
AnnaBridge	126:abea610beb85	2090	#define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) != RESET)
AnnaBridge	126:abea610beb85	2091	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) != RESET)
AnnaBridge	126:abea610beb85	2092	#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) != RESET)
AnnaBridge	126:abea610beb85	2093	#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) != RESET)
AnnaBridge	126:abea610beb85	2094	#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) != RESET)
AnnaBridge	126:abea610beb85	2095	#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) != RESET)
AnnaBridge	126:abea610beb85	2096	#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) != RESET)
AnnaBridge	126:abea610beb85	2097	#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) != RESET)
AnnaBridge	126:abea610beb85	2098	#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) != RESET)
AnnaBridge	126:abea610beb85	2099	#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) != RESET)
AnnaBridge	126:abea610beb85	2100	#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) != RESET)
AnnaBridge	126:abea610beb85	2101	#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) != RESET)
AnnaBridge	126:abea610beb85	2102	#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) != RESET)
AnnaBridge	126:abea610beb85	2103
AnnaBridge	126:abea610beb85	2104	#define __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) == RESET)
AnnaBridge	126:abea610beb85	2105	#define __HAL_RCC_AXI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) == RESET)
AnnaBridge	126:abea610beb85	2106	#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) == RESET)
AnnaBridge	126:abea610beb85	2107	#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) == RESET)
AnnaBridge	126:abea610beb85	2108	#define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) == RESET)
AnnaBridge	126:abea610beb85	2109	#define __HAL_RCC_DTCM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) == RESET)
AnnaBridge	126:abea610beb85	2110	#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == RESET)
AnnaBridge	126:abea610beb85	2111	#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) == RESET)
AnnaBridge	126:abea610beb85	2112	#define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) == RESET)
AnnaBridge	126:abea610beb85	2113	#define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) == RESET)
AnnaBridge	126:abea610beb85	2114	#define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) == RESET)
AnnaBridge	126:abea610beb85	2115	#define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) == RESET)
AnnaBridge	126:abea610beb85	2116	#define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) == RESET)
AnnaBridge	126:abea610beb85	2117	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) == RESET)
AnnaBridge	126:abea610beb85	2118	#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) == RESET)
AnnaBridge	126:abea610beb85	2119	#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) == RESET)
AnnaBridge	126:abea610beb85	2120	#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) == RESET)
AnnaBridge	126:abea610beb85	2121	#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) == RESET)
AnnaBridge	126:abea610beb85	2122	#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) == RESET)
AnnaBridge	126:abea610beb85	2123	#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) == RESET)
AnnaBridge	126:abea610beb85	2124	#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) == RESET)
AnnaBridge	126:abea610beb85	2125	#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) == RESET)
AnnaBridge	126:abea610beb85	2126	#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) == RESET)
AnnaBridge	126:abea610beb85	2127	#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) == RESET)
AnnaBridge	126:abea610beb85	2128	#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) == RESET)
AnnaBridge	126:abea610beb85	2129
AnnaBridge	126:abea610beb85	2130	/** @brief Get the enable or disable status of the AHB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	126:abea610beb85	2131	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	126:abea610beb85	2132	* power consumption.
AnnaBridge	126:abea610beb85	2133	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	126:abea610beb85	2134	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	126:abea610beb85	2135	*/
AnnaBridge	126:abea610beb85	2136	#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != RESET)
AnnaBridge	126:abea610beb85	2137	#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == RESET)
AnnaBridge	126:abea610beb85	2138
AnnaBridge	126:abea610beb85	2139	#if defined(STM32F767xx) \|\| defined(STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	2140	#define __HAL_RCC_JPEG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) != RESET)
AnnaBridge	126:abea610beb85	2141	#define __HAL_RCC_JPEG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) == RESET)
AnnaBridge	126:abea610beb85	2142	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	2143
AnnaBridge	126:abea610beb85	2144	#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != RESET)
AnnaBridge	126:abea610beb85	2145	#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == RESET)
AnnaBridge	126:abea610beb85	2146
AnnaBridge	126:abea610beb85	2147	#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) != RESET)
AnnaBridge	126:abea610beb85	2148	#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) == RESET)
AnnaBridge	126:abea610beb85	2149
AnnaBridge	126:abea610beb85	2150	#if defined(STM32F756xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	2151	#define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != RESET)
AnnaBridge	126:abea610beb85	2152	#define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != RESET)
AnnaBridge	126:abea610beb85	2153
AnnaBridge	126:abea610beb85	2154	#define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == RESET)
AnnaBridge	126:abea610beb85	2155	#define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == RESET)
AnnaBridge	126:abea610beb85	2156	#endif /* STM32F756xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	2157
AnnaBridge	126:abea610beb85	2158	/** @brief Get the enable or disable status of the AHB3 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	126:abea610beb85	2159	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	126:abea610beb85	2160	* power consumption.
AnnaBridge	126:abea610beb85	2161	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	126:abea610beb85	2162	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	126:abea610beb85	2163	*/
AnnaBridge	126:abea610beb85	2164	#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) != RESET)
AnnaBridge	126:abea610beb85	2165	#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) == RESET)
AnnaBridge	126:abea610beb85	2166
AnnaBridge	126:abea610beb85	2167	#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) != RESET)
AnnaBridge	126:abea610beb85	2168	#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) == RESET)
AnnaBridge	126:abea610beb85	2169
AnnaBridge	126:abea610beb85	2170	/** @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	126:abea610beb85	2171	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	126:abea610beb85	2172	* power consumption.
AnnaBridge	126:abea610beb85	2173	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	126:abea610beb85	2174	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	126:abea610beb85	2175	*/
AnnaBridge	126:abea610beb85	2176	#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != RESET)
AnnaBridge	126:abea610beb85	2177	#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != RESET)
AnnaBridge	126:abea610beb85	2178	#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != RESET)
AnnaBridge	126:abea610beb85	2179	#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != RESET)
AnnaBridge	126:abea610beb85	2180	#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) != RESET)
AnnaBridge	126:abea610beb85	2181	#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) != RESET)
AnnaBridge	126:abea610beb85	2182	#define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) != RESET)
AnnaBridge	126:abea610beb85	2183	#define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) != RESET)
AnnaBridge	126:abea610beb85	2184	#define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) != RESET)
AnnaBridge	126:abea610beb85	2185	#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) != RESET)
AnnaBridge	126:abea610beb85	2186	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	2187	#define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) != RESET)
AnnaBridge	126:abea610beb85	2188	#define __HAL_RCC_CAN3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) != RESET)
AnnaBridge	126:abea610beb85	2189	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	2190	#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != RESET)
AnnaBridge	126:abea610beb85	2191	#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != RESET)
AnnaBridge	126:abea610beb85	2192	#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) != RESET)
AnnaBridge	126:abea610beb85	2193	#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != RESET)
AnnaBridge	126:abea610beb85	2194	#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) != RESET)
AnnaBridge	126:abea610beb85	2195	#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != RESET)
AnnaBridge	126:abea610beb85	2196	#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != RESET)
AnnaBridge	126:abea610beb85	2197	#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) != RESET)
AnnaBridge	126:abea610beb85	2198	#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) != RESET)
AnnaBridge	126:abea610beb85	2199	#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) != RESET)
AnnaBridge	126:abea610beb85	2200	#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) != RESET)
AnnaBridge	126:abea610beb85	2201	#define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) != RESET)
AnnaBridge	126:abea610beb85	2202	#define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) != RESET)
AnnaBridge	126:abea610beb85	2203	#define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) != RESET)
AnnaBridge	126:abea610beb85	2204	#define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) != RESET)
AnnaBridge	126:abea610beb85	2205	#define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) != RESET)
AnnaBridge	126:abea610beb85	2206	#define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) != RESET)
AnnaBridge	126:abea610beb85	2207
AnnaBridge	126:abea610beb85	2208	#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) == RESET)
AnnaBridge	126:abea610beb85	2209	#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) == RESET)
AnnaBridge	126:abea610beb85	2210	#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) == RESET)
AnnaBridge	126:abea610beb85	2211	#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == RESET)
AnnaBridge	126:abea610beb85	2212	#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) == RESET)
AnnaBridge	126:abea610beb85	2213	#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) == RESET)
AnnaBridge	126:abea610beb85	2214	#define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) == RESET)
AnnaBridge	126:abea610beb85	2215	#define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) == RESET)
AnnaBridge	126:abea610beb85	2216	#define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) == RESET)
AnnaBridge	126:abea610beb85	2217	#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) == RESET)
AnnaBridge	126:abea610beb85	2218	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	2219	#define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) == RESET)
AnnaBridge	126:abea610beb85	2220	#define __HAL_RCC_CAN3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) == RESET)
AnnaBridge	126:abea610beb85	2221	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	2222	#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == RESET)
AnnaBridge	126:abea610beb85	2223	#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == RESET)
AnnaBridge	126:abea610beb85	2224	#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED()((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) == RESET)
AnnaBridge	126:abea610beb85	2225	#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == RESET)
AnnaBridge	126:abea610beb85	2226	#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) == RESET)
AnnaBridge	126:abea610beb85	2227	#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == RESET)
AnnaBridge	126:abea610beb85	2228	#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == RESET)
AnnaBridge	126:abea610beb85	2229	#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) == RESET)
AnnaBridge	126:abea610beb85	2230	#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) == RESET)
AnnaBridge	126:abea610beb85	2231	#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) == RESET)
AnnaBridge	126:abea610beb85	2232	#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) == RESET)
AnnaBridge	126:abea610beb85	2233	#define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) == RESET)
AnnaBridge	126:abea610beb85	2234	#define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) == RESET)
AnnaBridge	126:abea610beb85	2235	#define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) == RESET)
AnnaBridge	126:abea610beb85	2236	#define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) == RESET)
AnnaBridge	126:abea610beb85	2237	#define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) == RESET)
AnnaBridge	126:abea610beb85	2238	#define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) == RESET)
AnnaBridge	126:abea610beb85	2239
AnnaBridge	126:abea610beb85	2240	/** @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	126:abea610beb85	2241	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	126:abea610beb85	2242	* power consumption.
AnnaBridge	126:abea610beb85	2243	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	126:abea610beb85	2244	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	126:abea610beb85	2245	*/
AnnaBridge	126:abea610beb85	2246	#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != RESET)
AnnaBridge	126:abea610beb85	2247	#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != RESET)
AnnaBridge	126:abea610beb85	2248	#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != RESET)
AnnaBridge	126:abea610beb85	2249	#define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != RESET)
AnnaBridge	126:abea610beb85	2250	#define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) != RESET)
AnnaBridge	126:abea610beb85	2251	#define __HAL_RCC_ADC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) != RESET)
AnnaBridge	126:abea610beb85	2252	#define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) != RESET)
AnnaBridge	126:abea610beb85	2253	#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) != RESET)
AnnaBridge	126:abea610beb85	2254	#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != RESET)
AnnaBridge	126:abea610beb85	2255	#define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != RESET)
AnnaBridge	126:abea610beb85	2256	#define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) != RESET)
AnnaBridge	126:abea610beb85	2257	#define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) != RESET)
AnnaBridge	126:abea610beb85	2258	#define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) != RESET)
AnnaBridge	126:abea610beb85	2259	#define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != RESET)
AnnaBridge	126:abea610beb85	2260	#define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET)
AnnaBridge	126:abea610beb85	2261	#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != RESET)
AnnaBridge	126:abea610beb85	2262	#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != RESET)
AnnaBridge	126:abea610beb85	2263	#if defined (STM32F746xx) \|\| defined (STM32F756xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	2264	#define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) != RESET)
AnnaBridge	126:abea610beb85	2265	#endif /* STM32F746xx \|\| STM32F756xx \|\| STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	2266	#if defined (STM32F769xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	2267	#define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) != RESET)
AnnaBridge	126:abea610beb85	2268	#endif /* STM32F769xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	2269	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	2270	#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) != RESET)
AnnaBridge	126:abea610beb85	2271	#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != RESET)
AnnaBridge	126:abea610beb85	2272	#define __HAL_RCC_MDIO_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) != RESET)
AnnaBridge	126:abea610beb85	2273	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	2274
AnnaBridge	126:abea610beb85	2275	#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == RESET)
AnnaBridge	126:abea610beb85	2276	#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == RESET)
AnnaBridge	126:abea610beb85	2277	#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == RESET)
AnnaBridge	126:abea610beb85	2278	#define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == RESET)
AnnaBridge	126:abea610beb85	2279	#define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) == RESET)
AnnaBridge	126:abea610beb85	2280	#define __HAL_RCC_ADC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) == RESET)
AnnaBridge	126:abea610beb85	2281	#define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) == RESET)
AnnaBridge	126:abea610beb85	2282	#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) == RESET)
AnnaBridge	126:abea610beb85	2283	#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == RESET)
AnnaBridge	126:abea610beb85	2284	#define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == RESET)
AnnaBridge	126:abea610beb85	2285	#define __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) == RESET)
AnnaBridge	126:abea610beb85	2286	#define __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) == RESET)
AnnaBridge	126:abea610beb85	2287	#define __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) == RESET)
AnnaBridge	126:abea610beb85	2288	#define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == RESET)
AnnaBridge	126:abea610beb85	2289	#define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET)
AnnaBridge	126:abea610beb85	2290	#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == RESET)
AnnaBridge	126:abea610beb85	2291	#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == RESET)
AnnaBridge	126:abea610beb85	2292	#if defined (STM32F746xx) \|\| defined (STM32F756xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	2293	#define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) == RESET)
AnnaBridge	126:abea610beb85	2294	#endif /* STM32F746xx \|\| STM32F756xx \|\| STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	2295	#if defined (STM32F769xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	2296	#define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) == RESET)
AnnaBridge	126:abea610beb85	2297	#endif /* STM32F769xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	2298	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	2299	#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) == RESET)
AnnaBridge	126:abea610beb85	2300	#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == RESET)
AnnaBridge	126:abea610beb85	2301	#define __HAL_RCC_MDIO_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) == RESET)
AnnaBridge	126:abea610beb85	2302	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	2303	/**
AnnaBridge	126:abea610beb85	2304	* @}
AnnaBridge	126:abea610beb85	2305	*/
AnnaBridge	126:abea610beb85	2306
AnnaBridge	126:abea610beb85	2307	/------------------------------- PLL Configuration --------------------------/
AnnaBridge	126:abea610beb85	2308	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	2309	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
AnnaBridge	126:abea610beb85	2310	* @note This function must be used only when the main PLL is disabled.
AnnaBridge	126:abea610beb85	2311	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
AnnaBridge	126:abea610beb85	2312	* This parameter can be one of the following values:
AnnaBridge	126:abea610beb85	2313	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
AnnaBridge	126:abea610beb85	2314	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
AnnaBridge	126:abea610beb85	2315	* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
AnnaBridge	126:abea610beb85	2316	* @param __PLLM__: specifies the division factor for PLL VCO input clock
AnnaBridge	126:abea610beb85	2317	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
AnnaBridge	126:abea610beb85	2318	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
AnnaBridge	126:abea610beb85	2319	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
AnnaBridge	126:abea610beb85	2320	* of 2 MHz to limit PLL jitter.
AnnaBridge	126:abea610beb85	2321	* @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
AnnaBridge	126:abea610beb85	2322	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
AnnaBridge	126:abea610beb85	2323	* @note You have to set the PLLN parameter correctly to ensure that the VCO
AnnaBridge	126:abea610beb85	2324	* output frequency is between 100 and 432 MHz.
AnnaBridge	126:abea610beb85	2325	* @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
AnnaBridge	126:abea610beb85	2326	* This parameter must be a number in the range {2, 4, 6, or 8}.
AnnaBridge	126:abea610beb85	2327	* @note You have to set the PLLP parameter correctly to not exceed 216 MHz on
AnnaBridge	126:abea610beb85	2328	* the System clock frequency.
AnnaBridge	126:abea610beb85	2329	* @param __PLLQ__: specifies the division factor for OTG FS, SDMMC and RNG clocks
AnnaBridge	126:abea610beb85	2330	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
AnnaBridge	126:abea610beb85	2331	* @note If the USB OTG FS is used in your application, you have to set the
AnnaBridge	126:abea610beb85	2332	* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
AnnaBridge	126:abea610beb85	2333	* the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work
AnnaBridge	126:abea610beb85	2334	* correctly.
AnnaBridge	126:abea610beb85	2335	* @param __PLLR__: specifies the division factor for DSI clock
AnnaBridge	126:abea610beb85	2336	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
AnnaBridge	126:abea610beb85	2337	*/
AnnaBridge	126:abea610beb85	2338	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \
AnnaBridge	126:abea610beb85	2339	(RCC->PLLCFGR = ((__RCC_PLLSource__) \| (__PLLM__) \| \
AnnaBridge	126:abea610beb85	2340	((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) \| \
AnnaBridge	126:abea610beb85	2341	((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) \| \
AnnaBridge	126:abea610beb85	2342	((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ)) \| \
AnnaBridge	126:abea610beb85	2343	((__PLLR__) << POSITION_VAL(RCC_PLLCFGR_PLLR))))
AnnaBridge	126:abea610beb85	2344	#else
AnnaBridge	126:abea610beb85	2345	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
AnnaBridge	126:abea610beb85	2346	* @note This function must be used only when the main PLL is disabled.
AnnaBridge	126:abea610beb85	2347	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
AnnaBridge	126:abea610beb85	2348	* This parameter can be one of the following values:
AnnaBridge	126:abea610beb85	2349	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
AnnaBridge	126:abea610beb85	2350	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
AnnaBridge	126:abea610beb85	2351	* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
AnnaBridge	126:abea610beb85	2352	* @param __PLLM__: specifies the division factor for PLL VCO input clock
AnnaBridge	126:abea610beb85	2353	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
AnnaBridge	126:abea610beb85	2354	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
AnnaBridge	126:abea610beb85	2355	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
AnnaBridge	126:abea610beb85	2356	* of 2 MHz to limit PLL jitter.
AnnaBridge	126:abea610beb85	2357	* @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
AnnaBridge	126:abea610beb85	2358	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
AnnaBridge	126:abea610beb85	2359	* @note You have to set the PLLN parameter correctly to ensure that the VCO
AnnaBridge	126:abea610beb85	2360	* output frequency is between 100 and 432 MHz.
AnnaBridge	126:abea610beb85	2361	* @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
AnnaBridge	126:abea610beb85	2362	* This parameter must be a number in the range {2, 4, 6, or 8}.
AnnaBridge	126:abea610beb85	2363	* @note You have to set the PLLP parameter correctly to not exceed 216 MHz on
AnnaBridge	126:abea610beb85	2364	* the System clock frequency.
AnnaBridge	126:abea610beb85	2365	* @param __PLLQ__: specifies the division factor for OTG FS, SDMMC and RNG clocks
AnnaBridge	126:abea610beb85	2366	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
AnnaBridge	126:abea610beb85	2367	* @note If the USB OTG FS is used in your application, you have to set the
AnnaBridge	126:abea610beb85	2368	* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
AnnaBridge	126:abea610beb85	2369	* the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work
AnnaBridge	126:abea610beb85	2370	* correctly.
AnnaBridge	126:abea610beb85	2371	*/
AnnaBridge	126:abea610beb85	2372	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \
AnnaBridge	126:abea610beb85	2373	(RCC->PLLCFGR = (0x20000000 \| (__RCC_PLLSource__) \| (__PLLM__)\| \
AnnaBridge	126:abea610beb85	2374	((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) \| \
AnnaBridge	126:abea610beb85	2375	((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) \| \
AnnaBridge	126:abea610beb85	2376	((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
AnnaBridge	126:abea610beb85	2377	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	2378	/---------------------------------------------------------------------------------------------/
AnnaBridge	126:abea610beb85	2379
AnnaBridge	126:abea610beb85	2380	/** @brief Macro to configure the Timers clocks prescalers
AnnaBridge	126:abea610beb85	2381	* @param __PRESC__ : specifies the Timers clocks prescalers selection
AnnaBridge	126:abea610beb85	2382	* This parameter can be one of the following values:
AnnaBridge	126:abea610beb85	2383	* @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
AnnaBridge	126:abea610beb85	2384	* equal to HPRE if PPREx is corresponding to division by 1 or 2,
AnnaBridge	126:abea610beb85	2385	* else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
AnnaBridge	126:abea610beb85	2386	* division by 4 or more.
AnnaBridge	126:abea610beb85	2387	* @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
AnnaBridge	126:abea610beb85	2388	* equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
AnnaBridge	126:abea610beb85	2389	* else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
AnnaBridge	126:abea610beb85	2390	* to division by 8 or more.
AnnaBridge	126:abea610beb85	2391	*/
AnnaBridge	126:abea610beb85	2392	#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->DCKCFGR1 &= ~(RCC_DCKCFGR1_TIMPRE);\
AnnaBridge	126:abea610beb85	2393	RCC->DCKCFGR1 \|= (__PRESC__); \
AnnaBridge	126:abea610beb85	2394	}while(0)
AnnaBridge	126:abea610beb85	2395
AnnaBridge	126:abea610beb85	2396	/** @brief Macros to Enable or Disable the PLLISAI.
AnnaBridge	126:abea610beb85	2397	* @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
AnnaBridge	126:abea610beb85	2398	*/
AnnaBridge	126:abea610beb85	2399	#define __HAL_RCC_PLLSAI_ENABLE() (RCC->CR \|= (RCC_CR_PLLSAION))
AnnaBridge	126:abea610beb85	2400	#define __HAL_RCC_PLLSAI_DISABLE() (RCC->CR &= ~(RCC_CR_PLLSAION))
AnnaBridge	126:abea610beb85	2401
AnnaBridge	126:abea610beb85	2402	/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
AnnaBridge	126:abea610beb85	2403	* @note This function must be used only when the PLLSAI is disabled.
AnnaBridge	126:abea610beb85	2404	* @note PLLSAI clock source is common with the main PLL (configured in
AnnaBridge	126:abea610beb85	2405	* RCC_PLLConfig function )
AnnaBridge	126:abea610beb85	2406	* @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
AnnaBridge	126:abea610beb85	2407	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
AnnaBridge	126:abea610beb85	2408	* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
AnnaBridge	126:abea610beb85	2409	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
AnnaBridge	126:abea610beb85	2410	* @param __PLLSAIP__: specifies the division factor for USB, RNG, SDMMC clocks
AnnaBridge	126:abea610beb85	2411	* This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider.
AnnaBridge	126:abea610beb85	2412	* @param __PLLSAIQ__: specifies the division factor for SAI clock
AnnaBridge	126:abea610beb85	2413	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
AnnaBridge	126:abea610beb85	2414	* @param __PLLSAIR__: specifies the division factor for LTDC clock
AnnaBridge	126:abea610beb85	2415	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
AnnaBridge	126:abea610beb85	2416	*/
AnnaBridge	126:abea610beb85	2417	#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
AnnaBridge	126:abea610beb85	2418	(RCC->PLLSAICFGR = ((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) \|\
AnnaBridge	126:abea610beb85	2419	((__PLLSAIP__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) \|\
AnnaBridge	126:abea610beb85	2420	((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)) \|\
AnnaBridge	126:abea610beb85	2421	((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)))
AnnaBridge	126:abea610beb85	2422
AnnaBridge	126:abea610beb85	2423	/** @brief Macro to configure the PLLI2S clock multiplication and division factors.
AnnaBridge	126:abea610beb85	2424	* @note This macro must be used only when the PLLI2S is disabled.
AnnaBridge	126:abea610beb85	2425	* @note PLLI2S clock source is common with the main PLL (configured in
AnnaBridge	126:abea610beb85	2426	* HAL_RCC_ClockConfig() API)
AnnaBridge	126:abea610beb85	2427	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
AnnaBridge	126:abea610beb85	2428	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
AnnaBridge	126:abea610beb85	2429	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
AnnaBridge	126:abea610beb85	2430	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
AnnaBridge	126:abea610beb85	2431	* @param __PLLI2SP__: specifies the division factor for SPDDIF-RX clock.
AnnaBridge	126:abea610beb85	2432	* This parameter can be a value of @ref RCCEx_PLLI2SP_Clock_Divider.
AnnaBridge	126:abea610beb85	2433	* @param __PLLI2SQ__: specifies the division factor for SAI clock.
AnnaBridge	126:abea610beb85	2434	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
AnnaBridge	126:abea610beb85	2435	* @param __PLLI2SR__: specifies the division factor for I2S clock
AnnaBridge	126:abea610beb85	2436	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
AnnaBridge	126:abea610beb85	2437	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
AnnaBridge	126:abea610beb85	2438	* on the I2S clock frequency.
AnnaBridge	126:abea610beb85	2439	*/
AnnaBridge	126:abea610beb85	2440	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \
AnnaBridge	126:abea610beb85	2441	(RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \|\
AnnaBridge	126:abea610beb85	2442	((__PLLI2SP__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) \|\
AnnaBridge	126:abea610beb85	2443	((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) \|\
AnnaBridge	126:abea610beb85	2444	((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))
AnnaBridge	126:abea610beb85	2445
AnnaBridge	126:abea610beb85	2446	/** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
AnnaBridge	126:abea610beb85	2447	* @note This function must be called before enabling the PLLI2S.
AnnaBridge	126:abea610beb85	2448	* @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock .
AnnaBridge	126:abea610beb85	2449	* This parameter must be a number between 1 and 32.
AnnaBridge	126:abea610beb85	2450	* SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
AnnaBridge	126:abea610beb85	2451	*/
AnnaBridge	126:abea610beb85	2452	#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
AnnaBridge	126:abea610beb85	2453
AnnaBridge	126:abea610beb85	2454	/** @brief Macro to configure the SAI clock Divider coming from PLLSAI.
AnnaBridge	126:abea610beb85	2455	* @note This function must be called before enabling the PLLSAI.
AnnaBridge	126:abea610beb85	2456	* @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
AnnaBridge	126:abea610beb85	2457	* This parameter must be a number between Min_Data = 1 and Max_Data = 32.
AnnaBridge	126:abea610beb85	2458	* SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
AnnaBridge	126:abea610beb85	2459	*/
AnnaBridge	126:abea610beb85	2460	#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
AnnaBridge	126:abea610beb85	2461
AnnaBridge	126:abea610beb85	2462	/** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.
AnnaBridge	126:abea610beb85	2463	*
AnnaBridge	126:abea610beb85	2464	* @note This function must be called before enabling the PLLSAI.
AnnaBridge	126:abea610beb85	2465	* @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
AnnaBridge	126:abea610beb85	2466	* This parameter can be a value of @ref RCCEx_PLLSAI_DIVR.
AnnaBridge	126:abea610beb85	2467	* LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
AnnaBridge	126:abea610beb85	2468	*/
AnnaBridge	126:abea610beb85	2469	#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__)\
AnnaBridge	126:abea610beb85	2470	MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, (uint32_t)(__PLLSAIDivR__))
AnnaBridge	126:abea610beb85	2471
AnnaBridge	126:abea610beb85	2472	/** @brief Macro to configure SAI1 clock source selection.
AnnaBridge	126:abea610beb85	2473	* @note This function must be called before enabling PLLSAI, PLLI2S and
AnnaBridge	126:abea610beb85	2474	* the SAI clock.
AnnaBridge	126:abea610beb85	2475	* @param __SOURCE__: specifies the SAI1 clock source.
AnnaBridge	126:abea610beb85	2476	* This parameter can be one of the following values:
AnnaBridge	126:abea610beb85	2477	* @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
AnnaBridge	126:abea610beb85	2478	* as SAI1 clock.
AnnaBridge	126:abea610beb85	2479	* @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
AnnaBridge	126:abea610beb85	2480	* as SAI1 clock.
AnnaBridge	126:abea610beb85	2481	* @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
AnnaBridge	126:abea610beb85	2482	* used as SAI1 clock.
AnnaBridge	126:abea610beb85	2483	* @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock
AnnaBridge	126:abea610beb85	2484	* used as SAI1 clock.
AnnaBridge	126:abea610beb85	2485	* @note The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices
AnnaBridge	126:abea610beb85	2486	*/
AnnaBridge	126:abea610beb85	2487	#define __HAL_RCC_SAI1_CONFIG(__SOURCE__)\
AnnaBridge	126:abea610beb85	2488	MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL, (uint32_t)(__SOURCE__))
AnnaBridge	126:abea610beb85	2489
AnnaBridge	126:abea610beb85	2490	/** @brief Macro to get the SAI1 clock source.
AnnaBridge	126:abea610beb85	2491	* @retval The clock source can be one of the following values:
AnnaBridge	126:abea610beb85	2492	* @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
AnnaBridge	126:abea610beb85	2493	* as SAI1 clock.
AnnaBridge	126:abea610beb85	2494	* @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
AnnaBridge	126:abea610beb85	2495	* as SAI1 clock.
AnnaBridge	126:abea610beb85	2496	* @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
AnnaBridge	126:abea610beb85	2497	* used as SAI1 clock.
AnnaBridge	126:abea610beb85	2498	* @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock
AnnaBridge	126:abea610beb85	2499	* used as SAI1 clock.
AnnaBridge	126:abea610beb85	2500	* @note The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices
AnnaBridge	126:abea610beb85	2501	*/
AnnaBridge	126:abea610beb85	2502	#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL)))
AnnaBridge	126:abea610beb85	2503
AnnaBridge	126:abea610beb85	2504
AnnaBridge	126:abea610beb85	2505	/** @brief Macro to configure SAI2 clock source selection.
AnnaBridge	126:abea610beb85	2506	* @note This function must be called before enabling PLLSAI, PLLI2S and
AnnaBridge	126:abea610beb85	2507	* the SAI clock.
AnnaBridge	126:abea610beb85	2508	* @param __SOURCE__: specifies the SAI2 clock source.
AnnaBridge	126:abea610beb85	2509	* This parameter can be one of the following values:
AnnaBridge	126:abea610beb85	2510	* @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
AnnaBridge	126:abea610beb85	2511	* as SAI2 clock.
AnnaBridge	126:abea610beb85	2512	* @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
AnnaBridge	126:abea610beb85	2513	* as SAI2 clock.
AnnaBridge	126:abea610beb85	2514	* @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
AnnaBridge	126:abea610beb85	2515	* used as SAI2 clock.
AnnaBridge	126:abea610beb85	2516	* @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock
AnnaBridge	126:abea610beb85	2517	* used as SAI2 clock.
AnnaBridge	126:abea610beb85	2518	* @note The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices
AnnaBridge	126:abea610beb85	2519	*/
AnnaBridge	126:abea610beb85	2520	#define __HAL_RCC_SAI2_CONFIG(__SOURCE__)\
AnnaBridge	126:abea610beb85	2521	MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL, (uint32_t)(__SOURCE__))
AnnaBridge	126:abea610beb85	2522
AnnaBridge	126:abea610beb85	2523
AnnaBridge	126:abea610beb85	2524	/** @brief Macro to get the SAI2 clock source.
AnnaBridge	126:abea610beb85	2525	* @retval The clock source can be one of the following values:
AnnaBridge	126:abea610beb85	2526	* @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
AnnaBridge	126:abea610beb85	2527	* as SAI2 clock.
AnnaBridge	126:abea610beb85	2528	* @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
AnnaBridge	126:abea610beb85	2529	* as SAI2 clock.
AnnaBridge	126:abea610beb85	2530	* @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
AnnaBridge	126:abea610beb85	2531	* used as SAI2 clock.
AnnaBridge	126:abea610beb85	2532	* @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock
AnnaBridge	126:abea610beb85	2533	* used as SAI2 clock.
AnnaBridge	126:abea610beb85	2534	* @note The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices
AnnaBridge	126:abea610beb85	2535	*/
AnnaBridge	126:abea610beb85	2536	#define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL)))
AnnaBridge	126:abea610beb85	2537
AnnaBridge	126:abea610beb85	2538
AnnaBridge	126:abea610beb85	2539	/** @brief Enable PLLSAI_RDY interrupt.
AnnaBridge	126:abea610beb85	2540	*/
AnnaBridge	126:abea610beb85	2541	#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR \|= (RCC_CIR_PLLSAIRDYIE))
AnnaBridge	126:abea610beb85	2542
AnnaBridge	126:abea610beb85	2543	/** @brief Disable PLLSAI_RDY interrupt.
AnnaBridge	126:abea610beb85	2544	*/
AnnaBridge	126:abea610beb85	2545	#define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
AnnaBridge	126:abea610beb85	2546
AnnaBridge	126:abea610beb85	2547	/** @brief Clear the PLLSAI RDY interrupt pending bits.
AnnaBridge	126:abea610beb85	2548	*/
AnnaBridge	126:abea610beb85	2549	#define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR \|= (RCC_CIR_PLLSAIRDYF))
AnnaBridge	126:abea610beb85	2550
AnnaBridge	126:abea610beb85	2551	/** @brief Check the PLLSAI RDY interrupt has occurred or not.
AnnaBridge	126:abea610beb85	2552	* @retval The new state (TRUE or FALSE).
AnnaBridge	126:abea610beb85	2553	*/
AnnaBridge	126:abea610beb85	2554	#define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
AnnaBridge	126:abea610beb85	2555
AnnaBridge	126:abea610beb85	2556	/** @brief Check PLLSAI RDY flag is set or not.
AnnaBridge	126:abea610beb85	2557	* @retval The new state (TRUE or FALSE).
AnnaBridge	126:abea610beb85	2558	*/
AnnaBridge	126:abea610beb85	2559	#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
AnnaBridge	126:abea610beb85	2560
AnnaBridge	126:abea610beb85	2561	/** @brief Macro to Get I2S clock source selection.
AnnaBridge	126:abea610beb85	2562	* @retval The clock source can be one of the following values:
AnnaBridge	126:abea610beb85	2563	* @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
AnnaBridge	126:abea610beb85	2564	* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S clock source
AnnaBridge	126:abea610beb85	2565	*/
AnnaBridge	126:abea610beb85	2566	#define __HAL_RCC_GET_I2SCLKSOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC))
AnnaBridge	126:abea610beb85	2567
AnnaBridge	126:abea610beb85	2568	/** @brief Macro to configure the I2C1 clock (I2C1CLK).
AnnaBridge	126:abea610beb85	2569	*
AnnaBridge	126:abea610beb85	2570	* @param __I2C1_CLKSOURCE__: specifies the I2C1 clock source.
AnnaBridge	126:abea610beb85	2571	* This parameter can be one of the following values:
AnnaBridge	126:abea610beb85	2572	* @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
AnnaBridge	126:abea610beb85	2573	* @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
AnnaBridge	126:abea610beb85	2574	* @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
AnnaBridge	126:abea610beb85	2575	*/
AnnaBridge	126:abea610beb85	2576	#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
AnnaBridge	126:abea610beb85	2577	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))
AnnaBridge	126:abea610beb85	2578
AnnaBridge	126:abea610beb85	2579	/** @brief Macro to get the I2C1 clock source.
AnnaBridge	126:abea610beb85	2580	* @retval The clock source can be one of the following values:
AnnaBridge	126:abea610beb85	2581	* @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
AnnaBridge	126:abea610beb85	2582	* @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
AnnaBridge	126:abea610beb85	2583	* @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
AnnaBridge	126:abea610beb85	2584	*/
AnnaBridge	126:abea610beb85	2585	#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL)))
AnnaBridge	126:abea610beb85	2586
AnnaBridge	126:abea610beb85	2587	/** @brief Macro to configure the I2C2 clock (I2C2CLK).
AnnaBridge	126:abea610beb85	2588	*
AnnaBridge	126:abea610beb85	2589	* @param __I2C2_CLKSOURCE__: specifies the I2C2 clock source.
AnnaBridge	126:abea610beb85	2590	* This parameter can be one of the following values:
AnnaBridge	126:abea610beb85	2591	* @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock
AnnaBridge	126:abea610beb85	2592	* @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
AnnaBridge	126:abea610beb85	2593	* @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
AnnaBridge	126:abea610beb85	2594	*/
AnnaBridge	126:abea610beb85	2595	#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \
AnnaBridge	126:abea610beb85	2596	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))
AnnaBridge	126:abea610beb85	2597
AnnaBridge	126:abea610beb85	2598	/** @brief Macro to get the I2C2 clock source.
AnnaBridge	126:abea610beb85	2599	* @retval The clock source can be one of the following values:
AnnaBridge	126:abea610beb85	2600	* @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock
AnnaBridge	126:abea610beb85	2601	* @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
AnnaBridge	126:abea610beb85	2602	* @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
AnnaBridge	126:abea610beb85	2603	*/
AnnaBridge	126:abea610beb85	2604	#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL)))
AnnaBridge	126:abea610beb85	2605
AnnaBridge	126:abea610beb85	2606	/** @brief Macro to configure the I2C3 clock (I2C3CLK).
AnnaBridge	126:abea610beb85	2607	*
AnnaBridge	126:abea610beb85	2608	* @param __I2C3_CLKSOURCE__: specifies the I2C3 clock source.
AnnaBridge	126:abea610beb85	2609	* This parameter can be one of the following values:
AnnaBridge	126:abea610beb85	2610	* @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
AnnaBridge	126:abea610beb85	2611	* @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
AnnaBridge	126:abea610beb85	2612	* @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
AnnaBridge	126:abea610beb85	2613	*/
AnnaBridge	126:abea610beb85	2614	#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \
AnnaBridge	126:abea610beb85	2615	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))
AnnaBridge	126:abea610beb85	2616
AnnaBridge	126:abea610beb85	2617	/** @brief macro to get the I2C3 clock source.
AnnaBridge	126:abea610beb85	2618	* @retval The clock source can be one of the following values:
AnnaBridge	126:abea610beb85	2619	* @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
AnnaBridge	126:abea610beb85	2620	* @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
AnnaBridge	126:abea610beb85	2621	* @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
AnnaBridge	126:abea610beb85	2622	*/
AnnaBridge	126:abea610beb85	2623	#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL)))
AnnaBridge	126:abea610beb85	2624
AnnaBridge	126:abea610beb85	2625	/** @brief Macro to configure the I2C4 clock (I2C4CLK).
AnnaBridge	126:abea610beb85	2626	*
AnnaBridge	126:abea610beb85	2627	* @param __I2C4_CLKSOURCE__: specifies the I2C4 clock source.
AnnaBridge	126:abea610beb85	2628	* This parameter can be one of the following values:
AnnaBridge	126:abea610beb85	2629	* @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock
AnnaBridge	126:abea610beb85	2630	* @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
AnnaBridge	126:abea610beb85	2631	* @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock
AnnaBridge	126:abea610beb85	2632	*/
AnnaBridge	126:abea610beb85	2633	#define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \
AnnaBridge	126:abea610beb85	2634	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__))
AnnaBridge	126:abea610beb85	2635
AnnaBridge	126:abea610beb85	2636	/** @brief macro to get the I2C4 clock source.
AnnaBridge	126:abea610beb85	2637	* @retval The clock source can be one of the following values:
AnnaBridge	126:abea610beb85	2638	* @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock
AnnaBridge	126:abea610beb85	2639	* @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
AnnaBridge	126:abea610beb85	2640	* @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock
AnnaBridge	126:abea610beb85	2641	*/
AnnaBridge	126:abea610beb85	2642	#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL)))
AnnaBridge	126:abea610beb85	2643
AnnaBridge	126:abea610beb85	2644	/** @brief Macro to configure the USART1 clock (USART1CLK).
AnnaBridge	126:abea610beb85	2645	*
AnnaBridge	126:abea610beb85	2646	* @param __USART1_CLKSOURCE__: specifies the USART1 clock source.
AnnaBridge	126:abea610beb85	2647	* This parameter can be one of the following values:
AnnaBridge	126:abea610beb85	2648	* @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
AnnaBridge	126:abea610beb85	2649	* @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
AnnaBridge	126:abea610beb85	2650	* @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
AnnaBridge	126:abea610beb85	2651	* @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
AnnaBridge	126:abea610beb85	2652	*/
AnnaBridge	126:abea610beb85	2653	#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
AnnaBridge	126:abea610beb85	2654	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))
AnnaBridge	126:abea610beb85	2655
AnnaBridge	126:abea610beb85	2656	/** @brief macro to get the USART1 clock source.
AnnaBridge	126:abea610beb85	2657	* @retval The clock source can be one of the following values:
AnnaBridge	126:abea610beb85	2658	* @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
AnnaBridge	126:abea610beb85	2659	* @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
AnnaBridge	126:abea610beb85	2660	* @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
AnnaBridge	126:abea610beb85	2661	* @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
AnnaBridge	126:abea610beb85	2662	*/
AnnaBridge	126:abea610beb85	2663	#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL)))
AnnaBridge	126:abea610beb85	2664
AnnaBridge	126:abea610beb85	2665	/** @brief Macro to configure the USART2 clock (USART2CLK).
AnnaBridge	126:abea610beb85	2666	*
AnnaBridge	126:abea610beb85	2667	* @param __USART2_CLKSOURCE__: specifies the USART2 clock source.
AnnaBridge	126:abea610beb85	2668	* This parameter can be one of the following values:
AnnaBridge	126:abea610beb85	2669	* @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
AnnaBridge	126:abea610beb85	2670	* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
AnnaBridge	126:abea610beb85	2671	* @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
AnnaBridge	126:abea610beb85	2672	* @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
AnnaBridge	126:abea610beb85	2673	*/
AnnaBridge	126:abea610beb85	2674	#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
AnnaBridge	126:abea610beb85	2675	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))
AnnaBridge	126:abea610beb85	2676
AnnaBridge	126:abea610beb85	2677	/** @brief macro to get the USART2 clock source.
AnnaBridge	126:abea610beb85	2678	* @retval The clock source can be one of the following values:
AnnaBridge	126:abea610beb85	2679	* @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
AnnaBridge	126:abea610beb85	2680	* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
AnnaBridge	126:abea610beb85	2681	* @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
AnnaBridge	126:abea610beb85	2682	* @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
AnnaBridge	126:abea610beb85	2683	*/
AnnaBridge	126:abea610beb85	2684	#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL)))
AnnaBridge	126:abea610beb85	2685
AnnaBridge	126:abea610beb85	2686	/** @brief Macro to configure the USART3 clock (USART3CLK).
AnnaBridge	126:abea610beb85	2687	*
AnnaBridge	126:abea610beb85	2688	* @param __USART3_CLKSOURCE__: specifies the USART3 clock source.
AnnaBridge	126:abea610beb85	2689	* This parameter can be one of the following values:
AnnaBridge	126:abea610beb85	2690	* @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
AnnaBridge	126:abea610beb85	2691	* @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
AnnaBridge	126:abea610beb85	2692	* @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
AnnaBridge	126:abea610beb85	2693	* @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
AnnaBridge	126:abea610beb85	2694	*/
AnnaBridge	126:abea610beb85	2695	#define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \
AnnaBridge	126:abea610beb85	2696	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))
AnnaBridge	126:abea610beb85	2697
AnnaBridge	126:abea610beb85	2698	/** @brief macro to get the USART3 clock source.
AnnaBridge	126:abea610beb85	2699	* @retval The clock source can be one of the following values:
AnnaBridge	126:abea610beb85	2700	* @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
AnnaBridge	126:abea610beb85	2701	* @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
AnnaBridge	126:abea610beb85	2702	* @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
AnnaBridge	126:abea610beb85	2703	* @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
AnnaBridge	126:abea610beb85	2704	*/
AnnaBridge	126:abea610beb85	2705	#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL)))
AnnaBridge	126:abea610beb85	2706
AnnaBridge	126:abea610beb85	2707	/** @brief Macro to configure the UART4 clock (UART4CLK).
AnnaBridge	126:abea610beb85	2708	*
AnnaBridge	126:abea610beb85	2709	* @param __UART4_CLKSOURCE__: specifies the UART4 clock source.
AnnaBridge	126:abea610beb85	2710	* This parameter can be one of the following values:
AnnaBridge	126:abea610beb85	2711	* @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
AnnaBridge	126:abea610beb85	2712	* @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
AnnaBridge	126:abea610beb85	2713	* @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
AnnaBridge	126:abea610beb85	2714	* @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
AnnaBridge	126:abea610beb85	2715	*/
AnnaBridge	126:abea610beb85	2716	#define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \
AnnaBridge	126:abea610beb85	2717	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__))
AnnaBridge	126:abea610beb85	2718
AnnaBridge	126:abea610beb85	2719	/** @brief macro to get the UART4 clock source.
AnnaBridge	126:abea610beb85	2720	* @retval The clock source can be one of the following values:
AnnaBridge	126:abea610beb85	2721	* @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
AnnaBridge	126:abea610beb85	2722	* @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
AnnaBridge	126:abea610beb85	2723	* @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
AnnaBridge	126:abea610beb85	2724	* @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
AnnaBridge	126:abea610beb85	2725	*/
AnnaBridge	126:abea610beb85	2726	#define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL)))
AnnaBridge	126:abea610beb85	2727
AnnaBridge	126:abea610beb85	2728	/** @brief Macro to configure the UART5 clock (UART5CLK).
AnnaBridge	126:abea610beb85	2729	*
AnnaBridge	126:abea610beb85	2730	* @param __UART5_CLKSOURCE__: specifies the UART5 clock source.
AnnaBridge	126:abea610beb85	2731	* This parameter can be one of the following values:
AnnaBridge	126:abea610beb85	2732	* @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
AnnaBridge	126:abea610beb85	2733	* @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
AnnaBridge	126:abea610beb85	2734	* @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
AnnaBridge	126:abea610beb85	2735	* @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
AnnaBridge	126:abea610beb85	2736	*/
AnnaBridge	126:abea610beb85	2737	#define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \
AnnaBridge	126:abea610beb85	2738	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__))
AnnaBridge	126:abea610beb85	2739
AnnaBridge	126:abea610beb85	2740	/** @brief macro to get the UART5 clock source.
AnnaBridge	126:abea610beb85	2741	* @retval The clock source can be one of the following values:
AnnaBridge	126:abea610beb85	2742	* @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
AnnaBridge	126:abea610beb85	2743	* @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
AnnaBridge	126:abea610beb85	2744	* @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
AnnaBridge	126:abea610beb85	2745	* @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
AnnaBridge	126:abea610beb85	2746	*/
AnnaBridge	126:abea610beb85	2747	#define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL)))
AnnaBridge	126:abea610beb85	2748
AnnaBridge	126:abea610beb85	2749	/** @brief Macro to configure the USART6 clock (USART6CLK).
AnnaBridge	126:abea610beb85	2750	*
AnnaBridge	126:abea610beb85	2751	* @param __USART6_CLKSOURCE__: specifies the USART6 clock source.
AnnaBridge	126:abea610beb85	2752	* This parameter can be one of the following values:
AnnaBridge	126:abea610beb85	2753	* @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock
AnnaBridge	126:abea610beb85	2754	* @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
AnnaBridge	126:abea610beb85	2755	* @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock
AnnaBridge	126:abea610beb85	2756	* @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
AnnaBridge	126:abea610beb85	2757	*/
AnnaBridge	126:abea610beb85	2758	#define __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__) \
AnnaBridge	126:abea610beb85	2759	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__))
AnnaBridge	126:abea610beb85	2760
AnnaBridge	126:abea610beb85	2761	/** @brief macro to get the USART6 clock source.
AnnaBridge	126:abea610beb85	2762	* @retval The clock source can be one of the following values:
AnnaBridge	126:abea610beb85	2763	* @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock
AnnaBridge	126:abea610beb85	2764	* @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
AnnaBridge	126:abea610beb85	2765	* @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock
AnnaBridge	126:abea610beb85	2766	* @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
AnnaBridge	126:abea610beb85	2767	*/
AnnaBridge	126:abea610beb85	2768	#define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL)))
AnnaBridge	126:abea610beb85	2769
AnnaBridge	126:abea610beb85	2770	/** @brief Macro to configure the UART7 clock (UART7CLK).
AnnaBridge	126:abea610beb85	2771	*
AnnaBridge	126:abea610beb85	2772	* @param __UART7_CLKSOURCE__: specifies the UART7 clock source.
AnnaBridge	126:abea610beb85	2773	* This parameter can be one of the following values:
AnnaBridge	126:abea610beb85	2774	* @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock
AnnaBridge	126:abea610beb85	2775	* @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
AnnaBridge	126:abea610beb85	2776	* @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock
AnnaBridge	126:abea610beb85	2777	* @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
AnnaBridge	126:abea610beb85	2778	*/
AnnaBridge	126:abea610beb85	2779	#define __HAL_RCC_UART7_CONFIG(__UART7_CLKSOURCE__) \
AnnaBridge	126:abea610beb85	2780	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL, (uint32_t)(__UART7_CLKSOURCE__))
AnnaBridge	126:abea610beb85	2781
AnnaBridge	126:abea610beb85	2782	/** @brief macro to get the UART7 clock source.
AnnaBridge	126:abea610beb85	2783	* @retval The clock source can be one of the following values:
AnnaBridge	126:abea610beb85	2784	* @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock
AnnaBridge	126:abea610beb85	2785	* @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
AnnaBridge	126:abea610beb85	2786	* @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock
AnnaBridge	126:abea610beb85	2787	* @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
AnnaBridge	126:abea610beb85	2788	*/
AnnaBridge	126:abea610beb85	2789	#define __HAL_RCC_GET_UART7_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL)))
AnnaBridge	126:abea610beb85	2790
AnnaBridge	126:abea610beb85	2791	/** @brief Macro to configure the UART8 clock (UART8CLK).
AnnaBridge	126:abea610beb85	2792	*
AnnaBridge	126:abea610beb85	2793	* @param __UART8_CLKSOURCE__: specifies the UART8 clock source.
AnnaBridge	126:abea610beb85	2794	* This parameter can be one of the following values:
AnnaBridge	126:abea610beb85	2795	* @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock
AnnaBridge	126:abea610beb85	2796	* @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
AnnaBridge	126:abea610beb85	2797	* @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock
AnnaBridge	126:abea610beb85	2798	* @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
AnnaBridge	126:abea610beb85	2799	*/
AnnaBridge	126:abea610beb85	2800	#define __HAL_RCC_UART8_CONFIG(__UART8_CLKSOURCE__) \
AnnaBridge	126:abea610beb85	2801	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL, (uint32_t)(__UART8_CLKSOURCE__))
AnnaBridge	126:abea610beb85	2802
AnnaBridge	126:abea610beb85	2803	/** @brief macro to get the UART8 clock source.
AnnaBridge	126:abea610beb85	2804	* @retval The clock source can be one of the following values:
AnnaBridge	126:abea610beb85	2805	* @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock
AnnaBridge	126:abea610beb85	2806	* @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
AnnaBridge	126:abea610beb85	2807	* @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock
AnnaBridge	126:abea610beb85	2808	* @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
AnnaBridge	126:abea610beb85	2809	*/
AnnaBridge	126:abea610beb85	2810	#define __HAL_RCC_GET_UART8_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL)))
AnnaBridge	126:abea610beb85	2811
AnnaBridge	126:abea610beb85	2812	/** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK).
AnnaBridge	126:abea610beb85	2813	*
AnnaBridge	126:abea610beb85	2814	* @param __LPTIM1_CLKSOURCE__: specifies the LPTIM1 clock source.
AnnaBridge	126:abea610beb85	2815	* This parameter can be one of the following values:
AnnaBridge	126:abea610beb85	2816	* @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock
AnnaBridge	126:abea610beb85	2817	* @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock
AnnaBridge	126:abea610beb85	2818	* @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
AnnaBridge	126:abea610beb85	2819	* @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
AnnaBridge	126:abea610beb85	2820	*/
AnnaBridge	126:abea610beb85	2821	#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
AnnaBridge	126:abea610beb85	2822	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
AnnaBridge	126:abea610beb85	2823
AnnaBridge	126:abea610beb85	2824	/** @brief macro to get the LPTIM1 clock source.
AnnaBridge	126:abea610beb85	2825	* @retval The clock source can be one of the following values:
AnnaBridge	126:abea610beb85	2826	* @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock
AnnaBridge	126:abea610beb85	2827	* @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock
AnnaBridge	126:abea610beb85	2828	* @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
AnnaBridge	126:abea610beb85	2829	* @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
AnnaBridge	126:abea610beb85	2830	*/
AnnaBridge	126:abea610beb85	2831	#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)))
AnnaBridge	126:abea610beb85	2832
AnnaBridge	126:abea610beb85	2833	/** @brief Macro to configure the CEC clock (CECCLK).
AnnaBridge	126:abea610beb85	2834	*
AnnaBridge	126:abea610beb85	2835	* @param __CEC_CLKSOURCE__: specifies the CEC clock source.
AnnaBridge	126:abea610beb85	2836	* This parameter can be one of the following values:
AnnaBridge	126:abea610beb85	2837	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
AnnaBridge	126:abea610beb85	2838	* @arg RCC_CECCLKSOURCE_HSI: HSI divided by 488 selected as CEC clock
AnnaBridge	126:abea610beb85	2839	*/
AnnaBridge	126:abea610beb85	2840	#define __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__) \
AnnaBridge	126:abea610beb85	2841	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__CEC_CLKSOURCE__))
AnnaBridge	126:abea610beb85	2842
AnnaBridge	126:abea610beb85	2843	/** @brief macro to get the CEC clock source.
AnnaBridge	126:abea610beb85	2844	* @retval The clock source can be one of the following values:
AnnaBridge	126:abea610beb85	2845	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
AnnaBridge	126:abea610beb85	2846	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
AnnaBridge	126:abea610beb85	2847	*/
AnnaBridge	126:abea610beb85	2848	#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL)))
AnnaBridge	126:abea610beb85	2849
AnnaBridge	126:abea610beb85	2850	/** @brief Macro to configure the CLK48 source (CLK48CLK).
AnnaBridge	126:abea610beb85	2851	*
AnnaBridge	126:abea610beb85	2852	* @param __CLK48_SOURCE__: specifies the CLK48 clock source.
AnnaBridge	126:abea610beb85	2853	* This parameter can be one of the following values:
AnnaBridge	126:abea610beb85	2854	* @arg RCC_CLK48SOURCE_PLL: PLL selected as CLK48 source
AnnaBridge	126:abea610beb85	2855	* @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP selected as CLK48 source
AnnaBridge	126:abea610beb85	2856	*/
AnnaBridge	126:abea610beb85	2857	#define __HAL_RCC_CLK48_CONFIG(__CLK48_SOURCE__) \
AnnaBridge	126:abea610beb85	2858	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__CLK48_SOURCE__))
AnnaBridge	126:abea610beb85	2859
AnnaBridge	126:abea610beb85	2860	/** @brief macro to get the CLK48 source.
AnnaBridge	126:abea610beb85	2861	* @retval The clock source can be one of the following values:
AnnaBridge	126:abea610beb85	2862	* @arg RCC_CLK48SOURCE_PLL: PLL used as CLK48 source
AnnaBridge	126:abea610beb85	2863	* @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP used as CLK48 source
AnnaBridge	126:abea610beb85	2864	*/
AnnaBridge	126:abea610beb85	2865	#define __HAL_RCC_GET_CLK48_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)))
AnnaBridge	126:abea610beb85	2866
AnnaBridge	126:abea610beb85	2867	/** @brief Macro to configure the SDMMC1 clock (SDMMC1CLK).
AnnaBridge	126:abea610beb85	2868	*
AnnaBridge	126:abea610beb85	2869	* @param __SDMMC1_CLKSOURCE__: specifies the SDMMC1 clock source.
AnnaBridge	126:abea610beb85	2870	* This parameter can be one of the following values:
AnnaBridge	126:abea610beb85	2871	* @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC clock
AnnaBridge	126:abea610beb85	2872	* @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC clock
AnnaBridge	126:abea610beb85	2873	*/
AnnaBridge	126:abea610beb85	2874	#define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \
AnnaBridge	126:abea610beb85	2875	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL, (uint32_t)(__SDMMC1_CLKSOURCE__))
AnnaBridge	126:abea610beb85	2876
AnnaBridge	126:abea610beb85	2877	/** @brief macro to get the SDMMC1 clock source.
AnnaBridge	126:abea610beb85	2878	* @retval The clock source can be one of the following values:
AnnaBridge	126:abea610beb85	2879	* @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC1 clock
AnnaBridge	126:abea610beb85	2880	* @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC1 clock
AnnaBridge	126:abea610beb85	2881	*/
AnnaBridge	126:abea610beb85	2882	#define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL)))
AnnaBridge	126:abea610beb85	2883
AnnaBridge	126:abea610beb85	2884	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	2885	/** @brief Macro to configure the SDMMC2 clock (SDMMC2CLK).
AnnaBridge	126:abea610beb85	2886	* @param __SDMMC2_CLKSOURCE__: specifies the SDMMC2 clock source.
AnnaBridge	126:abea610beb85	2887	* This parameter can be one of the following values:
AnnaBridge	126:abea610beb85	2888	* @arg RCC_SDMMC2CLKSOURCE_CLK48: CLK48 selected as SDMMC2 clock
AnnaBridge	126:abea610beb85	2889	* @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock
AnnaBridge	126:abea610beb85	2890	*/
AnnaBridge	126:abea610beb85	2891	#define __HAL_RCC_SDMMC2_CONFIG(__SDMMC2_CLKSOURCE__) \
AnnaBridge	126:abea610beb85	2892	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL, (uint32_t)(__SDMMC2_CLKSOURCE__))
AnnaBridge	126:abea610beb85	2893
AnnaBridge	126:abea610beb85	2894	/** @brief macro to get the SDMMC2 clock source.
AnnaBridge	126:abea610beb85	2895	* @retval The clock source can be one of the following values:
AnnaBridge	126:abea610beb85	2896	* @arg RCC_SDMMC2CLKSOURCE_CLK48: CLK48 selected as SDMMC2 clock
AnnaBridge	126:abea610beb85	2897	* @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock
AnnaBridge	126:abea610beb85	2898	*/
AnnaBridge	126:abea610beb85	2899	#define __HAL_RCC_GET_SDMMC2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL)))
AnnaBridge	126:abea610beb85	2900
AnnaBridge	126:abea610beb85	2901	/** @brief Macro to configure the DFSDM1 clock
AnnaBridge	126:abea610beb85	2902	* @param __DFSDM1_CLKSOURCE__: specifies the DFSDM1 clock source.
AnnaBridge	126:abea610beb85	2903	* This parameter can be one of the following values:
AnnaBridge	126:abea610beb85	2904	* @arg RCC_DFSDM1CLKSOURCE_PCLK: PCLK2 Clock selected as DFSDM clock
AnnaBridge	126:abea610beb85	2905	* @arg RCC_DFSDMCLKSOURCE_SYSCLK: System Clock selected as DFSDM clock
AnnaBridge	126:abea610beb85	2906	*/
AnnaBridge	126:abea610beb85	2907	#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \
AnnaBridge	126:abea610beb85	2908	MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL, (uint32_t)(__DFSDM1_CLKSOURCE__))
AnnaBridge	126:abea610beb85	2909
AnnaBridge	126:abea610beb85	2910	/** @brief Macro to get the DFSDM1 clock source.
AnnaBridge	126:abea610beb85	2911	* @retval The clock source can be one of the following values:
AnnaBridge	126:abea610beb85	2912	* @arg RCC_DFSDM1CLKSOURCE_PCLK: PCLK2 Clock selected as DFSDM1 clock
AnnaBridge	126:abea610beb85	2913	* @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System Clock selected as DFSDM1 clock
AnnaBridge	126:abea610beb85	2914	*/
AnnaBridge	126:abea610beb85	2915	#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL)))
AnnaBridge	126:abea610beb85	2916
AnnaBridge	126:abea610beb85	2917	/** @brief Macro to configure the DFSDM1 Audio clock
AnnaBridge	126:abea610beb85	2918	* @param __DFSDM1AUDIO_CLKSOURCE__: specifies the DFSDM1 Audio clock source.
AnnaBridge	126:abea610beb85	2919	* This parameter can be one of the following values:
AnnaBridge	126:abea610beb85	2920	* @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1: SAI1 Clock selected as DFSDM1 Audio clock
AnnaBridge	126:abea610beb85	2921	* @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2: SAI2 Clock selected as DFSDM1 Audio clock
AnnaBridge	126:abea610beb85	2922	*/
AnnaBridge	126:abea610beb85	2923	#define __HAL_RCC_DFSDM1AUDIO_CONFIG(__DFSDM1AUDIO_CLKSOURCE__) \
AnnaBridge	126:abea610beb85	2924	MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL, (uint32_t)(__DFSDM1AUDIO_CLKSOURCE__))
AnnaBridge	126:abea610beb85	2925
AnnaBridge	126:abea610beb85	2926	/** @brief Macro to get the DFSDM1 Audio clock source.
AnnaBridge	126:abea610beb85	2927	* @retval The clock source can be one of the following values:
AnnaBridge	126:abea610beb85	2928	* @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1: SAI1 Clock selected as DFSDM1 Audio clock
AnnaBridge	126:abea610beb85	2929	* @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2: SAI2 Clock selected as DFSDM1 Audio clock
AnnaBridge	126:abea610beb85	2930	*/
AnnaBridge	126:abea610beb85	2931	#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL)))
AnnaBridge	126:abea610beb85	2932	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	2933
AnnaBridge	126:abea610beb85	2934	#if defined (STM32F769xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	2935	/** @brief Macro to configure the DSI clock.
AnnaBridge	126:abea610beb85	2936	* @param __DSI_CLKSOURCE__: specifies the DSI clock source.
AnnaBridge	126:abea610beb85	2937	* This parameter can be one of the following values:
AnnaBridge	126:abea610beb85	2938	* @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.
AnnaBridge	126:abea610beb85	2939	* @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.
AnnaBridge	126:abea610beb85	2940	*/
AnnaBridge	126:abea610beb85	2941	#define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL, (uint32_t)(__DSI_CLKSOURCE__)))
AnnaBridge	126:abea610beb85	2942
AnnaBridge	126:abea610beb85	2943	/** @brief Macro to Get the DSI clock.
AnnaBridge	126:abea610beb85	2944	* @retval The clock source can be one of the following values:
AnnaBridge	126:abea610beb85	2945	* @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.
AnnaBridge	126:abea610beb85	2946	* @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.
AnnaBridge	126:abea610beb85	2947	*/
AnnaBridge	126:abea610beb85	2948	#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL))
AnnaBridge	126:abea610beb85	2949	#endif /* STM32F769xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	2950	/**
AnnaBridge	126:abea610beb85	2951	* @}
AnnaBridge	126:abea610beb85	2952	*/
AnnaBridge	126:abea610beb85	2953
AnnaBridge	126:abea610beb85	2954	/* Exported functions --------------------------------------------------------*/
AnnaBridge	126:abea610beb85	2955	/** @addtogroup RCCEx_Exported_Functions_Group1
AnnaBridge	126:abea610beb85	2956	* @{
AnnaBridge	126:abea610beb85	2957	*/
AnnaBridge	126:abea610beb85	2958	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
AnnaBridge	126:abea610beb85	2959	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
AnnaBridge	126:abea610beb85	2960	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
AnnaBridge	126:abea610beb85	2961
AnnaBridge	126:abea610beb85	2962	/**
AnnaBridge	126:abea610beb85	2963	* @}
AnnaBridge	126:abea610beb85	2964	*/
AnnaBridge	126:abea610beb85	2965	/* Private macros ------------------------------------------------------------*/
AnnaBridge	126:abea610beb85	2966	/** @addtogroup RCCEx_Private_Macros RCCEx Private Macros
AnnaBridge	126:abea610beb85	2967	* @{
AnnaBridge	126:abea610beb85	2968	*/
AnnaBridge	126:abea610beb85	2969	/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
AnnaBridge	126:abea610beb85	2970	* @{
AnnaBridge	126:abea610beb85	2971	*/
AnnaBridge	126:abea610beb85	2972	#if defined(STM32F756xx) \|\| defined(STM32F746xx)
AnnaBridge	126:abea610beb85	2973	#define IS_RCC_PERIPHCLOCK(SELECTION) \
AnnaBridge	126:abea610beb85	2974	((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) \|\| \
AnnaBridge	126:abea610beb85	2975	(((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) \|\| \
AnnaBridge	126:abea610beb85	2976	(((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) \|\| \
AnnaBridge	126:abea610beb85	2977	(((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) \|\| \
AnnaBridge	126:abea610beb85	2978	(((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) \|\| \
AnnaBridge	126:abea610beb85	2979	(((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) \|\| \
AnnaBridge	126:abea610beb85	2980	(((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) \|\| \
AnnaBridge	126:abea610beb85	2981	(((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) \|\| \
AnnaBridge	126:abea610beb85	2982	(((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) \|\| \
AnnaBridge	126:abea610beb85	2983	(((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) \|\| \
AnnaBridge	126:abea610beb85	2984	(((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) \|\| \
AnnaBridge	126:abea610beb85	2985	(((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) \|\| \
AnnaBridge	126:abea610beb85	2986	(((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) \|\| \
AnnaBridge	126:abea610beb85	2987	(((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) \|\| \
AnnaBridge	126:abea610beb85	2988	(((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) \|\| \
AnnaBridge	126:abea610beb85	2989	(((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) \|\| \
AnnaBridge	126:abea610beb85	2990	(((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) \|\| \
AnnaBridge	126:abea610beb85	2991	(((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) \|\| \
AnnaBridge	126:abea610beb85	2992	(((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) \|\| \
AnnaBridge	126:abea610beb85	2993	(((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) \|\| \
AnnaBridge	126:abea610beb85	2994	(((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) \|\| \
AnnaBridge	126:abea610beb85	2995	(((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) \|\| \
AnnaBridge	126:abea610beb85	2996	(((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
AnnaBridge	126:abea610beb85	2997	#elif defined(STM32F745xx)
AnnaBridge	126:abea610beb85	2998	#define IS_RCC_PERIPHCLOCK(SELECTION) \
AnnaBridge	126:abea610beb85	2999	((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) \|\| \
AnnaBridge	126:abea610beb85	3000	(((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) \|\| \
AnnaBridge	126:abea610beb85	3001	(((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) \|\| \
AnnaBridge	126:abea610beb85	3002	(((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) \|\| \
AnnaBridge	126:abea610beb85	3003	(((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) \|\| \
AnnaBridge	126:abea610beb85	3004	(((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) \|\| \
AnnaBridge	126:abea610beb85	3005	(((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) \|\| \
AnnaBridge	126:abea610beb85	3006	(((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) \|\| \
AnnaBridge	126:abea610beb85	3007	(((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) \|\| \
AnnaBridge	126:abea610beb85	3008	(((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) \|\| \
AnnaBridge	126:abea610beb85	3009	(((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) \|\| \
AnnaBridge	126:abea610beb85	3010	(((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) \|\| \
AnnaBridge	126:abea610beb85	3011	(((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) \|\| \
AnnaBridge	126:abea610beb85	3012	(((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) \|\| \
AnnaBridge	126:abea610beb85	3013	(((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) \|\| \
AnnaBridge	126:abea610beb85	3014	(((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) \|\| \
AnnaBridge	126:abea610beb85	3015	(((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) \|\| \
AnnaBridge	126:abea610beb85	3016	(((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) \|\| \
AnnaBridge	126:abea610beb85	3017	(((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) \|\| \
AnnaBridge	126:abea610beb85	3018	(((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) \|\| \
AnnaBridge	126:abea610beb85	3019	(((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) \|\| \
AnnaBridge	126:abea610beb85	3020	(((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
AnnaBridge	126:abea610beb85	3021	#elif defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	3022	#define IS_RCC_PERIPHCLOCK(SELECTION) \
AnnaBridge	126:abea610beb85	3023	((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) \|\| \
AnnaBridge	126:abea610beb85	3024	(((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) \|\| \
AnnaBridge	126:abea610beb85	3025	(((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) \|\| \
AnnaBridge	126:abea610beb85	3026	(((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) \|\| \
AnnaBridge	126:abea610beb85	3027	(((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) \|\| \
AnnaBridge	126:abea610beb85	3028	(((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) \|\| \
AnnaBridge	126:abea610beb85	3029	(((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) \|\| \
AnnaBridge	126:abea610beb85	3030	(((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) \|\| \
AnnaBridge	126:abea610beb85	3031	(((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) \|\| \
AnnaBridge	126:abea610beb85	3032	(((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) \|\| \
AnnaBridge	126:abea610beb85	3033	(((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) \|\| \
AnnaBridge	126:abea610beb85	3034	(((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) \|\| \
AnnaBridge	126:abea610beb85	3035	(((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) \|\| \
AnnaBridge	126:abea610beb85	3036	(((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) \|\| \
AnnaBridge	126:abea610beb85	3037	(((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) \|\| \
AnnaBridge	126:abea610beb85	3038	(((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) \|\| \
AnnaBridge	126:abea610beb85	3039	(((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) \|\| \
AnnaBridge	126:abea610beb85	3040	(((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) \|\| \
AnnaBridge	126:abea610beb85	3041	(((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) \|\| \
AnnaBridge	126:abea610beb85	3042	(((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) \|\| \
AnnaBridge	126:abea610beb85	3043	(((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) \|\| \
AnnaBridge	126:abea610beb85	3044	(((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) \|\| \
AnnaBridge	126:abea610beb85	3045	(((SELECTION) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) \|\| \
AnnaBridge	126:abea610beb85	3046	(((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) \|\| \
AnnaBridge	126:abea610beb85	3047	(((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) \|\| \
AnnaBridge	126:abea610beb85	3048	(((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
AnnaBridge	126:abea610beb85	3049	#elif defined (STM32F765xx)
AnnaBridge	126:abea610beb85	3050	#define IS_RCC_PERIPHCLOCK(SELECTION) \
AnnaBridge	126:abea610beb85	3051	((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) \|\| \
AnnaBridge	126:abea610beb85	3052	(((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) \|\| \
AnnaBridge	126:abea610beb85	3053	(((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) \|\| \
AnnaBridge	126:abea610beb85	3054	(((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) \|\| \
AnnaBridge	126:abea610beb85	3055	(((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) \|\| \
AnnaBridge	126:abea610beb85	3056	(((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) \|\| \
AnnaBridge	126:abea610beb85	3057	(((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) \|\| \
AnnaBridge	126:abea610beb85	3058	(((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) \|\| \
AnnaBridge	126:abea610beb85	3059	(((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) \|\| \
AnnaBridge	126:abea610beb85	3060	(((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) \|\| \
AnnaBridge	126:abea610beb85	3061	(((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) \|\| \
AnnaBridge	126:abea610beb85	3062	(((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) \|\| \
AnnaBridge	126:abea610beb85	3063	(((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) \|\| \
AnnaBridge	126:abea610beb85	3064	(((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) \|\| \
AnnaBridge	126:abea610beb85	3065	(((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) \|\| \
AnnaBridge	126:abea610beb85	3066	(((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) \|\| \
AnnaBridge	126:abea610beb85	3067	(((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) \|\| \
AnnaBridge	126:abea610beb85	3068	(((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) \|\| \
AnnaBridge	126:abea610beb85	3069	(((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) \|\| \
AnnaBridge	126:abea610beb85	3070	(((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) \|\| \
AnnaBridge	126:abea610beb85	3071	(((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) \|\| \
AnnaBridge	126:abea610beb85	3072	(((SELECTION) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) \|\| \
AnnaBridge	126:abea610beb85	3073	(((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) \|\| \
AnnaBridge	126:abea610beb85	3074	(((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) \|\| \
AnnaBridge	126:abea610beb85	3075	(((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
AnnaBridge	126:abea610beb85	3076	#endif /* STM32F746xx \|\| STM32F756xx */
AnnaBridge	126:abea610beb85	3077	#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
AnnaBridge	126:abea610beb85	3078	#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) \|\|\
AnnaBridge	126:abea610beb85	3079	((VALUE) == RCC_PLLI2SP_DIV4) \|\|\
AnnaBridge	126:abea610beb85	3080	((VALUE) == RCC_PLLI2SP_DIV6) \|\|\
AnnaBridge	126:abea610beb85	3081	((VALUE) == RCC_PLLI2SP_DIV8))
AnnaBridge	126:abea610beb85	3082	#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
AnnaBridge	126:abea610beb85	3083	#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
AnnaBridge	126:abea610beb85	3084
AnnaBridge	126:abea610beb85	3085	#define IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
AnnaBridge	126:abea610beb85	3086	#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) \|\|\
AnnaBridge	126:abea610beb85	3087	((VALUE) == RCC_PLLSAIP_DIV4) \|\|\
AnnaBridge	126:abea610beb85	3088	((VALUE) == RCC_PLLSAIP_DIV6) \|\|\
AnnaBridge	126:abea610beb85	3089	((VALUE) == RCC_PLLSAIP_DIV8))
AnnaBridge	126:abea610beb85	3090	#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
AnnaBridge	126:abea610beb85	3091	#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
AnnaBridge	126:abea610beb85	3092
AnnaBridge	126:abea610beb85	3093	#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
AnnaBridge	126:abea610beb85	3094
AnnaBridge	126:abea610beb85	3095	#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
AnnaBridge	126:abea610beb85	3096
AnnaBridge	126:abea610beb85	3097	#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) \|\|\
AnnaBridge	126:abea610beb85	3098	((VALUE) == RCC_PLLSAIDIVR_4) \|\|\
AnnaBridge	126:abea610beb85	3099	((VALUE) == RCC_PLLSAIDIVR_8) \|\|\
AnnaBridge	126:abea610beb85	3100	((VALUE) == RCC_PLLSAIDIVR_16))
AnnaBridge	126:abea610beb85	3101	#define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_PLLI2S) \|\| \
AnnaBridge	126:abea610beb85	3102	((SOURCE) == RCC_I2SCLKSOURCE_EXT))
AnnaBridge	126:abea610beb85	3103
AnnaBridge	126:abea610beb85	3104	#define IS_RCC_SDMMC1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC1CLKSOURCE_SYSCLK) \|\| \
AnnaBridge	126:abea610beb85	3105	((SOURCE) == RCC_SDMMC1CLKSOURCE_CLK48))
AnnaBridge	126:abea610beb85	3106
AnnaBridge	126:abea610beb85	3107	#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) \|\| \
AnnaBridge	126:abea610beb85	3108	((SOURCE) == RCC_CECCLKSOURCE_LSE))
AnnaBridge	126:abea610beb85	3109	#define IS_RCC_USART1CLKSOURCE(SOURCE) \
AnnaBridge	126:abea610beb85	3110	(((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) \|\| \
AnnaBridge	126:abea610beb85	3111	((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
AnnaBridge	126:abea610beb85	3112	((SOURCE) == RCC_USART1CLKSOURCE_LSE) \|\| \
AnnaBridge	126:abea610beb85	3113	((SOURCE) == RCC_USART1CLKSOURCE_HSI))
AnnaBridge	126:abea610beb85	3114
AnnaBridge	126:abea610beb85	3115	#define IS_RCC_USART2CLKSOURCE(SOURCE) \
AnnaBridge	126:abea610beb85	3116	(((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) \|\| \
AnnaBridge	126:abea610beb85	3117	((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) \|\| \
AnnaBridge	126:abea610beb85	3118	((SOURCE) == RCC_USART2CLKSOURCE_LSE) \|\| \
AnnaBridge	126:abea610beb85	3119	((SOURCE) == RCC_USART2CLKSOURCE_HSI))
AnnaBridge	126:abea610beb85	3120	#define IS_RCC_USART3CLKSOURCE(SOURCE) \
AnnaBridge	126:abea610beb85	3121	(((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) \|\| \
AnnaBridge	126:abea610beb85	3122	((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) \|\| \
AnnaBridge	126:abea610beb85	3123	((SOURCE) == RCC_USART3CLKSOURCE_LSE) \|\| \
AnnaBridge	126:abea610beb85	3124	((SOURCE) == RCC_USART3CLKSOURCE_HSI))
AnnaBridge	126:abea610beb85	3125
AnnaBridge	126:abea610beb85	3126	#define IS_RCC_UART4CLKSOURCE(SOURCE) \
AnnaBridge	126:abea610beb85	3127	(((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) \|\| \
AnnaBridge	126:abea610beb85	3128	((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) \|\| \
AnnaBridge	126:abea610beb85	3129	((SOURCE) == RCC_UART4CLKSOURCE_LSE) \|\| \
AnnaBridge	126:abea610beb85	3130	((SOURCE) == RCC_UART4CLKSOURCE_HSI))
AnnaBridge	126:abea610beb85	3131
AnnaBridge	126:abea610beb85	3132	#define IS_RCC_UART5CLKSOURCE(SOURCE) \
AnnaBridge	126:abea610beb85	3133	(((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) \|\| \
AnnaBridge	126:abea610beb85	3134	((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) \|\| \
AnnaBridge	126:abea610beb85	3135	((SOURCE) == RCC_UART5CLKSOURCE_LSE) \|\| \
AnnaBridge	126:abea610beb85	3136	((SOURCE) == RCC_UART5CLKSOURCE_HSI))
AnnaBridge	126:abea610beb85	3137
AnnaBridge	126:abea610beb85	3138	#define IS_RCC_USART6CLKSOURCE(SOURCE) \
AnnaBridge	126:abea610beb85	3139	(((SOURCE) == RCC_USART6CLKSOURCE_PCLK2) \|\| \
AnnaBridge	126:abea610beb85	3140	((SOURCE) == RCC_USART6CLKSOURCE_SYSCLK) \|\| \
AnnaBridge	126:abea610beb85	3141	((SOURCE) == RCC_USART6CLKSOURCE_LSE) \|\| \
AnnaBridge	126:abea610beb85	3142	((SOURCE) == RCC_USART6CLKSOURCE_HSI))
AnnaBridge	126:abea610beb85	3143
AnnaBridge	126:abea610beb85	3144	#define IS_RCC_UART7CLKSOURCE(SOURCE) \
AnnaBridge	126:abea610beb85	3145	(((SOURCE) == RCC_UART7CLKSOURCE_PCLK1) \|\| \
AnnaBridge	126:abea610beb85	3146	((SOURCE) == RCC_UART7CLKSOURCE_SYSCLK) \|\| \
AnnaBridge	126:abea610beb85	3147	((SOURCE) == RCC_UART7CLKSOURCE_LSE) \|\| \
AnnaBridge	126:abea610beb85	3148	((SOURCE) == RCC_UART7CLKSOURCE_HSI))
AnnaBridge	126:abea610beb85	3149
AnnaBridge	126:abea610beb85	3150	#define IS_RCC_UART8CLKSOURCE(SOURCE) \
AnnaBridge	126:abea610beb85	3151	(((SOURCE) == RCC_UART8CLKSOURCE_PCLK1) \|\| \
AnnaBridge	126:abea610beb85	3152	((SOURCE) == RCC_UART8CLKSOURCE_SYSCLK) \|\| \
AnnaBridge	126:abea610beb85	3153	((SOURCE) == RCC_UART8CLKSOURCE_LSE) \|\| \
AnnaBridge	126:abea610beb85	3154	((SOURCE) == RCC_UART8CLKSOURCE_HSI))
AnnaBridge	126:abea610beb85	3155	#define IS_RCC_I2C1CLKSOURCE(SOURCE) \
AnnaBridge	126:abea610beb85	3156	(((SOURCE) == RCC_I2C1CLKSOURCE_PCLK1) \|\| \
AnnaBridge	126:abea610beb85	3157	((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK)\|\| \
AnnaBridge	126:abea610beb85	3158	((SOURCE) == RCC_I2C1CLKSOURCE_HSI))
AnnaBridge	126:abea610beb85	3159	#define IS_RCC_I2C2CLKSOURCE(SOURCE) \
AnnaBridge	126:abea610beb85	3160	(((SOURCE) == RCC_I2C2CLKSOURCE_PCLK1) \|\| \
AnnaBridge	126:abea610beb85	3161	((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK)\|\| \
AnnaBridge	126:abea610beb85	3162	((SOURCE) == RCC_I2C2CLKSOURCE_HSI))
AnnaBridge	126:abea610beb85	3163
AnnaBridge	126:abea610beb85	3164	#define IS_RCC_I2C3CLKSOURCE(SOURCE) \
AnnaBridge	126:abea610beb85	3165	(((SOURCE) == RCC_I2C3CLKSOURCE_PCLK1) \|\| \
AnnaBridge	126:abea610beb85	3166	((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK)\|\| \
AnnaBridge	126:abea610beb85	3167	((SOURCE) == RCC_I2C3CLKSOURCE_HSI))
AnnaBridge	126:abea610beb85	3168	#define IS_RCC_I2C4CLKSOURCE(SOURCE) \
AnnaBridge	126:abea610beb85	3169	(((SOURCE) == RCC_I2C4CLKSOURCE_PCLK1) \|\| \
AnnaBridge	126:abea610beb85	3170	((SOURCE) == RCC_I2C4CLKSOURCE_SYSCLK)\|\| \
AnnaBridge	126:abea610beb85	3171	((SOURCE) == RCC_I2C4CLKSOURCE_HSI))
AnnaBridge	126:abea610beb85	3172	#define IS_RCC_LPTIM1CLK(SOURCE) \
AnnaBridge	126:abea610beb85	3173	(((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK) \|\| \
AnnaBridge	126:abea610beb85	3174	((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) \|\| \
AnnaBridge	126:abea610beb85	3175	((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) \|\| \
AnnaBridge	126:abea610beb85	3176	((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
AnnaBridge	126:abea610beb85	3177	#define IS_RCC_CLK48SOURCE(SOURCE) \
AnnaBridge	126:abea610beb85	3178	(((SOURCE) == RCC_CLK48SOURCE_PLLSAIP) \|\| \
AnnaBridge	126:abea610beb85	3179	((SOURCE) == RCC_CLK48SOURCE_PLL))
AnnaBridge	126:abea610beb85	3180	#define IS_RCC_TIMPRES(VALUE) \
AnnaBridge	126:abea610beb85	3181	(((VALUE) == RCC_TIMPRES_DESACTIVATED) \|\| \
AnnaBridge	126:abea610beb85	3182	((VALUE) == RCC_TIMPRES_ACTIVATED))
AnnaBridge	126:abea610beb85	3183
AnnaBridge	126:abea610beb85	3184	#if defined (STM32F745xx) \|\| defined (STM32F746xx) \|\| defined (STM32F756xx)
AnnaBridge	126:abea610beb85	3185	#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) \|\| \
AnnaBridge	126:abea610beb85	3186	((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) \|\| \
AnnaBridge	126:abea610beb85	3187	((SOURCE) == RCC_SAI1CLKSOURCE_PIN))
AnnaBridge	126:abea610beb85	3188	#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) \|\| \
AnnaBridge	126:abea610beb85	3189	((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) \|\| \
AnnaBridge	126:abea610beb85	3190	((SOURCE) == RCC_SAI2CLKSOURCE_PIN))
AnnaBridge	126:abea610beb85	3191	#endif /* STM32F745xx \|\| STM32F746xx \|\| STM32F756xx */
AnnaBridge	126:abea610beb85	3192
AnnaBridge	126:abea610beb85	3193	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	3194	#define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
AnnaBridge	126:abea610beb85	3195
AnnaBridge	126:abea610beb85	3196	#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) \|\| \
AnnaBridge	126:abea610beb85	3197	((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) \|\| \
AnnaBridge	126:abea610beb85	3198	((SOURCE) == RCC_SAI1CLKSOURCE_PIN) \|\| \
AnnaBridge	126:abea610beb85	3199	((SOURCE) == RCC_SAI1CLKSOURCE_PLLSRC))
AnnaBridge	126:abea610beb85	3200
AnnaBridge	126:abea610beb85	3201	#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) \|\| \
AnnaBridge	126:abea610beb85	3202	((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) \|\| \
AnnaBridge	126:abea610beb85	3203	((SOURCE) == RCC_SAI2CLKSOURCE_PIN) \|\| \
AnnaBridge	126:abea610beb85	3204	((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC))
AnnaBridge	126:abea610beb85	3205
AnnaBridge	126:abea610beb85	3206	#define IS_RCC_SDMMC2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC2CLKSOURCE_SYSCLK) \|\| \
AnnaBridge	126:abea610beb85	3207	((SOURCE) == RCC_SDMMC2CLKSOURCE_CLK48))
AnnaBridge	126:abea610beb85	3208
AnnaBridge	126:abea610beb85	3209	#define IS_RCC_DFSDM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1CLKSOURCE_PCLK) \|\| \
AnnaBridge	126:abea610beb85	3210	((SOURCE) == RCC_DFSDM1CLKSOURCE_SYSCLK))
AnnaBridge	126:abea610beb85	3211
AnnaBridge	126:abea610beb85	3212	#define IS_RCC_DFSDM1AUDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) \|\| \
AnnaBridge	126:abea610beb85	3213	((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI2))
AnnaBridge	126:abea610beb85	3214	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	3215
AnnaBridge	126:abea610beb85	3216	#if defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
AnnaBridge	126:abea610beb85	3217	#define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) \|\|\
AnnaBridge	126:abea610beb85	3218	((SOURCE) == RCC_DSICLKSOURCE_DSIPHY))
AnnaBridge	126:abea610beb85	3219	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
AnnaBridge	126:abea610beb85	3220
AnnaBridge	126:abea610beb85	3221	/**
AnnaBridge	126:abea610beb85	3222	* @}
AnnaBridge	126:abea610beb85	3223	*/
AnnaBridge	126:abea610beb85	3224
AnnaBridge	126:abea610beb85	3225	/**
AnnaBridge	126:abea610beb85	3226	* @}
AnnaBridge	126:abea610beb85	3227	*/
AnnaBridge	126:abea610beb85	3228
AnnaBridge	126:abea610beb85	3229	/**
AnnaBridge	126:abea610beb85	3230	* @}
AnnaBridge	126:abea610beb85	3231	*/
AnnaBridge	126:abea610beb85	3232
AnnaBridge	126:abea610beb85	3233	/**
AnnaBridge	126:abea610beb85	3234	* @}
AnnaBridge	126:abea610beb85	3235	*/
AnnaBridge	126:abea610beb85	3236	#ifdef __cplusplus
AnnaBridge	126:abea610beb85	3237	}
AnnaBridge	126:abea610beb85	3238	#endif
AnnaBridge	126:abea610beb85	3239
AnnaBridge	126:abea610beb85	3240	#endif /* __STM32F7xx_HAL_RCC_EX_H */
AnnaBridge	126:abea610beb85	3241
AnnaBridge	126:abea610beb85	3242	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/