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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_F302R8/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_rcc_ex.h@136:ef9c61f8c49f, 2017-02-14 (annotated)

Committer:
Kojto
Date:
Tue Feb 14 11:24:20 2017 +0000
Revision:
136:ef9c61f8c49f
Parent:
135:176b8275d35d 
Release 136 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3432: Target STM USBHOST support https://github.com/ARMmbed/mbed-os/pull/3432

3181: NUCLEO_F207ZG extending PeripheralPins.c: all available alternate functions can be used now https://github.com/ARMmbed/mbed-os/pull/3181

3626: NUCLEO_F412ZG : Add USB Device +Host https://github.com/ARMmbed/mbed-os/pull/3626

3628: Fix warnings https://github.com/ARMmbed/mbed-os/pull/3628

3629: STM32: L0 LL layer https://github.com/ARMmbed/mbed-os/pull/3629

3632: IDE Export support for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3632

3642: Missing IRQ pin fix for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3642

3664: Fix ncs36510 sleep definitions https://github.com/ARMmbed/mbed-os/pull/3664

3655: [STM32F4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3655

3657: [STM32L4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3657

3658: [STM32F3] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3658

3685: STM32: I2C: reset state machine https://github.com/ARMmbed/mbed-os/pull/3685

3692: uVisor: Standardize available legacy heap and stack https://github.com/ARMmbed/mbed-os/pull/3692

3621: Fix for #2884, LPC824: export to LPCXpresso, target running with wron https://github.com/ARMmbed/mbed-os/pull/3621

3649: [STM32F7] Modify folder structure  https://github.com/ARMmbed/mbed-os/pull/3649

3695: Enforce device_name is valid in targets.json https://github.com/ARMmbed/mbed-os/pull/3695

3723: NCS36510: spi_format function bug fix https://github.com/ARMmbed/mbed-os/pull/3723

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 126:abea610beb85 1 /**
AnnaBridge 126:abea610beb85 2 ******************************************************************************
AnnaBridge 126:abea610beb85 3 * @file stm32f3xx_hal_rcc_ex.h
AnnaBridge 126:abea610beb85 4 * @author MCD Application Team
<> 135:176b8275d35d 5 * @version V1.4.0
<> 135:176b8275d35d 6 * @date 16-December-2016
AnnaBridge 126:abea610beb85 7 * @brief Header file of RCC HAL Extension module.
AnnaBridge 126:abea610beb85 8 ******************************************************************************
AnnaBridge 126:abea610beb85 9 * @attention
AnnaBridge 126:abea610beb85 10 *
AnnaBridge 126:abea610beb85 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge 126:abea610beb85 12 *
AnnaBridge 126:abea610beb85 13 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 126:abea610beb85 14 * are permitted provided that the following conditions are met:
AnnaBridge 126:abea610beb85 15 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 126:abea610beb85 16 * this list of conditions and the following disclaimer.
AnnaBridge 126:abea610beb85 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 126:abea610beb85 18 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 126:abea610beb85 19 * and/or other materials provided with the distribution.
AnnaBridge 126:abea610beb85 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 126:abea610beb85 21 * may be used to endorse or promote products derived from this software
AnnaBridge 126:abea610beb85 22 * without specific prior written permission.
AnnaBridge 126:abea610beb85 23 *
AnnaBridge 126:abea610beb85 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 126:abea610beb85 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 126:abea610beb85 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 126:abea610beb85 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 126:abea610beb85 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 126:abea610beb85 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 126:abea610beb85 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 126:abea610beb85 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 126:abea610beb85 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 126:abea610beb85 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 126:abea610beb85 34 *
AnnaBridge 126:abea610beb85 35 ******************************************************************************
AnnaBridge 126:abea610beb85 36 */
AnnaBridge 126:abea610beb85 37
AnnaBridge 126:abea610beb85 38 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 126:abea610beb85 39 #ifndef __STM32F3xx_HAL_RCC_EX_H
AnnaBridge 126:abea610beb85 40 #define __STM32F3xx_HAL_RCC_EX_H
AnnaBridge 126:abea610beb85 41
AnnaBridge 126:abea610beb85 42 #ifdef __cplusplus
AnnaBridge 126:abea610beb85 43 extern "C" {
AnnaBridge 126:abea610beb85 44 #endif
AnnaBridge 126:abea610beb85 45
AnnaBridge 126:abea610beb85 46 /* Includes ------------------------------------------------------------------*/
AnnaBridge 126:abea610beb85 47 #include "stm32f3xx_hal_def.h"
AnnaBridge 126:abea610beb85 48
AnnaBridge 126:abea610beb85 49 /** @addtogroup STM32F3xx_HAL_Driver
AnnaBridge 126:abea610beb85 50 * @{
AnnaBridge 126:abea610beb85 51 */
AnnaBridge 126:abea610beb85 52
AnnaBridge 126:abea610beb85 53 /** @addtogroup RCCEx
AnnaBridge 126:abea610beb85 54 * @{
AnnaBridge 126:abea610beb85 55 */
AnnaBridge 126:abea610beb85 56
AnnaBridge 126:abea610beb85 57 /** @addtogroup RCCEx_Private_Macros
AnnaBridge 126:abea610beb85 58 * @{
AnnaBridge 126:abea610beb85 59 */
AnnaBridge 126:abea610beb85 60
AnnaBridge 126:abea610beb85 61 #if defined(RCC_CFGR_PLLNODIV)
AnnaBridge 126:abea610beb85 62 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \
AnnaBridge 126:abea610beb85 63 ((SOURCE) == RCC_MCO1SOURCE_LSI) || \
AnnaBridge 126:abea610beb85 64 ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
AnnaBridge 126:abea610beb85 65 ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \
AnnaBridge 126:abea610beb85 66 ((SOURCE) == RCC_MCO1SOURCE_HSI) || \
AnnaBridge 126:abea610beb85 67 ((SOURCE) == RCC_MCO1SOURCE_HSE) || \
AnnaBridge 126:abea610beb85 68 ((SOURCE) == RCC_MCO1SOURCE_PLLCLK) || \
AnnaBridge 126:abea610beb85 69 ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2))
AnnaBridge 126:abea610beb85 70 #else
AnnaBridge 126:abea610beb85 71 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \
AnnaBridge 126:abea610beb85 72 ((SOURCE) == RCC_MCO1SOURCE_LSI) || \
AnnaBridge 126:abea610beb85 73 ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
AnnaBridge 126:abea610beb85 74 ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \
AnnaBridge 126:abea610beb85 75 ((SOURCE) == RCC_MCO1SOURCE_HSI) || \
AnnaBridge 126:abea610beb85 76 ((SOURCE) == RCC_MCO1SOURCE_HSE) || \
AnnaBridge 126:abea610beb85 77 ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2))
AnnaBridge 126:abea610beb85 78 #endif /* RCC_CFGR_PLLNODIV */
AnnaBridge 126:abea610beb85 79
AnnaBridge 126:abea610beb85 80 #if defined(STM32F301x8) || defined(STM32F318xx)
AnnaBridge 126:abea610beb85 81 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | \
AnnaBridge 126:abea610beb85 82 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
AnnaBridge 126:abea610beb85 83 RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_I2S | \
AnnaBridge 126:abea610beb85 84 RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_TIM1 | \
AnnaBridge 126:abea610beb85 85 RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \
AnnaBridge 126:abea610beb85 86 RCC_PERIPHCLK_TIM17 | RCC_PERIPHCLK_RTC))
AnnaBridge 126:abea610beb85 87 #endif /* STM32F301x8 || STM32F318xx */
AnnaBridge 126:abea610beb85 88 #if defined(STM32F302x8)
AnnaBridge 126:abea610beb85 89 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | \
AnnaBridge 126:abea610beb85 90 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
AnnaBridge 126:abea610beb85 91 RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_I2S | \
AnnaBridge 126:abea610beb85 92 RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_TIM1 | \
AnnaBridge 126:abea610beb85 93 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB | \
AnnaBridge 126:abea610beb85 94 RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \
AnnaBridge 126:abea610beb85 95 RCC_PERIPHCLK_TIM17))
AnnaBridge 126:abea610beb85 96 #endif /* STM32F302x8 */
AnnaBridge 126:abea610beb85 97 #if defined(STM32F302xC)
AnnaBridge 126:abea610beb85 98 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
AnnaBridge 126:abea610beb85 99 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
AnnaBridge 126:abea610beb85 100 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
AnnaBridge 126:abea610beb85 101 RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_I2S | \
AnnaBridge 126:abea610beb85 102 RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC | \
AnnaBridge 126:abea610beb85 103 RCC_PERIPHCLK_USB))
AnnaBridge 126:abea610beb85 104 #endif /* STM32F302xC */
AnnaBridge 126:abea610beb85 105 #if defined(STM32F303xC)
AnnaBridge 126:abea610beb85 106 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
AnnaBridge 126:abea610beb85 107 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
AnnaBridge 126:abea610beb85 108 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
AnnaBridge 126:abea610beb85 109 RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \
AnnaBridge 126:abea610beb85 110 RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \
AnnaBridge 126:abea610beb85 111 RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC | \
AnnaBridge 126:abea610beb85 112 RCC_PERIPHCLK_USB))
AnnaBridge 126:abea610beb85 113 #endif /* STM32F303xC */
AnnaBridge 126:abea610beb85 114 #if defined(STM32F302xE)
AnnaBridge 126:abea610beb85 115 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
AnnaBridge 126:abea610beb85 116 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
AnnaBridge 126:abea610beb85 117 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
AnnaBridge 126:abea610beb85 118 RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_I2S | \
AnnaBridge 126:abea610beb85 119 RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC | \
AnnaBridge 126:abea610beb85 120 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_I2C3 | \
AnnaBridge 126:abea610beb85 121 RCC_PERIPHCLK_TIM2 | RCC_PERIPHCLK_TIM34 | \
AnnaBridge 126:abea610beb85 122 RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \
AnnaBridge 126:abea610beb85 123 RCC_PERIPHCLK_TIM17))
AnnaBridge 126:abea610beb85 124 #endif /* STM32F302xE */
AnnaBridge 126:abea610beb85 125 #if defined(STM32F303xE)
AnnaBridge 126:abea610beb85 126 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
AnnaBridge 126:abea610beb85 127 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
AnnaBridge 126:abea610beb85 128 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
AnnaBridge 126:abea610beb85 129 RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \
AnnaBridge 126:abea610beb85 130 RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \
AnnaBridge 126:abea610beb85 131 RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC | \
AnnaBridge 126:abea610beb85 132 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_I2C3 | \
AnnaBridge 126:abea610beb85 133 RCC_PERIPHCLK_TIM2 | RCC_PERIPHCLK_TIM34 | \
AnnaBridge 126:abea610beb85 134 RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \
AnnaBridge 126:abea610beb85 135 RCC_PERIPHCLK_TIM17 | RCC_PERIPHCLK_TIM20))
AnnaBridge 126:abea610beb85 136 #endif /* STM32F303xE */
AnnaBridge 126:abea610beb85 137 #if defined(STM32F398xx)
AnnaBridge 126:abea610beb85 138 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
AnnaBridge 126:abea610beb85 139 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
AnnaBridge 126:abea610beb85 140 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
AnnaBridge 126:abea610beb85 141 RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \
AnnaBridge 126:abea610beb85 142 RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \
AnnaBridge 126:abea610beb85 143 RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC | \
AnnaBridge 126:abea610beb85 144 RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_TIM2 | \
AnnaBridge 126:abea610beb85 145 RCC_PERIPHCLK_TIM34 | RCC_PERIPHCLK_TIM15 | \
AnnaBridge 126:abea610beb85 146 RCC_PERIPHCLK_TIM16 | RCC_PERIPHCLK_TIM17 | \
AnnaBridge 126:abea610beb85 147 RCC_PERIPHCLK_TIM20))
AnnaBridge 126:abea610beb85 148 #endif /* STM32F398xx */
AnnaBridge 126:abea610beb85 149 #if defined(STM32F358xx)
AnnaBridge 126:abea610beb85 150 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
AnnaBridge 126:abea610beb85 151 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
AnnaBridge 126:abea610beb85 152 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
AnnaBridge 126:abea610beb85 153 RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \
AnnaBridge 126:abea610beb85 154 RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \
AnnaBridge 126:abea610beb85 155 RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC))
AnnaBridge 126:abea610beb85 156 #endif /* STM32F358xx */
AnnaBridge 126:abea610beb85 157 #if defined(STM32F303x8)
AnnaBridge 126:abea610beb85 158 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | \
AnnaBridge 126:abea610beb85 159 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_ADC12 | \
AnnaBridge 126:abea610beb85 160 RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC))
AnnaBridge 126:abea610beb85 161 #endif /* STM32F303x8 */
AnnaBridge 126:abea610beb85 162 #if defined(STM32F334x8)
AnnaBridge 126:abea610beb85 163 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | \
AnnaBridge 126:abea610beb85 164 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_ADC12 | \
AnnaBridge 126:abea610beb85 165 RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_HRTIM1 | \
AnnaBridge 126:abea610beb85 166 RCC_PERIPHCLK_RTC))
AnnaBridge 126:abea610beb85 167 #endif /* STM32F334x8 */
AnnaBridge 126:abea610beb85 168 #if defined(STM32F328xx)
AnnaBridge 126:abea610beb85 169 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | \
AnnaBridge 126:abea610beb85 170 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_ADC12 | \
AnnaBridge 126:abea610beb85 171 RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC))
AnnaBridge 126:abea610beb85 172 #endif /* STM32F328xx */
AnnaBridge 126:abea610beb85 173 #if defined(STM32F373xC)
AnnaBridge 126:abea610beb85 174 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
AnnaBridge 126:abea610beb85 175 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
AnnaBridge 126:abea610beb85 176 RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_SDADC | \
AnnaBridge 126:abea610beb85 177 RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC | \
AnnaBridge 126:abea610beb85 178 RCC_PERIPHCLK_USB))
AnnaBridge 126:abea610beb85 179 #endif /* STM32F373xC */
AnnaBridge 126:abea610beb85 180 #if defined(STM32F378xx)
AnnaBridge 126:abea610beb85 181 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
AnnaBridge 126:abea610beb85 182 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
AnnaBridge 126:abea610beb85 183 RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_SDADC | \
AnnaBridge 126:abea610beb85 184 RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC))
AnnaBridge 126:abea610beb85 185 #endif /* STM32F378xx */
AnnaBridge 126:abea610beb85 186
AnnaBridge 126:abea610beb85 187 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
AnnaBridge 126:abea610beb85 188 #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK1) || \
AnnaBridge 126:abea610beb85 189 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
AnnaBridge 126:abea610beb85 190 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
AnnaBridge 126:abea610beb85 191 ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
AnnaBridge 126:abea610beb85 192 #define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \
AnnaBridge 126:abea610beb85 193 ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
AnnaBridge 126:abea610beb85 194 #define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_HSI) || \
AnnaBridge 126:abea610beb85 195 ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK))
AnnaBridge 126:abea610beb85 196 #define IS_RCC_ADC1PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC1PLLCLK_OFF) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV1) || \
AnnaBridge 126:abea610beb85 197 ((ADCCLK) == RCC_ADC1PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV4) || \
AnnaBridge 126:abea610beb85 198 ((ADCCLK) == RCC_ADC1PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV8) || \
AnnaBridge 126:abea610beb85 199 ((ADCCLK) == RCC_ADC1PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV12) || \
AnnaBridge 126:abea610beb85 200 ((ADCCLK) == RCC_ADC1PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV32) || \
AnnaBridge 126:abea610beb85 201 ((ADCCLK) == RCC_ADC1PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV128) || \
AnnaBridge 126:abea610beb85 202 ((ADCCLK) == RCC_ADC1PLLCLK_DIV256))
AnnaBridge 126:abea610beb85 203 #define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) || \
AnnaBridge 126:abea610beb85 204 ((SOURCE) == RCC_I2SCLKSOURCE_EXT))
AnnaBridge 126:abea610beb85 205 #define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \
AnnaBridge 126:abea610beb85 206 ((SOURCE) == RCC_TIM1CLK_PLLCLK))
AnnaBridge 126:abea610beb85 207 #define IS_RCC_TIM15CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM15CLK_HCLK) || \
AnnaBridge 126:abea610beb85 208 ((SOURCE) == RCC_TIM15CLK_PLLCLK))
AnnaBridge 126:abea610beb85 209 #define IS_RCC_TIM16CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM16CLK_HCLK) || \
AnnaBridge 126:abea610beb85 210 ((SOURCE) == RCC_TIM16CLK_PLLCLK))
AnnaBridge 126:abea610beb85 211 #define IS_RCC_TIM17CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM17CLK_HCLK) || \
AnnaBridge 126:abea610beb85 212 ((SOURCE) == RCC_TIM17CLK_PLLCLK))
AnnaBridge 126:abea610beb85 213 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
AnnaBridge 126:abea610beb85 214 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
AnnaBridge 126:abea610beb85 215 #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \
AnnaBridge 126:abea610beb85 216 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
AnnaBridge 126:abea610beb85 217 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
AnnaBridge 126:abea610beb85 218 ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
AnnaBridge 126:abea610beb85 219 #define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \
AnnaBridge 126:abea610beb85 220 ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
AnnaBridge 126:abea610beb85 221 #define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) || \
AnnaBridge 126:abea610beb85 222 ((ADCCLK) == RCC_ADC12PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) || \
AnnaBridge 126:abea610beb85 223 ((ADCCLK) == RCC_ADC12PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) || \
AnnaBridge 126:abea610beb85 224 ((ADCCLK) == RCC_ADC12PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) || \
AnnaBridge 126:abea610beb85 225 ((ADCCLK) == RCC_ADC12PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) || \
AnnaBridge 126:abea610beb85 226 ((ADCCLK) == RCC_ADC12PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) || \
AnnaBridge 126:abea610beb85 227 ((ADCCLK) == RCC_ADC12PLLCLK_DIV256))
AnnaBridge 126:abea610beb85 228 #define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) || \
AnnaBridge 126:abea610beb85 229 ((SOURCE) == RCC_I2SCLKSOURCE_EXT))
AnnaBridge 126:abea610beb85 230 #define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \
AnnaBridge 126:abea610beb85 231 ((SOURCE) == RCC_TIM1CLK_PLLCLK))
AnnaBridge 126:abea610beb85 232 #define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) || \
AnnaBridge 126:abea610beb85 233 ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \
AnnaBridge 126:abea610beb85 234 ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \
AnnaBridge 126:abea610beb85 235 ((SOURCE) == RCC_UART4CLKSOURCE_HSI))
AnnaBridge 126:abea610beb85 236 #define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) || \
AnnaBridge 126:abea610beb85 237 ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \
AnnaBridge 126:abea610beb85 238 ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \
AnnaBridge 126:abea610beb85 239 ((SOURCE) == RCC_UART5CLKSOURCE_HSI))
AnnaBridge 126:abea610beb85 240 #endif /* STM32F302xC || STM32F303xC || STM32F358xx */
AnnaBridge 126:abea610beb85 241 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
AnnaBridge 126:abea610beb85 242 #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \
AnnaBridge 126:abea610beb85 243 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
AnnaBridge 126:abea610beb85 244 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
AnnaBridge 126:abea610beb85 245 ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
AnnaBridge 126:abea610beb85 246 #define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \
AnnaBridge 126:abea610beb85 247 ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
AnnaBridge 126:abea610beb85 248 #define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_HSI) || \
AnnaBridge 126:abea610beb85 249 ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK))
AnnaBridge 126:abea610beb85 250 #define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) || \
AnnaBridge 126:abea610beb85 251 ((ADCCLK) == RCC_ADC12PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) || \
AnnaBridge 126:abea610beb85 252 ((ADCCLK) == RCC_ADC12PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) || \
AnnaBridge 126:abea610beb85 253 ((ADCCLK) == RCC_ADC12PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) || \
AnnaBridge 126:abea610beb85 254 ((ADCCLK) == RCC_ADC12PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) || \
AnnaBridge 126:abea610beb85 255 ((ADCCLK) == RCC_ADC12PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) || \
AnnaBridge 126:abea610beb85 256 ((ADCCLK) == RCC_ADC12PLLCLK_DIV256))
AnnaBridge 126:abea610beb85 257 #define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) || \
AnnaBridge 126:abea610beb85 258 ((SOURCE) == RCC_I2SCLKSOURCE_EXT))
AnnaBridge 126:abea610beb85 259 #define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \
AnnaBridge 126:abea610beb85 260 ((SOURCE) == RCC_TIM1CLK_PLLCLK))
AnnaBridge 126:abea610beb85 261 #define IS_RCC_TIM2CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM2CLK_HCLK) || \
AnnaBridge 126:abea610beb85 262 ((SOURCE) == RCC_TIM2CLK_PLLCLK))
AnnaBridge 126:abea610beb85 263 #define IS_RCC_TIM3CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM34CLK_HCLK) || \
AnnaBridge 126:abea610beb85 264 ((SOURCE) == RCC_TIM34CLK_PLLCLK))
AnnaBridge 126:abea610beb85 265 #define IS_RCC_TIM15CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM15CLK_HCLK) || \
AnnaBridge 126:abea610beb85 266 ((SOURCE) == RCC_TIM15CLK_PLLCLK))
AnnaBridge 126:abea610beb85 267 #define IS_RCC_TIM16CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM16CLK_HCLK) || \
AnnaBridge 126:abea610beb85 268 ((SOURCE) == RCC_TIM16CLK_PLLCLK))
AnnaBridge 126:abea610beb85 269 #define IS_RCC_TIM17CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM17CLK_HCLK) || \
AnnaBridge 126:abea610beb85 270 ((SOURCE) == RCC_TIM17CLK_PLLCLK))
AnnaBridge 126:abea610beb85 271 #define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) || \
AnnaBridge 126:abea610beb85 272 ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \
AnnaBridge 126:abea610beb85 273 ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \
AnnaBridge 126:abea610beb85 274 ((SOURCE) == RCC_UART4CLKSOURCE_HSI))
AnnaBridge 126:abea610beb85 275 #define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) || \
AnnaBridge 126:abea610beb85 276 ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \
AnnaBridge 126:abea610beb85 277 ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \
AnnaBridge 126:abea610beb85 278 ((SOURCE) == RCC_UART5CLKSOURCE_HSI))
AnnaBridge 126:abea610beb85 279 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
AnnaBridge 126:abea610beb85 280 #if defined(STM32F303xE) || defined(STM32F398xx)
AnnaBridge 126:abea610beb85 281 #define IS_RCC_TIM20CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM20CLK_HCLK) || \
AnnaBridge 126:abea610beb85 282 ((SOURCE) == RCC_TIM20CLK_PLLCLK))
AnnaBridge 126:abea610beb85 283 #endif /* STM32F303xE || STM32F398xx */
AnnaBridge 126:abea610beb85 284 #if defined(STM32F303xE) || defined(STM32F398xx)\
AnnaBridge 126:abea610beb85 285 || defined(STM32F303xC) || defined(STM32F358xx)
AnnaBridge 126:abea610beb85 286 #define IS_RCC_ADC34PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC34PLLCLK_OFF) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV1) || \
AnnaBridge 126:abea610beb85 287 ((ADCCLK) == RCC_ADC34PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV4) || \
AnnaBridge 126:abea610beb85 288 ((ADCCLK) == RCC_ADC34PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV8) || \
AnnaBridge 126:abea610beb85 289 ((ADCCLK) == RCC_ADC34PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV12) || \
AnnaBridge 126:abea610beb85 290 ((ADCCLK) == RCC_ADC34PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV32) || \
AnnaBridge 126:abea610beb85 291 ((ADCCLK) == RCC_ADC34PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV128) || \
AnnaBridge 126:abea610beb85 292 ((ADCCLK) == RCC_ADC34PLLCLK_DIV256))
AnnaBridge 126:abea610beb85 293 #define IS_RCC_TIM8CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM8CLK_HCLK) || \
AnnaBridge 126:abea610beb85 294 ((SOURCE) == RCC_TIM8CLK_PLLCLK))
AnnaBridge 126:abea610beb85 295 #endif /* STM32F303xC || STM32F303xE || STM32F398xx || STM32F358xx */
AnnaBridge 126:abea610beb85 296 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
AnnaBridge 126:abea610beb85 297 #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK1) || \
AnnaBridge 126:abea610beb85 298 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
AnnaBridge 126:abea610beb85 299 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
AnnaBridge 126:abea610beb85 300 ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
AnnaBridge 126:abea610beb85 301 #define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) || \
AnnaBridge 126:abea610beb85 302 ((ADCCLK) == RCC_ADC12PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) || \
AnnaBridge 126:abea610beb85 303 ((ADCCLK) == RCC_ADC12PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) || \
AnnaBridge 126:abea610beb85 304 ((ADCCLK) == RCC_ADC12PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) || \
AnnaBridge 126:abea610beb85 305 ((ADCCLK) == RCC_ADC12PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) || \
AnnaBridge 126:abea610beb85 306 ((ADCCLK) == RCC_ADC12PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) || \
AnnaBridge 126:abea610beb85 307 ((ADCCLK) == RCC_ADC12PLLCLK_DIV256))
AnnaBridge 126:abea610beb85 308 #define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \
AnnaBridge 126:abea610beb85 309 ((SOURCE) == RCC_TIM1CLK_PLLCLK))
AnnaBridge 126:abea610beb85 310 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
AnnaBridge 126:abea610beb85 311 #if defined(STM32F334x8)
AnnaBridge 126:abea610beb85 312 #define IS_RCC_HRTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_HRTIM1CLK_HCLK) || \
AnnaBridge 126:abea610beb85 313 ((SOURCE) == RCC_HRTIM1CLK_PLLCLK))
AnnaBridge 126:abea610beb85 314 #endif /* STM32F334x8 */
AnnaBridge 126:abea610beb85 315 #if defined(STM32F373xC) || defined(STM32F378xx)
AnnaBridge 126:abea610beb85 316 #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \
AnnaBridge 126:abea610beb85 317 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
AnnaBridge 126:abea610beb85 318 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
AnnaBridge 126:abea610beb85 319 ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
AnnaBridge 126:abea610beb85 320 #define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \
AnnaBridge 126:abea610beb85 321 ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
AnnaBridge 126:abea610beb85 322 #define IS_RCC_ADC1PCLK2_DIV(ADCCLK) (((ADCCLK) == RCC_ADC1PCLK2_DIV2) || ((ADCCLK) == RCC_ADC1PCLK2_DIV4) || \
AnnaBridge 126:abea610beb85 323 ((ADCCLK) == RCC_ADC1PCLK2_DIV6) || ((ADCCLK) == RCC_ADC1PCLK2_DIV8))
AnnaBridge 126:abea610beb85 324 #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \
AnnaBridge 126:abea610beb85 325 ((SOURCE) == RCC_CECCLKSOURCE_LSE))
AnnaBridge 126:abea610beb85 326 #define IS_RCC_SDADCSYSCLK_DIV(DIV) (((DIV) == RCC_SDADCSYSCLK_DIV1) || ((DIV) == RCC_SDADCSYSCLK_DIV2) || \
AnnaBridge 126:abea610beb85 327 ((DIV) == RCC_SDADCSYSCLK_DIV4) || ((DIV) == RCC_SDADCSYSCLK_DIV6) || \
AnnaBridge 126:abea610beb85 328 ((DIV) == RCC_SDADCSYSCLK_DIV8) || ((DIV) == RCC_SDADCSYSCLK_DIV10) || \
AnnaBridge 126:abea610beb85 329 ((DIV) == RCC_SDADCSYSCLK_DIV12) || ((DIV) == RCC_SDADCSYSCLK_DIV14) || \
AnnaBridge 126:abea610beb85 330 ((DIV) == RCC_SDADCSYSCLK_DIV16) || ((DIV) == RCC_SDADCSYSCLK_DIV20) || \
AnnaBridge 126:abea610beb85 331 ((DIV) == RCC_SDADCSYSCLK_DIV24) || ((DIV) == RCC_SDADCSYSCLK_DIV28) || \
AnnaBridge 126:abea610beb85 332 ((DIV) == RCC_SDADCSYSCLK_DIV32) || ((DIV) == RCC_SDADCSYSCLK_DIV36) || \
AnnaBridge 126:abea610beb85 333 ((DIV) == RCC_SDADCSYSCLK_DIV40) || ((DIV) == RCC_SDADCSYSCLK_DIV44) || \
AnnaBridge 126:abea610beb85 334 ((DIV) == RCC_SDADCSYSCLK_DIV48))
AnnaBridge 126:abea610beb85 335 #endif /* STM32F373xC || STM32F378xx */
AnnaBridge 126:abea610beb85 336 #if defined(STM32F302xE) || defined(STM32F303xE)\
AnnaBridge 126:abea610beb85 337 || defined(STM32F302xC) || defined(STM32F303xC)\
AnnaBridge 126:abea610beb85 338 || defined(STM32F302x8) \
AnnaBridge 126:abea610beb85 339 || defined(STM32F373xC)
AnnaBridge 126:abea610beb85 340 #define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_PLL) || \
AnnaBridge 126:abea610beb85 341 ((SOURCE) == RCC_USBCLKSOURCE_PLL_DIV1_5))
AnnaBridge 126:abea610beb85 342 #endif /* STM32F302xE || STM32F303xE || */
AnnaBridge 126:abea610beb85 343 /* STM32F302xC || STM32F303xC || */
AnnaBridge 126:abea610beb85 344 /* STM32F302x8 || */
AnnaBridge 126:abea610beb85 345 /* STM32F373xC */
AnnaBridge 126:abea610beb85 346 #if defined(RCC_CFGR_MCOPRE)
AnnaBridge 126:abea610beb85 347 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
AnnaBridge 126:abea610beb85 348 ((DIV) == RCC_MCODIV_4) || ((DIV) == RCC_MCODIV_8) || \
AnnaBridge 126:abea610beb85 349 ((DIV) == RCC_MCODIV_16) || ((DIV) == RCC_MCODIV_32) || \
AnnaBridge 126:abea610beb85 350 ((DIV) == RCC_MCODIV_64) || ((DIV) == RCC_MCODIV_128))
AnnaBridge 126:abea610beb85 351 #else
AnnaBridge 126:abea610beb85 352 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1))
AnnaBridge 126:abea610beb85 353 #endif /* RCC_CFGR_MCOPRE */
AnnaBridge 126:abea610beb85 354
AnnaBridge 126:abea610beb85 355 #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \
AnnaBridge 126:abea610beb85 356 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \
AnnaBridge 126:abea610beb85 357 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \
AnnaBridge 126:abea610beb85 358 ((__DRIVE__) == RCC_LSEDRIVE_HIGH))
AnnaBridge 126:abea610beb85 359
AnnaBridge 126:abea610beb85 360 /**
AnnaBridge 126:abea610beb85 361 * @}
AnnaBridge 126:abea610beb85 362 */
AnnaBridge 126:abea610beb85 363
AnnaBridge 126:abea610beb85 364 /* Exported types ------------------------------------------------------------*/
AnnaBridge 126:abea610beb85 365 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
AnnaBridge 126:abea610beb85 366 * @{
AnnaBridge 126:abea610beb85 367 */
AnnaBridge 126:abea610beb85 368
AnnaBridge 126:abea610beb85 369 /**
AnnaBridge 126:abea610beb85 370 * @brief RCC extended clocks structure definition
AnnaBridge 126:abea610beb85 371 */
AnnaBridge 126:abea610beb85 372 #if defined(STM32F301x8) || defined(STM32F318xx)
AnnaBridge 126:abea610beb85 373 typedef struct
AnnaBridge 126:abea610beb85 374 {
AnnaBridge 126:abea610beb85 375 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge 126:abea610beb85 376 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge 126:abea610beb85 377
AnnaBridge 126:abea610beb85 378 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
AnnaBridge 126:abea610beb85 379 This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge 126:abea610beb85 380
AnnaBridge 126:abea610beb85 381 uint32_t Usart1ClockSelection; /*!< USART1 clock source
AnnaBridge 126:abea610beb85 382 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
AnnaBridge 126:abea610beb85 383
AnnaBridge 126:abea610beb85 384 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
AnnaBridge 126:abea610beb85 385 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
AnnaBridge 126:abea610beb85 386
AnnaBridge 126:abea610beb85 387 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
AnnaBridge 126:abea610beb85 388 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
AnnaBridge 126:abea610beb85 389
AnnaBridge 126:abea610beb85 390 uint32_t I2c3ClockSelection; /*!< I2C3 clock source
AnnaBridge 126:abea610beb85 391 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
AnnaBridge 126:abea610beb85 392
AnnaBridge 126:abea610beb85 393 uint32_t Adc1ClockSelection; /*!< ADC1 clock source
AnnaBridge 126:abea610beb85 394 This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
AnnaBridge 126:abea610beb85 395
AnnaBridge 126:abea610beb85 396 uint32_t I2sClockSelection; /*!< I2S clock source
AnnaBridge 126:abea610beb85 397 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
AnnaBridge 126:abea610beb85 398
AnnaBridge 126:abea610beb85 399 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
AnnaBridge 126:abea610beb85 400 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
AnnaBridge 126:abea610beb85 401
AnnaBridge 126:abea610beb85 402 uint32_t Tim15ClockSelection; /*!< TIM15 clock source
AnnaBridge 126:abea610beb85 403 This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
AnnaBridge 126:abea610beb85 404
AnnaBridge 126:abea610beb85 405 uint32_t Tim16ClockSelection; /*!< TIM16 clock source
AnnaBridge 126:abea610beb85 406 This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
AnnaBridge 126:abea610beb85 407
AnnaBridge 126:abea610beb85 408 uint32_t Tim17ClockSelection; /*!< TIM17 clock source
AnnaBridge 126:abea610beb85 409 This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
AnnaBridge 126:abea610beb85 410 }RCC_PeriphCLKInitTypeDef;
AnnaBridge 126:abea610beb85 411 #endif /* STM32F301x8 || STM32F318xx */
AnnaBridge 126:abea610beb85 412
AnnaBridge 126:abea610beb85 413 #if defined(STM32F302x8)
AnnaBridge 126:abea610beb85 414 typedef struct
AnnaBridge 126:abea610beb85 415 {
AnnaBridge 126:abea610beb85 416 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge 126:abea610beb85 417 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge 126:abea610beb85 418
AnnaBridge 126:abea610beb85 419 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
AnnaBridge 126:abea610beb85 420 This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge 126:abea610beb85 421
AnnaBridge 126:abea610beb85 422 uint32_t Usart1ClockSelection; /*!< USART1 clock source
AnnaBridge 126:abea610beb85 423 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
AnnaBridge 126:abea610beb85 424
AnnaBridge 126:abea610beb85 425 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
AnnaBridge 126:abea610beb85 426 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
AnnaBridge 126:abea610beb85 427
AnnaBridge 126:abea610beb85 428 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
AnnaBridge 126:abea610beb85 429 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
AnnaBridge 126:abea610beb85 430
AnnaBridge 126:abea610beb85 431 uint32_t I2c3ClockSelection; /*!< I2C3 clock source
AnnaBridge 126:abea610beb85 432 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
AnnaBridge 126:abea610beb85 433
AnnaBridge 126:abea610beb85 434 uint32_t Adc1ClockSelection; /*!< ADC1 clock source
AnnaBridge 126:abea610beb85 435 This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
AnnaBridge 126:abea610beb85 436
AnnaBridge 126:abea610beb85 437 uint32_t I2sClockSelection; /*!< I2S clock source
AnnaBridge 126:abea610beb85 438 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
AnnaBridge 126:abea610beb85 439
AnnaBridge 126:abea610beb85 440 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
AnnaBridge 126:abea610beb85 441 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
AnnaBridge 126:abea610beb85 442
AnnaBridge 126:abea610beb85 443 uint32_t Tim15ClockSelection; /*!< TIM15 clock source
AnnaBridge 126:abea610beb85 444 This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
AnnaBridge 126:abea610beb85 445
AnnaBridge 126:abea610beb85 446 uint32_t Tim16ClockSelection; /*!< TIM16 clock source
AnnaBridge 126:abea610beb85 447 This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
AnnaBridge 126:abea610beb85 448
AnnaBridge 126:abea610beb85 449 uint32_t Tim17ClockSelection; /*!< TIM17 clock source
AnnaBridge 126:abea610beb85 450 This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
AnnaBridge 126:abea610beb85 451
AnnaBridge 126:abea610beb85 452 uint32_t USBClockSelection; /*!< USB clock source
AnnaBridge 126:abea610beb85 453 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
AnnaBridge 126:abea610beb85 454
AnnaBridge 126:abea610beb85 455 }RCC_PeriphCLKInitTypeDef;
AnnaBridge 126:abea610beb85 456 #endif /* STM32F302x8 */
AnnaBridge 126:abea610beb85 457
AnnaBridge 126:abea610beb85 458 #if defined(STM32F302xC)
AnnaBridge 126:abea610beb85 459 typedef struct
AnnaBridge 126:abea610beb85 460 {
AnnaBridge 126:abea610beb85 461 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge 126:abea610beb85 462 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge 126:abea610beb85 463
AnnaBridge 126:abea610beb85 464 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
AnnaBridge 126:abea610beb85 465 This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge 126:abea610beb85 466
AnnaBridge 126:abea610beb85 467 uint32_t Usart1ClockSelection; /*!< USART1 clock source
AnnaBridge 126:abea610beb85 468 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
AnnaBridge 126:abea610beb85 469
AnnaBridge 126:abea610beb85 470 uint32_t Usart2ClockSelection; /*!< USART2 clock source
AnnaBridge 126:abea610beb85 471 This parameter can be a value of @ref RCC_USART2_Clock_Source */
AnnaBridge 126:abea610beb85 472
AnnaBridge 126:abea610beb85 473 uint32_t Usart3ClockSelection; /*!< USART3 clock source
AnnaBridge 126:abea610beb85 474 This parameter can be a value of @ref RCC_USART3_Clock_Source */
AnnaBridge 126:abea610beb85 475
AnnaBridge 126:abea610beb85 476 uint32_t Uart4ClockSelection; /*!< UART4 clock source
AnnaBridge 126:abea610beb85 477 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
AnnaBridge 126:abea610beb85 478
AnnaBridge 126:abea610beb85 479 uint32_t Uart5ClockSelection; /*!< UART5 clock source
AnnaBridge 126:abea610beb85 480 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
AnnaBridge 126:abea610beb85 481
AnnaBridge 126:abea610beb85 482 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
AnnaBridge 126:abea610beb85 483 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
AnnaBridge 126:abea610beb85 484
AnnaBridge 126:abea610beb85 485 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
AnnaBridge 126:abea610beb85 486 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
AnnaBridge 126:abea610beb85 487
AnnaBridge 126:abea610beb85 488 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
AnnaBridge 126:abea610beb85 489 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
AnnaBridge 126:abea610beb85 490
AnnaBridge 126:abea610beb85 491 uint32_t I2sClockSelection; /*!< I2S clock source
AnnaBridge 126:abea610beb85 492 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
AnnaBridge 126:abea610beb85 493
AnnaBridge 126:abea610beb85 494 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
AnnaBridge 126:abea610beb85 495 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
AnnaBridge 126:abea610beb85 496
AnnaBridge 126:abea610beb85 497 uint32_t USBClockSelection; /*!< USB clock source
AnnaBridge 126:abea610beb85 498 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
AnnaBridge 126:abea610beb85 499
AnnaBridge 126:abea610beb85 500 }RCC_PeriphCLKInitTypeDef;
AnnaBridge 126:abea610beb85 501 #endif /* STM32F302xC */
AnnaBridge 126:abea610beb85 502
AnnaBridge 126:abea610beb85 503 #if defined(STM32F303xC)
AnnaBridge 126:abea610beb85 504 typedef struct
AnnaBridge 126:abea610beb85 505 {
AnnaBridge 126:abea610beb85 506 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge 126:abea610beb85 507 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge 126:abea610beb85 508
AnnaBridge 126:abea610beb85 509 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
AnnaBridge 126:abea610beb85 510 This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge 126:abea610beb85 511
AnnaBridge 126:abea610beb85 512 uint32_t Usart1ClockSelection; /*!< USART1 clock source
AnnaBridge 126:abea610beb85 513 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
AnnaBridge 126:abea610beb85 514
AnnaBridge 126:abea610beb85 515 uint32_t Usart2ClockSelection; /*!< USART2 clock source
AnnaBridge 126:abea610beb85 516 This parameter can be a value of @ref RCC_USART2_Clock_Source */
AnnaBridge 126:abea610beb85 517
AnnaBridge 126:abea610beb85 518 uint32_t Usart3ClockSelection; /*!< USART3 clock source
AnnaBridge 126:abea610beb85 519 This parameter can be a value of @ref RCC_USART3_Clock_Source */
AnnaBridge 126:abea610beb85 520
AnnaBridge 126:abea610beb85 521 uint32_t Uart4ClockSelection; /*!< UART4 clock source
AnnaBridge 126:abea610beb85 522 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
AnnaBridge 126:abea610beb85 523
AnnaBridge 126:abea610beb85 524 uint32_t Uart5ClockSelection; /*!< UART5 clock source
AnnaBridge 126:abea610beb85 525 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
AnnaBridge 126:abea610beb85 526
AnnaBridge 126:abea610beb85 527 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
AnnaBridge 126:abea610beb85 528 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
AnnaBridge 126:abea610beb85 529
AnnaBridge 126:abea610beb85 530 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
AnnaBridge 126:abea610beb85 531 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
AnnaBridge 126:abea610beb85 532
AnnaBridge 126:abea610beb85 533 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
AnnaBridge 126:abea610beb85 534 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
AnnaBridge 126:abea610beb85 535
AnnaBridge 126:abea610beb85 536 uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
AnnaBridge 126:abea610beb85 537 This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
AnnaBridge 126:abea610beb85 538
AnnaBridge 126:abea610beb85 539 uint32_t I2sClockSelection; /*!< I2S clock source
AnnaBridge 126:abea610beb85 540 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
AnnaBridge 126:abea610beb85 541
AnnaBridge 126:abea610beb85 542 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
AnnaBridge 126:abea610beb85 543 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
AnnaBridge 126:abea610beb85 544
AnnaBridge 126:abea610beb85 545 uint32_t Tim8ClockSelection; /*!< TIM8 clock source
AnnaBridge 126:abea610beb85 546 This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
AnnaBridge 126:abea610beb85 547
AnnaBridge 126:abea610beb85 548 uint32_t USBClockSelection; /*!< USB clock source
AnnaBridge 126:abea610beb85 549 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
AnnaBridge 126:abea610beb85 550
AnnaBridge 126:abea610beb85 551 }RCC_PeriphCLKInitTypeDef;
AnnaBridge 126:abea610beb85 552 #endif /* STM32F303xC */
AnnaBridge 126:abea610beb85 553
AnnaBridge 126:abea610beb85 554 #if defined(STM32F302xE)
AnnaBridge 126:abea610beb85 555 typedef struct
AnnaBridge 126:abea610beb85 556 {
AnnaBridge 126:abea610beb85 557 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge 126:abea610beb85 558 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge 126:abea610beb85 559
AnnaBridge 126:abea610beb85 560 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
AnnaBridge 126:abea610beb85 561 This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge 126:abea610beb85 562
AnnaBridge 126:abea610beb85 563 uint32_t Usart1ClockSelection; /*!< USART1 clock source
AnnaBridge 126:abea610beb85 564 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
AnnaBridge 126:abea610beb85 565
AnnaBridge 126:abea610beb85 566 uint32_t Usart2ClockSelection; /*!< USART2 clock source
AnnaBridge 126:abea610beb85 567 This parameter can be a value of @ref RCC_USART2_Clock_Source */
AnnaBridge 126:abea610beb85 568
AnnaBridge 126:abea610beb85 569 uint32_t Usart3ClockSelection; /*!< USART3 clock source
AnnaBridge 126:abea610beb85 570 This parameter can be a value of @ref RCC_USART3_Clock_Source */
AnnaBridge 126:abea610beb85 571
AnnaBridge 126:abea610beb85 572 uint32_t Uart4ClockSelection; /*!< UART4 clock source
AnnaBridge 126:abea610beb85 573 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
AnnaBridge 126:abea610beb85 574
AnnaBridge 126:abea610beb85 575 uint32_t Uart5ClockSelection; /*!< UART5 clock source
AnnaBridge 126:abea610beb85 576 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
AnnaBridge 126:abea610beb85 577
AnnaBridge 126:abea610beb85 578 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
AnnaBridge 126:abea610beb85 579 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
AnnaBridge 126:abea610beb85 580
AnnaBridge 126:abea610beb85 581 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
AnnaBridge 126:abea610beb85 582 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
AnnaBridge 126:abea610beb85 583
AnnaBridge 126:abea610beb85 584 uint32_t I2c3ClockSelection; /*!< I2C3 clock source
AnnaBridge 126:abea610beb85 585 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
AnnaBridge 126:abea610beb85 586
AnnaBridge 126:abea610beb85 587 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
AnnaBridge 126:abea610beb85 588 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
AnnaBridge 126:abea610beb85 589
AnnaBridge 126:abea610beb85 590 uint32_t I2sClockSelection; /*!< I2S clock source
AnnaBridge 126:abea610beb85 591 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
AnnaBridge 126:abea610beb85 592
AnnaBridge 126:abea610beb85 593 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
AnnaBridge 126:abea610beb85 594 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
AnnaBridge 126:abea610beb85 595
AnnaBridge 126:abea610beb85 596 uint32_t Tim2ClockSelection; /*!< TIM2 clock source
AnnaBridge 126:abea610beb85 597 This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */
AnnaBridge 126:abea610beb85 598
AnnaBridge 126:abea610beb85 599 uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source
AnnaBridge 126:abea610beb85 600 This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */
AnnaBridge 126:abea610beb85 601
AnnaBridge 126:abea610beb85 602 uint32_t Tim15ClockSelection; /*!< TIM15 clock source
AnnaBridge 126:abea610beb85 603 This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
AnnaBridge 126:abea610beb85 604
AnnaBridge 126:abea610beb85 605 uint32_t Tim16ClockSelection; /*!< TIM16 clock source
AnnaBridge 126:abea610beb85 606 This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
AnnaBridge 126:abea610beb85 607
AnnaBridge 126:abea610beb85 608 uint32_t Tim17ClockSelection; /*!< TIM17 clock source
AnnaBridge 126:abea610beb85 609 This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
AnnaBridge 126:abea610beb85 610
AnnaBridge 126:abea610beb85 611 uint32_t USBClockSelection; /*!< USB clock source
AnnaBridge 126:abea610beb85 612 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
AnnaBridge 126:abea610beb85 613
AnnaBridge 126:abea610beb85 614 }RCC_PeriphCLKInitTypeDef;
AnnaBridge 126:abea610beb85 615 #endif /* STM32F302xE */
AnnaBridge 126:abea610beb85 616
AnnaBridge 126:abea610beb85 617 #if defined(STM32F303xE)
AnnaBridge 126:abea610beb85 618 typedef struct
AnnaBridge 126:abea610beb85 619 {
AnnaBridge 126:abea610beb85 620 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge 126:abea610beb85 621 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge 126:abea610beb85 622
AnnaBridge 126:abea610beb85 623 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
AnnaBridge 126:abea610beb85 624 This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge 126:abea610beb85 625
AnnaBridge 126:abea610beb85 626 uint32_t Usart1ClockSelection; /*!< USART1 clock source
AnnaBridge 126:abea610beb85 627 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
AnnaBridge 126:abea610beb85 628
AnnaBridge 126:abea610beb85 629 uint32_t Usart2ClockSelection; /*!< USART2 clock source
AnnaBridge 126:abea610beb85 630 This parameter can be a value of @ref RCC_USART2_Clock_Source */
AnnaBridge 126:abea610beb85 631
AnnaBridge 126:abea610beb85 632 uint32_t Usart3ClockSelection; /*!< USART3 clock source
AnnaBridge 126:abea610beb85 633 This parameter can be a value of @ref RCC_USART3_Clock_Source */
AnnaBridge 126:abea610beb85 634
AnnaBridge 126:abea610beb85 635 uint32_t Uart4ClockSelection; /*!< UART4 clock source
AnnaBridge 126:abea610beb85 636 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
AnnaBridge 126:abea610beb85 637
AnnaBridge 126:abea610beb85 638 uint32_t Uart5ClockSelection; /*!< UART5 clock source
AnnaBridge 126:abea610beb85 639 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
AnnaBridge 126:abea610beb85 640
AnnaBridge 126:abea610beb85 641 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
AnnaBridge 126:abea610beb85 642 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
AnnaBridge 126:abea610beb85 643
AnnaBridge 126:abea610beb85 644 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
AnnaBridge 126:abea610beb85 645 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
AnnaBridge 126:abea610beb85 646
AnnaBridge 126:abea610beb85 647 uint32_t I2c3ClockSelection; /*!< I2C3 clock source
AnnaBridge 126:abea610beb85 648 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
AnnaBridge 126:abea610beb85 649
AnnaBridge 126:abea610beb85 650 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
AnnaBridge 126:abea610beb85 651 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
AnnaBridge 126:abea610beb85 652
AnnaBridge 126:abea610beb85 653 uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
AnnaBridge 126:abea610beb85 654 This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
AnnaBridge 126:abea610beb85 655
AnnaBridge 126:abea610beb85 656 uint32_t I2sClockSelection; /*!< I2S clock source
AnnaBridge 126:abea610beb85 657 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
AnnaBridge 126:abea610beb85 658
AnnaBridge 126:abea610beb85 659 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
AnnaBridge 126:abea610beb85 660 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
AnnaBridge 126:abea610beb85 661
AnnaBridge 126:abea610beb85 662 uint32_t Tim2ClockSelection; /*!< TIM2 clock source
AnnaBridge 126:abea610beb85 663 This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */
AnnaBridge 126:abea610beb85 664
AnnaBridge 126:abea610beb85 665 uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source
AnnaBridge 126:abea610beb85 666 This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */
AnnaBridge 126:abea610beb85 667
AnnaBridge 126:abea610beb85 668 uint32_t Tim8ClockSelection; /*!< TIM8 clock source
AnnaBridge 126:abea610beb85 669 This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
AnnaBridge 126:abea610beb85 670
AnnaBridge 126:abea610beb85 671 uint32_t Tim15ClockSelection; /*!< TIM15 clock source
AnnaBridge 126:abea610beb85 672 This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
AnnaBridge 126:abea610beb85 673
AnnaBridge 126:abea610beb85 674 uint32_t Tim16ClockSelection; /*!< TIM16 clock source
AnnaBridge 126:abea610beb85 675 This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
AnnaBridge 126:abea610beb85 676
AnnaBridge 126:abea610beb85 677 uint32_t Tim17ClockSelection; /*!< TIM17 clock source
AnnaBridge 126:abea610beb85 678 This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
AnnaBridge 126:abea610beb85 679
AnnaBridge 126:abea610beb85 680 uint32_t Tim20ClockSelection; /*!< TIM20 clock source
AnnaBridge 126:abea610beb85 681 This parameter can be a value of @ref RCCEx_TIM20_Clock_Source */
AnnaBridge 126:abea610beb85 682
AnnaBridge 126:abea610beb85 683 uint32_t USBClockSelection; /*!< USB clock source
AnnaBridge 126:abea610beb85 684 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
AnnaBridge 126:abea610beb85 685
AnnaBridge 126:abea610beb85 686 }RCC_PeriphCLKInitTypeDef;
AnnaBridge 126:abea610beb85 687 #endif /* STM32F303xE */
AnnaBridge 126:abea610beb85 688
AnnaBridge 126:abea610beb85 689 #if defined(STM32F398xx)
AnnaBridge 126:abea610beb85 690 typedef struct
AnnaBridge 126:abea610beb85 691 {
AnnaBridge 126:abea610beb85 692 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge 126:abea610beb85 693 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge 126:abea610beb85 694
AnnaBridge 126:abea610beb85 695 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
AnnaBridge 126:abea610beb85 696 This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge 126:abea610beb85 697
AnnaBridge 126:abea610beb85 698 uint32_t Usart1ClockSelection; /*!< USART1 clock source
AnnaBridge 126:abea610beb85 699 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
AnnaBridge 126:abea610beb85 700
AnnaBridge 126:abea610beb85 701 uint32_t Usart2ClockSelection; /*!< USART2 clock source
AnnaBridge 126:abea610beb85 702 This parameter can be a value of @ref RCC_USART2_Clock_Source */
AnnaBridge 126:abea610beb85 703
AnnaBridge 126:abea610beb85 704 uint32_t Usart3ClockSelection; /*!< USART3 clock source
AnnaBridge 126:abea610beb85 705 This parameter can be a value of @ref RCC_USART3_Clock_Source */
AnnaBridge 126:abea610beb85 706
AnnaBridge 126:abea610beb85 707 uint32_t Uart4ClockSelection; /*!< UART4 clock source
AnnaBridge 126:abea610beb85 708 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
AnnaBridge 126:abea610beb85 709
AnnaBridge 126:abea610beb85 710 uint32_t Uart5ClockSelection; /*!< UART5 clock source
AnnaBridge 126:abea610beb85 711 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
AnnaBridge 126:abea610beb85 712
AnnaBridge 126:abea610beb85 713 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
AnnaBridge 126:abea610beb85 714 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
AnnaBridge 126:abea610beb85 715
AnnaBridge 126:abea610beb85 716 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
AnnaBridge 126:abea610beb85 717 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
AnnaBridge 126:abea610beb85 718
AnnaBridge 126:abea610beb85 719 uint32_t I2c3ClockSelection; /*!< I2C3 clock source
AnnaBridge 126:abea610beb85 720 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
AnnaBridge 126:abea610beb85 721
AnnaBridge 126:abea610beb85 722 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
AnnaBridge 126:abea610beb85 723 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
AnnaBridge 126:abea610beb85 724
AnnaBridge 126:abea610beb85 725 uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
AnnaBridge 126:abea610beb85 726 This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
AnnaBridge 126:abea610beb85 727
AnnaBridge 126:abea610beb85 728 uint32_t I2sClockSelection; /*!< I2S clock source
AnnaBridge 126:abea610beb85 729 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
AnnaBridge 126:abea610beb85 730
AnnaBridge 126:abea610beb85 731 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
AnnaBridge 126:abea610beb85 732 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
AnnaBridge 126:abea610beb85 733
AnnaBridge 126:abea610beb85 734 uint32_t Tim2ClockSelection; /*!< TIM2 clock source
AnnaBridge 126:abea610beb85 735 This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */
AnnaBridge 126:abea610beb85 736
AnnaBridge 126:abea610beb85 737 uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source
AnnaBridge 126:abea610beb85 738 This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */
AnnaBridge 126:abea610beb85 739
AnnaBridge 126:abea610beb85 740 uint32_t Tim8ClockSelection; /*!< TIM8 clock source
AnnaBridge 126:abea610beb85 741 This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
AnnaBridge 126:abea610beb85 742
AnnaBridge 126:abea610beb85 743 uint32_t Tim15ClockSelection; /*!< TIM15 clock source
AnnaBridge 126:abea610beb85 744 This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
AnnaBridge 126:abea610beb85 745
AnnaBridge 126:abea610beb85 746 uint32_t Tim16ClockSelection; /*!< TIM16 clock source
AnnaBridge 126:abea610beb85 747 This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
AnnaBridge 126:abea610beb85 748
AnnaBridge 126:abea610beb85 749 uint32_t Tim17ClockSelection; /*!< TIM17 clock source
AnnaBridge 126:abea610beb85 750 This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
AnnaBridge 126:abea610beb85 751
AnnaBridge 126:abea610beb85 752 uint32_t Tim20ClockSelection; /*!< TIM20 clock source
AnnaBridge 126:abea610beb85 753 This parameter can be a value of @ref RCCEx_TIM20_Clock_Source */
AnnaBridge 126:abea610beb85 754
AnnaBridge 126:abea610beb85 755 }RCC_PeriphCLKInitTypeDef;
AnnaBridge 126:abea610beb85 756 #endif /* STM32F398xx */
AnnaBridge 126:abea610beb85 757
AnnaBridge 126:abea610beb85 758 #if defined(STM32F358xx)
AnnaBridge 126:abea610beb85 759 typedef struct
AnnaBridge 126:abea610beb85 760 {
AnnaBridge 126:abea610beb85 761 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge 126:abea610beb85 762 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge 126:abea610beb85 763
AnnaBridge 126:abea610beb85 764 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
AnnaBridge 126:abea610beb85 765 This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge 126:abea610beb85 766
AnnaBridge 126:abea610beb85 767 uint32_t Usart1ClockSelection; /*!< USART1 clock source
AnnaBridge 126:abea610beb85 768 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
AnnaBridge 126:abea610beb85 769
AnnaBridge 126:abea610beb85 770 uint32_t Usart2ClockSelection; /*!< USART2 clock source
AnnaBridge 126:abea610beb85 771 This parameter can be a value of @ref RCC_USART2_Clock_Source */
AnnaBridge 126:abea610beb85 772
AnnaBridge 126:abea610beb85 773 uint32_t Usart3ClockSelection; /*!< USART3 clock source
AnnaBridge 126:abea610beb85 774 This parameter can be a value of @ref RCC_USART3_Clock_Source */
AnnaBridge 126:abea610beb85 775
AnnaBridge 126:abea610beb85 776 uint32_t Uart4ClockSelection; /*!< UART4 clock source
AnnaBridge 126:abea610beb85 777 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
AnnaBridge 126:abea610beb85 778
AnnaBridge 126:abea610beb85 779 uint32_t Uart5ClockSelection; /*!< UART5 clock source
AnnaBridge 126:abea610beb85 780 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
AnnaBridge 126:abea610beb85 781
AnnaBridge 126:abea610beb85 782 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
AnnaBridge 126:abea610beb85 783 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
AnnaBridge 126:abea610beb85 784
AnnaBridge 126:abea610beb85 785 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
AnnaBridge 126:abea610beb85 786 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
AnnaBridge 126:abea610beb85 787
AnnaBridge 126:abea610beb85 788 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
AnnaBridge 126:abea610beb85 789 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
AnnaBridge 126:abea610beb85 790
AnnaBridge 126:abea610beb85 791 uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
AnnaBridge 126:abea610beb85 792 This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
AnnaBridge 126:abea610beb85 793
AnnaBridge 126:abea610beb85 794 uint32_t I2sClockSelection; /*!< I2S clock source
AnnaBridge 126:abea610beb85 795 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
AnnaBridge 126:abea610beb85 796
AnnaBridge 126:abea610beb85 797 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
AnnaBridge 126:abea610beb85 798 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
AnnaBridge 126:abea610beb85 799
AnnaBridge 126:abea610beb85 800 uint32_t Tim8ClockSelection; /*!< TIM8 clock source
AnnaBridge 126:abea610beb85 801 This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
AnnaBridge 126:abea610beb85 802
AnnaBridge 126:abea610beb85 803 }RCC_PeriphCLKInitTypeDef;
AnnaBridge 126:abea610beb85 804 #endif /* STM32F358xx */
AnnaBridge 126:abea610beb85 805
AnnaBridge 126:abea610beb85 806 #if defined(STM32F303x8)
AnnaBridge 126:abea610beb85 807 typedef struct
AnnaBridge 126:abea610beb85 808 {
AnnaBridge 126:abea610beb85 809 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge 126:abea610beb85 810 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge 126:abea610beb85 811
AnnaBridge 126:abea610beb85 812 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
AnnaBridge 126:abea610beb85 813 This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge 126:abea610beb85 814
AnnaBridge 126:abea610beb85 815 uint32_t Usart1ClockSelection; /*!< USART1 clock source
AnnaBridge 126:abea610beb85 816 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
AnnaBridge 126:abea610beb85 817
AnnaBridge 126:abea610beb85 818 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
AnnaBridge 126:abea610beb85 819 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
AnnaBridge 126:abea610beb85 820
AnnaBridge 126:abea610beb85 821 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
AnnaBridge 126:abea610beb85 822 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
AnnaBridge 126:abea610beb85 823
AnnaBridge 126:abea610beb85 824 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
AnnaBridge 126:abea610beb85 825 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
AnnaBridge 126:abea610beb85 826
AnnaBridge 126:abea610beb85 827 }RCC_PeriphCLKInitTypeDef;
AnnaBridge 126:abea610beb85 828 #endif /* STM32F303x8 */
AnnaBridge 126:abea610beb85 829
AnnaBridge 126:abea610beb85 830 #if defined(STM32F334x8)
AnnaBridge 126:abea610beb85 831 typedef struct
AnnaBridge 126:abea610beb85 832 {
AnnaBridge 126:abea610beb85 833 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge 126:abea610beb85 834 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge 126:abea610beb85 835
AnnaBridge 126:abea610beb85 836 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
AnnaBridge 126:abea610beb85 837 This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge 126:abea610beb85 838
AnnaBridge 126:abea610beb85 839 uint32_t Usart1ClockSelection; /*!< USART1 clock source
AnnaBridge 126:abea610beb85 840 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
AnnaBridge 126:abea610beb85 841
AnnaBridge 126:abea610beb85 842 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
AnnaBridge 126:abea610beb85 843 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
AnnaBridge 126:abea610beb85 844
AnnaBridge 126:abea610beb85 845 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
AnnaBridge 126:abea610beb85 846 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
AnnaBridge 126:abea610beb85 847
AnnaBridge 126:abea610beb85 848 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
AnnaBridge 126:abea610beb85 849 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
AnnaBridge 126:abea610beb85 850
AnnaBridge 126:abea610beb85 851 uint32_t Hrtim1ClockSelection; /*!< HRTIM1 clock source
AnnaBridge 126:abea610beb85 852 This parameter can be a value of @ref RCCEx_HRTIM1_Clock_Source */
AnnaBridge 126:abea610beb85 853
AnnaBridge 126:abea610beb85 854 }RCC_PeriphCLKInitTypeDef;
AnnaBridge 126:abea610beb85 855 #endif /* STM32F334x8 */
AnnaBridge 126:abea610beb85 856
AnnaBridge 126:abea610beb85 857 #if defined(STM32F328xx)
AnnaBridge 126:abea610beb85 858 typedef struct
AnnaBridge 126:abea610beb85 859 {
AnnaBridge 126:abea610beb85 860 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge 126:abea610beb85 861 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge 126:abea610beb85 862
AnnaBridge 126:abea610beb85 863 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
AnnaBridge 126:abea610beb85 864 This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge 126:abea610beb85 865
AnnaBridge 126:abea610beb85 866 uint32_t Usart1ClockSelection; /*!< USART1 clock source
AnnaBridge 126:abea610beb85 867 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
AnnaBridge 126:abea610beb85 868
AnnaBridge 126:abea610beb85 869 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
AnnaBridge 126:abea610beb85 870 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
AnnaBridge 126:abea610beb85 871
AnnaBridge 126:abea610beb85 872 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
AnnaBridge 126:abea610beb85 873 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
AnnaBridge 126:abea610beb85 874
AnnaBridge 126:abea610beb85 875 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
AnnaBridge 126:abea610beb85 876 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
AnnaBridge 126:abea610beb85 877
AnnaBridge 126:abea610beb85 878 }RCC_PeriphCLKInitTypeDef;
AnnaBridge 126:abea610beb85 879 #endif /* STM32F328xx */
AnnaBridge 126:abea610beb85 880
AnnaBridge 126:abea610beb85 881 #if defined(STM32F373xC)
AnnaBridge 126:abea610beb85 882 typedef struct
AnnaBridge 126:abea610beb85 883 {
AnnaBridge 126:abea610beb85 884 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge 126:abea610beb85 885 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge 126:abea610beb85 886
AnnaBridge 126:abea610beb85 887 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
AnnaBridge 126:abea610beb85 888 This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge 126:abea610beb85 889
AnnaBridge 126:abea610beb85 890 uint32_t Usart1ClockSelection; /*!< USART1 clock source
AnnaBridge 126:abea610beb85 891 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
AnnaBridge 126:abea610beb85 892
AnnaBridge 126:abea610beb85 893 uint32_t Usart2ClockSelection; /*!< USART2 clock source
AnnaBridge 126:abea610beb85 894 This parameter can be a value of @ref RCC_USART2_Clock_Source */
AnnaBridge 126:abea610beb85 895
AnnaBridge 126:abea610beb85 896 uint32_t Usart3ClockSelection; /*!< USART3 clock source
AnnaBridge 126:abea610beb85 897 This parameter can be a value of @ref RCC_USART3_Clock_Source */
AnnaBridge 126:abea610beb85 898
AnnaBridge 126:abea610beb85 899 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
AnnaBridge 126:abea610beb85 900 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
AnnaBridge 126:abea610beb85 901
AnnaBridge 126:abea610beb85 902 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
AnnaBridge 126:abea610beb85 903 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
AnnaBridge 126:abea610beb85 904
AnnaBridge 126:abea610beb85 905 uint32_t Adc1ClockSelection; /*!< ADC1 clock source
AnnaBridge 126:abea610beb85 906 This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
AnnaBridge 126:abea610beb85 907
AnnaBridge 126:abea610beb85 908 uint32_t SdadcClockSelection; /*!< SDADC clock prescaler
AnnaBridge 126:abea610beb85 909 This parameter can be a value of @ref RCCEx_SDADC_Clock_Prescaler */
AnnaBridge 126:abea610beb85 910
AnnaBridge 126:abea610beb85 911 uint32_t CecClockSelection; /*!< HDMI CEC clock source
AnnaBridge 126:abea610beb85 912 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
AnnaBridge 126:abea610beb85 913
AnnaBridge 126:abea610beb85 914 uint32_t USBClockSelection; /*!< USB clock source
AnnaBridge 126:abea610beb85 915 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
AnnaBridge 126:abea610beb85 916
AnnaBridge 126:abea610beb85 917 }RCC_PeriphCLKInitTypeDef;
AnnaBridge 126:abea610beb85 918 #endif /* STM32F373xC */
AnnaBridge 126:abea610beb85 919
AnnaBridge 126:abea610beb85 920 #if defined(STM32F378xx)
AnnaBridge 126:abea610beb85 921 typedef struct
AnnaBridge 126:abea610beb85 922 {
AnnaBridge 126:abea610beb85 923 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge 126:abea610beb85 924 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge 126:abea610beb85 925
AnnaBridge 126:abea610beb85 926 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
AnnaBridge 126:abea610beb85 927 This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge 126:abea610beb85 928
AnnaBridge 126:abea610beb85 929 uint32_t Usart1ClockSelection; /*!< USART1 clock source
AnnaBridge 126:abea610beb85 930 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
AnnaBridge 126:abea610beb85 931
AnnaBridge 126:abea610beb85 932 uint32_t Usart2ClockSelection; /*!< USART2 clock source
AnnaBridge 126:abea610beb85 933 This parameter can be a value of @ref RCC_USART2_Clock_Source */
AnnaBridge 126:abea610beb85 934
AnnaBridge 126:abea610beb85 935 uint32_t Usart3ClockSelection; /*!< USART3 clock source
AnnaBridge 126:abea610beb85 936 This parameter can be a value of @ref RCC_USART3_Clock_Source */
AnnaBridge 126:abea610beb85 937
AnnaBridge 126:abea610beb85 938 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
AnnaBridge 126:abea610beb85 939 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
AnnaBridge 126:abea610beb85 940
AnnaBridge 126:abea610beb85 941 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
AnnaBridge 126:abea610beb85 942 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
AnnaBridge 126:abea610beb85 943
AnnaBridge 126:abea610beb85 944 uint32_t Adc1ClockSelection; /*!< ADC1 clock source
AnnaBridge 126:abea610beb85 945 This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
AnnaBridge 126:abea610beb85 946
AnnaBridge 126:abea610beb85 947 uint32_t SdadcClockSelection; /*!< SDADC clock prescaler
AnnaBridge 126:abea610beb85 948 This parameter can be a value of @ref RCCEx_SDADC_Clock_Prescaler */
AnnaBridge 126:abea610beb85 949
AnnaBridge 126:abea610beb85 950 uint32_t CecClockSelection; /*!< HDMI CEC clock source
AnnaBridge 126:abea610beb85 951 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
AnnaBridge 126:abea610beb85 952
AnnaBridge 126:abea610beb85 953 }RCC_PeriphCLKInitTypeDef;
AnnaBridge 126:abea610beb85 954 #endif /* STM32F378xx */
AnnaBridge 126:abea610beb85 955
AnnaBridge 126:abea610beb85 956 /**
AnnaBridge 126:abea610beb85 957 * @}
AnnaBridge 126:abea610beb85 958 */
AnnaBridge 126:abea610beb85 959
AnnaBridge 126:abea610beb85 960 /* Exported constants --------------------------------------------------------*/
AnnaBridge 126:abea610beb85 961 /** @defgroup RCCEx_Exported_Constants RCC Extended Exported Constants
AnnaBridge 126:abea610beb85 962 * @{
AnnaBridge 126:abea610beb85 963 */
AnnaBridge 126:abea610beb85 964 /** @defgroup RCCEx_MCO_Clock_Source RCC Extended MCO Clock Source
AnnaBridge 126:abea610beb85 965 * @{
AnnaBridge 126:abea610beb85 966 */
AnnaBridge 126:abea610beb85 967 #define RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK
AnnaBridge 126:abea610beb85 968 #define RCC_MCO1SOURCE_LSI RCC_CFGR_MCO_LSI
AnnaBridge 126:abea610beb85 969 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO_LSE
AnnaBridge 126:abea610beb85 970 #define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
AnnaBridge 126:abea610beb85 971 #define RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI
AnnaBridge 126:abea610beb85 972 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE
AnnaBridge 126:abea610beb85 973 #if defined(RCC_CFGR_PLLNODIV)
AnnaBridge 126:abea610beb85 974 #define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_PLLNODIV | RCC_CFGR_MCO_PLL)
AnnaBridge 126:abea610beb85 975 #endif /* RCC_CFGR_PLLNODIV */
AnnaBridge 126:abea610beb85 976 #define RCC_MCO1SOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL
AnnaBridge 126:abea610beb85 977
AnnaBridge 126:abea610beb85 978 /**
AnnaBridge 126:abea610beb85 979 * @}
AnnaBridge 126:abea610beb85 980 */
AnnaBridge 126:abea610beb85 981
AnnaBridge 126:abea610beb85 982 /** @defgroup RCCEx_Periph_Clock_Selection RCC Extended Periph Clock Selection
AnnaBridge 126:abea610beb85 983 * @{
AnnaBridge 126:abea610beb85 984 */
AnnaBridge 126:abea610beb85 985 #if defined(STM32F301x8) || defined(STM32F318xx)
<> 135:176b8275d35d 986 #define RCC_PERIPHCLK_USART1 (0x00000001U)
<> 135:176b8275d35d 987 #define RCC_PERIPHCLK_I2C1 (0x00000020U)
<> 135:176b8275d35d 988 #define RCC_PERIPHCLK_I2C2 (0x00000040U)
<> 135:176b8275d35d 989 #define RCC_PERIPHCLK_ADC1 (0x00000080U)
<> 135:176b8275d35d 990 #define RCC_PERIPHCLK_I2S (0x00000200U)
<> 135:176b8275d35d 991 #define RCC_PERIPHCLK_TIM1 (0x00001000U)
<> 135:176b8275d35d 992 #define RCC_PERIPHCLK_I2C3 (0x00008000U)
<> 135:176b8275d35d 993 #define RCC_PERIPHCLK_RTC (0x00010000U)
<> 135:176b8275d35d 994 #define RCC_PERIPHCLK_TIM15 (0x00040000U)
<> 135:176b8275d35d 995 #define RCC_PERIPHCLK_TIM16 (0x00080000U)
<> 135:176b8275d35d 996 #define RCC_PERIPHCLK_TIM17 (0x00100000U)
AnnaBridge 126:abea610beb85 997
AnnaBridge 126:abea610beb85 998 #endif /* STM32F301x8 || STM32F318xx */
AnnaBridge 126:abea610beb85 999
AnnaBridge 126:abea610beb85 1000 #if defined(STM32F302x8)
<> 135:176b8275d35d 1001 #define RCC_PERIPHCLK_USART1 (0x00000001U)
<> 135:176b8275d35d 1002 #define RCC_PERIPHCLK_I2C1 (0x00000020U)
<> 135:176b8275d35d 1003 #define RCC_PERIPHCLK_I2C2 (0x00000040U)
<> 135:176b8275d35d 1004 #define RCC_PERIPHCLK_ADC1 (0x00000080U)
<> 135:176b8275d35d 1005 #define RCC_PERIPHCLK_I2S (0x00000200U)
<> 135:176b8275d35d 1006 #define RCC_PERIPHCLK_TIM1 (0x00001000U)
<> 135:176b8275d35d 1007 #define RCC_PERIPHCLK_I2C3 (0x00008000U)
<> 135:176b8275d35d 1008 #define RCC_PERIPHCLK_RTC (0x00010000U)
<> 135:176b8275d35d 1009 #define RCC_PERIPHCLK_USB (0x00020000U)
<> 135:176b8275d35d 1010 #define RCC_PERIPHCLK_TIM15 (0x00040000U)
<> 135:176b8275d35d 1011 #define RCC_PERIPHCLK_TIM16 (0x00080000U)
<> 135:176b8275d35d 1012 #define RCC_PERIPHCLK_TIM17 (0x00100000U)
AnnaBridge 126:abea610beb85 1013
AnnaBridge 126:abea610beb85 1014
AnnaBridge 126:abea610beb85 1015 #endif /* STM32F302x8 */
AnnaBridge 126:abea610beb85 1016
AnnaBridge 126:abea610beb85 1017 #if defined(STM32F302xC)
<> 135:176b8275d35d 1018 #define RCC_PERIPHCLK_USART1 (0x00000001U)
<> 135:176b8275d35d 1019 #define RCC_PERIPHCLK_USART2 (0x00000002U)
<> 135:176b8275d35d 1020 #define RCC_PERIPHCLK_USART3 (0x00000004U)
<> 135:176b8275d35d 1021 #define RCC_PERIPHCLK_UART4 (0x00000008U)
<> 135:176b8275d35d 1022 #define RCC_PERIPHCLK_UART5 (0x00000010U)
<> 135:176b8275d35d 1023 #define RCC_PERIPHCLK_I2C1 (0x00000020U)
<> 135:176b8275d35d 1024 #define RCC_PERIPHCLK_I2C2 (0x00000040U)
<> 135:176b8275d35d 1025 #define RCC_PERIPHCLK_ADC12 (0x00000080U)
<> 135:176b8275d35d 1026 #define RCC_PERIPHCLK_I2S (0x00000200U)
<> 135:176b8275d35d 1027 #define RCC_PERIPHCLK_TIM1 (0x00001000U)
<> 135:176b8275d35d 1028 #define RCC_PERIPHCLK_RTC (0x00010000U)
<> 135:176b8275d35d 1029 #define RCC_PERIPHCLK_USB (0x00020000U)
AnnaBridge 126:abea610beb85 1030
AnnaBridge 126:abea610beb85 1031 #endif /* STM32F302xC */
AnnaBridge 126:abea610beb85 1032
AnnaBridge 126:abea610beb85 1033 #if defined(STM32F303xC)
<> 135:176b8275d35d 1034 #define RCC_PERIPHCLK_USART1 (0x00000001U)
<> 135:176b8275d35d 1035 #define RCC_PERIPHCLK_USART2 (0x00000002U)
<> 135:176b8275d35d 1036 #define RCC_PERIPHCLK_USART3 (0x00000004U)
<> 135:176b8275d35d 1037 #define RCC_PERIPHCLK_UART4 (0x00000008U)
<> 135:176b8275d35d 1038 #define RCC_PERIPHCLK_UART5 (0x00000010U)
<> 135:176b8275d35d 1039 #define RCC_PERIPHCLK_I2C1 (0x00000020U)
<> 135:176b8275d35d 1040 #define RCC_PERIPHCLK_I2C2 (0x00000040U)
<> 135:176b8275d35d 1041 #define RCC_PERIPHCLK_ADC12 (0x00000080U)
<> 135:176b8275d35d 1042 #define RCC_PERIPHCLK_ADC34 (0x00000100U)
<> 135:176b8275d35d 1043 #define RCC_PERIPHCLK_I2S (0x00000200U)
<> 135:176b8275d35d 1044 #define RCC_PERIPHCLK_TIM1 (0x00001000U)
<> 135:176b8275d35d 1045 #define RCC_PERIPHCLK_TIM8 (0x00002000U)
<> 135:176b8275d35d 1046 #define RCC_PERIPHCLK_RTC (0x00010000U)
<> 135:176b8275d35d 1047 #define RCC_PERIPHCLK_USB (0x00020000U)
AnnaBridge 126:abea610beb85 1048
AnnaBridge 126:abea610beb85 1049 #endif /* STM32F303xC */
AnnaBridge 126:abea610beb85 1050
AnnaBridge 126:abea610beb85 1051 #if defined(STM32F302xE)
<> 135:176b8275d35d 1052 #define RCC_PERIPHCLK_USART1 (0x00000001U)
<> 135:176b8275d35d 1053 #define RCC_PERIPHCLK_USART2 (0x00000002U)
<> 135:176b8275d35d 1054 #define RCC_PERIPHCLK_USART3 (0x00000004U)
<> 135:176b8275d35d 1055 #define RCC_PERIPHCLK_UART4 (0x00000008U)
<> 135:176b8275d35d 1056 #define RCC_PERIPHCLK_UART5 (0x00000010U)
<> 135:176b8275d35d 1057 #define RCC_PERIPHCLK_I2C1 (0x00000020U)
<> 135:176b8275d35d 1058 #define RCC_PERIPHCLK_I2C2 (0x00000040U)
<> 135:176b8275d35d 1059 #define RCC_PERIPHCLK_ADC12 (0x00000080U)
<> 135:176b8275d35d 1060 #define RCC_PERIPHCLK_I2S (0x00000200U)
<> 135:176b8275d35d 1061 #define RCC_PERIPHCLK_TIM1 (0x00001000U)
<> 135:176b8275d35d 1062 #define RCC_PERIPHCLK_RTC (0x00010000U)
<> 135:176b8275d35d 1063 #define RCC_PERIPHCLK_USB (0x00020000U)
<> 135:176b8275d35d 1064 #define RCC_PERIPHCLK_I2C3 (0x00040000U)
<> 135:176b8275d35d 1065 #define RCC_PERIPHCLK_TIM2 (0x00100000U)
<> 135:176b8275d35d 1066 #define RCC_PERIPHCLK_TIM34 (0x00200000U)
<> 135:176b8275d35d 1067 #define RCC_PERIPHCLK_TIM15 (0x00400000U)
<> 135:176b8275d35d 1068 #define RCC_PERIPHCLK_TIM16 (0x00800000U)
<> 135:176b8275d35d 1069 #define RCC_PERIPHCLK_TIM17 (0x01000000U)
AnnaBridge 126:abea610beb85 1070
AnnaBridge 126:abea610beb85 1071 #endif /* STM32F302xE */
AnnaBridge 126:abea610beb85 1072
AnnaBridge 126:abea610beb85 1073 #if defined(STM32F303xE)
<> 135:176b8275d35d 1074 #define RCC_PERIPHCLK_USART1 (0x00000001U)
<> 135:176b8275d35d 1075 #define RCC_PERIPHCLK_USART2 (0x00000002U)
<> 135:176b8275d35d 1076 #define RCC_PERIPHCLK_USART3 (0x00000004U)
<> 135:176b8275d35d 1077 #define RCC_PERIPHCLK_UART4 (0x00000008U)
<> 135:176b8275d35d 1078 #define RCC_PERIPHCLK_UART5 (0x00000010U)
<> 135:176b8275d35d 1079 #define RCC_PERIPHCLK_I2C1 (0x00000020U)
<> 135:176b8275d35d 1080 #define RCC_PERIPHCLK_I2C2 (0x00000040U)
<> 135:176b8275d35d 1081 #define RCC_PERIPHCLK_ADC12 (0x00000080U)
<> 135:176b8275d35d 1082 #define RCC_PERIPHCLK_ADC34 (0x00000100U)
<> 135:176b8275d35d 1083 #define RCC_PERIPHCLK_I2S (0x00000200U)
<> 135:176b8275d35d 1084 #define RCC_PERIPHCLK_TIM1 (0x00001000U)
<> 135:176b8275d35d 1085 #define RCC_PERIPHCLK_TIM8 (0x00002000U)
<> 135:176b8275d35d 1086 #define RCC_PERIPHCLK_RTC (0x00010000U)
<> 135:176b8275d35d 1087 #define RCC_PERIPHCLK_USB (0x00020000U)
<> 135:176b8275d35d 1088 #define RCC_PERIPHCLK_I2C3 (0x00040000U)
<> 135:176b8275d35d 1089 #define RCC_PERIPHCLK_TIM2 (0x00100000U)
<> 135:176b8275d35d 1090 #define RCC_PERIPHCLK_TIM34 (0x00200000U)
<> 135:176b8275d35d 1091 #define RCC_PERIPHCLK_TIM15 (0x00400000U)
<> 135:176b8275d35d 1092 #define RCC_PERIPHCLK_TIM16 (0x00800000U)
<> 135:176b8275d35d 1093 #define RCC_PERIPHCLK_TIM17 (0x01000000U)
<> 135:176b8275d35d 1094 #define RCC_PERIPHCLK_TIM20 (0x02000000U)
AnnaBridge 126:abea610beb85 1095
AnnaBridge 126:abea610beb85 1096 #endif /* STM32F303xE */
AnnaBridge 126:abea610beb85 1097
AnnaBridge 126:abea610beb85 1098 #if defined(STM32F398xx)
<> 135:176b8275d35d 1099 #define RCC_PERIPHCLK_USART1 (0x00000001U)
<> 135:176b8275d35d 1100 #define RCC_PERIPHCLK_USART2 (0x00000002U)
<> 135:176b8275d35d 1101 #define RCC_PERIPHCLK_USART3 (0x00000004U)
<> 135:176b8275d35d 1102 #define RCC_PERIPHCLK_UART4 (0x00000008U)
<> 135:176b8275d35d 1103 #define RCC_PERIPHCLK_UART5 (0x00000010U)
<> 135:176b8275d35d 1104 #define RCC_PERIPHCLK_I2C1 (0x00000020U)
<> 135:176b8275d35d 1105 #define RCC_PERIPHCLK_I2C2 (0x00000040U)
<> 135:176b8275d35d 1106 #define RCC_PERIPHCLK_ADC12 (0x00000080U)
<> 135:176b8275d35d 1107 #define RCC_PERIPHCLK_ADC34 (0x00000100U)
<> 135:176b8275d35d 1108 #define RCC_PERIPHCLK_I2S (0x00000200U)
<> 135:176b8275d35d 1109 #define RCC_PERIPHCLK_TIM1 (0x00001000U)
<> 135:176b8275d35d 1110 #define RCC_PERIPHCLK_TIM8 (0x00002000U)
<> 135:176b8275d35d 1111 #define RCC_PERIPHCLK_RTC (0x00010000U)
<> 135:176b8275d35d 1112 #define RCC_PERIPHCLK_I2C3 (0x00040000U)
<> 135:176b8275d35d 1113 #define RCC_PERIPHCLK_TIM2 (0x00100000U)
<> 135:176b8275d35d 1114 #define RCC_PERIPHCLK_TIM34 (0x00200000U)
<> 135:176b8275d35d 1115 #define RCC_PERIPHCLK_TIM15 (0x00400000U)
<> 135:176b8275d35d 1116 #define RCC_PERIPHCLK_TIM16 (0x00800000U)
<> 135:176b8275d35d 1117 #define RCC_PERIPHCLK_TIM17 (0x01000000U)
<> 135:176b8275d35d 1118 #define RCC_PERIPHCLK_TIM20 (0x02000000U)
AnnaBridge 126:abea610beb85 1119
AnnaBridge 126:abea610beb85 1120
AnnaBridge 126:abea610beb85 1121 #endif /* STM32F398xx */
AnnaBridge 126:abea610beb85 1122
AnnaBridge 126:abea610beb85 1123 #if defined(STM32F358xx)
<> 135:176b8275d35d 1124 #define RCC_PERIPHCLK_USART1 (0x00000001U)
<> 135:176b8275d35d 1125 #define RCC_PERIPHCLK_USART2 (0x00000002U)
<> 135:176b8275d35d 1126 #define RCC_PERIPHCLK_USART3 (0x00000004U)
<> 135:176b8275d35d 1127 #define RCC_PERIPHCLK_UART4 (0x00000008U)
<> 135:176b8275d35d 1128 #define RCC_PERIPHCLK_UART5 (0x00000010U)
<> 135:176b8275d35d 1129 #define RCC_PERIPHCLK_I2C1 (0x00000020U)
<> 135:176b8275d35d 1130 #define RCC_PERIPHCLK_I2C2 (0x00000040U)
<> 135:176b8275d35d 1131 #define RCC_PERIPHCLK_ADC12 (0x00000080U)
<> 135:176b8275d35d 1132 #define RCC_PERIPHCLK_ADC34 (0x00000100U)
<> 135:176b8275d35d 1133 #define RCC_PERIPHCLK_I2S (0x00000200U)
<> 135:176b8275d35d 1134 #define RCC_PERIPHCLK_TIM1 (0x00001000U)
<> 135:176b8275d35d 1135 #define RCC_PERIPHCLK_TIM8 (0x00002000U)
<> 135:176b8275d35d 1136 #define RCC_PERIPHCLK_RTC (0x00010000U)
AnnaBridge 126:abea610beb85 1137
AnnaBridge 126:abea610beb85 1138 #endif /* STM32F358xx */
AnnaBridge 126:abea610beb85 1139
AnnaBridge 126:abea610beb85 1140 #if defined(STM32F303x8)
<> 135:176b8275d35d 1141 #define RCC_PERIPHCLK_USART1 (0x00000001U)
<> 135:176b8275d35d 1142 #define RCC_PERIPHCLK_I2C1 (0x00000020U)
<> 135:176b8275d35d 1143 #define RCC_PERIPHCLK_ADC12 (0x00000080U)
<> 135:176b8275d35d 1144 #define RCC_PERIPHCLK_TIM1 (0x00001000U)
<> 135:176b8275d35d 1145 #define RCC_PERIPHCLK_RTC (0x00010000U)
AnnaBridge 126:abea610beb85 1146
AnnaBridge 126:abea610beb85 1147 #endif /* STM32F303x8 */
AnnaBridge 126:abea610beb85 1148
AnnaBridge 126:abea610beb85 1149 #if defined(STM32F334x8)
<> 135:176b8275d35d 1150 #define RCC_PERIPHCLK_USART1 (0x00000001U)
<> 135:176b8275d35d 1151 #define RCC_PERIPHCLK_I2C1 (0x00000020U)
<> 135:176b8275d35d 1152 #define RCC_PERIPHCLK_ADC12 (0x00000080U)
<> 135:176b8275d35d 1153 #define RCC_PERIPHCLK_TIM1 (0x00001000U)
<> 135:176b8275d35d 1154 #define RCC_PERIPHCLK_HRTIM1 (0x00004000U)
<> 135:176b8275d35d 1155 #define RCC_PERIPHCLK_RTC (0x00010000U)
AnnaBridge 126:abea610beb85 1156
AnnaBridge 126:abea610beb85 1157
AnnaBridge 126:abea610beb85 1158 #endif /* STM32F334x8 */
AnnaBridge 126:abea610beb85 1159
AnnaBridge 126:abea610beb85 1160 #if defined(STM32F328xx)
<> 135:176b8275d35d 1161 #define RCC_PERIPHCLK_USART1 (0x00000001U)
<> 135:176b8275d35d 1162 #define RCC_PERIPHCLK_I2C1 (0x00000020U)
<> 135:176b8275d35d 1163 #define RCC_PERIPHCLK_ADC12 (0x00000080U)
<> 135:176b8275d35d 1164 #define RCC_PERIPHCLK_TIM1 (0x00001000U)
<> 135:176b8275d35d 1165 #define RCC_PERIPHCLK_RTC (0x00010000U)
AnnaBridge 126:abea610beb85 1166
AnnaBridge 126:abea610beb85 1167 #endif /* STM32F328xx */
AnnaBridge 126:abea610beb85 1168
AnnaBridge 126:abea610beb85 1169 #if defined(STM32F373xC)
<> 135:176b8275d35d 1170 #define RCC_PERIPHCLK_USART1 (0x00000001U)
<> 135:176b8275d35d 1171 #define RCC_PERIPHCLK_USART2 (0x00000002U)
<> 135:176b8275d35d 1172 #define RCC_PERIPHCLK_USART3 (0x00000004U)
<> 135:176b8275d35d 1173 #define RCC_PERIPHCLK_I2C1 (0x00000020U)
<> 135:176b8275d35d 1174 #define RCC_PERIPHCLK_I2C2 (0x00000040U)
<> 135:176b8275d35d 1175 #define RCC_PERIPHCLK_ADC1 (0x00000080U)
<> 135:176b8275d35d 1176 #define RCC_PERIPHCLK_CEC (0x00000400U)
<> 135:176b8275d35d 1177 #define RCC_PERIPHCLK_SDADC (0x00000800U)
<> 135:176b8275d35d 1178 #define RCC_PERIPHCLK_RTC (0x00010000U)
<> 135:176b8275d35d 1179 #define RCC_PERIPHCLK_USB (0x00020000U)
AnnaBridge 126:abea610beb85 1180
AnnaBridge 126:abea610beb85 1181 #endif /* STM32F373xC */
AnnaBridge 126:abea610beb85 1182
AnnaBridge 126:abea610beb85 1183 #if defined(STM32F378xx)
<> 135:176b8275d35d 1184 #define RCC_PERIPHCLK_USART1 (0x00000001U)
<> 135:176b8275d35d 1185 #define RCC_PERIPHCLK_USART2 (0x00000002U)
<> 135:176b8275d35d 1186 #define RCC_PERIPHCLK_USART3 (0x00000004U)
<> 135:176b8275d35d 1187 #define RCC_PERIPHCLK_I2C1 (0x00000020U)
<> 135:176b8275d35d 1188 #define RCC_PERIPHCLK_I2C2 (0x00000040U)
<> 135:176b8275d35d 1189 #define RCC_PERIPHCLK_ADC1 (0x00000080U)
<> 135:176b8275d35d 1190 #define RCC_PERIPHCLK_CEC (0x00000400U)
<> 135:176b8275d35d 1191 #define RCC_PERIPHCLK_SDADC (0x00000800U)
<> 135:176b8275d35d 1192 #define RCC_PERIPHCLK_RTC (0x00010000U)
AnnaBridge 126:abea610beb85 1193
AnnaBridge 126:abea610beb85 1194 #endif /* STM32F378xx */
AnnaBridge 126:abea610beb85 1195 /**
AnnaBridge 126:abea610beb85 1196 * @}
AnnaBridge 126:abea610beb85 1197 */
AnnaBridge 126:abea610beb85 1198
AnnaBridge 126:abea610beb85 1199 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
AnnaBridge 126:abea610beb85 1200
AnnaBridge 126:abea610beb85 1201 /** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
AnnaBridge 126:abea610beb85 1202 * @{
AnnaBridge 126:abea610beb85 1203 */
AnnaBridge 126:abea610beb85 1204 #define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK1
AnnaBridge 126:abea610beb85 1205 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
AnnaBridge 126:abea610beb85 1206 #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
AnnaBridge 126:abea610beb85 1207 #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
AnnaBridge 126:abea610beb85 1208
AnnaBridge 126:abea610beb85 1209 /**
AnnaBridge 126:abea610beb85 1210 * @}
AnnaBridge 126:abea610beb85 1211 */
AnnaBridge 126:abea610beb85 1212
AnnaBridge 126:abea610beb85 1213 /** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
AnnaBridge 126:abea610beb85 1214 * @{
AnnaBridge 126:abea610beb85 1215 */
AnnaBridge 126:abea610beb85 1216 #define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
AnnaBridge 126:abea610beb85 1217 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
AnnaBridge 126:abea610beb85 1218
AnnaBridge 126:abea610beb85 1219 /**
AnnaBridge 126:abea610beb85 1220 * @}
AnnaBridge 126:abea610beb85 1221 */
AnnaBridge 126:abea610beb85 1222
AnnaBridge 126:abea610beb85 1223 /** @defgroup RCCEx_I2C3_Clock_Source RCC Extended I2C3 Clock Source
AnnaBridge 126:abea610beb85 1224 * @{
AnnaBridge 126:abea610beb85 1225 */
AnnaBridge 126:abea610beb85 1226 #define RCC_I2C3CLKSOURCE_HSI RCC_CFGR3_I2C3SW_HSI
AnnaBridge 126:abea610beb85 1227 #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CFGR3_I2C3SW_SYSCLK
AnnaBridge 126:abea610beb85 1228
AnnaBridge 126:abea610beb85 1229 /**
AnnaBridge 126:abea610beb85 1230 * @}
AnnaBridge 126:abea610beb85 1231 */
AnnaBridge 126:abea610beb85 1232
AnnaBridge 126:abea610beb85 1233 /** @defgroup RCCEx_ADC1_Clock_Source RCC Extended ADC1 Clock Source
AnnaBridge 126:abea610beb85 1234 * @{
AnnaBridge 126:abea610beb85 1235 */
AnnaBridge 126:abea610beb85 1236 #define RCC_ADC1PLLCLK_OFF RCC_CFGR2_ADC1PRES_NO
AnnaBridge 126:abea610beb85 1237 #define RCC_ADC1PLLCLK_DIV1 RCC_CFGR2_ADC1PRES_DIV1
AnnaBridge 126:abea610beb85 1238 #define RCC_ADC1PLLCLK_DIV2 RCC_CFGR2_ADC1PRES_DIV2
AnnaBridge 126:abea610beb85 1239 #define RCC_ADC1PLLCLK_DIV4 RCC_CFGR2_ADC1PRES_DIV4
AnnaBridge 126:abea610beb85 1240 #define RCC_ADC1PLLCLK_DIV6 RCC_CFGR2_ADC1PRES_DIV6
AnnaBridge 126:abea610beb85 1241 #define RCC_ADC1PLLCLK_DIV8 RCC_CFGR2_ADC1PRES_DIV8
AnnaBridge 126:abea610beb85 1242 #define RCC_ADC1PLLCLK_DIV10 RCC_CFGR2_ADC1PRES_DIV10
AnnaBridge 126:abea610beb85 1243 #define RCC_ADC1PLLCLK_DIV12 RCC_CFGR2_ADC1PRES_DIV12
AnnaBridge 126:abea610beb85 1244 #define RCC_ADC1PLLCLK_DIV16 RCC_CFGR2_ADC1PRES_DIV16
AnnaBridge 126:abea610beb85 1245 #define RCC_ADC1PLLCLK_DIV32 RCC_CFGR2_ADC1PRES_DIV32
AnnaBridge 126:abea610beb85 1246 #define RCC_ADC1PLLCLK_DIV64 RCC_CFGR2_ADC1PRES_DIV64
AnnaBridge 126:abea610beb85 1247 #define RCC_ADC1PLLCLK_DIV128 RCC_CFGR2_ADC1PRES_DIV128
AnnaBridge 126:abea610beb85 1248 #define RCC_ADC1PLLCLK_DIV256 RCC_CFGR2_ADC1PRES_DIV256
AnnaBridge 126:abea610beb85 1249
AnnaBridge 126:abea610beb85 1250 /**
AnnaBridge 126:abea610beb85 1251 * @}
AnnaBridge 126:abea610beb85 1252 */
AnnaBridge 126:abea610beb85 1253
AnnaBridge 126:abea610beb85 1254 /** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source
AnnaBridge 126:abea610beb85 1255 * @{
AnnaBridge 126:abea610beb85 1256 */
AnnaBridge 126:abea610beb85 1257 #define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK
AnnaBridge 126:abea610beb85 1258 #define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT
AnnaBridge 126:abea610beb85 1259
AnnaBridge 126:abea610beb85 1260 /**
AnnaBridge 126:abea610beb85 1261 * @}
AnnaBridge 126:abea610beb85 1262 */
AnnaBridge 126:abea610beb85 1263
AnnaBridge 126:abea610beb85 1264 /** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
AnnaBridge 126:abea610beb85 1265 * @{
AnnaBridge 126:abea610beb85 1266 */
AnnaBridge 126:abea610beb85 1267 #define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
AnnaBridge 126:abea610beb85 1268 #define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
AnnaBridge 126:abea610beb85 1269
AnnaBridge 126:abea610beb85 1270 /**
AnnaBridge 126:abea610beb85 1271 * @}
AnnaBridge 126:abea610beb85 1272 */
AnnaBridge 126:abea610beb85 1273
AnnaBridge 126:abea610beb85 1274 /** @defgroup RCCEx_TIM15_Clock_Source RCC Extended TIM15 Clock Source
AnnaBridge 126:abea610beb85 1275 * @{
AnnaBridge 126:abea610beb85 1276 */
AnnaBridge 126:abea610beb85 1277 #define RCC_TIM15CLK_HCLK RCC_CFGR3_TIM15SW_HCLK
AnnaBridge 126:abea610beb85 1278 #define RCC_TIM15CLK_PLLCLK RCC_CFGR3_TIM15SW_PLL
AnnaBridge 126:abea610beb85 1279
AnnaBridge 126:abea610beb85 1280 /**
AnnaBridge 126:abea610beb85 1281 * @}
AnnaBridge 126:abea610beb85 1282 */
AnnaBridge 126:abea610beb85 1283
AnnaBridge 126:abea610beb85 1284 /** @defgroup RCCEx_TIM16_Clock_Source RCC Extended TIM16 Clock Source
AnnaBridge 126:abea610beb85 1285 * @{
AnnaBridge 126:abea610beb85 1286 */
AnnaBridge 126:abea610beb85 1287 #define RCC_TIM16CLK_HCLK RCC_CFGR3_TIM16SW_HCLK
AnnaBridge 126:abea610beb85 1288 #define RCC_TIM16CLK_PLLCLK RCC_CFGR3_TIM16SW_PLL
AnnaBridge 126:abea610beb85 1289
AnnaBridge 126:abea610beb85 1290 /**
AnnaBridge 126:abea610beb85 1291 * @}
AnnaBridge 126:abea610beb85 1292 */
AnnaBridge 126:abea610beb85 1293
AnnaBridge 126:abea610beb85 1294 /** @defgroup RCCEx_TIM17_Clock_Source RCC Extended TIM17 Clock Source
AnnaBridge 126:abea610beb85 1295 * @{
AnnaBridge 126:abea610beb85 1296 */
AnnaBridge 126:abea610beb85 1297 #define RCC_TIM17CLK_HCLK RCC_CFGR3_TIM17SW_HCLK
AnnaBridge 126:abea610beb85 1298 #define RCC_TIM17CLK_PLLCLK RCC_CFGR3_TIM17SW_PLL
AnnaBridge 126:abea610beb85 1299
AnnaBridge 126:abea610beb85 1300 /**
AnnaBridge 126:abea610beb85 1301 * @}
AnnaBridge 126:abea610beb85 1302 */
AnnaBridge 126:abea610beb85 1303
AnnaBridge 126:abea610beb85 1304 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
AnnaBridge 126:abea610beb85 1305
AnnaBridge 126:abea610beb85 1306 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
AnnaBridge 126:abea610beb85 1307
AnnaBridge 126:abea610beb85 1308 /** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
AnnaBridge 126:abea610beb85 1309 * @{
AnnaBridge 126:abea610beb85 1310 */
AnnaBridge 126:abea610beb85 1311 #define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK2
AnnaBridge 126:abea610beb85 1312 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
AnnaBridge 126:abea610beb85 1313 #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
AnnaBridge 126:abea610beb85 1314 #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
AnnaBridge 126:abea610beb85 1315
AnnaBridge 126:abea610beb85 1316 /**
AnnaBridge 126:abea610beb85 1317 * @}
AnnaBridge 126:abea610beb85 1318 */
AnnaBridge 126:abea610beb85 1319
AnnaBridge 126:abea610beb85 1320 /** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
AnnaBridge 126:abea610beb85 1321 * @{
AnnaBridge 126:abea610beb85 1322 */
AnnaBridge 126:abea610beb85 1323 #define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
AnnaBridge 126:abea610beb85 1324 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
AnnaBridge 126:abea610beb85 1325
AnnaBridge 126:abea610beb85 1326 /**
AnnaBridge 126:abea610beb85 1327 * @}
AnnaBridge 126:abea610beb85 1328 */
AnnaBridge 126:abea610beb85 1329
AnnaBridge 126:abea610beb85 1330 /** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source
AnnaBridge 126:abea610beb85 1331 * @{
AnnaBridge 126:abea610beb85 1332 */
AnnaBridge 126:abea610beb85 1333
AnnaBridge 126:abea610beb85 1334 /* ADC1 & ADC2 */
AnnaBridge 126:abea610beb85 1335 #define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO
AnnaBridge 126:abea610beb85 1336 #define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1
AnnaBridge 126:abea610beb85 1337 #define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2
AnnaBridge 126:abea610beb85 1338 #define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4
AnnaBridge 126:abea610beb85 1339 #define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6
AnnaBridge 126:abea610beb85 1340 #define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8
AnnaBridge 126:abea610beb85 1341 #define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10
AnnaBridge 126:abea610beb85 1342 #define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12
AnnaBridge 126:abea610beb85 1343 #define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16
AnnaBridge 126:abea610beb85 1344 #define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32
AnnaBridge 126:abea610beb85 1345 #define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64
AnnaBridge 126:abea610beb85 1346 #define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128
AnnaBridge 126:abea610beb85 1347 #define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256
AnnaBridge 126:abea610beb85 1348
AnnaBridge 126:abea610beb85 1349 /**
AnnaBridge 126:abea610beb85 1350 * @}
AnnaBridge 126:abea610beb85 1351 */
AnnaBridge 126:abea610beb85 1352
AnnaBridge 126:abea610beb85 1353 /** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source
AnnaBridge 126:abea610beb85 1354 * @{
AnnaBridge 126:abea610beb85 1355 */
AnnaBridge 126:abea610beb85 1356 #define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK
AnnaBridge 126:abea610beb85 1357 #define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT
AnnaBridge 126:abea610beb85 1358
AnnaBridge 126:abea610beb85 1359 /**
AnnaBridge 126:abea610beb85 1360 * @}
AnnaBridge 126:abea610beb85 1361 */
AnnaBridge 126:abea610beb85 1362 /** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
AnnaBridge 126:abea610beb85 1363 * @{
AnnaBridge 126:abea610beb85 1364 */
AnnaBridge 126:abea610beb85 1365 #define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
AnnaBridge 126:abea610beb85 1366 #define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
AnnaBridge 126:abea610beb85 1367
AnnaBridge 126:abea610beb85 1368 /**
AnnaBridge 126:abea610beb85 1369 * @}
AnnaBridge 126:abea610beb85 1370 */
AnnaBridge 126:abea610beb85 1371
AnnaBridge 126:abea610beb85 1372 /** @defgroup RCCEx_UART4_Clock_Source RCC Extended UART4 Clock Source
AnnaBridge 126:abea610beb85 1373 * @{
AnnaBridge 126:abea610beb85 1374 */
AnnaBridge 126:abea610beb85 1375 #define RCC_UART4CLKSOURCE_PCLK1 RCC_CFGR3_UART4SW_PCLK
AnnaBridge 126:abea610beb85 1376 #define RCC_UART4CLKSOURCE_SYSCLK RCC_CFGR3_UART4SW_SYSCLK
AnnaBridge 126:abea610beb85 1377 #define RCC_UART4CLKSOURCE_LSE RCC_CFGR3_UART4SW_LSE
AnnaBridge 126:abea610beb85 1378 #define RCC_UART4CLKSOURCE_HSI RCC_CFGR3_UART4SW_HSI
AnnaBridge 126:abea610beb85 1379
AnnaBridge 126:abea610beb85 1380 /**
AnnaBridge 126:abea610beb85 1381 * @}
AnnaBridge 126:abea610beb85 1382 */
AnnaBridge 126:abea610beb85 1383
AnnaBridge 126:abea610beb85 1384 /** @defgroup RCCEx_UART5_Clock_Source RCC Extended UART5 Clock Source
AnnaBridge 126:abea610beb85 1385 * @{
AnnaBridge 126:abea610beb85 1386 */
AnnaBridge 126:abea610beb85 1387 #define RCC_UART5CLKSOURCE_PCLK1 RCC_CFGR3_UART5SW_PCLK
AnnaBridge 126:abea610beb85 1388 #define RCC_UART5CLKSOURCE_SYSCLK RCC_CFGR3_UART5SW_SYSCLK
AnnaBridge 126:abea610beb85 1389 #define RCC_UART5CLKSOURCE_LSE RCC_CFGR3_UART5SW_LSE
AnnaBridge 126:abea610beb85 1390 #define RCC_UART5CLKSOURCE_HSI RCC_CFGR3_UART5SW_HSI
AnnaBridge 126:abea610beb85 1391
AnnaBridge 126:abea610beb85 1392 /**
AnnaBridge 126:abea610beb85 1393 * @}
AnnaBridge 126:abea610beb85 1394 */
AnnaBridge 126:abea610beb85 1395
AnnaBridge 126:abea610beb85 1396 #endif /* STM32F302xC || STM32F303xC || STM32F358xx */
AnnaBridge 126:abea610beb85 1397
AnnaBridge 126:abea610beb85 1398 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
AnnaBridge 126:abea610beb85 1399
AnnaBridge 126:abea610beb85 1400 /** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
AnnaBridge 126:abea610beb85 1401 * @{
AnnaBridge 126:abea610beb85 1402 */
AnnaBridge 126:abea610beb85 1403 #define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK2
AnnaBridge 126:abea610beb85 1404 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
AnnaBridge 126:abea610beb85 1405 #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
AnnaBridge 126:abea610beb85 1406 #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
AnnaBridge 126:abea610beb85 1407
AnnaBridge 126:abea610beb85 1408 /**
AnnaBridge 126:abea610beb85 1409 * @}
AnnaBridge 126:abea610beb85 1410 */
AnnaBridge 126:abea610beb85 1411
AnnaBridge 126:abea610beb85 1412 /** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
AnnaBridge 126:abea610beb85 1413 * @{
AnnaBridge 126:abea610beb85 1414 */
AnnaBridge 126:abea610beb85 1415 #define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
AnnaBridge 126:abea610beb85 1416 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
AnnaBridge 126:abea610beb85 1417
AnnaBridge 126:abea610beb85 1418 /**
AnnaBridge 126:abea610beb85 1419 * @}
AnnaBridge 126:abea610beb85 1420 */
AnnaBridge 126:abea610beb85 1421
AnnaBridge 126:abea610beb85 1422 /** @defgroup RCCEx_I2C3_Clock_Source RCC Extended I2C3 Clock Source
AnnaBridge 126:abea610beb85 1423 * @{
AnnaBridge 126:abea610beb85 1424 */
AnnaBridge 126:abea610beb85 1425 #define RCC_I2C3CLKSOURCE_HSI RCC_CFGR3_I2C3SW_HSI
AnnaBridge 126:abea610beb85 1426 #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CFGR3_I2C3SW_SYSCLK
AnnaBridge 126:abea610beb85 1427
AnnaBridge 126:abea610beb85 1428 /**
AnnaBridge 126:abea610beb85 1429 * @}
AnnaBridge 126:abea610beb85 1430 */
AnnaBridge 126:abea610beb85 1431
AnnaBridge 126:abea610beb85 1432 /** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source
AnnaBridge 126:abea610beb85 1433 * @{
AnnaBridge 126:abea610beb85 1434 */
AnnaBridge 126:abea610beb85 1435
AnnaBridge 126:abea610beb85 1436 /* ADC1 & ADC2 */
AnnaBridge 126:abea610beb85 1437 #define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO
AnnaBridge 126:abea610beb85 1438 #define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1
AnnaBridge 126:abea610beb85 1439 #define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2
AnnaBridge 126:abea610beb85 1440 #define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4
AnnaBridge 126:abea610beb85 1441 #define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6
AnnaBridge 126:abea610beb85 1442 #define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8
AnnaBridge 126:abea610beb85 1443 #define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10
AnnaBridge 126:abea610beb85 1444 #define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12
AnnaBridge 126:abea610beb85 1445 #define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16
AnnaBridge 126:abea610beb85 1446 #define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32
AnnaBridge 126:abea610beb85 1447 #define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64
AnnaBridge 126:abea610beb85 1448 #define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128
AnnaBridge 126:abea610beb85 1449 #define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256
AnnaBridge 126:abea610beb85 1450
AnnaBridge 126:abea610beb85 1451 /**
AnnaBridge 126:abea610beb85 1452 * @}
AnnaBridge 126:abea610beb85 1453 */
AnnaBridge 126:abea610beb85 1454
AnnaBridge 126:abea610beb85 1455 /** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source
AnnaBridge 126:abea610beb85 1456 * @{
AnnaBridge 126:abea610beb85 1457 */
AnnaBridge 126:abea610beb85 1458 #define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK
AnnaBridge 126:abea610beb85 1459 #define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT
AnnaBridge 126:abea610beb85 1460
AnnaBridge 126:abea610beb85 1461 /**
AnnaBridge 126:abea610beb85 1462 * @}
AnnaBridge 126:abea610beb85 1463 */
AnnaBridge 126:abea610beb85 1464
AnnaBridge 126:abea610beb85 1465 /** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
AnnaBridge 126:abea610beb85 1466 * @{
AnnaBridge 126:abea610beb85 1467 */
AnnaBridge 126:abea610beb85 1468 #define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
AnnaBridge 126:abea610beb85 1469 #define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
AnnaBridge 126:abea610beb85 1470
AnnaBridge 126:abea610beb85 1471 /**
AnnaBridge 126:abea610beb85 1472 * @}
AnnaBridge 126:abea610beb85 1473 */
AnnaBridge 126:abea610beb85 1474
AnnaBridge 126:abea610beb85 1475 /** @defgroup RCCEx_TIM2_Clock_Source RCC Extended TIM2 Clock Source
AnnaBridge 126:abea610beb85 1476 * @{
AnnaBridge 126:abea610beb85 1477 */
AnnaBridge 126:abea610beb85 1478 #define RCC_TIM2CLK_HCLK RCC_CFGR3_TIM2SW_HCLK
AnnaBridge 126:abea610beb85 1479 #define RCC_TIM2CLK_PLLCLK RCC_CFGR3_TIM2SW_PLL
AnnaBridge 126:abea610beb85 1480
AnnaBridge 126:abea610beb85 1481 /**
AnnaBridge 126:abea610beb85 1482 * @}
AnnaBridge 126:abea610beb85 1483 */
AnnaBridge 126:abea610beb85 1484
AnnaBridge 126:abea610beb85 1485 /** @defgroup RCCEx_TIM34_Clock_Source RCC Extended TIM3 & TIM4 Clock Source
AnnaBridge 126:abea610beb85 1486 * @{
AnnaBridge 126:abea610beb85 1487 */
AnnaBridge 126:abea610beb85 1488 #define RCC_TIM34CLK_HCLK RCC_CFGR3_TIM34SW_HCLK
AnnaBridge 126:abea610beb85 1489 #define RCC_TIM34CLK_PLLCLK RCC_CFGR3_TIM34SW_PLL
AnnaBridge 126:abea610beb85 1490
AnnaBridge 126:abea610beb85 1491 /**
AnnaBridge 126:abea610beb85 1492 * @}
AnnaBridge 126:abea610beb85 1493 */
AnnaBridge 126:abea610beb85 1494
AnnaBridge 126:abea610beb85 1495 /** @defgroup RCCEx_TIM15_Clock_Source RCC Extended TIM15 Clock Source
AnnaBridge 126:abea610beb85 1496 * @{
AnnaBridge 126:abea610beb85 1497 */
AnnaBridge 126:abea610beb85 1498 #define RCC_TIM15CLK_HCLK RCC_CFGR3_TIM15SW_HCLK
AnnaBridge 126:abea610beb85 1499 #define RCC_TIM15CLK_PLLCLK RCC_CFGR3_TIM15SW_PLL
AnnaBridge 126:abea610beb85 1500
AnnaBridge 126:abea610beb85 1501 /**
AnnaBridge 126:abea610beb85 1502 * @}
AnnaBridge 126:abea610beb85 1503 */
AnnaBridge 126:abea610beb85 1504
AnnaBridge 126:abea610beb85 1505 /** @defgroup RCCEx_TIM16_Clock_Source RCC Extended TIM16 Clock Source
AnnaBridge 126:abea610beb85 1506 * @{
AnnaBridge 126:abea610beb85 1507 */
AnnaBridge 126:abea610beb85 1508 #define RCC_TIM16CLK_HCLK RCC_CFGR3_TIM16SW_HCLK
AnnaBridge 126:abea610beb85 1509 #define RCC_TIM16CLK_PLLCLK RCC_CFGR3_TIM16SW_PLL
AnnaBridge 126:abea610beb85 1510
AnnaBridge 126:abea610beb85 1511 /**
AnnaBridge 126:abea610beb85 1512 * @}
AnnaBridge 126:abea610beb85 1513 */
AnnaBridge 126:abea610beb85 1514
AnnaBridge 126:abea610beb85 1515 /** @defgroup RCCEx_TIM17_Clock_Source RCC Extended TIM17 Clock Source
AnnaBridge 126:abea610beb85 1516 * @{
AnnaBridge 126:abea610beb85 1517 */
AnnaBridge 126:abea610beb85 1518 #define RCC_TIM17CLK_HCLK RCC_CFGR3_TIM17SW_HCLK
AnnaBridge 126:abea610beb85 1519 #define RCC_TIM17CLK_PLLCLK RCC_CFGR3_TIM17SW_PLL
AnnaBridge 126:abea610beb85 1520
AnnaBridge 126:abea610beb85 1521 /**
AnnaBridge 126:abea610beb85 1522 * @}
AnnaBridge 126:abea610beb85 1523 */
AnnaBridge 126:abea610beb85 1524
AnnaBridge 126:abea610beb85 1525 /** @defgroup RCCEx_UART4_Clock_Source RCC Extended UART4 Clock Source
AnnaBridge 126:abea610beb85 1526 * @{
AnnaBridge 126:abea610beb85 1527 */
AnnaBridge 126:abea610beb85 1528 #define RCC_UART4CLKSOURCE_PCLK1 RCC_CFGR3_UART4SW_PCLK
AnnaBridge 126:abea610beb85 1529 #define RCC_UART4CLKSOURCE_SYSCLK RCC_CFGR3_UART4SW_SYSCLK
AnnaBridge 126:abea610beb85 1530 #define RCC_UART4CLKSOURCE_LSE RCC_CFGR3_UART4SW_LSE
AnnaBridge 126:abea610beb85 1531 #define RCC_UART4CLKSOURCE_HSI RCC_CFGR3_UART4SW_HSI
AnnaBridge 126:abea610beb85 1532
AnnaBridge 126:abea610beb85 1533 /**
AnnaBridge 126:abea610beb85 1534 * @}
AnnaBridge 126:abea610beb85 1535 */
AnnaBridge 126:abea610beb85 1536
AnnaBridge 126:abea610beb85 1537 /** @defgroup RCCEx_UART5_Clock_Source RCC Extended UART5 Clock Source
AnnaBridge 126:abea610beb85 1538 * @{
AnnaBridge 126:abea610beb85 1539 */
AnnaBridge 126:abea610beb85 1540 #define RCC_UART5CLKSOURCE_PCLK1 RCC_CFGR3_UART5SW_PCLK
AnnaBridge 126:abea610beb85 1541 #define RCC_UART5CLKSOURCE_SYSCLK RCC_CFGR3_UART5SW_SYSCLK
AnnaBridge 126:abea610beb85 1542 #define RCC_UART5CLKSOURCE_LSE RCC_CFGR3_UART5SW_LSE
AnnaBridge 126:abea610beb85 1543 #define RCC_UART5CLKSOURCE_HSI RCC_CFGR3_UART5SW_HSI
AnnaBridge 126:abea610beb85 1544
AnnaBridge 126:abea610beb85 1545 /**
AnnaBridge 126:abea610beb85 1546 * @}
AnnaBridge 126:abea610beb85 1547 */
AnnaBridge 126:abea610beb85 1548
AnnaBridge 126:abea610beb85 1549 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
AnnaBridge 126:abea610beb85 1550
AnnaBridge 126:abea610beb85 1551 #if defined(STM32F303xE) || defined(STM32F398xx)
AnnaBridge 126:abea610beb85 1552 /** @defgroup RCCEx_TIM20_Clock_Source RCC Extended TIM20 Clock Source
AnnaBridge 126:abea610beb85 1553 * @{
AnnaBridge 126:abea610beb85 1554 */
AnnaBridge 126:abea610beb85 1555 #define RCC_TIM20CLK_HCLK RCC_CFGR3_TIM20SW_HCLK
AnnaBridge 126:abea610beb85 1556 #define RCC_TIM20CLK_PLLCLK RCC_CFGR3_TIM20SW_PLL
AnnaBridge 126:abea610beb85 1557
AnnaBridge 126:abea610beb85 1558 /**
AnnaBridge 126:abea610beb85 1559 * @}
AnnaBridge 126:abea610beb85 1560 */
AnnaBridge 126:abea610beb85 1561 #endif /* STM32F303xE || STM32F398xx */
AnnaBridge 126:abea610beb85 1562
AnnaBridge 126:abea610beb85 1563 #if defined(STM32F303xE) || defined(STM32F398xx)\
AnnaBridge 126:abea610beb85 1564 || defined(STM32F303xC) || defined(STM32F358xx)
AnnaBridge 126:abea610beb85 1565
AnnaBridge 126:abea610beb85 1566 /** @defgroup RCCEx_ADC34_Clock_Source RCC Extended ADC34 Clock Source
AnnaBridge 126:abea610beb85 1567 * @{
AnnaBridge 126:abea610beb85 1568 */
AnnaBridge 126:abea610beb85 1569
AnnaBridge 126:abea610beb85 1570 /* ADC3 & ADC4 */
AnnaBridge 126:abea610beb85 1571 #define RCC_ADC34PLLCLK_OFF RCC_CFGR2_ADCPRE34_NO
AnnaBridge 126:abea610beb85 1572 #define RCC_ADC34PLLCLK_DIV1 RCC_CFGR2_ADCPRE34_DIV1
AnnaBridge 126:abea610beb85 1573 #define RCC_ADC34PLLCLK_DIV2 RCC_CFGR2_ADCPRE34_DIV2
AnnaBridge 126:abea610beb85 1574 #define RCC_ADC34PLLCLK_DIV4 RCC_CFGR2_ADCPRE34_DIV4
AnnaBridge 126:abea610beb85 1575 #define RCC_ADC34PLLCLK_DIV6 RCC_CFGR2_ADCPRE34_DIV6
AnnaBridge 126:abea610beb85 1576 #define RCC_ADC34PLLCLK_DIV8 RCC_CFGR2_ADCPRE34_DIV8
AnnaBridge 126:abea610beb85 1577 #define RCC_ADC34PLLCLK_DIV10 RCC_CFGR2_ADCPRE34_DIV10
AnnaBridge 126:abea610beb85 1578 #define RCC_ADC34PLLCLK_DIV12 RCC_CFGR2_ADCPRE34_DIV12
AnnaBridge 126:abea610beb85 1579 #define RCC_ADC34PLLCLK_DIV16 RCC_CFGR2_ADCPRE34_DIV16
AnnaBridge 126:abea610beb85 1580 #define RCC_ADC34PLLCLK_DIV32 RCC_CFGR2_ADCPRE34_DIV32
AnnaBridge 126:abea610beb85 1581 #define RCC_ADC34PLLCLK_DIV64 RCC_CFGR2_ADCPRE34_DIV64
AnnaBridge 126:abea610beb85 1582 #define RCC_ADC34PLLCLK_DIV128 RCC_CFGR2_ADCPRE34_DIV128
AnnaBridge 126:abea610beb85 1583 #define RCC_ADC34PLLCLK_DIV256 RCC_CFGR2_ADCPRE34_DIV256
AnnaBridge 126:abea610beb85 1584
AnnaBridge 126:abea610beb85 1585 /**
AnnaBridge 126:abea610beb85 1586 * @}
AnnaBridge 126:abea610beb85 1587 */
AnnaBridge 126:abea610beb85 1588
AnnaBridge 126:abea610beb85 1589 /** @defgroup RCCEx_TIM8_Clock_Source RCC Extended TIM8 Clock Source
AnnaBridge 126:abea610beb85 1590 * @{
AnnaBridge 126:abea610beb85 1591 */
AnnaBridge 126:abea610beb85 1592 #define RCC_TIM8CLK_HCLK RCC_CFGR3_TIM8SW_HCLK
AnnaBridge 126:abea610beb85 1593 #define RCC_TIM8CLK_PLLCLK RCC_CFGR3_TIM8SW_PLL
AnnaBridge 126:abea610beb85 1594
AnnaBridge 126:abea610beb85 1595 /**
AnnaBridge 126:abea610beb85 1596 * @}
AnnaBridge 126:abea610beb85 1597 */
AnnaBridge 126:abea610beb85 1598
AnnaBridge 126:abea610beb85 1599 #endif /* STM32F303xC || STM32F303xE || STM32F398xx || STM32F358xx */
AnnaBridge 126:abea610beb85 1600
AnnaBridge 126:abea610beb85 1601 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
AnnaBridge 126:abea610beb85 1602
AnnaBridge 126:abea610beb85 1603 /** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
AnnaBridge 126:abea610beb85 1604 * @{
AnnaBridge 126:abea610beb85 1605 */
AnnaBridge 126:abea610beb85 1606 #define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK1
AnnaBridge 126:abea610beb85 1607 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
AnnaBridge 126:abea610beb85 1608 #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
AnnaBridge 126:abea610beb85 1609 #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
AnnaBridge 126:abea610beb85 1610
AnnaBridge 126:abea610beb85 1611 /**
AnnaBridge 126:abea610beb85 1612 * @}
AnnaBridge 126:abea610beb85 1613 */
AnnaBridge 126:abea610beb85 1614
AnnaBridge 126:abea610beb85 1615 /** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source
AnnaBridge 126:abea610beb85 1616 * @{
AnnaBridge 126:abea610beb85 1617 */
AnnaBridge 126:abea610beb85 1618 /* ADC1 & ADC2 */
AnnaBridge 126:abea610beb85 1619 #define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO
AnnaBridge 126:abea610beb85 1620 #define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1
AnnaBridge 126:abea610beb85 1621 #define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2
AnnaBridge 126:abea610beb85 1622 #define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4
AnnaBridge 126:abea610beb85 1623 #define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6
AnnaBridge 126:abea610beb85 1624 #define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8
AnnaBridge 126:abea610beb85 1625 #define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10
AnnaBridge 126:abea610beb85 1626 #define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12
AnnaBridge 126:abea610beb85 1627 #define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16
AnnaBridge 126:abea610beb85 1628 #define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32
AnnaBridge 126:abea610beb85 1629 #define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64
AnnaBridge 126:abea610beb85 1630 #define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128
AnnaBridge 126:abea610beb85 1631 #define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256
AnnaBridge 126:abea610beb85 1632
AnnaBridge 126:abea610beb85 1633 /**
AnnaBridge 126:abea610beb85 1634 * @}
AnnaBridge 126:abea610beb85 1635 */
AnnaBridge 126:abea610beb85 1636
AnnaBridge 126:abea610beb85 1637 /** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
AnnaBridge 126:abea610beb85 1638 * @{
AnnaBridge 126:abea610beb85 1639 */
AnnaBridge 126:abea610beb85 1640 #define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
AnnaBridge 126:abea610beb85 1641 #define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
AnnaBridge 126:abea610beb85 1642
AnnaBridge 126:abea610beb85 1643 /**
AnnaBridge 126:abea610beb85 1644 * @}
AnnaBridge 126:abea610beb85 1645 */
AnnaBridge 126:abea610beb85 1646
AnnaBridge 126:abea610beb85 1647 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
AnnaBridge 126:abea610beb85 1648
AnnaBridge 126:abea610beb85 1649 #if defined(STM32F334x8)
AnnaBridge 126:abea610beb85 1650
AnnaBridge 126:abea610beb85 1651 /** @defgroup RCCEx_HRTIM1_Clock_Source RCC Extended HRTIM1 Clock Source
AnnaBridge 126:abea610beb85 1652 * @{
AnnaBridge 126:abea610beb85 1653 */
AnnaBridge 126:abea610beb85 1654 #define RCC_HRTIM1CLK_HCLK RCC_CFGR3_HRTIM1SW_HCLK
AnnaBridge 126:abea610beb85 1655 #define RCC_HRTIM1CLK_PLLCLK RCC_CFGR3_HRTIM1SW_PLL
AnnaBridge 126:abea610beb85 1656
AnnaBridge 126:abea610beb85 1657 /**
AnnaBridge 126:abea610beb85 1658 * @}
AnnaBridge 126:abea610beb85 1659 */
AnnaBridge 126:abea610beb85 1660
AnnaBridge 126:abea610beb85 1661 #endif /* STM32F334x8 */
AnnaBridge 126:abea610beb85 1662
AnnaBridge 126:abea610beb85 1663 #if defined(STM32F373xC) || defined(STM32F378xx)
AnnaBridge 126:abea610beb85 1664
AnnaBridge 126:abea610beb85 1665 /** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
AnnaBridge 126:abea610beb85 1666 * @{
AnnaBridge 126:abea610beb85 1667 */
AnnaBridge 126:abea610beb85 1668 #define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK2
AnnaBridge 126:abea610beb85 1669 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
AnnaBridge 126:abea610beb85 1670 #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
AnnaBridge 126:abea610beb85 1671 #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
AnnaBridge 126:abea610beb85 1672
AnnaBridge 126:abea610beb85 1673 /**
AnnaBridge 126:abea610beb85 1674 * @}
AnnaBridge 126:abea610beb85 1675 */
AnnaBridge 126:abea610beb85 1676
AnnaBridge 126:abea610beb85 1677 /** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
AnnaBridge 126:abea610beb85 1678 * @{
AnnaBridge 126:abea610beb85 1679 */
AnnaBridge 126:abea610beb85 1680 #define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
AnnaBridge 126:abea610beb85 1681 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
AnnaBridge 126:abea610beb85 1682
AnnaBridge 126:abea610beb85 1683 /**
AnnaBridge 126:abea610beb85 1684 * @}
AnnaBridge 126:abea610beb85 1685 */
AnnaBridge 126:abea610beb85 1686
AnnaBridge 126:abea610beb85 1687 /** @defgroup RCCEx_ADC1_Clock_Source RCC Extended ADC1 Clock Source
AnnaBridge 126:abea610beb85 1688 * @{
AnnaBridge 126:abea610beb85 1689 */
AnnaBridge 126:abea610beb85 1690
AnnaBridge 126:abea610beb85 1691 /* ADC1 */
AnnaBridge 126:abea610beb85 1692 #define RCC_ADC1PCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2
AnnaBridge 126:abea610beb85 1693 #define RCC_ADC1PCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4
AnnaBridge 126:abea610beb85 1694 #define RCC_ADC1PCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6
AnnaBridge 126:abea610beb85 1695 #define RCC_ADC1PCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8
AnnaBridge 126:abea610beb85 1696
AnnaBridge 126:abea610beb85 1697 /**
AnnaBridge 126:abea610beb85 1698 * @}
AnnaBridge 126:abea610beb85 1699 */
AnnaBridge 126:abea610beb85 1700
AnnaBridge 126:abea610beb85 1701 /** @defgroup RCCEx_CEC_Clock_Source RCC Extended CEC Clock Source
AnnaBridge 126:abea610beb85 1702 * @{
AnnaBridge 126:abea610beb85 1703 */
AnnaBridge 126:abea610beb85 1704 #define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244
AnnaBridge 126:abea610beb85 1705 #define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE
AnnaBridge 126:abea610beb85 1706
AnnaBridge 126:abea610beb85 1707 /**
AnnaBridge 126:abea610beb85 1708 * @}
AnnaBridge 126:abea610beb85 1709 */
AnnaBridge 126:abea610beb85 1710
AnnaBridge 126:abea610beb85 1711 /** @defgroup RCCEx_SDADC_Clock_Prescaler RCC Extended SDADC Clock Prescaler
AnnaBridge 126:abea610beb85 1712 * @{
AnnaBridge 126:abea610beb85 1713 */
<> 135:176b8275d35d 1714 #define RCC_SDADCSYSCLK_DIV1 RCC_CFGR_SDPRE_DIV1
<> 135:176b8275d35d 1715 #define RCC_SDADCSYSCLK_DIV2 RCC_CFGR_SDPRE_DIV2
<> 135:176b8275d35d 1716 #define RCC_SDADCSYSCLK_DIV4 RCC_CFGR_SDPRE_DIV4
<> 135:176b8275d35d 1717 #define RCC_SDADCSYSCLK_DIV6 RCC_CFGR_SDPRE_DIV6
<> 135:176b8275d35d 1718 #define RCC_SDADCSYSCLK_DIV8 RCC_CFGR_SDPRE_DIV8
<> 135:176b8275d35d 1719 #define RCC_SDADCSYSCLK_DIV10 RCC_CFGR_SDPRE_DIV10
<> 135:176b8275d35d 1720 #define RCC_SDADCSYSCLK_DIV12 RCC_CFGR_SDPRE_DIV12
<> 135:176b8275d35d 1721 #define RCC_SDADCSYSCLK_DIV14 RCC_CFGR_SDPRE_DIV14
<> 135:176b8275d35d 1722 #define RCC_SDADCSYSCLK_DIV16 RCC_CFGR_SDPRE_DIV16
<> 135:176b8275d35d 1723 #define RCC_SDADCSYSCLK_DIV20 RCC_CFGR_SDPRE_DIV20
<> 135:176b8275d35d 1724 #define RCC_SDADCSYSCLK_DIV24 RCC_CFGR_SDPRE_DIV24
<> 135:176b8275d35d 1725 #define RCC_SDADCSYSCLK_DIV28 RCC_CFGR_SDPRE_DIV28
<> 135:176b8275d35d 1726 #define RCC_SDADCSYSCLK_DIV32 RCC_CFGR_SDPRE_DIV32
<> 135:176b8275d35d 1727 #define RCC_SDADCSYSCLK_DIV36 RCC_CFGR_SDPRE_DIV36
<> 135:176b8275d35d 1728 #define RCC_SDADCSYSCLK_DIV40 RCC_CFGR_SDPRE_DIV40
<> 135:176b8275d35d 1729 #define RCC_SDADCSYSCLK_DIV44 RCC_CFGR_SDPRE_DIV44
<> 135:176b8275d35d 1730 #define RCC_SDADCSYSCLK_DIV48 RCC_CFGR_SDPRE_DIV48
AnnaBridge 126:abea610beb85 1731
AnnaBridge 126:abea610beb85 1732 /**
AnnaBridge 126:abea610beb85 1733 * @}
AnnaBridge 126:abea610beb85 1734 */
AnnaBridge 126:abea610beb85 1735
AnnaBridge 126:abea610beb85 1736 #endif /* STM32F373xC || STM32F378xx */
AnnaBridge 126:abea610beb85 1737
AnnaBridge 126:abea610beb85 1738 #if defined(STM32F302xE) || defined(STM32F303xE)\
AnnaBridge 126:abea610beb85 1739 || defined(STM32F302xC) || defined(STM32F303xC)\
AnnaBridge 126:abea610beb85 1740 || defined(STM32F302x8) \
AnnaBridge 126:abea610beb85 1741 || defined(STM32F373xC)
AnnaBridge 126:abea610beb85 1742 /** @defgroup RCCEx_USB_Clock_Source RCC Extended USB Clock Source
AnnaBridge 126:abea610beb85 1743 * @{
AnnaBridge 126:abea610beb85 1744 */
AnnaBridge 126:abea610beb85 1745
AnnaBridge 126:abea610beb85 1746 #define RCC_USBCLKSOURCE_PLL RCC_CFGR_USBPRE_DIV1
AnnaBridge 126:abea610beb85 1747 #define RCC_USBCLKSOURCE_PLL_DIV1_5 RCC_CFGR_USBPRE_DIV1_5
AnnaBridge 126:abea610beb85 1748
AnnaBridge 126:abea610beb85 1749 /**
AnnaBridge 126:abea610beb85 1750 * @}
AnnaBridge 126:abea610beb85 1751 */
AnnaBridge 126:abea610beb85 1752
AnnaBridge 126:abea610beb85 1753 #endif /* STM32F302xE || STM32F303xE || */
AnnaBridge 126:abea610beb85 1754 /* STM32F302xC || STM32F303xC || */
AnnaBridge 126:abea610beb85 1755 /* STM32F302x8 || */
AnnaBridge 126:abea610beb85 1756 /* STM32F373xC */
AnnaBridge 126:abea610beb85 1757
AnnaBridge 126:abea610beb85 1758
AnnaBridge 126:abea610beb85 1759 /** @defgroup RCCEx_MCOx_Clock_Prescaler RCC Extended MCOx Clock Prescaler
AnnaBridge 126:abea610beb85 1760 * @{
AnnaBridge 126:abea610beb85 1761 */
AnnaBridge 126:abea610beb85 1762 #if defined(RCC_CFGR_MCOPRE)
AnnaBridge 126:abea610beb85 1763
<> 135:176b8275d35d 1764 #define RCC_MCODIV_1 (0x00000000U)
<> 135:176b8275d35d 1765 #define RCC_MCODIV_2 (0x10000000U)
<> 135:176b8275d35d 1766 #define RCC_MCODIV_4 (0x20000000U)
<> 135:176b8275d35d 1767 #define RCC_MCODIV_8 (0x30000000U)
<> 135:176b8275d35d 1768 #define RCC_MCODIV_16 (0x40000000U)
<> 135:176b8275d35d 1769 #define RCC_MCODIV_32 (0x50000000U)
<> 135:176b8275d35d 1770 #define RCC_MCODIV_64 (0x60000000U)
<> 135:176b8275d35d 1771 #define RCC_MCODIV_128 (0x70000000U)
AnnaBridge 126:abea610beb85 1772
AnnaBridge 126:abea610beb85 1773 #else
AnnaBridge 126:abea610beb85 1774
<> 135:176b8275d35d 1775 #define RCC_MCODIV_1 (0x00000000U)
AnnaBridge 126:abea610beb85 1776
AnnaBridge 126:abea610beb85 1777 #endif /* RCC_CFGR_MCOPRE */
AnnaBridge 126:abea610beb85 1778
AnnaBridge 126:abea610beb85 1779 /**
AnnaBridge 126:abea610beb85 1780 * @}
AnnaBridge 126:abea610beb85 1781 */
AnnaBridge 126:abea610beb85 1782
AnnaBridge 126:abea610beb85 1783 /** @defgroup RCCEx_LSEDrive_Configuration RCC LSE Drive Configuration
AnnaBridge 126:abea610beb85 1784 * @{
AnnaBridge 126:abea610beb85 1785 */
AnnaBridge 126:abea610beb85 1786
<> 135:176b8275d35d 1787 #define RCC_LSEDRIVE_LOW (0x00000000U) /*!< Xtal mode lower driving capability */
AnnaBridge 126:abea610beb85 1788 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low driving capability */
AnnaBridge 126:abea610beb85 1789 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high driving capability */
AnnaBridge 126:abea610beb85 1790 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */
AnnaBridge 126:abea610beb85 1791
AnnaBridge 126:abea610beb85 1792 /**
AnnaBridge 126:abea610beb85 1793 * @}
AnnaBridge 126:abea610beb85 1794 */
AnnaBridge 126:abea610beb85 1795
AnnaBridge 126:abea610beb85 1796 /**
AnnaBridge 126:abea610beb85 1797 * @}
AnnaBridge 126:abea610beb85 1798 */
AnnaBridge 126:abea610beb85 1799
AnnaBridge 126:abea610beb85 1800 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 126:abea610beb85 1801 /** @defgroup RCCEx_Exported_Macros RCC Extended Exported Macros
AnnaBridge 126:abea610beb85 1802 * @{
AnnaBridge 126:abea610beb85 1803 */
AnnaBridge 126:abea610beb85 1804
AnnaBridge 126:abea610beb85 1805 /** @defgroup RCCEx_PLL_Configuration RCC Extended PLL Configuration
AnnaBridge 126:abea610beb85 1806 * @{
AnnaBridge 126:abea610beb85 1807 */
AnnaBridge 126:abea610beb85 1808 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
AnnaBridge 126:abea610beb85 1809 /** @brief Macro to configure the PLL clock source, multiplication and division factors.
AnnaBridge 126:abea610beb85 1810 * @note This macro must be used only when the PLL is disabled.
AnnaBridge 126:abea610beb85 1811 *
AnnaBridge 126:abea610beb85 1812 * @param __RCC_PLLSource__ specifies the PLL entry clock source.
AnnaBridge 126:abea610beb85 1813 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 1814 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
AnnaBridge 126:abea610beb85 1815 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
AnnaBridge 126:abea610beb85 1816 * @param __PREDIV__ specifies the predivider factor for PLL VCO input clock
AnnaBridge 126:abea610beb85 1817 * This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16.
AnnaBridge 126:abea610beb85 1818 * @param __PLLMUL__ specifies the multiplication factor for PLL VCO input clock
AnnaBridge 126:abea610beb85 1819 * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
AnnaBridge 126:abea610beb85 1820 *
AnnaBridge 126:abea610beb85 1821 */
AnnaBridge 126:abea610beb85 1822 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PREDIV__, __PLLMUL__) \
AnnaBridge 126:abea610beb85 1823 do { \
AnnaBridge 126:abea610beb85 1824 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \
AnnaBridge 126:abea610beb85 1825 MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSource__))); \
<> 135:176b8275d35d 1826 } while(0U)
AnnaBridge 126:abea610beb85 1827 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
AnnaBridge 126:abea610beb85 1828
AnnaBridge 126:abea610beb85 1829 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
AnnaBridge 126:abea610beb85 1830 || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
AnnaBridge 126:abea610beb85 1831 || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\
AnnaBridge 126:abea610beb85 1832 || defined(STM32F373xC) || defined(STM32F378xx)
AnnaBridge 126:abea610beb85 1833 /** @brief Macro to configure the PLL clock source and multiplication factor.
AnnaBridge 126:abea610beb85 1834 * @note This macro must be used only when the PLL is disabled.
AnnaBridge 126:abea610beb85 1835 *
AnnaBridge 126:abea610beb85 1836 * @param __RCC_PLLSource__ specifies the PLL entry clock source.
AnnaBridge 126:abea610beb85 1837 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 1838 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
AnnaBridge 126:abea610beb85 1839 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
AnnaBridge 126:abea610beb85 1840 * @param __PLLMUL__ specifies the multiplication factor for PLL VCO input clock
AnnaBridge 126:abea610beb85 1841 * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
AnnaBridge 126:abea610beb85 1842 *
AnnaBridge 126:abea610beb85 1843 */
AnnaBridge 126:abea610beb85 1844 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PLLMUL__) \
AnnaBridge 126:abea610beb85 1845 MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSource__)))
AnnaBridge 126:abea610beb85 1846 #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
AnnaBridge 126:abea610beb85 1847 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
AnnaBridge 126:abea610beb85 1848 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
AnnaBridge 126:abea610beb85 1849 /* STM32F373xC || STM32F378xx */
AnnaBridge 126:abea610beb85 1850 /**
AnnaBridge 126:abea610beb85 1851 * @}
AnnaBridge 126:abea610beb85 1852 */
AnnaBridge 126:abea610beb85 1853
AnnaBridge 126:abea610beb85 1854 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
AnnaBridge 126:abea610beb85 1855 || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
AnnaBridge 126:abea610beb85 1856 || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\
AnnaBridge 126:abea610beb85 1857 || defined(STM32F373xC) || defined(STM32F378xx)
AnnaBridge 126:abea610beb85 1858 /** @defgroup RCCEx_HSE_Configuration RCC Extended HSE Configuration
AnnaBridge 126:abea610beb85 1859 * @{
AnnaBridge 126:abea610beb85 1860 */
AnnaBridge 126:abea610beb85 1861
AnnaBridge 126:abea610beb85 1862 /**
AnnaBridge 126:abea610beb85 1863 * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
AnnaBridge 126:abea610beb85 1864 * @note Predivision factor can not be changed if PLL is used as system clock
AnnaBridge 126:abea610beb85 1865 * In this case, you have to select another source of the system clock, disable the PLL and
AnnaBridge 126:abea610beb85 1866 * then change the HSE predivision factor.
AnnaBridge 126:abea610beb85 1867 * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE.
AnnaBridge 126:abea610beb85 1868 * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
AnnaBridge 126:abea610beb85 1869 */
AnnaBridge 126:abea610beb85 1870 #define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \
AnnaBridge 126:abea610beb85 1871 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSE_PREDIV_VALUE__))
AnnaBridge 126:abea610beb85 1872
AnnaBridge 126:abea610beb85 1873 /**
AnnaBridge 126:abea610beb85 1874 * @brief Macro to get prediv1 factor for PLL.
AnnaBridge 126:abea610beb85 1875 */
AnnaBridge 126:abea610beb85 1876 #define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV)
AnnaBridge 126:abea610beb85 1877
AnnaBridge 126:abea610beb85 1878 /**
AnnaBridge 126:abea610beb85 1879 * @}
AnnaBridge 126:abea610beb85 1880 */
AnnaBridge 126:abea610beb85 1881 #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
AnnaBridge 126:abea610beb85 1882 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
AnnaBridge 126:abea610beb85 1883 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
AnnaBridge 126:abea610beb85 1884 /* STM32F373xC || STM32F378xx */
AnnaBridge 126:abea610beb85 1885
AnnaBridge 126:abea610beb85 1886 /** @defgroup RCCEx_AHB_Clock_Enable_Disable RCC Extended AHB Clock Enable Disable
AnnaBridge 126:abea610beb85 1887 * @brief Enable or disable the AHB peripheral clock.
AnnaBridge 126:abea610beb85 1888 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 126:abea610beb85 1889 * is disabled and the application software has to enable this clock before
AnnaBridge 126:abea610beb85 1890 * using it.
AnnaBridge 126:abea610beb85 1891 * @{
AnnaBridge 126:abea610beb85 1892 */
AnnaBridge 126:abea610beb85 1893 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
AnnaBridge 126:abea610beb85 1894 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 1895 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 1896 SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC1EN);\
AnnaBridge 126:abea610beb85 1897 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 1898 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC1EN);\
AnnaBridge 126:abea610beb85 1899 UNUSED(tmpreg); \
<> 135:176b8275d35d 1900 } while(0U)
AnnaBridge 126:abea610beb85 1901
AnnaBridge 126:abea610beb85 1902 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC1EN))
AnnaBridge 126:abea610beb85 1903 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
AnnaBridge 126:abea610beb85 1904
AnnaBridge 126:abea610beb85 1905 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
AnnaBridge 126:abea610beb85 1906 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
AnnaBridge 126:abea610beb85 1907 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 1908 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 1909 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
AnnaBridge 126:abea610beb85 1910 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 1911 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
AnnaBridge 126:abea610beb85 1912 UNUSED(tmpreg); \
<> 135:176b8275d35d 1913 } while(0U)
AnnaBridge 126:abea610beb85 1914 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 1915 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 1916 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
AnnaBridge 126:abea610beb85 1917 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 1918 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
AnnaBridge 126:abea610beb85 1919 UNUSED(tmpreg); \
<> 135:176b8275d35d 1920 } while(0U)
AnnaBridge 126:abea610beb85 1921 #define __HAL_RCC_ADC12_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 1922 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 1923 SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\
AnnaBridge 126:abea610beb85 1924 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 1925 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\
AnnaBridge 126:abea610beb85 1926 UNUSED(tmpreg); \
<> 135:176b8275d35d 1927 } while(0U)
AnnaBridge 126:abea610beb85 1928 /* Aliases for STM32 F3 compatibility */
AnnaBridge 126:abea610beb85 1929 #define __HAL_RCC_ADC1_CLK_ENABLE() __HAL_RCC_ADC12_CLK_ENABLE()
AnnaBridge 126:abea610beb85 1930 #define __HAL_RCC_ADC2_CLK_ENABLE() __HAL_RCC_ADC12_CLK_ENABLE()
AnnaBridge 126:abea610beb85 1931
AnnaBridge 126:abea610beb85 1932 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
AnnaBridge 126:abea610beb85 1933 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
AnnaBridge 126:abea610beb85 1934 #define __HAL_RCC_ADC12_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC12EN))
AnnaBridge 126:abea610beb85 1935 /* Aliases for STM32 F3 compatibility */
AnnaBridge 126:abea610beb85 1936 #define __HAL_RCC_ADC1_CLK_DISABLE() __HAL_RCC_ADC12_CLK_DISABLE()
AnnaBridge 126:abea610beb85 1937 #define __HAL_RCC_ADC2_CLK_DISABLE() __HAL_RCC_ADC12_CLK_DISABLE()
AnnaBridge 126:abea610beb85 1938 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
AnnaBridge 126:abea610beb85 1939 /* STM32F302xC || STM32F303xC || STM32F358xx */
AnnaBridge 126:abea610beb85 1940
AnnaBridge 126:abea610beb85 1941 #if defined(STM32F303xE) || defined(STM32F398xx)\
AnnaBridge 126:abea610beb85 1942 || defined(STM32F303xC) || defined(STM32F358xx)
AnnaBridge 126:abea610beb85 1943 #define __HAL_RCC_ADC34_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 1944 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 1945 SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC34EN);\
AnnaBridge 126:abea610beb85 1946 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 1947 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC34EN);\
AnnaBridge 126:abea610beb85 1948 UNUSED(tmpreg); \
<> 135:176b8275d35d 1949 } while(0U)
AnnaBridge 126:abea610beb85 1950 #define __HAL_RCC_ADC34_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC34EN))
AnnaBridge 126:abea610beb85 1951 #endif /* STM32F303xE || STM32F398xx || */
AnnaBridge 126:abea610beb85 1952 /* STM32F303xC || STM32F358xx */
AnnaBridge 126:abea610beb85 1953
AnnaBridge 126:abea610beb85 1954 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
AnnaBridge 126:abea610beb85 1955 #define __HAL_RCC_ADC12_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 1956 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 1957 SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\
AnnaBridge 126:abea610beb85 1958 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 1959 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\
AnnaBridge 126:abea610beb85 1960 UNUSED(tmpreg); \
<> 135:176b8275d35d 1961 } while(0U)
AnnaBridge 126:abea610beb85 1962 /* Aliases for STM32 F3 compatibility */
AnnaBridge 126:abea610beb85 1963 #define __HAL_RCC_ADC1_CLK_ENABLE() __HAL_RCC_ADC12_CLK_ENABLE()
AnnaBridge 126:abea610beb85 1964 #define __HAL_RCC_ADC2_CLK_ENABLE() __HAL_RCC_ADC12_CLK_ENABLE()
AnnaBridge 126:abea610beb85 1965
AnnaBridge 126:abea610beb85 1966 #define __HAL_RCC_ADC12_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC12EN))
AnnaBridge 126:abea610beb85 1967 /* Aliases for STM32 F3 compatibility */
AnnaBridge 126:abea610beb85 1968 #define __HAL_RCC_ADC1_CLK_DISABLE() __HAL_RCC_ADC12_CLK_DISABLE()
AnnaBridge 126:abea610beb85 1969 #define __HAL_RCC_ADC2_CLK_DISABLE() __HAL_RCC_ADC12_CLK_DISABLE()
AnnaBridge 126:abea610beb85 1970 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
AnnaBridge 126:abea610beb85 1971
AnnaBridge 126:abea610beb85 1972 #if defined(STM32F373xC) || defined(STM32F378xx)
AnnaBridge 126:abea610beb85 1973 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 1974 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 1975 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
AnnaBridge 126:abea610beb85 1976 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 1977 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
AnnaBridge 126:abea610beb85 1978 UNUSED(tmpreg); \
<> 135:176b8275d35d 1979 } while(0U)
AnnaBridge 126:abea610beb85 1980 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 1981 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 1982 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
AnnaBridge 126:abea610beb85 1983 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 1984 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
AnnaBridge 126:abea610beb85 1985 UNUSED(tmpreg); \
<> 135:176b8275d35d 1986 } while(0U)
AnnaBridge 126:abea610beb85 1987
AnnaBridge 126:abea610beb85 1988 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
AnnaBridge 126:abea610beb85 1989 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
AnnaBridge 126:abea610beb85 1990 #endif /* STM32F373xC || STM32F378xx */
AnnaBridge 126:abea610beb85 1991
AnnaBridge 126:abea610beb85 1992 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
AnnaBridge 126:abea610beb85 1993 #define __HAL_RCC_FMC_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 1994 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 1995 SET_BIT(RCC->AHBENR, RCC_AHBENR_FMCEN);\
AnnaBridge 126:abea610beb85 1996 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 1997 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FMCEN);\
AnnaBridge 126:abea610beb85 1998 UNUSED(tmpreg); \
<> 135:176b8275d35d 1999 } while(0U)
AnnaBridge 126:abea610beb85 2000 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 2001 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 2002 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\
AnnaBridge 126:abea610beb85 2003 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 2004 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\
AnnaBridge 126:abea610beb85 2005 UNUSED(tmpreg); \
<> 135:176b8275d35d 2006 } while(0U)
AnnaBridge 126:abea610beb85 2007 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 2008 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 2009 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\
AnnaBridge 126:abea610beb85 2010 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 2011 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\
AnnaBridge 126:abea610beb85 2012 UNUSED(tmpreg); \
<> 135:176b8275d35d 2013 } while(0U)
AnnaBridge 126:abea610beb85 2014
AnnaBridge 126:abea610beb85 2015 #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FMCEN))
AnnaBridge 126:abea610beb85 2016 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOGEN))
AnnaBridge 126:abea610beb85 2017 #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOHEN))
AnnaBridge 126:abea610beb85 2018 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
AnnaBridge 126:abea610beb85 2019 /**
AnnaBridge 126:abea610beb85 2020 * @}
AnnaBridge 126:abea610beb85 2021 */
AnnaBridge 126:abea610beb85 2022
AnnaBridge 126:abea610beb85 2023 /** @defgroup RCCEx_APB1_Clock_Enable_Disable RCC Extended APB1 Clock Enable Disable
AnnaBridge 126:abea610beb85 2024 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
AnnaBridge 126:abea610beb85 2025 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 126:abea610beb85 2026 * is disabled and the application software has to enable this clock before
AnnaBridge 126:abea610beb85 2027 * using it.
AnnaBridge 126:abea610beb85 2028 * @{
AnnaBridge 126:abea610beb85 2029 */
AnnaBridge 126:abea610beb85 2030 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
AnnaBridge 126:abea610beb85 2031 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 2032 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 2033 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
AnnaBridge 126:abea610beb85 2034 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 2035 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
AnnaBridge 126:abea610beb85 2036 UNUSED(tmpreg); \
<> 135:176b8275d35d 2037 } while(0U)
AnnaBridge 126:abea610beb85 2038 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 2039 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 2040 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
AnnaBridge 126:abea610beb85 2041 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 2042 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
AnnaBridge 126:abea610beb85 2043 UNUSED(tmpreg); \
<> 135:176b8275d35d 2044 } while(0U)
AnnaBridge 126:abea610beb85 2045 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 2046 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 2047 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
AnnaBridge 126:abea610beb85 2048 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 2049 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
AnnaBridge 126:abea610beb85 2050 UNUSED(tmpreg); \
<> 135:176b8275d35d 2051 } while(0U)
AnnaBridge 126:abea610beb85 2052 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 2053 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 2054 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
AnnaBridge 126:abea610beb85 2055 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 2056 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
AnnaBridge 126:abea610beb85 2057 UNUSED(tmpreg); \
<> 135:176b8275d35d 2058 } while(0U)
AnnaBridge 126:abea610beb85 2059
AnnaBridge 126:abea610beb85 2060 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
AnnaBridge 126:abea610beb85 2061 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
AnnaBridge 126:abea610beb85 2062 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
AnnaBridge 126:abea610beb85 2063 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
AnnaBridge 126:abea610beb85 2064 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
AnnaBridge 126:abea610beb85 2065
AnnaBridge 126:abea610beb85 2066 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
AnnaBridge 126:abea610beb85 2067 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
AnnaBridge 126:abea610beb85 2068 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 2069 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 2070 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
AnnaBridge 126:abea610beb85 2071 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 2072 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
AnnaBridge 126:abea610beb85 2073 UNUSED(tmpreg); \
<> 135:176b8275d35d 2074 } while(0U)
AnnaBridge 126:abea610beb85 2075 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 2076 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 2077 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
AnnaBridge 126:abea610beb85 2078 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 2079 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
AnnaBridge 126:abea610beb85 2080 UNUSED(tmpreg); \
<> 135:176b8275d35d 2081 } while(0U)
AnnaBridge 126:abea610beb85 2082 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 2083 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 2084 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
AnnaBridge 126:abea610beb85 2085 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 2086 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
AnnaBridge 126:abea610beb85 2087 UNUSED(tmpreg); \
<> 135:176b8275d35d 2088 } while(0U)
AnnaBridge 126:abea610beb85 2089 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 2090 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 2091 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
AnnaBridge 126:abea610beb85 2092 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 2093 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
AnnaBridge 126:abea610beb85 2094 UNUSED(tmpreg); \
<> 135:176b8275d35d 2095 } while(0U)
AnnaBridge 126:abea610beb85 2096 #define __HAL_RCC_UART4_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 2097 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 2098 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
AnnaBridge 126:abea610beb85 2099 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 2100 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
AnnaBridge 126:abea610beb85 2101 UNUSED(tmpreg); \
<> 135:176b8275d35d 2102 } while(0U)
AnnaBridge 126:abea610beb85 2103 #define __HAL_RCC_UART5_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 2104 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 2105 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
AnnaBridge 126:abea610beb85 2106 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 2107 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
AnnaBridge 126:abea610beb85 2108 UNUSED(tmpreg); \
<> 135:176b8275d35d 2109 } while(0U)
AnnaBridge 126:abea610beb85 2110 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 2111 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 2112 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
AnnaBridge 126:abea610beb85 2113 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 2114 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
AnnaBridge 126:abea610beb85 2115 UNUSED(tmpreg); \
<> 135:176b8275d35d 2116 } while(0U)
AnnaBridge 126:abea610beb85 2117
AnnaBridge 126:abea610beb85 2118 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
AnnaBridge 126:abea610beb85 2119 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
AnnaBridge 126:abea610beb85 2120 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
AnnaBridge 126:abea610beb85 2121 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
AnnaBridge 126:abea610beb85 2122 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
AnnaBridge 126:abea610beb85 2123 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
AnnaBridge 126:abea610beb85 2124 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
AnnaBridge 126:abea610beb85 2125 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
AnnaBridge 126:abea610beb85 2126 /* STM32F302xC || STM32F303xC || STM32F358xx */
AnnaBridge 126:abea610beb85 2127
AnnaBridge 126:abea610beb85 2128 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
AnnaBridge 126:abea610beb85 2129 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 2130 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 2131 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
AnnaBridge 126:abea610beb85 2132 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 2133 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
AnnaBridge 126:abea610beb85 2134 UNUSED(tmpreg); \
<> 135:176b8275d35d 2135 } while(0U)
AnnaBridge 126:abea610beb85 2136 #define __HAL_RCC_DAC2_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 2137 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 2138 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\
AnnaBridge 126:abea610beb85 2139 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 2140 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\
AnnaBridge 126:abea610beb85 2141 UNUSED(tmpreg); \
<> 135:176b8275d35d 2142 } while(0U)
AnnaBridge 126:abea610beb85 2143
AnnaBridge 126:abea610beb85 2144 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
AnnaBridge 126:abea610beb85 2145 #define __HAL_RCC_DAC2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC2EN))
AnnaBridge 126:abea610beb85 2146 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
AnnaBridge 126:abea610beb85 2147
AnnaBridge 126:abea610beb85 2148 #if defined(STM32F373xC) || defined(STM32F378xx)
AnnaBridge 126:abea610beb85 2149 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 2150 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 2151 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
AnnaBridge 126:abea610beb85 2152 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 2153 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
AnnaBridge 126:abea610beb85 2154 UNUSED(tmpreg); \
<> 135:176b8275d35d 2155 } while(0U)
AnnaBridge 126:abea610beb85 2156 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 2157 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 2158 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
AnnaBridge 126:abea610beb85 2159 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 2160 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
AnnaBridge 126:abea610beb85 2161 UNUSED(tmpreg); \
<> 135:176b8275d35d 2162 } while(0U)
AnnaBridge 126:abea610beb85 2163 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 2164 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 2165 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
AnnaBridge 126:abea610beb85 2166 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 2167 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
AnnaBridge 126:abea610beb85 2168 UNUSED(tmpreg); \
<> 135:176b8275d35d 2169 } while(0U)
AnnaBridge 126:abea610beb85 2170 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 2171 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 2172 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
AnnaBridge 126:abea610beb85 2173 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 2174 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
AnnaBridge 126:abea610beb85 2175 UNUSED(tmpreg); \
<> 135:176b8275d35d 2176 } while(0U)
AnnaBridge 126:abea610beb85 2177 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 2178 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 2179 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
AnnaBridge 126:abea610beb85 2180 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 2181 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
AnnaBridge 126:abea610beb85 2182 UNUSED(tmpreg); \
<> 135:176b8275d35d 2183 } while(0U)
AnnaBridge 126:abea610beb85 2184 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 2185 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 2186 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
AnnaBridge 126:abea610beb85 2187 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 2188 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
AnnaBridge 126:abea610beb85 2189 UNUSED(tmpreg); \
<> 135:176b8275d35d 2190 } while(0U)
AnnaBridge 126:abea610beb85 2191 #define __HAL_RCC_TIM18_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 2192 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 2193 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM18EN);\
AnnaBridge 126:abea610beb85 2194 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 2195 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM18EN);\
AnnaBridge 126:abea610beb85 2196 UNUSED(tmpreg); \
<> 135:176b8275d35d 2197 } while(0U)
AnnaBridge 126:abea610beb85 2198 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 2199 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 2200 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
AnnaBridge 126:abea610beb85 2201 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 2202 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
AnnaBridge 126:abea610beb85 2203 UNUSED(tmpreg); \
<> 135:176b8275d35d 2204 } while(0U)
AnnaBridge 126:abea610beb85 2205 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 2206 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 2207 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
AnnaBridge 126:abea610beb85 2208 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 2209 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
AnnaBridge 126:abea610beb85 2210 UNUSED(tmpreg); \
<> 135:176b8275d35d 2211 } while(0U)
AnnaBridge 126:abea610beb85 2212 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 2213 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 2214 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
AnnaBridge 126:abea610beb85 2215 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 2216 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
AnnaBridge 126:abea610beb85 2217 UNUSED(tmpreg); \
<> 135:176b8275d35d 2218 } while(0U)
AnnaBridge 126:abea610beb85 2219 #define __HAL_RCC_DAC2_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 2220 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 2221 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\
AnnaBridge 126:abea610beb85 2222 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 2223 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\
AnnaBridge 126:abea610beb85 2224 UNUSED(tmpreg); \
<> 135:176b8275d35d 2225 } while(0U)
AnnaBridge 126:abea610beb85 2226 #define __HAL_RCC_CEC_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 2227 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 2228 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
AnnaBridge 126:abea610beb85 2229 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 2230 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
AnnaBridge 126:abea610beb85 2231 UNUSED(tmpreg); \
<> 135:176b8275d35d 2232 } while(0U)
AnnaBridge 126:abea610beb85 2233
AnnaBridge 126:abea610beb85 2234 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
AnnaBridge 126:abea610beb85 2235 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
AnnaBridge 126:abea610beb85 2236 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
AnnaBridge 126:abea610beb85 2237 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
AnnaBridge 126:abea610beb85 2238 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
AnnaBridge 126:abea610beb85 2239 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
AnnaBridge 126:abea610beb85 2240 #define __HAL_RCC_TIM18_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM18EN))
AnnaBridge 126:abea610beb85 2241 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
AnnaBridge 126:abea610beb85 2242 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
AnnaBridge 126:abea610beb85 2243 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
AnnaBridge 126:abea610beb85 2244 #define __HAL_RCC_DAC2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC2EN))
AnnaBridge 126:abea610beb85 2245 #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
AnnaBridge 126:abea610beb85 2246 #endif /* STM32F373xC || STM32F378xx */
AnnaBridge 126:abea610beb85 2247
AnnaBridge 126:abea610beb85 2248 #if defined(STM32F303xE) || defined(STM32F398xx) \
AnnaBridge 126:abea610beb85 2249 || defined(STM32F303xC) || defined(STM32F358xx) \
AnnaBridge 126:abea610beb85 2250 || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
AnnaBridge 126:abea610beb85 2251 || defined(STM32F373xC) || defined(STM32F378xx)
AnnaBridge 126:abea610beb85 2252 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 2253 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 2254 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
AnnaBridge 126:abea610beb85 2255 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 2256 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
AnnaBridge 126:abea610beb85 2257 UNUSED(tmpreg); \
<> 135:176b8275d35d 2258 } while(0U)
AnnaBridge 126:abea610beb85 2259
AnnaBridge 126:abea610beb85 2260 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
AnnaBridge 126:abea610beb85 2261 #endif /* STM32F303xE || STM32F398xx || */
AnnaBridge 126:abea610beb85 2262 /* STM32F303xC || STM32F358xx || */
AnnaBridge 126:abea610beb85 2263 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
AnnaBridge 126:abea610beb85 2264 /* STM32F373xC || STM32F378xx */
AnnaBridge 126:abea610beb85 2265
AnnaBridge 126:abea610beb85 2266 #if defined(STM32F302xE) || defined(STM32F303xE)\
AnnaBridge 126:abea610beb85 2267 || defined(STM32F302xC) || defined(STM32F303xC)\
AnnaBridge 126:abea610beb85 2268 || defined(STM32F302x8) \
AnnaBridge 126:abea610beb85 2269 || defined(STM32F373xC)
AnnaBridge 126:abea610beb85 2270 #define __HAL_RCC_USB_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 2271 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 2272 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
AnnaBridge 126:abea610beb85 2273 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 2274 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
AnnaBridge 126:abea610beb85 2275 UNUSED(tmpreg); \
<> 135:176b8275d35d 2276 } while(0U)
AnnaBridge 126:abea610beb85 2277
AnnaBridge 126:abea610beb85 2278 #define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
AnnaBridge 126:abea610beb85 2279 #endif /* STM32F302xE || STM32F303xE || */
AnnaBridge 126:abea610beb85 2280 /* STM32F302xC || STM32F303xC || */
AnnaBridge 126:abea610beb85 2281 /* STM32F302x8 || */
AnnaBridge 126:abea610beb85 2282 /* STM32F373xC */
AnnaBridge 126:abea610beb85 2283
AnnaBridge 126:abea610beb85 2284 #if !defined(STM32F301x8)
AnnaBridge 126:abea610beb85 2285 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 2286 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 2287 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\
AnnaBridge 126:abea610beb85 2288 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 2289 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\
AnnaBridge 126:abea610beb85 2290 UNUSED(tmpreg); \
<> 135:176b8275d35d 2291 } while(0U)
AnnaBridge 126:abea610beb85 2292
AnnaBridge 126:abea610beb85 2293 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN))
AnnaBridge 126:abea610beb85 2294 #endif /* STM32F301x8*/
AnnaBridge 126:abea610beb85 2295
AnnaBridge 126:abea610beb85 2296 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
AnnaBridge 126:abea610beb85 2297 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 2298 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 2299 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
AnnaBridge 126:abea610beb85 2300 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 2301 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
AnnaBridge 126:abea610beb85 2302 UNUSED(tmpreg); \
<> 135:176b8275d35d 2303 } while(0U)
AnnaBridge 126:abea610beb85 2304
AnnaBridge 126:abea610beb85 2305 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
AnnaBridge 126:abea610beb85 2306 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
AnnaBridge 126:abea610beb85 2307 /**
AnnaBridge 126:abea610beb85 2308 * @}
AnnaBridge 126:abea610beb85 2309 */
AnnaBridge 126:abea610beb85 2310
AnnaBridge 126:abea610beb85 2311 /** @defgroup RCCEx_APB2_Clock_Enable_Disable RCC Extended APB2 Clock Enable Disable
AnnaBridge 126:abea610beb85 2312 * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
AnnaBridge 126:abea610beb85 2313 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 126:abea610beb85 2314 * is disabled and the application software has to enable this clock before
AnnaBridge 126:abea610beb85 2315 * using it.
AnnaBridge 126:abea610beb85 2316 * @{
AnnaBridge 126:abea610beb85 2317 */
AnnaBridge 126:abea610beb85 2318 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
AnnaBridge 126:abea610beb85 2319 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
AnnaBridge 126:abea610beb85 2320 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 2321 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 2322 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
AnnaBridge 126:abea610beb85 2323 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 2324 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
AnnaBridge 126:abea610beb85 2325 UNUSED(tmpreg); \
<> 135:176b8275d35d 2326 } while(0U)
AnnaBridge 126:abea610beb85 2327
AnnaBridge 126:abea610beb85 2328 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
AnnaBridge 126:abea610beb85 2329 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
AnnaBridge 126:abea610beb85 2330 /* STM32F302xC || STM32F303xC || STM32F358xx */
AnnaBridge 126:abea610beb85 2331
AnnaBridge 126:abea610beb85 2332 #if defined(STM32F303xE) || defined(STM32F398xx)\
AnnaBridge 126:abea610beb85 2333 || defined(STM32F303xC) || defined(STM32F358xx)
AnnaBridge 126:abea610beb85 2334 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 2335 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 2336 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
AnnaBridge 126:abea610beb85 2337 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 2338 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
AnnaBridge 126:abea610beb85 2339 UNUSED(tmpreg); \
<> 135:176b8275d35d 2340 } while(0U)
AnnaBridge 126:abea610beb85 2341
AnnaBridge 126:abea610beb85 2342 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
AnnaBridge 126:abea610beb85 2343 #endif /* STM32F303xE || STM32F398xx || */
AnnaBridge 126:abea610beb85 2344 /* STM32F303xC || STM32F358xx */
AnnaBridge 126:abea610beb85 2345
AnnaBridge 126:abea610beb85 2346 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
AnnaBridge 126:abea610beb85 2347 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 2348 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 2349 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
AnnaBridge 126:abea610beb85 2350 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 2351 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
AnnaBridge 126:abea610beb85 2352 UNUSED(tmpreg); \
<> 135:176b8275d35d 2353 } while(0U)
AnnaBridge 126:abea610beb85 2354
AnnaBridge 126:abea610beb85 2355 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
AnnaBridge 126:abea610beb85 2356 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
AnnaBridge 126:abea610beb85 2357
AnnaBridge 126:abea610beb85 2358 #if defined(STM32F334x8)
AnnaBridge 126:abea610beb85 2359 #define __HAL_RCC_HRTIM1_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 2360 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 2361 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN);\
AnnaBridge 126:abea610beb85 2362 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 2363 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN);\
AnnaBridge 126:abea610beb85 2364 UNUSED(tmpreg); \
<> 135:176b8275d35d 2365 } while(0U)
AnnaBridge 126:abea610beb85 2366
AnnaBridge 126:abea610beb85 2367 #define __HAL_RCC_HRTIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_HRTIM1EN))
AnnaBridge 126:abea610beb85 2368 #endif /* STM32F334x8 */
AnnaBridge 126:abea610beb85 2369
AnnaBridge 126:abea610beb85 2370 #if defined(STM32F373xC) || defined(STM32F378xx)
AnnaBridge 126:abea610beb85 2371 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 2372 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 2373 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
AnnaBridge 126:abea610beb85 2374 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 2375 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
AnnaBridge 126:abea610beb85 2376 UNUSED(tmpreg); \
<> 135:176b8275d35d 2377 } while(0U)
AnnaBridge 126:abea610beb85 2378 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 2379 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 2380 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
AnnaBridge 126:abea610beb85 2381 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 2382 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
AnnaBridge 126:abea610beb85 2383 UNUSED(tmpreg); \
<> 135:176b8275d35d 2384 } while(0U)
AnnaBridge 126:abea610beb85 2385 #define __HAL_RCC_TIM19_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 2386 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 2387 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM19EN);\
AnnaBridge 126:abea610beb85 2388 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 2389 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM19EN);\
AnnaBridge 126:abea610beb85 2390 UNUSED(tmpreg); \
<> 135:176b8275d35d 2391 } while(0U)
AnnaBridge 126:abea610beb85 2392 #define __HAL_RCC_SDADC1_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 2393 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 2394 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC1EN);\
AnnaBridge 126:abea610beb85 2395 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 2396 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC1EN);\
AnnaBridge 126:abea610beb85 2397 UNUSED(tmpreg); \
<> 135:176b8275d35d 2398 } while(0U)
AnnaBridge 126:abea610beb85 2399 #define __HAL_RCC_SDADC2_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 2400 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 2401 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC2EN);\
AnnaBridge 126:abea610beb85 2402 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 2403 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC2EN);\
AnnaBridge 126:abea610beb85 2404 UNUSED(tmpreg); \
<> 135:176b8275d35d 2405 } while(0U)
AnnaBridge 126:abea610beb85 2406 #define __HAL_RCC_SDADC3_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 2407 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 2408 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC3EN);\
AnnaBridge 126:abea610beb85 2409 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 2410 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC3EN);\
AnnaBridge 126:abea610beb85 2411 UNUSED(tmpreg); \
<> 135:176b8275d35d 2412 } while(0U)
AnnaBridge 126:abea610beb85 2413
AnnaBridge 126:abea610beb85 2414 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
AnnaBridge 126:abea610beb85 2415 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
AnnaBridge 126:abea610beb85 2416 #define __HAL_RCC_TIM19_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM19EN))
AnnaBridge 126:abea610beb85 2417 #define __HAL_RCC_SDADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC1EN))
AnnaBridge 126:abea610beb85 2418 #define __HAL_RCC_SDADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC2EN))
AnnaBridge 126:abea610beb85 2419 #define __HAL_RCC_SDADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC3EN))
AnnaBridge 126:abea610beb85 2420 #endif /* STM32F373xC || STM32F378xx */
AnnaBridge 126:abea610beb85 2421
AnnaBridge 126:abea610beb85 2422 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
AnnaBridge 126:abea610beb85 2423 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
AnnaBridge 126:abea610beb85 2424 || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
AnnaBridge 126:abea610beb85 2425 || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
AnnaBridge 126:abea610beb85 2426 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 2427 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 2428 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
AnnaBridge 126:abea610beb85 2429 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 2430 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
AnnaBridge 126:abea610beb85 2431 UNUSED(tmpreg); \
<> 135:176b8275d35d 2432 } while(0U)
AnnaBridge 126:abea610beb85 2433
AnnaBridge 126:abea610beb85 2434 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
AnnaBridge 126:abea610beb85 2435 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
AnnaBridge 126:abea610beb85 2436 /* STM32F302xC || STM32F303xC || STM32F358xx || */
AnnaBridge 126:abea610beb85 2437 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
AnnaBridge 126:abea610beb85 2438 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
AnnaBridge 126:abea610beb85 2439
AnnaBridge 126:abea610beb85 2440 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
AnnaBridge 126:abea610beb85 2441 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 2442 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 2443 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
AnnaBridge 126:abea610beb85 2444 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 2445 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
AnnaBridge 126:abea610beb85 2446 UNUSED(tmpreg); \
<> 135:176b8275d35d 2447 } while(0U)
AnnaBridge 126:abea610beb85 2448
AnnaBridge 126:abea610beb85 2449 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
AnnaBridge 126:abea610beb85 2450 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
AnnaBridge 126:abea610beb85 2451
AnnaBridge 126:abea610beb85 2452 #if defined(STM32F303xE) || defined(STM32F398xx)
AnnaBridge 126:abea610beb85 2453 #define __HAL_RCC_TIM20_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 2454 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 2455 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN);\
AnnaBridge 126:abea610beb85 2456 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 2457 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN);\
AnnaBridge 126:abea610beb85 2458 UNUSED(tmpreg); \
<> 135:176b8275d35d 2459 } while(0U)
AnnaBridge 126:abea610beb85 2460 #define __HAL_RCC_TIM20_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM20EN))
AnnaBridge 126:abea610beb85 2461 #endif /* STM32F303xE || STM32F398xx */
AnnaBridge 126:abea610beb85 2462
AnnaBridge 126:abea610beb85 2463 /**
AnnaBridge 126:abea610beb85 2464 * @}
AnnaBridge 126:abea610beb85 2465 */
AnnaBridge 126:abea610beb85 2466
AnnaBridge 126:abea610beb85 2467 /** @defgroup RCCEx_AHB_Peripheral_Clock_Enable_Disable_Status RCC Extended AHB Peripheral Clock Enable Disable Status
AnnaBridge 126:abea610beb85 2468 * @brief Get the enable or disable status of the AHB peripheral clock.
AnnaBridge 126:abea610beb85 2469 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 126:abea610beb85 2470 * is disabled and the application software has to enable this clock before
AnnaBridge 126:abea610beb85 2471 * using it.
AnnaBridge 126:abea610beb85 2472 * @{
AnnaBridge 126:abea610beb85 2473 */
AnnaBridge 126:abea610beb85 2474 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
AnnaBridge 126:abea610beb85 2475 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC1EN)) != RESET)
AnnaBridge 126:abea610beb85 2476
AnnaBridge 126:abea610beb85 2477 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC1EN)) == RESET)
AnnaBridge 126:abea610beb85 2478 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
AnnaBridge 126:abea610beb85 2479
AnnaBridge 126:abea610beb85 2480 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
AnnaBridge 126:abea610beb85 2481 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
AnnaBridge 126:abea610beb85 2482 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
AnnaBridge 126:abea610beb85 2483 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET)
AnnaBridge 126:abea610beb85 2484 #define __HAL_RCC_ADC12_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC12EN)) != RESET)
AnnaBridge 126:abea610beb85 2485
AnnaBridge 126:abea610beb85 2486 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
AnnaBridge 126:abea610beb85 2487 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET)
AnnaBridge 126:abea610beb85 2488 #define __HAL_RCC_ADC12_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC12EN)) == RESET)
AnnaBridge 126:abea610beb85 2489 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
AnnaBridge 126:abea610beb85 2490 /* STM32F302xC || STM32F303xC || STM32F358xx */
AnnaBridge 126:abea610beb85 2491
AnnaBridge 126:abea610beb85 2492 #if defined(STM32F303xE) || defined(STM32F398xx)\
AnnaBridge 126:abea610beb85 2493 || defined(STM32F303xC) || defined(STM32F358xx)
AnnaBridge 126:abea610beb85 2494 #define __HAL_RCC_ADC34_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC34EN)) != RESET)
AnnaBridge 126:abea610beb85 2495
AnnaBridge 126:abea610beb85 2496 #define __HAL_RCC_ADC34_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC34EN)) == RESET)
AnnaBridge 126:abea610beb85 2497 #endif /* STM32F303xE || STM32F398xx || */
AnnaBridge 126:abea610beb85 2498 /* STM32F303xC || STM32F358xx */
AnnaBridge 126:abea610beb85 2499
AnnaBridge 126:abea610beb85 2500 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
AnnaBridge 126:abea610beb85 2501 #define __HAL_RCC_ADC12_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC12EN)) != RESET)
AnnaBridge 126:abea610beb85 2502
AnnaBridge 126:abea610beb85 2503 #define __HAL_RCC_ADC12_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC12EN)) == RESET)
AnnaBridge 126:abea610beb85 2504 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
AnnaBridge 126:abea610beb85 2505
AnnaBridge 126:abea610beb85 2506 #if defined(STM32F373xC) || defined(STM32F378xx)
AnnaBridge 126:abea610beb85 2507 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
AnnaBridge 126:abea610beb85 2508 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET)
AnnaBridge 126:abea610beb85 2509
AnnaBridge 126:abea610beb85 2510 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
AnnaBridge 126:abea610beb85 2511 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET)
AnnaBridge 126:abea610beb85 2512 #endif /* STM32F373xC || STM32F378xx */
AnnaBridge 126:abea610beb85 2513
AnnaBridge 126:abea610beb85 2514 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
AnnaBridge 126:abea610beb85 2515 #define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FMCEN)) != RESET)
AnnaBridge 126:abea610beb85 2516 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) != RESET)
AnnaBridge 126:abea610beb85 2517 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOHEN)) != RESET)
AnnaBridge 126:abea610beb85 2518
AnnaBridge 126:abea610beb85 2519 #define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FMCEN)) == RESET)
AnnaBridge 126:abea610beb85 2520 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) == RESET)
AnnaBridge 126:abea610beb85 2521 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOHEN)) == RESET)
AnnaBridge 126:abea610beb85 2522 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
AnnaBridge 126:abea610beb85 2523 /**
AnnaBridge 126:abea610beb85 2524 * @}
AnnaBridge 126:abea610beb85 2525 */
AnnaBridge 126:abea610beb85 2526
AnnaBridge 126:abea610beb85 2527 /** @defgroup RCCEx_APB1_Clock_Enable_Disable_Status RCC Extended APB1 Peripheral Clock Enable Disable Status
AnnaBridge 126:abea610beb85 2528 * @brief Get the enable or disable status of the APB1 peripheral clock.
AnnaBridge 126:abea610beb85 2529 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 126:abea610beb85 2530 * is disabled and the application software has to enable this clock before
AnnaBridge 126:abea610beb85 2531 * using it.
AnnaBridge 126:abea610beb85 2532 * @{
AnnaBridge 126:abea610beb85 2533 */
AnnaBridge 126:abea610beb85 2534 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
AnnaBridge 126:abea610beb85 2535 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
AnnaBridge 126:abea610beb85 2536 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
AnnaBridge 126:abea610beb85 2537 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
AnnaBridge 126:abea610beb85 2538 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
AnnaBridge 126:abea610beb85 2539
AnnaBridge 126:abea610beb85 2540 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
AnnaBridge 126:abea610beb85 2541 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
AnnaBridge 126:abea610beb85 2542 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
AnnaBridge 126:abea610beb85 2543 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
AnnaBridge 126:abea610beb85 2544 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
AnnaBridge 126:abea610beb85 2545
AnnaBridge 126:abea610beb85 2546 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
AnnaBridge 126:abea610beb85 2547 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
AnnaBridge 126:abea610beb85 2548 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
AnnaBridge 126:abea610beb85 2549 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
AnnaBridge 126:abea610beb85 2550 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
AnnaBridge 126:abea610beb85 2551 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
AnnaBridge 126:abea610beb85 2552 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
AnnaBridge 126:abea610beb85 2553 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
AnnaBridge 126:abea610beb85 2554 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
AnnaBridge 126:abea610beb85 2555
AnnaBridge 126:abea610beb85 2556 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
AnnaBridge 126:abea610beb85 2557 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
AnnaBridge 126:abea610beb85 2558 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
AnnaBridge 126:abea610beb85 2559 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
AnnaBridge 126:abea610beb85 2560 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
AnnaBridge 126:abea610beb85 2561 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
AnnaBridge 126:abea610beb85 2562 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
AnnaBridge 126:abea610beb85 2563 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
AnnaBridge 126:abea610beb85 2564 /* STM32F302xC || STM32F303xC || STM32F358xx */
AnnaBridge 126:abea610beb85 2565
AnnaBridge 126:abea610beb85 2566 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
AnnaBridge 126:abea610beb85 2567 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
AnnaBridge 126:abea610beb85 2568 #define __HAL_RCC_DAC2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN)) != RESET)
AnnaBridge 126:abea610beb85 2569
AnnaBridge 126:abea610beb85 2570 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
AnnaBridge 126:abea610beb85 2571 #define __HAL_RCC_DAC2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN)) == RESET)
AnnaBridge 126:abea610beb85 2572 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
AnnaBridge 126:abea610beb85 2573
AnnaBridge 126:abea610beb85 2574 #if defined(STM32F373xC) || defined(STM32F378xx)
AnnaBridge 126:abea610beb85 2575 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
AnnaBridge 126:abea610beb85 2576 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
AnnaBridge 126:abea610beb85 2577 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
AnnaBridge 126:abea610beb85 2578 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
AnnaBridge 126:abea610beb85 2579 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
AnnaBridge 126:abea610beb85 2580 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
AnnaBridge 126:abea610beb85 2581 #define __HAL_RCC_TIM18_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM18EN)) != RESET)
AnnaBridge 126:abea610beb85 2582 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
AnnaBridge 126:abea610beb85 2583 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
AnnaBridge 126:abea610beb85 2584 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
AnnaBridge 126:abea610beb85 2585 #define __HAL_RCC_DAC2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN)) != RESET)
AnnaBridge 126:abea610beb85 2586 #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
AnnaBridge 126:abea610beb85 2587
AnnaBridge 126:abea610beb85 2588 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
AnnaBridge 126:abea610beb85 2589 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
AnnaBridge 126:abea610beb85 2590 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
AnnaBridge 126:abea610beb85 2591 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
AnnaBridge 126:abea610beb85 2592 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
AnnaBridge 126:abea610beb85 2593 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
AnnaBridge 126:abea610beb85 2594 #define __HAL_RCC_TIM18_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM18EN)) == RESET)
AnnaBridge 126:abea610beb85 2595 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
AnnaBridge 126:abea610beb85 2596 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
AnnaBridge 126:abea610beb85 2597 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
AnnaBridge 126:abea610beb85 2598 #define __HAL_RCC_DAC2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN)) == RESET)
AnnaBridge 126:abea610beb85 2599 #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
AnnaBridge 126:abea610beb85 2600 #endif /* STM32F373xC || STM32F378xx */
AnnaBridge 126:abea610beb85 2601
AnnaBridge 126:abea610beb85 2602 #if defined(STM32F303xE) || defined(STM32F398xx) \
AnnaBridge 126:abea610beb85 2603 || defined(STM32F303xC) || defined(STM32F358xx) \
AnnaBridge 126:abea610beb85 2604 || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
AnnaBridge 126:abea610beb85 2605 || defined(STM32F373xC) || defined(STM32F378xx)
AnnaBridge 126:abea610beb85 2606 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
AnnaBridge 126:abea610beb85 2607
AnnaBridge 126:abea610beb85 2608 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
AnnaBridge 126:abea610beb85 2609 #endif /* STM32F303xE || STM32F398xx || */
AnnaBridge 126:abea610beb85 2610 /* STM32F303xC || STM32F358xx || */
AnnaBridge 126:abea610beb85 2611 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
AnnaBridge 126:abea610beb85 2612 /* STM32F373xC || STM32F378xx */
AnnaBridge 126:abea610beb85 2613
AnnaBridge 126:abea610beb85 2614 #if defined(STM32F302xE) || defined(STM32F303xE)\
AnnaBridge 126:abea610beb85 2615 || defined(STM32F302xC) || defined(STM32F303xC)\
AnnaBridge 126:abea610beb85 2616 || defined(STM32F302x8) \
AnnaBridge 126:abea610beb85 2617 || defined(STM32F373xC)
AnnaBridge 126:abea610beb85 2618 #define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET)
AnnaBridge 126:abea610beb85 2619
AnnaBridge 126:abea610beb85 2620 #define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET)
AnnaBridge 126:abea610beb85 2621 #endif /* STM32F302xE || STM32F303xE || */
AnnaBridge 126:abea610beb85 2622 /* STM32F302xC || STM32F303xC || */
AnnaBridge 126:abea610beb85 2623 /* STM32F302x8 || */
AnnaBridge 126:abea610beb85 2624 /* STM32F373xC */
AnnaBridge 126:abea610beb85 2625
AnnaBridge 126:abea610beb85 2626 #if !defined(STM32F301x8)
AnnaBridge 126:abea610beb85 2627 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CANEN)) != RESET)
AnnaBridge 126:abea610beb85 2628
AnnaBridge 126:abea610beb85 2629 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CANEN)) == RESET)
AnnaBridge 126:abea610beb85 2630 #endif /* STM32F301x8*/
AnnaBridge 126:abea610beb85 2631
AnnaBridge 126:abea610beb85 2632 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
AnnaBridge 126:abea610beb85 2633 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
AnnaBridge 126:abea610beb85 2634
AnnaBridge 126:abea610beb85 2635 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
AnnaBridge 126:abea610beb85 2636 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
AnnaBridge 126:abea610beb85 2637 /**
AnnaBridge 126:abea610beb85 2638 * @}
AnnaBridge 126:abea610beb85 2639 */
AnnaBridge 126:abea610beb85 2640
AnnaBridge 126:abea610beb85 2641 /** @defgroup RCCEx_APB2_Clock_Enable_Disable_Status RCC Extended APB2 Peripheral Clock Enable Disable Status
AnnaBridge 126:abea610beb85 2642 * @brief Get the enable or disable status of the APB2 peripheral clock.
AnnaBridge 126:abea610beb85 2643 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 126:abea610beb85 2644 * is disabled and the application software has to enable this clock before
AnnaBridge 126:abea610beb85 2645 * using it.
AnnaBridge 126:abea610beb85 2646 * @{
AnnaBridge 126:abea610beb85 2647 */
AnnaBridge 126:abea610beb85 2648 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
AnnaBridge 126:abea610beb85 2649 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
AnnaBridge 126:abea610beb85 2650 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
AnnaBridge 126:abea610beb85 2651
AnnaBridge 126:abea610beb85 2652 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
AnnaBridge 126:abea610beb85 2653 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
AnnaBridge 126:abea610beb85 2654 /* STM32F302xC || STM32F303xC || STM32F358xx */
AnnaBridge 126:abea610beb85 2655
AnnaBridge 126:abea610beb85 2656 #if defined(STM32F303xE) || defined(STM32F398xx)\
AnnaBridge 126:abea610beb85 2657 || defined(STM32F303xC) || defined(STM32F358xx)
AnnaBridge 126:abea610beb85 2658 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
AnnaBridge 126:abea610beb85 2659
AnnaBridge 126:abea610beb85 2660 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
AnnaBridge 126:abea610beb85 2661 #endif /* STM32F303xE || STM32F398xx || */
AnnaBridge 126:abea610beb85 2662 /* STM32F303xC || STM32F358xx */
AnnaBridge 126:abea610beb85 2663
AnnaBridge 126:abea610beb85 2664 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
AnnaBridge 126:abea610beb85 2665 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
AnnaBridge 126:abea610beb85 2666
AnnaBridge 126:abea610beb85 2667 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
AnnaBridge 126:abea610beb85 2668 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
AnnaBridge 126:abea610beb85 2669
AnnaBridge 126:abea610beb85 2670 #if defined(STM32F334x8)
AnnaBridge 126:abea610beb85 2671 #define __HAL_RCC_HRTIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_HRTIM1EN)) != RESET)
AnnaBridge 126:abea610beb85 2672
AnnaBridge 126:abea610beb85 2673 #define __HAL_RCC_HRTIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_HRTIM1EN)) == RESET)
AnnaBridge 126:abea610beb85 2674 #endif /* STM32F334x8 */
AnnaBridge 126:abea610beb85 2675
AnnaBridge 126:abea610beb85 2676 #if defined(STM32F373xC) || defined(STM32F378xx)
AnnaBridge 126:abea610beb85 2677 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
AnnaBridge 126:abea610beb85 2678 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
AnnaBridge 126:abea610beb85 2679 #define __HAL_RCC_TIM19_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM19EN)) != RESET)
AnnaBridge 126:abea610beb85 2680 #define __HAL_RCC_SDADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC1EN)) != RESET)
AnnaBridge 126:abea610beb85 2681 #define __HAL_RCC_SDADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC2EN)) != RESET)
AnnaBridge 126:abea610beb85 2682 #define __HAL_RCC_SDADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC3EN)) != RESET)
AnnaBridge 126:abea610beb85 2683
AnnaBridge 126:abea610beb85 2684 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
AnnaBridge 126:abea610beb85 2685 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
AnnaBridge 126:abea610beb85 2686 #define __HAL_RCC_TIM19_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM19EN)) == RESET)
AnnaBridge 126:abea610beb85 2687 #define __HAL_RCC_SDADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC1EN)) == RESET)
AnnaBridge 126:abea610beb85 2688 #define __HAL_RCC_SDADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC2EN)) == RESET)
AnnaBridge 126:abea610beb85 2689 #define __HAL_RCC_SDADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC3EN)) == RESET)
AnnaBridge 126:abea610beb85 2690 #endif /* STM32F373xC || STM32F378xx */
AnnaBridge 126:abea610beb85 2691
AnnaBridge 126:abea610beb85 2692 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
AnnaBridge 126:abea610beb85 2693 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
AnnaBridge 126:abea610beb85 2694 || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
AnnaBridge 126:abea610beb85 2695 || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
AnnaBridge 126:abea610beb85 2696 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
AnnaBridge 126:abea610beb85 2697
AnnaBridge 126:abea610beb85 2698 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
AnnaBridge 126:abea610beb85 2699 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
AnnaBridge 126:abea610beb85 2700 /* STM32F302xC || STM32F303xC || STM32F358xx || */
AnnaBridge 126:abea610beb85 2701 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
AnnaBridge 126:abea610beb85 2702 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
AnnaBridge 126:abea610beb85 2703
AnnaBridge 126:abea610beb85 2704 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
AnnaBridge 126:abea610beb85 2705 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
AnnaBridge 126:abea610beb85 2706
AnnaBridge 126:abea610beb85 2707 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
AnnaBridge 126:abea610beb85 2708 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
AnnaBridge 126:abea610beb85 2709
AnnaBridge 126:abea610beb85 2710 #if defined(STM32F303xE) || defined(STM32F398xx)
AnnaBridge 126:abea610beb85 2711 #define __HAL_RCC_TIM20_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM20EN)) != RESET)
AnnaBridge 126:abea610beb85 2712
AnnaBridge 126:abea610beb85 2713 #define __HAL_RCC_TIM20_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM20EN)) == RESET)
AnnaBridge 126:abea610beb85 2714 #endif /* STM32F303xE || STM32F398xx */
AnnaBridge 126:abea610beb85 2715 /**
AnnaBridge 126:abea610beb85 2716 * @}
AnnaBridge 126:abea610beb85 2717 */
AnnaBridge 126:abea610beb85 2718
AnnaBridge 126:abea610beb85 2719 /** @defgroup RCCEx_AHB_Force_Release_Reset RCC Extended AHB Force Release Reset
AnnaBridge 126:abea610beb85 2720 * @brief Force or release AHB peripheral reset.
AnnaBridge 126:abea610beb85 2721 * @{
AnnaBridge 126:abea610beb85 2722 */
AnnaBridge 126:abea610beb85 2723 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
AnnaBridge 126:abea610beb85 2724 #define __HAL_RCC_ADC1_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC1RST))
AnnaBridge 126:abea610beb85 2725
AnnaBridge 126:abea610beb85 2726 #define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC1RST))
AnnaBridge 126:abea610beb85 2727 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
AnnaBridge 126:abea610beb85 2728
AnnaBridge 126:abea610beb85 2729 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
AnnaBridge 126:abea610beb85 2730 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
AnnaBridge 126:abea610beb85 2731 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST))
AnnaBridge 126:abea610beb85 2732 #define __HAL_RCC_ADC12_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC12RST))
AnnaBridge 126:abea610beb85 2733 /* Aliases for STM32 F3 compatibility */
AnnaBridge 126:abea610beb85 2734 #define __HAL_RCC_ADC1_FORCE_RESET() __HAL_RCC_ADC12_FORCE_RESET()
AnnaBridge 126:abea610beb85 2735 #define __HAL_RCC_ADC2_FORCE_RESET() __HAL_RCC_ADC12_FORCE_RESET()
AnnaBridge 126:abea610beb85 2736
AnnaBridge 126:abea610beb85 2737 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
AnnaBridge 126:abea610beb85 2738 #define __HAL_RCC_ADC12_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC12RST))
AnnaBridge 126:abea610beb85 2739 /* Aliases for STM32 F3 compatibility */
AnnaBridge 126:abea610beb85 2740 #define __HAL_RCC_ADC1_RELEASE_RESET() __HAL_RCC_ADC12_RELEASE_RESET()
AnnaBridge 126:abea610beb85 2741 #define __HAL_RCC_ADC2_RELEASE_RESET() __HAL_RCC_ADC12_RELEASE_RESET()
AnnaBridge 126:abea610beb85 2742 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
AnnaBridge 126:abea610beb85 2743 /* STM32F302xC || STM32F303xC || STM32F358xx */
AnnaBridge 126:abea610beb85 2744
AnnaBridge 126:abea610beb85 2745 #if defined(STM32F303xE) || defined(STM32F398xx)\
AnnaBridge 126:abea610beb85 2746 || defined(STM32F303xC) || defined(STM32F358xx)
AnnaBridge 126:abea610beb85 2747 #define __HAL_RCC_ADC34_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC34RST))
AnnaBridge 126:abea610beb85 2748
AnnaBridge 126:abea610beb85 2749 #define __HAL_RCC_ADC34_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC34RST))
AnnaBridge 126:abea610beb85 2750 #endif /* STM32F303xE || STM32F398xx || */
AnnaBridge 126:abea610beb85 2751 /* STM32F303xC || STM32F358xx */
AnnaBridge 126:abea610beb85 2752
AnnaBridge 126:abea610beb85 2753 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
AnnaBridge 126:abea610beb85 2754 #define __HAL_RCC_ADC12_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC12RST))
AnnaBridge 126:abea610beb85 2755 /* Aliases for STM32 F3 compatibility */
AnnaBridge 126:abea610beb85 2756 #define __HAL_RCC_ADC1_FORCE_RESET() __HAL_RCC_ADC12_FORCE_RESET()
AnnaBridge 126:abea610beb85 2757 #define __HAL_RCC_ADC2_FORCE_RESET() __HAL_RCC_ADC12_FORCE_RESET()
AnnaBridge 126:abea610beb85 2758
AnnaBridge 126:abea610beb85 2759 #define __HAL_RCC_ADC12_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC12RST))
AnnaBridge 126:abea610beb85 2760 /* Aliases for STM32 F3 compatibility */
AnnaBridge 126:abea610beb85 2761 #define __HAL_RCC_ADC1_RELEASE_RESET() __HAL_RCC_ADC12_RELEASE_RESET()
AnnaBridge 126:abea610beb85 2762 #define __HAL_RCC_ADC2_RELEASE_RESET() __HAL_RCC_ADC12_RELEASE_RESET()
AnnaBridge 126:abea610beb85 2763 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
AnnaBridge 126:abea610beb85 2764
AnnaBridge 126:abea610beb85 2765 #if defined(STM32F373xC) || defined(STM32F378xx)
AnnaBridge 126:abea610beb85 2766 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST))
AnnaBridge 126:abea610beb85 2767
AnnaBridge 126:abea610beb85 2768 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
AnnaBridge 126:abea610beb85 2769 #endif /* STM32F373xC || STM32F378xx */
AnnaBridge 126:abea610beb85 2770
AnnaBridge 126:abea610beb85 2771 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
AnnaBridge 126:abea610beb85 2772 #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_FMCRST))
AnnaBridge 126:abea610beb85 2773 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOGRST))
AnnaBridge 126:abea610beb85 2774 #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOHRST))
AnnaBridge 126:abea610beb85 2775
AnnaBridge 126:abea610beb85 2776 #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FMCRST))
AnnaBridge 126:abea610beb85 2777 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOGRST))
AnnaBridge 126:abea610beb85 2778 #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOHRST))
AnnaBridge 126:abea610beb85 2779 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
AnnaBridge 126:abea610beb85 2780 /**
AnnaBridge 126:abea610beb85 2781 * @}
AnnaBridge 126:abea610beb85 2782 */
AnnaBridge 126:abea610beb85 2783
AnnaBridge 126:abea610beb85 2784 /** @defgroup RCCEx_APB1_Force_Release_Reset RCC Extended APB1 Force Release Reset
AnnaBridge 126:abea610beb85 2785 * @brief Force or release APB1 peripheral reset.
AnnaBridge 126:abea610beb85 2786 * @{
AnnaBridge 126:abea610beb85 2787 */
AnnaBridge 126:abea610beb85 2788 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
AnnaBridge 126:abea610beb85 2789 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
AnnaBridge 126:abea610beb85 2790 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
AnnaBridge 126:abea610beb85 2791 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
AnnaBridge 126:abea610beb85 2792 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
AnnaBridge 126:abea610beb85 2793
AnnaBridge 126:abea610beb85 2794 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
AnnaBridge 126:abea610beb85 2795 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
AnnaBridge 126:abea610beb85 2796 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
AnnaBridge 126:abea610beb85 2797 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
AnnaBridge 126:abea610beb85 2798 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
AnnaBridge 126:abea610beb85 2799
AnnaBridge 126:abea610beb85 2800 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
AnnaBridge 126:abea610beb85 2801 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
AnnaBridge 126:abea610beb85 2802 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
AnnaBridge 126:abea610beb85 2803 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
AnnaBridge 126:abea610beb85 2804 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
AnnaBridge 126:abea610beb85 2805 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
AnnaBridge 126:abea610beb85 2806 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
AnnaBridge 126:abea610beb85 2807 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
AnnaBridge 126:abea610beb85 2808 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
AnnaBridge 126:abea610beb85 2809
AnnaBridge 126:abea610beb85 2810 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
AnnaBridge 126:abea610beb85 2811 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
AnnaBridge 126:abea610beb85 2812 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
AnnaBridge 126:abea610beb85 2813 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
AnnaBridge 126:abea610beb85 2814 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
AnnaBridge 126:abea610beb85 2815 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
AnnaBridge 126:abea610beb85 2816 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
AnnaBridge 126:abea610beb85 2817 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
AnnaBridge 126:abea610beb85 2818 /* STM32F302xC || STM32F303xC || STM32F358xx */
AnnaBridge 126:abea610beb85 2819
AnnaBridge 126:abea610beb85 2820 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
AnnaBridge 126:abea610beb85 2821 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
AnnaBridge 126:abea610beb85 2822 #define __HAL_RCC_DAC2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC2RST))
AnnaBridge 126:abea610beb85 2823
AnnaBridge 126:abea610beb85 2824 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
AnnaBridge 126:abea610beb85 2825 #define __HAL_RCC_DAC2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC2RST))
AnnaBridge 126:abea610beb85 2826 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
AnnaBridge 126:abea610beb85 2827
AnnaBridge 126:abea610beb85 2828 #if defined(STM32F373xC) || defined(STM32F378xx)
AnnaBridge 126:abea610beb85 2829 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
AnnaBridge 126:abea610beb85 2830 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
AnnaBridge 126:abea610beb85 2831 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
AnnaBridge 126:abea610beb85 2832 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
AnnaBridge 126:abea610beb85 2833 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
AnnaBridge 126:abea610beb85 2834 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
AnnaBridge 126:abea610beb85 2835 #define __HAL_RCC_TIM18_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM18RST))
AnnaBridge 126:abea610beb85 2836 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
AnnaBridge 126:abea610beb85 2837 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
AnnaBridge 126:abea610beb85 2838 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
AnnaBridge 126:abea610beb85 2839 #define __HAL_RCC_DAC2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC2RST))
AnnaBridge 126:abea610beb85 2840 #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
AnnaBridge 126:abea610beb85 2841
AnnaBridge 126:abea610beb85 2842 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
AnnaBridge 126:abea610beb85 2843 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
AnnaBridge 126:abea610beb85 2844 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
AnnaBridge 126:abea610beb85 2845 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
AnnaBridge 126:abea610beb85 2846 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
AnnaBridge 126:abea610beb85 2847 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
AnnaBridge 126:abea610beb85 2848 #define __HAL_RCC_TIM18_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM18RST))
AnnaBridge 126:abea610beb85 2849 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
AnnaBridge 126:abea610beb85 2850 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
AnnaBridge 126:abea610beb85 2851 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
AnnaBridge 126:abea610beb85 2852 #define __HAL_RCC_DAC2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC2RST))
AnnaBridge 126:abea610beb85 2853 #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
AnnaBridge 126:abea610beb85 2854 #endif /* STM32F373xC || STM32F378xx */
AnnaBridge 126:abea610beb85 2855
AnnaBridge 126:abea610beb85 2856 #if defined(STM32F303xE) || defined(STM32F398xx)\
AnnaBridge 126:abea610beb85 2857 || defined(STM32F303xC) || defined(STM32F358xx)\
AnnaBridge 126:abea610beb85 2858 || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
AnnaBridge 126:abea610beb85 2859 || defined(STM32F373xC) || defined(STM32F378xx)
AnnaBridge 126:abea610beb85 2860 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
AnnaBridge 126:abea610beb85 2861
AnnaBridge 126:abea610beb85 2862 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
AnnaBridge 126:abea610beb85 2863 #endif /* STM32F303xE || STM32F398xx || */
AnnaBridge 126:abea610beb85 2864 /* STM32F303xC || STM32F358xx || */
AnnaBridge 126:abea610beb85 2865 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
AnnaBridge 126:abea610beb85 2866 /* STM32F373xC || STM32F378xx */
AnnaBridge 126:abea610beb85 2867
AnnaBridge 126:abea610beb85 2868 #if defined(STM32F302xE) || defined(STM32F303xE)\
AnnaBridge 126:abea610beb85 2869 || defined(STM32F302xC) || defined(STM32F303xC)\
AnnaBridge 126:abea610beb85 2870 || defined(STM32F302x8) \
AnnaBridge 126:abea610beb85 2871 || defined(STM32F373xC)
AnnaBridge 126:abea610beb85 2872 #define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
AnnaBridge 126:abea610beb85 2873
AnnaBridge 126:abea610beb85 2874 #define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
AnnaBridge 126:abea610beb85 2875 #endif /* STM32F302xE || STM32F303xE || */
AnnaBridge 126:abea610beb85 2876 /* STM32F302xC || STM32F303xC || */
AnnaBridge 126:abea610beb85 2877 /* STM32F302x8 || */
AnnaBridge 126:abea610beb85 2878 /* STM32F373xC */
AnnaBridge 126:abea610beb85 2879
AnnaBridge 126:abea610beb85 2880 #if !defined(STM32F301x8)
AnnaBridge 126:abea610beb85 2881 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CANRST))
AnnaBridge 126:abea610beb85 2882
AnnaBridge 126:abea610beb85 2883 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST))
AnnaBridge 126:abea610beb85 2884 #endif /* STM32F301x8*/
AnnaBridge 126:abea610beb85 2885
AnnaBridge 126:abea610beb85 2886 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
AnnaBridge 126:abea610beb85 2887 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
AnnaBridge 126:abea610beb85 2888
AnnaBridge 126:abea610beb85 2889 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
AnnaBridge 126:abea610beb85 2890 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
AnnaBridge 126:abea610beb85 2891 /**
AnnaBridge 126:abea610beb85 2892 * @}
AnnaBridge 126:abea610beb85 2893 */
AnnaBridge 126:abea610beb85 2894
AnnaBridge 126:abea610beb85 2895 /** @defgroup RCCEx_APB2_Force_Release_Reset RCC Extended APB2 Force Release Reset
AnnaBridge 126:abea610beb85 2896 * @brief Force or release APB2 peripheral reset.
AnnaBridge 126:abea610beb85 2897 * @{
AnnaBridge 126:abea610beb85 2898 */
AnnaBridge 126:abea610beb85 2899 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
AnnaBridge 126:abea610beb85 2900 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
AnnaBridge 126:abea610beb85 2901 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
AnnaBridge 126:abea610beb85 2902
AnnaBridge 126:abea610beb85 2903 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
AnnaBridge 126:abea610beb85 2904 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
AnnaBridge 126:abea610beb85 2905 /* STM32F302xC || STM32F303xC || STM32F358xx */
AnnaBridge 126:abea610beb85 2906
AnnaBridge 126:abea610beb85 2907 #if defined(STM32F303xE) || defined(STM32F398xx)\
AnnaBridge 126:abea610beb85 2908 || defined(STM32F303xC) || defined(STM32F358xx)
AnnaBridge 126:abea610beb85 2909 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
AnnaBridge 126:abea610beb85 2910
AnnaBridge 126:abea610beb85 2911 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
AnnaBridge 126:abea610beb85 2912 #endif /* STM32F303xE || STM32F398xx || */
AnnaBridge 126:abea610beb85 2913 /* STM32F303xC || STM32F358xx */
AnnaBridge 126:abea610beb85 2914
AnnaBridge 126:abea610beb85 2915 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
AnnaBridge 126:abea610beb85 2916 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
AnnaBridge 126:abea610beb85 2917
AnnaBridge 126:abea610beb85 2918 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
AnnaBridge 126:abea610beb85 2919 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
AnnaBridge 126:abea610beb85 2920
AnnaBridge 126:abea610beb85 2921 #if defined(STM32F334x8)
AnnaBridge 126:abea610beb85 2922 #define __HAL_RCC_HRTIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_HRTIM1RST))
AnnaBridge 126:abea610beb85 2923
AnnaBridge 126:abea610beb85 2924 #define __HAL_RCC_HRTIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_HRTIM1RST))
AnnaBridge 126:abea610beb85 2925 #endif /* STM32F334x8 */
AnnaBridge 126:abea610beb85 2926
AnnaBridge 126:abea610beb85 2927 #if defined(STM32F373xC) || defined(STM32F378xx)
AnnaBridge 126:abea610beb85 2928 #define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
AnnaBridge 126:abea610beb85 2929 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
AnnaBridge 126:abea610beb85 2930 #define __HAL_RCC_TIM19_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM19RST))
AnnaBridge 126:abea610beb85 2931 #define __HAL_RCC_SDADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC1RST))
AnnaBridge 126:abea610beb85 2932 #define __HAL_RCC_SDADC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC2RST))
AnnaBridge 126:abea610beb85 2933 #define __HAL_RCC_SDADC3_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC3RST))
AnnaBridge 126:abea610beb85 2934
AnnaBridge 126:abea610beb85 2935 #define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
AnnaBridge 126:abea610beb85 2936 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
AnnaBridge 126:abea610beb85 2937 #define __HAL_RCC_TIM19_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM19RST))
AnnaBridge 126:abea610beb85 2938 #define __HAL_RCC_SDADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC1RST))
AnnaBridge 126:abea610beb85 2939 #define __HAL_RCC_SDADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC2RST))
AnnaBridge 126:abea610beb85 2940 #define __HAL_RCC_SDADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC3RST))
AnnaBridge 126:abea610beb85 2941 #endif /* STM32F373xC || STM32F378xx */
AnnaBridge 126:abea610beb85 2942
AnnaBridge 126:abea610beb85 2943 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
AnnaBridge 126:abea610beb85 2944 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
AnnaBridge 126:abea610beb85 2945 || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
AnnaBridge 126:abea610beb85 2946 || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
AnnaBridge 126:abea610beb85 2947 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
AnnaBridge 126:abea610beb85 2948
AnnaBridge 126:abea610beb85 2949 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
AnnaBridge 126:abea610beb85 2950 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
AnnaBridge 126:abea610beb85 2951 /* STM32F302xC || STM32F303xC || STM32F358xx || */
AnnaBridge 126:abea610beb85 2952 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
AnnaBridge 126:abea610beb85 2953 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
AnnaBridge 126:abea610beb85 2954
AnnaBridge 126:abea610beb85 2955 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
AnnaBridge 126:abea610beb85 2956 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
AnnaBridge 126:abea610beb85 2957
AnnaBridge 126:abea610beb85 2958 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
AnnaBridge 126:abea610beb85 2959 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
AnnaBridge 126:abea610beb85 2960
AnnaBridge 126:abea610beb85 2961 #if defined(STM32F303xE) || defined(STM32F398xx)
AnnaBridge 126:abea610beb85 2962 #define __HAL_RCC_TIM20_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM20RST))
AnnaBridge 126:abea610beb85 2963
AnnaBridge 126:abea610beb85 2964 #define __HAL_RCC_TIM20_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM20RST))
AnnaBridge 126:abea610beb85 2965 #endif /* STM32F303xE || STM32F398xx */
AnnaBridge 126:abea610beb85 2966
AnnaBridge 126:abea610beb85 2967 /**
AnnaBridge 126:abea610beb85 2968 * @}
AnnaBridge 126:abea610beb85 2969 */
AnnaBridge 126:abea610beb85 2970
AnnaBridge 126:abea610beb85 2971 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
AnnaBridge 126:abea610beb85 2972 /** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
AnnaBridge 126:abea610beb85 2973 * @{
AnnaBridge 126:abea610beb85 2974 */
AnnaBridge 126:abea610beb85 2975
AnnaBridge 126:abea610beb85 2976 /** @brief Macro to configure the I2C2 clock (I2C2CLK).
AnnaBridge 126:abea610beb85 2977 * @param __I2C2CLKSource__ specifies the I2C2 clock source.
AnnaBridge 126:abea610beb85 2978 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 2979 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
AnnaBridge 126:abea610beb85 2980 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
AnnaBridge 126:abea610beb85 2981 */
AnnaBridge 126:abea610beb85 2982 #define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
AnnaBridge 126:abea610beb85 2983 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
AnnaBridge 126:abea610beb85 2984
AnnaBridge 126:abea610beb85 2985 /** @brief Macro to get the I2C2 clock source.
AnnaBridge 126:abea610beb85 2986 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 2987 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
AnnaBridge 126:abea610beb85 2988 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
AnnaBridge 126:abea610beb85 2989 */
AnnaBridge 126:abea610beb85 2990 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
AnnaBridge 126:abea610beb85 2991
AnnaBridge 126:abea610beb85 2992 /** @brief Macro to configure the I2C3 clock (I2C3CLK).
AnnaBridge 126:abea610beb85 2993 * @param __I2C3CLKSource__ specifies the I2C3 clock source.
AnnaBridge 126:abea610beb85 2994 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 2995 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
AnnaBridge 126:abea610beb85 2996 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
AnnaBridge 126:abea610beb85 2997 */
AnnaBridge 126:abea610beb85 2998 #define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \
AnnaBridge 126:abea610beb85 2999 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C3SW, (uint32_t)(__I2C3CLKSource__))
AnnaBridge 126:abea610beb85 3000
AnnaBridge 126:abea610beb85 3001 /** @brief Macro to get the I2C3 clock source.
AnnaBridge 126:abea610beb85 3002 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 3003 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
AnnaBridge 126:abea610beb85 3004 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
AnnaBridge 126:abea610beb85 3005 */
AnnaBridge 126:abea610beb85 3006 #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C3SW)))
AnnaBridge 126:abea610beb85 3007
AnnaBridge 126:abea610beb85 3008 /**
AnnaBridge 126:abea610beb85 3009 * @}
AnnaBridge 126:abea610beb85 3010 */
AnnaBridge 126:abea610beb85 3011
AnnaBridge 126:abea610beb85 3012 /** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
AnnaBridge 126:abea610beb85 3013 * @{
AnnaBridge 126:abea610beb85 3014 */
AnnaBridge 126:abea610beb85 3015 /** @brief Macro to configure the TIM1 clock (TIM1CLK).
AnnaBridge 126:abea610beb85 3016 * @param __TIM1CLKSource__ specifies the TIM1 clock source.
AnnaBridge 126:abea610beb85 3017 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 3018 * @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock
AnnaBridge 126:abea610beb85 3019 * @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock
AnnaBridge 126:abea610beb85 3020 */
AnnaBridge 126:abea610beb85 3021 #define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \
AnnaBridge 126:abea610beb85 3022 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__))
AnnaBridge 126:abea610beb85 3023
AnnaBridge 126:abea610beb85 3024 /** @brief Macro to get the TIM1 clock (TIM1CLK).
AnnaBridge 126:abea610beb85 3025 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 3026 * @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock
AnnaBridge 126:abea610beb85 3027 * @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock
AnnaBridge 126:abea610beb85 3028 */
AnnaBridge 126:abea610beb85 3029 #define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
AnnaBridge 126:abea610beb85 3030
AnnaBridge 126:abea610beb85 3031 /** @brief Macro to configure the TIM15 clock (TIM15CLK).
AnnaBridge 126:abea610beb85 3032 * @param __TIM15CLKSource__ specifies the TIM15 clock source.
AnnaBridge 126:abea610beb85 3033 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 3034 * @arg @ref RCC_TIM15CLK_HCLK HCLK selected as TIM15 clock
AnnaBridge 126:abea610beb85 3035 * @arg @ref RCC_TIM15CLK_PLL PLL Clock selected as TIM15 clock
AnnaBridge 126:abea610beb85 3036 */
AnnaBridge 126:abea610beb85 3037 #define __HAL_RCC_TIM15_CONFIG(__TIM15CLKSource__) \
AnnaBridge 126:abea610beb85 3038 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM15SW, (uint32_t)(__TIM15CLKSource__))
AnnaBridge 126:abea610beb85 3039
AnnaBridge 126:abea610beb85 3040 /** @brief Macro to get the TIM15 clock (TIM15CLK).
AnnaBridge 126:abea610beb85 3041 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 3042 * @arg @ref RCC_TIM15CLK_HCLK HCLK selected as TIM15 clock
AnnaBridge 126:abea610beb85 3043 * @arg @ref RCC_TIM15CLK_PLL PLL Clock selected as TIM15 clock
AnnaBridge 126:abea610beb85 3044 */
AnnaBridge 126:abea610beb85 3045 #define __HAL_RCC_GET_TIM15_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM15SW)))
AnnaBridge 126:abea610beb85 3046
AnnaBridge 126:abea610beb85 3047 /** @brief Macro to configure the TIM16 clock (TIM16CLK).
AnnaBridge 126:abea610beb85 3048 * @param __TIM16CLKSource__ specifies the TIM16 clock source.
AnnaBridge 126:abea610beb85 3049 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 3050 * @arg @ref RCC_TIM16CLK_HCLK HCLK selected as TIM16 clock
AnnaBridge 126:abea610beb85 3051 * @arg @ref RCC_TIM16CLK_PLL PLL Clock selected as TIM16 clock
AnnaBridge 126:abea610beb85 3052 */
AnnaBridge 126:abea610beb85 3053 #define __HAL_RCC_TIM16_CONFIG(__TIM16CLKSource__) \
AnnaBridge 126:abea610beb85 3054 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM16SW, (uint32_t)(__TIM16CLKSource__))
AnnaBridge 126:abea610beb85 3055
AnnaBridge 126:abea610beb85 3056 /** @brief Macro to get the TIM16 clock (TIM16CLK).
AnnaBridge 126:abea610beb85 3057 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 3058 * @arg @ref RCC_TIM16CLK_HCLK HCLK selected as TIM16 clock
AnnaBridge 126:abea610beb85 3059 * @arg @ref RCC_TIM16CLK_PLL PLL Clock selected as TIM16 clock
AnnaBridge 126:abea610beb85 3060 */
AnnaBridge 126:abea610beb85 3061 #define __HAL_RCC_GET_TIM16_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM16SW)))
AnnaBridge 126:abea610beb85 3062
AnnaBridge 126:abea610beb85 3063 /** @brief Macro to configure the TIM17 clock (TIM17CLK).
AnnaBridge 126:abea610beb85 3064 * @param __TIM17CLKSource__ specifies the TIM17 clock source.
AnnaBridge 126:abea610beb85 3065 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 3066 * @arg @ref RCC_TIM17CLK_HCLK HCLK selected as TIM17 clock
AnnaBridge 126:abea610beb85 3067 * @arg @ref RCC_TIM17CLK_PLL PLL Clock selected as TIM17 clock
AnnaBridge 126:abea610beb85 3068 */
AnnaBridge 126:abea610beb85 3069 #define __HAL_RCC_TIM17_CONFIG(__TIM17CLKSource__) \
AnnaBridge 126:abea610beb85 3070 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM17SW, (uint32_t)(__TIM17CLKSource__))
AnnaBridge 126:abea610beb85 3071
AnnaBridge 126:abea610beb85 3072 /** @brief Macro to get the TIM17 clock (TIM17CLK).
AnnaBridge 126:abea610beb85 3073 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 3074 * @arg @ref RCC_TIM17CLK_HCLK HCLK selected as TIM17 clock
AnnaBridge 126:abea610beb85 3075 * @arg @ref RCC_TIM17CLK_PLL PLL Clock selected as TIM17 clock
AnnaBridge 126:abea610beb85 3076 */
AnnaBridge 126:abea610beb85 3077 #define __HAL_RCC_GET_TIM17_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM17SW)))
AnnaBridge 126:abea610beb85 3078
AnnaBridge 126:abea610beb85 3079 /**
AnnaBridge 126:abea610beb85 3080 * @}
AnnaBridge 126:abea610beb85 3081 */
AnnaBridge 126:abea610beb85 3082
AnnaBridge 126:abea610beb85 3083 /** @defgroup RCCEx_I2Sx_Clock_Config RCC Extended I2Sx Clock Config
AnnaBridge 126:abea610beb85 3084 * @{
AnnaBridge 126:abea610beb85 3085 */
AnnaBridge 126:abea610beb85 3086 /** @brief Macro to configure the I2S clock source (I2SCLK).
AnnaBridge 126:abea610beb85 3087 * @note This function must be called before enabling the I2S APB clock.
AnnaBridge 126:abea610beb85 3088 * @param __I2SCLKSource__ specifies the I2S clock source.
AnnaBridge 126:abea610beb85 3089 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 3090 * @arg @ref RCC_I2SCLKSOURCE_SYSCLK SYSCLK clock used as I2S clock source
AnnaBridge 126:abea610beb85 3091 * @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin
AnnaBridge 126:abea610beb85 3092 * used as I2S clock source
AnnaBridge 126:abea610beb85 3093 */
AnnaBridge 126:abea610beb85 3094 #define __HAL_RCC_I2S_CONFIG(__I2SCLKSource__) \
AnnaBridge 126:abea610beb85 3095 MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, (uint32_t)(__I2SCLKSource__))
AnnaBridge 126:abea610beb85 3096
AnnaBridge 126:abea610beb85 3097 /** @brief Macro to get the I2S clock source (I2SCLK).
AnnaBridge 126:abea610beb85 3098 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 3099 * @arg @ref RCC_I2SCLKSOURCE_SYSCLK SYSCLK clock used as I2S clock source
AnnaBridge 126:abea610beb85 3100 * @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin
AnnaBridge 126:abea610beb85 3101 * used as I2S clock source
AnnaBridge 126:abea610beb85 3102 */
AnnaBridge 126:abea610beb85 3103 #define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))
AnnaBridge 126:abea610beb85 3104 /**
AnnaBridge 126:abea610beb85 3105 * @}
AnnaBridge 126:abea610beb85 3106 */
AnnaBridge 126:abea610beb85 3107
AnnaBridge 126:abea610beb85 3108 /** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
AnnaBridge 126:abea610beb85 3109 * @{
AnnaBridge 126:abea610beb85 3110 */
AnnaBridge 126:abea610beb85 3111
AnnaBridge 126:abea610beb85 3112 /** @brief Macro to configure the ADC1 clock (ADC1CLK).
AnnaBridge 126:abea610beb85 3113 * @param __ADC1CLKSource__ specifies the ADC1 clock source.
AnnaBridge 126:abea610beb85 3114 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 3115 * @arg @ref RCC_ADC1PLLCLK_OFF ADC1 PLL clock disabled, ADC1 can use AHB clock
AnnaBridge 126:abea610beb85 3116 * @arg @ref RCC_ADC1PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 clock
AnnaBridge 126:abea610beb85 3117 * @arg @ref RCC_ADC1PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 clock
AnnaBridge 126:abea610beb85 3118 * @arg @ref RCC_ADC1PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 clock
AnnaBridge 126:abea610beb85 3119 * @arg @ref RCC_ADC1PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 clock
AnnaBridge 126:abea610beb85 3120 * @arg @ref RCC_ADC1PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 clock
AnnaBridge 126:abea610beb85 3121 * @arg @ref RCC_ADC1PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 clock
AnnaBridge 126:abea610beb85 3122 * @arg @ref RCC_ADC1PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 clock
AnnaBridge 126:abea610beb85 3123 * @arg @ref RCC_ADC1PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 clock
AnnaBridge 126:abea610beb85 3124 * @arg @ref RCC_ADC1PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 clock
AnnaBridge 126:abea610beb85 3125 * @arg @ref RCC_ADC1PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 clock
AnnaBridge 126:abea610beb85 3126 * @arg @ref RCC_ADC1PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 clock
AnnaBridge 126:abea610beb85 3127 * @arg @ref RCC_ADC1PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 clock
AnnaBridge 126:abea610beb85 3128 */
AnnaBridge 126:abea610beb85 3129 #define __HAL_RCC_ADC1_CONFIG(__ADC1CLKSource__) \
AnnaBridge 126:abea610beb85 3130 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADC1PRES, (uint32_t)(__ADC1CLKSource__))
AnnaBridge 126:abea610beb85 3131
AnnaBridge 126:abea610beb85 3132 /** @brief Macro to get the ADC1 clock
AnnaBridge 126:abea610beb85 3133 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 3134 * @arg @ref RCC_ADC1PLLCLK_OFF ADC1 PLL clock disabled, ADC1 can use AHB clock
AnnaBridge 126:abea610beb85 3135 * @arg @ref RCC_ADC1PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 clock
AnnaBridge 126:abea610beb85 3136 * @arg @ref RCC_ADC1PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 clock
AnnaBridge 126:abea610beb85 3137 * @arg @ref RCC_ADC1PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 clock
AnnaBridge 126:abea610beb85 3138 * @arg @ref RCC_ADC1PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 clock
AnnaBridge 126:abea610beb85 3139 * @arg @ref RCC_ADC1PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 clock
AnnaBridge 126:abea610beb85 3140 * @arg @ref RCC_ADC1PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 clock
AnnaBridge 126:abea610beb85 3141 * @arg @ref RCC_ADC1PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 clock
AnnaBridge 126:abea610beb85 3142 * @arg @ref RCC_ADC1PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 clock
AnnaBridge 126:abea610beb85 3143 * @arg @ref RCC_ADC1PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 clock
AnnaBridge 126:abea610beb85 3144 * @arg @ref RCC_ADC1PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 clock
AnnaBridge 126:abea610beb85 3145 * @arg @ref RCC_ADC1PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 clock
AnnaBridge 126:abea610beb85 3146 * @arg @ref RCC_ADC1PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 clock
AnnaBridge 126:abea610beb85 3147 */
AnnaBridge 126:abea610beb85 3148 #define __HAL_RCC_GET_ADC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADC1PRES)))
AnnaBridge 126:abea610beb85 3149 /**
AnnaBridge 126:abea610beb85 3150 * @}
AnnaBridge 126:abea610beb85 3151 */
AnnaBridge 126:abea610beb85 3152
AnnaBridge 126:abea610beb85 3153 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
AnnaBridge 126:abea610beb85 3154
AnnaBridge 126:abea610beb85 3155 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
AnnaBridge 126:abea610beb85 3156 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
AnnaBridge 126:abea610beb85 3157 /** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
AnnaBridge 126:abea610beb85 3158 * @{
AnnaBridge 126:abea610beb85 3159 */
AnnaBridge 126:abea610beb85 3160
AnnaBridge 126:abea610beb85 3161 /** @brief Macro to configure the I2C2 clock (I2C2CLK).
AnnaBridge 126:abea610beb85 3162 * @param __I2C2CLKSource__ specifies the I2C2 clock source.
AnnaBridge 126:abea610beb85 3163 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 3164 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
AnnaBridge 126:abea610beb85 3165 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
AnnaBridge 126:abea610beb85 3166 */
AnnaBridge 126:abea610beb85 3167 #define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
AnnaBridge 126:abea610beb85 3168 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
AnnaBridge 126:abea610beb85 3169
AnnaBridge 126:abea610beb85 3170 /** @brief Macro to get the I2C2 clock source.
AnnaBridge 126:abea610beb85 3171 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 3172 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
AnnaBridge 126:abea610beb85 3173 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
AnnaBridge 126:abea610beb85 3174 */
AnnaBridge 126:abea610beb85 3175 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
AnnaBridge 126:abea610beb85 3176 /**
AnnaBridge 126:abea610beb85 3177 * @}
AnnaBridge 126:abea610beb85 3178 */
AnnaBridge 126:abea610beb85 3179
AnnaBridge 126:abea610beb85 3180 /** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
AnnaBridge 126:abea610beb85 3181 * @{
AnnaBridge 126:abea610beb85 3182 */
AnnaBridge 126:abea610beb85 3183
AnnaBridge 126:abea610beb85 3184 /** @brief Macro to configure the ADC1 & ADC2 clock (ADC12CLK).
AnnaBridge 126:abea610beb85 3185 * @param __ADC12CLKSource__ specifies the ADC1 & ADC2 clock source.
AnnaBridge 126:abea610beb85 3186 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 3187 * @arg @ref RCC_ADC12PLLCLK_OFF ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
AnnaBridge 126:abea610beb85 3188 * @arg @ref RCC_ADC12PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3189 * @arg @ref RCC_ADC12PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3190 * @arg @ref RCC_ADC12PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3191 * @arg @ref RCC_ADC12PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3192 * @arg @ref RCC_ADC12PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3193 * @arg @ref RCC_ADC12PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3194 * @arg @ref RCC_ADC12PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3195 * @arg @ref RCC_ADC12PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3196 * @arg @ref RCC_ADC12PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3197 * @arg @ref RCC_ADC12PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3198 * @arg @ref RCC_ADC12PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3199 * @arg @ref RCC_ADC12PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3200 */
AnnaBridge 126:abea610beb85 3201 #define __HAL_RCC_ADC12_CONFIG(__ADC12CLKSource__) \
AnnaBridge 126:abea610beb85 3202 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, (uint32_t)(__ADC12CLKSource__))
AnnaBridge 126:abea610beb85 3203
AnnaBridge 126:abea610beb85 3204 /** @brief Macro to get the ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3205 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 3206 * @arg @ref RCC_ADC12PLLCLK_OFF ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
AnnaBridge 126:abea610beb85 3207 * @arg @ref RCC_ADC12PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3208 * @arg @ref RCC_ADC12PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3209 * @arg @ref RCC_ADC12PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3210 * @arg @ref RCC_ADC12PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3211 * @arg @ref RCC_ADC12PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3212 * @arg @ref RCC_ADC12PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3213 * @arg @ref RCC_ADC12PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3214 * @arg @ref RCC_ADC12PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3215 * @arg @ref RCC_ADC12PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3216 * @arg @ref RCC_ADC12PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3217 * @arg @ref RCC_ADC12PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3218 * @arg @ref RCC_ADC12PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3219 */
AnnaBridge 126:abea610beb85 3220 #define __HAL_RCC_GET_ADC12_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE12)))
AnnaBridge 126:abea610beb85 3221 /**
AnnaBridge 126:abea610beb85 3222 * @}
AnnaBridge 126:abea610beb85 3223 */
AnnaBridge 126:abea610beb85 3224
AnnaBridge 126:abea610beb85 3225 /** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
AnnaBridge 126:abea610beb85 3226 * @{
AnnaBridge 126:abea610beb85 3227 */
AnnaBridge 126:abea610beb85 3228
AnnaBridge 126:abea610beb85 3229 /** @brief Macro to configure the TIM1 clock (TIM1CLK).
AnnaBridge 126:abea610beb85 3230 * @param __TIM1CLKSource__ specifies the TIM1 clock source.
AnnaBridge 126:abea610beb85 3231 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 3232 * @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock
AnnaBridge 126:abea610beb85 3233 * @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock
AnnaBridge 126:abea610beb85 3234 */
AnnaBridge 126:abea610beb85 3235 #define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \
AnnaBridge 126:abea610beb85 3236 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__))
AnnaBridge 126:abea610beb85 3237
AnnaBridge 126:abea610beb85 3238 /** @brief Macro to get the TIM1 clock (TIM1CLK).
AnnaBridge 126:abea610beb85 3239 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 3240 * @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock
AnnaBridge 126:abea610beb85 3241 * @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock
AnnaBridge 126:abea610beb85 3242 */
AnnaBridge 126:abea610beb85 3243 #define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
AnnaBridge 126:abea610beb85 3244 /**
AnnaBridge 126:abea610beb85 3245 * @}
AnnaBridge 126:abea610beb85 3246 */
AnnaBridge 126:abea610beb85 3247
AnnaBridge 126:abea610beb85 3248 /** @defgroup RCCEx_I2Sx_Clock_Config RCC Extended I2Sx Clock Config
AnnaBridge 126:abea610beb85 3249 * @{
AnnaBridge 126:abea610beb85 3250 */
AnnaBridge 126:abea610beb85 3251
AnnaBridge 126:abea610beb85 3252 /** @brief Macro to configure the I2S clock source (I2SCLK).
AnnaBridge 126:abea610beb85 3253 * @note This function must be called before enabling the I2S APB clock.
AnnaBridge 126:abea610beb85 3254 * @param __I2SCLKSource__ specifies the I2S clock source.
AnnaBridge 126:abea610beb85 3255 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 3256 * @arg @ref RCC_I2SCLKSOURCE_SYSCLK SYSCLK clock used as I2S clock source
AnnaBridge 126:abea610beb85 3257 * @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin
AnnaBridge 126:abea610beb85 3258 * used as I2S clock source
AnnaBridge 126:abea610beb85 3259 */
AnnaBridge 126:abea610beb85 3260 #define __HAL_RCC_I2S_CONFIG(__I2SCLKSource__) \
AnnaBridge 126:abea610beb85 3261 MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, (uint32_t)(__I2SCLKSource__))
AnnaBridge 126:abea610beb85 3262
AnnaBridge 126:abea610beb85 3263 /** @brief Macro to get the I2S clock source (I2SCLK).
AnnaBridge 126:abea610beb85 3264 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 3265 * @arg @ref RCC_I2SCLKSOURCE_SYSCLK SYSCLK clock used as I2S clock source
AnnaBridge 126:abea610beb85 3266 * @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin
AnnaBridge 126:abea610beb85 3267 * used as I2S clock source
AnnaBridge 126:abea610beb85 3268 */
AnnaBridge 126:abea610beb85 3269 #define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))
AnnaBridge 126:abea610beb85 3270 /**
AnnaBridge 126:abea610beb85 3271 * @}
AnnaBridge 126:abea610beb85 3272 */
AnnaBridge 126:abea610beb85 3273
AnnaBridge 126:abea610beb85 3274 /** @defgroup RCCEx_UARTx_Clock_Config RCC Extended UARTx Clock Config
AnnaBridge 126:abea610beb85 3275 * @{
AnnaBridge 126:abea610beb85 3276 */
AnnaBridge 126:abea610beb85 3277
AnnaBridge 126:abea610beb85 3278 /** @brief Macro to configure the UART4 clock (UART4CLK).
AnnaBridge 126:abea610beb85 3279 * @param __UART4CLKSource__ specifies the UART4 clock source.
AnnaBridge 126:abea610beb85 3280 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 3281 * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock
AnnaBridge 126:abea610beb85 3282 * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock
AnnaBridge 126:abea610beb85 3283 * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock
AnnaBridge 126:abea610beb85 3284 * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock
AnnaBridge 126:abea610beb85 3285 */
AnnaBridge 126:abea610beb85 3286 #define __HAL_RCC_UART4_CONFIG(__UART4CLKSource__) \
AnnaBridge 126:abea610beb85 3287 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_UART4SW, (uint32_t)(__UART4CLKSource__))
AnnaBridge 126:abea610beb85 3288
AnnaBridge 126:abea610beb85 3289 /** @brief Macro to get the UART4 clock source.
AnnaBridge 126:abea610beb85 3290 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 3291 * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock
AnnaBridge 126:abea610beb85 3292 * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock
AnnaBridge 126:abea610beb85 3293 * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock
AnnaBridge 126:abea610beb85 3294 * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock
AnnaBridge 126:abea610beb85 3295 */
AnnaBridge 126:abea610beb85 3296 #define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_UART4SW)))
AnnaBridge 126:abea610beb85 3297
AnnaBridge 126:abea610beb85 3298 /** @brief Macro to configure the UART5 clock (UART5CLK).
AnnaBridge 126:abea610beb85 3299 * @param __UART5CLKSource__ specifies the UART5 clock source.
AnnaBridge 126:abea610beb85 3300 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 3301 * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock
AnnaBridge 126:abea610beb85 3302 * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock
AnnaBridge 126:abea610beb85 3303 * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock
AnnaBridge 126:abea610beb85 3304 * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock
AnnaBridge 126:abea610beb85 3305 */
AnnaBridge 126:abea610beb85 3306 #define __HAL_RCC_UART5_CONFIG(__UART5CLKSource__) \
AnnaBridge 126:abea610beb85 3307 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_UART5SW, (uint32_t)(__UART5CLKSource__))
AnnaBridge 126:abea610beb85 3308
AnnaBridge 126:abea610beb85 3309 /** @brief Macro to get the UART5 clock source.
AnnaBridge 126:abea610beb85 3310 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 3311 * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock
AnnaBridge 126:abea610beb85 3312 * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock
AnnaBridge 126:abea610beb85 3313 * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock
AnnaBridge 126:abea610beb85 3314 * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock
AnnaBridge 126:abea610beb85 3315 */
AnnaBridge 126:abea610beb85 3316 #define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_UART5SW)))
AnnaBridge 126:abea610beb85 3317 /**
AnnaBridge 126:abea610beb85 3318 * @}
AnnaBridge 126:abea610beb85 3319 */
AnnaBridge 126:abea610beb85 3320 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
AnnaBridge 126:abea610beb85 3321 /* STM32F302xC || STM32F303xC || STM32F358xx */
AnnaBridge 126:abea610beb85 3322
AnnaBridge 126:abea610beb85 3323 #if defined(STM32F303xE) || defined(STM32F398xx)\
AnnaBridge 126:abea610beb85 3324 || defined(STM32F303xC) || defined(STM32F358xx)
AnnaBridge 126:abea610beb85 3325 /** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
AnnaBridge 126:abea610beb85 3326 * @{
AnnaBridge 126:abea610beb85 3327 */
AnnaBridge 126:abea610beb85 3328
AnnaBridge 126:abea610beb85 3329 /** @brief Macro to configure the ADC3 & ADC4 clock (ADC34CLK).
AnnaBridge 126:abea610beb85 3330 * @param __ADC34CLKSource__ specifies the ADC3 & ADC4 clock source.
AnnaBridge 126:abea610beb85 3331 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 3332 * @arg @ref RCC_ADC34PLLCLK_OFF ADC3 & ADC4 PLL clock disabled, ADC3 & ADC4 can use AHB clock
AnnaBridge 126:abea610beb85 3333 * @arg @ref RCC_ADC34PLLCLK_DIV1 PLL clock divided by 1 selected as ADC3 & ADC4 clock
AnnaBridge 126:abea610beb85 3334 * @arg @ref RCC_ADC34PLLCLK_DIV2 PLL clock divided by 2 selected as ADC3 & ADC4 clock
AnnaBridge 126:abea610beb85 3335 * @arg @ref RCC_ADC34PLLCLK_DIV4 PLL clock divided by 4 selected as ADC3 & ADC4 clock
AnnaBridge 126:abea610beb85 3336 * @arg @ref RCC_ADC34PLLCLK_DIV6 PLL clock divided by 6 selected as ADC3 & ADC4 clock
AnnaBridge 126:abea610beb85 3337 * @arg @ref RCC_ADC34PLLCLK_DIV8 PLL clock divided by 8 selected as ADC3 & ADC4 clock
AnnaBridge 126:abea610beb85 3338 * @arg @ref RCC_ADC34PLLCLK_DIV10 PLL clock divided by 10 selected as ADC3 & ADC4 clock
AnnaBridge 126:abea610beb85 3339 * @arg @ref RCC_ADC34PLLCLK_DIV12 PLL clock divided by 12 selected as ADC3 & ADC4 clock
AnnaBridge 126:abea610beb85 3340 * @arg @ref RCC_ADC34PLLCLK_DIV16 PLL clock divided by 16 selected as ADC3 & ADC4 clock
AnnaBridge 126:abea610beb85 3341 * @arg @ref RCC_ADC34PLLCLK_DIV32 PLL clock divided by 32 selected as ADC3 & ADC4 clock
AnnaBridge 126:abea610beb85 3342 * @arg @ref RCC_ADC34PLLCLK_DIV64 PLL clock divided by 64 selected as ADC3 & ADC4 clock
AnnaBridge 126:abea610beb85 3343 * @arg @ref RCC_ADC34PLLCLK_DIV128 PLL clock divided by 128 selected as ADC3 & ADC4 clock
AnnaBridge 126:abea610beb85 3344 * @arg @ref RCC_ADC34PLLCLK_DIV256 PLL clock divided by 256 selected as ADC3 & ADC4 clock
AnnaBridge 126:abea610beb85 3345 */
AnnaBridge 126:abea610beb85 3346 #define __HAL_RCC_ADC34_CONFIG(__ADC34CLKSource__) \
AnnaBridge 126:abea610beb85 3347 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE34, (uint32_t)(__ADC34CLKSource__))
AnnaBridge 126:abea610beb85 3348
AnnaBridge 126:abea610beb85 3349 /** @brief Macro to get the ADC3 & ADC4 clock
AnnaBridge 126:abea610beb85 3350 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 3351 * @arg @ref RCC_ADC34PLLCLK_OFF ADC3 & ADC4 PLL clock disabled, ADC3 & ADC4 can use AHB clock
AnnaBridge 126:abea610beb85 3352 * @arg @ref RCC_ADC34PLLCLK_DIV1 PLL clock divided by 1 selected as ADC3 & ADC4 clock
AnnaBridge 126:abea610beb85 3353 * @arg @ref RCC_ADC34PLLCLK_DIV2 PLL clock divided by 2 selected as ADC3 & ADC4 clock
AnnaBridge 126:abea610beb85 3354 * @arg @ref RCC_ADC34PLLCLK_DIV4 PLL clock divided by 4 selected as ADC3 & ADC4 clock
AnnaBridge 126:abea610beb85 3355 * @arg @ref RCC_ADC34PLLCLK_DIV6 PLL clock divided by 6 selected as ADC3 & ADC4 clock
AnnaBridge 126:abea610beb85 3356 * @arg @ref RCC_ADC34PLLCLK_DIV8 PLL clock divided by 8 selected as ADC3 & ADC4 clock
AnnaBridge 126:abea610beb85 3357 * @arg @ref RCC_ADC34PLLCLK_DIV10 PLL clock divided by 10 selected as ADC3 & ADC4 clock
AnnaBridge 126:abea610beb85 3358 * @arg @ref RCC_ADC34PLLCLK_DIV12 PLL clock divided by 12 selected as ADC3 & ADC4 clock
AnnaBridge 126:abea610beb85 3359 * @arg @ref RCC_ADC34PLLCLK_DIV16 PLL clock divided by 16 selected as ADC3 & ADC4 clock
AnnaBridge 126:abea610beb85 3360 * @arg @ref RCC_ADC34PLLCLK_DIV32 PLL clock divided by 32 selected as ADC3 & ADC4 clock
AnnaBridge 126:abea610beb85 3361 * @arg @ref RCC_ADC34PLLCLK_DIV64 PLL clock divided by 64 selected as ADC3 & ADC4 clock
AnnaBridge 126:abea610beb85 3362 * @arg @ref RCC_ADC34PLLCLK_DIV128 PLL clock divided by 128 selected as ADC3 & ADC4 clock
AnnaBridge 126:abea610beb85 3363 * @arg @ref RCC_ADC34PLLCLK_DIV256 PLL clock divided by 256 selected as ADC3 & ADC4 clock
AnnaBridge 126:abea610beb85 3364 */
AnnaBridge 126:abea610beb85 3365 #define __HAL_RCC_GET_ADC34_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE34)))
AnnaBridge 126:abea610beb85 3366 /**
AnnaBridge 126:abea610beb85 3367 * @}
AnnaBridge 126:abea610beb85 3368 */
AnnaBridge 126:abea610beb85 3369
AnnaBridge 126:abea610beb85 3370 /** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
AnnaBridge 126:abea610beb85 3371 * @{
AnnaBridge 126:abea610beb85 3372 */
AnnaBridge 126:abea610beb85 3373
AnnaBridge 126:abea610beb85 3374 /** @brief Macro to configure the TIM8 clock (TIM8CLK).
AnnaBridge 126:abea610beb85 3375 * @param __TIM8CLKSource__ specifies the TIM8 clock source.
AnnaBridge 126:abea610beb85 3376 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 3377 * @arg @ref RCC_TIM8CLK_HCLK HCLK selected as TIM8 clock
AnnaBridge 126:abea610beb85 3378 * @arg @ref RCC_TIM8CLK_PLLCLK PLL Clock selected as TIM8 clock
AnnaBridge 126:abea610beb85 3379 */
AnnaBridge 126:abea610beb85 3380 #define __HAL_RCC_TIM8_CONFIG(__TIM8CLKSource__) \
AnnaBridge 126:abea610beb85 3381 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM8SW, (uint32_t)(__TIM8CLKSource__))
AnnaBridge 126:abea610beb85 3382
AnnaBridge 126:abea610beb85 3383 /** @brief Macro to get the TIM8 clock (TIM8CLK).
AnnaBridge 126:abea610beb85 3384 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 3385 * @arg @ref RCC_TIM8CLK_HCLK HCLK selected as TIM8 clock
AnnaBridge 126:abea610beb85 3386 * @arg @ref RCC_TIM8CLK_PLLCLK PLL Clock selected as TIM8 clock
AnnaBridge 126:abea610beb85 3387 */
AnnaBridge 126:abea610beb85 3388 #define __HAL_RCC_GET_TIM8_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM8SW)))
AnnaBridge 126:abea610beb85 3389
AnnaBridge 126:abea610beb85 3390 /**
AnnaBridge 126:abea610beb85 3391 * @}
AnnaBridge 126:abea610beb85 3392 */
AnnaBridge 126:abea610beb85 3393 #endif /* STM32F303xE || STM32F398xx || */
AnnaBridge 126:abea610beb85 3394 /* STM32F303xC || STM32F358xx */
AnnaBridge 126:abea610beb85 3395
AnnaBridge 126:abea610beb85 3396 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
AnnaBridge 126:abea610beb85 3397 /** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
AnnaBridge 126:abea610beb85 3398 * @{
AnnaBridge 126:abea610beb85 3399 */
AnnaBridge 126:abea610beb85 3400
AnnaBridge 126:abea610beb85 3401 /** @brief Macro to configure the ADC1 & ADC2 clock (ADC12CLK).
AnnaBridge 126:abea610beb85 3402 * @param __ADC12CLKSource__ specifies the ADC1 & ADC2 clock source.
AnnaBridge 126:abea610beb85 3403 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 3404 * @arg @ref RCC_ADC12PLLCLK_OFF ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
AnnaBridge 126:abea610beb85 3405 * @arg @ref RCC_ADC12PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3406 * @arg @ref RCC_ADC12PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3407 * @arg @ref RCC_ADC12PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3408 * @arg @ref RCC_ADC12PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3409 * @arg @ref RCC_ADC12PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3410 * @arg @ref RCC_ADC12PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3411 * @arg @ref RCC_ADC12PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3412 * @arg @ref RCC_ADC12PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3413 * @arg @ref RCC_ADC12PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3414 * @arg @ref RCC_ADC12PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3415 * @arg @ref RCC_ADC12PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3416 * @arg @ref RCC_ADC12PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3417 */
AnnaBridge 126:abea610beb85 3418 #define __HAL_RCC_ADC12_CONFIG(__ADC12CLKSource__) \
AnnaBridge 126:abea610beb85 3419 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, (uint32_t)(__ADC12CLKSource__))
AnnaBridge 126:abea610beb85 3420
AnnaBridge 126:abea610beb85 3421 /** @brief Macro to get the ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3422 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 3423 * @arg @ref RCC_ADC12PLLCLK_OFF ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
AnnaBridge 126:abea610beb85 3424 * @arg @ref RCC_ADC12PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3425 * @arg @ref RCC_ADC12PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3426 * @arg @ref RCC_ADC12PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3427 * @arg @ref RCC_ADC12PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3428 * @arg @ref RCC_ADC12PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3429 * @arg @ref RCC_ADC12PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3430 * @arg @ref RCC_ADC12PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3431 * @arg @ref RCC_ADC12PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3432 * @arg @ref RCC_ADC12PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3433 * @arg @ref RCC_ADC12PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3434 * @arg @ref RCC_ADC12PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3435 * @arg @ref RCC_ADC12PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 & ADC2 clock
AnnaBridge 126:abea610beb85 3436 */
AnnaBridge 126:abea610beb85 3437 #define __HAL_RCC_GET_ADC12_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE12)))
AnnaBridge 126:abea610beb85 3438 /**
AnnaBridge 126:abea610beb85 3439 * @}
AnnaBridge 126:abea610beb85 3440 */
AnnaBridge 126:abea610beb85 3441
AnnaBridge 126:abea610beb85 3442 /** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
AnnaBridge 126:abea610beb85 3443 * @{
AnnaBridge 126:abea610beb85 3444 */
AnnaBridge 126:abea610beb85 3445 /** @brief Macro to configure the TIM1 clock (TIM1CLK).
AnnaBridge 126:abea610beb85 3446 * @param __TIM1CLKSource__ specifies the TIM1 clock source.
AnnaBridge 126:abea610beb85 3447 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 3448 * @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock
AnnaBridge 126:abea610beb85 3449 * @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock
AnnaBridge 126:abea610beb85 3450 */
AnnaBridge 126:abea610beb85 3451 #define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \
AnnaBridge 126:abea610beb85 3452 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__))
AnnaBridge 126:abea610beb85 3453
AnnaBridge 126:abea610beb85 3454 /** @brief Macro to get the TIM1 clock (TIM1CLK).
AnnaBridge 126:abea610beb85 3455 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 3456 * @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock
AnnaBridge 126:abea610beb85 3457 * @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock
AnnaBridge 126:abea610beb85 3458 */
AnnaBridge 126:abea610beb85 3459 #define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
AnnaBridge 126:abea610beb85 3460 /**
AnnaBridge 126:abea610beb85 3461 * @}
AnnaBridge 126:abea610beb85 3462 */
AnnaBridge 126:abea610beb85 3463 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
AnnaBridge 126:abea610beb85 3464
AnnaBridge 126:abea610beb85 3465 #if defined(STM32F334x8)
AnnaBridge 126:abea610beb85 3466 /** @defgroup RCCEx_HRTIMx_Clock_Config RCC Extended HRTIMx Clock Config
AnnaBridge 126:abea610beb85 3467 * @{
AnnaBridge 126:abea610beb85 3468 */
AnnaBridge 126:abea610beb85 3469 /** @brief Macro to configure the HRTIM1 clock.
AnnaBridge 126:abea610beb85 3470 * @param __HRTIM1CLKSource__ specifies the HRTIM1 clock source.
AnnaBridge 126:abea610beb85 3471 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 3472 * @arg @ref RCC_HRTIM1CLK_HCLK HCLK selected as HRTIM1 clock
AnnaBridge 126:abea610beb85 3473 * @arg @ref RCC_HRTIM1CLK_PLLCLK PLL Clock selected as HRTIM1 clock
AnnaBridge 126:abea610beb85 3474 */
AnnaBridge 126:abea610beb85 3475 #define __HAL_RCC_HRTIM1_CONFIG(__HRTIM1CLKSource__) \
AnnaBridge 126:abea610beb85 3476 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_HRTIM1SW, (uint32_t)(__HRTIM1CLKSource__))
AnnaBridge 126:abea610beb85 3477
AnnaBridge 126:abea610beb85 3478 /** @brief Macro to get the HRTIM1 clock source.
AnnaBridge 126:abea610beb85 3479 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 3480 * @arg @ref RCC_HRTIM1CLK_HCLK HCLK selected as HRTIM1 clock
AnnaBridge 126:abea610beb85 3481 * @arg @ref RCC_HRTIM1CLK_PLLCLK PLL Clock selected as HRTIM1 clock
AnnaBridge 126:abea610beb85 3482 */
AnnaBridge 126:abea610beb85 3483 #define __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_HRTIM1SW)))
AnnaBridge 126:abea610beb85 3484 /**
AnnaBridge 126:abea610beb85 3485 * @}
AnnaBridge 126:abea610beb85 3486 */
AnnaBridge 126:abea610beb85 3487 #endif /* STM32F334x8 */
AnnaBridge 126:abea610beb85 3488
AnnaBridge 126:abea610beb85 3489 #if defined(STM32F373xC) || defined(STM32F378xx)
AnnaBridge 126:abea610beb85 3490 /** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
AnnaBridge 126:abea610beb85 3491 * @{
AnnaBridge 126:abea610beb85 3492 */
AnnaBridge 126:abea610beb85 3493 /** @brief Macro to configure the I2C2 clock (I2C2CLK).
AnnaBridge 126:abea610beb85 3494 * @param __I2C2CLKSource__ specifies the I2C2 clock source.
AnnaBridge 126:abea610beb85 3495 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 3496 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
AnnaBridge 126:abea610beb85 3497 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
AnnaBridge 126:abea610beb85 3498 */
AnnaBridge 126:abea610beb85 3499 #define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
AnnaBridge 126:abea610beb85 3500 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
AnnaBridge 126:abea610beb85 3501
AnnaBridge 126:abea610beb85 3502 /** @brief Macro to get the I2C2 clock source.
AnnaBridge 126:abea610beb85 3503 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 3504 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
AnnaBridge 126:abea610beb85 3505 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
AnnaBridge 126:abea610beb85 3506 */
AnnaBridge 126:abea610beb85 3507 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
AnnaBridge 126:abea610beb85 3508 /**
AnnaBridge 126:abea610beb85 3509 * @}
AnnaBridge 126:abea610beb85 3510 */
AnnaBridge 126:abea610beb85 3511
AnnaBridge 126:abea610beb85 3512 /** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
AnnaBridge 126:abea610beb85 3513 * @{
AnnaBridge 126:abea610beb85 3514 */
AnnaBridge 126:abea610beb85 3515 /** @brief Macro to configure the ADC1 clock (ADC1CLK).
AnnaBridge 126:abea610beb85 3516 * @param __ADC1CLKSource__ specifies the ADC1 clock source.
AnnaBridge 126:abea610beb85 3517 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 3518 * @arg @ref RCC_ADC1PCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC1 clock
AnnaBridge 126:abea610beb85 3519 * @arg @ref RCC_ADC1PCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC1 clock
AnnaBridge 126:abea610beb85 3520 * @arg @ref RCC_ADC1PCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC1 clock
AnnaBridge 126:abea610beb85 3521 * @arg @ref RCC_ADC1PCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC1 clock
AnnaBridge 126:abea610beb85 3522 */
AnnaBridge 126:abea610beb85 3523 #define __HAL_RCC_ADC1_CONFIG(__ADC1CLKSource__) \
AnnaBridge 126:abea610beb85 3524 MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADC1CLKSource__))
AnnaBridge 126:abea610beb85 3525
AnnaBridge 126:abea610beb85 3526 /** @brief Macro to get the ADC1 clock (ADC1CLK).
AnnaBridge 126:abea610beb85 3527 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 3528 * @arg @ref RCC_ADC1PCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC1 clock
AnnaBridge 126:abea610beb85 3529 * @arg @ref RCC_ADC1PCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC1 clock
AnnaBridge 126:abea610beb85 3530 * @arg @ref RCC_ADC1PCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC1 clock
AnnaBridge 126:abea610beb85 3531 * @arg @ref RCC_ADC1PCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC1 clock
AnnaBridge 126:abea610beb85 3532 */
AnnaBridge 126:abea610beb85 3533 #define __HAL_RCC_GET_ADC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE)))
AnnaBridge 126:abea610beb85 3534 /**
AnnaBridge 126:abea610beb85 3535 * @}
AnnaBridge 126:abea610beb85 3536 */
AnnaBridge 126:abea610beb85 3537
AnnaBridge 126:abea610beb85 3538 /** @defgroup RCCEx_SDADCx_Clock_Config RCC Extended SDADCx Clock Config
AnnaBridge 126:abea610beb85 3539 * @{
AnnaBridge 126:abea610beb85 3540 */
AnnaBridge 126:abea610beb85 3541 /** @brief Macro to configure the SDADCx clock (SDADCxCLK).
AnnaBridge 126:abea610beb85 3542 * @param __SDADCPrescaler__ specifies the SDADCx system clock prescaler.
AnnaBridge 126:abea610beb85 3543 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 3544 * @arg @ref RCC_SDADCSYSCLK_DIV1 SYSCLK clock selected as SDADCx clock
AnnaBridge 126:abea610beb85 3545 * @arg @ref RCC_SDADCSYSCLK_DIV2 SYSCLK clock divided by 2 selected as SDADCx clock
AnnaBridge 126:abea610beb85 3546 * @arg @ref RCC_SDADCSYSCLK_DIV4 SYSCLK clock divided by 4 selected as SDADCx clock
AnnaBridge 126:abea610beb85 3547 * @arg @ref RCC_SDADCSYSCLK_DIV6 SYSCLK clock divided by 6 selected as SDADCx clock
AnnaBridge 126:abea610beb85 3548 * @arg @ref RCC_SDADCSYSCLK_DIV8 SYSCLK clock divided by 8 selected as SDADCx clock
AnnaBridge 126:abea610beb85 3549 * @arg @ref RCC_SDADCSYSCLK_DIV10 SYSCLK clock divided by 10 selected as SDADCx clock
AnnaBridge 126:abea610beb85 3550 * @arg @ref RCC_SDADCSYSCLK_DIV12 SYSCLK clock divided by 12 selected as SDADCx clock
AnnaBridge 126:abea610beb85 3551 * @arg @ref RCC_SDADCSYSCLK_DIV14 SYSCLK clock divided by 14 selected as SDADCx clock
AnnaBridge 126:abea610beb85 3552 * @arg @ref RCC_SDADCSYSCLK_DIV16 SYSCLK clock divided by 16 selected as SDADCx clock
AnnaBridge 126:abea610beb85 3553 * @arg @ref RCC_SDADCSYSCLK_DIV20 SYSCLK clock divided by 20 selected as SDADCx clock
AnnaBridge 126:abea610beb85 3554 * @arg @ref RCC_SDADCSYSCLK_DIV24 SYSCLK clock divided by 24 selected as SDADCx clock
AnnaBridge 126:abea610beb85 3555 * @arg @ref RCC_SDADCSYSCLK_DIV28 SYSCLK clock divided by 28 selected as SDADCx clock
AnnaBridge 126:abea610beb85 3556 * @arg @ref RCC_SDADCSYSCLK_DIV32 SYSCLK clock divided by 32 selected as SDADCx clock
AnnaBridge 126:abea610beb85 3557 * @arg @ref RCC_SDADCSYSCLK_DIV36 SYSCLK clock divided by 36 selected as SDADCx clock
AnnaBridge 126:abea610beb85 3558 * @arg @ref RCC_SDADCSYSCLK_DIV40 SYSCLK clock divided by 40 selected as SDADCx clock
AnnaBridge 126:abea610beb85 3559 * @arg @ref RCC_SDADCSYSCLK_DIV44 SYSCLK clock divided by 44 selected as SDADCx clock
AnnaBridge 126:abea610beb85 3560 * @arg @ref RCC_SDADCSYSCLK_DIV48 SYSCLK clock divided by 48 selected as SDADCx clock
AnnaBridge 126:abea610beb85 3561 */
AnnaBridge 126:abea610beb85 3562 #define __HAL_RCC_SDADC_CONFIG(__SDADCPrescaler__) \
<> 135:176b8275d35d 3563 MODIFY_REG(RCC->CFGR, RCC_CFGR_SDPRE, (uint32_t)(__SDADCPrescaler__))
AnnaBridge 126:abea610beb85 3564
AnnaBridge 126:abea610beb85 3565 /** @brief Macro to get the SDADCx clock prescaler.
AnnaBridge 126:abea610beb85 3566 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 3567 * @arg @ref RCC_SDADCSYSCLK_DIV1 SYSCLK clock selected as SDADCx clock
AnnaBridge 126:abea610beb85 3568 * @arg @ref RCC_SDADCSYSCLK_DIV2 SYSCLK clock divided by 2 selected as SDADCx clock
AnnaBridge 126:abea610beb85 3569 * @arg @ref RCC_SDADCSYSCLK_DIV4 SYSCLK clock divided by 4 selected as SDADCx clock
AnnaBridge 126:abea610beb85 3570 * @arg @ref RCC_SDADCSYSCLK_DIV6 SYSCLK clock divided by 6 selected as SDADCx clock
AnnaBridge 126:abea610beb85 3571 * @arg @ref RCC_SDADCSYSCLK_DIV8 SYSCLK clock divided by 8 selected as SDADCx clock
AnnaBridge 126:abea610beb85 3572 * @arg @ref RCC_SDADCSYSCLK_DIV10 SYSCLK clock divided by 10 selected as SDADCx clock
AnnaBridge 126:abea610beb85 3573 * @arg @ref RCC_SDADCSYSCLK_DIV12 SYSCLK clock divided by 12 selected as SDADCx clock
AnnaBridge 126:abea610beb85 3574 * @arg @ref RCC_SDADCSYSCLK_DIV14 SYSCLK clock divided by 14 selected as SDADCx clock
AnnaBridge 126:abea610beb85 3575 * @arg @ref RCC_SDADCSYSCLK_DIV16 SYSCLK clock divided by 16 selected as SDADCx clock
AnnaBridge 126:abea610beb85 3576 * @arg @ref RCC_SDADCSYSCLK_DIV20 SYSCLK clock divided by 20 selected as SDADCx clock
AnnaBridge 126:abea610beb85 3577 * @arg @ref RCC_SDADCSYSCLK_DIV24 SYSCLK clock divided by 24 selected as SDADCx clock
AnnaBridge 126:abea610beb85 3578 * @arg @ref RCC_SDADCSYSCLK_DIV28 SYSCLK clock divided by 28 selected as SDADCx clock
AnnaBridge 126:abea610beb85 3579 * @arg @ref RCC_SDADCSYSCLK_DIV32 SYSCLK clock divided by 32 selected as SDADCx clock
AnnaBridge 126:abea610beb85 3580 * @arg @ref RCC_SDADCSYSCLK_DIV36 SYSCLK clock divided by 36 selected as SDADCx clock
AnnaBridge 126:abea610beb85 3581 * @arg @ref RCC_SDADCSYSCLK_DIV40 SYSCLK clock divided by 40 selected as SDADCx clock
AnnaBridge 126:abea610beb85 3582 * @arg @ref RCC_SDADCSYSCLK_DIV44 SYSCLK clock divided by 44 selected as SDADCx clock
AnnaBridge 126:abea610beb85 3583 * @arg @ref RCC_SDADCSYSCLK_DIV48 SYSCLK clock divided by 48 selected as SDADCx clock
AnnaBridge 126:abea610beb85 3584 */
<> 135:176b8275d35d 3585 #define __HAL_RCC_GET_SDADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SDPRE)))
AnnaBridge 126:abea610beb85 3586 /**
AnnaBridge 126:abea610beb85 3587 * @}
AnnaBridge 126:abea610beb85 3588 */
AnnaBridge 126:abea610beb85 3589
AnnaBridge 126:abea610beb85 3590 /** @defgroup RCCEx_CECx_Clock_Config RCC Extended CECx Clock Config
AnnaBridge 126:abea610beb85 3591 * @{
AnnaBridge 126:abea610beb85 3592 */
AnnaBridge 126:abea610beb85 3593 /** @brief Macro to configure the CEC clock.
AnnaBridge 126:abea610beb85 3594 * @param __CECCLKSource__ specifies the CEC clock source.
AnnaBridge 126:abea610beb85 3595 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 3596 * @arg @ref RCC_CECCLKSOURCE_HSI HSI selected as CEC clock
AnnaBridge 126:abea610beb85 3597 * @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock
AnnaBridge 126:abea610beb85 3598 */
AnnaBridge 126:abea610beb85 3599 #define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
AnnaBridge 126:abea610beb85 3600 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSource__))
AnnaBridge 126:abea610beb85 3601
AnnaBridge 126:abea610beb85 3602 /** @brief Macro to get the HDMI CEC clock source.
AnnaBridge 126:abea610beb85 3603 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 3604 * @arg @ref RCC_CECCLKSOURCE_HSI HSI selected as CEC clock
AnnaBridge 126:abea610beb85 3605 * @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock
AnnaBridge 126:abea610beb85 3606 */
AnnaBridge 126:abea610beb85 3607 #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW)))
AnnaBridge 126:abea610beb85 3608 /**
AnnaBridge 126:abea610beb85 3609 * @}
AnnaBridge 126:abea610beb85 3610 */
AnnaBridge 126:abea610beb85 3611
AnnaBridge 126:abea610beb85 3612 #endif /* STM32F373xC || STM32F378xx */
AnnaBridge 126:abea610beb85 3613
AnnaBridge 126:abea610beb85 3614 #if defined(STM32F302xE) || defined(STM32F303xE)\
AnnaBridge 126:abea610beb85 3615 || defined(STM32F302xC) || defined(STM32F303xC)\
AnnaBridge 126:abea610beb85 3616 || defined(STM32F302x8) \
AnnaBridge 126:abea610beb85 3617 || defined(STM32F373xC)
AnnaBridge 126:abea610beb85 3618
AnnaBridge 126:abea610beb85 3619 /** @defgroup RCCEx_USBx_Clock_Config RCC Extended USBx Clock Config
AnnaBridge 126:abea610beb85 3620 * @{
AnnaBridge 126:abea610beb85 3621 */
AnnaBridge 126:abea610beb85 3622 /** @brief Macro to configure the USB clock (USBCLK).
AnnaBridge 126:abea610beb85 3623 * @param __USBCLKSource__ specifies the USB clock source.
AnnaBridge 126:abea610beb85 3624 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 3625 * @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock divided by 1 selected as USB clock
AnnaBridge 126:abea610beb85 3626 * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL Clock divided by 1.5 selected as USB clock
AnnaBridge 126:abea610beb85 3627 */
AnnaBridge 126:abea610beb85 3628 #define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
AnnaBridge 126:abea610beb85 3629 MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSource__))
AnnaBridge 126:abea610beb85 3630
AnnaBridge 126:abea610beb85 3631 /** @brief Macro to get the USB clock source.
AnnaBridge 126:abea610beb85 3632 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 3633 * @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock divided by 1 selected as USB clock
AnnaBridge 126:abea610beb85 3634 * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL Clock divided by 1.5 selected as USB clock
AnnaBridge 126:abea610beb85 3635 */
AnnaBridge 126:abea610beb85 3636 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE)))
AnnaBridge 126:abea610beb85 3637 /**
AnnaBridge 126:abea610beb85 3638 * @}
AnnaBridge 126:abea610beb85 3639 */
AnnaBridge 126:abea610beb85 3640
AnnaBridge 126:abea610beb85 3641 #endif /* STM32F302xE || STM32F303xE || */
AnnaBridge 126:abea610beb85 3642 /* STM32F302xC || STM32F303xC || */
AnnaBridge 126:abea610beb85 3643 /* STM32F302x8 || */
AnnaBridge 126:abea610beb85 3644 /* STM32F373xC */
AnnaBridge 126:abea610beb85 3645
AnnaBridge 126:abea610beb85 3646 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
AnnaBridge 126:abea610beb85 3647
AnnaBridge 126:abea610beb85 3648 /** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
AnnaBridge 126:abea610beb85 3649 * @{
AnnaBridge 126:abea610beb85 3650 */
AnnaBridge 126:abea610beb85 3651 /** @brief Macro to configure the I2C3 clock (I2C3CLK).
AnnaBridge 126:abea610beb85 3652 * @param __I2C3CLKSource__ specifies the I2C3 clock source.
AnnaBridge 126:abea610beb85 3653 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 3654 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
AnnaBridge 126:abea610beb85 3655 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
AnnaBridge 126:abea610beb85 3656 */
AnnaBridge 126:abea610beb85 3657 #define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \
AnnaBridge 126:abea610beb85 3658 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C3SW, (uint32_t)(__I2C3CLKSource__))
AnnaBridge 126:abea610beb85 3659
AnnaBridge 126:abea610beb85 3660 /** @brief Macro to get the I2C3 clock source.
AnnaBridge 126:abea610beb85 3661 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 3662 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
AnnaBridge 126:abea610beb85 3663 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
AnnaBridge 126:abea610beb85 3664 */
AnnaBridge 126:abea610beb85 3665 #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C3SW)))
AnnaBridge 126:abea610beb85 3666 /**
AnnaBridge 126:abea610beb85 3667 * @}
AnnaBridge 126:abea610beb85 3668 */
AnnaBridge 126:abea610beb85 3669
AnnaBridge 126:abea610beb85 3670 /** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
AnnaBridge 126:abea610beb85 3671 * @{
AnnaBridge 126:abea610beb85 3672 */
AnnaBridge 126:abea610beb85 3673 /** @brief Macro to configure the TIM2 clock (TIM2CLK).
AnnaBridge 126:abea610beb85 3674 * @param __TIM2CLKSource__ specifies the TIM2 clock source.
AnnaBridge 126:abea610beb85 3675 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 3676 * @arg @ref RCC_TIM2CLK_HCLK HCLK selected as TIM2 clock
AnnaBridge 126:abea610beb85 3677 * @arg @ref RCC_TIM2CLK_PLL PLL Clock selected as TIM2 clock
AnnaBridge 126:abea610beb85 3678 */
AnnaBridge 126:abea610beb85 3679 #define __HAL_RCC_TIM2_CONFIG(__TIM2CLKSource__) \
AnnaBridge 126:abea610beb85 3680 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM2SW, (uint32_t)(__TIM2CLKSource__))
AnnaBridge 126:abea610beb85 3681
AnnaBridge 126:abea610beb85 3682 /** @brief Macro to get the TIM2 clock (TIM2CLK).
AnnaBridge 126:abea610beb85 3683 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 3684 * @arg @ref RCC_TIM2CLK_HCLK HCLK selected as TIM2 clock
AnnaBridge 126:abea610beb85 3685 * @arg @ref RCC_TIM2CLK_PLL PLL Clock selected as TIM2 clock
AnnaBridge 126:abea610beb85 3686 */
AnnaBridge 126:abea610beb85 3687 #define __HAL_RCC_GET_TIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM2SW)))
AnnaBridge 126:abea610beb85 3688
AnnaBridge 126:abea610beb85 3689 /** @brief Macro to configure the TIM3 & TIM4 clock (TIM34CLK).
AnnaBridge 126:abea610beb85 3690 * @param __TIM34CLKSource__ specifies the TIM3 & TIM4 clock source.
AnnaBridge 126:abea610beb85 3691 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 3692 * @arg @ref RCC_TIM34CLK_HCLK HCLK selected as TIM3 & TIM4 clock
AnnaBridge 126:abea610beb85 3693 * @arg @ref RCC_TIM34CLK_PLL PLL Clock selected as TIM3 & TIM4 clock
AnnaBridge 126:abea610beb85 3694 */
AnnaBridge 126:abea610beb85 3695 #define __HAL_RCC_TIM34_CONFIG(__TIM34CLKSource__) \
AnnaBridge 126:abea610beb85 3696 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM34SW, (uint32_t)(__TIM34CLKSource__))
AnnaBridge 126:abea610beb85 3697
AnnaBridge 126:abea610beb85 3698 /** @brief Macro to get the TIM3 & TIM4 clock (TIM34CLK).
AnnaBridge 126:abea610beb85 3699 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 3700 * @arg @ref RCC_TIM34CLK_HCLK HCLK selected as TIM3 & TIM4 clock
AnnaBridge 126:abea610beb85 3701 * @arg @ref RCC_TIM34CLK_PLL PLL Clock selected as TIM3 & TIM4 clock
AnnaBridge 126:abea610beb85 3702 */
AnnaBridge 126:abea610beb85 3703 #define __HAL_RCC_GET_TIM34_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM34SW)))
AnnaBridge 126:abea610beb85 3704
AnnaBridge 126:abea610beb85 3705 /** @brief Macro to configure the TIM15 clock (TIM15CLK).
AnnaBridge 126:abea610beb85 3706 * @param __TIM15CLKSource__ specifies the TIM15 clock source.
AnnaBridge 126:abea610beb85 3707 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 3708 * @arg @ref RCC_TIM15CLK_HCLK HCLK selected as TIM15 clock
AnnaBridge 126:abea610beb85 3709 * @arg @ref RCC_TIM15CLK_PLL PLL Clock selected as TIM15 clock
AnnaBridge 126:abea610beb85 3710 */
AnnaBridge 126:abea610beb85 3711 #define __HAL_RCC_TIM15_CONFIG(__TIM15CLKSource__) \
AnnaBridge 126:abea610beb85 3712 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM15SW, (uint32_t)(__TIM15CLKSource__))
AnnaBridge 126:abea610beb85 3713
AnnaBridge 126:abea610beb85 3714 /** @brief Macro to get the TIM15 clock (TIM15CLK).
AnnaBridge 126:abea610beb85 3715 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 3716 * @arg @ref RCC_TIM15CLK_HCLK HCLK selected as TIM15 clock
AnnaBridge 126:abea610beb85 3717 * @arg @ref RCC_TIM15CLK_PLL PLL Clock selected as TIM15 clock
AnnaBridge 126:abea610beb85 3718 */
AnnaBridge 126:abea610beb85 3719 #define __HAL_RCC_GET_TIM15_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM15SW)))
AnnaBridge 126:abea610beb85 3720
AnnaBridge 126:abea610beb85 3721 /** @brief Macro to configure the TIM16 clock (TIM16CLK).
AnnaBridge 126:abea610beb85 3722 * @param __TIM16CLKSource__ specifies the TIM16 clock source.
AnnaBridge 126:abea610beb85 3723 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 3724 * @arg @ref RCC_TIM16CLK_HCLK HCLK selected as TIM16 clock
AnnaBridge 126:abea610beb85 3725 * @arg @ref RCC_TIM16CLK_PLL PLL Clock selected as TIM16 clock
AnnaBridge 126:abea610beb85 3726 */
AnnaBridge 126:abea610beb85 3727 #define __HAL_RCC_TIM16_CONFIG(__TIM16CLKSource__) \
AnnaBridge 126:abea610beb85 3728 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM16SW, (uint32_t)(__TIM16CLKSource__))
AnnaBridge 126:abea610beb85 3729
AnnaBridge 126:abea610beb85 3730 /** @brief Macro to get the TIM16 clock (TIM16CLK).
AnnaBridge 126:abea610beb85 3731 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 3732 * @arg @ref RCC_TIM16CLK_HCLK HCLK selected as TIM16 clock
AnnaBridge 126:abea610beb85 3733 * @arg @ref RCC_TIM16CLK_PLL PLL Clock selected as TIM16 clock
AnnaBridge 126:abea610beb85 3734 */
AnnaBridge 126:abea610beb85 3735 #define __HAL_RCC_GET_TIM16_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM16SW)))
AnnaBridge 126:abea610beb85 3736
AnnaBridge 126:abea610beb85 3737 /** @brief Macro to configure the TIM17 clock (TIM17CLK).
AnnaBridge 126:abea610beb85 3738 * @param __TIM17CLKSource__ specifies the TIM17 clock source.
AnnaBridge 126:abea610beb85 3739 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 3740 * @arg @ref RCC_TIM17CLK_HCLK HCLK selected as TIM17 clock
AnnaBridge 126:abea610beb85 3741 * @arg @ref RCC_TIM17CLK_PLL PLL Clock selected as TIM17 clock
AnnaBridge 126:abea610beb85 3742 */
AnnaBridge 126:abea610beb85 3743 #define __HAL_RCC_TIM17_CONFIG(__TIM17CLKSource__) \
AnnaBridge 126:abea610beb85 3744 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM17SW, (uint32_t)(__TIM17CLKSource__))
AnnaBridge 126:abea610beb85 3745
AnnaBridge 126:abea610beb85 3746 /** @brief Macro to get the TIM17 clock (TIM17CLK).
AnnaBridge 126:abea610beb85 3747 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 3748 * @arg @ref RCC_TIM17CLK_HCLK HCLK selected as TIM17 clock
AnnaBridge 126:abea610beb85 3749 * @arg @ref RCC_TIM17CLK_PLL PLL Clock selected as TIM17 clock
AnnaBridge 126:abea610beb85 3750 */
AnnaBridge 126:abea610beb85 3751 #define __HAL_RCC_GET_TIM17_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM17SW)))
AnnaBridge 126:abea610beb85 3752
AnnaBridge 126:abea610beb85 3753 /**
AnnaBridge 126:abea610beb85 3754 * @}
AnnaBridge 126:abea610beb85 3755 */
AnnaBridge 126:abea610beb85 3756
AnnaBridge 126:abea610beb85 3757 #endif /* STM32f302xE || STM32f303xE || STM32F398xx */
AnnaBridge 126:abea610beb85 3758
AnnaBridge 126:abea610beb85 3759 #if defined(STM32F303xE) || defined(STM32F398xx)
AnnaBridge 126:abea610beb85 3760 /** @addtogroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
AnnaBridge 126:abea610beb85 3761 * @{
AnnaBridge 126:abea610beb85 3762 */
AnnaBridge 126:abea610beb85 3763 /** @brief Macro to configure the TIM20 clock (TIM20CLK).
AnnaBridge 126:abea610beb85 3764 * @param __TIM20CLKSource__ specifies the TIM20 clock source.
AnnaBridge 126:abea610beb85 3765 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 3766 * @arg @ref RCC_TIM20CLK_HCLK HCLK selected as TIM20 clock
AnnaBridge 126:abea610beb85 3767 * @arg @ref RCC_TIM20CLK_PLL PLL Clock selected as TIM20 clock
AnnaBridge 126:abea610beb85 3768 */
AnnaBridge 126:abea610beb85 3769 #define __HAL_RCC_TIM20_CONFIG(__TIM20CLKSource__) \
AnnaBridge 126:abea610beb85 3770 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM20SW, (uint32_t)(__TIM20CLKSource__))
AnnaBridge 126:abea610beb85 3771
AnnaBridge 126:abea610beb85 3772 /** @brief Macro to get the TIM20 clock (TIM20CLK).
AnnaBridge 126:abea610beb85 3773 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 3774 * @arg @ref RCC_TIM20CLK_HCLK HCLK selected as TIM20 clock
AnnaBridge 126:abea610beb85 3775 * @arg @ref RCC_TIM20CLK_PLL PLL Clock selected as TIM20 clock
AnnaBridge 126:abea610beb85 3776 */
AnnaBridge 126:abea610beb85 3777 #define __HAL_RCC_GET_TIM20_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM20SW)))
AnnaBridge 126:abea610beb85 3778
AnnaBridge 126:abea610beb85 3779 /**
AnnaBridge 126:abea610beb85 3780 * @}
AnnaBridge 126:abea610beb85 3781 */
AnnaBridge 126:abea610beb85 3782 #endif /* STM32f303xE || STM32F398xx */
AnnaBridge 126:abea610beb85 3783
AnnaBridge 126:abea610beb85 3784 /** @defgroup RCCEx_LSE_Configuration LSE Drive Configuration
AnnaBridge 126:abea610beb85 3785 * @{
AnnaBridge 126:abea610beb85 3786 */
AnnaBridge 126:abea610beb85 3787
AnnaBridge 126:abea610beb85 3788 /**
AnnaBridge 126:abea610beb85 3789 * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability.
AnnaBridge 126:abea610beb85 3790 * @param __RCC_LSEDRIVE__ specifies the new state of the LSE drive capability.
AnnaBridge 126:abea610beb85 3791 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 3792 * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability.
AnnaBridge 126:abea610beb85 3793 * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability.
AnnaBridge 126:abea610beb85 3794 * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability.
AnnaBridge 126:abea610beb85 3795 * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability.
AnnaBridge 126:abea610beb85 3796 * @retval None
AnnaBridge 126:abea610beb85 3797 */
AnnaBridge 126:abea610beb85 3798 #define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) (MODIFY_REG(RCC->BDCR,\
AnnaBridge 126:abea610beb85 3799 RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) ))
AnnaBridge 126:abea610beb85 3800
AnnaBridge 126:abea610beb85 3801 /**
AnnaBridge 126:abea610beb85 3802 * @}
AnnaBridge 126:abea610beb85 3803 */
AnnaBridge 126:abea610beb85 3804
AnnaBridge 126:abea610beb85 3805 /**
AnnaBridge 126:abea610beb85 3806 * @}
AnnaBridge 126:abea610beb85 3807 */
AnnaBridge 126:abea610beb85 3808
AnnaBridge 126:abea610beb85 3809 /* Exported functions --------------------------------------------------------*/
AnnaBridge 126:abea610beb85 3810 /** @addtogroup RCCEx_Exported_Functions
AnnaBridge 126:abea610beb85 3811 * @{
AnnaBridge 126:abea610beb85 3812 */
AnnaBridge 126:abea610beb85 3813
AnnaBridge 126:abea610beb85 3814 /** @addtogroup RCCEx_Exported_Functions_Group1
AnnaBridge 126:abea610beb85 3815 * @{
AnnaBridge 126:abea610beb85 3816 */
AnnaBridge 126:abea610beb85 3817
AnnaBridge 126:abea610beb85 3818 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
AnnaBridge 126:abea610beb85 3819 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
AnnaBridge 126:abea610beb85 3820 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
AnnaBridge 126:abea610beb85 3821
AnnaBridge 126:abea610beb85 3822 /**
AnnaBridge 126:abea610beb85 3823 * @}
AnnaBridge 126:abea610beb85 3824 */
AnnaBridge 126:abea610beb85 3825
AnnaBridge 126:abea610beb85 3826 /**
AnnaBridge 126:abea610beb85 3827 * @}
AnnaBridge 126:abea610beb85 3828 */
AnnaBridge 126:abea610beb85 3829
AnnaBridge 126:abea610beb85 3830 /**
AnnaBridge 126:abea610beb85 3831 * @}
AnnaBridge 126:abea610beb85 3832 */
AnnaBridge 126:abea610beb85 3833
AnnaBridge 126:abea610beb85 3834 /**
AnnaBridge 126:abea610beb85 3835 * @}
AnnaBridge 126:abea610beb85 3836 */
AnnaBridge 126:abea610beb85 3837
AnnaBridge 126:abea610beb85 3838 #ifdef __cplusplus
AnnaBridge 126:abea610beb85 3839 }
AnnaBridge 126:abea610beb85 3840 #endif
AnnaBridge 126:abea610beb85 3841
AnnaBridge 126:abea610beb85 3842 #endif /* __STM32F3xx_HAL_RCC_EX_H */
AnnaBridge 126:abea610beb85 3843
AnnaBridge 126:abea610beb85 3844 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
AnnaBridge 126:abea610beb85 3845