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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_MOTE_L152RC/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_pwr.h@136:ef9c61f8c49f, 2017-02-14 (annotated)

Committer:
Kojto
Date:
Tue Feb 14 11:24:20 2017 +0000
Revision:
136:ef9c61f8c49f
Parent:
128:9bcdf88f62b0
Child:
165:d1b4690b3f8b
Release 136 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3432: Target STM USBHOST support https://github.com/ARMmbed/mbed-os/pull/3432

3181: NUCLEO_F207ZG extending PeripheralPins.c: all available alternate functions can be used now https://github.com/ARMmbed/mbed-os/pull/3181

3626: NUCLEO_F412ZG : Add USB Device +Host https://github.com/ARMmbed/mbed-os/pull/3626

3628: Fix warnings https://github.com/ARMmbed/mbed-os/pull/3628

3629: STM32: L0 LL layer https://github.com/ARMmbed/mbed-os/pull/3629

3632: IDE Export support for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3632

3642: Missing IRQ pin fix for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3642

3664: Fix ncs36510 sleep definitions https://github.com/ARMmbed/mbed-os/pull/3664

3655: [STM32F4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3655

3657: [STM32L4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3657

3658: [STM32F3] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3658

3685: STM32: I2C: reset state machine https://github.com/ARMmbed/mbed-os/pull/3685

3692: uVisor: Standardize available legacy heap and stack https://github.com/ARMmbed/mbed-os/pull/3692

3621: Fix for #2884, LPC824: export to LPCXpresso, target running with wron https://github.com/ARMmbed/mbed-os/pull/3621

3649: [STM32F7] Modify folder structure  https://github.com/ARMmbed/mbed-os/pull/3649

3695: Enforce device_name is valid in targets.json https://github.com/ARMmbed/mbed-os/pull/3695

3723: NCS36510: spi_format function bug fix https://github.com/ARMmbed/mbed-os/pull/3723

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 /**
<> 128:9bcdf88f62b0 2 ******************************************************************************
<> 128:9bcdf88f62b0 3 * @file stm32l1xx_ll_pwr.h
<> 128:9bcdf88f62b0 4 * @author MCD Application Team
<> 128:9bcdf88f62b0 5 * @version V1.2.0
<> 128:9bcdf88f62b0 6 * @date 01-July-2016
<> 128:9bcdf88f62b0 7 * @brief Header file of PWR LL module.
<> 128:9bcdf88f62b0 8 ******************************************************************************
<> 128:9bcdf88f62b0 9 * @attention
<> 128:9bcdf88f62b0 10 *
<> 128:9bcdf88f62b0 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 128:9bcdf88f62b0 12 *
<> 128:9bcdf88f62b0 13 * Redistribution and use in source and binary forms, with or without modification,
<> 128:9bcdf88f62b0 14 * are permitted provided that the following conditions are met:
<> 128:9bcdf88f62b0 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 128:9bcdf88f62b0 16 * this list of conditions and the following disclaimer.
<> 128:9bcdf88f62b0 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 128:9bcdf88f62b0 18 * this list of conditions and the following disclaimer in the documentation
<> 128:9bcdf88f62b0 19 * and/or other materials provided with the distribution.
<> 128:9bcdf88f62b0 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 128:9bcdf88f62b0 21 * may be used to endorse or promote products derived from this software
<> 128:9bcdf88f62b0 22 * without specific prior written permission.
<> 128:9bcdf88f62b0 23 *
<> 128:9bcdf88f62b0 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 128:9bcdf88f62b0 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 128:9bcdf88f62b0 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 128:9bcdf88f62b0 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 128:9bcdf88f62b0 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 128:9bcdf88f62b0 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 128:9bcdf88f62b0 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 128:9bcdf88f62b0 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 128:9bcdf88f62b0 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 128:9bcdf88f62b0 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 128:9bcdf88f62b0 34 *
<> 128:9bcdf88f62b0 35 ******************************************************************************
<> 128:9bcdf88f62b0 36 */
<> 128:9bcdf88f62b0 37
<> 128:9bcdf88f62b0 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 128:9bcdf88f62b0 39 #ifndef __STM32L1xx_LL_PWR_H
<> 128:9bcdf88f62b0 40 #define __STM32L1xx_LL_PWR_H
<> 128:9bcdf88f62b0 41
<> 128:9bcdf88f62b0 42 #ifdef __cplusplus
<> 128:9bcdf88f62b0 43 extern "C" {
<> 128:9bcdf88f62b0 44 #endif
<> 128:9bcdf88f62b0 45
<> 128:9bcdf88f62b0 46 /* Includes ------------------------------------------------------------------*/
<> 128:9bcdf88f62b0 47 #include "stm32l1xx.h"
<> 128:9bcdf88f62b0 48
<> 128:9bcdf88f62b0 49 /** @addtogroup STM32L1xx_LL_Driver
<> 128:9bcdf88f62b0 50 * @{
<> 128:9bcdf88f62b0 51 */
<> 128:9bcdf88f62b0 52
<> 128:9bcdf88f62b0 53 #if defined(PWR)
<> 128:9bcdf88f62b0 54
<> 128:9bcdf88f62b0 55 /** @defgroup PWR_LL PWR
<> 128:9bcdf88f62b0 56 * @{
<> 128:9bcdf88f62b0 57 */
<> 128:9bcdf88f62b0 58
<> 128:9bcdf88f62b0 59 /* Private types -------------------------------------------------------------*/
<> 128:9bcdf88f62b0 60 /* Private variables ---------------------------------------------------------*/
<> 128:9bcdf88f62b0 61
<> 128:9bcdf88f62b0 62 /* Private constants ---------------------------------------------------------*/
<> 128:9bcdf88f62b0 63
<> 128:9bcdf88f62b0 64 /* Private macros ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 65
<> 128:9bcdf88f62b0 66 /* Exported types ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 67 /* Exported constants --------------------------------------------------------*/
<> 128:9bcdf88f62b0 68 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
<> 128:9bcdf88f62b0 69 * @{
<> 128:9bcdf88f62b0 70 */
<> 128:9bcdf88f62b0 71
<> 128:9bcdf88f62b0 72 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
<> 128:9bcdf88f62b0 73 * @brief Flags defines which can be used with LL_PWR_WriteReg function
<> 128:9bcdf88f62b0 74 * @{
<> 128:9bcdf88f62b0 75 */
<> 128:9bcdf88f62b0 76 #define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */
<> 128:9bcdf88f62b0 77 #define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */
<> 128:9bcdf88f62b0 78 /**
<> 128:9bcdf88f62b0 79 * @}
<> 128:9bcdf88f62b0 80 */
<> 128:9bcdf88f62b0 81
<> 128:9bcdf88f62b0 82 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
<> 128:9bcdf88f62b0 83 * @brief Flags defines which can be used with LL_PWR_ReadReg function
<> 128:9bcdf88f62b0 84 * @{
<> 128:9bcdf88f62b0 85 */
<> 128:9bcdf88f62b0 86 #define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */
<> 128:9bcdf88f62b0 87 #define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */
<> 128:9bcdf88f62b0 88 #if defined (PWR_PVD_SUPPORT)
<> 128:9bcdf88f62b0 89 #define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */
<> 128:9bcdf88f62b0 90 #endif
<> 128:9bcdf88f62b0 91 #if defined (PWR_CSR_VREFINTRDYF)
<> 128:9bcdf88f62b0 92 #define LL_PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF /*!< VREFINT ready flag */
<> 128:9bcdf88f62b0 93 #endif
<> 128:9bcdf88f62b0 94 #define LL_PWR_CSR_VOSF PWR_CSR_VOSF /*!< Voltage scaling select flag */
<> 128:9bcdf88f62b0 95 #define LL_PWR_CSR_REGLPF PWR_CSR_REGLPF /*!< Regulator low power flag */
<> 128:9bcdf88f62b0 96 #define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1 /*!< Enable WKUP pin 1 */
<> 128:9bcdf88f62b0 97 #define LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2 /*!< Enable WKUP pin 2 */
<> 128:9bcdf88f62b0 98 #if defined (PWR_CSR_EWUP3)
<> 128:9bcdf88f62b0 99 #define LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3 /*!< Enable WKUP pin 3 */
<> 128:9bcdf88f62b0 100 #endif /* PWR_CSR_EWUP3 */
<> 128:9bcdf88f62b0 101 /**
<> 128:9bcdf88f62b0 102 * @}
<> 128:9bcdf88f62b0 103 */
<> 128:9bcdf88f62b0 104
<> 128:9bcdf88f62b0 105 /** @defgroup PWR_LL_EC_REGU_VOLTAGE Regulator Voltage
<> 128:9bcdf88f62b0 106 * @{
<> 128:9bcdf88f62b0 107 */
<> 128:9bcdf88f62b0 108 #define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR_VOS_0) /*!< 1.8V (range 1) */
<> 128:9bcdf88f62b0 109 #define LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR_VOS_1) /*!< 1.5V (range 2) */
<> 128:9bcdf88f62b0 110 #define LL_PWR_REGU_VOLTAGE_SCALE3 (PWR_CR_VOS_0 | PWR_CR_VOS_1) /*!< 1.2V (range 3) */
<> 128:9bcdf88f62b0 111 /**
<> 128:9bcdf88f62b0 112 * @}
<> 128:9bcdf88f62b0 113 */
<> 128:9bcdf88f62b0 114
<> 128:9bcdf88f62b0 115 /** @defgroup PWR_LL_EC_MODE_PWR Mode Power
<> 128:9bcdf88f62b0 116 * @{
<> 128:9bcdf88f62b0 117 */
<> 128:9bcdf88f62b0 118 #define LL_PWR_MODE_STOP ((uint32_t)0x00000000U) /*!< Enter Stop mode when the CPU enters deepsleep */
<> 128:9bcdf88f62b0 119 #define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */
<> 128:9bcdf88f62b0 120 /**
<> 128:9bcdf88f62b0 121 * @}
<> 128:9bcdf88f62b0 122 */
<> 128:9bcdf88f62b0 123
<> 128:9bcdf88f62b0 124 /** @defgroup PWR_LL_EC_REGU_MODE_LP_MODES Regulator Mode In Low Power Modes
<> 128:9bcdf88f62b0 125 * @{
<> 128:9bcdf88f62b0 126 */
<> 128:9bcdf88f62b0 127 #define LL_PWR_REGU_LPMODES_MAIN ((uint32_t)0x00000000U) /*!< Voltage regulator in main mode during deepsleep/sleep/low-power run mode */
<> 128:9bcdf88f62b0 128 #define LL_PWR_REGU_LPMODES_LOW_POWER (PWR_CR_LPSDSR) /*!< Voltage regulator in low-power mode during deepsleep/sleep/low-power run mode */
<> 128:9bcdf88f62b0 129 /**
<> 128:9bcdf88f62b0 130 * @}
<> 128:9bcdf88f62b0 131 */
<> 128:9bcdf88f62b0 132
<> 128:9bcdf88f62b0 133 #if defined(PWR_CR_LPDS)
<> 128:9bcdf88f62b0 134 /** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode
<> 128:9bcdf88f62b0 135 * @{
<> 128:9bcdf88f62b0 136 */
<> 128:9bcdf88f62b0 137 #define LL_PWR_REGU_DSMODE_MAIN ((uint32_t)0x00000000U) /*!< Voltage regulator in main mode during deepsleep mode */
<> 128:9bcdf88f62b0 138 #define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage regulator in low-power mode during deepsleep mode */
<> 128:9bcdf88f62b0 139 /**
<> 128:9bcdf88f62b0 140 * @}
<> 128:9bcdf88f62b0 141 */
<> 128:9bcdf88f62b0 142 #endif /* PWR_CR_LPDS */
<> 128:9bcdf88f62b0 143
<> 128:9bcdf88f62b0 144 #if defined (PWR_PVD_SUPPORT)
<> 128:9bcdf88f62b0 145 /** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
<> 128:9bcdf88f62b0 146 * @{
<> 128:9bcdf88f62b0 147 */
<> 128:9bcdf88f62b0 148 #define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold detected by PVD 1.9 V */
<> 128:9bcdf88f62b0 149 #define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold detected by PVD 2.1 V */
<> 128:9bcdf88f62b0 150 #define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold detected by PVD 2.3 V */
<> 128:9bcdf88f62b0 151 #define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold detected by PVD 2.5 V */
<> 128:9bcdf88f62b0 152 #define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold detected by PVD 2.7 V */
<> 128:9bcdf88f62b0 153 #define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold detected by PVD 2.9 V */
<> 128:9bcdf88f62b0 154 #define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold detected by PVD 3.1 V */
<> 128:9bcdf88f62b0 155 #define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< External input analog voltage (Compare internally to VREFINT) */
<> 128:9bcdf88f62b0 156 /**
<> 128:9bcdf88f62b0 157 * @}
<> 128:9bcdf88f62b0 158 */
<> 128:9bcdf88f62b0 159 #endif
<> 128:9bcdf88f62b0 160
<> 128:9bcdf88f62b0 161 /** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins
<> 128:9bcdf88f62b0 162 * @{
<> 128:9bcdf88f62b0 163 */
<> 128:9bcdf88f62b0 164 #define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1) /*!< WKUP pin 1 : PA0 */
<> 128:9bcdf88f62b0 165 #define LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2) /*!< WKUP pin 2 : PC13 */
<> 128:9bcdf88f62b0 166 #if defined (PWR_CSR_EWUP3)
<> 128:9bcdf88f62b0 167 #define LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3) /*!< WKUP pin 3 : PE6 or PA2 according to device */
<> 128:9bcdf88f62b0 168 #endif /* PWR_CSR_EWUP3 */
<> 128:9bcdf88f62b0 169 /**
<> 128:9bcdf88f62b0 170 * @}
<> 128:9bcdf88f62b0 171 */
<> 128:9bcdf88f62b0 172
<> 128:9bcdf88f62b0 173 /**
<> 128:9bcdf88f62b0 174 * @}
<> 128:9bcdf88f62b0 175 */
<> 128:9bcdf88f62b0 176
<> 128:9bcdf88f62b0 177
<> 128:9bcdf88f62b0 178 /* Exported macro ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 179 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
<> 128:9bcdf88f62b0 180 * @{
<> 128:9bcdf88f62b0 181 */
<> 128:9bcdf88f62b0 182
<> 128:9bcdf88f62b0 183 /** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
<> 128:9bcdf88f62b0 184 * @{
<> 128:9bcdf88f62b0 185 */
<> 128:9bcdf88f62b0 186
<> 128:9bcdf88f62b0 187 /**
<> 128:9bcdf88f62b0 188 * @brief Write a value in PWR register
<> 128:9bcdf88f62b0 189 * @param __REG__ Register to be written
<> 128:9bcdf88f62b0 190 * @param __VALUE__ Value to be written in the register
<> 128:9bcdf88f62b0 191 * @retval None
<> 128:9bcdf88f62b0 192 */
<> 128:9bcdf88f62b0 193 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
<> 128:9bcdf88f62b0 194
<> 128:9bcdf88f62b0 195 /**
<> 128:9bcdf88f62b0 196 * @brief Read a value in PWR register
<> 128:9bcdf88f62b0 197 * @param __REG__ Register to be read
<> 128:9bcdf88f62b0 198 * @retval Register value
<> 128:9bcdf88f62b0 199 */
<> 128:9bcdf88f62b0 200 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
<> 128:9bcdf88f62b0 201 /**
<> 128:9bcdf88f62b0 202 * @}
<> 128:9bcdf88f62b0 203 */
<> 128:9bcdf88f62b0 204
<> 128:9bcdf88f62b0 205 /**
<> 128:9bcdf88f62b0 206 * @}
<> 128:9bcdf88f62b0 207 */
<> 128:9bcdf88f62b0 208
<> 128:9bcdf88f62b0 209
<> 128:9bcdf88f62b0 210 /* Exported functions --------------------------------------------------------*/
<> 128:9bcdf88f62b0 211 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
<> 128:9bcdf88f62b0 212 * @{
<> 128:9bcdf88f62b0 213 */
<> 128:9bcdf88f62b0 214
<> 128:9bcdf88f62b0 215 /** @defgroup PWR_LL_EF_Configuration Configuration
<> 128:9bcdf88f62b0 216 * @{
<> 128:9bcdf88f62b0 217 */
<> 128:9bcdf88f62b0 218
<> 128:9bcdf88f62b0 219 /**
<> 128:9bcdf88f62b0 220 * @brief Switch the regulator from main mode to low-power mode
<> 128:9bcdf88f62b0 221 * @rmtoll CR LPRUN LL_PWR_EnableLowPowerRunMode
<> 128:9bcdf88f62b0 222 * @note Remind to set the regulator to low power before enabling
<> 128:9bcdf88f62b0 223 * LowPower run mode (bit @ref LL_PWR_REGU_LPMODES_LOW_POWER).
<> 128:9bcdf88f62b0 224 * @retval None
<> 128:9bcdf88f62b0 225 */
<> 128:9bcdf88f62b0 226 __STATIC_INLINE void LL_PWR_EnableLowPowerRunMode(void)
<> 128:9bcdf88f62b0 227 {
<> 128:9bcdf88f62b0 228 SET_BIT(PWR->CR, PWR_CR_LPRUN);
<> 128:9bcdf88f62b0 229 }
<> 128:9bcdf88f62b0 230
<> 128:9bcdf88f62b0 231 /**
<> 128:9bcdf88f62b0 232 * @brief Switch the regulator from low-power mode to main mode
<> 128:9bcdf88f62b0 233 * @rmtoll CR LPRUN LL_PWR_DisableLowPowerRunMode
<> 128:9bcdf88f62b0 234 * @retval None
<> 128:9bcdf88f62b0 235 */
<> 128:9bcdf88f62b0 236 __STATIC_INLINE void LL_PWR_DisableLowPowerRunMode(void)
<> 128:9bcdf88f62b0 237 {
<> 128:9bcdf88f62b0 238 CLEAR_BIT(PWR->CR, PWR_CR_LPRUN);
<> 128:9bcdf88f62b0 239 }
<> 128:9bcdf88f62b0 240
<> 128:9bcdf88f62b0 241 /**
<> 128:9bcdf88f62b0 242 * @brief Check if the regulator is in low-power mode
<> 128:9bcdf88f62b0 243 * @rmtoll CR LPRUN LL_PWR_IsEnabledLowPowerRunMode
<> 128:9bcdf88f62b0 244 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 245 */
<> 128:9bcdf88f62b0 246 __STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void)
<> 128:9bcdf88f62b0 247 {
<> 128:9bcdf88f62b0 248 return (READ_BIT(PWR->CR, PWR_CR_LPRUN) == (PWR_CR_LPRUN));
<> 128:9bcdf88f62b0 249 }
<> 128:9bcdf88f62b0 250
<> 128:9bcdf88f62b0 251 /**
<> 128:9bcdf88f62b0 252 * @brief Set voltage regulator to low-power and switch from
<> 128:9bcdf88f62b0 253 * run main mode to run low-power mode.
<> 128:9bcdf88f62b0 254 * @rmtoll CR LPSDSR LL_PWR_EnterLowPowerRunMode\n
<> 128:9bcdf88f62b0 255 * CR LPRUN LL_PWR_EnterLowPowerRunMode
<> 128:9bcdf88f62b0 256 * @note This "high level" function is introduced to provide functional
<> 128:9bcdf88f62b0 257 * compatibility with other families. Notice that the two registers
<> 128:9bcdf88f62b0 258 * have to be written sequentially, so this function is not atomic.
<> 128:9bcdf88f62b0 259 * To assure atomicity you can call separately the following functions:
<> 128:9bcdf88f62b0 260 * - @ref LL_PWR_SetRegulModeLP(@ref LL_PWR_REGU_LPMODES_LOW_POWER);
<> 128:9bcdf88f62b0 261 * - @ref LL_PWR_EnableLowPowerRunMode();
<> 128:9bcdf88f62b0 262 * @retval None
<> 128:9bcdf88f62b0 263 */
<> 128:9bcdf88f62b0 264 __STATIC_INLINE void LL_PWR_EnterLowPowerRunMode(void)
<> 128:9bcdf88f62b0 265 {
<> 128:9bcdf88f62b0 266 SET_BIT(PWR->CR, PWR_CR_LPSDSR); /* => LL_PWR_SetRegulModeLP(LL_PWR_REGU_LPMODES_LOW_POWER) */
<> 128:9bcdf88f62b0 267 SET_BIT(PWR->CR, PWR_CR_LPRUN); /* => LL_PWR_EnableLowPowerRunMode() */
<> 128:9bcdf88f62b0 268 }
<> 128:9bcdf88f62b0 269
<> 128:9bcdf88f62b0 270 /**
<> 128:9bcdf88f62b0 271 * @brief Set voltage regulator to main and switch from
<> 128:9bcdf88f62b0 272 * run main mode to low-power mode.
<> 128:9bcdf88f62b0 273 * @rmtoll CR LPSDSR LL_PWR_ExitLowPowerRunMode\n
<> 128:9bcdf88f62b0 274 * CR LPRUN LL_PWR_ExitLowPowerRunMode
<> 128:9bcdf88f62b0 275 * @note This "high level" function is introduced to provide functional
<> 128:9bcdf88f62b0 276 * compatibility with other families. Notice that the two registers
<> 128:9bcdf88f62b0 277 * have to be written sequentially, so this function is not atomic.
<> 128:9bcdf88f62b0 278 * To assure atomicity you can call separately the following functions:
<> 128:9bcdf88f62b0 279 * - @ref LL_PWR_DisableLowPowerRunMode();
<> 128:9bcdf88f62b0 280 * - @ref LL_PWR_SetRegulModeLP(@ref LL_PWR_REGU_LPMODES_MAIN);
<> 128:9bcdf88f62b0 281 * @retval None
<> 128:9bcdf88f62b0 282 */
<> 128:9bcdf88f62b0 283 __STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void)
<> 128:9bcdf88f62b0 284 {
<> 128:9bcdf88f62b0 285 CLEAR_BIT(PWR->CR, PWR_CR_LPRUN); /* => LL_PWR_DisableLowPowerRunMode() */
<> 128:9bcdf88f62b0 286 CLEAR_BIT(PWR->CR, PWR_CR_LPSDSR); /* => LL_PWR_SetRegulModeLP(LL_PWR_REGU_LPMODES_MAIN) */
<> 128:9bcdf88f62b0 287 }
<> 128:9bcdf88f62b0 288
<> 128:9bcdf88f62b0 289 /**
<> 128:9bcdf88f62b0 290 * @brief Set the main internal regulator output voltage
<> 128:9bcdf88f62b0 291 * @rmtoll CR VOS LL_PWR_SetRegulVoltageScaling
<> 128:9bcdf88f62b0 292 * @param VoltageScaling This parameter can be one of the following values:
<> 128:9bcdf88f62b0 293 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
<> 128:9bcdf88f62b0 294 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
<> 128:9bcdf88f62b0 295 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
<> 128:9bcdf88f62b0 296 * @retval None
<> 128:9bcdf88f62b0 297 */
<> 128:9bcdf88f62b0 298 __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
<> 128:9bcdf88f62b0 299 {
<> 128:9bcdf88f62b0 300 MODIFY_REG(PWR->CR, PWR_CR_VOS, VoltageScaling);
<> 128:9bcdf88f62b0 301 }
<> 128:9bcdf88f62b0 302
<> 128:9bcdf88f62b0 303 /**
<> 128:9bcdf88f62b0 304 * @brief Get the main internal regulator output voltage
<> 128:9bcdf88f62b0 305 * @rmtoll CR VOS LL_PWR_GetRegulVoltageScaling
<> 128:9bcdf88f62b0 306 * @retval Returned value can be one of the following values:
<> 128:9bcdf88f62b0 307 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
<> 128:9bcdf88f62b0 308 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
<> 128:9bcdf88f62b0 309 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
<> 128:9bcdf88f62b0 310 */
<> 128:9bcdf88f62b0 311 __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
<> 128:9bcdf88f62b0 312 {
<> 128:9bcdf88f62b0 313 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_VOS));
<> 128:9bcdf88f62b0 314 }
<> 128:9bcdf88f62b0 315
<> 128:9bcdf88f62b0 316 /**
<> 128:9bcdf88f62b0 317 * @brief Enable access to the backup domain
<> 128:9bcdf88f62b0 318 * @rmtoll CR DBP LL_PWR_EnableBkUpAccess
<> 128:9bcdf88f62b0 319 * @retval None
<> 128:9bcdf88f62b0 320 */
<> 128:9bcdf88f62b0 321 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
<> 128:9bcdf88f62b0 322 {
<> 128:9bcdf88f62b0 323 SET_BIT(PWR->CR, PWR_CR_DBP);
<> 128:9bcdf88f62b0 324 }
<> 128:9bcdf88f62b0 325
<> 128:9bcdf88f62b0 326 /**
<> 128:9bcdf88f62b0 327 * @brief Disable access to the backup domain
<> 128:9bcdf88f62b0 328 * @rmtoll CR DBP LL_PWR_DisableBkUpAccess
<> 128:9bcdf88f62b0 329 * @retval None
<> 128:9bcdf88f62b0 330 */
<> 128:9bcdf88f62b0 331 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
<> 128:9bcdf88f62b0 332 {
<> 128:9bcdf88f62b0 333 CLEAR_BIT(PWR->CR, PWR_CR_DBP);
<> 128:9bcdf88f62b0 334 }
<> 128:9bcdf88f62b0 335
<> 128:9bcdf88f62b0 336 /**
<> 128:9bcdf88f62b0 337 * @brief Check if the backup domain is enabled
<> 128:9bcdf88f62b0 338 * @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess
<> 128:9bcdf88f62b0 339 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 340 */
<> 128:9bcdf88f62b0 341 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
<> 128:9bcdf88f62b0 342 {
<> 128:9bcdf88f62b0 343 return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP));
<> 128:9bcdf88f62b0 344 }
<> 128:9bcdf88f62b0 345
<> 128:9bcdf88f62b0 346 /**
<> 128:9bcdf88f62b0 347 * @brief Set voltage regulator mode during low power modes
<> 128:9bcdf88f62b0 348 * @rmtoll CR LPSDSR LL_PWR_SetRegulModeLP
<> 128:9bcdf88f62b0 349 * @param RegulMode This parameter can be one of the following values:
<> 128:9bcdf88f62b0 350 * @arg @ref LL_PWR_REGU_LPMODES_MAIN
<> 128:9bcdf88f62b0 351 * @arg @ref LL_PWR_REGU_LPMODES_LOW_POWER
<> 128:9bcdf88f62b0 352 * @retval None
<> 128:9bcdf88f62b0 353 */
<> 128:9bcdf88f62b0 354 __STATIC_INLINE void LL_PWR_SetRegulModeLP(uint32_t RegulMode)
<> 128:9bcdf88f62b0 355 {
<> 128:9bcdf88f62b0 356 MODIFY_REG(PWR->CR, PWR_CR_LPSDSR, RegulMode);
<> 128:9bcdf88f62b0 357 }
<> 128:9bcdf88f62b0 358
<> 128:9bcdf88f62b0 359 /**
<> 128:9bcdf88f62b0 360 * @brief Get voltage regulator mode during low power modes
<> 128:9bcdf88f62b0 361 * @rmtoll CR LPSDSR LL_PWR_GetRegulModeLP
<> 128:9bcdf88f62b0 362 * @retval Returned value can be one of the following values:
<> 128:9bcdf88f62b0 363 * @arg @ref LL_PWR_REGU_LPMODES_MAIN
<> 128:9bcdf88f62b0 364 * @arg @ref LL_PWR_REGU_LPMODES_LOW_POWER
<> 128:9bcdf88f62b0 365 */
<> 128:9bcdf88f62b0 366 __STATIC_INLINE uint32_t LL_PWR_GetRegulModeLP(void)
<> 128:9bcdf88f62b0 367 {
<> 128:9bcdf88f62b0 368 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPSDSR));
<> 128:9bcdf88f62b0 369 }
<> 128:9bcdf88f62b0 370
<> 128:9bcdf88f62b0 371 #if defined(PWR_CR_LPDS)
<> 128:9bcdf88f62b0 372 /**
<> 128:9bcdf88f62b0 373 * @brief Set voltage regulator mode during deep sleep mode
<> 128:9bcdf88f62b0 374 * @rmtoll CR LPDS LL_PWR_SetRegulModeDS
<> 128:9bcdf88f62b0 375 * @param RegulMode This parameter can be one of the following values:
<> 128:9bcdf88f62b0 376 * @arg @ref LL_PWR_REGU_DSMODE_MAIN
<> 128:9bcdf88f62b0 377 * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
<> 128:9bcdf88f62b0 378 * @retval None
<> 128:9bcdf88f62b0 379 */
<> 128:9bcdf88f62b0 380 __STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
<> 128:9bcdf88f62b0 381 {
<> 128:9bcdf88f62b0 382 MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode);
<> 128:9bcdf88f62b0 383 }
<> 128:9bcdf88f62b0 384
<> 128:9bcdf88f62b0 385 /**
<> 128:9bcdf88f62b0 386 * @brief Get voltage regulator mode during deep sleep mode
<> 128:9bcdf88f62b0 387 * @rmtoll CR LPDS LL_PWR_GetRegulModeDS
<> 128:9bcdf88f62b0 388 * @retval Returned value can be one of the following values:
<> 128:9bcdf88f62b0 389 * @arg @ref LL_PWR_REGU_DSMODE_MAIN
<> 128:9bcdf88f62b0 390 * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
<> 128:9bcdf88f62b0 391 */
<> 128:9bcdf88f62b0 392 __STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
<> 128:9bcdf88f62b0 393 {
<> 128:9bcdf88f62b0 394 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS));
<> 128:9bcdf88f62b0 395 }
<> 128:9bcdf88f62b0 396 #endif /* PWR_CR_LPDS */
<> 128:9bcdf88f62b0 397
<> 128:9bcdf88f62b0 398 /**
<> 128:9bcdf88f62b0 399 * @brief Set power down mode when CPU enters deepsleep
<> 128:9bcdf88f62b0 400 * @rmtoll CR PDDS LL_PWR_SetPowerMode
<> 128:9bcdf88f62b0 401 * @param PDMode This parameter can be one of the following values:
<> 128:9bcdf88f62b0 402 * @arg @ref LL_PWR_MODE_STOP
<> 128:9bcdf88f62b0 403 * @arg @ref LL_PWR_MODE_STANDBY
<> 128:9bcdf88f62b0 404 * @note Set the regulator to low power (bit @ref LL_PWR_REGU_LPMODES_LOW_POWER)
<> 128:9bcdf88f62b0 405 * before setting MODE_STOP. If the regulator remains in "main mode",
<> 128:9bcdf88f62b0 406 * it consumes more power without providing any additional feature.
<> 128:9bcdf88f62b0 407 * In MODE_STANDBY the regulator is automatically off.
<> 128:9bcdf88f62b0 408 * @retval None
<> 128:9bcdf88f62b0 409 */
<> 128:9bcdf88f62b0 410 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
<> 128:9bcdf88f62b0 411 {
<> 128:9bcdf88f62b0 412 MODIFY_REG(PWR->CR, PWR_CR_PDDS, PDMode);
<> 128:9bcdf88f62b0 413 }
<> 128:9bcdf88f62b0 414
<> 128:9bcdf88f62b0 415 /**
<> 128:9bcdf88f62b0 416 * @brief Get power down mode when CPU enters deepsleep
<> 128:9bcdf88f62b0 417 * @rmtoll CR PDDS LL_PWR_GetPowerMode
<> 128:9bcdf88f62b0 418 * @retval Returned value can be one of the following values:
<> 128:9bcdf88f62b0 419 * @arg @ref LL_PWR_MODE_STOP
<> 128:9bcdf88f62b0 420 * @arg @ref LL_PWR_MODE_STANDBY
<> 128:9bcdf88f62b0 421 */
<> 128:9bcdf88f62b0 422 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
<> 128:9bcdf88f62b0 423 {
<> 128:9bcdf88f62b0 424 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PDDS));
<> 128:9bcdf88f62b0 425 }
<> 128:9bcdf88f62b0 426
<> 128:9bcdf88f62b0 427 #if defined (PWR_PVD_SUPPORT)
<> 128:9bcdf88f62b0 428 /**
<> 128:9bcdf88f62b0 429 * @brief Configure the voltage threshold detected by the Power Voltage Detector
<> 128:9bcdf88f62b0 430 * @rmtoll CR PLS LL_PWR_SetPVDLevel
<> 128:9bcdf88f62b0 431 * @param PVDLevel This parameter can be one of the following values:
<> 128:9bcdf88f62b0 432 * @arg @ref LL_PWR_PVDLEVEL_0
<> 128:9bcdf88f62b0 433 * @arg @ref LL_PWR_PVDLEVEL_1
<> 128:9bcdf88f62b0 434 * @arg @ref LL_PWR_PVDLEVEL_2
<> 128:9bcdf88f62b0 435 * @arg @ref LL_PWR_PVDLEVEL_3
<> 128:9bcdf88f62b0 436 * @arg @ref LL_PWR_PVDLEVEL_4
<> 128:9bcdf88f62b0 437 * @arg @ref LL_PWR_PVDLEVEL_5
<> 128:9bcdf88f62b0 438 * @arg @ref LL_PWR_PVDLEVEL_6
<> 128:9bcdf88f62b0 439 * @arg @ref LL_PWR_PVDLEVEL_7
<> 128:9bcdf88f62b0 440 * @retval None
<> 128:9bcdf88f62b0 441 */
<> 128:9bcdf88f62b0 442 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
<> 128:9bcdf88f62b0 443 {
<> 128:9bcdf88f62b0 444 MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel);
<> 128:9bcdf88f62b0 445 }
<> 128:9bcdf88f62b0 446
<> 128:9bcdf88f62b0 447 /**
<> 128:9bcdf88f62b0 448 * @brief Get the voltage threshold detection
<> 128:9bcdf88f62b0 449 * @rmtoll CR PLS LL_PWR_GetPVDLevel
<> 128:9bcdf88f62b0 450 * @retval Returned value can be one of the following values:
<> 128:9bcdf88f62b0 451 * @arg @ref LL_PWR_PVDLEVEL_0
<> 128:9bcdf88f62b0 452 * @arg @ref LL_PWR_PVDLEVEL_1
<> 128:9bcdf88f62b0 453 * @arg @ref LL_PWR_PVDLEVEL_2
<> 128:9bcdf88f62b0 454 * @arg @ref LL_PWR_PVDLEVEL_3
<> 128:9bcdf88f62b0 455 * @arg @ref LL_PWR_PVDLEVEL_4
<> 128:9bcdf88f62b0 456 * @arg @ref LL_PWR_PVDLEVEL_5
<> 128:9bcdf88f62b0 457 * @arg @ref LL_PWR_PVDLEVEL_6
<> 128:9bcdf88f62b0 458 * @arg @ref LL_PWR_PVDLEVEL_7
<> 128:9bcdf88f62b0 459 */
<> 128:9bcdf88f62b0 460 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
<> 128:9bcdf88f62b0 461 {
<> 128:9bcdf88f62b0 462 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS));
<> 128:9bcdf88f62b0 463 }
<> 128:9bcdf88f62b0 464
<> 128:9bcdf88f62b0 465 /**
<> 128:9bcdf88f62b0 466 * @brief Enable Power Voltage Detector
<> 128:9bcdf88f62b0 467 * @rmtoll CR PVDE LL_PWR_EnablePVD
<> 128:9bcdf88f62b0 468 * @retval None
<> 128:9bcdf88f62b0 469 */
<> 128:9bcdf88f62b0 470 __STATIC_INLINE void LL_PWR_EnablePVD(void)
<> 128:9bcdf88f62b0 471 {
<> 128:9bcdf88f62b0 472 SET_BIT(PWR->CR, PWR_CR_PVDE);
<> 128:9bcdf88f62b0 473 }
<> 128:9bcdf88f62b0 474
<> 128:9bcdf88f62b0 475 /**
<> 128:9bcdf88f62b0 476 * @brief Disable Power Voltage Detector
<> 128:9bcdf88f62b0 477 * @rmtoll CR PVDE LL_PWR_DisablePVD
<> 128:9bcdf88f62b0 478 * @retval None
<> 128:9bcdf88f62b0 479 */
<> 128:9bcdf88f62b0 480 __STATIC_INLINE void LL_PWR_DisablePVD(void)
<> 128:9bcdf88f62b0 481 {
<> 128:9bcdf88f62b0 482 CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
<> 128:9bcdf88f62b0 483 }
<> 128:9bcdf88f62b0 484
<> 128:9bcdf88f62b0 485 /**
<> 128:9bcdf88f62b0 486 * @brief Check if Power Voltage Detector is enabled
<> 128:9bcdf88f62b0 487 * @rmtoll CR PVDE LL_PWR_IsEnabledPVD
<> 128:9bcdf88f62b0 488 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 489 */
<> 128:9bcdf88f62b0 490 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
<> 128:9bcdf88f62b0 491 {
<> 128:9bcdf88f62b0 492 return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));
<> 128:9bcdf88f62b0 493 }
<> 128:9bcdf88f62b0 494 #endif
<> 128:9bcdf88f62b0 495
<> 128:9bcdf88f62b0 496 /**
<> 128:9bcdf88f62b0 497 * @brief Enable the WakeUp PINx functionality
<> 128:9bcdf88f62b0 498 * @rmtoll CSR EWUP1 LL_PWR_EnableWakeUpPin\n
<> 128:9bcdf88f62b0 499 * CSR EWUP2 LL_PWR_EnableWakeUpPin\n
<> 128:9bcdf88f62b0 500 * CSR EWUP3 LL_PWR_EnableWakeUpPin
<> 128:9bcdf88f62b0 501 * @param WakeUpPin This parameter can be one of the following values:
<> 128:9bcdf88f62b0 502 * @arg @ref LL_PWR_WAKEUP_PIN1
<> 128:9bcdf88f62b0 503 * @arg @ref LL_PWR_WAKEUP_PIN2
<> 128:9bcdf88f62b0 504 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
<> 128:9bcdf88f62b0 505 *
<> 128:9bcdf88f62b0 506 * (*) not available on all devices
<> 128:9bcdf88f62b0 507 * @retval None
<> 128:9bcdf88f62b0 508 */
<> 128:9bcdf88f62b0 509 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
<> 128:9bcdf88f62b0 510 {
<> 128:9bcdf88f62b0 511 SET_BIT(PWR->CSR, WakeUpPin);
<> 128:9bcdf88f62b0 512 }
<> 128:9bcdf88f62b0 513
<> 128:9bcdf88f62b0 514 /**
<> 128:9bcdf88f62b0 515 * @brief Disable the WakeUp PINx functionality
<> 128:9bcdf88f62b0 516 * @rmtoll CSR EWUP1 LL_PWR_DisableWakeUpPin\n
<> 128:9bcdf88f62b0 517 * CSR EWUP2 LL_PWR_DisableWakeUpPin\n
<> 128:9bcdf88f62b0 518 * CSR EWUP3 LL_PWR_DisableWakeUpPin
<> 128:9bcdf88f62b0 519 * @param WakeUpPin This parameter can be one of the following values:
<> 128:9bcdf88f62b0 520 * @arg @ref LL_PWR_WAKEUP_PIN1
<> 128:9bcdf88f62b0 521 * @arg @ref LL_PWR_WAKEUP_PIN2
<> 128:9bcdf88f62b0 522 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
<> 128:9bcdf88f62b0 523 *
<> 128:9bcdf88f62b0 524 * (*) not available on all devices
<> 128:9bcdf88f62b0 525 * @retval None
<> 128:9bcdf88f62b0 526 */
<> 128:9bcdf88f62b0 527 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
<> 128:9bcdf88f62b0 528 {
<> 128:9bcdf88f62b0 529 CLEAR_BIT(PWR->CSR, WakeUpPin);
<> 128:9bcdf88f62b0 530 }
<> 128:9bcdf88f62b0 531
<> 128:9bcdf88f62b0 532 /**
<> 128:9bcdf88f62b0 533 * @brief Check if the WakeUp PINx functionality is enabled
<> 128:9bcdf88f62b0 534 * @rmtoll CSR EWUP1 LL_PWR_IsEnabledWakeUpPin\n
<> 128:9bcdf88f62b0 535 * CSR EWUP2 LL_PWR_IsEnabledWakeUpPin\n
<> 128:9bcdf88f62b0 536 * CSR EWUP3 LL_PWR_IsEnabledWakeUpPin
<> 128:9bcdf88f62b0 537 * @param WakeUpPin This parameter can be one of the following values:
<> 128:9bcdf88f62b0 538 * @arg @ref LL_PWR_WAKEUP_PIN1
<> 128:9bcdf88f62b0 539 * @arg @ref LL_PWR_WAKEUP_PIN2
<> 128:9bcdf88f62b0 540 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
<> 128:9bcdf88f62b0 541 *
<> 128:9bcdf88f62b0 542 * (*) not available on all devices
<> 128:9bcdf88f62b0 543 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 544 */
<> 128:9bcdf88f62b0 545 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
<> 128:9bcdf88f62b0 546 {
<> 128:9bcdf88f62b0 547 return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin));
<> 128:9bcdf88f62b0 548 }
<> 128:9bcdf88f62b0 549
<> 128:9bcdf88f62b0 550 /**
<> 128:9bcdf88f62b0 551 * @brief Enable ultra low-power mode by enabling VREFINT switch off in low-power modes
<> 128:9bcdf88f62b0 552 * @rmtoll CR ULP LL_PWR_EnableUltraLowPower
<> 128:9bcdf88f62b0 553 * @retval None
<> 128:9bcdf88f62b0 554 */
<> 128:9bcdf88f62b0 555 __STATIC_INLINE void LL_PWR_EnableUltraLowPower(void)
<> 128:9bcdf88f62b0 556 {
<> 128:9bcdf88f62b0 557 SET_BIT(PWR->CR, PWR_CR_ULP);
<> 128:9bcdf88f62b0 558 }
<> 128:9bcdf88f62b0 559
<> 128:9bcdf88f62b0 560 /**
<> 128:9bcdf88f62b0 561 * @brief Disable ultra low-power mode by disabling VREFINT switch off in low-power modes
<> 128:9bcdf88f62b0 562 * @rmtoll CR ULP LL_PWR_DisableUltraLowPower
<> 128:9bcdf88f62b0 563 * @retval None
<> 128:9bcdf88f62b0 564 */
<> 128:9bcdf88f62b0 565 __STATIC_INLINE void LL_PWR_DisableUltraLowPower(void)
<> 128:9bcdf88f62b0 566 {
<> 128:9bcdf88f62b0 567 CLEAR_BIT(PWR->CR, PWR_CR_ULP);
<> 128:9bcdf88f62b0 568 }
<> 128:9bcdf88f62b0 569
<> 128:9bcdf88f62b0 570 /**
<> 128:9bcdf88f62b0 571 * @brief Check if ultra low-power mode is enabled by checking if VREFINT switch off in low-power modes is enabled
<> 128:9bcdf88f62b0 572 * @rmtoll CR ULP LL_PWR_IsEnabledUltraLowPower
<> 128:9bcdf88f62b0 573 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 574 */
<> 128:9bcdf88f62b0 575 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUltraLowPower(void)
<> 128:9bcdf88f62b0 576 {
<> 128:9bcdf88f62b0 577 return (READ_BIT(PWR->CR, PWR_CR_ULP) == (PWR_CR_ULP));
<> 128:9bcdf88f62b0 578 }
<> 128:9bcdf88f62b0 579
<> 128:9bcdf88f62b0 580 /**
<> 128:9bcdf88f62b0 581 * @brief Enable fast wakeup by ignoring VREFINT startup time when exiting from low-power mode
<> 128:9bcdf88f62b0 582 * @rmtoll CR FWU LL_PWR_EnableFastWakeUp
<> 128:9bcdf88f62b0 583 * @note Works in conjunction with ultra low power mode.
<> 128:9bcdf88f62b0 584 * @retval None
<> 128:9bcdf88f62b0 585 */
<> 128:9bcdf88f62b0 586 __STATIC_INLINE void LL_PWR_EnableFastWakeUp(void)
<> 128:9bcdf88f62b0 587 {
<> 128:9bcdf88f62b0 588 SET_BIT(PWR->CR, PWR_CR_FWU);
<> 128:9bcdf88f62b0 589 }
<> 128:9bcdf88f62b0 590
<> 128:9bcdf88f62b0 591 /**
<> 128:9bcdf88f62b0 592 * @brief Disable fast wakeup by waiting VREFINT startup time when exiting from low-power mode
<> 128:9bcdf88f62b0 593 * @rmtoll CR FWU LL_PWR_DisableFastWakeUp
<> 128:9bcdf88f62b0 594 * @note Works in conjunction with ultra low power mode.
<> 128:9bcdf88f62b0 595 * @retval None
<> 128:9bcdf88f62b0 596 */
<> 128:9bcdf88f62b0 597 __STATIC_INLINE void LL_PWR_DisableFastWakeUp(void)
<> 128:9bcdf88f62b0 598 {
<> 128:9bcdf88f62b0 599 CLEAR_BIT(PWR->CR, PWR_CR_FWU);
<> 128:9bcdf88f62b0 600 }
<> 128:9bcdf88f62b0 601
<> 128:9bcdf88f62b0 602 /**
<> 128:9bcdf88f62b0 603 * @brief Check if fast wakeup is enabled by checking if VREFINT startup time when exiting from low-power mode is ignored
<> 128:9bcdf88f62b0 604 * @rmtoll CR FWU LL_PWR_IsEnabledFastWakeUp
<> 128:9bcdf88f62b0 605 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 606 */
<> 128:9bcdf88f62b0 607 __STATIC_INLINE uint32_t LL_PWR_IsEnabledFastWakeUp(void)
<> 128:9bcdf88f62b0 608 {
<> 128:9bcdf88f62b0 609 return (READ_BIT(PWR->CR, PWR_CR_FWU) == (PWR_CR_FWU));
<> 128:9bcdf88f62b0 610 }
<> 128:9bcdf88f62b0 611
<> 128:9bcdf88f62b0 612 /**
<> 128:9bcdf88f62b0 613 * @}
<> 128:9bcdf88f62b0 614 */
<> 128:9bcdf88f62b0 615
<> 128:9bcdf88f62b0 616 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
<> 128:9bcdf88f62b0 617 * @{
<> 128:9bcdf88f62b0 618 */
<> 128:9bcdf88f62b0 619
<> 128:9bcdf88f62b0 620 /**
<> 128:9bcdf88f62b0 621 * @brief Get Wake-up Flag
<> 128:9bcdf88f62b0 622 * @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU
<> 128:9bcdf88f62b0 623 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 624 */
<> 128:9bcdf88f62b0 625 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void)
<> 128:9bcdf88f62b0 626 {
<> 128:9bcdf88f62b0 627 return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF));
<> 128:9bcdf88f62b0 628 }
<> 128:9bcdf88f62b0 629
<> 128:9bcdf88f62b0 630 /**
<> 128:9bcdf88f62b0 631 * @brief Get Standby Flag
<> 128:9bcdf88f62b0 632 * @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB
<> 128:9bcdf88f62b0 633 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 634 */
<> 128:9bcdf88f62b0 635 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
<> 128:9bcdf88f62b0 636 {
<> 128:9bcdf88f62b0 637 return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));
<> 128:9bcdf88f62b0 638 }
<> 128:9bcdf88f62b0 639
<> 128:9bcdf88f62b0 640 #if defined (PWR_PVD_SUPPORT)
<> 128:9bcdf88f62b0 641 /**
<> 128:9bcdf88f62b0 642 * @brief Indicate whether VDD voltage is below the selected PVD threshold
<> 128:9bcdf88f62b0 643 * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO
<> 128:9bcdf88f62b0 644 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 645 */
<> 128:9bcdf88f62b0 646 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
<> 128:9bcdf88f62b0 647 {
<> 128:9bcdf88f62b0 648 return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));
<> 128:9bcdf88f62b0 649 }
<> 128:9bcdf88f62b0 650 #endif
<> 128:9bcdf88f62b0 651
<> 128:9bcdf88f62b0 652 #if defined (PWR_CSR_VREFINTRDYF)
<> 128:9bcdf88f62b0 653 /**
<> 128:9bcdf88f62b0 654 * @brief Get Internal Reference VrefInt Flag
<> 128:9bcdf88f62b0 655 * @rmtoll CSR VREFINTRDYF LL_PWR_IsActiveFlag_VREFINTRDY
<> 128:9bcdf88f62b0 656 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 657 */
<> 128:9bcdf88f62b0 658 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VREFINTRDY(void)
<> 128:9bcdf88f62b0 659 {
<> 128:9bcdf88f62b0 660 return (READ_BIT(PWR->CSR, PWR_CSR_VREFINTRDYF) == (PWR_CSR_VREFINTRDYF));
<> 128:9bcdf88f62b0 661 }
<> 128:9bcdf88f62b0 662 #endif
<> 128:9bcdf88f62b0 663
<> 128:9bcdf88f62b0 664 /**
<> 128:9bcdf88f62b0 665 * @brief Indicate whether the regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level
<> 128:9bcdf88f62b0 666 * @rmtoll CSR VOSF LL_PWR_IsActiveFlag_VOSF
<> 128:9bcdf88f62b0 667 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 668 */
<> 128:9bcdf88f62b0 669 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOSF(void)
<> 128:9bcdf88f62b0 670 {
<> 128:9bcdf88f62b0 671 return (READ_BIT(PWR->CSR, PWR_CSR_VOSF) == (PWR_CSR_VOSF));
<> 128:9bcdf88f62b0 672 }
<> 128:9bcdf88f62b0 673
<> 128:9bcdf88f62b0 674 /**
<> 128:9bcdf88f62b0 675 * @brief Indicate whether the regulator is ready in main mode or is in low-power mode
<> 128:9bcdf88f62b0 676 * @rmtoll CSR REGLPF LL_PWR_IsActiveFlag_REGLPF
<> 128:9bcdf88f62b0 677 * @note Take care, return value "0" means the regulator is ready. Return value "1" means the output voltage range is still changing.
<> 128:9bcdf88f62b0 678 * @retval State of bit (1 or 0).
<> 128:9bcdf88f62b0 679 */
<> 128:9bcdf88f62b0 680 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void)
<> 128:9bcdf88f62b0 681 {
<> 128:9bcdf88f62b0 682 return (READ_BIT(PWR->CSR, PWR_CSR_REGLPF) == (PWR_CSR_REGLPF));
<> 128:9bcdf88f62b0 683 }
<> 128:9bcdf88f62b0 684
<> 128:9bcdf88f62b0 685 /**
<> 128:9bcdf88f62b0 686 * @brief Clear Standby Flag
<> 128:9bcdf88f62b0 687 * @rmtoll CR CSBF LL_PWR_ClearFlag_SB
<> 128:9bcdf88f62b0 688 * @retval None
<> 128:9bcdf88f62b0 689 */
<> 128:9bcdf88f62b0 690 __STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
<> 128:9bcdf88f62b0 691 {
<> 128:9bcdf88f62b0 692 SET_BIT(PWR->CR, PWR_CR_CSBF);
<> 128:9bcdf88f62b0 693 }
<> 128:9bcdf88f62b0 694
<> 128:9bcdf88f62b0 695 /**
<> 128:9bcdf88f62b0 696 * @brief Clear Wake-up Flags
<> 128:9bcdf88f62b0 697 * @rmtoll CR CWUF LL_PWR_ClearFlag_WU
<> 128:9bcdf88f62b0 698 * @retval None
<> 128:9bcdf88f62b0 699 */
<> 128:9bcdf88f62b0 700 __STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
<> 128:9bcdf88f62b0 701 {
<> 128:9bcdf88f62b0 702 SET_BIT(PWR->CR, PWR_CR_CWUF);
<> 128:9bcdf88f62b0 703 }
<> 128:9bcdf88f62b0 704
<> 128:9bcdf88f62b0 705
<> 128:9bcdf88f62b0 706 #if defined(USE_FULL_LL_DRIVER)
<> 128:9bcdf88f62b0 707 /** @defgroup PWR_LL_EF_Init De-initialization function
<> 128:9bcdf88f62b0 708 * @{
<> 128:9bcdf88f62b0 709 */
<> 128:9bcdf88f62b0 710 ErrorStatus LL_PWR_DeInit(void);
<> 128:9bcdf88f62b0 711 /**
<> 128:9bcdf88f62b0 712 * @}
<> 128:9bcdf88f62b0 713 */
<> 128:9bcdf88f62b0 714 #endif /* USE_FULL_LL_DRIVER */
<> 128:9bcdf88f62b0 715
<> 128:9bcdf88f62b0 716 /**
<> 128:9bcdf88f62b0 717 * @}
<> 128:9bcdf88f62b0 718 */
<> 128:9bcdf88f62b0 719
<> 128:9bcdf88f62b0 720 /**
<> 128:9bcdf88f62b0 721 * @}
<> 128:9bcdf88f62b0 722 */
<> 128:9bcdf88f62b0 723
<> 128:9bcdf88f62b0 724 /**
<> 128:9bcdf88f62b0 725 * @}
<> 128:9bcdf88f62b0 726 */
<> 128:9bcdf88f62b0 727
<> 128:9bcdf88f62b0 728 #endif /* defined(PWR) */
<> 128:9bcdf88f62b0 729
<> 128:9bcdf88f62b0 730 /**
<> 128:9bcdf88f62b0 731 * @}
<> 128:9bcdf88f62b0 732 */
<> 128:9bcdf88f62b0 733
<> 128:9bcdf88f62b0 734 #ifdef __cplusplus
<> 128:9bcdf88f62b0 735 }
<> 128:9bcdf88f62b0 736 #endif
<> 128:9bcdf88f62b0 737
<> 128:9bcdf88f62b0 738 #endif /* __STM32L1xx_LL_PWR_H */
<> 128:9bcdf88f62b0 739
<> 128:9bcdf88f62b0 740 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/