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TARGET_MOTE_L152RC/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_dma.h@136:ef9c61f8c49f, 2017-02-14 (annotated)

Committer:: Kojto
Date:: Tue Feb 14 11:24:20 2017 +0000
Revision:: 136:ef9c61f8c49f
Parent:: 128:9bcdf88f62b0
Child:: 165:d1b4690b3f8b

Release 136 of the mbed library

Ports for Upcoming Targets

Fixes and Changes

3432: Target STM USBHOST support https://github.com/ARMmbed/mbed-os/pull/3432

3181: NUCLEO_F207ZG extending PeripheralPins.c: all available alternate functions can be used now https://github.com/ARMmbed/mbed-os/pull/3181

3626: NUCLEO_F412ZG : Add USB Device +Host https://github.com/ARMmbed/mbed-os/pull/3626

3628: Fix warnings https://github.com/ARMmbed/mbed-os/pull/3628

3629: STM32: L0 LL layer https://github.com/ARMmbed/mbed-os/pull/3629

3632: IDE Export support for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3632

3642: Missing IRQ pin fix for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3642

3664: Fix ncs36510 sleep definitions https://github.com/ARMmbed/mbed-os/pull/3664

3655: [STM32F4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3655

3657: [STM32L4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3657

3658: [STM32F3] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3658

3685: STM32: I2C: reset state machine https://github.com/ARMmbed/mbed-os/pull/3685

3692: uVisor: Standardize available legacy heap and stack https://github.com/ARMmbed/mbed-os/pull/3692

3621: Fix for #2884, LPC824: export to LPCXpresso, target running with wron https://github.com/ARMmbed/mbed-os/pull/3621

3649: [STM32F7] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3649

3695: Enforce device_name is valid in targets.json https://github.com/ARMmbed/mbed-os/pull/3695

3723: NCS36510: spi_format function bug fix https://github.com/ARMmbed/mbed-os/pull/3723

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	128:9bcdf88f62b0	1	/**
<>	128:9bcdf88f62b0	2	******************************************************************************
<>	128:9bcdf88f62b0	3	* @file stm32l1xx_ll_dma.h
<>	128:9bcdf88f62b0	4	* @author MCD Application Team
<>	128:9bcdf88f62b0	5	* @version V1.2.0
<>	128:9bcdf88f62b0	6	* @date 01-July-2016
<>	128:9bcdf88f62b0	7	* @brief Header file of DMA LL module.
<>	128:9bcdf88f62b0	8	******************************************************************************
<>	128:9bcdf88f62b0	9	* @attention
<>	128:9bcdf88f62b0	10	*
<>	128:9bcdf88f62b0	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	128:9bcdf88f62b0	12	*
<>	128:9bcdf88f62b0	13	* Redistribution and use in source and binary forms, with or without modification,
<>	128:9bcdf88f62b0	14	* are permitted provided that the following conditions are met:
<>	128:9bcdf88f62b0	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	128:9bcdf88f62b0	16	* this list of conditions and the following disclaimer.
<>	128:9bcdf88f62b0	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	128:9bcdf88f62b0	18	* this list of conditions and the following disclaimer in the documentation
<>	128:9bcdf88f62b0	19	* and/or other materials provided with the distribution.
<>	128:9bcdf88f62b0	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	128:9bcdf88f62b0	21	* may be used to endorse or promote products derived from this software
<>	128:9bcdf88f62b0	22	* without specific prior written permission.
<>	128:9bcdf88f62b0	23	*
<>	128:9bcdf88f62b0	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	128:9bcdf88f62b0	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	128:9bcdf88f62b0	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	128:9bcdf88f62b0	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	128:9bcdf88f62b0	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	128:9bcdf88f62b0	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	128:9bcdf88f62b0	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	128:9bcdf88f62b0	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	128:9bcdf88f62b0	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	128:9bcdf88f62b0	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	128:9bcdf88f62b0	34	*
<>	128:9bcdf88f62b0	35	******************************************************************************
<>	128:9bcdf88f62b0	36	*/
<>	128:9bcdf88f62b0	37
<>	128:9bcdf88f62b0	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	128:9bcdf88f62b0	39	#ifndef __STM32L1xx_LL_DMA_H
<>	128:9bcdf88f62b0	40	#define __STM32L1xx_LL_DMA_H
<>	128:9bcdf88f62b0	41
<>	128:9bcdf88f62b0	42	#ifdef __cplusplus
<>	128:9bcdf88f62b0	43	extern "C" {
<>	128:9bcdf88f62b0	44	#endif
<>	128:9bcdf88f62b0	45
<>	128:9bcdf88f62b0	46	/* Includes ------------------------------------------------------------------*/
<>	128:9bcdf88f62b0	47	#include "stm32l1xx.h"
<>	128:9bcdf88f62b0	48
<>	128:9bcdf88f62b0	49	/** @addtogroup STM32L1xx_LL_Driver
<>	128:9bcdf88f62b0	50	* @{
<>	128:9bcdf88f62b0	51	*/
<>	128:9bcdf88f62b0	52
<>	128:9bcdf88f62b0	53	#if defined (DMA1) \|\| defined (DMA2)
<>	128:9bcdf88f62b0	54
<>	128:9bcdf88f62b0	55	/** @defgroup DMA_LL DMA
<>	128:9bcdf88f62b0	56	* @{
<>	128:9bcdf88f62b0	57	*/
<>	128:9bcdf88f62b0	58
<>	128:9bcdf88f62b0	59	/* Private types -------------------------------------------------------------*/
<>	128:9bcdf88f62b0	60	/* Private variables ---------------------------------------------------------*/
<>	128:9bcdf88f62b0	61	/** @defgroup DMA_LL_Private_Variables DMA Private Variables
<>	128:9bcdf88f62b0	62	* @{
<>	128:9bcdf88f62b0	63	*/
<>	128:9bcdf88f62b0	64	/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
<>	128:9bcdf88f62b0	65	static const uint8_t CHANNEL_OFFSET_TAB[] =
<>	128:9bcdf88f62b0	66	{
<>	128:9bcdf88f62b0	67	(uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
<>	128:9bcdf88f62b0	68	(uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
<>	128:9bcdf88f62b0	69	(uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
<>	128:9bcdf88f62b0	70	(uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
<>	128:9bcdf88f62b0	71	(uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
<>	128:9bcdf88f62b0	72	(uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
<>	128:9bcdf88f62b0	73	(uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
<>	128:9bcdf88f62b0	74	};
<>	128:9bcdf88f62b0	75	/**
<>	128:9bcdf88f62b0	76	* @}
<>	128:9bcdf88f62b0	77	*/
<>	128:9bcdf88f62b0	78
<>	128:9bcdf88f62b0	79	/* Private constants ---------------------------------------------------------*/
<>	128:9bcdf88f62b0	80	/** @defgroup DMA_LL_Private_Constants DMA Private Constants
<>	128:9bcdf88f62b0	81	* @{
<>	128:9bcdf88f62b0	82	*/
<>	128:9bcdf88f62b0	83	/* Define used to get CSELR register offset */
<>	128:9bcdf88f62b0	84	#define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
<>	128:9bcdf88f62b0	85
<>	128:9bcdf88f62b0	86	/* Defines used for the bit position in the register and perform offsets */
<>	128:9bcdf88f62b0	87	#define DMA_POSITION_CSELR_CXS POSITION_VAL(DMA_CSELR_C1S << ((Channel-1U)*4U))
<>	128:9bcdf88f62b0	88	/**
<>	128:9bcdf88f62b0	89	* @}
<>	128:9bcdf88f62b0	90	*/
<>	128:9bcdf88f62b0	91
<>	128:9bcdf88f62b0	92	/* Private macros ------------------------------------------------------------*/
<>	128:9bcdf88f62b0	93	#if defined(USE_FULL_LL_DRIVER)
<>	128:9bcdf88f62b0	94	/** @defgroup DMA_LL_Private_Macros DMA Private Macros
<>	128:9bcdf88f62b0	95	* @{
<>	128:9bcdf88f62b0	96	*/
<>	128:9bcdf88f62b0	97	/**
<>	128:9bcdf88f62b0	98	* @}
<>	128:9bcdf88f62b0	99	*/
<>	128:9bcdf88f62b0	100	#endif /USE_FULL_LL_DRIVER/
<>	128:9bcdf88f62b0	101
<>	128:9bcdf88f62b0	102	/* Exported types ------------------------------------------------------------*/
<>	128:9bcdf88f62b0	103	#if defined(USE_FULL_LL_DRIVER)
<>	128:9bcdf88f62b0	104	/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
<>	128:9bcdf88f62b0	105	* @{
<>	128:9bcdf88f62b0	106	*/
<>	128:9bcdf88f62b0	107	typedef struct
<>	128:9bcdf88f62b0	108	{
<>	128:9bcdf88f62b0	109	uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
<>	128:9bcdf88f62b0	110	or as Source base address in case of memory to memory transfer direction.
<>	128:9bcdf88f62b0	111
<>	128:9bcdf88f62b0	112	This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
<>	128:9bcdf88f62b0	113
<>	128:9bcdf88f62b0	114	uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
<>	128:9bcdf88f62b0	115	or as Destination base address in case of memory to memory transfer direction.
<>	128:9bcdf88f62b0	116
<>	128:9bcdf88f62b0	117	This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
<>	128:9bcdf88f62b0	118
<>	128:9bcdf88f62b0	119	uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
<>	128:9bcdf88f62b0	120	from memory to memory or from peripheral to memory.
<>	128:9bcdf88f62b0	121	This parameter can be a value of @ref DMA_LL_EC_DIRECTION
<>	128:9bcdf88f62b0	122
<>	128:9bcdf88f62b0	123	This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
<>	128:9bcdf88f62b0	124
<>	128:9bcdf88f62b0	125	uint32_t Mode; /*!< Specifies the normal or circular operation mode.
<>	128:9bcdf88f62b0	126	This parameter can be a value of @ref DMA_LL_EC_MODE
<>	128:9bcdf88f62b0	127	@note: The circular buffer mode cannot be used if the memory to memory
<>	128:9bcdf88f62b0	128	data transfer direction is configured on the selected Channel
<>	128:9bcdf88f62b0	129
<>	128:9bcdf88f62b0	130	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
<>	128:9bcdf88f62b0	131
<>	128:9bcdf88f62b0	132	uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
<>	128:9bcdf88f62b0	133	is incremented or not.
<>	128:9bcdf88f62b0	134	This parameter can be a value of @ref DMA_LL_EC_PERIPH
<>	128:9bcdf88f62b0	135
<>	128:9bcdf88f62b0	136	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
<>	128:9bcdf88f62b0	137
<>	128:9bcdf88f62b0	138	uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
<>	128:9bcdf88f62b0	139	is incremented or not.
<>	128:9bcdf88f62b0	140	This parameter can be a value of @ref DMA_LL_EC_MEMORY
<>	128:9bcdf88f62b0	141
<>	128:9bcdf88f62b0	142	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
<>	128:9bcdf88f62b0	143
<>	128:9bcdf88f62b0	144	uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
<>	128:9bcdf88f62b0	145	in case of memory to memory transfer direction.
<>	128:9bcdf88f62b0	146	This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
<>	128:9bcdf88f62b0	147
<>	128:9bcdf88f62b0	148	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
<>	128:9bcdf88f62b0	149
<>	128:9bcdf88f62b0	150	uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
<>	128:9bcdf88f62b0	151	in case of memory to memory transfer direction.
<>	128:9bcdf88f62b0	152	This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
<>	128:9bcdf88f62b0	153
<>	128:9bcdf88f62b0	154	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
<>	128:9bcdf88f62b0	155
<>	128:9bcdf88f62b0	156	uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
<>	128:9bcdf88f62b0	157	The data unit is equal to the source buffer configuration set in PeripheralSize
<>	128:9bcdf88f62b0	158	or MemorySize parameters depending in the transfer direction.
<>	128:9bcdf88f62b0	159	This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
<>	128:9bcdf88f62b0	160
<>	128:9bcdf88f62b0	161	This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
<>	128:9bcdf88f62b0	162
<>	128:9bcdf88f62b0	163	uint32_t Priority; /*!< Specifies the channel priority level.
<>	128:9bcdf88f62b0	164	This parameter can be a value of @ref DMA_LL_EC_PRIORITY
<>	128:9bcdf88f62b0	165
<>	128:9bcdf88f62b0	166	This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
<>	128:9bcdf88f62b0	167
<>	128:9bcdf88f62b0	168	} LL_DMA_InitTypeDef;
<>	128:9bcdf88f62b0	169	/**
<>	128:9bcdf88f62b0	170	* @}
<>	128:9bcdf88f62b0	171	*/
<>	128:9bcdf88f62b0	172	#endif /USE_FULL_LL_DRIVER/
<>	128:9bcdf88f62b0	173
<>	128:9bcdf88f62b0	174	/* Exported constants --------------------------------------------------------*/
<>	128:9bcdf88f62b0	175	/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
<>	128:9bcdf88f62b0	176	* @{
<>	128:9bcdf88f62b0	177	*/
<>	128:9bcdf88f62b0	178	/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
<>	128:9bcdf88f62b0	179	* @brief Flags defines which can be used with LL_DMA_WriteReg function
<>	128:9bcdf88f62b0	180	* @{
<>	128:9bcdf88f62b0	181	*/
<>	128:9bcdf88f62b0	182	#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /!< Channel 1 global flag /
<>	128:9bcdf88f62b0	183	#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /!< Channel 1 transfer complete flag /
<>	128:9bcdf88f62b0	184	#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /!< Channel 1 half transfer flag /
<>	128:9bcdf88f62b0	185	#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /!< Channel 1 transfer error flag /
<>	128:9bcdf88f62b0	186	#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /!< Channel 2 global flag /
<>	128:9bcdf88f62b0	187	#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /!< Channel 2 transfer complete flag /
<>	128:9bcdf88f62b0	188	#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /!< Channel 2 half transfer flag /
<>	128:9bcdf88f62b0	189	#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /!< Channel 2 transfer error flag /
<>	128:9bcdf88f62b0	190	#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /!< Channel 3 global flag /
<>	128:9bcdf88f62b0	191	#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /!< Channel 3 transfer complete flag /
<>	128:9bcdf88f62b0	192	#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /!< Channel 3 half transfer flag /
<>	128:9bcdf88f62b0	193	#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /!< Channel 3 transfer error flag /
<>	128:9bcdf88f62b0	194	#define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /!< Channel 4 global flag /
<>	128:9bcdf88f62b0	195	#define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /!< Channel 4 transfer complete flag /
<>	128:9bcdf88f62b0	196	#define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /!< Channel 4 half transfer flag /
<>	128:9bcdf88f62b0	197	#define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /!< Channel 4 transfer error flag /
<>	128:9bcdf88f62b0	198	#define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /!< Channel 5 global flag /
<>	128:9bcdf88f62b0	199	#define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /!< Channel 5 transfer complete flag /
<>	128:9bcdf88f62b0	200	#define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /!< Channel 5 half transfer flag /
<>	128:9bcdf88f62b0	201	#define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /!< Channel 5 transfer error flag /
<>	128:9bcdf88f62b0	202	#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /!< Channel 6 global flag /
<>	128:9bcdf88f62b0	203	#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /!< Channel 6 transfer complete flag /
<>	128:9bcdf88f62b0	204	#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /!< Channel 6 half transfer flag /
<>	128:9bcdf88f62b0	205	#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /!< Channel 6 transfer error flag /
<>	128:9bcdf88f62b0	206	#define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /!< Channel 7 global flag /
<>	128:9bcdf88f62b0	207	#define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /!< Channel 7 transfer complete flag /
<>	128:9bcdf88f62b0	208	#define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /!< Channel 7 half transfer flag /
<>	128:9bcdf88f62b0	209	#define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /!< Channel 7 transfer error flag /
<>	128:9bcdf88f62b0	210	/**
<>	128:9bcdf88f62b0	211	* @}
<>	128:9bcdf88f62b0	212	*/
<>	128:9bcdf88f62b0	213
<>	128:9bcdf88f62b0	214	/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
<>	128:9bcdf88f62b0	215	* @brief Flags defines which can be used with LL_DMA_ReadReg function
<>	128:9bcdf88f62b0	216	* @{
<>	128:9bcdf88f62b0	217	*/
<>	128:9bcdf88f62b0	218	#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /!< Channel 1 global flag /
<>	128:9bcdf88f62b0	219	#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /!< Channel 1 transfer complete flag /
<>	128:9bcdf88f62b0	220	#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /!< Channel 1 half transfer flag /
<>	128:9bcdf88f62b0	221	#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /!< Channel 1 transfer error flag /
<>	128:9bcdf88f62b0	222	#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /!< Channel 2 global flag /
<>	128:9bcdf88f62b0	223	#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /!< Channel 2 transfer complete flag /
<>	128:9bcdf88f62b0	224	#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /!< Channel 2 half transfer flag /
<>	128:9bcdf88f62b0	225	#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /!< Channel 2 transfer error flag /
<>	128:9bcdf88f62b0	226	#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /!< Channel 3 global flag /
<>	128:9bcdf88f62b0	227	#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /!< Channel 3 transfer complete flag /
<>	128:9bcdf88f62b0	228	#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /!< Channel 3 half transfer flag /
<>	128:9bcdf88f62b0	229	#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /!< Channel 3 transfer error flag /
<>	128:9bcdf88f62b0	230	#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /!< Channel 4 global flag /
<>	128:9bcdf88f62b0	231	#define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /!< Channel 4 transfer complete flag /
<>	128:9bcdf88f62b0	232	#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /!< Channel 4 half transfer flag /
<>	128:9bcdf88f62b0	233	#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /!< Channel 4 transfer error flag /
<>	128:9bcdf88f62b0	234	#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /!< Channel 5 global flag /
<>	128:9bcdf88f62b0	235	#define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /!< Channel 5 transfer complete flag /
<>	128:9bcdf88f62b0	236	#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /!< Channel 5 half transfer flag /
<>	128:9bcdf88f62b0	237	#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /!< Channel 5 transfer error flag /
<>	128:9bcdf88f62b0	238	#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /!< Channel 6 global flag /
<>	128:9bcdf88f62b0	239	#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /!< Channel 6 transfer complete flag /
<>	128:9bcdf88f62b0	240	#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /!< Channel 6 half transfer flag /
<>	128:9bcdf88f62b0	241	#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /!< Channel 6 transfer error flag /
<>	128:9bcdf88f62b0	242	#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /!< Channel 7 global flag /
<>	128:9bcdf88f62b0	243	#define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /!< Channel 7 transfer complete flag /
<>	128:9bcdf88f62b0	244	#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /!< Channel 7 half transfer flag /
<>	128:9bcdf88f62b0	245	#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /!< Channel 7 transfer error flag /
<>	128:9bcdf88f62b0	246	/**
<>	128:9bcdf88f62b0	247	* @}
<>	128:9bcdf88f62b0	248	*/
<>	128:9bcdf88f62b0	249
<>	128:9bcdf88f62b0	250	/** @defgroup DMA_LL_EC_IT IT Defines
<>	128:9bcdf88f62b0	251	* @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
<>	128:9bcdf88f62b0	252	* @{
<>	128:9bcdf88f62b0	253	*/
<>	128:9bcdf88f62b0	254	#define LL_DMA_CCR_TCIE DMA_CCR_TCIE /!< Transfer complete interrupt /
<>	128:9bcdf88f62b0	255	#define LL_DMA_CCR_HTIE DMA_CCR_HTIE /!< Half Transfer interrupt /
<>	128:9bcdf88f62b0	256	#define LL_DMA_CCR_TEIE DMA_CCR_TEIE /!< Transfer error interrupt /
<>	128:9bcdf88f62b0	257	/**
<>	128:9bcdf88f62b0	258	* @}
<>	128:9bcdf88f62b0	259	*/
<>	128:9bcdf88f62b0	260
<>	128:9bcdf88f62b0	261	/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
<>	128:9bcdf88f62b0	262	* @{
<>	128:9bcdf88f62b0	263	*/
<>	128:9bcdf88f62b0	264	#define LL_DMA_CHANNEL_1 ((uint32_t)0x00000001U) /!< DMA Channel 1 /
<>	128:9bcdf88f62b0	265	#define LL_DMA_CHANNEL_2 ((uint32_t)0x00000002U) /!< DMA Channel 2 /
<>	128:9bcdf88f62b0	266	#define LL_DMA_CHANNEL_3 ((uint32_t)0x00000003U) /!< DMA Channel 3 /
<>	128:9bcdf88f62b0	267	#define LL_DMA_CHANNEL_4 ((uint32_t)0x00000004U) /!< DMA Channel 4 /
<>	128:9bcdf88f62b0	268	#define LL_DMA_CHANNEL_5 ((uint32_t)0x00000005U) /!< DMA Channel 5 /
<>	128:9bcdf88f62b0	269	#define LL_DMA_CHANNEL_6 ((uint32_t)0x00000006U) /!< DMA Channel 6 /
<>	128:9bcdf88f62b0	270	#define LL_DMA_CHANNEL_7 ((uint32_t)0x00000007U) /!< DMA Channel 7 /
<>	128:9bcdf88f62b0	271	#if defined(USE_FULL_LL_DRIVER)
<>	128:9bcdf88f62b0	272	#define LL_DMA_CHANNEL_ALL ((uint32_t)0xFFFF0000U) /!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). /
<>	128:9bcdf88f62b0	273	#endif /USE_FULL_LL_DRIVER/
<>	128:9bcdf88f62b0	274	/**
<>	128:9bcdf88f62b0	275	* @}
<>	128:9bcdf88f62b0	276	*/
<>	128:9bcdf88f62b0	277
<>	128:9bcdf88f62b0	278	/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
<>	128:9bcdf88f62b0	279	* @{
<>	128:9bcdf88f62b0	280	*/
<>	128:9bcdf88f62b0	281	#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /!< Peripheral to memory direction /
<>	128:9bcdf88f62b0	282	#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /!< Memory to peripheral direction /
<>	128:9bcdf88f62b0	283	#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /!< Memory to memory direction /
<>	128:9bcdf88f62b0	284	/**
<>	128:9bcdf88f62b0	285	* @}
<>	128:9bcdf88f62b0	286	*/
<>	128:9bcdf88f62b0	287
<>	128:9bcdf88f62b0	288	/** @defgroup DMA_LL_EC_MODE Transfer mode
<>	128:9bcdf88f62b0	289	* @{
<>	128:9bcdf88f62b0	290	*/
<>	128:9bcdf88f62b0	291	#define LL_DMA_MODE_NORMAL ((uint32_t)0x00000000U) /!< Normal Mode /
<>	128:9bcdf88f62b0	292	#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /!< Circular Mode /
<>	128:9bcdf88f62b0	293	/**
<>	128:9bcdf88f62b0	294	* @}
<>	128:9bcdf88f62b0	295	*/
<>	128:9bcdf88f62b0	296
<>	128:9bcdf88f62b0	297	/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
<>	128:9bcdf88f62b0	298	* @{
<>	128:9bcdf88f62b0	299	*/
<>	128:9bcdf88f62b0	300	#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /!< Peripheral increment mode Enable /
<>	128:9bcdf88f62b0	301	#define LL_DMA_PERIPH_NOINCREMENT ((uint32_t)0x00000000U) /!< Peripheral increment mode Disable /
<>	128:9bcdf88f62b0	302	/**
<>	128:9bcdf88f62b0	303	* @}
<>	128:9bcdf88f62b0	304	*/
<>	128:9bcdf88f62b0	305
<>	128:9bcdf88f62b0	306	/** @defgroup DMA_LL_EC_MEMORY Memory increment mode
<>	128:9bcdf88f62b0	307	* @{
<>	128:9bcdf88f62b0	308	*/
<>	128:9bcdf88f62b0	309	#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /!< Memory increment mode Enable /
<>	128:9bcdf88f62b0	310	#define LL_DMA_MEMORY_NOINCREMENT ((uint32_t)0x00000000U) /!< Memory increment mode Disable /
<>	128:9bcdf88f62b0	311	/**
<>	128:9bcdf88f62b0	312	* @}
<>	128:9bcdf88f62b0	313	*/
<>	128:9bcdf88f62b0	314
<>	128:9bcdf88f62b0	315	/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
<>	128:9bcdf88f62b0	316	* @{
<>	128:9bcdf88f62b0	317	*/
<>	128:9bcdf88f62b0	318	#define LL_DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /!< Peripheral data alignment : Byte /
<>	128:9bcdf88f62b0	319	#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /!< Peripheral data alignment : HalfWord /
<>	128:9bcdf88f62b0	320	#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /!< Peripheral data alignment : Word /
<>	128:9bcdf88f62b0	321	/**
<>	128:9bcdf88f62b0	322	* @}
<>	128:9bcdf88f62b0	323	*/
<>	128:9bcdf88f62b0	324
<>	128:9bcdf88f62b0	325	/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
<>	128:9bcdf88f62b0	326	* @{
<>	128:9bcdf88f62b0	327	*/
<>	128:9bcdf88f62b0	328	#define LL_DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /!< Memory data alignment : Byte /
<>	128:9bcdf88f62b0	329	#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /!< Memory data alignment : HalfWord /
<>	128:9bcdf88f62b0	330	#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /!< Memory data alignment : Word /
<>	128:9bcdf88f62b0	331	/**
<>	128:9bcdf88f62b0	332	* @}
<>	128:9bcdf88f62b0	333	*/
<>	128:9bcdf88f62b0	334
<>	128:9bcdf88f62b0	335	/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
<>	128:9bcdf88f62b0	336	* @{
<>	128:9bcdf88f62b0	337	*/
<>	128:9bcdf88f62b0	338	#define LL_DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /!< Priority level : Low /
<>	128:9bcdf88f62b0	339	#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /!< Priority level : Medium /
<>	128:9bcdf88f62b0	340	#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /!< Priority level : High /
<>	128:9bcdf88f62b0	341	#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /!< Priority level : Very_High /
<>	128:9bcdf88f62b0	342	/**
<>	128:9bcdf88f62b0	343	* @}
<>	128:9bcdf88f62b0	344	*/
<>	128:9bcdf88f62b0	345
<>	128:9bcdf88f62b0	346
<>	128:9bcdf88f62b0	347	/**
<>	128:9bcdf88f62b0	348	* @}
<>	128:9bcdf88f62b0	349	*/
<>	128:9bcdf88f62b0	350
<>	128:9bcdf88f62b0	351	/* Exported macro ------------------------------------------------------------*/
<>	128:9bcdf88f62b0	352	/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
<>	128:9bcdf88f62b0	353	* @{
<>	128:9bcdf88f62b0	354	*/
<>	128:9bcdf88f62b0	355
<>	128:9bcdf88f62b0	356	/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
<>	128:9bcdf88f62b0	357	* @{
<>	128:9bcdf88f62b0	358	*/
<>	128:9bcdf88f62b0	359	/**
<>	128:9bcdf88f62b0	360	* @brief Write a value in DMA register
<>	128:9bcdf88f62b0	361	* @param __INSTANCE__ DMA Instance
<>	128:9bcdf88f62b0	362	* @param __REG__ Register to be written
<>	128:9bcdf88f62b0	363	* @param __VALUE__ Value to be written in the register
<>	128:9bcdf88f62b0	364	* @retval None
<>	128:9bcdf88f62b0	365	*/
<>	128:9bcdf88f62b0	366	#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<>	128:9bcdf88f62b0	367
<>	128:9bcdf88f62b0	368	/**
<>	128:9bcdf88f62b0	369	* @brief Read a value in DMA register
<>	128:9bcdf88f62b0	370	* @param __INSTANCE__ DMA Instance
<>	128:9bcdf88f62b0	371	* @param __REG__ Register to be read
<>	128:9bcdf88f62b0	372	* @retval Register value
<>	128:9bcdf88f62b0	373	*/
<>	128:9bcdf88f62b0	374	#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<>	128:9bcdf88f62b0	375	/**
<>	128:9bcdf88f62b0	376	* @}
<>	128:9bcdf88f62b0	377	*/
<>	128:9bcdf88f62b0	378
<>	128:9bcdf88f62b0	379	/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
<>	128:9bcdf88f62b0	380	* @{
<>	128:9bcdf88f62b0	381	*/
<>	128:9bcdf88f62b0	382	/**
<>	128:9bcdf88f62b0	383	* @brief Convert DMAx_Channely into DMAx
<>	128:9bcdf88f62b0	384	* @param __CHANNEL_INSTANCE__ DMAx_Channely
<>	128:9bcdf88f62b0	385	* @retval DMAx
<>	128:9bcdf88f62b0	386	*/
<>	128:9bcdf88f62b0	387	#if defined(DMA2)
<>	128:9bcdf88f62b0	388	#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
<>	128:9bcdf88f62b0	389	(((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
<>	128:9bcdf88f62b0	390	#else
<>	128:9bcdf88f62b0	391	#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
<>	128:9bcdf88f62b0	392	#endif
<>	128:9bcdf88f62b0	393
<>	128:9bcdf88f62b0	394	/**
<>	128:9bcdf88f62b0	395	* @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
<>	128:9bcdf88f62b0	396	* @param __CHANNEL_INSTANCE__ DMAx_Channely
<>	128:9bcdf88f62b0	397	* @retval LL_DMA_CHANNEL_y
<>	128:9bcdf88f62b0	398	*/
<>	128:9bcdf88f62b0	399	#if defined (DMA2)
<>	128:9bcdf88f62b0	400	#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
<>	128:9bcdf88f62b0	401	#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
<>	128:9bcdf88f62b0	402	(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
<>	128:9bcdf88f62b0	403	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
<>	128:9bcdf88f62b0	404	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
<>	128:9bcdf88f62b0	405	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
<>	128:9bcdf88f62b0	406	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
<>	128:9bcdf88f62b0	407	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
<>	128:9bcdf88f62b0	408	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
<>	128:9bcdf88f62b0	409	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
<>	128:9bcdf88f62b0	410	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
<>	128:9bcdf88f62b0	411	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
<>	128:9bcdf88f62b0	412	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
<>	128:9bcdf88f62b0	413	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
<>	128:9bcdf88f62b0	414	LL_DMA_CHANNEL_7)
<>	128:9bcdf88f62b0	415	#else
<>	128:9bcdf88f62b0	416	#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
<>	128:9bcdf88f62b0	417	(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
<>	128:9bcdf88f62b0	418	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
<>	128:9bcdf88f62b0	419	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
<>	128:9bcdf88f62b0	420	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
<>	128:9bcdf88f62b0	421	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
<>	128:9bcdf88f62b0	422	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
<>	128:9bcdf88f62b0	423	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
<>	128:9bcdf88f62b0	424	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
<>	128:9bcdf88f62b0	425	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
<>	128:9bcdf88f62b0	426	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
<>	128:9bcdf88f62b0	427	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
<>	128:9bcdf88f62b0	428	LL_DMA_CHANNEL_7)
<>	128:9bcdf88f62b0	429	#endif
<>	128:9bcdf88f62b0	430	#else
<>	128:9bcdf88f62b0	431	#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
<>	128:9bcdf88f62b0	432	(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
<>	128:9bcdf88f62b0	433	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
<>	128:9bcdf88f62b0	434	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
<>	128:9bcdf88f62b0	435	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
<>	128:9bcdf88f62b0	436	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
<>	128:9bcdf88f62b0	437	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
<>	128:9bcdf88f62b0	438	LL_DMA_CHANNEL_7)
<>	128:9bcdf88f62b0	439	#endif
<>	128:9bcdf88f62b0	440
<>	128:9bcdf88f62b0	441	/**
<>	128:9bcdf88f62b0	442	* @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
<>	128:9bcdf88f62b0	443	* @param __DMA_INSTANCE__ DMAx
<>	128:9bcdf88f62b0	444	* @param __CHANNEL__ LL_DMA_CHANNEL_y
<>	128:9bcdf88f62b0	445	* @retval DMAx_Channely
<>	128:9bcdf88f62b0	446	*/
<>	128:9bcdf88f62b0	447	#if defined (DMA2)
<>	128:9bcdf88f62b0	448	#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
<>	128:9bcdf88f62b0	449	#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
<>	128:9bcdf88f62b0	450	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
<>	128:9bcdf88f62b0	451	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
<>	128:9bcdf88f62b0	452	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
<>	128:9bcdf88f62b0	453	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
<>	128:9bcdf88f62b0	454	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
<>	128:9bcdf88f62b0	455	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
<>	128:9bcdf88f62b0	456	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
<>	128:9bcdf88f62b0	457	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
<>	128:9bcdf88f62b0	458	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
<>	128:9bcdf88f62b0	459	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
<>	128:9bcdf88f62b0	460	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
<>	128:9bcdf88f62b0	461	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
<>	128:9bcdf88f62b0	462	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
<>	128:9bcdf88f62b0	463	DMA2_Channel7)
<>	128:9bcdf88f62b0	464	#else
<>	128:9bcdf88f62b0	465	#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
<>	128:9bcdf88f62b0	466	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
<>	128:9bcdf88f62b0	467	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
<>	128:9bcdf88f62b0	468	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
<>	128:9bcdf88f62b0	469	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
<>	128:9bcdf88f62b0	470	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
<>	128:9bcdf88f62b0	471	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
<>	128:9bcdf88f62b0	472	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
<>	128:9bcdf88f62b0	473	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
<>	128:9bcdf88f62b0	474	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
<>	128:9bcdf88f62b0	475	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
<>	128:9bcdf88f62b0	476	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
<>	128:9bcdf88f62b0	477	DMA1_Channel7)
<>	128:9bcdf88f62b0	478	#endif
<>	128:9bcdf88f62b0	479	#else
<>	128:9bcdf88f62b0	480	#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
<>	128:9bcdf88f62b0	481	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
<>	128:9bcdf88f62b0	482	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
<>	128:9bcdf88f62b0	483	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
<>	128:9bcdf88f62b0	484	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
<>	128:9bcdf88f62b0	485	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
<>	128:9bcdf88f62b0	486	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
<>	128:9bcdf88f62b0	487	DMA1_Channel7)
<>	128:9bcdf88f62b0	488	#endif
<>	128:9bcdf88f62b0	489
<>	128:9bcdf88f62b0	490	/**
<>	128:9bcdf88f62b0	491	* @}
<>	128:9bcdf88f62b0	492	*/
<>	128:9bcdf88f62b0	493
<>	128:9bcdf88f62b0	494	/**
<>	128:9bcdf88f62b0	495	* @}
<>	128:9bcdf88f62b0	496	*/
<>	128:9bcdf88f62b0	497
<>	128:9bcdf88f62b0	498	/* Exported functions --------------------------------------------------------*/
<>	128:9bcdf88f62b0	499	/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
<>	128:9bcdf88f62b0	500	* @{
<>	128:9bcdf88f62b0	501	*/
<>	128:9bcdf88f62b0	502
<>	128:9bcdf88f62b0	503	/** @defgroup DMA_LL_EF_Configuration Configuration
<>	128:9bcdf88f62b0	504	* @{
<>	128:9bcdf88f62b0	505	*/
<>	128:9bcdf88f62b0	506	/**
<>	128:9bcdf88f62b0	507	* @brief Enable DMA channel.
<>	128:9bcdf88f62b0	508	* @rmtoll CCR EN LL_DMA_EnableChannel
<>	128:9bcdf88f62b0	509	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	510	* @param Channel This parameter can be one of the following values:
<>	128:9bcdf88f62b0	511	* @arg @ref LL_DMA_CHANNEL_1
<>	128:9bcdf88f62b0	512	* @arg @ref LL_DMA_CHANNEL_2
<>	128:9bcdf88f62b0	513	* @arg @ref LL_DMA_CHANNEL_3
<>	128:9bcdf88f62b0	514	* @arg @ref LL_DMA_CHANNEL_4
<>	128:9bcdf88f62b0	515	* @arg @ref LL_DMA_CHANNEL_5
<>	128:9bcdf88f62b0	516	* @arg @ref LL_DMA_CHANNEL_6
<>	128:9bcdf88f62b0	517	* @arg @ref LL_DMA_CHANNEL_7
<>	128:9bcdf88f62b0	518	* @retval None
<>	128:9bcdf88f62b0	519	*/
<>	128:9bcdf88f62b0	520	__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
<>	128:9bcdf88f62b0	521	{
<>	128:9bcdf88f62b0	522	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
<>	128:9bcdf88f62b0	523	}
<>	128:9bcdf88f62b0	524
<>	128:9bcdf88f62b0	525	/**
<>	128:9bcdf88f62b0	526	* @brief Disable DMA channel.
<>	128:9bcdf88f62b0	527	* @rmtoll CCR EN LL_DMA_DisableChannel
<>	128:9bcdf88f62b0	528	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	529	* @param Channel This parameter can be one of the following values:
<>	128:9bcdf88f62b0	530	* @arg @ref LL_DMA_CHANNEL_1
<>	128:9bcdf88f62b0	531	* @arg @ref LL_DMA_CHANNEL_2
<>	128:9bcdf88f62b0	532	* @arg @ref LL_DMA_CHANNEL_3
<>	128:9bcdf88f62b0	533	* @arg @ref LL_DMA_CHANNEL_4
<>	128:9bcdf88f62b0	534	* @arg @ref LL_DMA_CHANNEL_5
<>	128:9bcdf88f62b0	535	* @arg @ref LL_DMA_CHANNEL_6
<>	128:9bcdf88f62b0	536	* @arg @ref LL_DMA_CHANNEL_7
<>	128:9bcdf88f62b0	537	* @retval None
<>	128:9bcdf88f62b0	538	*/
<>	128:9bcdf88f62b0	539	__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
<>	128:9bcdf88f62b0	540	{
<>	128:9bcdf88f62b0	541	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
<>	128:9bcdf88f62b0	542	}
<>	128:9bcdf88f62b0	543
<>	128:9bcdf88f62b0	544	/**
<>	128:9bcdf88f62b0	545	* @brief Check if DMA channel is enabled or disabled.
<>	128:9bcdf88f62b0	546	* @rmtoll CCR EN LL_DMA_IsEnabledChannel
<>	128:9bcdf88f62b0	547	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	548	* @param Channel This parameter can be one of the following values:
<>	128:9bcdf88f62b0	549	* @arg @ref LL_DMA_CHANNEL_1
<>	128:9bcdf88f62b0	550	* @arg @ref LL_DMA_CHANNEL_2
<>	128:9bcdf88f62b0	551	* @arg @ref LL_DMA_CHANNEL_3
<>	128:9bcdf88f62b0	552	* @arg @ref LL_DMA_CHANNEL_4
<>	128:9bcdf88f62b0	553	* @arg @ref LL_DMA_CHANNEL_5
<>	128:9bcdf88f62b0	554	* @arg @ref LL_DMA_CHANNEL_6
<>	128:9bcdf88f62b0	555	* @arg @ref LL_DMA_CHANNEL_7
<>	128:9bcdf88f62b0	556	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	557	*/
<>	128:9bcdf88f62b0	558	__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
<>	128:9bcdf88f62b0	559	{
<>	128:9bcdf88f62b0	560	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	128:9bcdf88f62b0	561	DMA_CCR_EN) == (DMA_CCR_EN));
<>	128:9bcdf88f62b0	562	}
<>	128:9bcdf88f62b0	563
<>	128:9bcdf88f62b0	564	/**
<>	128:9bcdf88f62b0	565	* @brief Configure all parameters link to DMA transfer.
<>	128:9bcdf88f62b0	566	* @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
<>	128:9bcdf88f62b0	567	* CCR MEM2MEM LL_DMA_ConfigTransfer\n
<>	128:9bcdf88f62b0	568	* CCR CIRC LL_DMA_ConfigTransfer\n
<>	128:9bcdf88f62b0	569	* CCR PINC LL_DMA_ConfigTransfer\n
<>	128:9bcdf88f62b0	570	* CCR MINC LL_DMA_ConfigTransfer\n
<>	128:9bcdf88f62b0	571	* CCR PSIZE LL_DMA_ConfigTransfer\n
<>	128:9bcdf88f62b0	572	* CCR MSIZE LL_DMA_ConfigTransfer\n
<>	128:9bcdf88f62b0	573	* CCR PL LL_DMA_ConfigTransfer
<>	128:9bcdf88f62b0	574	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	575	* @param Channel This parameter can be one of the following values:
<>	128:9bcdf88f62b0	576	* @arg @ref LL_DMA_CHANNEL_1
<>	128:9bcdf88f62b0	577	* @arg @ref LL_DMA_CHANNEL_2
<>	128:9bcdf88f62b0	578	* @arg @ref LL_DMA_CHANNEL_3
<>	128:9bcdf88f62b0	579	* @arg @ref LL_DMA_CHANNEL_4
<>	128:9bcdf88f62b0	580	* @arg @ref LL_DMA_CHANNEL_5
<>	128:9bcdf88f62b0	581	* @arg @ref LL_DMA_CHANNEL_6
<>	128:9bcdf88f62b0	582	* @arg @ref LL_DMA_CHANNEL_7
<>	128:9bcdf88f62b0	583	* @param Configuration This parameter must be a combination of all the following values:
<>	128:9bcdf88f62b0	584	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
<>	128:9bcdf88f62b0	585	* @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
<>	128:9bcdf88f62b0	586	* @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
<>	128:9bcdf88f62b0	587	* @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
<>	128:9bcdf88f62b0	588	* @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
<>	128:9bcdf88f62b0	589	* @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
<>	128:9bcdf88f62b0	590	* @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
<>	128:9bcdf88f62b0	591	* @retval None
<>	128:9bcdf88f62b0	592	*/
<>	128:9bcdf88f62b0	593	__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
<>	128:9bcdf88f62b0	594	{
<>	128:9bcdf88f62b0	595	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	128:9bcdf88f62b0	596	DMA_CCR_DIR \| DMA_CCR_MEM2MEM \| DMA_CCR_CIRC \| DMA_CCR_PINC \| DMA_CCR_MINC \| DMA_CCR_PSIZE \| DMA_CCR_MSIZE \| DMA_CCR_PL,
<>	128:9bcdf88f62b0	597	Configuration);
<>	128:9bcdf88f62b0	598	}
<>	128:9bcdf88f62b0	599
<>	128:9bcdf88f62b0	600	/**
<>	128:9bcdf88f62b0	601	* @brief Set Data transfer direction (read from peripheral or from memory).
<>	128:9bcdf88f62b0	602	* @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
<>	128:9bcdf88f62b0	603	* CCR MEM2MEM LL_DMA_SetDataTransferDirection
<>	128:9bcdf88f62b0	604	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	605	* @param Channel This parameter can be one of the following values:
<>	128:9bcdf88f62b0	606	* @arg @ref LL_DMA_CHANNEL_1
<>	128:9bcdf88f62b0	607	* @arg @ref LL_DMA_CHANNEL_2
<>	128:9bcdf88f62b0	608	* @arg @ref LL_DMA_CHANNEL_3
<>	128:9bcdf88f62b0	609	* @arg @ref LL_DMA_CHANNEL_4
<>	128:9bcdf88f62b0	610	* @arg @ref LL_DMA_CHANNEL_5
<>	128:9bcdf88f62b0	611	* @arg @ref LL_DMA_CHANNEL_6
<>	128:9bcdf88f62b0	612	* @arg @ref LL_DMA_CHANNEL_7
<>	128:9bcdf88f62b0	613	* @param Direction This parameter can be one of the following values:
<>	128:9bcdf88f62b0	614	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
<>	128:9bcdf88f62b0	615	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
<>	128:9bcdf88f62b0	616	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
<>	128:9bcdf88f62b0	617	* @retval None
<>	128:9bcdf88f62b0	618	*/
<>	128:9bcdf88f62b0	619	__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
<>	128:9bcdf88f62b0	620	{
<>	128:9bcdf88f62b0	621	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	128:9bcdf88f62b0	622	DMA_CCR_DIR \| DMA_CCR_MEM2MEM, Direction);
<>	128:9bcdf88f62b0	623	}
<>	128:9bcdf88f62b0	624
<>	128:9bcdf88f62b0	625	/**
<>	128:9bcdf88f62b0	626	* @brief Get Data transfer direction (read from peripheral or from memory).
<>	128:9bcdf88f62b0	627	* @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
<>	128:9bcdf88f62b0	628	* CCR MEM2MEM LL_DMA_GetDataTransferDirection
<>	128:9bcdf88f62b0	629	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	630	* @param Channel This parameter can be one of the following values:
<>	128:9bcdf88f62b0	631	* @arg @ref LL_DMA_CHANNEL_1
<>	128:9bcdf88f62b0	632	* @arg @ref LL_DMA_CHANNEL_2
<>	128:9bcdf88f62b0	633	* @arg @ref LL_DMA_CHANNEL_3
<>	128:9bcdf88f62b0	634	* @arg @ref LL_DMA_CHANNEL_4
<>	128:9bcdf88f62b0	635	* @arg @ref LL_DMA_CHANNEL_5
<>	128:9bcdf88f62b0	636	* @arg @ref LL_DMA_CHANNEL_6
<>	128:9bcdf88f62b0	637	* @arg @ref LL_DMA_CHANNEL_7
<>	128:9bcdf88f62b0	638	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	639	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
<>	128:9bcdf88f62b0	640	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
<>	128:9bcdf88f62b0	641	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
<>	128:9bcdf88f62b0	642	*/
<>	128:9bcdf88f62b0	643	__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
<>	128:9bcdf88f62b0	644	{
<>	128:9bcdf88f62b0	645	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	128:9bcdf88f62b0	646	DMA_CCR_DIR \| DMA_CCR_MEM2MEM));
<>	128:9bcdf88f62b0	647	}
<>	128:9bcdf88f62b0	648
<>	128:9bcdf88f62b0	649	/**
<>	128:9bcdf88f62b0	650	* @brief Set DMA mode circular or normal.
<>	128:9bcdf88f62b0	651	* @note The circular buffer mode cannot be used if the memory-to-memory
<>	128:9bcdf88f62b0	652	* data transfer is configured on the selected Channel.
<>	128:9bcdf88f62b0	653	* @rmtoll CCR CIRC LL_DMA_SetMode
<>	128:9bcdf88f62b0	654	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	655	* @param Channel This parameter can be one of the following values:
<>	128:9bcdf88f62b0	656	* @arg @ref LL_DMA_CHANNEL_1
<>	128:9bcdf88f62b0	657	* @arg @ref LL_DMA_CHANNEL_2
<>	128:9bcdf88f62b0	658	* @arg @ref LL_DMA_CHANNEL_3
<>	128:9bcdf88f62b0	659	* @arg @ref LL_DMA_CHANNEL_4
<>	128:9bcdf88f62b0	660	* @arg @ref LL_DMA_CHANNEL_5
<>	128:9bcdf88f62b0	661	* @arg @ref LL_DMA_CHANNEL_6
<>	128:9bcdf88f62b0	662	* @arg @ref LL_DMA_CHANNEL_7
<>	128:9bcdf88f62b0	663	* @param Mode This parameter can be one of the following values:
<>	128:9bcdf88f62b0	664	* @arg @ref LL_DMA_MODE_NORMAL
<>	128:9bcdf88f62b0	665	* @arg @ref LL_DMA_MODE_CIRCULAR
<>	128:9bcdf88f62b0	666	* @retval None
<>	128:9bcdf88f62b0	667	*/
<>	128:9bcdf88f62b0	668	__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
<>	128:9bcdf88f62b0	669	{
<>	128:9bcdf88f62b0	670	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
<>	128:9bcdf88f62b0	671	Mode);
<>	128:9bcdf88f62b0	672	}
<>	128:9bcdf88f62b0	673
<>	128:9bcdf88f62b0	674	/**
<>	128:9bcdf88f62b0	675	* @brief Get DMA mode circular or normal.
<>	128:9bcdf88f62b0	676	* @rmtoll CCR CIRC LL_DMA_GetMode
<>	128:9bcdf88f62b0	677	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	678	* @param Channel This parameter can be one of the following values:
<>	128:9bcdf88f62b0	679	* @arg @ref LL_DMA_CHANNEL_1
<>	128:9bcdf88f62b0	680	* @arg @ref LL_DMA_CHANNEL_2
<>	128:9bcdf88f62b0	681	* @arg @ref LL_DMA_CHANNEL_3
<>	128:9bcdf88f62b0	682	* @arg @ref LL_DMA_CHANNEL_4
<>	128:9bcdf88f62b0	683	* @arg @ref LL_DMA_CHANNEL_5
<>	128:9bcdf88f62b0	684	* @arg @ref LL_DMA_CHANNEL_6
<>	128:9bcdf88f62b0	685	* @arg @ref LL_DMA_CHANNEL_7
<>	128:9bcdf88f62b0	686	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	687	* @arg @ref LL_DMA_MODE_NORMAL
<>	128:9bcdf88f62b0	688	* @arg @ref LL_DMA_MODE_CIRCULAR
<>	128:9bcdf88f62b0	689	*/
<>	128:9bcdf88f62b0	690	__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
<>	128:9bcdf88f62b0	691	{
<>	128:9bcdf88f62b0	692	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	128:9bcdf88f62b0	693	DMA_CCR_CIRC));
<>	128:9bcdf88f62b0	694	}
<>	128:9bcdf88f62b0	695
<>	128:9bcdf88f62b0	696	/**
<>	128:9bcdf88f62b0	697	* @brief Set Peripheral increment mode.
<>	128:9bcdf88f62b0	698	* @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
<>	128:9bcdf88f62b0	699	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	700	* @param Channel This parameter can be one of the following values:
<>	128:9bcdf88f62b0	701	* @arg @ref LL_DMA_CHANNEL_1
<>	128:9bcdf88f62b0	702	* @arg @ref LL_DMA_CHANNEL_2
<>	128:9bcdf88f62b0	703	* @arg @ref LL_DMA_CHANNEL_3
<>	128:9bcdf88f62b0	704	* @arg @ref LL_DMA_CHANNEL_4
<>	128:9bcdf88f62b0	705	* @arg @ref LL_DMA_CHANNEL_5
<>	128:9bcdf88f62b0	706	* @arg @ref LL_DMA_CHANNEL_6
<>	128:9bcdf88f62b0	707	* @arg @ref LL_DMA_CHANNEL_7
<>	128:9bcdf88f62b0	708	* @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
<>	128:9bcdf88f62b0	709	* @arg @ref LL_DMA_PERIPH_INCREMENT
<>	128:9bcdf88f62b0	710	* @arg @ref LL_DMA_PERIPH_NOINCREMENT
<>	128:9bcdf88f62b0	711	* @retval None
<>	128:9bcdf88f62b0	712	*/
<>	128:9bcdf88f62b0	713	__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
<>	128:9bcdf88f62b0	714	{
<>	128:9bcdf88f62b0	715	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
<>	128:9bcdf88f62b0	716	PeriphOrM2MSrcIncMode);
<>	128:9bcdf88f62b0	717	}
<>	128:9bcdf88f62b0	718
<>	128:9bcdf88f62b0	719	/**
<>	128:9bcdf88f62b0	720	* @brief Get Peripheral increment mode.
<>	128:9bcdf88f62b0	721	* @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
<>	128:9bcdf88f62b0	722	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	723	* @param Channel This parameter can be one of the following values:
<>	128:9bcdf88f62b0	724	* @arg @ref LL_DMA_CHANNEL_1
<>	128:9bcdf88f62b0	725	* @arg @ref LL_DMA_CHANNEL_2
<>	128:9bcdf88f62b0	726	* @arg @ref LL_DMA_CHANNEL_3
<>	128:9bcdf88f62b0	727	* @arg @ref LL_DMA_CHANNEL_4
<>	128:9bcdf88f62b0	728	* @arg @ref LL_DMA_CHANNEL_5
<>	128:9bcdf88f62b0	729	* @arg @ref LL_DMA_CHANNEL_6
<>	128:9bcdf88f62b0	730	* @arg @ref LL_DMA_CHANNEL_7
<>	128:9bcdf88f62b0	731	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	732	* @arg @ref LL_DMA_PERIPH_INCREMENT
<>	128:9bcdf88f62b0	733	* @arg @ref LL_DMA_PERIPH_NOINCREMENT
<>	128:9bcdf88f62b0	734	*/
<>	128:9bcdf88f62b0	735	__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
<>	128:9bcdf88f62b0	736	{
<>	128:9bcdf88f62b0	737	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	128:9bcdf88f62b0	738	DMA_CCR_PINC));
<>	128:9bcdf88f62b0	739	}
<>	128:9bcdf88f62b0	740
<>	128:9bcdf88f62b0	741	/**
<>	128:9bcdf88f62b0	742	* @brief Set Memory increment mode.
<>	128:9bcdf88f62b0	743	* @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
<>	128:9bcdf88f62b0	744	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	745	* @param Channel This parameter can be one of the following values:
<>	128:9bcdf88f62b0	746	* @arg @ref LL_DMA_CHANNEL_1
<>	128:9bcdf88f62b0	747	* @arg @ref LL_DMA_CHANNEL_2
<>	128:9bcdf88f62b0	748	* @arg @ref LL_DMA_CHANNEL_3
<>	128:9bcdf88f62b0	749	* @arg @ref LL_DMA_CHANNEL_4
<>	128:9bcdf88f62b0	750	* @arg @ref LL_DMA_CHANNEL_5
<>	128:9bcdf88f62b0	751	* @arg @ref LL_DMA_CHANNEL_6
<>	128:9bcdf88f62b0	752	* @arg @ref LL_DMA_CHANNEL_7
<>	128:9bcdf88f62b0	753	* @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
<>	128:9bcdf88f62b0	754	* @arg @ref LL_DMA_MEMORY_INCREMENT
<>	128:9bcdf88f62b0	755	* @arg @ref LL_DMA_MEMORY_NOINCREMENT
<>	128:9bcdf88f62b0	756	* @retval None
<>	128:9bcdf88f62b0	757	*/
<>	128:9bcdf88f62b0	758	__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
<>	128:9bcdf88f62b0	759	{
<>	128:9bcdf88f62b0	760	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
<>	128:9bcdf88f62b0	761	MemoryOrM2MDstIncMode);
<>	128:9bcdf88f62b0	762	}
<>	128:9bcdf88f62b0	763
<>	128:9bcdf88f62b0	764	/**
<>	128:9bcdf88f62b0	765	* @brief Get Memory increment mode.
<>	128:9bcdf88f62b0	766	* @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
<>	128:9bcdf88f62b0	767	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	768	* @param Channel This parameter can be one of the following values:
<>	128:9bcdf88f62b0	769	* @arg @ref LL_DMA_CHANNEL_1
<>	128:9bcdf88f62b0	770	* @arg @ref LL_DMA_CHANNEL_2
<>	128:9bcdf88f62b0	771	* @arg @ref LL_DMA_CHANNEL_3
<>	128:9bcdf88f62b0	772	* @arg @ref LL_DMA_CHANNEL_4
<>	128:9bcdf88f62b0	773	* @arg @ref LL_DMA_CHANNEL_5
<>	128:9bcdf88f62b0	774	* @arg @ref LL_DMA_CHANNEL_6
<>	128:9bcdf88f62b0	775	* @arg @ref LL_DMA_CHANNEL_7
<>	128:9bcdf88f62b0	776	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	777	* @arg @ref LL_DMA_MEMORY_INCREMENT
<>	128:9bcdf88f62b0	778	* @arg @ref LL_DMA_MEMORY_NOINCREMENT
<>	128:9bcdf88f62b0	779	*/
<>	128:9bcdf88f62b0	780	__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
<>	128:9bcdf88f62b0	781	{
<>	128:9bcdf88f62b0	782	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	128:9bcdf88f62b0	783	DMA_CCR_MINC));
<>	128:9bcdf88f62b0	784	}
<>	128:9bcdf88f62b0	785
<>	128:9bcdf88f62b0	786	/**
<>	128:9bcdf88f62b0	787	* @brief Set Peripheral size.
<>	128:9bcdf88f62b0	788	* @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
<>	128:9bcdf88f62b0	789	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	790	* @param Channel This parameter can be one of the following values:
<>	128:9bcdf88f62b0	791	* @arg @ref LL_DMA_CHANNEL_1
<>	128:9bcdf88f62b0	792	* @arg @ref LL_DMA_CHANNEL_2
<>	128:9bcdf88f62b0	793	* @arg @ref LL_DMA_CHANNEL_3
<>	128:9bcdf88f62b0	794	* @arg @ref LL_DMA_CHANNEL_4
<>	128:9bcdf88f62b0	795	* @arg @ref LL_DMA_CHANNEL_5
<>	128:9bcdf88f62b0	796	* @arg @ref LL_DMA_CHANNEL_6
<>	128:9bcdf88f62b0	797	* @arg @ref LL_DMA_CHANNEL_7
<>	128:9bcdf88f62b0	798	* @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
<>	128:9bcdf88f62b0	799	* @arg @ref LL_DMA_PDATAALIGN_BYTE
<>	128:9bcdf88f62b0	800	* @arg @ref LL_DMA_PDATAALIGN_HALFWORD
<>	128:9bcdf88f62b0	801	* @arg @ref LL_DMA_PDATAALIGN_WORD
<>	128:9bcdf88f62b0	802	* @retval None
<>	128:9bcdf88f62b0	803	*/
<>	128:9bcdf88f62b0	804	__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
<>	128:9bcdf88f62b0	805	{
<>	128:9bcdf88f62b0	806	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
<>	128:9bcdf88f62b0	807	PeriphOrM2MSrcDataSize);
<>	128:9bcdf88f62b0	808	}
<>	128:9bcdf88f62b0	809
<>	128:9bcdf88f62b0	810	/**
<>	128:9bcdf88f62b0	811	* @brief Get Peripheral size.
<>	128:9bcdf88f62b0	812	* @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
<>	128:9bcdf88f62b0	813	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	814	* @param Channel This parameter can be one of the following values:
<>	128:9bcdf88f62b0	815	* @arg @ref LL_DMA_CHANNEL_1
<>	128:9bcdf88f62b0	816	* @arg @ref LL_DMA_CHANNEL_2
<>	128:9bcdf88f62b0	817	* @arg @ref LL_DMA_CHANNEL_3
<>	128:9bcdf88f62b0	818	* @arg @ref LL_DMA_CHANNEL_4
<>	128:9bcdf88f62b0	819	* @arg @ref LL_DMA_CHANNEL_5
<>	128:9bcdf88f62b0	820	* @arg @ref LL_DMA_CHANNEL_6
<>	128:9bcdf88f62b0	821	* @arg @ref LL_DMA_CHANNEL_7
<>	128:9bcdf88f62b0	822	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	823	* @arg @ref LL_DMA_PDATAALIGN_BYTE
<>	128:9bcdf88f62b0	824	* @arg @ref LL_DMA_PDATAALIGN_HALFWORD
<>	128:9bcdf88f62b0	825	* @arg @ref LL_DMA_PDATAALIGN_WORD
<>	128:9bcdf88f62b0	826	*/
<>	128:9bcdf88f62b0	827	__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
<>	128:9bcdf88f62b0	828	{
<>	128:9bcdf88f62b0	829	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	128:9bcdf88f62b0	830	DMA_CCR_PSIZE));
<>	128:9bcdf88f62b0	831	}
<>	128:9bcdf88f62b0	832
<>	128:9bcdf88f62b0	833	/**
<>	128:9bcdf88f62b0	834	* @brief Set Memory size.
<>	128:9bcdf88f62b0	835	* @rmtoll CCR MSIZE LL_DMA_SetMemorySize
<>	128:9bcdf88f62b0	836	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	837	* @param Channel This parameter can be one of the following values:
<>	128:9bcdf88f62b0	838	* @arg @ref LL_DMA_CHANNEL_1
<>	128:9bcdf88f62b0	839	* @arg @ref LL_DMA_CHANNEL_2
<>	128:9bcdf88f62b0	840	* @arg @ref LL_DMA_CHANNEL_3
<>	128:9bcdf88f62b0	841	* @arg @ref LL_DMA_CHANNEL_4
<>	128:9bcdf88f62b0	842	* @arg @ref LL_DMA_CHANNEL_5
<>	128:9bcdf88f62b0	843	* @arg @ref LL_DMA_CHANNEL_6
<>	128:9bcdf88f62b0	844	* @arg @ref LL_DMA_CHANNEL_7
<>	128:9bcdf88f62b0	845	* @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
<>	128:9bcdf88f62b0	846	* @arg @ref LL_DMA_MDATAALIGN_BYTE
<>	128:9bcdf88f62b0	847	* @arg @ref LL_DMA_MDATAALIGN_HALFWORD
<>	128:9bcdf88f62b0	848	* @arg @ref LL_DMA_MDATAALIGN_WORD
<>	128:9bcdf88f62b0	849	* @retval None
<>	128:9bcdf88f62b0	850	*/
<>	128:9bcdf88f62b0	851	__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
<>	128:9bcdf88f62b0	852	{
<>	128:9bcdf88f62b0	853	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
<>	128:9bcdf88f62b0	854	MemoryOrM2MDstDataSize);
<>	128:9bcdf88f62b0	855	}
<>	128:9bcdf88f62b0	856
<>	128:9bcdf88f62b0	857	/**
<>	128:9bcdf88f62b0	858	* @brief Get Memory size.
<>	128:9bcdf88f62b0	859	* @rmtoll CCR MSIZE LL_DMA_GetMemorySize
<>	128:9bcdf88f62b0	860	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	861	* @param Channel This parameter can be one of the following values:
<>	128:9bcdf88f62b0	862	* @arg @ref LL_DMA_CHANNEL_1
<>	128:9bcdf88f62b0	863	* @arg @ref LL_DMA_CHANNEL_2
<>	128:9bcdf88f62b0	864	* @arg @ref LL_DMA_CHANNEL_3
<>	128:9bcdf88f62b0	865	* @arg @ref LL_DMA_CHANNEL_4
<>	128:9bcdf88f62b0	866	* @arg @ref LL_DMA_CHANNEL_5
<>	128:9bcdf88f62b0	867	* @arg @ref LL_DMA_CHANNEL_6
<>	128:9bcdf88f62b0	868	* @arg @ref LL_DMA_CHANNEL_7
<>	128:9bcdf88f62b0	869	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	870	* @arg @ref LL_DMA_MDATAALIGN_BYTE
<>	128:9bcdf88f62b0	871	* @arg @ref LL_DMA_MDATAALIGN_HALFWORD
<>	128:9bcdf88f62b0	872	* @arg @ref LL_DMA_MDATAALIGN_WORD
<>	128:9bcdf88f62b0	873	*/
<>	128:9bcdf88f62b0	874	__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
<>	128:9bcdf88f62b0	875	{
<>	128:9bcdf88f62b0	876	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	128:9bcdf88f62b0	877	DMA_CCR_MSIZE));
<>	128:9bcdf88f62b0	878	}
<>	128:9bcdf88f62b0	879
<>	128:9bcdf88f62b0	880	/**
<>	128:9bcdf88f62b0	881	* @brief Set Channel priority level.
<>	128:9bcdf88f62b0	882	* @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
<>	128:9bcdf88f62b0	883	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	884	* @param Channel This parameter can be one of the following values:
<>	128:9bcdf88f62b0	885	* @arg @ref LL_DMA_CHANNEL_1
<>	128:9bcdf88f62b0	886	* @arg @ref LL_DMA_CHANNEL_2
<>	128:9bcdf88f62b0	887	* @arg @ref LL_DMA_CHANNEL_3
<>	128:9bcdf88f62b0	888	* @arg @ref LL_DMA_CHANNEL_4
<>	128:9bcdf88f62b0	889	* @arg @ref LL_DMA_CHANNEL_5
<>	128:9bcdf88f62b0	890	* @arg @ref LL_DMA_CHANNEL_6
<>	128:9bcdf88f62b0	891	* @arg @ref LL_DMA_CHANNEL_7
<>	128:9bcdf88f62b0	892	* @param Priority This parameter can be one of the following values:
<>	128:9bcdf88f62b0	893	* @arg @ref LL_DMA_PRIORITY_LOW
<>	128:9bcdf88f62b0	894	* @arg @ref LL_DMA_PRIORITY_MEDIUM
<>	128:9bcdf88f62b0	895	* @arg @ref LL_DMA_PRIORITY_HIGH
<>	128:9bcdf88f62b0	896	* @arg @ref LL_DMA_PRIORITY_VERYHIGH
<>	128:9bcdf88f62b0	897	* @retval None
<>	128:9bcdf88f62b0	898	*/
<>	128:9bcdf88f62b0	899	__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
<>	128:9bcdf88f62b0	900	{
<>	128:9bcdf88f62b0	901	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
<>	128:9bcdf88f62b0	902	Priority);
<>	128:9bcdf88f62b0	903	}
<>	128:9bcdf88f62b0	904
<>	128:9bcdf88f62b0	905	/**
<>	128:9bcdf88f62b0	906	* @brief Get Channel priority level.
<>	128:9bcdf88f62b0	907	* @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
<>	128:9bcdf88f62b0	908	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	909	* @param Channel This parameter can be one of the following values:
<>	128:9bcdf88f62b0	910	* @arg @ref LL_DMA_CHANNEL_1
<>	128:9bcdf88f62b0	911	* @arg @ref LL_DMA_CHANNEL_2
<>	128:9bcdf88f62b0	912	* @arg @ref LL_DMA_CHANNEL_3
<>	128:9bcdf88f62b0	913	* @arg @ref LL_DMA_CHANNEL_4
<>	128:9bcdf88f62b0	914	* @arg @ref LL_DMA_CHANNEL_5
<>	128:9bcdf88f62b0	915	* @arg @ref LL_DMA_CHANNEL_6
<>	128:9bcdf88f62b0	916	* @arg @ref LL_DMA_CHANNEL_7
<>	128:9bcdf88f62b0	917	* @retval Returned value can be one of the following values:
<>	128:9bcdf88f62b0	918	* @arg @ref LL_DMA_PRIORITY_LOW
<>	128:9bcdf88f62b0	919	* @arg @ref LL_DMA_PRIORITY_MEDIUM
<>	128:9bcdf88f62b0	920	* @arg @ref LL_DMA_PRIORITY_HIGH
<>	128:9bcdf88f62b0	921	* @arg @ref LL_DMA_PRIORITY_VERYHIGH
<>	128:9bcdf88f62b0	922	*/
<>	128:9bcdf88f62b0	923	__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
<>	128:9bcdf88f62b0	924	{
<>	128:9bcdf88f62b0	925	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	128:9bcdf88f62b0	926	DMA_CCR_PL));
<>	128:9bcdf88f62b0	927	}
<>	128:9bcdf88f62b0	928
<>	128:9bcdf88f62b0	929	/**
<>	128:9bcdf88f62b0	930	* @brief Set Number of data to transfer.
<>	128:9bcdf88f62b0	931	* @note This action has no effect if
<>	128:9bcdf88f62b0	932	* channel is enabled.
<>	128:9bcdf88f62b0	933	* @rmtoll CNDTR NDT LL_DMA_SetDataLength
<>	128:9bcdf88f62b0	934	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	935	* @param Channel This parameter can be one of the following values:
<>	128:9bcdf88f62b0	936	* @arg @ref LL_DMA_CHANNEL_1
<>	128:9bcdf88f62b0	937	* @arg @ref LL_DMA_CHANNEL_2
<>	128:9bcdf88f62b0	938	* @arg @ref LL_DMA_CHANNEL_3
<>	128:9bcdf88f62b0	939	* @arg @ref LL_DMA_CHANNEL_4
<>	128:9bcdf88f62b0	940	* @arg @ref LL_DMA_CHANNEL_5
<>	128:9bcdf88f62b0	941	* @arg @ref LL_DMA_CHANNEL_6
<>	128:9bcdf88f62b0	942	* @arg @ref LL_DMA_CHANNEL_7
<>	128:9bcdf88f62b0	943	* @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
<>	128:9bcdf88f62b0	944	* @retval None
<>	128:9bcdf88f62b0	945	*/
<>	128:9bcdf88f62b0	946	__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
<>	128:9bcdf88f62b0	947	{
<>	128:9bcdf88f62b0	948	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
<>	128:9bcdf88f62b0	949	DMA_CNDTR_NDT, NbData);
<>	128:9bcdf88f62b0	950	}
<>	128:9bcdf88f62b0	951
<>	128:9bcdf88f62b0	952	/**
<>	128:9bcdf88f62b0	953	* @brief Get Number of data to transfer.
<>	128:9bcdf88f62b0	954	* @note Once the channel is enabled, the return value indicate the
<>	128:9bcdf88f62b0	955	* remaining bytes to be transmitted.
<>	128:9bcdf88f62b0	956	* @rmtoll CNDTR NDT LL_DMA_GetDataLength
<>	128:9bcdf88f62b0	957	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	958	* @param Channel This parameter can be one of the following values:
<>	128:9bcdf88f62b0	959	* @arg @ref LL_DMA_CHANNEL_1
<>	128:9bcdf88f62b0	960	* @arg @ref LL_DMA_CHANNEL_2
<>	128:9bcdf88f62b0	961	* @arg @ref LL_DMA_CHANNEL_3
<>	128:9bcdf88f62b0	962	* @arg @ref LL_DMA_CHANNEL_4
<>	128:9bcdf88f62b0	963	* @arg @ref LL_DMA_CHANNEL_5
<>	128:9bcdf88f62b0	964	* @arg @ref LL_DMA_CHANNEL_6
<>	128:9bcdf88f62b0	965	* @arg @ref LL_DMA_CHANNEL_7
<>	128:9bcdf88f62b0	966	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	128:9bcdf88f62b0	967	*/
<>	128:9bcdf88f62b0	968	__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
<>	128:9bcdf88f62b0	969	{
<>	128:9bcdf88f62b0	970	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
<>	128:9bcdf88f62b0	971	DMA_CNDTR_NDT));
<>	128:9bcdf88f62b0	972	}
<>	128:9bcdf88f62b0	973
<>	128:9bcdf88f62b0	974	/**
<>	128:9bcdf88f62b0	975	* @brief Configure the Source and Destination addresses.
<>	128:9bcdf88f62b0	976	* @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr)
<>	128:9bcdf88f62b0	977	* @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
<>	128:9bcdf88f62b0	978	* CMAR MA LL_DMA_ConfigAddresses
<>	128:9bcdf88f62b0	979	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	980	* @param Channel This parameter can be one of the following values:
<>	128:9bcdf88f62b0	981	* @arg @ref LL_DMA_CHANNEL_1
<>	128:9bcdf88f62b0	982	* @arg @ref LL_DMA_CHANNEL_2
<>	128:9bcdf88f62b0	983	* @arg @ref LL_DMA_CHANNEL_3
<>	128:9bcdf88f62b0	984	* @arg @ref LL_DMA_CHANNEL_4
<>	128:9bcdf88f62b0	985	* @arg @ref LL_DMA_CHANNEL_5
<>	128:9bcdf88f62b0	986	* @arg @ref LL_DMA_CHANNEL_6
<>	128:9bcdf88f62b0	987	* @arg @ref LL_DMA_CHANNEL_7
<>	128:9bcdf88f62b0	988	* @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	128:9bcdf88f62b0	989	* @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	128:9bcdf88f62b0	990	* @param Direction This parameter can be one of the following values:
<>	128:9bcdf88f62b0	991	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
<>	128:9bcdf88f62b0	992	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
<>	128:9bcdf88f62b0	993	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
<>	128:9bcdf88f62b0	994	* @retval None
<>	128:9bcdf88f62b0	995	*/
<>	128:9bcdf88f62b0	996	__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
<>	128:9bcdf88f62b0	997	uint32_t DstAddress, uint32_t Direction)
<>	128:9bcdf88f62b0	998	{
<>	128:9bcdf88f62b0	999	/* Direction Memory to Periph */
<>	128:9bcdf88f62b0	1000	if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
<>	128:9bcdf88f62b0	1001	{
<>	128:9bcdf88f62b0	1002	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
<>	128:9bcdf88f62b0	1003	SrcAddress);
<>	128:9bcdf88f62b0	1004	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
<>	128:9bcdf88f62b0	1005	DstAddress);
<>	128:9bcdf88f62b0	1006	}
<>	128:9bcdf88f62b0	1007	/* Direction Periph to Memory and Memory to Memory */
<>	128:9bcdf88f62b0	1008	else
<>	128:9bcdf88f62b0	1009	{
<>	128:9bcdf88f62b0	1010	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
<>	128:9bcdf88f62b0	1011	SrcAddress);
<>	128:9bcdf88f62b0	1012	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
<>	128:9bcdf88f62b0	1013	DstAddress);
<>	128:9bcdf88f62b0	1014	}
<>	128:9bcdf88f62b0	1015	}
<>	128:9bcdf88f62b0	1016
<>	128:9bcdf88f62b0	1017	/**
<>	128:9bcdf88f62b0	1018	* @brief Set the Memory address.
<>	128:9bcdf88f62b0	1019	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
<>	128:9bcdf88f62b0	1020	* @rmtoll CMAR MA LL_DMA_SetMemoryAddress
<>	128:9bcdf88f62b0	1021	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1022	* @param Channel This parameter can be one of the following values:
<>	128:9bcdf88f62b0	1023	* @arg @ref LL_DMA_CHANNEL_1
<>	128:9bcdf88f62b0	1024	* @arg @ref LL_DMA_CHANNEL_2
<>	128:9bcdf88f62b0	1025	* @arg @ref LL_DMA_CHANNEL_3
<>	128:9bcdf88f62b0	1026	* @arg @ref LL_DMA_CHANNEL_4
<>	128:9bcdf88f62b0	1027	* @arg @ref LL_DMA_CHANNEL_5
<>	128:9bcdf88f62b0	1028	* @arg @ref LL_DMA_CHANNEL_6
<>	128:9bcdf88f62b0	1029	* @arg @ref LL_DMA_CHANNEL_7
<>	128:9bcdf88f62b0	1030	* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	128:9bcdf88f62b0	1031	* @retval None
<>	128:9bcdf88f62b0	1032	*/
<>	128:9bcdf88f62b0	1033	__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
<>	128:9bcdf88f62b0	1034	{
<>	128:9bcdf88f62b0	1035	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
<>	128:9bcdf88f62b0	1036	MemoryAddress);
<>	128:9bcdf88f62b0	1037	}
<>	128:9bcdf88f62b0	1038
<>	128:9bcdf88f62b0	1039	/**
<>	128:9bcdf88f62b0	1040	* @brief Set the Peripheral address.
<>	128:9bcdf88f62b0	1041	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
<>	128:9bcdf88f62b0	1042	* @rmtoll CPAR PA LL_DMA_SetPeriphAddress
<>	128:9bcdf88f62b0	1043	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1044	* @param Channel This parameter can be one of the following values:
<>	128:9bcdf88f62b0	1045	* @arg @ref LL_DMA_CHANNEL_1
<>	128:9bcdf88f62b0	1046	* @arg @ref LL_DMA_CHANNEL_2
<>	128:9bcdf88f62b0	1047	* @arg @ref LL_DMA_CHANNEL_3
<>	128:9bcdf88f62b0	1048	* @arg @ref LL_DMA_CHANNEL_4
<>	128:9bcdf88f62b0	1049	* @arg @ref LL_DMA_CHANNEL_5
<>	128:9bcdf88f62b0	1050	* @arg @ref LL_DMA_CHANNEL_6
<>	128:9bcdf88f62b0	1051	* @arg @ref LL_DMA_CHANNEL_7
<>	128:9bcdf88f62b0	1052	* @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	128:9bcdf88f62b0	1053	* @retval None
<>	128:9bcdf88f62b0	1054	*/
<>	128:9bcdf88f62b0	1055	__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
<>	128:9bcdf88f62b0	1056	{
<>	128:9bcdf88f62b0	1057	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
<>	128:9bcdf88f62b0	1058	PeriphAddress);
<>	128:9bcdf88f62b0	1059	}
<>	128:9bcdf88f62b0	1060
<>	128:9bcdf88f62b0	1061	/**
<>	128:9bcdf88f62b0	1062	* @brief Get Memory address.
<>	128:9bcdf88f62b0	1063	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
<>	128:9bcdf88f62b0	1064	* @rmtoll CMAR MA LL_DMA_GetMemoryAddress
<>	128:9bcdf88f62b0	1065	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1066	* @param Channel This parameter can be one of the following values:
<>	128:9bcdf88f62b0	1067	* @arg @ref LL_DMA_CHANNEL_1
<>	128:9bcdf88f62b0	1068	* @arg @ref LL_DMA_CHANNEL_2
<>	128:9bcdf88f62b0	1069	* @arg @ref LL_DMA_CHANNEL_3
<>	128:9bcdf88f62b0	1070	* @arg @ref LL_DMA_CHANNEL_4
<>	128:9bcdf88f62b0	1071	* @arg @ref LL_DMA_CHANNEL_5
<>	128:9bcdf88f62b0	1072	* @arg @ref LL_DMA_CHANNEL_6
<>	128:9bcdf88f62b0	1073	* @arg @ref LL_DMA_CHANNEL_7
<>	128:9bcdf88f62b0	1074	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	128:9bcdf88f62b0	1075	*/
<>	128:9bcdf88f62b0	1076	__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
<>	128:9bcdf88f62b0	1077	{
<>	128:9bcdf88f62b0	1078	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR,
<>	128:9bcdf88f62b0	1079	DMA_CMAR_MA));
<>	128:9bcdf88f62b0	1080	}
<>	128:9bcdf88f62b0	1081
<>	128:9bcdf88f62b0	1082	/**
<>	128:9bcdf88f62b0	1083	* @brief Get Peripheral address.
<>	128:9bcdf88f62b0	1084	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
<>	128:9bcdf88f62b0	1085	* @rmtoll CPAR PA LL_DMA_GetPeriphAddress
<>	128:9bcdf88f62b0	1086	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1087	* @param Channel This parameter can be one of the following values:
<>	128:9bcdf88f62b0	1088	* @arg @ref LL_DMA_CHANNEL_1
<>	128:9bcdf88f62b0	1089	* @arg @ref LL_DMA_CHANNEL_2
<>	128:9bcdf88f62b0	1090	* @arg @ref LL_DMA_CHANNEL_3
<>	128:9bcdf88f62b0	1091	* @arg @ref LL_DMA_CHANNEL_4
<>	128:9bcdf88f62b0	1092	* @arg @ref LL_DMA_CHANNEL_5
<>	128:9bcdf88f62b0	1093	* @arg @ref LL_DMA_CHANNEL_6
<>	128:9bcdf88f62b0	1094	* @arg @ref LL_DMA_CHANNEL_7
<>	128:9bcdf88f62b0	1095	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	128:9bcdf88f62b0	1096	*/
<>	128:9bcdf88f62b0	1097	__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
<>	128:9bcdf88f62b0	1098	{
<>	128:9bcdf88f62b0	1099	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR,
<>	128:9bcdf88f62b0	1100	DMA_CPAR_PA));
<>	128:9bcdf88f62b0	1101	}
<>	128:9bcdf88f62b0	1102
<>	128:9bcdf88f62b0	1103	/**
<>	128:9bcdf88f62b0	1104	* @brief Set the Memory to Memory Source address.
<>	128:9bcdf88f62b0	1105	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
<>	128:9bcdf88f62b0	1106	* @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
<>	128:9bcdf88f62b0	1107	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1108	* @param Channel This parameter can be one of the following values:
<>	128:9bcdf88f62b0	1109	* @arg @ref LL_DMA_CHANNEL_1
<>	128:9bcdf88f62b0	1110	* @arg @ref LL_DMA_CHANNEL_2
<>	128:9bcdf88f62b0	1111	* @arg @ref LL_DMA_CHANNEL_3
<>	128:9bcdf88f62b0	1112	* @arg @ref LL_DMA_CHANNEL_4
<>	128:9bcdf88f62b0	1113	* @arg @ref LL_DMA_CHANNEL_5
<>	128:9bcdf88f62b0	1114	* @arg @ref LL_DMA_CHANNEL_6
<>	128:9bcdf88f62b0	1115	* @arg @ref LL_DMA_CHANNEL_7
<>	128:9bcdf88f62b0	1116	* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	128:9bcdf88f62b0	1117	* @retval None
<>	128:9bcdf88f62b0	1118	*/
<>	128:9bcdf88f62b0	1119	__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
<>	128:9bcdf88f62b0	1120	{
<>	128:9bcdf88f62b0	1121	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
<>	128:9bcdf88f62b0	1122	MemoryAddress);
<>	128:9bcdf88f62b0	1123	}
<>	128:9bcdf88f62b0	1124
<>	128:9bcdf88f62b0	1125	/**
<>	128:9bcdf88f62b0	1126	* @brief Set the Memory to Memory Destination address.
<>	128:9bcdf88f62b0	1127	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
<>	128:9bcdf88f62b0	1128	* @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
<>	128:9bcdf88f62b0	1129	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1130	* @param Channel This parameter can be one of the following values:
<>	128:9bcdf88f62b0	1131	* @arg @ref LL_DMA_CHANNEL_1
<>	128:9bcdf88f62b0	1132	* @arg @ref LL_DMA_CHANNEL_2
<>	128:9bcdf88f62b0	1133	* @arg @ref LL_DMA_CHANNEL_3
<>	128:9bcdf88f62b0	1134	* @arg @ref LL_DMA_CHANNEL_4
<>	128:9bcdf88f62b0	1135	* @arg @ref LL_DMA_CHANNEL_5
<>	128:9bcdf88f62b0	1136	* @arg @ref LL_DMA_CHANNEL_6
<>	128:9bcdf88f62b0	1137	* @arg @ref LL_DMA_CHANNEL_7
<>	128:9bcdf88f62b0	1138	* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	128:9bcdf88f62b0	1139	* @retval None
<>	128:9bcdf88f62b0	1140	*/
<>	128:9bcdf88f62b0	1141	__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
<>	128:9bcdf88f62b0	1142	{
<>	128:9bcdf88f62b0	1143	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
<>	128:9bcdf88f62b0	1144	MemoryAddress);
<>	128:9bcdf88f62b0	1145	}
<>	128:9bcdf88f62b0	1146
<>	128:9bcdf88f62b0	1147	/**
<>	128:9bcdf88f62b0	1148	* @brief Get the Memory to Memory Source address.
<>	128:9bcdf88f62b0	1149	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
<>	128:9bcdf88f62b0	1150	* @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
<>	128:9bcdf88f62b0	1151	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1152	* @param Channel This parameter can be one of the following values:
<>	128:9bcdf88f62b0	1153	* @arg @ref LL_DMA_CHANNEL_1
<>	128:9bcdf88f62b0	1154	* @arg @ref LL_DMA_CHANNEL_2
<>	128:9bcdf88f62b0	1155	* @arg @ref LL_DMA_CHANNEL_3
<>	128:9bcdf88f62b0	1156	* @arg @ref LL_DMA_CHANNEL_4
<>	128:9bcdf88f62b0	1157	* @arg @ref LL_DMA_CHANNEL_5
<>	128:9bcdf88f62b0	1158	* @arg @ref LL_DMA_CHANNEL_6
<>	128:9bcdf88f62b0	1159	* @arg @ref LL_DMA_CHANNEL_7
<>	128:9bcdf88f62b0	1160	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	128:9bcdf88f62b0	1161	*/
<>	128:9bcdf88f62b0	1162	__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
<>	128:9bcdf88f62b0	1163	{
<>	128:9bcdf88f62b0	1164	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR,
<>	128:9bcdf88f62b0	1165	DMA_CPAR_PA));
<>	128:9bcdf88f62b0	1166	}
<>	128:9bcdf88f62b0	1167
<>	128:9bcdf88f62b0	1168	/**
<>	128:9bcdf88f62b0	1169	* @brief Get the Memory to Memory Destination address.
<>	128:9bcdf88f62b0	1170	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
<>	128:9bcdf88f62b0	1171	* @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
<>	128:9bcdf88f62b0	1172	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1173	* @param Channel This parameter can be one of the following values:
<>	128:9bcdf88f62b0	1174	* @arg @ref LL_DMA_CHANNEL_1
<>	128:9bcdf88f62b0	1175	* @arg @ref LL_DMA_CHANNEL_2
<>	128:9bcdf88f62b0	1176	* @arg @ref LL_DMA_CHANNEL_3
<>	128:9bcdf88f62b0	1177	* @arg @ref LL_DMA_CHANNEL_4
<>	128:9bcdf88f62b0	1178	* @arg @ref LL_DMA_CHANNEL_5
<>	128:9bcdf88f62b0	1179	* @arg @ref LL_DMA_CHANNEL_6
<>	128:9bcdf88f62b0	1180	* @arg @ref LL_DMA_CHANNEL_7
<>	128:9bcdf88f62b0	1181	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<>	128:9bcdf88f62b0	1182	*/
<>	128:9bcdf88f62b0	1183	__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
<>	128:9bcdf88f62b0	1184	{
<>	128:9bcdf88f62b0	1185	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR,
<>	128:9bcdf88f62b0	1186	DMA_CMAR_MA));
<>	128:9bcdf88f62b0	1187	}
<>	128:9bcdf88f62b0	1188
<>	128:9bcdf88f62b0	1189
<>	128:9bcdf88f62b0	1190	/**
<>	128:9bcdf88f62b0	1191	* @}
<>	128:9bcdf88f62b0	1192	*/
<>	128:9bcdf88f62b0	1193
<>	128:9bcdf88f62b0	1194	/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
<>	128:9bcdf88f62b0	1195	* @{
<>	128:9bcdf88f62b0	1196	*/
<>	128:9bcdf88f62b0	1197
<>	128:9bcdf88f62b0	1198	/**
<>	128:9bcdf88f62b0	1199	* @brief Get Channel 1 global interrupt flag.
<>	128:9bcdf88f62b0	1200	* @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
<>	128:9bcdf88f62b0	1201	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1202	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1203	*/
<>	128:9bcdf88f62b0	1204	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1205	{
<>	128:9bcdf88f62b0	1206	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1));
<>	128:9bcdf88f62b0	1207	}
<>	128:9bcdf88f62b0	1208
<>	128:9bcdf88f62b0	1209	/**
<>	128:9bcdf88f62b0	1210	* @brief Get Channel 2 global interrupt flag.
<>	128:9bcdf88f62b0	1211	* @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
<>	128:9bcdf88f62b0	1212	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1213	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1214	*/
<>	128:9bcdf88f62b0	1215	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1216	{
<>	128:9bcdf88f62b0	1217	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2));
<>	128:9bcdf88f62b0	1218	}
<>	128:9bcdf88f62b0	1219
<>	128:9bcdf88f62b0	1220	/**
<>	128:9bcdf88f62b0	1221	* @brief Get Channel 3 global interrupt flag.
<>	128:9bcdf88f62b0	1222	* @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
<>	128:9bcdf88f62b0	1223	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1224	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1225	*/
<>	128:9bcdf88f62b0	1226	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1227	{
<>	128:9bcdf88f62b0	1228	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3));
<>	128:9bcdf88f62b0	1229	}
<>	128:9bcdf88f62b0	1230
<>	128:9bcdf88f62b0	1231	/**
<>	128:9bcdf88f62b0	1232	* @brief Get Channel 4 global interrupt flag.
<>	128:9bcdf88f62b0	1233	* @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
<>	128:9bcdf88f62b0	1234	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1235	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1236	*/
<>	128:9bcdf88f62b0	1237	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1238	{
<>	128:9bcdf88f62b0	1239	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4));
<>	128:9bcdf88f62b0	1240	}
<>	128:9bcdf88f62b0	1241
<>	128:9bcdf88f62b0	1242	/**
<>	128:9bcdf88f62b0	1243	* @brief Get Channel 5 global interrupt flag.
<>	128:9bcdf88f62b0	1244	* @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
<>	128:9bcdf88f62b0	1245	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1246	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1247	*/
<>	128:9bcdf88f62b0	1248	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1249	{
<>	128:9bcdf88f62b0	1250	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5));
<>	128:9bcdf88f62b0	1251	}
<>	128:9bcdf88f62b0	1252
<>	128:9bcdf88f62b0	1253	/**
<>	128:9bcdf88f62b0	1254	* @brief Get Channel 6 global interrupt flag.
<>	128:9bcdf88f62b0	1255	* @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
<>	128:9bcdf88f62b0	1256	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1257	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1258	*/
<>	128:9bcdf88f62b0	1259	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1260	{
<>	128:9bcdf88f62b0	1261	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6));
<>	128:9bcdf88f62b0	1262	}
<>	128:9bcdf88f62b0	1263
<>	128:9bcdf88f62b0	1264	/**
<>	128:9bcdf88f62b0	1265	* @brief Get Channel 7 global interrupt flag.
<>	128:9bcdf88f62b0	1266	* @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
<>	128:9bcdf88f62b0	1267	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1268	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1269	*/
<>	128:9bcdf88f62b0	1270	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1271	{
<>	128:9bcdf88f62b0	1272	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7));
<>	128:9bcdf88f62b0	1273	}
<>	128:9bcdf88f62b0	1274
<>	128:9bcdf88f62b0	1275	/**
<>	128:9bcdf88f62b0	1276	* @brief Get Channel 1 transfer complete flag.
<>	128:9bcdf88f62b0	1277	* @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
<>	128:9bcdf88f62b0	1278	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1279	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1280	*/
<>	128:9bcdf88f62b0	1281	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1282	{
<>	128:9bcdf88f62b0	1283	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1));
<>	128:9bcdf88f62b0	1284	}
<>	128:9bcdf88f62b0	1285
<>	128:9bcdf88f62b0	1286	/**
<>	128:9bcdf88f62b0	1287	* @brief Get Channel 2 transfer complete flag.
<>	128:9bcdf88f62b0	1288	* @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
<>	128:9bcdf88f62b0	1289	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1290	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1291	*/
<>	128:9bcdf88f62b0	1292	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1293	{
<>	128:9bcdf88f62b0	1294	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2));
<>	128:9bcdf88f62b0	1295	}
<>	128:9bcdf88f62b0	1296
<>	128:9bcdf88f62b0	1297	/**
<>	128:9bcdf88f62b0	1298	* @brief Get Channel 3 transfer complete flag.
<>	128:9bcdf88f62b0	1299	* @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
<>	128:9bcdf88f62b0	1300	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1301	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1302	*/
<>	128:9bcdf88f62b0	1303	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1304	{
<>	128:9bcdf88f62b0	1305	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3));
<>	128:9bcdf88f62b0	1306	}
<>	128:9bcdf88f62b0	1307
<>	128:9bcdf88f62b0	1308	/**
<>	128:9bcdf88f62b0	1309	* @brief Get Channel 4 transfer complete flag.
<>	128:9bcdf88f62b0	1310	* @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
<>	128:9bcdf88f62b0	1311	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1312	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1313	*/
<>	128:9bcdf88f62b0	1314	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1315	{
<>	128:9bcdf88f62b0	1316	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4));
<>	128:9bcdf88f62b0	1317	}
<>	128:9bcdf88f62b0	1318
<>	128:9bcdf88f62b0	1319	/**
<>	128:9bcdf88f62b0	1320	* @brief Get Channel 5 transfer complete flag.
<>	128:9bcdf88f62b0	1321	* @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
<>	128:9bcdf88f62b0	1322	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1323	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1324	*/
<>	128:9bcdf88f62b0	1325	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1326	{
<>	128:9bcdf88f62b0	1327	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5));
<>	128:9bcdf88f62b0	1328	}
<>	128:9bcdf88f62b0	1329
<>	128:9bcdf88f62b0	1330	/**
<>	128:9bcdf88f62b0	1331	* @brief Get Channel 6 transfer complete flag.
<>	128:9bcdf88f62b0	1332	* @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
<>	128:9bcdf88f62b0	1333	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1334	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1335	*/
<>	128:9bcdf88f62b0	1336	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1337	{
<>	128:9bcdf88f62b0	1338	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6));
<>	128:9bcdf88f62b0	1339	}
<>	128:9bcdf88f62b0	1340
<>	128:9bcdf88f62b0	1341	/**
<>	128:9bcdf88f62b0	1342	* @brief Get Channel 7 transfer complete flag.
<>	128:9bcdf88f62b0	1343	* @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
<>	128:9bcdf88f62b0	1344	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1345	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1346	*/
<>	128:9bcdf88f62b0	1347	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1348	{
<>	128:9bcdf88f62b0	1349	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7));
<>	128:9bcdf88f62b0	1350	}
<>	128:9bcdf88f62b0	1351
<>	128:9bcdf88f62b0	1352	/**
<>	128:9bcdf88f62b0	1353	* @brief Get Channel 1 half transfer flag.
<>	128:9bcdf88f62b0	1354	* @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
<>	128:9bcdf88f62b0	1355	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1356	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1357	*/
<>	128:9bcdf88f62b0	1358	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1359	{
<>	128:9bcdf88f62b0	1360	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1));
<>	128:9bcdf88f62b0	1361	}
<>	128:9bcdf88f62b0	1362
<>	128:9bcdf88f62b0	1363	/**
<>	128:9bcdf88f62b0	1364	* @brief Get Channel 2 half transfer flag.
<>	128:9bcdf88f62b0	1365	* @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
<>	128:9bcdf88f62b0	1366	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1367	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1368	*/
<>	128:9bcdf88f62b0	1369	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1370	{
<>	128:9bcdf88f62b0	1371	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2));
<>	128:9bcdf88f62b0	1372	}
<>	128:9bcdf88f62b0	1373
<>	128:9bcdf88f62b0	1374	/**
<>	128:9bcdf88f62b0	1375	* @brief Get Channel 3 half transfer flag.
<>	128:9bcdf88f62b0	1376	* @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
<>	128:9bcdf88f62b0	1377	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1378	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1379	*/
<>	128:9bcdf88f62b0	1380	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1381	{
<>	128:9bcdf88f62b0	1382	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3));
<>	128:9bcdf88f62b0	1383	}
<>	128:9bcdf88f62b0	1384
<>	128:9bcdf88f62b0	1385	/**
<>	128:9bcdf88f62b0	1386	* @brief Get Channel 4 half transfer flag.
<>	128:9bcdf88f62b0	1387	* @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
<>	128:9bcdf88f62b0	1388	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1389	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1390	*/
<>	128:9bcdf88f62b0	1391	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1392	{
<>	128:9bcdf88f62b0	1393	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4));
<>	128:9bcdf88f62b0	1394	}
<>	128:9bcdf88f62b0	1395
<>	128:9bcdf88f62b0	1396	/**
<>	128:9bcdf88f62b0	1397	* @brief Get Channel 5 half transfer flag.
<>	128:9bcdf88f62b0	1398	* @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
<>	128:9bcdf88f62b0	1399	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1400	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1401	*/
<>	128:9bcdf88f62b0	1402	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1403	{
<>	128:9bcdf88f62b0	1404	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5));
<>	128:9bcdf88f62b0	1405	}
<>	128:9bcdf88f62b0	1406
<>	128:9bcdf88f62b0	1407	/**
<>	128:9bcdf88f62b0	1408	* @brief Get Channel 6 half transfer flag.
<>	128:9bcdf88f62b0	1409	* @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
<>	128:9bcdf88f62b0	1410	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1411	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1412	*/
<>	128:9bcdf88f62b0	1413	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1414	{
<>	128:9bcdf88f62b0	1415	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6));
<>	128:9bcdf88f62b0	1416	}
<>	128:9bcdf88f62b0	1417
<>	128:9bcdf88f62b0	1418	/**
<>	128:9bcdf88f62b0	1419	* @brief Get Channel 7 half transfer flag.
<>	128:9bcdf88f62b0	1420	* @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
<>	128:9bcdf88f62b0	1421	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1422	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1423	*/
<>	128:9bcdf88f62b0	1424	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1425	{
<>	128:9bcdf88f62b0	1426	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7));
<>	128:9bcdf88f62b0	1427	}
<>	128:9bcdf88f62b0	1428
<>	128:9bcdf88f62b0	1429	/**
<>	128:9bcdf88f62b0	1430	* @brief Get Channel 1 transfer error flag.
<>	128:9bcdf88f62b0	1431	* @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
<>	128:9bcdf88f62b0	1432	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1433	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1434	*/
<>	128:9bcdf88f62b0	1435	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1436	{
<>	128:9bcdf88f62b0	1437	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1));
<>	128:9bcdf88f62b0	1438	}
<>	128:9bcdf88f62b0	1439
<>	128:9bcdf88f62b0	1440	/**
<>	128:9bcdf88f62b0	1441	* @brief Get Channel 2 transfer error flag.
<>	128:9bcdf88f62b0	1442	* @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
<>	128:9bcdf88f62b0	1443	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1444	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1445	*/
<>	128:9bcdf88f62b0	1446	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1447	{
<>	128:9bcdf88f62b0	1448	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2));
<>	128:9bcdf88f62b0	1449	}
<>	128:9bcdf88f62b0	1450
<>	128:9bcdf88f62b0	1451	/**
<>	128:9bcdf88f62b0	1452	* @brief Get Channel 3 transfer error flag.
<>	128:9bcdf88f62b0	1453	* @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
<>	128:9bcdf88f62b0	1454	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1455	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1456	*/
<>	128:9bcdf88f62b0	1457	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1458	{
<>	128:9bcdf88f62b0	1459	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3));
<>	128:9bcdf88f62b0	1460	}
<>	128:9bcdf88f62b0	1461
<>	128:9bcdf88f62b0	1462	/**
<>	128:9bcdf88f62b0	1463	* @brief Get Channel 4 transfer error flag.
<>	128:9bcdf88f62b0	1464	* @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
<>	128:9bcdf88f62b0	1465	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1466	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1467	*/
<>	128:9bcdf88f62b0	1468	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1469	{
<>	128:9bcdf88f62b0	1470	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4));
<>	128:9bcdf88f62b0	1471	}
<>	128:9bcdf88f62b0	1472
<>	128:9bcdf88f62b0	1473	/**
<>	128:9bcdf88f62b0	1474	* @brief Get Channel 5 transfer error flag.
<>	128:9bcdf88f62b0	1475	* @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
<>	128:9bcdf88f62b0	1476	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1477	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1478	*/
<>	128:9bcdf88f62b0	1479	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1480	{
<>	128:9bcdf88f62b0	1481	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5));
<>	128:9bcdf88f62b0	1482	}
<>	128:9bcdf88f62b0	1483
<>	128:9bcdf88f62b0	1484	/**
<>	128:9bcdf88f62b0	1485	* @brief Get Channel 6 transfer error flag.
<>	128:9bcdf88f62b0	1486	* @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
<>	128:9bcdf88f62b0	1487	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1488	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1489	*/
<>	128:9bcdf88f62b0	1490	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1491	{
<>	128:9bcdf88f62b0	1492	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6));
<>	128:9bcdf88f62b0	1493	}
<>	128:9bcdf88f62b0	1494
<>	128:9bcdf88f62b0	1495	/**
<>	128:9bcdf88f62b0	1496	* @brief Get Channel 7 transfer error flag.
<>	128:9bcdf88f62b0	1497	* @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
<>	128:9bcdf88f62b0	1498	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1499	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1500	*/
<>	128:9bcdf88f62b0	1501	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1502	{
<>	128:9bcdf88f62b0	1503	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7));
<>	128:9bcdf88f62b0	1504	}
<>	128:9bcdf88f62b0	1505
<>	128:9bcdf88f62b0	1506	/**
<>	128:9bcdf88f62b0	1507	* @brief Clear Channel 1 global interrupt flag.
<>	128:9bcdf88f62b0	1508	* @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
<>	128:9bcdf88f62b0	1509	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1510	* @retval None
<>	128:9bcdf88f62b0	1511	*/
<>	128:9bcdf88f62b0	1512	__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1513	{
<>	128:9bcdf88f62b0	1514	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF1);
<>	128:9bcdf88f62b0	1515	}
<>	128:9bcdf88f62b0	1516
<>	128:9bcdf88f62b0	1517	/**
<>	128:9bcdf88f62b0	1518	* @brief Clear Channel 2 global interrupt flag.
<>	128:9bcdf88f62b0	1519	* @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
<>	128:9bcdf88f62b0	1520	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1521	* @retval None
<>	128:9bcdf88f62b0	1522	*/
<>	128:9bcdf88f62b0	1523	__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1524	{
<>	128:9bcdf88f62b0	1525	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF2);
<>	128:9bcdf88f62b0	1526	}
<>	128:9bcdf88f62b0	1527
<>	128:9bcdf88f62b0	1528	/**
<>	128:9bcdf88f62b0	1529	* @brief Clear Channel 3 global interrupt flag.
<>	128:9bcdf88f62b0	1530	* @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
<>	128:9bcdf88f62b0	1531	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1532	* @retval None
<>	128:9bcdf88f62b0	1533	*/
<>	128:9bcdf88f62b0	1534	__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1535	{
<>	128:9bcdf88f62b0	1536	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF3);
<>	128:9bcdf88f62b0	1537	}
<>	128:9bcdf88f62b0	1538
<>	128:9bcdf88f62b0	1539	/**
<>	128:9bcdf88f62b0	1540	* @brief Clear Channel 4 global interrupt flag.
<>	128:9bcdf88f62b0	1541	* @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
<>	128:9bcdf88f62b0	1542	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1543	* @retval None
<>	128:9bcdf88f62b0	1544	*/
<>	128:9bcdf88f62b0	1545	__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1546	{
<>	128:9bcdf88f62b0	1547	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF4);
<>	128:9bcdf88f62b0	1548	}
<>	128:9bcdf88f62b0	1549
<>	128:9bcdf88f62b0	1550	/**
<>	128:9bcdf88f62b0	1551	* @brief Clear Channel 5 global interrupt flag.
<>	128:9bcdf88f62b0	1552	* @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
<>	128:9bcdf88f62b0	1553	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1554	* @retval None
<>	128:9bcdf88f62b0	1555	*/
<>	128:9bcdf88f62b0	1556	__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1557	{
<>	128:9bcdf88f62b0	1558	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF5);
<>	128:9bcdf88f62b0	1559	}
<>	128:9bcdf88f62b0	1560
<>	128:9bcdf88f62b0	1561	/**
<>	128:9bcdf88f62b0	1562	* @brief Clear Channel 6 global interrupt flag.
<>	128:9bcdf88f62b0	1563	* @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
<>	128:9bcdf88f62b0	1564	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1565	* @retval None
<>	128:9bcdf88f62b0	1566	*/
<>	128:9bcdf88f62b0	1567	__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1568	{
<>	128:9bcdf88f62b0	1569	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF6);
<>	128:9bcdf88f62b0	1570	}
<>	128:9bcdf88f62b0	1571
<>	128:9bcdf88f62b0	1572	/**
<>	128:9bcdf88f62b0	1573	* @brief Clear Channel 7 global interrupt flag.
<>	128:9bcdf88f62b0	1574	* @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
<>	128:9bcdf88f62b0	1575	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1576	* @retval None
<>	128:9bcdf88f62b0	1577	*/
<>	128:9bcdf88f62b0	1578	__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1579	{
<>	128:9bcdf88f62b0	1580	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF7);
<>	128:9bcdf88f62b0	1581	}
<>	128:9bcdf88f62b0	1582
<>	128:9bcdf88f62b0	1583	/**
<>	128:9bcdf88f62b0	1584	* @brief Clear Channel 1 transfer complete flag.
<>	128:9bcdf88f62b0	1585	* @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
<>	128:9bcdf88f62b0	1586	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1587	* @retval None
<>	128:9bcdf88f62b0	1588	*/
<>	128:9bcdf88f62b0	1589	__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1590	{
<>	128:9bcdf88f62b0	1591	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF1);
<>	128:9bcdf88f62b0	1592	}
<>	128:9bcdf88f62b0	1593
<>	128:9bcdf88f62b0	1594	/**
<>	128:9bcdf88f62b0	1595	* @brief Clear Channel 2 transfer complete flag.
<>	128:9bcdf88f62b0	1596	* @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
<>	128:9bcdf88f62b0	1597	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1598	* @retval None
<>	128:9bcdf88f62b0	1599	*/
<>	128:9bcdf88f62b0	1600	__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1601	{
<>	128:9bcdf88f62b0	1602	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF2);
<>	128:9bcdf88f62b0	1603	}
<>	128:9bcdf88f62b0	1604
<>	128:9bcdf88f62b0	1605	/**
<>	128:9bcdf88f62b0	1606	* @brief Clear Channel 3 transfer complete flag.
<>	128:9bcdf88f62b0	1607	* @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
<>	128:9bcdf88f62b0	1608	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1609	* @retval None
<>	128:9bcdf88f62b0	1610	*/
<>	128:9bcdf88f62b0	1611	__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1612	{
<>	128:9bcdf88f62b0	1613	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF3);
<>	128:9bcdf88f62b0	1614	}
<>	128:9bcdf88f62b0	1615
<>	128:9bcdf88f62b0	1616	/**
<>	128:9bcdf88f62b0	1617	* @brief Clear Channel 4 transfer complete flag.
<>	128:9bcdf88f62b0	1618	* @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
<>	128:9bcdf88f62b0	1619	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1620	* @retval None
<>	128:9bcdf88f62b0	1621	*/
<>	128:9bcdf88f62b0	1622	__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1623	{
<>	128:9bcdf88f62b0	1624	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF4);
<>	128:9bcdf88f62b0	1625	}
<>	128:9bcdf88f62b0	1626
<>	128:9bcdf88f62b0	1627	/**
<>	128:9bcdf88f62b0	1628	* @brief Clear Channel 5 transfer complete flag.
<>	128:9bcdf88f62b0	1629	* @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
<>	128:9bcdf88f62b0	1630	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1631	* @retval None
<>	128:9bcdf88f62b0	1632	*/
<>	128:9bcdf88f62b0	1633	__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1634	{
<>	128:9bcdf88f62b0	1635	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF5);
<>	128:9bcdf88f62b0	1636	}
<>	128:9bcdf88f62b0	1637
<>	128:9bcdf88f62b0	1638	/**
<>	128:9bcdf88f62b0	1639	* @brief Clear Channel 6 transfer complete flag.
<>	128:9bcdf88f62b0	1640	* @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
<>	128:9bcdf88f62b0	1641	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1642	* @retval None
<>	128:9bcdf88f62b0	1643	*/
<>	128:9bcdf88f62b0	1644	__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1645	{
<>	128:9bcdf88f62b0	1646	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF6);
<>	128:9bcdf88f62b0	1647	}
<>	128:9bcdf88f62b0	1648
<>	128:9bcdf88f62b0	1649	/**
<>	128:9bcdf88f62b0	1650	* @brief Clear Channel 7 transfer complete flag.
<>	128:9bcdf88f62b0	1651	* @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
<>	128:9bcdf88f62b0	1652	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1653	* @retval None
<>	128:9bcdf88f62b0	1654	*/
<>	128:9bcdf88f62b0	1655	__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1656	{
<>	128:9bcdf88f62b0	1657	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF7);
<>	128:9bcdf88f62b0	1658	}
<>	128:9bcdf88f62b0	1659
<>	128:9bcdf88f62b0	1660	/**
<>	128:9bcdf88f62b0	1661	* @brief Clear Channel 1 half transfer flag.
<>	128:9bcdf88f62b0	1662	* @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
<>	128:9bcdf88f62b0	1663	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1664	* @retval None
<>	128:9bcdf88f62b0	1665	*/
<>	128:9bcdf88f62b0	1666	__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1667	{
<>	128:9bcdf88f62b0	1668	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF1);
<>	128:9bcdf88f62b0	1669	}
<>	128:9bcdf88f62b0	1670
<>	128:9bcdf88f62b0	1671	/**
<>	128:9bcdf88f62b0	1672	* @brief Clear Channel 2 half transfer flag.
<>	128:9bcdf88f62b0	1673	* @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
<>	128:9bcdf88f62b0	1674	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1675	* @retval None
<>	128:9bcdf88f62b0	1676	*/
<>	128:9bcdf88f62b0	1677	__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1678	{
<>	128:9bcdf88f62b0	1679	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF2);
<>	128:9bcdf88f62b0	1680	}
<>	128:9bcdf88f62b0	1681
<>	128:9bcdf88f62b0	1682	/**
<>	128:9bcdf88f62b0	1683	* @brief Clear Channel 3 half transfer flag.
<>	128:9bcdf88f62b0	1684	* @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
<>	128:9bcdf88f62b0	1685	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1686	* @retval None
<>	128:9bcdf88f62b0	1687	*/
<>	128:9bcdf88f62b0	1688	__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1689	{
<>	128:9bcdf88f62b0	1690	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF3);
<>	128:9bcdf88f62b0	1691	}
<>	128:9bcdf88f62b0	1692
<>	128:9bcdf88f62b0	1693	/**
<>	128:9bcdf88f62b0	1694	* @brief Clear Channel 4 half transfer flag.
<>	128:9bcdf88f62b0	1695	* @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
<>	128:9bcdf88f62b0	1696	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1697	* @retval None
<>	128:9bcdf88f62b0	1698	*/
<>	128:9bcdf88f62b0	1699	__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1700	{
<>	128:9bcdf88f62b0	1701	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF4);
<>	128:9bcdf88f62b0	1702	}
<>	128:9bcdf88f62b0	1703
<>	128:9bcdf88f62b0	1704	/**
<>	128:9bcdf88f62b0	1705	* @brief Clear Channel 5 half transfer flag.
<>	128:9bcdf88f62b0	1706	* @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
<>	128:9bcdf88f62b0	1707	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1708	* @retval None
<>	128:9bcdf88f62b0	1709	*/
<>	128:9bcdf88f62b0	1710	__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1711	{
<>	128:9bcdf88f62b0	1712	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF5);
<>	128:9bcdf88f62b0	1713	}
<>	128:9bcdf88f62b0	1714
<>	128:9bcdf88f62b0	1715	/**
<>	128:9bcdf88f62b0	1716	* @brief Clear Channel 6 half transfer flag.
<>	128:9bcdf88f62b0	1717	* @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
<>	128:9bcdf88f62b0	1718	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1719	* @retval None
<>	128:9bcdf88f62b0	1720	*/
<>	128:9bcdf88f62b0	1721	__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1722	{
<>	128:9bcdf88f62b0	1723	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF6);
<>	128:9bcdf88f62b0	1724	}
<>	128:9bcdf88f62b0	1725
<>	128:9bcdf88f62b0	1726	/**
<>	128:9bcdf88f62b0	1727	* @brief Clear Channel 7 half transfer flag.
<>	128:9bcdf88f62b0	1728	* @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
<>	128:9bcdf88f62b0	1729	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1730	* @retval None
<>	128:9bcdf88f62b0	1731	*/
<>	128:9bcdf88f62b0	1732	__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1733	{
<>	128:9bcdf88f62b0	1734	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF7);
<>	128:9bcdf88f62b0	1735	}
<>	128:9bcdf88f62b0	1736
<>	128:9bcdf88f62b0	1737	/**
<>	128:9bcdf88f62b0	1738	* @brief Clear Channel 1 transfer error flag.
<>	128:9bcdf88f62b0	1739	* @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
<>	128:9bcdf88f62b0	1740	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1741	* @retval None
<>	128:9bcdf88f62b0	1742	*/
<>	128:9bcdf88f62b0	1743	__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1744	{
<>	128:9bcdf88f62b0	1745	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF1);
<>	128:9bcdf88f62b0	1746	}
<>	128:9bcdf88f62b0	1747
<>	128:9bcdf88f62b0	1748	/**
<>	128:9bcdf88f62b0	1749	* @brief Clear Channel 2 transfer error flag.
<>	128:9bcdf88f62b0	1750	* @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
<>	128:9bcdf88f62b0	1751	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1752	* @retval None
<>	128:9bcdf88f62b0	1753	*/
<>	128:9bcdf88f62b0	1754	__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1755	{
<>	128:9bcdf88f62b0	1756	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF2);
<>	128:9bcdf88f62b0	1757	}
<>	128:9bcdf88f62b0	1758
<>	128:9bcdf88f62b0	1759	/**
<>	128:9bcdf88f62b0	1760	* @brief Clear Channel 3 transfer error flag.
<>	128:9bcdf88f62b0	1761	* @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
<>	128:9bcdf88f62b0	1762	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1763	* @retval None
<>	128:9bcdf88f62b0	1764	*/
<>	128:9bcdf88f62b0	1765	__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1766	{
<>	128:9bcdf88f62b0	1767	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF3);
<>	128:9bcdf88f62b0	1768	}
<>	128:9bcdf88f62b0	1769
<>	128:9bcdf88f62b0	1770	/**
<>	128:9bcdf88f62b0	1771	* @brief Clear Channel 4 transfer error flag.
<>	128:9bcdf88f62b0	1772	* @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
<>	128:9bcdf88f62b0	1773	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1774	* @retval None
<>	128:9bcdf88f62b0	1775	*/
<>	128:9bcdf88f62b0	1776	__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1777	{
<>	128:9bcdf88f62b0	1778	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF4);
<>	128:9bcdf88f62b0	1779	}
<>	128:9bcdf88f62b0	1780
<>	128:9bcdf88f62b0	1781	/**
<>	128:9bcdf88f62b0	1782	* @brief Clear Channel 5 transfer error flag.
<>	128:9bcdf88f62b0	1783	* @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
<>	128:9bcdf88f62b0	1784	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1785	* @retval None
<>	128:9bcdf88f62b0	1786	*/
<>	128:9bcdf88f62b0	1787	__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1788	{
<>	128:9bcdf88f62b0	1789	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF5);
<>	128:9bcdf88f62b0	1790	}
<>	128:9bcdf88f62b0	1791
<>	128:9bcdf88f62b0	1792	/**
<>	128:9bcdf88f62b0	1793	* @brief Clear Channel 6 transfer error flag.
<>	128:9bcdf88f62b0	1794	* @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
<>	128:9bcdf88f62b0	1795	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1796	* @retval None
<>	128:9bcdf88f62b0	1797	*/
<>	128:9bcdf88f62b0	1798	__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1799	{
<>	128:9bcdf88f62b0	1800	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF6);
<>	128:9bcdf88f62b0	1801	}
<>	128:9bcdf88f62b0	1802
<>	128:9bcdf88f62b0	1803	/**
<>	128:9bcdf88f62b0	1804	* @brief Clear Channel 7 transfer error flag.
<>	128:9bcdf88f62b0	1805	* @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
<>	128:9bcdf88f62b0	1806	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1807	* @retval None
<>	128:9bcdf88f62b0	1808	*/
<>	128:9bcdf88f62b0	1809	__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
<>	128:9bcdf88f62b0	1810	{
<>	128:9bcdf88f62b0	1811	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF7);
<>	128:9bcdf88f62b0	1812	}
<>	128:9bcdf88f62b0	1813
<>	128:9bcdf88f62b0	1814	/**
<>	128:9bcdf88f62b0	1815	* @}
<>	128:9bcdf88f62b0	1816	*/
<>	128:9bcdf88f62b0	1817
<>	128:9bcdf88f62b0	1818	/** @defgroup DMA_LL_EF_IT_Management IT_Management
<>	128:9bcdf88f62b0	1819	* @{
<>	128:9bcdf88f62b0	1820	*/
<>	128:9bcdf88f62b0	1821	/**
<>	128:9bcdf88f62b0	1822	* @brief Enable Transfer complete interrupt.
<>	128:9bcdf88f62b0	1823	* @rmtoll CCR TCIE LL_DMA_EnableIT_TC
<>	128:9bcdf88f62b0	1824	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1825	* @param Channel This parameter can be one of the following values:
<>	128:9bcdf88f62b0	1826	* @arg @ref LL_DMA_CHANNEL_1
<>	128:9bcdf88f62b0	1827	* @arg @ref LL_DMA_CHANNEL_2
<>	128:9bcdf88f62b0	1828	* @arg @ref LL_DMA_CHANNEL_3
<>	128:9bcdf88f62b0	1829	* @arg @ref LL_DMA_CHANNEL_4
<>	128:9bcdf88f62b0	1830	* @arg @ref LL_DMA_CHANNEL_5
<>	128:9bcdf88f62b0	1831	* @arg @ref LL_DMA_CHANNEL_6
<>	128:9bcdf88f62b0	1832	* @arg @ref LL_DMA_CHANNEL_7
<>	128:9bcdf88f62b0	1833	* @retval None
<>	128:9bcdf88f62b0	1834	*/
<>	128:9bcdf88f62b0	1835	__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
<>	128:9bcdf88f62b0	1836	{
<>	128:9bcdf88f62b0	1837	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
<>	128:9bcdf88f62b0	1838	}
<>	128:9bcdf88f62b0	1839
<>	128:9bcdf88f62b0	1840	/**
<>	128:9bcdf88f62b0	1841	* @brief Enable Half transfer interrupt.
<>	128:9bcdf88f62b0	1842	* @rmtoll CCR HTIE LL_DMA_EnableIT_HT
<>	128:9bcdf88f62b0	1843	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1844	* @param Channel This parameter can be one of the following values:
<>	128:9bcdf88f62b0	1845	* @arg @ref LL_DMA_CHANNEL_1
<>	128:9bcdf88f62b0	1846	* @arg @ref LL_DMA_CHANNEL_2
<>	128:9bcdf88f62b0	1847	* @arg @ref LL_DMA_CHANNEL_3
<>	128:9bcdf88f62b0	1848	* @arg @ref LL_DMA_CHANNEL_4
<>	128:9bcdf88f62b0	1849	* @arg @ref LL_DMA_CHANNEL_5
<>	128:9bcdf88f62b0	1850	* @arg @ref LL_DMA_CHANNEL_6
<>	128:9bcdf88f62b0	1851	* @arg @ref LL_DMA_CHANNEL_7
<>	128:9bcdf88f62b0	1852	* @retval None
<>	128:9bcdf88f62b0	1853	*/
<>	128:9bcdf88f62b0	1854	__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
<>	128:9bcdf88f62b0	1855	{
<>	128:9bcdf88f62b0	1856	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
<>	128:9bcdf88f62b0	1857	}
<>	128:9bcdf88f62b0	1858
<>	128:9bcdf88f62b0	1859	/**
<>	128:9bcdf88f62b0	1860	* @brief Enable Transfer error interrupt.
<>	128:9bcdf88f62b0	1861	* @rmtoll CCR TEIE LL_DMA_EnableIT_TE
<>	128:9bcdf88f62b0	1862	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1863	* @param Channel This parameter can be one of the following values:
<>	128:9bcdf88f62b0	1864	* @arg @ref LL_DMA_CHANNEL_1
<>	128:9bcdf88f62b0	1865	* @arg @ref LL_DMA_CHANNEL_2
<>	128:9bcdf88f62b0	1866	* @arg @ref LL_DMA_CHANNEL_3
<>	128:9bcdf88f62b0	1867	* @arg @ref LL_DMA_CHANNEL_4
<>	128:9bcdf88f62b0	1868	* @arg @ref LL_DMA_CHANNEL_5
<>	128:9bcdf88f62b0	1869	* @arg @ref LL_DMA_CHANNEL_6
<>	128:9bcdf88f62b0	1870	* @arg @ref LL_DMA_CHANNEL_7
<>	128:9bcdf88f62b0	1871	* @retval None
<>	128:9bcdf88f62b0	1872	*/
<>	128:9bcdf88f62b0	1873	__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
<>	128:9bcdf88f62b0	1874	{
<>	128:9bcdf88f62b0	1875	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
<>	128:9bcdf88f62b0	1876	}
<>	128:9bcdf88f62b0	1877
<>	128:9bcdf88f62b0	1878	/**
<>	128:9bcdf88f62b0	1879	* @brief Disable Transfer complete interrupt.
<>	128:9bcdf88f62b0	1880	* @rmtoll CCR TCIE LL_DMA_DisableIT_TC
<>	128:9bcdf88f62b0	1881	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1882	* @param Channel This parameter can be one of the following values:
<>	128:9bcdf88f62b0	1883	* @arg @ref LL_DMA_CHANNEL_1
<>	128:9bcdf88f62b0	1884	* @arg @ref LL_DMA_CHANNEL_2
<>	128:9bcdf88f62b0	1885	* @arg @ref LL_DMA_CHANNEL_3
<>	128:9bcdf88f62b0	1886	* @arg @ref LL_DMA_CHANNEL_4
<>	128:9bcdf88f62b0	1887	* @arg @ref LL_DMA_CHANNEL_5
<>	128:9bcdf88f62b0	1888	* @arg @ref LL_DMA_CHANNEL_6
<>	128:9bcdf88f62b0	1889	* @arg @ref LL_DMA_CHANNEL_7
<>	128:9bcdf88f62b0	1890	* @retval None
<>	128:9bcdf88f62b0	1891	*/
<>	128:9bcdf88f62b0	1892	__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
<>	128:9bcdf88f62b0	1893	{
<>	128:9bcdf88f62b0	1894	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
<>	128:9bcdf88f62b0	1895	}
<>	128:9bcdf88f62b0	1896
<>	128:9bcdf88f62b0	1897	/**
<>	128:9bcdf88f62b0	1898	* @brief Disable Half transfer interrupt.
<>	128:9bcdf88f62b0	1899	* @rmtoll CCR HTIE LL_DMA_DisableIT_HT
<>	128:9bcdf88f62b0	1900	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1901	* @param Channel This parameter can be one of the following values:
<>	128:9bcdf88f62b0	1902	* @arg @ref LL_DMA_CHANNEL_1
<>	128:9bcdf88f62b0	1903	* @arg @ref LL_DMA_CHANNEL_2
<>	128:9bcdf88f62b0	1904	* @arg @ref LL_DMA_CHANNEL_3
<>	128:9bcdf88f62b0	1905	* @arg @ref LL_DMA_CHANNEL_4
<>	128:9bcdf88f62b0	1906	* @arg @ref LL_DMA_CHANNEL_5
<>	128:9bcdf88f62b0	1907	* @arg @ref LL_DMA_CHANNEL_6
<>	128:9bcdf88f62b0	1908	* @arg @ref LL_DMA_CHANNEL_7
<>	128:9bcdf88f62b0	1909	* @retval None
<>	128:9bcdf88f62b0	1910	*/
<>	128:9bcdf88f62b0	1911	__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
<>	128:9bcdf88f62b0	1912	{
<>	128:9bcdf88f62b0	1913	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
<>	128:9bcdf88f62b0	1914	}
<>	128:9bcdf88f62b0	1915
<>	128:9bcdf88f62b0	1916	/**
<>	128:9bcdf88f62b0	1917	* @brief Disable Transfer error interrupt.
<>	128:9bcdf88f62b0	1918	* @rmtoll CCR TEIE LL_DMA_DisableIT_TE
<>	128:9bcdf88f62b0	1919	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1920	* @param Channel This parameter can be one of the following values:
<>	128:9bcdf88f62b0	1921	* @arg @ref LL_DMA_CHANNEL_1
<>	128:9bcdf88f62b0	1922	* @arg @ref LL_DMA_CHANNEL_2
<>	128:9bcdf88f62b0	1923	* @arg @ref LL_DMA_CHANNEL_3
<>	128:9bcdf88f62b0	1924	* @arg @ref LL_DMA_CHANNEL_4
<>	128:9bcdf88f62b0	1925	* @arg @ref LL_DMA_CHANNEL_5
<>	128:9bcdf88f62b0	1926	* @arg @ref LL_DMA_CHANNEL_6
<>	128:9bcdf88f62b0	1927	* @arg @ref LL_DMA_CHANNEL_7
<>	128:9bcdf88f62b0	1928	* @retval None
<>	128:9bcdf88f62b0	1929	*/
<>	128:9bcdf88f62b0	1930	__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
<>	128:9bcdf88f62b0	1931	{
<>	128:9bcdf88f62b0	1932	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
<>	128:9bcdf88f62b0	1933	}
<>	128:9bcdf88f62b0	1934
<>	128:9bcdf88f62b0	1935	/**
<>	128:9bcdf88f62b0	1936	* @brief Check if Transfer complete Interrupt is enabled.
<>	128:9bcdf88f62b0	1937	* @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
<>	128:9bcdf88f62b0	1938	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1939	* @param Channel This parameter can be one of the following values:
<>	128:9bcdf88f62b0	1940	* @arg @ref LL_DMA_CHANNEL_1
<>	128:9bcdf88f62b0	1941	* @arg @ref LL_DMA_CHANNEL_2
<>	128:9bcdf88f62b0	1942	* @arg @ref LL_DMA_CHANNEL_3
<>	128:9bcdf88f62b0	1943	* @arg @ref LL_DMA_CHANNEL_4
<>	128:9bcdf88f62b0	1944	* @arg @ref LL_DMA_CHANNEL_5
<>	128:9bcdf88f62b0	1945	* @arg @ref LL_DMA_CHANNEL_6
<>	128:9bcdf88f62b0	1946	* @arg @ref LL_DMA_CHANNEL_7
<>	128:9bcdf88f62b0	1947	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1948	*/
<>	128:9bcdf88f62b0	1949	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
<>	128:9bcdf88f62b0	1950	{
<>	128:9bcdf88f62b0	1951	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	128:9bcdf88f62b0	1952	DMA_CCR_TCIE) == (DMA_CCR_TCIE));
<>	128:9bcdf88f62b0	1953	}
<>	128:9bcdf88f62b0	1954
<>	128:9bcdf88f62b0	1955	/**
<>	128:9bcdf88f62b0	1956	* @brief Check if Half transfer Interrupt is enabled.
<>	128:9bcdf88f62b0	1957	* @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
<>	128:9bcdf88f62b0	1958	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1959	* @param Channel This parameter can be one of the following values:
<>	128:9bcdf88f62b0	1960	* @arg @ref LL_DMA_CHANNEL_1
<>	128:9bcdf88f62b0	1961	* @arg @ref LL_DMA_CHANNEL_2
<>	128:9bcdf88f62b0	1962	* @arg @ref LL_DMA_CHANNEL_3
<>	128:9bcdf88f62b0	1963	* @arg @ref LL_DMA_CHANNEL_4
<>	128:9bcdf88f62b0	1964	* @arg @ref LL_DMA_CHANNEL_5
<>	128:9bcdf88f62b0	1965	* @arg @ref LL_DMA_CHANNEL_6
<>	128:9bcdf88f62b0	1966	* @arg @ref LL_DMA_CHANNEL_7
<>	128:9bcdf88f62b0	1967	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1968	*/
<>	128:9bcdf88f62b0	1969	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
<>	128:9bcdf88f62b0	1970	{
<>	128:9bcdf88f62b0	1971	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	128:9bcdf88f62b0	1972	DMA_CCR_HTIE) == (DMA_CCR_HTIE));
<>	128:9bcdf88f62b0	1973	}
<>	128:9bcdf88f62b0	1974
<>	128:9bcdf88f62b0	1975	/**
<>	128:9bcdf88f62b0	1976	* @brief Check if Transfer error Interrupt is enabled.
<>	128:9bcdf88f62b0	1977	* @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
<>	128:9bcdf88f62b0	1978	* @param DMAx DMAx Instance
<>	128:9bcdf88f62b0	1979	* @param Channel This parameter can be one of the following values:
<>	128:9bcdf88f62b0	1980	* @arg @ref LL_DMA_CHANNEL_1
<>	128:9bcdf88f62b0	1981	* @arg @ref LL_DMA_CHANNEL_2
<>	128:9bcdf88f62b0	1982	* @arg @ref LL_DMA_CHANNEL_3
<>	128:9bcdf88f62b0	1983	* @arg @ref LL_DMA_CHANNEL_4
<>	128:9bcdf88f62b0	1984	* @arg @ref LL_DMA_CHANNEL_5
<>	128:9bcdf88f62b0	1985	* @arg @ref LL_DMA_CHANNEL_6
<>	128:9bcdf88f62b0	1986	* @arg @ref LL_DMA_CHANNEL_7
<>	128:9bcdf88f62b0	1987	* @retval State of bit (1 or 0).
<>	128:9bcdf88f62b0	1988	*/
<>	128:9bcdf88f62b0	1989	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
<>	128:9bcdf88f62b0	1990	{
<>	128:9bcdf88f62b0	1991	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<>	128:9bcdf88f62b0	1992	DMA_CCR_TEIE) == (DMA_CCR_TEIE));
<>	128:9bcdf88f62b0	1993	}
<>	128:9bcdf88f62b0	1994
<>	128:9bcdf88f62b0	1995	/**
<>	128:9bcdf88f62b0	1996	* @}
<>	128:9bcdf88f62b0	1997	*/
<>	128:9bcdf88f62b0	1998
<>	128:9bcdf88f62b0	1999	#if defined(USE_FULL_LL_DRIVER)
<>	128:9bcdf88f62b0	2000	/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
<>	128:9bcdf88f62b0	2001	* @{
<>	128:9bcdf88f62b0	2002	*/
<>	128:9bcdf88f62b0	2003
<>	128:9bcdf88f62b0	2004	uint32_t LL_DMA_Init(DMA_TypeDef DMAx, uint32_t Channel, LL_DMA_InitTypeDef DMA_InitStruct);
<>	128:9bcdf88f62b0	2005	uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
<>	128:9bcdf88f62b0	2006	void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
<>	128:9bcdf88f62b0	2007
<>	128:9bcdf88f62b0	2008	/**
<>	128:9bcdf88f62b0	2009	* @}
<>	128:9bcdf88f62b0	2010	*/
<>	128:9bcdf88f62b0	2011	#endif /* USE_FULL_LL_DRIVER */
<>	128:9bcdf88f62b0	2012
<>	128:9bcdf88f62b0	2013	/**
<>	128:9bcdf88f62b0	2014	* @}
<>	128:9bcdf88f62b0	2015	*/
<>	128:9bcdf88f62b0	2016
<>	128:9bcdf88f62b0	2017	/**
<>	128:9bcdf88f62b0	2018	* @}
<>	128:9bcdf88f62b0	2019	*/
<>	128:9bcdf88f62b0	2020
<>	128:9bcdf88f62b0	2021	#endif /* DMA1 \|\| DMA2 */
<>	128:9bcdf88f62b0	2022
<>	128:9bcdf88f62b0	2023	/**
<>	128:9bcdf88f62b0	2024	* @}
<>	128:9bcdf88f62b0	2025	*/
<>	128:9bcdf88f62b0	2026
<>	128:9bcdf88f62b0	2027	#ifdef __cplusplus
<>	128:9bcdf88f62b0	2028	}
<>	128:9bcdf88f62b0	2029	#endif
<>	128:9bcdf88f62b0	2030
<>	128:9bcdf88f62b0	2031	#endif /* __STM32L1xx_LL_DMA_H */
<>	128:9bcdf88f62b0	2032
<>	128:9bcdf88f62b0	2033	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/