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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_MOTE_L152RC/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_adc_ex.h@136:ef9c61f8c49f, 2017-02-14 (annotated)

Committer:
Kojto
Date:
Tue Feb 14 11:24:20 2017 +0000
Revision:
136:ef9c61f8c49f
Parent:
128:9bcdf88f62b0
Child:
165:d1b4690b3f8b
Release 136 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3432: Target STM USBHOST support https://github.com/ARMmbed/mbed-os/pull/3432

3181: NUCLEO_F207ZG extending PeripheralPins.c: all available alternate functions can be used now https://github.com/ARMmbed/mbed-os/pull/3181

3626: NUCLEO_F412ZG : Add USB Device +Host https://github.com/ARMmbed/mbed-os/pull/3626

3628: Fix warnings https://github.com/ARMmbed/mbed-os/pull/3628

3629: STM32: L0 LL layer https://github.com/ARMmbed/mbed-os/pull/3629

3632: IDE Export support for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3632

3642: Missing IRQ pin fix for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3642

3664: Fix ncs36510 sleep definitions https://github.com/ARMmbed/mbed-os/pull/3664

3655: [STM32F4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3655

3657: [STM32L4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3657

3658: [STM32F3] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3658

3685: STM32: I2C: reset state machine https://github.com/ARMmbed/mbed-os/pull/3685

3692: uVisor: Standardize available legacy heap and stack https://github.com/ARMmbed/mbed-os/pull/3692

3621: Fix for #2884, LPC824: export to LPCXpresso, target running with wron https://github.com/ARMmbed/mbed-os/pull/3621

3649: [STM32F7] Modify folder structure  https://github.com/ARMmbed/mbed-os/pull/3649

3695: Enforce device_name is valid in targets.json https://github.com/ARMmbed/mbed-os/pull/3695

3723: NCS36510: spi_format function bug fix https://github.com/ARMmbed/mbed-os/pull/3723

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 /**
<> 128:9bcdf88f62b0 2 ******************************************************************************
<> 128:9bcdf88f62b0 3 * @file stm32l1xx_hal_adc_ex.h
<> 128:9bcdf88f62b0 4 * @author MCD Application Team
<> 128:9bcdf88f62b0 5 * @version V1.2.0
<> 128:9bcdf88f62b0 6 * @date 01-July-2016
<> 128:9bcdf88f62b0 7 * @brief Header file of ADC HAL Extension module.
<> 128:9bcdf88f62b0 8 ******************************************************************************
<> 128:9bcdf88f62b0 9 * @attention
<> 128:9bcdf88f62b0 10 *
<> 128:9bcdf88f62b0 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 128:9bcdf88f62b0 12 *
<> 128:9bcdf88f62b0 13 * Redistribution and use in source and binary forms, with or without modification,
<> 128:9bcdf88f62b0 14 * are permitted provided that the following conditions are met:
<> 128:9bcdf88f62b0 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 128:9bcdf88f62b0 16 * this list of conditions and the following disclaimer.
<> 128:9bcdf88f62b0 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 128:9bcdf88f62b0 18 * this list of conditions and the following disclaimer in the documentation
<> 128:9bcdf88f62b0 19 * and/or other materials provided with the distribution.
<> 128:9bcdf88f62b0 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 128:9bcdf88f62b0 21 * may be used to endorse or promote products derived from this software
<> 128:9bcdf88f62b0 22 * without specific prior written permission.
<> 128:9bcdf88f62b0 23 *
<> 128:9bcdf88f62b0 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 128:9bcdf88f62b0 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 128:9bcdf88f62b0 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 128:9bcdf88f62b0 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 128:9bcdf88f62b0 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 128:9bcdf88f62b0 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 128:9bcdf88f62b0 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 128:9bcdf88f62b0 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 128:9bcdf88f62b0 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 128:9bcdf88f62b0 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 128:9bcdf88f62b0 34 *
<> 128:9bcdf88f62b0 35 ******************************************************************************
<> 128:9bcdf88f62b0 36 */
<> 128:9bcdf88f62b0 37
<> 128:9bcdf88f62b0 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 128:9bcdf88f62b0 39 #ifndef __STM32L1xx_HAL_ADC_EX_H
<> 128:9bcdf88f62b0 40 #define __STM32L1xx_HAL_ADC_EX_H
<> 128:9bcdf88f62b0 41
<> 128:9bcdf88f62b0 42 #ifdef __cplusplus
<> 128:9bcdf88f62b0 43 extern "C" {
<> 128:9bcdf88f62b0 44 #endif
<> 128:9bcdf88f62b0 45
<> 128:9bcdf88f62b0 46 /* Includes ------------------------------------------------------------------*/
<> 128:9bcdf88f62b0 47 #include "stm32l1xx_hal_def.h"
<> 128:9bcdf88f62b0 48
<> 128:9bcdf88f62b0 49 /** @addtogroup STM32L1xx_HAL_Driver
<> 128:9bcdf88f62b0 50 * @{
<> 128:9bcdf88f62b0 51 */
<> 128:9bcdf88f62b0 52
<> 128:9bcdf88f62b0 53 /** @addtogroup ADCEx
<> 128:9bcdf88f62b0 54 * @{
<> 128:9bcdf88f62b0 55 */
<> 128:9bcdf88f62b0 56
<> 128:9bcdf88f62b0 57 /* Exported types ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 58 /** @defgroup ADCEx_Exported_Types ADCEx Exported Types
<> 128:9bcdf88f62b0 59 * @{
<> 128:9bcdf88f62b0 60 */
<> 128:9bcdf88f62b0 61
<> 128:9bcdf88f62b0 62 /**
<> 128:9bcdf88f62b0 63 * @brief ADC Configuration injected Channel structure definition
<> 128:9bcdf88f62b0 64 * @note Parameters of this structure are shared within 2 scopes:
<> 128:9bcdf88f62b0 65 * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset
<> 128:9bcdf88f62b0 66 * - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
<> 128:9bcdf88f62b0 67 * AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.
<> 128:9bcdf88f62b0 68 * @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
<> 128:9bcdf88f62b0 69 * ADC state can be either:
<> 128:9bcdf88f62b0 70 * - For all parameters: ADC disabled
<> 128:9bcdf88f62b0 71 * - For all except parameters 'InjectedDiscontinuousConvMode' and 'AutoInjectedConv': ADC enabled without conversion on going on injected group.
<> 128:9bcdf88f62b0 72 * - For parameters 'ExternalTrigInjecConv' and 'ExternalTrigInjecConvEdge': ADC enabled, even with conversion on going on injected group.
<> 128:9bcdf88f62b0 73 */
<> 128:9bcdf88f62b0 74 typedef struct
<> 128:9bcdf88f62b0 75 {
<> 128:9bcdf88f62b0 76 uint32_t InjectedChannel; /*!< Selection of ADC channel to configure
<> 128:9bcdf88f62b0 77 This parameter can be a value of @ref ADC_channels
<> 128:9bcdf88f62b0 78 Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
<> 128:9bcdf88f62b0 79 uint32_t InjectedRank; /*!< Rank in the injected group sequencer
<> 128:9bcdf88f62b0 80 This parameter must be a value of @ref ADCEx_injected_rank
<> 128:9bcdf88f62b0 81 Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
<> 128:9bcdf88f62b0 82 uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
<> 128:9bcdf88f62b0 83 Unit: ADC clock cycles
<> 128:9bcdf88f62b0 84 Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
<> 128:9bcdf88f62b0 85 This parameter can be a value of @ref ADC_sampling_times
<> 128:9bcdf88f62b0 86 Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
<> 128:9bcdf88f62b0 87 If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
<> 128:9bcdf88f62b0 88 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
<> 128:9bcdf88f62b0 89 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
<> 128:9bcdf88f62b0 90 Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
<> 128:9bcdf88f62b0 91 uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only).
<> 128:9bcdf88f62b0 92 Offset value must be a positive number.
<> 128:9bcdf88f62b0 93 Depending of ADC resolution selected (12, 10, 8 or 6 bits),
<> 128:9bcdf88f62b0 94 this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
<> 128:9bcdf88f62b0 95 uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
<> 128:9bcdf88f62b0 96 To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
<> 128:9bcdf88f62b0 97 This parameter must be a number between Min_Data = 1 and Max_Data = 4.
<> 128:9bcdf88f62b0 98 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
<> 128:9bcdf88f62b0 99 configure a channel on injected group can impact the configuration of other channels previously set. */
<> 128:9bcdf88f62b0 100 uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
<> 128:9bcdf88f62b0 101 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
<> 128:9bcdf88f62b0 102 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
<> 128:9bcdf88f62b0 103 This parameter can be set to ENABLE or DISABLE.
<> 128:9bcdf88f62b0 104 Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.
<> 128:9bcdf88f62b0 105 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
<> 128:9bcdf88f62b0 106 configure a channel on injected group can impact the configuration of other channels previously set. */
<> 128:9bcdf88f62b0 107 uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
<> 128:9bcdf88f62b0 108 This parameter can be set to ENABLE or DISABLE.
<> 128:9bcdf88f62b0 109 Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
<> 128:9bcdf88f62b0 110 Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
<> 128:9bcdf88f62b0 111 Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
<> 128:9bcdf88f62b0 112 To maintain JAUTO always enabled, DMA must be configured in circular mode.
<> 128:9bcdf88f62b0 113 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
<> 128:9bcdf88f62b0 114 configure a channel on injected group can impact the configuration of other channels previously set. */
<> 128:9bcdf88f62b0 115 uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group.
<> 128:9bcdf88f62b0 116 If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.
<> 128:9bcdf88f62b0 117 If set to external trigger source, triggering is on event rising edge.
<> 128:9bcdf88f62b0 118 This parameter can be a value of @ref ADCEx_External_trigger_source_Injected
<> 128:9bcdf88f62b0 119 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
<> 128:9bcdf88f62b0 120 If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly)
<> 128:9bcdf88f62b0 121 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
<> 128:9bcdf88f62b0 122 configure a channel on injected group can impact the configuration of other channels previously set. */
<> 128:9bcdf88f62b0 123 uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group.
<> 128:9bcdf88f62b0 124 This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected.
<> 128:9bcdf88f62b0 125 If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.
<> 128:9bcdf88f62b0 126 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
<> 128:9bcdf88f62b0 127 configure a channel on injected group can impact the configuration of other channels previously set. */
<> 128:9bcdf88f62b0 128 }ADC_InjectionConfTypeDef;
<> 128:9bcdf88f62b0 129 /**
<> 128:9bcdf88f62b0 130 * @}
<> 128:9bcdf88f62b0 131 */
<> 128:9bcdf88f62b0 132
<> 128:9bcdf88f62b0 133
<> 128:9bcdf88f62b0 134 /* Exported constants --------------------------------------------------------*/
<> 128:9bcdf88f62b0 135
<> 128:9bcdf88f62b0 136 /** @defgroup ADCEx_Exported_Constants ADCEx Exported Constants
<> 128:9bcdf88f62b0 137 * @{
<> 128:9bcdf88f62b0 138 */
<> 128:9bcdf88f62b0 139
<> 128:9bcdf88f62b0 140 /** @defgroup ADCEx_injected_rank ADCEx rank into injected group
<> 128:9bcdf88f62b0 141 * @{
<> 128:9bcdf88f62b0 142 */
<> 128:9bcdf88f62b0 143 #define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001)
<> 128:9bcdf88f62b0 144 #define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002)
<> 128:9bcdf88f62b0 145 #define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003)
<> 128:9bcdf88f62b0 146 #define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004)
<> 128:9bcdf88f62b0 147 /**
<> 128:9bcdf88f62b0 148 * @}
<> 128:9bcdf88f62b0 149 */
<> 128:9bcdf88f62b0 150
<> 128:9bcdf88f62b0 151 /** @defgroup ADCEx_External_trigger_edge_Injected ADCEx external trigger enable for injected group
<> 128:9bcdf88f62b0 152 * @{
<> 128:9bcdf88f62b0 153 */
<> 128:9bcdf88f62b0 154 #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE ((uint32_t)0x00000000)
<> 128:9bcdf88f62b0 155 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_CR2_JEXTEN_0)
<> 128:9bcdf88f62b0 156 #define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING ((uint32_t)ADC_CR2_JEXTEN_1)
<> 128:9bcdf88f62b0 157 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING ((uint32_t)ADC_CR2_JEXTEN)
<> 128:9bcdf88f62b0 158 /**
<> 128:9bcdf88f62b0 159 * @}
<> 128:9bcdf88f62b0 160 */
<> 128:9bcdf88f62b0 161
<> 128:9bcdf88f62b0 162 /** @defgroup ADCEx_External_trigger_source_Injected ADCEx External trigger source Injected
<> 128:9bcdf88f62b0 163 * @{
<> 128:9bcdf88f62b0 164 */
<> 128:9bcdf88f62b0 165 /* External triggers for injected groups of ADC1 */
<> 128:9bcdf88f62b0 166 #define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC_EXTERNALTRIGINJEC_T2_CC1
<> 128:9bcdf88f62b0 167 #define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC_EXTERNALTRIGINJEC_T2_TRGO
<> 128:9bcdf88f62b0 168 #define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC_EXTERNALTRIGINJEC_T3_CC4
<> 128:9bcdf88f62b0 169 #define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC_EXTERNALTRIGINJEC_T4_TRGO
<> 128:9bcdf88f62b0 170 #define ADC_EXTERNALTRIGINJECCONV_T4_CC1 ADC_EXTERNALTRIGINJEC_T4_CC1
<> 128:9bcdf88f62b0 171 #define ADC_EXTERNALTRIGINJECCONV_T4_CC2 ADC_EXTERNALTRIGINJEC_T4_CC2
<> 128:9bcdf88f62b0 172 #define ADC_EXTERNALTRIGINJECCONV_T4_CC3 ADC_EXTERNALTRIGINJEC_T4_CC3
<> 128:9bcdf88f62b0 173 #define ADC_EXTERNALTRIGINJECCONV_T7_TRGO ADC_EXTERNALTRIGINJEC_T7_TRGO
<> 128:9bcdf88f62b0 174 #define ADC_EXTERNALTRIGINJECCONV_T9_CC1 ADC_EXTERNALTRIGINJEC_T9_CC1
<> 128:9bcdf88f62b0 175 #define ADC_EXTERNALTRIGINJECCONV_T9_TRGO ADC_EXTERNALTRIGINJEC_T9_TRGO
<> 128:9bcdf88f62b0 176 #define ADC_EXTERNALTRIGINJECCONV_T10_CC1 ADC_EXTERNALTRIGINJEC_T10_CC1
<> 128:9bcdf88f62b0 177 #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC_EXTERNALTRIGINJEC_EXT_IT15
<> 128:9bcdf88f62b0 178 #define ADC_INJECTED_SOFTWARE_START ((uint32_t)0x00000010)
<> 128:9bcdf88f62b0 179 /**
<> 128:9bcdf88f62b0 180 * @}
<> 128:9bcdf88f62b0 181 */
<> 128:9bcdf88f62b0 182
<> 128:9bcdf88f62b0 183 /**
<> 128:9bcdf88f62b0 184 * @}
<> 128:9bcdf88f62b0 185 */
<> 128:9bcdf88f62b0 186
<> 128:9bcdf88f62b0 187
<> 128:9bcdf88f62b0 188 /* Private constants ---------------------------------------------------------*/
<> 128:9bcdf88f62b0 189
<> 128:9bcdf88f62b0 190 /** @addtogroup ADCEx_Private_Constants ADCEx Private Constants
<> 128:9bcdf88f62b0 191 * @{
<> 128:9bcdf88f62b0 192 */
<> 128:9bcdf88f62b0 193
<> 128:9bcdf88f62b0 194 /** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Injected ADCEx Internal HAL driver Ext trig src Injected
<> 128:9bcdf88f62b0 195 * @{
<> 128:9bcdf88f62b0 196 */
<> 128:9bcdf88f62b0 197
<> 128:9bcdf88f62b0 198 /* List of external triggers of injected group for ADC1: */
<> 128:9bcdf88f62b0 199 /* (used internally by HAL driver. To not use into HAL structure parameters) */
<> 128:9bcdf88f62b0 200 #define ADC_EXTERNALTRIGINJEC_T9_CC1 ((uint32_t) 0x00000000)
<> 128:9bcdf88f62b0 201 #define ADC_EXTERNALTRIGINJEC_T9_TRGO ((uint32_t)( ADC_CR2_JEXTSEL_0))
<> 128:9bcdf88f62b0 202 #define ADC_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)( ADC_CR2_JEXTSEL_1 ))
<> 128:9bcdf88f62b0 203 #define ADC_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)( ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
<> 128:9bcdf88f62b0 204 #define ADC_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)( ADC_CR2_JEXTSEL_2 ))
<> 128:9bcdf88f62b0 205 #define ADC_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)( ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
<> 128:9bcdf88f62b0 206 #define ADC_EXTERNALTRIGINJEC_T4_CC1 ((uint32_t)( ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 ))
<> 128:9bcdf88f62b0 207 #define ADC_EXTERNALTRIGINJEC_T4_CC2 ((uint32_t)( ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
<> 128:9bcdf88f62b0 208 #define ADC_EXTERNALTRIGINJEC_T4_CC3 ((uint32_t)(ADC_CR2_JEXTSEL_3 ))
<> 128:9bcdf88f62b0 209 #define ADC_EXTERNALTRIGINJEC_T10_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0))
<> 128:9bcdf88f62b0 210 #define ADC_EXTERNALTRIGINJEC_T7_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 ))
<> 128:9bcdf88f62b0 211 #define ADC_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
<> 128:9bcdf88f62b0 212 /**
<> 128:9bcdf88f62b0 213 * @}
<> 128:9bcdf88f62b0 214 */
<> 128:9bcdf88f62b0 215
<> 128:9bcdf88f62b0 216 /**
<> 128:9bcdf88f62b0 217 * @}
<> 128:9bcdf88f62b0 218 */
<> 128:9bcdf88f62b0 219
<> 128:9bcdf88f62b0 220
<> 128:9bcdf88f62b0 221 /* Exported macro ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 222
<> 128:9bcdf88f62b0 223 /** @defgroup ADCEx_Exported_Macros ADCEx Exported Macros
<> 128:9bcdf88f62b0 224 * @{
<> 128:9bcdf88f62b0 225 */
<> 128:9bcdf88f62b0 226 /* Macro for internal HAL driver usage, and possibly can be used into code of */
<> 128:9bcdf88f62b0 227 /* final user. */
<> 128:9bcdf88f62b0 228
<> 128:9bcdf88f62b0 229 /**
<> 128:9bcdf88f62b0 230 * @brief Selection of channels bank.
<> 128:9bcdf88f62b0 231 * Note: Banks availability depends on devices categories.
<> 128:9bcdf88f62b0 232 * This macro is intended to change bank selection quickly on the fly,
<> 128:9bcdf88f62b0 233 * without going through ADC init structure update and execution of function
<> 128:9bcdf88f62b0 234 * 'HAL_ADC_Init()'.
<> 128:9bcdf88f62b0 235 * @param __HANDLE__: ADC handle
<> 128:9bcdf88f62b0 236 * @param __BANK__: Bank selection. This parameter can be a value of @ref ADC_ChannelsBank.
<> 128:9bcdf88f62b0 237 * @retval None
<> 128:9bcdf88f62b0 238 */
<> 128:9bcdf88f62b0 239 #define __HAL_ADC_CHANNELS_BANK(__HANDLE__, __BANK__) \
<> 128:9bcdf88f62b0 240 MODIFY_REG((__HANDLE__)->Instance->CR2, ADC_CR2_CFG, (__BANK__))
<> 128:9bcdf88f62b0 241
<> 128:9bcdf88f62b0 242 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
<> 128:9bcdf88f62b0 243 /**
<> 128:9bcdf88f62b0 244 * @brief Configures the ADC channels speed.
<> 128:9bcdf88f62b0 245 * Limited to channels 3, 8, 13 and to devices category Cat.3, Cat.4, Cat.5.
<> 128:9bcdf88f62b0 246 * - For ADC_CHANNEL_3: Used as ADC direct channel (fast channel) if OPAMP1 is
<> 128:9bcdf88f62b0 247 * in power down mode.
<> 128:9bcdf88f62b0 248 * - For ADC_CHANNEL_8: Used as ADC direct channel (fast channel) if OPAMP2 is
<> 128:9bcdf88f62b0 249 * in power down mode.
<> 128:9bcdf88f62b0 250 * - For ADC_CHANNEL_13: Used as ADC re-routed channel if OPAMP3 is in
<> 128:9bcdf88f62b0 251 * power down mode. Otherwise, channel 13 is connected to OPAMP3 output and
<> 128:9bcdf88f62b0 252 * routed through switches COMP1_SW1 and VCOMP to ADC switch matrix.
<> 128:9bcdf88f62b0 253 * (Note: OPAMP3 is available on STM32L1 Cat.4 only).
<> 128:9bcdf88f62b0 254 * @param __CHANNEL__: ADC channel
<> 128:9bcdf88f62b0 255 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 256 * @arg ADC_CHANNEL_3: Channel 3 is selected.
<> 128:9bcdf88f62b0 257 * @arg ADC_CHANNEL_8: Channel 8 is selected.
<> 128:9bcdf88f62b0 258 * @arg ADC_CHANNEL_13: Channel 13 is selected.
<> 128:9bcdf88f62b0 259 * @retval None
<> 128:9bcdf88f62b0 260 */
<> 128:9bcdf88f62b0 261 #define __HAL_ADC_CHANNEL_SPEED_FAST(__CHANNEL__) \
<> 128:9bcdf88f62b0 262 ( ( ((__CHANNEL__) == ADC_CHANNEL_3) \
<> 128:9bcdf88f62b0 263 )? \
<> 128:9bcdf88f62b0 264 (SET_BIT(COMP->CSR, COMP_CSR_FCH3)) \
<> 128:9bcdf88f62b0 265 : \
<> 128:9bcdf88f62b0 266 ( ( ((__CHANNEL__) == ADC_CHANNEL_8) \
<> 128:9bcdf88f62b0 267 )? \
<> 128:9bcdf88f62b0 268 (SET_BIT(COMP->CSR, COMP_CSR_FCH8)) \
<> 128:9bcdf88f62b0 269 : \
<> 128:9bcdf88f62b0 270 ( ( ((__CHANNEL__) == ADC_CHANNEL_13) \
<> 128:9bcdf88f62b0 271 )? \
<> 128:9bcdf88f62b0 272 (SET_BIT(COMP->CSR, COMP_CSR_RCH13)) \
<> 128:9bcdf88f62b0 273 : \
<> 128:9bcdf88f62b0 274 (SET_BIT(COMP->CSR, 0x00000000)) \
<> 128:9bcdf88f62b0 275 ) \
<> 128:9bcdf88f62b0 276 ) \
<> 128:9bcdf88f62b0 277 )
<> 128:9bcdf88f62b0 278
<> 128:9bcdf88f62b0 279 #define __HAL_ADC_CHANNEL_SPEED_SLOW(__CHANNEL__) \
<> 128:9bcdf88f62b0 280 ( ( ((__CHANNEL__) == ADC_CHANNEL_3) \
<> 128:9bcdf88f62b0 281 )? \
<> 128:9bcdf88f62b0 282 (CLEAR_BIT(COMP->CSR, COMP_CSR_FCH3)) \
<> 128:9bcdf88f62b0 283 : \
<> 128:9bcdf88f62b0 284 ( ( ((__CHANNEL__) == ADC_CHANNEL_8) \
<> 128:9bcdf88f62b0 285 )? \
<> 128:9bcdf88f62b0 286 (CLEAR_BIT(COMP->CSR, COMP_CSR_FCH8)) \
<> 128:9bcdf88f62b0 287 : \
<> 128:9bcdf88f62b0 288 ( ( ((__CHANNEL__) == ADC_CHANNEL_13) \
<> 128:9bcdf88f62b0 289 )? \
<> 128:9bcdf88f62b0 290 (CLEAR_BIT(COMP->CSR, COMP_CSR_RCH13)) \
<> 128:9bcdf88f62b0 291 : \
<> 128:9bcdf88f62b0 292 (SET_BIT(COMP->CSR, 0x00000000)) \
<> 128:9bcdf88f62b0 293 ) \
<> 128:9bcdf88f62b0 294 ) \
<> 128:9bcdf88f62b0 295 )
<> 128:9bcdf88f62b0 296 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
<> 128:9bcdf88f62b0 297
<> 128:9bcdf88f62b0 298 /**
<> 128:9bcdf88f62b0 299 * @}
<> 128:9bcdf88f62b0 300 */
<> 128:9bcdf88f62b0 301
<> 128:9bcdf88f62b0 302 /* Private macro ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 303
<> 128:9bcdf88f62b0 304 /** @defgroup ADCEx_Private_Macro ADCEx Private Macro
<> 128:9bcdf88f62b0 305 * @{
<> 128:9bcdf88f62b0 306 */
<> 128:9bcdf88f62b0 307 /* Macro reserved for internal HAL driver usage, not intended to be used in */
<> 128:9bcdf88f62b0 308 /* code of final user. */
<> 128:9bcdf88f62b0 309
<> 128:9bcdf88f62b0 310 /**
<> 128:9bcdf88f62b0 311 * @brief Set ADC ranks available in register SQR1.
<> 128:9bcdf88f62b0 312 * Register SQR1 bits availability depends on device category.
<> 128:9bcdf88f62b0 313 * @param _NbrOfConversion_: Regular channel sequence length
<> 128:9bcdf88f62b0 314 * @retval None
<> 128:9bcdf88f62b0 315 */
<> 128:9bcdf88f62b0 316 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
<> 128:9bcdf88f62b0 317 #define __ADC_SQR1_SQXX (ADC_SQR1_SQ28 | ADC_SQR1_SQ27 | ADC_SQR1_SQ26 | ADC_SQR1_SQ25)
<> 128:9bcdf88f62b0 318 #else
<> 128:9bcdf88f62b0 319 #define __ADC_SQR1_SQXX (ADC_SQR1_SQ27 | ADC_SQR1_SQ26 | ADC_SQR1_SQ25)
<> 128:9bcdf88f62b0 320 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
<> 128:9bcdf88f62b0 321
<> 128:9bcdf88f62b0 322 /**
<> 128:9bcdf88f62b0 323 * @brief Set the ADC's sample time for channel numbers between 30 and 31.
<> 128:9bcdf88f62b0 324 * Register SMPR0 availability depends on device category. If register is not
<> 128:9bcdf88f62b0 325 * available on the current device, this macro does nothing.
<> 128:9bcdf88f62b0 326 * @retval None
<> 128:9bcdf88f62b0 327 * @param _SAMPLETIME_: Sample time parameter.
<> 128:9bcdf88f62b0 328 * @param _CHANNELNB_: Channel number.
<> 128:9bcdf88f62b0 329 * @retval None
<> 128:9bcdf88f62b0 330 */
<> 128:9bcdf88f62b0 331 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
<> 128:9bcdf88f62b0 332 #define ADC_SMPR0(_SAMPLETIME_, _CHANNELNB_) \
<> 128:9bcdf88f62b0 333 ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 30)))
<> 128:9bcdf88f62b0 334 #else
<> 128:9bcdf88f62b0 335 #define ADC_SMPR0(_SAMPLETIME_, _CHANNELNB_) \
<> 128:9bcdf88f62b0 336 ((uint32_t)0x00000000)
<> 128:9bcdf88f62b0 337 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
<> 128:9bcdf88f62b0 338
<> 128:9bcdf88f62b0 339 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
<> 128:9bcdf88f62b0 340 /**
<> 128:9bcdf88f62b0 341 * @brief Set the ADC's sample time for channel numbers between 20 and 29.
<> 128:9bcdf88f62b0 342 * @param _SAMPLETIME_: Sample time parameter.
<> 128:9bcdf88f62b0 343 * @param _CHANNELNB_: Channel number.
<> 128:9bcdf88f62b0 344 * @retval None
<> 128:9bcdf88f62b0 345 */
<> 128:9bcdf88f62b0 346 #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) \
<> 128:9bcdf88f62b0 347 ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 20)))
<> 128:9bcdf88f62b0 348 #else
<> 128:9bcdf88f62b0 349 /**
<> 128:9bcdf88f62b0 350 * @brief Set the ADC's sample time for channel numbers between 20 and 26.
<> 128:9bcdf88f62b0 351 * @param _SAMPLETIME_: Sample time parameter.
<> 128:9bcdf88f62b0 352 * @param _CHANNELNB_: Channel number.
<> 128:9bcdf88f62b0 353 * @retval None
<> 128:9bcdf88f62b0 354 */
<> 128:9bcdf88f62b0 355 #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) \
<> 128:9bcdf88f62b0 356 ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 20)))
<> 128:9bcdf88f62b0 357 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
<> 128:9bcdf88f62b0 358
<> 128:9bcdf88f62b0 359 /**
<> 128:9bcdf88f62b0 360 * @brief Defines the highest channel available in register SMPR1. Channels
<> 128:9bcdf88f62b0 361 * availability depends on device category:
<> 128:9bcdf88f62b0 362 * Highest channel in register SMPR1 is channel 26 for devices Cat.1, Cat.2, Cat.3
<> 128:9bcdf88f62b0 363 * Highest channel in register SMPR1 is channel 29 for devices Cat.4, Cat.5
<> 128:9bcdf88f62b0 364 * @param None
<> 128:9bcdf88f62b0 365 * @retval None
<> 128:9bcdf88f62b0 366 */
<> 128:9bcdf88f62b0 367 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
<> 128:9bcdf88f62b0 368 #define ADC_SMPR1_CHANNEL_MAX ADC_CHANNEL_29
<> 128:9bcdf88f62b0 369 #else
<> 128:9bcdf88f62b0 370 #define ADC_SMPR1_CHANNEL_MAX ADC_CHANNEL_26
<> 128:9bcdf88f62b0 371 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
<> 128:9bcdf88f62b0 372
<> 128:9bcdf88f62b0 373
<> 128:9bcdf88f62b0 374 /**
<> 128:9bcdf88f62b0 375 * @brief Define mask of configuration bits of ADC and regular group in
<> 128:9bcdf88f62b0 376 * register CR2 (bits of ADC enable, conversion start and injected group are
<> 128:9bcdf88f62b0 377 * excluded of this mask).
<> 128:9bcdf88f62b0 378 * @retval None
<> 128:9bcdf88f62b0 379 */
<> 128:9bcdf88f62b0 380 #if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
<> 128:9bcdf88f62b0 381 #define ADC_CR2_MASK_ADCINIT() \
<> 128:9bcdf88f62b0 382 (ADC_CR2_EXTEN | ADC_CR2_EXTSEL | ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | ADC_CR2_DELS | ADC_CR2_CFG | ADC_CR2_CONT)
<> 128:9bcdf88f62b0 383 #else
<> 128:9bcdf88f62b0 384 #define ADC_CR2_MASK_ADCINIT() \
<> 128:9bcdf88f62b0 385 (ADC_CR2_EXTEN | ADC_CR2_EXTSEL | ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | ADC_CR2_DELS | ADC_CR2_CONT)
<> 128:9bcdf88f62b0 386 #endif
<> 128:9bcdf88f62b0 387
<> 128:9bcdf88f62b0 388
<> 128:9bcdf88f62b0 389 /**
<> 128:9bcdf88f62b0 390 * @brief Get the maximum ADC conversion cycles on all channels.
<> 128:9bcdf88f62b0 391 * Returns the selected sampling time + conversion time (12.5 ADC clock cycles)
<> 128:9bcdf88f62b0 392 * Approximation of sampling time within 2 ranges, returns the highest value:
<> 128:9bcdf88f62b0 393 * below 24 cycles {4 cycles; 9 cycles; 16 cycles; 24 cycles}
<> 128:9bcdf88f62b0 394 * between 48 cycles and 384 cycles {48 cycles; 96 cycles; 192 cycles; 384 cycles}
<> 128:9bcdf88f62b0 395 * Unit: ADC clock cycles
<> 128:9bcdf88f62b0 396 * @param __HANDLE__: ADC handle
<> 128:9bcdf88f62b0 397 * @retval ADC conversion cycles on all channels
<> 128:9bcdf88f62b0 398 */
<> 128:9bcdf88f62b0 399 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
<> 128:9bcdf88f62b0 400 #define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \
<> 128:9bcdf88f62b0 401 (( (((__HANDLE__)->Instance->SMPR3 & ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT2) == RESET) && \
<> 128:9bcdf88f62b0 402 (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && \
<> 128:9bcdf88f62b0 403 (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) && \
<> 128:9bcdf88f62b0 404 (((__HANDLE__)->Instance->SMPR0 & ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT2) == RESET) ) ? \
<> 128:9bcdf88f62b0 405 \
<> 128:9bcdf88f62b0 406 ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_24CYCLES : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_384CYCLES \
<> 128:9bcdf88f62b0 407 )
<> 128:9bcdf88f62b0 408 #else
<> 128:9bcdf88f62b0 409 #define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \
<> 128:9bcdf88f62b0 410 (( (((__HANDLE__)->Instance->SMPR3 & ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT2) == RESET) && \
<> 128:9bcdf88f62b0 411 (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && \
<> 128:9bcdf88f62b0 412 (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) ) ? \
<> 128:9bcdf88f62b0 413 \
<> 128:9bcdf88f62b0 414 ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_24CYCLES : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_384CYCLES \
<> 128:9bcdf88f62b0 415 )
<> 128:9bcdf88f62b0 416 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
<> 128:9bcdf88f62b0 417
<> 128:9bcdf88f62b0 418 /**
<> 128:9bcdf88f62b0 419 * @brief Get the ADC clock prescaler from ADC common control register
<> 128:9bcdf88f62b0 420 * and convert it to its decimal number setting (refer to reference manual)
<> 128:9bcdf88f62b0 421 * @retval None
<> 128:9bcdf88f62b0 422 */
<> 128:9bcdf88f62b0 423 #define ADC_GET_CLOCK_PRESCALER_DECIMAL(__HANDLE__) \
<> 128:9bcdf88f62b0 424 ((0x01) << ((ADC->CCR & ADC_CCR_ADCPRE) >> POSITION_VAL(ADC_CCR_ADCPRE)))
<> 128:9bcdf88f62b0 425
<> 128:9bcdf88f62b0 426 /**
<> 128:9bcdf88f62b0 427 * @brief Clear register SMPR0.
<> 128:9bcdf88f62b0 428 * Register SMPR0 availability depends on device category. If register is not
<> 128:9bcdf88f62b0 429 * available on the current device, this macro performs no action.
<> 128:9bcdf88f62b0 430 * @param __HANDLE__: ADC handle
<> 128:9bcdf88f62b0 431 * @retval None
<> 128:9bcdf88f62b0 432 */
<> 128:9bcdf88f62b0 433 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
<> 128:9bcdf88f62b0 434 #define ADC_SMPR1_CLEAR(__HANDLE__) \
<> 128:9bcdf88f62b0 435 CLEAR_BIT((__HANDLE__)->Instance->SMPR1, (ADC_SMPR1_SMP29 | ADC_SMPR1_SMP28 | ADC_SMPR1_SMP27 | \
<> 128:9bcdf88f62b0 436 ADC_SMPR1_SMP26 | ADC_SMPR1_SMP25 | ADC_SMPR1_SMP24 | \
<> 128:9bcdf88f62b0 437 ADC_SMPR1_SMP23 | ADC_SMPR1_SMP22 | ADC_SMPR1_SMP21 | \
<> 128:9bcdf88f62b0 438 ADC_SMPR1_SMP20 ))
<> 128:9bcdf88f62b0 439
<> 128:9bcdf88f62b0 440 #define ADC_SMPR0_CLEAR(__HANDLE__) \
<> 128:9bcdf88f62b0 441 (CLEAR_BIT((__HANDLE__)->Instance->SMPR0, (ADC_SMPR0_SMP31 | ADC_SMPR0_SMP30)))
<> 128:9bcdf88f62b0 442 #else
<> 128:9bcdf88f62b0 443 #define ADC_SMPR1_CLEAR(__HANDLE__) \
<> 128:9bcdf88f62b0 444 CLEAR_BIT((__HANDLE__)->Instance->SMPR1, (ADC_SMPR1_SMP26 | ADC_SMPR1_SMP25 | ADC_SMPR1_SMP24 | \
<> 128:9bcdf88f62b0 445 ADC_SMPR1_SMP23 | ADC_SMPR1_SMP22 | ADC_SMPR1_SMP21 | \
<> 128:9bcdf88f62b0 446 ADC_SMPR1_SMP20 ))
<> 128:9bcdf88f62b0 447
<> 128:9bcdf88f62b0 448 #define ADC_SMPR0_CLEAR(__HANDLE__) __NOP()
<> 128:9bcdf88f62b0 449 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
<> 128:9bcdf88f62b0 450
<> 128:9bcdf88f62b0 451 /**
<> 128:9bcdf88f62b0 452 * @brief Clear register CR2.
<> 128:9bcdf88f62b0 453 * @param __HANDLE__: ADC handle
<> 128:9bcdf88f62b0 454 * @retval None
<> 128:9bcdf88f62b0 455 */
<> 128:9bcdf88f62b0 456 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
<> 128:9bcdf88f62b0 457 #define ADC_CR2_CLEAR(__HANDLE__) \
<> 128:9bcdf88f62b0 458 (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL | \
<> 128:9bcdf88f62b0 459 ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL | \
<> 128:9bcdf88f62b0 460 ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | \
<> 128:9bcdf88f62b0 461 ADC_CR2_DMA | ADC_CR2_DELS | ADC_CR2_CFG | \
<> 128:9bcdf88f62b0 462 ADC_CR2_CONT | ADC_CR2_ADON )) \
<> 128:9bcdf88f62b0 463 )
<> 128:9bcdf88f62b0 464 #else
<> 128:9bcdf88f62b0 465 #define ADC_CR2_CLEAR(__HANDLE__) \
<> 128:9bcdf88f62b0 466 (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL | \
<> 128:9bcdf88f62b0 467 ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL | \
<> 128:9bcdf88f62b0 468 ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | \
<> 128:9bcdf88f62b0 469 ADC_CR2_DMA | ADC_CR2_DELS | \
<> 128:9bcdf88f62b0 470 ADC_CR2_CONT | ADC_CR2_ADON )) \
<> 128:9bcdf88f62b0 471 )
<> 128:9bcdf88f62b0 472 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
<> 128:9bcdf88f62b0 473
<> 128:9bcdf88f62b0 474 /**
<> 128:9bcdf88f62b0 475 * @brief Set the sampling time of selected channel on register SMPR0
<> 128:9bcdf88f62b0 476 * Register SMPR0 availability depends on device category. If register is not
<> 128:9bcdf88f62b0 477 * available on the current device, this macro performs no action.
<> 128:9bcdf88f62b0 478 * @param __HANDLE__: ADC handle
<> 128:9bcdf88f62b0 479 * @param _SAMPLETIME_: Sample time parameter.
<> 128:9bcdf88f62b0 480 * @param __CHANNEL__: Channel number.
<> 128:9bcdf88f62b0 481 * @retval None
<> 128:9bcdf88f62b0 482 */
<> 128:9bcdf88f62b0 483 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
<> 128:9bcdf88f62b0 484 #define ADC_SMPR0_CHANNEL_SET(__HANDLE__, _SAMPLETIME_, __CHANNEL__) \
<> 128:9bcdf88f62b0 485 MODIFY_REG((__HANDLE__)->Instance->SMPR0, \
<> 128:9bcdf88f62b0 486 ADC_SMPR0(ADC_SMPR0_SMP30, (__CHANNEL__)), \
<> 128:9bcdf88f62b0 487 ADC_SMPR0((_SAMPLETIME_), (__CHANNEL__)) )
<> 128:9bcdf88f62b0 488 #else
<> 128:9bcdf88f62b0 489 #define ADC_SMPR0_CHANNEL_SET(__HANDLE__, _SAMPLETIME_, __CHANNEL__) __NOP()
<> 128:9bcdf88f62b0 490 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
<> 128:9bcdf88f62b0 491
<> 128:9bcdf88f62b0 492
<> 128:9bcdf88f62b0 493 #define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || \
<> 128:9bcdf88f62b0 494 ((CHANNEL) == ADC_INJECTED_RANK_2) || \
<> 128:9bcdf88f62b0 495 ((CHANNEL) == ADC_INJECTED_RANK_3) || \
<> 128:9bcdf88f62b0 496 ((CHANNEL) == ADC_INJECTED_RANK_4) )
<> 128:9bcdf88f62b0 497
<> 128:9bcdf88f62b0 498 #define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \
<> 128:9bcdf88f62b0 499 ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \
<> 128:9bcdf88f62b0 500 ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \
<> 128:9bcdf88f62b0 501 ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) )
<> 128:9bcdf88f62b0 502
<> 128:9bcdf88f62b0 503 #define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
<> 128:9bcdf88f62b0 504 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
<> 128:9bcdf88f62b0 505 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
<> 128:9bcdf88f62b0 506 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
<> 128:9bcdf88f62b0 507 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC1) || \
<> 128:9bcdf88f62b0 508 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC2) || \
<> 128:9bcdf88f62b0 509 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \
<> 128:9bcdf88f62b0 510 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T7_TRGO) || \
<> 128:9bcdf88f62b0 511 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T9_CC1) || \
<> 128:9bcdf88f62b0 512 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T9_TRGO) || \
<> 128:9bcdf88f62b0 513 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T10_CC1) || \
<> 128:9bcdf88f62b0 514 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
<> 128:9bcdf88f62b0 515 ((REGTRIG) == ADC_SOFTWARE_START) )
<> 128:9bcdf88f62b0 516
<> 128:9bcdf88f62b0 517 /** @defgroup ADCEx_injected_nb_conv_verification ADCEx injected nb conv verification
<> 128:9bcdf88f62b0 518 * @{
<> 128:9bcdf88f62b0 519 */
<> 128:9bcdf88f62b0 520 #define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)4)))
<> 128:9bcdf88f62b0 521 /**
<> 128:9bcdf88f62b0 522 * @}
<> 128:9bcdf88f62b0 523 */
<> 128:9bcdf88f62b0 524
<> 128:9bcdf88f62b0 525 /**
<> 128:9bcdf88f62b0 526 * @}
<> 128:9bcdf88f62b0 527 */
<> 128:9bcdf88f62b0 528
<> 128:9bcdf88f62b0 529
<> 128:9bcdf88f62b0 530 /* Exported functions --------------------------------------------------------*/
<> 128:9bcdf88f62b0 531 /** @addtogroup ADCEx_Exported_Functions
<> 128:9bcdf88f62b0 532 * @{
<> 128:9bcdf88f62b0 533 */
<> 128:9bcdf88f62b0 534
<> 128:9bcdf88f62b0 535 /* IO operation functions *****************************************************/
<> 128:9bcdf88f62b0 536 /** @addtogroup ADCEx_Exported_Functions_Group1
<> 128:9bcdf88f62b0 537 * @{
<> 128:9bcdf88f62b0 538 */
<> 128:9bcdf88f62b0 539
<> 128:9bcdf88f62b0 540 /* Blocking mode: Polling */
<> 128:9bcdf88f62b0 541 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);
<> 128:9bcdf88f62b0 542 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);
<> 128:9bcdf88f62b0 543 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
<> 128:9bcdf88f62b0 544
<> 128:9bcdf88f62b0 545 /* Non-blocking mode: Interruption */
<> 128:9bcdf88f62b0 546 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);
<> 128:9bcdf88f62b0 547 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
<> 128:9bcdf88f62b0 548
<> 128:9bcdf88f62b0 549 /* ADC retrieve conversion value intended to be used with polling or interruption */
<> 128:9bcdf88f62b0 550 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
<> 128:9bcdf88f62b0 551
<> 128:9bcdf88f62b0 552 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
<> 128:9bcdf88f62b0 553 void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
<> 128:9bcdf88f62b0 554 /**
<> 128:9bcdf88f62b0 555 * @}
<> 128:9bcdf88f62b0 556 */
<> 128:9bcdf88f62b0 557
<> 128:9bcdf88f62b0 558
<> 128:9bcdf88f62b0 559 /* Peripheral Control functions ***********************************************/
<> 128:9bcdf88f62b0 560 /** @addtogroup ADCEx_Exported_Functions_Group2
<> 128:9bcdf88f62b0 561 * @{
<> 128:9bcdf88f62b0 562 */
<> 128:9bcdf88f62b0 563
<> 128:9bcdf88f62b0 564 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
<> 128:9bcdf88f62b0 565 /**
<> 128:9bcdf88f62b0 566 * @}
<> 128:9bcdf88f62b0 567 */
<> 128:9bcdf88f62b0 568
<> 128:9bcdf88f62b0 569
<> 128:9bcdf88f62b0 570 /**
<> 128:9bcdf88f62b0 571 * @}
<> 128:9bcdf88f62b0 572 */
<> 128:9bcdf88f62b0 573
<> 128:9bcdf88f62b0 574
<> 128:9bcdf88f62b0 575 /**
<> 128:9bcdf88f62b0 576 * @}
<> 128:9bcdf88f62b0 577 */
<> 128:9bcdf88f62b0 578
<> 128:9bcdf88f62b0 579 /**
<> 128:9bcdf88f62b0 580 * @}
<> 128:9bcdf88f62b0 581 */
<> 128:9bcdf88f62b0 582
<> 128:9bcdf88f62b0 583 #ifdef __cplusplus
<> 128:9bcdf88f62b0 584 }
<> 128:9bcdf88f62b0 585 #endif
<> 128:9bcdf88f62b0 586
<> 128:9bcdf88f62b0 587 #endif /* __STM32L1xx_HAL_ADC_EX_H */
<> 128:9bcdf88f62b0 588
<> 128:9bcdf88f62b0 589
<> 128:9bcdf88f62b0 590 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/