mbed - The official Mbed 2 C/C++ SDK provides the softwa…

Users » mbed_official » Code » mbed

mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_MOTE_L152RC/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_adc.h@136:ef9c61f8c49f, 2017-02-14 (annotated)

Committer:: Kojto
Date:: Tue Feb 14 11:24:20 2017 +0000
Revision:: 136:ef9c61f8c49f
Parent:: 128:9bcdf88f62b0
Child:: 165:d1b4690b3f8b

Release 136 of the mbed library

Ports for Upcoming Targets

Fixes and Changes

3432: Target STM USBHOST support https://github.com/ARMmbed/mbed-os/pull/3432

3181: NUCLEO_F207ZG extending PeripheralPins.c: all available alternate functions can be used now https://github.com/ARMmbed/mbed-os/pull/3181

3626: NUCLEO_F412ZG : Add USB Device +Host https://github.com/ARMmbed/mbed-os/pull/3626

3628: Fix warnings https://github.com/ARMmbed/mbed-os/pull/3628

3629: STM32: L0 LL layer https://github.com/ARMmbed/mbed-os/pull/3629

3632: IDE Export support for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3632

3642: Missing IRQ pin fix for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3642

3664: Fix ncs36510 sleep definitions https://github.com/ARMmbed/mbed-os/pull/3664

3655: [STM32F4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3655

3657: [STM32L4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3657

3658: [STM32F3] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3658

3685: STM32: I2C: reset state machine https://github.com/ARMmbed/mbed-os/pull/3685

3692: uVisor: Standardize available legacy heap and stack https://github.com/ARMmbed/mbed-os/pull/3692

3621: Fix for #2884, LPC824: export to LPCXpresso, target running with wron https://github.com/ARMmbed/mbed-os/pull/3621

3649: [STM32F7] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3649

3695: Enforce device_name is valid in targets.json https://github.com/ARMmbed/mbed-os/pull/3695

3723: NCS36510: spi_format function bug fix https://github.com/ARMmbed/mbed-os/pull/3723

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	128:9bcdf88f62b0	1	/**
<>	128:9bcdf88f62b0	2	******************************************************************************
<>	128:9bcdf88f62b0	3	* @file stm32l1xx_hal_adc.h
<>	128:9bcdf88f62b0	4	* @author MCD Application Team
<>	128:9bcdf88f62b0	5	* @version V1.2.0
<>	128:9bcdf88f62b0	6	* @date 01-July-2016
<>	128:9bcdf88f62b0	7	* @brief Header file containing functions prototypes of ADC HAL library.
<>	128:9bcdf88f62b0	8	******************************************************************************
<>	128:9bcdf88f62b0	9	* @attention
<>	128:9bcdf88f62b0	10	*
<>	128:9bcdf88f62b0	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	128:9bcdf88f62b0	12	*
<>	128:9bcdf88f62b0	13	* Redistribution and use in source and binary forms, with or without modification,
<>	128:9bcdf88f62b0	14	* are permitted provided that the following conditions are met:
<>	128:9bcdf88f62b0	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	128:9bcdf88f62b0	16	* this list of conditions and the following disclaimer.
<>	128:9bcdf88f62b0	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	128:9bcdf88f62b0	18	* this list of conditions and the following disclaimer in the documentation
<>	128:9bcdf88f62b0	19	* and/or other materials provided with the distribution.
<>	128:9bcdf88f62b0	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	128:9bcdf88f62b0	21	* may be used to endorse or promote products derived from this software
<>	128:9bcdf88f62b0	22	* without specific prior written permission.
<>	128:9bcdf88f62b0	23	*
<>	128:9bcdf88f62b0	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	128:9bcdf88f62b0	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	128:9bcdf88f62b0	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	128:9bcdf88f62b0	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	128:9bcdf88f62b0	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	128:9bcdf88f62b0	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	128:9bcdf88f62b0	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	128:9bcdf88f62b0	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	128:9bcdf88f62b0	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	128:9bcdf88f62b0	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	128:9bcdf88f62b0	34	*
<>	128:9bcdf88f62b0	35	******************************************************************************
<>	128:9bcdf88f62b0	36	*/
<>	128:9bcdf88f62b0	37
<>	128:9bcdf88f62b0	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	128:9bcdf88f62b0	39	#ifndef __STM32L1xx_HAL_ADC_H
<>	128:9bcdf88f62b0	40	#define __STM32L1xx_HAL_ADC_H
<>	128:9bcdf88f62b0	41
<>	128:9bcdf88f62b0	42	#ifdef __cplusplus
<>	128:9bcdf88f62b0	43	extern "C" {
<>	128:9bcdf88f62b0	44	#endif
<>	128:9bcdf88f62b0	45
<>	128:9bcdf88f62b0	46	/* Includes ------------------------------------------------------------------*/
<>	128:9bcdf88f62b0	47	#include "stm32l1xx_hal_def.h"
<>	128:9bcdf88f62b0	48
<>	128:9bcdf88f62b0	49	/** @addtogroup STM32L1xx_HAL_Driver
<>	128:9bcdf88f62b0	50	* @{
<>	128:9bcdf88f62b0	51	*/
<>	128:9bcdf88f62b0	52
<>	128:9bcdf88f62b0	53	/** @addtogroup ADC
<>	128:9bcdf88f62b0	54	* @{
<>	128:9bcdf88f62b0	55	*/
<>	128:9bcdf88f62b0	56
<>	128:9bcdf88f62b0	57	/* Exported types ------------------------------------------------------------*/
<>	128:9bcdf88f62b0	58	/** @defgroup ADC_Exported_Types ADC Exported Types
<>	128:9bcdf88f62b0	59	* @{
<>	128:9bcdf88f62b0	60	*/
<>	128:9bcdf88f62b0	61
<>	128:9bcdf88f62b0	62	/**
<>	128:9bcdf88f62b0	63	* @brief Structure definition of ADC and regular group initialization
<>	128:9bcdf88f62b0	64	* @note Parameters of this structure are shared within 2 scopes:
<>	128:9bcdf88f62b0	65	* - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank.
<>	128:9bcdf88f62b0	66	* - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
<>	128:9bcdf88f62b0	67	* @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
<>	128:9bcdf88f62b0	68	* ADC state can be either:
<>	128:9bcdf88f62b0	69	* - For all parameters: ADC disabled
<>	128:9bcdf88f62b0	70	* - For all parameters except 'Resolution', 'ScanConvMode', 'LowPowerAutoWait', 'LowPowerAutoPowerOff', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group.
<>	128:9bcdf88f62b0	71	* - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going.
<>	128:9bcdf88f62b0	72	* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
<>	128:9bcdf88f62b0	73	* without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fullfills the ADC state condition) on the fly).
<>	128:9bcdf88f62b0	74	*/
<>	128:9bcdf88f62b0	75	typedef struct
<>	128:9bcdf88f62b0	76	{
<>	128:9bcdf88f62b0	77	uint32_t ClockPrescaler; /*!< Select ADC clock source (asynchronous clock derived from HSI RC oscillator) and clock prescaler.
<>	128:9bcdf88f62b0	78	This parameter can be a value of @ref ADC_ClockPrescaler
<>	128:9bcdf88f62b0	79	Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits,
<>	128:9bcdf88f62b0	80	AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits.
<>	128:9bcdf88f62b0	81	Note: HSI RC oscillator must be preliminarily enabled at RCC top level. */
<>	128:9bcdf88f62b0	82	uint32_t Resolution; /*!< Configures the ADC resolution.
<>	128:9bcdf88f62b0	83	This parameter can be a value of @ref ADC_Resolution */
<>	128:9bcdf88f62b0	84	uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
<>	128:9bcdf88f62b0	85	or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
<>	128:9bcdf88f62b0	86	This parameter can be a value of @ref ADC_Data_align */
<>	128:9bcdf88f62b0	87	uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
<>	128:9bcdf88f62b0	88	This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
<>	128:9bcdf88f62b0	89	If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
<>	128:9bcdf88f62b0	90	Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
<>	128:9bcdf88f62b0	91	If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
<>	128:9bcdf88f62b0	92	Scan direction is upward: from rank1 to rank 'n'.
<>	128:9bcdf88f62b0	93	This parameter can be a value of @ref ADC_Scan_mode */
<>	128:9bcdf88f62b0	94	uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
<>	128:9bcdf88f62b0	95	This parameter can be a value of @ref ADC_EOCSelection.
<>	128:9bcdf88f62b0	96	Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence.
<>	128:9bcdf88f62b0	97	Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT)
<>	128:9bcdf88f62b0	98	or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion.
<>	128:9bcdf88f62b0	99	Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()).
<>	128:9bcdf88f62b0	100	If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */
<>	128:9bcdf88f62b0	101	uint32_t LowPowerAutoWait; /*!< Selects the dynamic low power Auto Delay: new conversion start only when the previous
<>	128:9bcdf88f62b0	102	conversion (for regular group) or previous sequence (for injected group) has been treated by user software, using function HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue().
<>	128:9bcdf88f62b0	103	This feature automatically adapts the speed of ADC to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications.
<>	128:9bcdf88f62b0	104	This parameter can be a value of @ref ADC_LowPowerAutoWait.
<>	128:9bcdf88f62b0	105	Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they have to clear immediately the EOC flag to free the IRQ vector sequencer.
<>	128:9bcdf88f62b0	106	Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed
<>	128:9bcdf88f62b0	107	and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion (in case of usage of injected group, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...).
<>	128:9bcdf88f62b0	108	Note: ADC clock latency and some timing constraints depending on clock prescaler have to be taken into account: refer to reference manual (register ADC_CR2 bit DELS description). */
<>	128:9bcdf88f62b0	109	uint32_t LowPowerAutoPowerOff; /*!< Selects the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling).
<>	128:9bcdf88f62b0	110	This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait').
<>	128:9bcdf88f62b0	111	This parameter can be a value of @ref ADC_LowPowerAutoPowerOff. */
<>	128:9bcdf88f62b0	112	uint32_t ChannelsBank; /*!< Selects the ADC channels bank.
<>	128:9bcdf88f62b0	113	This parameter can be a value of @ref ADC_ChannelsBank.
<>	128:9bcdf88f62b0	114	Note: Banks availability depends on devices categories.
<>	128:9bcdf88f62b0	115	Note: To change bank selection on the fly, without going through execution of 'HAL_ADC_Init()', macro '__HAL_ADC_CHANNELS_BANK()' can be used directly. */
<>	128:9bcdf88f62b0	116	uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
<>	128:9bcdf88f62b0	117	after the selected trigger occurred (software start or external trigger).
<>	128:9bcdf88f62b0	118	This parameter can be set to ENABLE or DISABLE. */
<>	128:9bcdf88f62b0	119	#if defined(STM32L100xC) \|\| defined (STM32L151xC) \|\| defined (STM32L152xC) \|\| defined (STM32L162xC) \|\| defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD) \|\| defined(STM32L151xE) \|\| defined(STM32L151xDX) \|\| defined (STM32L152xE) \|\| defined (STM32L152xDX) \|\| defined (STM32L162xE) \|\| defined (STM32L162xDX)
<>	128:9bcdf88f62b0	120	uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
<>	128:9bcdf88f62b0	121	To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
<>	128:9bcdf88f62b0	122	This parameter must be a number between Min_Data = 1 and Max_Data = 28. */
<>	128:9bcdf88f62b0	123	#else
<>	128:9bcdf88f62b0	124	uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
<>	128:9bcdf88f62b0	125	To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
<>	128:9bcdf88f62b0	126	This parameter must be a number between Min_Data = 1 and Max_Data = 27. */
<>	128:9bcdf88f62b0	127	#endif /* STM32L100xC \|\| STM32L151xC \|\| STM32L152xC \|\| STM32L162xC \|\| STM32L151xCA \|\| STM32L151xD \|\| STM32L152xCA \|\| STM32L152xD \|\| STM32L162xCA \|\| STM32L162xD \|\| STM32L151xE \|\| STM32L151xDX \|\| STM32L152xE \|\| STM32L152xDX \|\| STM32L162xE \|\| STM32L162xDX */
<>	128:9bcdf88f62b0	128	uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
<>	128:9bcdf88f62b0	129	Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
<>	128:9bcdf88f62b0	130	Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
<>	128:9bcdf88f62b0	131	This parameter can be set to ENABLE or DISABLE. */
<>	128:9bcdf88f62b0	132	uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided.
<>	128:9bcdf88f62b0	133	If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
<>	128:9bcdf88f62b0	134	This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
<>	128:9bcdf88f62b0	135	uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
<>	128:9bcdf88f62b0	136	If set to ADC_SOFTWARE_START, external triggers are disabled.
<>	128:9bcdf88f62b0	137	If set to external trigger source, triggering is on event rising edge by default.
<>	128:9bcdf88f62b0	138	This parameter can be a value of @ref ADC_External_trigger_source_Regular */
<>	128:9bcdf88f62b0	139	uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group.
<>	128:9bcdf88f62b0	140	If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
<>	128:9bcdf88f62b0	141	This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
<>	128:9bcdf88f62b0	142	uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
<>	128:9bcdf88f62b0	143	or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
<>	128:9bcdf88f62b0	144	Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
<>	128:9bcdf88f62b0	145	Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).
<>	128:9bcdf88f62b0	146	This parameter can be set to ENABLE or DISABLE. */
<>	128:9bcdf88f62b0	147	}ADC_InitTypeDef;
<>	128:9bcdf88f62b0	148
<>	128:9bcdf88f62b0	149	/**
<>	128:9bcdf88f62b0	150	* @brief Structure definition of ADC channel for regular group
<>	128:9bcdf88f62b0	151	* @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
<>	128:9bcdf88f62b0	152	* ADC can be either disabled or enabled without conversion on going on regular group.
<>	128:9bcdf88f62b0	153	*/
<>	128:9bcdf88f62b0	154	typedef struct
<>	128:9bcdf88f62b0	155	{
<>	128:9bcdf88f62b0	156	uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
<>	128:9bcdf88f62b0	157	This parameter can be a value of @ref ADC_channels
<>	128:9bcdf88f62b0	158	Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.
<>	128:9bcdf88f62b0	159	Maximum number of channels by device category (without taking in account each device package constraints):
<>	128:9bcdf88f62b0	160	STM32L1 category 1, 2: 24 channels on external pins + 3 channels on internal measurement paths (VrefInt, Temp sensor, Vcomp): Channel 0 to channel 26.
<>	128:9bcdf88f62b0	161	STM32L1 category 3: 25 channels on external pins + 3 channels on internal measurement paths (VrefInt, Temp sensor, Vcomp): Channel 0 to channel 26, 1 additional channel in bank B. Note: OPAMP1 and OPAMP2 are connected internally but not increasing internal channels number: they are sharing ADC input with external channels ADC_IN3 and ADC_IN8.
<>	128:9bcdf88f62b0	162	STM32L1 category 4, 5: 40 channels on external pins + 3 channels on internal measurement paths (VrefInt, Temp sensor, Vcomp): Channel 0 to channel 31, 11 additional channels in bank B. Note: OPAMP1 and OPAMP2 are connected internally but not increasing internal channels number: they are sharing ADC input with external channels ADC_IN3 and ADC_IN8.
<>	128:9bcdf88f62b0	163	Note: In case of peripherals OPAMPx not used: 3 channels (3, 8, 13) can be configured as direct channels (fast channels). Refer to macro ' __HAL_ADC_CHANNEL_SPEED_FAST() '.
<>	128:9bcdf88f62b0	164	Note: In case of peripheral OPAMP3 and ADC channel OPAMP3 used (OPAMP3 available on STM32L1 devices Cat.4 only): the analog switch COMP1_SW1 must be closed. Refer to macro: ' __HAL_OPAMP_OPAMP3OUT_CONNECT_ADC_COMP1() '. */
<>	128:9bcdf88f62b0	165	uint32_t Rank; /*!< Specifies the rank in the regular group sequencer.
<>	128:9bcdf88f62b0	166	This parameter can be a value of @ref ADC_regular_rank
<>	128:9bcdf88f62b0	167	Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
<>	128:9bcdf88f62b0	168	uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
<>	128:9bcdf88f62b0	169	Unit: ADC clock cycles
<>	128:9bcdf88f62b0	170	Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
<>	128:9bcdf88f62b0	171	This parameter can be a value of @ref ADC_sampling_times
<>	128:9bcdf88f62b0	172	Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
<>	128:9bcdf88f62b0	173	If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
<>	128:9bcdf88f62b0	174	Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
<>	128:9bcdf88f62b0	175	sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
<>	128:9bcdf88f62b0	176	Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
<>	128:9bcdf88f62b0	177	}ADC_ChannelConfTypeDef;
<>	128:9bcdf88f62b0	178
<>	128:9bcdf88f62b0	179	/**
<>	128:9bcdf88f62b0	180	* @brief ADC Configuration analog watchdog definition
<>	128:9bcdf88f62b0	181	* @note The setting of these parameters with function is conditioned to ADC state.
<>	128:9bcdf88f62b0	182	* ADC state can be either disabled or enabled without conversion on going on regular and injected groups.
<>	128:9bcdf88f62b0	183	*/
<>	128:9bcdf88f62b0	184	typedef struct
<>	128:9bcdf88f62b0	185	{
<>	128:9bcdf88f62b0	186	uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group.
<>	128:9bcdf88f62b0	187	This parameter can be a value of @ref ADC_analog_watchdog_mode. */
<>	128:9bcdf88f62b0	188	uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog.
<>	128:9bcdf88f62b0	189	This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode)
<>	128:9bcdf88f62b0	190	This parameter can be a value of @ref ADC_channels. */
<>	128:9bcdf88f62b0	191	uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
<>	128:9bcdf88f62b0	192	This parameter can be set to ENABLE or DISABLE */
<>	128:9bcdf88f62b0	193	uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
<>	128:9bcdf88f62b0	194	This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
<>	128:9bcdf88f62b0	195	uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
<>	128:9bcdf88f62b0	196	This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
<>	128:9bcdf88f62b0	197	uint32_t WatchdogNumber; /!< Reserved for future use, can be set to 0 /
<>	128:9bcdf88f62b0	198	}ADC_AnalogWDGConfTypeDef;
<>	128:9bcdf88f62b0	199
<>	128:9bcdf88f62b0	200	/**
<>	128:9bcdf88f62b0	201	* @brief HAL ADC state machine: ADC states definition (bitfields)
<>	128:9bcdf88f62b0	202	*/
<>	128:9bcdf88f62b0	203	/* States of ADC global scope */
<>	128:9bcdf88f62b0	204	#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000) /!< ADC not yet initialized or disabled /
<>	128:9bcdf88f62b0	205	#define HAL_ADC_STATE_READY ((uint32_t)0x00000001) /!< ADC peripheral ready for use /
<>	128:9bcdf88f62b0	206	#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002) /!< ADC is busy to internal process (initialization, calibration) /
<>	128:9bcdf88f62b0	207	#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004) /!< TimeOut occurrence /
<>	128:9bcdf88f62b0	208
<>	128:9bcdf88f62b0	209	/* States of ADC errors */
<>	128:9bcdf88f62b0	210	#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010) /!< Internal error occurrence /
<>	128:9bcdf88f62b0	211	#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020) /!< Configuration error occurrence /
<>	128:9bcdf88f62b0	212	#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040) /!< DMA error occurrence /
<>	128:9bcdf88f62b0	213
<>	128:9bcdf88f62b0	214	/* States of ADC group regular */
<>	128:9bcdf88f62b0	215	#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
<>	128:9bcdf88f62b0	216	external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
<>	128:9bcdf88f62b0	217	#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200) /!< Conversion data available on group regular /
<>	128:9bcdf88f62b0	218	#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400) /!< Overrun occurrence /
<>	128:9bcdf88f62b0	219	#define HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800) /!< Not available on STM32L1 device: End Of Sampling flag raised /
<>	128:9bcdf88f62b0	220
<>	128:9bcdf88f62b0	221	/* States of ADC group injected */
<>	128:9bcdf88f62b0	222	#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
<>	128:9bcdf88f62b0	223	external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
<>	128:9bcdf88f62b0	224	#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000) /!< Conversion data available on group injected /
<>	128:9bcdf88f62b0	225	#define HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000) /!< Not available on STM32L1 device: Injected queue overflow occurrence /
<>	128:9bcdf88f62b0	226
<>	128:9bcdf88f62b0	227	/* States of ADC analog watchdogs */
<>	128:9bcdf88f62b0	228	#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000) /!< Out-of-window occurrence of analog watchdog 1 /
<>	128:9bcdf88f62b0	229	#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000) /!< Not available on STM32L1 device: Out-of-window occurrence of analog watchdog 2 /
<>	128:9bcdf88f62b0	230	#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000) /!< Not available on STM32L1 device: Out-of-window occurrence of analog watchdog 3 /
<>	128:9bcdf88f62b0	231
<>	128:9bcdf88f62b0	232	/* States of ADC multi-mode */
<>	128:9bcdf88f62b0	233	#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000) /!< Not available on STM32L1 device: ADC in multimode slave state, controlled by another ADC master ( /
<>	128:9bcdf88f62b0	234
<>	128:9bcdf88f62b0	235
<>	128:9bcdf88f62b0	236	/**
<>	128:9bcdf88f62b0	237	* @brief ADC handle Structure definition
<>	128:9bcdf88f62b0	238	*/
<>	128:9bcdf88f62b0	239	typedef struct
<>	128:9bcdf88f62b0	240	{
<>	128:9bcdf88f62b0	241	ADC_TypeDef Instance; /!< Register base address */
<>	128:9bcdf88f62b0	242
<>	128:9bcdf88f62b0	243	ADC_InitTypeDef Init; /!< ADC required parameters /
<>	128:9bcdf88f62b0	244
<>	128:9bcdf88f62b0	245	__IO uint32_t NbrOfConversionRank ; /!< ADC conversion rank counter /
<>	128:9bcdf88f62b0	246
<>	128:9bcdf88f62b0	247	DMA_HandleTypeDef DMA_Handle; /!< Pointer DMA Handler */
<>	128:9bcdf88f62b0	248
<>	128:9bcdf88f62b0	249	HAL_LockTypeDef Lock; /!< ADC locking object /
<>	128:9bcdf88f62b0	250
<>	128:9bcdf88f62b0	251	__IO uint32_t State; /!< ADC communication state (bitmap of ADC states) /
<>	128:9bcdf88f62b0	252
<>	128:9bcdf88f62b0	253	__IO uint32_t ErrorCode; /!< ADC Error code /
<>	128:9bcdf88f62b0	254	}ADC_HandleTypeDef;
<>	128:9bcdf88f62b0	255	/**
<>	128:9bcdf88f62b0	256	* @}
<>	128:9bcdf88f62b0	257	*/
<>	128:9bcdf88f62b0	258
<>	128:9bcdf88f62b0	259
<>	128:9bcdf88f62b0	260
<>	128:9bcdf88f62b0	261	/* Exported constants --------------------------------------------------------*/
<>	128:9bcdf88f62b0	262
<>	128:9bcdf88f62b0	263	/** @defgroup ADC_Exported_Constants ADC Exported Constants
<>	128:9bcdf88f62b0	264	* @{
<>	128:9bcdf88f62b0	265	*/
<>	128:9bcdf88f62b0	266
<>	128:9bcdf88f62b0	267	/** @defgroup ADC_Error_Code ADC Error Code
<>	128:9bcdf88f62b0	268	* @{
<>	128:9bcdf88f62b0	269	*/
<>	128:9bcdf88f62b0	270	#define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /!< No error /
<>	128:9bcdf88f62b0	271	#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01) /*!< ADC IP internal error: if problem of clocking,
<>	128:9bcdf88f62b0	272	enable/disable, erroneous state */
<>	128:9bcdf88f62b0	273	#define HAL_ADC_ERROR_OVR ((uint32_t)0x02) /!< Overrun error /
<>	128:9bcdf88f62b0	274	#define HAL_ADC_ERROR_DMA ((uint32_t)0x04) /!< DMA transfer error /
<>	128:9bcdf88f62b0	275	/**
<>	128:9bcdf88f62b0	276	* @}
<>	128:9bcdf88f62b0	277	*/
<>	128:9bcdf88f62b0	278
<>	128:9bcdf88f62b0	279	/** @defgroup ADC_ClockPrescaler ADC ClockPrescaler
<>	128:9bcdf88f62b0	280	* @{
<>	128:9bcdf88f62b0	281	*/
<>	128:9bcdf88f62b0	282	#define ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000) /!< ADC asynchronous clock derived from ADC dedicated HSI without prescaler /
<>	128:9bcdf88f62b0	283	#define ADC_CLOCK_ASYNC_DIV2 ((uint32_t)ADC_CCR_ADCPRE_0) /!< ADC asynchronous clock derived from ADC dedicated HSI divided by a prescaler of 2 /
<>	128:9bcdf88f62b0	284	#define ADC_CLOCK_ASYNC_DIV4 ((uint32_t)ADC_CCR_ADCPRE_1) /!< ADC asynchronous clock derived from ADC dedicated HSI divided by a prescaler of 4 /
<>	128:9bcdf88f62b0	285	/**
<>	128:9bcdf88f62b0	286	* @}
<>	128:9bcdf88f62b0	287	*/
<>	128:9bcdf88f62b0	288
<>	128:9bcdf88f62b0	289	/** @defgroup ADC_Resolution ADC Resolution
<>	128:9bcdf88f62b0	290	* @{
<>	128:9bcdf88f62b0	291	*/
<>	128:9bcdf88f62b0	292	#define ADC_RESOLUTION_12B ((uint32_t)0x00000000) /!< ADC 12-bit resolution /
<>	128:9bcdf88f62b0	293	#define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0) /!< ADC 10-bit resolution /
<>	128:9bcdf88f62b0	294	#define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1) /!< ADC 8-bit resolution /
<>	128:9bcdf88f62b0	295	#define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES) /!< ADC 6-bit resolution /
<>	128:9bcdf88f62b0	296	/**
<>	128:9bcdf88f62b0	297	* @}
<>	128:9bcdf88f62b0	298	*/
<>	128:9bcdf88f62b0	299
<>	128:9bcdf88f62b0	300	/** @defgroup ADC_Data_align ADC Data_align
<>	128:9bcdf88f62b0	301	* @{
<>	128:9bcdf88f62b0	302	*/
<>	128:9bcdf88f62b0	303	#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)
<>	128:9bcdf88f62b0	304	#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
<>	128:9bcdf88f62b0	305	/**
<>	128:9bcdf88f62b0	306	* @}
<>	128:9bcdf88f62b0	307	*/
<>	128:9bcdf88f62b0	308
<>	128:9bcdf88f62b0	309	/** @defgroup ADC_Scan_mode ADC Scan mode
<>	128:9bcdf88f62b0	310	* @{
<>	128:9bcdf88f62b0	311	*/
<>	128:9bcdf88f62b0	312	#define ADC_SCAN_DISABLE ((uint32_t)0x00000000)
<>	128:9bcdf88f62b0	313	#define ADC_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN)
<>	128:9bcdf88f62b0	314	/**
<>	128:9bcdf88f62b0	315	* @}
<>	128:9bcdf88f62b0	316	*/
<>	128:9bcdf88f62b0	317
<>	128:9bcdf88f62b0	318	/** @defgroup ADC_External_trigger_edge_Regular ADC external trigger enable for regular group
<>	128:9bcdf88f62b0	319	* @{
<>	128:9bcdf88f62b0	320	*/
<>	128:9bcdf88f62b0	321	#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000)
<>	128:9bcdf88f62b0	322	#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0)
<>	128:9bcdf88f62b0	323	#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1)
<>	128:9bcdf88f62b0	324	#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN)
<>	128:9bcdf88f62b0	325	/**
<>	128:9bcdf88f62b0	326	* @}
<>	128:9bcdf88f62b0	327	*/
<>	128:9bcdf88f62b0	328
<>	128:9bcdf88f62b0	329	/** @defgroup ADC_External_trigger_source_Regular ADC External trigger source Regular
<>	128:9bcdf88f62b0	330	* @{
<>	128:9bcdf88f62b0	331	*/
<>	128:9bcdf88f62b0	332	/* List of external triggers with generic trigger name, sorted by trigger */
<>	128:9bcdf88f62b0	333	/* name: */
<>	128:9bcdf88f62b0	334
<>	128:9bcdf88f62b0	335	/* External triggers of regular group for ADC1 */
<>	128:9bcdf88f62b0	336	#define ADC_EXTERNALTRIGCONV_T2_CC3 ADC_EXTERNALTRIG_T2_CC3
<>	128:9bcdf88f62b0	337	#define ADC_EXTERNALTRIGCONV_T2_CC2 ADC_EXTERNALTRIG_T2_CC2
<>	128:9bcdf88f62b0	338	#define ADC_EXTERNALTRIGCONV_T2_TRGO ADC_EXTERNALTRIG_T2_TRGO
<>	128:9bcdf88f62b0	339	#define ADC_EXTERNALTRIGCONV_T3_CC1 ADC_EXTERNALTRIG_T3_CC1
<>	128:9bcdf88f62b0	340	#define ADC_EXTERNALTRIGCONV_T3_CC3 ADC_EXTERNALTRIG_T3_CC3
<>	128:9bcdf88f62b0	341	#define ADC_EXTERNALTRIGCONV_T3_TRGO ADC_EXTERNALTRIG_T3_TRGO
<>	128:9bcdf88f62b0	342	#define ADC_EXTERNALTRIGCONV_T4_CC4 ADC_EXTERNALTRIG_T4_CC4
<>	128:9bcdf88f62b0	343	#define ADC_EXTERNALTRIGCONV_T4_TRGO ADC_EXTERNALTRIG_T4_TRGO
<>	128:9bcdf88f62b0	344	#define ADC_EXTERNALTRIGCONV_T6_TRGO ADC_EXTERNALTRIG_T6_TRGO
<>	128:9bcdf88f62b0	345	#define ADC_EXTERNALTRIGCONV_T9_CC2 ADC_EXTERNALTRIG_T9_CC2
<>	128:9bcdf88f62b0	346	#define ADC_EXTERNALTRIGCONV_T9_TRGO ADC_EXTERNALTRIG_T9_TRGO
<>	128:9bcdf88f62b0	347	#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC_EXTERNALTRIG_EXT_IT11
<>	128:9bcdf88f62b0	348	#define ADC_SOFTWARE_START ((uint32_t)0x00000010)
<>	128:9bcdf88f62b0	349	/**
<>	128:9bcdf88f62b0	350	* @}
<>	128:9bcdf88f62b0	351	*/
<>	128:9bcdf88f62b0	352
<>	128:9bcdf88f62b0	353	/** @defgroup ADC_EOCSelection ADC EOCSelection
<>	128:9bcdf88f62b0	354	* @{
<>	128:9bcdf88f62b0	355	*/
<>	128:9bcdf88f62b0	356	#define ADC_EOC_SEQ_CONV ((uint32_t)0x00000000)
<>	128:9bcdf88f62b0	357	#define ADC_EOC_SINGLE_CONV ((uint32_t)ADC_CR2_EOCS)
<>	128:9bcdf88f62b0	358	/**
<>	128:9bcdf88f62b0	359	* @}
<>	128:9bcdf88f62b0	360	*/
<>	128:9bcdf88f62b0	361
<>	128:9bcdf88f62b0	362	/** @defgroup ADC_LowPowerAutoWait ADC LowPowerAutoWait
<>	128:9bcdf88f62b0	363	* @{
<>	128:9bcdf88f62b0	364	*/
<>	128:9bcdf88f62b0	365	/!< Note : For compatibility with other STM32 devices with ADC autowait /
<>	128:9bcdf88f62b0	366	/* feature limited to enable or disable settings: */
<>	128:9bcdf88f62b0	367	/* Setting "ADC_AUTOWAIT_UNTIL_DATA_READ" is equivalent to "ENABLE". */
<>	128:9bcdf88f62b0	368
<>	128:9bcdf88f62b0	369	#define ADC_AUTOWAIT_DISABLE ((uint32_t)0x00000000)
<>	128:9bcdf88f62b0	370	#define ADC_AUTOWAIT_UNTIL_DATA_READ ((uint32_t)( ADC_CR2_DELS_0)) /!< Insert a delay between ADC conversions: infinite delay, until the result of previous conversion is read /
<>	128:9bcdf88f62b0	371	#define ADC_AUTOWAIT_7_APBCLOCKCYCLES ((uint32_t)( ADC_CR2_DELS_1 )) /!< Insert a delay between ADC conversions: 7 APB clock cycles /
<>	128:9bcdf88f62b0	372	#define ADC_AUTOWAIT_15_APBCLOCKCYCLES ((uint32_t)( ADC_CR2_DELS_1 \| ADC_CR2_DELS_0)) /!< Insert a delay between ADC conversions: 15 APB clock cycles /
<>	128:9bcdf88f62b0	373	#define ADC_AUTOWAIT_31_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 )) /!< Insert a delay between ADC conversions: 31 APB clock cycles /
<>	128:9bcdf88f62b0	374	#define ADC_AUTOWAIT_63_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 \| ADC_CR2_DELS_0)) /!< Insert a delay between ADC conversions: 63 APB clock cycles /
<>	128:9bcdf88f62b0	375	#define ADC_AUTOWAIT_127_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 \| ADC_CR2_DELS_1 )) /!< Insert a delay between ADC conversions: 127 APB clock cycles /
<>	128:9bcdf88f62b0	376	#define ADC_AUTOWAIT_255_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 \| ADC_CR2_DELS_1 \| ADC_CR2_DELS_0)) /!< Insert a delay between ADC conversions: 255 APB clock cycles /
<>	128:9bcdf88f62b0	377
<>	128:9bcdf88f62b0	378	/**
<>	128:9bcdf88f62b0	379	* @}
<>	128:9bcdf88f62b0	380	*/
<>	128:9bcdf88f62b0	381
<>	128:9bcdf88f62b0	382	/** @defgroup ADC_LowPowerAutoPowerOff ADC LowPowerAutoPowerOff
<>	128:9bcdf88f62b0	383	* @{
<>	128:9bcdf88f62b0	384	*/
<>	128:9bcdf88f62b0	385	#define ADC_AUTOPOWEROFF_DISABLE ((uint32_t)0x00000000)
<>	128:9bcdf88f62b0	386	#define ADC_AUTOPOWEROFF_IDLE_PHASE ((uint32_t)ADC_CR1_PDI) /!< ADC power off when ADC is not converting (idle phase) /
<>	128:9bcdf88f62b0	387	#define ADC_AUTOPOWEROFF_DELAY_PHASE ((uint32_t)ADC_CR1_PDD) /!< ADC power off when a delay is inserted between conversions (see parameter ADC_LowPowerAutoWait) /
<>	128:9bcdf88f62b0	388	#define ADC_AUTOPOWEROFF_IDLE_DELAY_PHASES ((uint32_t)(ADC_CR1_PDI \| ADC_CR1_PDD)) /!< ADC power off when ADC is not converting (idle phase) and when a delay is inserted between conversions /
<>	128:9bcdf88f62b0	389	/**
<>	128:9bcdf88f62b0	390	* @}
<>	128:9bcdf88f62b0	391	*/
<>	128:9bcdf88f62b0	392
<>	128:9bcdf88f62b0	393
<>	128:9bcdf88f62b0	394	/** @defgroup ADC_ChannelsBank ADC ChannelsBank
<>	128:9bcdf88f62b0	395	* @{
<>	128:9bcdf88f62b0	396	*/
<>	128:9bcdf88f62b0	397	#if defined(STM32L100xC) \|\| defined (STM32L151xC) \|\| defined (STM32L152xC) \|\| defined (STM32L162xC) \|\| defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD) \|\| defined(STM32L151xE) \|\| defined(STM32L151xDX) \|\| defined (STM32L152xE) \|\| defined (STM32L152xDX) \|\| defined (STM32L162xE) \|\| defined (STM32L162xDX)
<>	128:9bcdf88f62b0	398	#define ADC_CHANNELS_BANK_A ((uint32_t)0x00000000)
<>	128:9bcdf88f62b0	399	#define ADC_CHANNELS_BANK_B ((uint32_t)ADC_CR2_CFG)
<>	128:9bcdf88f62b0	400
<>	128:9bcdf88f62b0	401	#define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A) \|\| \
<>	128:9bcdf88f62b0	402	((BANK) == ADC_CHANNELS_BANK_B) )
<>	128:9bcdf88f62b0	403	#else
<>	128:9bcdf88f62b0	404	#define ADC_CHANNELS_BANK_A ((uint32_t)0x00000000)
<>	128:9bcdf88f62b0	405
<>	128:9bcdf88f62b0	406	#define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A))
<>	128:9bcdf88f62b0	407	#endif /* STM32L100xC \|\| STM32L151xC \|\| STM32L152xC \|\| STM32L162xC \|\| STM32L151xCA \|\| STM32L151xD \|\| STM32L152xCA \|\| STM32L152xD \|\| STM32L162xCA \|\| STM32L162xD \|\| STM32L151xE \|\| STM32L151xDX \|\| STM32L152xE \|\| STM32L152xDX \|\| STM32L162xE \|\| STM32L162xDX */
<>	128:9bcdf88f62b0	408	/**
<>	128:9bcdf88f62b0	409	* @}
<>	128:9bcdf88f62b0	410	*/
<>	128:9bcdf88f62b0	411
<>	128:9bcdf88f62b0	412	/** @defgroup ADC_channels ADC channels
<>	128:9bcdf88f62b0	413	* @{
<>	128:9bcdf88f62b0	414	*/
<>	128:9bcdf88f62b0	415	/* Note: Depending on devices, some channels may not be available on package */
<>	128:9bcdf88f62b0	416	/* pins. Refer to device datasheet for channels availability. */
<>	128:9bcdf88f62b0	417	#define ADC_CHANNEL_0 ((uint32_t)0x00000000) /* Channel different in bank A and bank B */
<>	128:9bcdf88f62b0	418	#define ADC_CHANNEL_1 ((uint32_t)( ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */
<>	128:9bcdf88f62b0	419	#define ADC_CHANNEL_2 ((uint32_t)( ADC_SQR5_SQ1_1 )) /* Channel different in bank A and bank B */
<>	128:9bcdf88f62b0	420	#define ADC_CHANNEL_3 ((uint32_t)( ADC_SQR5_SQ1_1 \| ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */
<>	128:9bcdf88f62b0	421	#define ADC_CHANNEL_4 ((uint32_t)( ADC_SQR5_SQ1_2 )) /* Direct (fast) channel */
<>	128:9bcdf88f62b0	422	#define ADC_CHANNEL_5 ((uint32_t)( ADC_SQR5_SQ1_2 \| ADC_SQR5_SQ1_0)) /* Direct (fast) channel */
<>	128:9bcdf88f62b0	423	#define ADC_CHANNEL_6 ((uint32_t)( ADC_SQR5_SQ1_2 \| ADC_SQR5_SQ1_1 )) /* Channel different in bank A and bank B */
<>	128:9bcdf88f62b0	424	#define ADC_CHANNEL_7 ((uint32_t)( ADC_SQR5_SQ1_2 \| ADC_SQR5_SQ1_1 \| ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */
<>	128:9bcdf88f62b0	425	#define ADC_CHANNEL_8 ((uint32_t)( ADC_SQR5_SQ1_3 )) /* Channel different in bank A and bank B */
<>	128:9bcdf88f62b0	426	#define ADC_CHANNEL_9 ((uint32_t)( ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */
<>	128:9bcdf88f62b0	427	#define ADC_CHANNEL_10 ((uint32_t)( ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_1 )) /* Channel different in bank A and bank B */
<>	128:9bcdf88f62b0	428	#define ADC_CHANNEL_11 ((uint32_t)( ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_1 \| ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */
<>	128:9bcdf88f62b0	429	#define ADC_CHANNEL_12 ((uint32_t)( ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_2 )) /* Channel different in bank A and bank B */
<>	128:9bcdf88f62b0	430	#define ADC_CHANNEL_13 ((uint32_t)( ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_2 \| ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
<>	128:9bcdf88f62b0	431	#define ADC_CHANNEL_14 ((uint32_t)( ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_2 \| ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */
<>	128:9bcdf88f62b0	432	#define ADC_CHANNEL_15 ((uint32_t)( ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_2 \| ADC_SQR5_SQ1_1 \| ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
<>	128:9bcdf88f62b0	433	#define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR5_SQ1_4 )) /* Channel common to both bank A and bank B */
<>	128:9bcdf88f62b0	434	#define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
<>	128:9bcdf88f62b0	435	#define ADC_CHANNEL_18 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */
<>	128:9bcdf88f62b0	436	#define ADC_CHANNEL_19 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_1 \| ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
<>	128:9bcdf88f62b0	437	#define ADC_CHANNEL_20 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_2 )) /* Channel common to both bank A and bank B */
<>	128:9bcdf88f62b0	438	#define ADC_CHANNEL_21 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_2 \| ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
<>	128:9bcdf88f62b0	439	#define ADC_CHANNEL_22 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_2 \| ADC_SQR5_SQ1_1 )) /* Direct (fast) channel */
<>	128:9bcdf88f62b0	440	#define ADC_CHANNEL_23 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_2 \| ADC_SQR5_SQ1_1 \| ADC_SQR5_SQ1_0)) /* Direct (fast) channel */
<>	128:9bcdf88f62b0	441	#define ADC_CHANNEL_24 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_3 )) /* Direct (fast) channel */
<>	128:9bcdf88f62b0	442	#define ADC_CHANNEL_25 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_0)) /* Direct (fast) channel */
<>	128:9bcdf88f62b0	443	#define ADC_CHANNEL_26 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */
<>	128:9bcdf88f62b0	444	#if defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD) \|\| defined(STM32L151xE) \|\| defined(STM32L151xDX) \|\| defined (STM32L152xE) \|\| defined (STM32L152xDX) \|\| defined (STM32L162xE) \|\| defined (STM32L162xDX)
<>	128:9bcdf88f62b0	445	#define ADC_CHANNEL_27 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_1 \| ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
<>	128:9bcdf88f62b0	446	#define ADC_CHANNEL_28 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_2 )) /* Channel common to both bank A and bank B */
<>	128:9bcdf88f62b0	447	#define ADC_CHANNEL_29 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_2 \| ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
<>	128:9bcdf88f62b0	448	#define ADC_CHANNEL_30 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_2 \| ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */
<>	128:9bcdf88f62b0	449	#define ADC_CHANNEL_31 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_2 \| ADC_SQR5_SQ1_1 \| ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
<>	128:9bcdf88f62b0	450	#endif /* STM32L151xCA \|\| STM32L151xD \|\| STM32L152xCA \|\| STM32L152xD \|\| STM32L162xCA \|\| STM32L162xD \|\| STM32L151xE \|\| STM32L151xDX \|\| STM32L152xE \|\| STM32L152xDX \|\| STM32L162xE \|\| STM32L162xDX */
<>	128:9bcdf88f62b0	451
<>	128:9bcdf88f62b0	452	#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 /* ADC internal channel (no connection on device pin). Channel common to both bank A and bank B. */
<>	128:9bcdf88f62b0	453	#define ADC_CHANNEL_VREFINT ADC_CHANNEL_17 /* ADC internal channel (no connection on device pin). Channel common to both bank A and bank B. */
<>	128:9bcdf88f62b0	454	#define ADC_CHANNEL_VCOMP ADC_CHANNEL_26 /* ADC internal channel (no connection on device pin). Channel common to both bank A and bank B. */
<>	128:9bcdf88f62b0	455
<>	128:9bcdf88f62b0	456	#if defined(STM32L100xC) \|\| defined (STM32L151xC) \|\| defined (STM32L152xC) \|\| defined (STM32L162xC) \|\| defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD) \|\| defined(STM32L151xE) \|\| defined(STM32L151xDX) \|\| defined (STM32L152xE) \|\| defined (STM32L152xDX) \|\| defined (STM32L162xE) \|\| defined (STM32L162xDX)
<>	128:9bcdf88f62b0	457	#define ADC_CHANNEL_VOPAMP1 ADC_CHANNEL_3 /* Internal connection from OPAMP1 output to ADC switch matrix */
<>	128:9bcdf88f62b0	458	#define ADC_CHANNEL_VOPAMP2 ADC_CHANNEL_8 /* Internal connection from OPAMP2 output to ADC switch matrix */
<>	128:9bcdf88f62b0	459	#if defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD)
<>	128:9bcdf88f62b0	460	#define ADC_CHANNEL_VOPAMP3 ADC_CHANNEL_13 /* Internal connection from OPAMP3 output to ADC switch matrix */
<>	128:9bcdf88f62b0	461	#endif /* STM32L151xCA \|\| STM32L151xD \|\| STM32L152xCA \|\| STM32L152xD \|\| STM32L162xCA \|\| STM32L162xD */
<>	128:9bcdf88f62b0	462	#endif /* STM32L100xC \|\| STM32L151xC \|\| STM32L152xC \|\| STM32L162xC \|\| STM32L151xCA \|\| STM32L151xD \|\| STM32L152xCA \|\| STM32L152xD \|\| STM32L162xCA \|\| STM32L162xD \|\| STM32L151xE \|\| STM32L151xDX \|\| STM32L152xE \|\| STM32L152xDX \|\| STM32L162xE \|\| STM32L162xDX */
<>	128:9bcdf88f62b0	463	/**
<>	128:9bcdf88f62b0	464	* @}
<>	128:9bcdf88f62b0	465	*/
<>	128:9bcdf88f62b0	466
<>	128:9bcdf88f62b0	467	/** @defgroup ADC_sampling_times ADC sampling times
<>	128:9bcdf88f62b0	468	* @{
<>	128:9bcdf88f62b0	469	*/
<>	128:9bcdf88f62b0	470	#define ADC_SAMPLETIME_4CYCLES ((uint32_t)0x00000000) /!< Sampling time 4 ADC clock cycles /
<>	128:9bcdf88f62b0	471	#define ADC_SAMPLETIME_9CYCLES ((uint32_t) ADC_SMPR3_SMP0_0) /!< Sampling time 9 ADC clock cycles /
<>	128:9bcdf88f62b0	472	#define ADC_SAMPLETIME_16CYCLES ((uint32_t) ADC_SMPR3_SMP0_1) /!< Sampling time 16 ADC clock cycles /
<>	128:9bcdf88f62b0	473	#define ADC_SAMPLETIME_24CYCLES ((uint32_t)(ADC_SMPR3_SMP0_1 \| ADC_SMPR3_SMP0_0)) /!< Sampling time 24 ADC clock cycles /
<>	128:9bcdf88f62b0	474	#define ADC_SAMPLETIME_48CYCLES ((uint32_t) ADC_SMPR3_SMP0_2) /!< Sampling time 48 ADC clock cycles /
<>	128:9bcdf88f62b0	475	#define ADC_SAMPLETIME_96CYCLES ((uint32_t)(ADC_SMPR3_SMP0_2 \| ADC_SMPR3_SMP0_0)) /!< Sampling time 96 ADC clock cycles /
<>	128:9bcdf88f62b0	476	#define ADC_SAMPLETIME_192CYCLES ((uint32_t)(ADC_SMPR3_SMP0_2 \| ADC_SMPR3_SMP0_1)) /!< Sampling time 192 ADC clock cycles /
<>	128:9bcdf88f62b0	477	#define ADC_SAMPLETIME_384CYCLES ((uint32_t) ADC_SMPR3_SMP0) /!< Sampling time 384 ADC clock cycles /
<>	128:9bcdf88f62b0	478	/**
<>	128:9bcdf88f62b0	479	* @}
<>	128:9bcdf88f62b0	480	*/
<>	128:9bcdf88f62b0	481
<>	128:9bcdf88f62b0	482	/** @defgroup ADC_sampling_times_all_channels ADC sampling times all channels
<>	128:9bcdf88f62b0	483	* @{
<>	128:9bcdf88f62b0	484	*/
<>	128:9bcdf88f62b0	485	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT2 \
<>	128:9bcdf88f62b0	486	(ADC_SMPR3_SMP9_2 \| ADC_SMPR3_SMP8_2 \| ADC_SMPR3_SMP7_2 \| ADC_SMPR3_SMP6_2 \| \
<>	128:9bcdf88f62b0	487	ADC_SMPR3_SMP5_2 \| ADC_SMPR3_SMP4_2 \| ADC_SMPR3_SMP3_2 \| ADC_SMPR3_SMP2_2 \| \
<>	128:9bcdf88f62b0	488	ADC_SMPR3_SMP1_2 \| ADC_SMPR3_SMP0_2)
<>	128:9bcdf88f62b0	489	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \
<>	128:9bcdf88f62b0	490	(ADC_SMPR2_SMP19_2 \| ADC_SMPR2_SMP18_2 \| ADC_SMPR2_SMP17_2 \| ADC_SMPR2_SMP16_2 \| \
<>	128:9bcdf88f62b0	491	ADC_SMPR2_SMP15_2 \| ADC_SMPR2_SMP14_2 \| ADC_SMPR2_SMP13_2 \| ADC_SMPR2_SMP12_2 \| \
<>	128:9bcdf88f62b0	492	ADC_SMPR2_SMP11_2 \| ADC_SMPR2_SMP10_2)
<>	128:9bcdf88f62b0	493	#if defined(STM32L100xB) \|\| defined (STM32L151xB) \|\| defined (STM32L152xB) \|\| defined(STM32L100xBA) \|\| defined (STM32L151xBA) \|\| defined (STM32L152xBA) \|\| defined(STM32L100xC) \|\| defined (STM32L151xC) \|\| defined (STM32L152xC) \|\| defined (STM32L162xC)
<>	128:9bcdf88f62b0	494	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \
<>	128:9bcdf88f62b0	495	(ADC_SMPR1_SMP26_2 \| ADC_SMPR1_SMP25_2 \| ADC_SMPR1_SMP24_2 \| ADC_SMPR1_SMP23_2 \| \
<>	128:9bcdf88f62b0	496	ADC_SMPR1_SMP22_2 \| ADC_SMPR1_SMP21_2 \| ADC_SMPR1_SMP20_2)
<>	128:9bcdf88f62b0	497	#endif /* STM32L100xB \|\| STM32L151xB \|\| STM32L152xB \|\| STM32L100xBA \|\| STM32L151xBA \|\| STM32L152xBA \|\| STM32L100xC \|\| STM32L151xC \|\| STM32L152xC \|\| STM32L162xC */
<>	128:9bcdf88f62b0	498	#if defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD) \|\| defined(STM32L151xE) \|\| defined(STM32L151xDX) \|\| defined (STM32L152xE) \|\| defined (STM32L152xDX) \|\| defined (STM32L162xE) \|\| defined (STM32L162xDX)
<>	128:9bcdf88f62b0	499	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \
<>	128:9bcdf88f62b0	500	(ADC_SMPR1_SMP29_2 \| ADC_SMPR1_SMP28_2 \| ADC_SMPR1_SMP27_2 \| ADC_SMPR1_SMP26_2 \| \
<>	128:9bcdf88f62b0	501	ADC_SMPR1_SMP25_2 \| ADC_SMPR1_SMP24_2 \| ADC_SMPR1_SMP23_2 \| ADC_SMPR1_SMP22_2 \| \
<>	128:9bcdf88f62b0	502	ADC_SMPR1_SMP21_2 \| ADC_SMPR1_SMP20_2)
<>	128:9bcdf88f62b0	503	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT2 \
<>	128:9bcdf88f62b0	504	(ADC_SMPR0_SMP31_2 \| ADC_SMPR0_SMP30_2 )
<>	128:9bcdf88f62b0	505	#endif /* STM32L151xCA \|\| STM32L151xD \|\| STM32L152xCA \|\| STM32L152xD \|\| STM32L162xCA \|\| STM32L162xD \|\| STM32L151xE \|\| STM32L151xDX \|\| STM32L152xE \|\| STM32L152xDX \|\| STM32L162xE \|\| STM32L162xDX */
<>	128:9bcdf88f62b0	506
<>	128:9bcdf88f62b0	507	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT1 \
<>	128:9bcdf88f62b0	508	(ADC_SMPR3_SMP9_1 \| ADC_SMPR3_SMP8_1 \| ADC_SMPR3_SMP7_1 \| ADC_SMPR3_SMP6_1 \| \
<>	128:9bcdf88f62b0	509	ADC_SMPR3_SMP5_1 \| ADC_SMPR3_SMP4_1 \| ADC_SMPR3_SMP3_1 \| ADC_SMPR3_SMP2_1 \| \
<>	128:9bcdf88f62b0	510	ADC_SMPR3_SMP1_1 \| ADC_SMPR3_SMP0_1)
<>	128:9bcdf88f62b0	511	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \
<>	128:9bcdf88f62b0	512	(ADC_SMPR2_SMP19_1 \| ADC_SMPR2_SMP18_1 \| ADC_SMPR2_SMP17_1 \| ADC_SMPR2_SMP16_1 \| \
<>	128:9bcdf88f62b0	513	ADC_SMPR2_SMP15_1 \| ADC_SMPR2_SMP14_1 \| ADC_SMPR2_SMP13_1 \| ADC_SMPR2_SMP12_1 \| \
<>	128:9bcdf88f62b0	514	ADC_SMPR2_SMP11_1 \| ADC_SMPR2_SMP10_1)
<>	128:9bcdf88f62b0	515	#if defined(STM32L100xB) \|\| defined (STM32L151xB) \|\| defined (STM32L152xB) \|\| defined(STM32L100xBA) \|\| defined (STM32L151xBA) \|\| defined (STM32L152xBA) \|\| defined(STM32L100xC) \|\| defined (STM32L151xC) \|\| defined (STM32L152xC) \|\| defined (STM32L162xC)
<>	128:9bcdf88f62b0	516	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \
<>	128:9bcdf88f62b0	517	(ADC_SMPR1_SMP26_1 \| ADC_SMPR1_SMP25_1 \| ADC_SMPR1_SMP24_1 \| ADC_SMPR1_SMP23_1 \| \
<>	128:9bcdf88f62b0	518	ADC_SMPR1_SMP22_1 \| ADC_SMPR1_SMP21_1 \| ADC_SMPR1_SMP20_1)
<>	128:9bcdf88f62b0	519	#endif /* STM32L100xB \|\| STM32L151xB \|\| STM32L152xB \|\| STM32L100xBA \|\| STM32L151xBA \|\| STM32L152xBA \|\| STM32L100xC \|\| STM32L151xC \|\| STM32L152xC \|\| STM32L162xC */
<>	128:9bcdf88f62b0	520	#if defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD) \|\| defined(STM32L151xE) \|\| defined(STM32L151xDX) \|\| defined (STM32L152xE) \|\| defined (STM32L152xDX) \|\| defined (STM32L162xE) \|\| defined (STM32L162xDX)
<>	128:9bcdf88f62b0	521	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \
<>	128:9bcdf88f62b0	522	(ADC_SMPR1_SMP29_1 \| ADC_SMPR1_SMP28_1 \| ADC_SMPR1_SMP27_1 \| ADC_SMPR1_SMP26_1 \| \
<>	128:9bcdf88f62b0	523	ADC_SMPR1_SMP25_1 \| ADC_SMPR1_SMP24_1 \| ADC_SMPR1_SMP23_1 \| ADC_SMPR1_SMP22_1 \| \
<>	128:9bcdf88f62b0	524	ADC_SMPR1_SMP21_1 \| ADC_SMPR1_SMP20_1)
<>	128:9bcdf88f62b0	525	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT1 \
<>	128:9bcdf88f62b0	526	(ADC_SMPR0_SMP31_1 \| ADC_SMPR0_SMP30_1 )
<>	128:9bcdf88f62b0	527	#endif /* STM32L151xCA \|\| STM32L151xD \|\| STM32L152xCA \|\| STM32L152xD \|\| STM32L162xCA \|\| STM32L162xD \|\| STM32L151xE \|\| STM32L151xDX \|\| STM32L152xE \|\| STM32L152xDX \|\| STM32L162xE \|\| STM32L162xDX */
<>	128:9bcdf88f62b0	528
<>	128:9bcdf88f62b0	529	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT0 \
<>	128:9bcdf88f62b0	530	(ADC_SMPR3_SMP9_0 \| ADC_SMPR3_SMP8_0 \| ADC_SMPR3_SMP7_0 \| ADC_SMPR3_SMP6_0 \| \
<>	128:9bcdf88f62b0	531	ADC_SMPR3_SMP5_0 \| ADC_SMPR3_SMP4_0 \| ADC_SMPR3_SMP3_0 \| ADC_SMPR3_SMP2_0 \| \
<>	128:9bcdf88f62b0	532	ADC_SMPR3_SMP1_0 \| ADC_SMPR3_SMP0_0)
<>	128:9bcdf88f62b0	533	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 \
<>	128:9bcdf88f62b0	534	(ADC_SMPR2_SMP19_0 \| ADC_SMPR2_SMP18_0 \| ADC_SMPR2_SMP17_0 \| ADC_SMPR2_SMP16_0 \| \
<>	128:9bcdf88f62b0	535	ADC_SMPR2_SMP15_0 \| ADC_SMPR2_SMP14_0 \| ADC_SMPR2_SMP13_0 \| ADC_SMPR2_SMP12_0 \| \
<>	128:9bcdf88f62b0	536	ADC_SMPR2_SMP11_0 \| ADC_SMPR2_SMP10_0)
<>	128:9bcdf88f62b0	537	#if defined(STM32L100xB) \|\| defined (STM32L151xB) \|\| defined (STM32L152xB) \|\| defined(STM32L100xBA) \|\| defined (STM32L151xBA) \|\| defined (STM32L152xBA) \|\| defined(STM32L100xC) \|\| defined (STM32L151xC) \|\| defined (STM32L152xC) \|\| defined (STM32L162xC)
<>	128:9bcdf88f62b0	538	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \
<>	128:9bcdf88f62b0	539	(ADC_SMPR1_SMP26_0 \| ADC_SMPR1_SMP25_0 \| ADC_SMPR1_SMP24_0 \| ADC_SMPR1_SMP23_0 \| \
<>	128:9bcdf88f62b0	540	ADC_SMPR1_SMP22_0 \| ADC_SMPR1_SMP21_0 \| ADC_SMPR1_SMP20_0)
<>	128:9bcdf88f62b0	541	#endif /* STM32L100xB \|\| STM32L151xB \|\| STM32L152xB \|\| STM32L100xBA \|\| STM32L151xBA \|\| STM32L152xBA \|\| STM32L100xC \|\| STM32L151xC \|\| STM32L152xC \|\| STM32L162xC */
<>	128:9bcdf88f62b0	542	#if defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD) \|\| defined(STM32L151xE) \|\| defined(STM32L151xDX) \|\| defined (STM32L152xE) \|\| defined (STM32L152xDX) \|\| defined (STM32L162xE) \|\| defined (STM32L162xDX)
<>	128:9bcdf88f62b0	543	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \
<>	128:9bcdf88f62b0	544	(ADC_SMPR1_SMP29_0 \| ADC_SMPR1_SMP28_0 \| ADC_SMPR1_SMP27_0 \| ADC_SMPR1_SMP26_0 \| \
<>	128:9bcdf88f62b0	545	ADC_SMPR1_SMP25_0 \| ADC_SMPR1_SMP24_0 \| ADC_SMPR1_SMP23_0 \| ADC_SMPR1_SMP22_0 \| \
<>	128:9bcdf88f62b0	546	ADC_SMPR1_SMP21_0 \| ADC_SMPR1_SMP20_0)
<>	128:9bcdf88f62b0	547	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT0 \
<>	128:9bcdf88f62b0	548	(ADC_SMPR0_SMP31_0 \| ADC_SMPR0_SMP30_0 )
<>	128:9bcdf88f62b0	549	#endif /* STM32L151xCA \|\| STM32L151xD \|\| STM32L152xCA \|\| STM32L152xD \|\| STM32L162xCA \|\| STM32L162xD \|\| STM32L151xE \|\| STM32L151xDX \|\| STM32L152xE \|\| STM32L152xDX \|\| STM32L162xE \|\| STM32L162xDX */
<>	128:9bcdf88f62b0	550	/**
<>	128:9bcdf88f62b0	551	* @}
<>	128:9bcdf88f62b0	552	*/
<>	128:9bcdf88f62b0	553
<>	128:9bcdf88f62b0	554	/** @defgroup ADC_regular_rank ADC rank into regular group
<>	128:9bcdf88f62b0	555	* @{
<>	128:9bcdf88f62b0	556	*/
<>	128:9bcdf88f62b0	557	#define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001)
<>	128:9bcdf88f62b0	558	#define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002)
<>	128:9bcdf88f62b0	559	#define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003)
<>	128:9bcdf88f62b0	560	#define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004)
<>	128:9bcdf88f62b0	561	#define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005)
<>	128:9bcdf88f62b0	562	#define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006)
<>	128:9bcdf88f62b0	563	#define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007)
<>	128:9bcdf88f62b0	564	#define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008)
<>	128:9bcdf88f62b0	565	#define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009)
<>	128:9bcdf88f62b0	566	#define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A)
<>	128:9bcdf88f62b0	567	#define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B)
<>	128:9bcdf88f62b0	568	#define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C)
<>	128:9bcdf88f62b0	569	#define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D)
<>	128:9bcdf88f62b0	570	#define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E)
<>	128:9bcdf88f62b0	571	#define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F)
<>	128:9bcdf88f62b0	572	#define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010)
<>	128:9bcdf88f62b0	573	#define ADC_REGULAR_RANK_17 ((uint32_t)0x00000011)
<>	128:9bcdf88f62b0	574	#define ADC_REGULAR_RANK_18 ((uint32_t)0x00000012)
<>	128:9bcdf88f62b0	575	#define ADC_REGULAR_RANK_19 ((uint32_t)0x00000013)
<>	128:9bcdf88f62b0	576	#define ADC_REGULAR_RANK_20 ((uint32_t)0x00000014)
<>	128:9bcdf88f62b0	577	#define ADC_REGULAR_RANK_21 ((uint32_t)0x00000015)
<>	128:9bcdf88f62b0	578	#define ADC_REGULAR_RANK_22 ((uint32_t)0x00000016)
<>	128:9bcdf88f62b0	579	#define ADC_REGULAR_RANK_23 ((uint32_t)0x00000017)
<>	128:9bcdf88f62b0	580	#define ADC_REGULAR_RANK_24 ((uint32_t)0x00000018)
<>	128:9bcdf88f62b0	581	#define ADC_REGULAR_RANK_25 ((uint32_t)0x00000019)
<>	128:9bcdf88f62b0	582	#define ADC_REGULAR_RANK_26 ((uint32_t)0x0000001A)
<>	128:9bcdf88f62b0	583	#define ADC_REGULAR_RANK_27 ((uint32_t)0x0000001B)
<>	128:9bcdf88f62b0	584	#if defined(STM32L100xC) \|\| defined (STM32L151xC) \|\| defined (STM32L152xC) \|\| defined (STM32L162xC) \|\| defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD) \|\| defined(STM32L151xE) \|\| defined(STM32L151xDX) \|\| defined (STM32L152xE) \|\| defined (STM32L152xDX) \|\| defined (STM32L162xE) \|\| defined (STM32L162xDX)
<>	128:9bcdf88f62b0	585	#define ADC_REGULAR_RANK_28 ((uint32_t)0x0000001C)
<>	128:9bcdf88f62b0	586	#endif /* STM32L100xC \|\| STM32L151xC \|\| STM32L152xC \|\| STM32L162xC \|\| STM32L151xCA \|\| STM32L151xD \|\| STM32L152xCA \|\| STM32L152xD \|\| STM32L162xCA \|\| STM32L162xD \|\| STM32L151xE \|\| STM32L151xDX \|\| STM32L152xE \|\| STM32L152xDX \|\| STM32L162xE \|\| STM32L162xDX */
<>	128:9bcdf88f62b0	587	/**
<>	128:9bcdf88f62b0	588	* @}
<>	128:9bcdf88f62b0	589	*/
<>	128:9bcdf88f62b0	590
<>	128:9bcdf88f62b0	591	/** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode
<>	128:9bcdf88f62b0	592	* @{
<>	128:9bcdf88f62b0	593	*/
<>	128:9bcdf88f62b0	594	#define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000)
<>	128:9bcdf88f62b0	595	#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL \| ADC_CR1_AWDEN))
<>	128:9bcdf88f62b0	596	#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL \| ADC_CR1_JAWDEN))
<>	128:9bcdf88f62b0	597	#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL \| ADC_CR1_AWDEN \| ADC_CR1_JAWDEN))
<>	128:9bcdf88f62b0	598	#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CR1_AWDEN)
<>	128:9bcdf88f62b0	599	#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CR1_JAWDEN)
<>	128:9bcdf88f62b0	600	#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN \| ADC_CR1_JAWDEN))
<>	128:9bcdf88f62b0	601	/**
<>	128:9bcdf88f62b0	602	* @}
<>	128:9bcdf88f62b0	603	*/
<>	128:9bcdf88f62b0	604
<>	128:9bcdf88f62b0	605	/** @defgroup ADC_conversion_group ADC conversion group
<>	128:9bcdf88f62b0	606	* @{
<>	128:9bcdf88f62b0	607	*/
<>	128:9bcdf88f62b0	608	#define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC))
<>	128:9bcdf88f62b0	609	#define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC))
<>	128:9bcdf88f62b0	610	#define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC \| ADC_FLAG_JEOC))
<>	128:9bcdf88f62b0	611	/**
<>	128:9bcdf88f62b0	612	* @}
<>	128:9bcdf88f62b0	613	*/
<>	128:9bcdf88f62b0	614
<>	128:9bcdf88f62b0	615	/** @defgroup ADC_Event_type ADC Event type
<>	128:9bcdf88f62b0	616	* @{
<>	128:9bcdf88f62b0	617	*/
<>	128:9bcdf88f62b0	618	#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /!< ADC Analog watchdog event /
<>	128:9bcdf88f62b0	619	#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) /!< ADC overrun event /
<>	128:9bcdf88f62b0	620	/**
<>	128:9bcdf88f62b0	621	* @}
<>	128:9bcdf88f62b0	622	*/
<>	128:9bcdf88f62b0	623
<>	128:9bcdf88f62b0	624	/** @defgroup ADC_interrupts_definition ADC interrupts definition
<>	128:9bcdf88f62b0	625	* @{
<>	128:9bcdf88f62b0	626	*/
<>	128:9bcdf88f62b0	627	#define ADC_IT_EOC ADC_CR1_EOCIE /!< ADC End of Regular Conversion interrupt source /
<>	128:9bcdf88f62b0	628	#define ADC_IT_JEOC ADC_CR1_JEOCIE /!< ADC End of Injected Conversion interrupt source /
<>	128:9bcdf88f62b0	629	#define ADC_IT_AWD ADC_CR1_AWDIE /!< ADC Analog watchdog interrupt source /
<>	128:9bcdf88f62b0	630	#define ADC_IT_OVR ADC_CR1_OVRIE /!< ADC overrun interrupt source /
<>	128:9bcdf88f62b0	631	/**
<>	128:9bcdf88f62b0	632	* @}
<>	128:9bcdf88f62b0	633	*/
<>	128:9bcdf88f62b0	634
<>	128:9bcdf88f62b0	635	/** @defgroup ADC_flags_definition ADC flags definition
<>	128:9bcdf88f62b0	636	* @{
<>	128:9bcdf88f62b0	637	*/
<>	128:9bcdf88f62b0	638	#define ADC_FLAG_AWD ADC_SR_AWD /!< ADC Analog watchdog flag /
<>	128:9bcdf88f62b0	639	#define ADC_FLAG_EOC ADC_SR_EOC /!< ADC End of Regular conversion flag /
<>	128:9bcdf88f62b0	640	#define ADC_FLAG_JEOC ADC_SR_JEOC /!< ADC End of Injected conversion flag /
<>	128:9bcdf88f62b0	641	#define ADC_FLAG_JSTRT ADC_SR_JSTRT /!< ADC Injected group start flag /
<>	128:9bcdf88f62b0	642	#define ADC_FLAG_STRT ADC_SR_STRT /!< ADC Regular group start flag /
<>	128:9bcdf88f62b0	643	#define ADC_FLAG_OVR ADC_SR_OVR /!< ADC overrun flag /
<>	128:9bcdf88f62b0	644	#define ADC_FLAG_ADONS ADC_SR_ADONS /!< ADC ready status flag /
<>	128:9bcdf88f62b0	645	#define ADC_FLAG_RCNR ADC_SR_RCNR /!< ADC Regular group ready status flag /
<>	128:9bcdf88f62b0	646	#define ADC_FLAG_JCNR ADC_SR_JCNR /!< ADC Injected group ready status flag /
<>	128:9bcdf88f62b0	647	/**
<>	128:9bcdf88f62b0	648	* @}
<>	128:9bcdf88f62b0	649	*/
<>	128:9bcdf88f62b0	650
<>	128:9bcdf88f62b0	651	/**
<>	128:9bcdf88f62b0	652	* @}
<>	128:9bcdf88f62b0	653	*/
<>	128:9bcdf88f62b0	654
<>	128:9bcdf88f62b0	655
<>	128:9bcdf88f62b0	656	/* Private constants ---------------------------------------------------------*/
<>	128:9bcdf88f62b0	657
<>	128:9bcdf88f62b0	658	/** @addtogroup ADC_Private_Constants ADC Private Constants
<>	128:9bcdf88f62b0	659	* @{
<>	128:9bcdf88f62b0	660	*/
<>	128:9bcdf88f62b0	661
<>	128:9bcdf88f62b0	662	/* List of external triggers of regular group for ADC1: */
<>	128:9bcdf88f62b0	663	/* (used internally by HAL driver. To not use into HAL structure parameters) */
<>	128:9bcdf88f62b0	664
<>	128:9bcdf88f62b0	665	/* External triggers of regular group for ADC1 */
<>	128:9bcdf88f62b0	666	#define ADC_EXTERNALTRIG_T9_CC2 ((uint32_t) 0x00000000)
<>	128:9bcdf88f62b0	667	#define ADC_EXTERNALTRIG_T9_TRGO ((uint32_t)( ADC_CR2_EXTSEL_0))
<>	128:9bcdf88f62b0	668	#define ADC_EXTERNALTRIG_T2_CC3 ((uint32_t)( ADC_CR2_EXTSEL_1 ))
<>	128:9bcdf88f62b0	669	#define ADC_EXTERNALTRIG_T2_CC2 ((uint32_t)( ADC_CR2_EXTSEL_1 \| ADC_CR2_EXTSEL_0))
<>	128:9bcdf88f62b0	670	#define ADC_EXTERNALTRIG_T3_TRGO ((uint32_t)( ADC_CR2_EXTSEL_2 ))
<>	128:9bcdf88f62b0	671	#define ADC_EXTERNALTRIG_T4_CC4 ((uint32_t)( ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_0))
<>	128:9bcdf88f62b0	672	#define ADC_EXTERNALTRIG_T2_TRGO ((uint32_t)( ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_1 ))
<>	128:9bcdf88f62b0	673	#define ADC_EXTERNALTRIG_T3_CC1 ((uint32_t)( ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_1 \| ADC_CR2_EXTSEL_0))
<>	128:9bcdf88f62b0	674	#define ADC_EXTERNALTRIG_T3_CC3 ((uint32_t)(ADC_CR2_EXTSEL_3 ))
<>	128:9bcdf88f62b0	675	#define ADC_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_0))
<>	128:9bcdf88f62b0	676	#define ADC_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_1 ))
<>	128:9bcdf88f62b0	677	#define ADC_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_1 \| ADC_CR2_EXTSEL_0))
<>	128:9bcdf88f62b0	678
<>	128:9bcdf88f62b0	679	/* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */
<>	128:9bcdf88f62b0	680	#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC \| ADC_FLAG_JEOC \| ADC_FLAG_AWD \| \
<>	128:9bcdf88f62b0	681	ADC_FLAG_OVR)
<>	128:9bcdf88f62b0	682
<>	128:9bcdf88f62b0	683	/**
<>	128:9bcdf88f62b0	684	* @}
<>	128:9bcdf88f62b0	685	*/
<>	128:9bcdf88f62b0	686
<>	128:9bcdf88f62b0	687
<>	128:9bcdf88f62b0	688	/* Exported macro ------------------------------------------------------------*/
<>	128:9bcdf88f62b0	689
<>	128:9bcdf88f62b0	690	/** @defgroup ADC_Exported_Macros ADC Exported Macros
<>	128:9bcdf88f62b0	691	* @{
<>	128:9bcdf88f62b0	692	*/
<>	128:9bcdf88f62b0	693	/* Macro for internal HAL driver usage, and possibly can be used into code of */
<>	128:9bcdf88f62b0	694	/* final user. */
<>	128:9bcdf88f62b0	695
<>	128:9bcdf88f62b0	696	/**
<>	128:9bcdf88f62b0	697	* @brief Enable the ADC peripheral
<>	128:9bcdf88f62b0	698	* @param __HANDLE__: ADC handle
<>	128:9bcdf88f62b0	699	* @retval None
<>	128:9bcdf88f62b0	700	*/
<>	128:9bcdf88f62b0	701	#define __HAL_ADC_ENABLE(__HANDLE__) \
<>	128:9bcdf88f62b0	702	(__HANDLE__)->Instance->CR2 \|= ADC_CR2_ADON
<>	128:9bcdf88f62b0	703
<>	128:9bcdf88f62b0	704	/**
<>	128:9bcdf88f62b0	705	* @brief Disable the ADC peripheral
<>	128:9bcdf88f62b0	706	* @param __HANDLE__: ADC handle
<>	128:9bcdf88f62b0	707	* @retval None
<>	128:9bcdf88f62b0	708	*/
<>	128:9bcdf88f62b0	709	#define __HAL_ADC_DISABLE(__HANDLE__) \
<>	128:9bcdf88f62b0	710	(__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON
<>	128:9bcdf88f62b0	711
<>	128:9bcdf88f62b0	712	/**
<>	128:9bcdf88f62b0	713	* @brief Enable the ADC end of conversion interrupt.
<>	128:9bcdf88f62b0	714	* @param __HANDLE__: ADC handle
<>	128:9bcdf88f62b0	715	* @param __INTERRUPT__: ADC Interrupt
<>	128:9bcdf88f62b0	716	* This parameter can be any combination of the following values:
<>	128:9bcdf88f62b0	717	* @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
<>	128:9bcdf88f62b0	718	* @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
<>	128:9bcdf88f62b0	719	* @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
<>	128:9bcdf88f62b0	720	* @arg ADC_IT_OVR: ADC overrun interrupt source
<>	128:9bcdf88f62b0	721	* @retval None
<>	128:9bcdf88f62b0	722	*/
<>	128:9bcdf88f62b0	723	#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
<>	128:9bcdf88f62b0	724	(SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
<>	128:9bcdf88f62b0	725
<>	128:9bcdf88f62b0	726	/**
<>	128:9bcdf88f62b0	727	* @brief Disable the ADC end of conversion interrupt.
<>	128:9bcdf88f62b0	728	* @param __HANDLE__: ADC handle
<>	128:9bcdf88f62b0	729	* @param __INTERRUPT__: ADC Interrupt
<>	128:9bcdf88f62b0	730	* This parameter can be any combination of the following values:
<>	128:9bcdf88f62b0	731	* @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
<>	128:9bcdf88f62b0	732	* @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
<>	128:9bcdf88f62b0	733	* @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
<>	128:9bcdf88f62b0	734	* @arg ADC_IT_OVR: ADC overrun interrupt source
<>	128:9bcdf88f62b0	735	* @retval None
<>	128:9bcdf88f62b0	736	*/
<>	128:9bcdf88f62b0	737	#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
<>	128:9bcdf88f62b0	738	(CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
<>	128:9bcdf88f62b0	739
<>	128:9bcdf88f62b0	740	/** @brief Checks if the specified ADC interrupt source is enabled or disabled.
<>	128:9bcdf88f62b0	741	* @param __HANDLE__: ADC handle
<>	128:9bcdf88f62b0	742	* @param __INTERRUPT__: ADC interrupt source to check
<>	128:9bcdf88f62b0	743	* This parameter can be any combination of the following values:
<>	128:9bcdf88f62b0	744	* @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
<>	128:9bcdf88f62b0	745	* @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
<>	128:9bcdf88f62b0	746	* @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
<>	128:9bcdf88f62b0	747	* @arg ADC_IT_OVR: ADC overrun interrupt source
<>	128:9bcdf88f62b0	748	* @retval State of interruption (SET or RESET)
<>	128:9bcdf88f62b0	749	*/
<>	128:9bcdf88f62b0	750	#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
<>	128:9bcdf88f62b0	751	(((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
<>	128:9bcdf88f62b0	752
<>	128:9bcdf88f62b0	753	/**
<>	128:9bcdf88f62b0	754	* @brief Get the selected ADC's flag status.
<>	128:9bcdf88f62b0	755	* @param __HANDLE__: ADC handle
<>	128:9bcdf88f62b0	756	* @param __FLAG__: ADC flag
<>	128:9bcdf88f62b0	757	* This parameter can be any combination of the following values:
<>	128:9bcdf88f62b0	758	* @arg ADC_FLAG_STRT: ADC Regular group start flag
<>	128:9bcdf88f62b0	759	* @arg ADC_FLAG_JSTRT: ADC Injected group start flag
<>	128:9bcdf88f62b0	760	* @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
<>	128:9bcdf88f62b0	761	* @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
<>	128:9bcdf88f62b0	762	* @arg ADC_FLAG_AWD: ADC Analog watchdog flag
<>	128:9bcdf88f62b0	763	* @arg ADC_FLAG_OVR: ADC overrun flag
<>	128:9bcdf88f62b0	764	* @arg ADC_FLAG_ADONS: ADC ready status flag
<>	128:9bcdf88f62b0	765	* @arg ADC_FLAG_RCNR: ADC Regular group ready status flag
<>	128:9bcdf88f62b0	766	* @arg ADC_FLAG_JCNR: ADC Injected group ready status flag
<>	128:9bcdf88f62b0	767	* @retval None
<>	128:9bcdf88f62b0	768	*/
<>	128:9bcdf88f62b0	769	#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
<>	128:9bcdf88f62b0	770	((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
<>	128:9bcdf88f62b0	771
<>	128:9bcdf88f62b0	772	/**
<>	128:9bcdf88f62b0	773	* @brief Clear the ADC's pending flags
<>	128:9bcdf88f62b0	774	* @param __HANDLE__: ADC handle
<>	128:9bcdf88f62b0	775	* @param __FLAG__: ADC flag
<>	128:9bcdf88f62b0	776	* @arg ADC_FLAG_STRT: ADC Regular group start flag
<>	128:9bcdf88f62b0	777	* @arg ADC_FLAG_JSTRT: ADC Injected group start flag
<>	128:9bcdf88f62b0	778	* @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
<>	128:9bcdf88f62b0	779	* @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
<>	128:9bcdf88f62b0	780	* @arg ADC_FLAG_AWD: ADC Analog watchdog flag
<>	128:9bcdf88f62b0	781	* @arg ADC_FLAG_OVR: ADC overrun flag
<>	128:9bcdf88f62b0	782	* @arg ADC_FLAG_ADONS: ADC ready status flag
<>	128:9bcdf88f62b0	783	* @arg ADC_FLAG_RCNR: ADC Regular group ready status flag
<>	128:9bcdf88f62b0	784	* @arg ADC_FLAG_JCNR: ADC Injected group ready status flag
<>	128:9bcdf88f62b0	785	* @retval None
<>	128:9bcdf88f62b0	786	*/
<>	128:9bcdf88f62b0	787	#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
<>	128:9bcdf88f62b0	788	(((__HANDLE__)->Instance->SR) = ~(__FLAG__))
<>	128:9bcdf88f62b0	789
<>	128:9bcdf88f62b0	790	/** @brief Reset ADC handle state
<>	128:9bcdf88f62b0	791	* @param __HANDLE__: ADC handle
<>	128:9bcdf88f62b0	792	* @retval None
<>	128:9bcdf88f62b0	793	*/
<>	128:9bcdf88f62b0	794	#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
<>	128:9bcdf88f62b0	795	((__HANDLE__)->State = HAL_ADC_STATE_RESET)
<>	128:9bcdf88f62b0	796
<>	128:9bcdf88f62b0	797	/**
<>	128:9bcdf88f62b0	798	* @}
<>	128:9bcdf88f62b0	799	*/
<>	128:9bcdf88f62b0	800
<>	128:9bcdf88f62b0	801	/* Private macro ------------------------------------------------------------*/
<>	128:9bcdf88f62b0	802
<>	128:9bcdf88f62b0	803	/** @defgroup ADC_Private_Macros ADC Private Macros
<>	128:9bcdf88f62b0	804	* @{
<>	128:9bcdf88f62b0	805	*/
<>	128:9bcdf88f62b0	806	/* Macro reserved for internal HAL driver usage, not intended to be used in */
<>	128:9bcdf88f62b0	807	/* code of final user. */
<>	128:9bcdf88f62b0	808
<>	128:9bcdf88f62b0	809	/**
<>	128:9bcdf88f62b0	810	* @brief Verification of ADC state: enabled or disabled
<>	128:9bcdf88f62b0	811	* @param __HANDLE__: ADC handle
<>	128:9bcdf88f62b0	812	* @retval SET (ADC enabled) or RESET (ADC disabled)
<>	128:9bcdf88f62b0	813	*/
<>	128:9bcdf88f62b0	814	#define ADC_IS_ENABLE(__HANDLE__) \
<>	128:9bcdf88f62b0	815	((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS ) \
<>	128:9bcdf88f62b0	816	) ? SET : RESET)
<>	128:9bcdf88f62b0	817
<>	128:9bcdf88f62b0	818	/**
<>	128:9bcdf88f62b0	819	* @brief Test if conversion trigger of regular group is software start
<>	128:9bcdf88f62b0	820	* or external trigger.
<>	128:9bcdf88f62b0	821	* @param __HANDLE__: ADC handle
<>	128:9bcdf88f62b0	822	* @retval SET (software start) or RESET (external trigger)
<>	128:9bcdf88f62b0	823	*/
<>	128:9bcdf88f62b0	824	#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
<>	128:9bcdf88f62b0	825	(((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
<>	128:9bcdf88f62b0	826
<>	128:9bcdf88f62b0	827	/**
<>	128:9bcdf88f62b0	828	* @brief Test if conversion trigger of injected group is software start
<>	128:9bcdf88f62b0	829	* or external trigger.
<>	128:9bcdf88f62b0	830	* @param __HANDLE__: ADC handle
<>	128:9bcdf88f62b0	831	* @retval SET (software start) or RESET (external trigger)
<>	128:9bcdf88f62b0	832	*/
<>	128:9bcdf88f62b0	833	#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
<>	128:9bcdf88f62b0	834	(((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET)
<>	128:9bcdf88f62b0	835
<>	128:9bcdf88f62b0	836	/**
<>	128:9bcdf88f62b0	837	* @brief Simultaneously clears and sets specific bits of the handle State
<>	128:9bcdf88f62b0	838	* @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
<>	128:9bcdf88f62b0	839	* the first parameter is the ADC handle State, the second parameter is the
<>	128:9bcdf88f62b0	840	* bit field to clear, the third and last parameter is the bit field to set.
<>	128:9bcdf88f62b0	841	* @retval None
<>	128:9bcdf88f62b0	842	*/
<>	128:9bcdf88f62b0	843	#define ADC_STATE_CLR_SET MODIFY_REG
<>	128:9bcdf88f62b0	844
<>	128:9bcdf88f62b0	845	/**
<>	128:9bcdf88f62b0	846	* @brief Clear ADC error code (set it to error code: "no error")
<>	128:9bcdf88f62b0	847	* @param __HANDLE__: ADC handle
<>	128:9bcdf88f62b0	848	* @retval None
<>	128:9bcdf88f62b0	849	*/
<>	128:9bcdf88f62b0	850	#define ADC_CLEAR_ERRORCODE(__HANDLE__) \
<>	128:9bcdf88f62b0	851	((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
<>	128:9bcdf88f62b0	852
<>	128:9bcdf88f62b0	853	/**
<>	128:9bcdf88f62b0	854	* @brief Set ADC number of ranks into regular channel sequence length.
<>	128:9bcdf88f62b0	855	* @param _NbrOfConversion_: Regular channel sequence length
<>	128:9bcdf88f62b0	856	* @retval None
<>	128:9bcdf88f62b0	857	*/
<>	128:9bcdf88f62b0	858	#define ADC_SQR1_L_SHIFT(_NbrOfConversion_) \
<>	128:9bcdf88f62b0	859	(((_NbrOfConversion_) - (uint8_t)1) << POSITION_VAL(ADC_SQR1_L))
<>	128:9bcdf88f62b0	860
<>	128:9bcdf88f62b0	861	/**
<>	128:9bcdf88f62b0	862	* @brief Set the ADC's sample time for channel numbers between 10 and 18.
<>	128:9bcdf88f62b0	863	* @param _SAMPLETIME_: Sample time parameter.
<>	128:9bcdf88f62b0	864	* @param _CHANNELNB_: Channel number.
<>	128:9bcdf88f62b0	865	* @retval None
<>	128:9bcdf88f62b0	866	*/
<>	128:9bcdf88f62b0	867	#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) \
<>	128:9bcdf88f62b0	868	((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 10)))
<>	128:9bcdf88f62b0	869
<>	128:9bcdf88f62b0	870	/**
<>	128:9bcdf88f62b0	871	* @brief Set the ADC's sample time for channel numbers between 0 and 9.
<>	128:9bcdf88f62b0	872	* @param _SAMPLETIME_: Sample time parameter.
<>	128:9bcdf88f62b0	873	* @param _CHANNELNB_: Channel number.
<>	128:9bcdf88f62b0	874	* @retval None
<>	128:9bcdf88f62b0	875	*/
<>	128:9bcdf88f62b0	876	#define ADC_SMPR3(_SAMPLETIME_, _CHANNELNB_) \
<>	128:9bcdf88f62b0	877	((_SAMPLETIME_) << (3 * (_CHANNELNB_)))
<>	128:9bcdf88f62b0	878
<>	128:9bcdf88f62b0	879	/**
<>	128:9bcdf88f62b0	880	* @brief Set the selected regular channel rank for rank between 1 and 6.
<>	128:9bcdf88f62b0	881	* @param _CHANNELNB_: Channel number.
<>	128:9bcdf88f62b0	882	* @param _RANKNB_: Rank number.
<>	128:9bcdf88f62b0	883	* @retval None
<>	128:9bcdf88f62b0	884	*/
<>	128:9bcdf88f62b0	885	#define ADC_SQR5_RK(_CHANNELNB_, _RANKNB_) \
<>	128:9bcdf88f62b0	886	((_CHANNELNB_) << (5 * ((_RANKNB_) - 1)))
<>	128:9bcdf88f62b0	887
<>	128:9bcdf88f62b0	888	/**
<>	128:9bcdf88f62b0	889	* @brief Set the selected regular channel rank for rank between 7 and 12.
<>	128:9bcdf88f62b0	890	* @param _CHANNELNB_: Channel number.
<>	128:9bcdf88f62b0	891	* @param _RANKNB_: Rank number.
<>	128:9bcdf88f62b0	892	* @retval None
<>	128:9bcdf88f62b0	893	*/
<>	128:9bcdf88f62b0	894	#define ADC_SQR4_RK(_CHANNELNB_, _RANKNB_) \
<>	128:9bcdf88f62b0	895	((_CHANNELNB_) << (5 * ((_RANKNB_) - 7)))
<>	128:9bcdf88f62b0	896
<>	128:9bcdf88f62b0	897	/**
<>	128:9bcdf88f62b0	898	* @brief Set the selected regular channel rank for rank between 13 and 18.
<>	128:9bcdf88f62b0	899	* @param _CHANNELNB_: Channel number.
<>	128:9bcdf88f62b0	900	* @param _RANKNB_: Rank number.
<>	128:9bcdf88f62b0	901	* @retval None
<>	128:9bcdf88f62b0	902	*/
<>	128:9bcdf88f62b0	903	#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) \
<>	128:9bcdf88f62b0	904	((_CHANNELNB_) << (5 * ((_RANKNB_) - 13)))
<>	128:9bcdf88f62b0	905
<>	128:9bcdf88f62b0	906	/**
<>	128:9bcdf88f62b0	907	* @brief Set the selected regular channel rank for rank between 19 and 24.
<>	128:9bcdf88f62b0	908	* @param _CHANNELNB_: Channel number.
<>	128:9bcdf88f62b0	909	* @param _RANKNB_: Rank number.
<>	128:9bcdf88f62b0	910	* @retval None
<>	128:9bcdf88f62b0	911	*/
<>	128:9bcdf88f62b0	912	#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) \
<>	128:9bcdf88f62b0	913	((_CHANNELNB_) << (5 * ((_RANKNB_) - 19)))
<>	128:9bcdf88f62b0	914
<>	128:9bcdf88f62b0	915	/**
<>	128:9bcdf88f62b0	916	* @brief Set the selected regular channel rank for rank between 25 and 28.
<>	128:9bcdf88f62b0	917	* @param _CHANNELNB_: Channel number.
<>	128:9bcdf88f62b0	918	* @param _RANKNB_: Rank number.
<>	128:9bcdf88f62b0	919	* @retval None
<>	128:9bcdf88f62b0	920	*/
<>	128:9bcdf88f62b0	921	#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) \
<>	128:9bcdf88f62b0	922	((_CHANNELNB_) << (5 * ((_RANKNB_) - 25)))
<>	128:9bcdf88f62b0	923
<>	128:9bcdf88f62b0	924	/**
<>	128:9bcdf88f62b0	925	* @brief Set the injected sequence length.
<>	128:9bcdf88f62b0	926	* @param _JSQR_JL_: Sequence length.
<>	128:9bcdf88f62b0	927	* @retval None
<>	128:9bcdf88f62b0	928	*/
<>	128:9bcdf88f62b0	929	#define ADC_JSQR_JL_SHIFT(_JSQR_JL_) (((_JSQR_JL_) -1) << 20)
<>	128:9bcdf88f62b0	930
<>	128:9bcdf88f62b0	931	/**
<>	128:9bcdf88f62b0	932	* @brief Set the selected injected channel rank
<>	128:9bcdf88f62b0	933	* Note: on STM32L1 devices, channel rank position in JSQR register
<>	128:9bcdf88f62b0	934	* is depending on total number of ranks selected into
<>	128:9bcdf88f62b0	935	* injected sequencer (ranks sequence starting from 4-JL)
<>	128:9bcdf88f62b0	936	* @param _CHANNELNB_: Channel number.
<>	128:9bcdf88f62b0	937	* @param _RANKNB_: Rank number.
<>	128:9bcdf88f62b0	938	* @param _JSQR_JL_: Sequence length.
<>	128:9bcdf88f62b0	939	* @retval None
<>	128:9bcdf88f62b0	940	*/
<>	128:9bcdf88f62b0	941	#define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) \
<>	128:9bcdf88f62b0	942	((_CHANNELNB_) << (5 * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1)))
<>	128:9bcdf88f62b0	943
<>	128:9bcdf88f62b0	944	/**
<>	128:9bcdf88f62b0	945	* @brief Enable the ADC DMA continuous request.
<>	128:9bcdf88f62b0	946	* @param _DMACONTREQ_MODE_: DMA continuous request mode.
<>	128:9bcdf88f62b0	947	* @retval None
<>	128:9bcdf88f62b0	948	*/
<>	128:9bcdf88f62b0	949	#define ADC_CR2_DMACONTREQ(_DMACONTREQ_MODE_) \
<>	128:9bcdf88f62b0	950	((_DMACONTREQ_MODE_) << POSITION_VAL(ADC_CR2_DDS))
<>	128:9bcdf88f62b0	951
<>	128:9bcdf88f62b0	952	/**
<>	128:9bcdf88f62b0	953	* @brief Enable ADC continuous conversion mode.
<>	128:9bcdf88f62b0	954	* @param _CONTINUOUS_MODE_: Continuous mode.
<>	128:9bcdf88f62b0	955	* @retval None
<>	128:9bcdf88f62b0	956	*/
<>	128:9bcdf88f62b0	957	#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) \
<>	128:9bcdf88f62b0	958	((_CONTINUOUS_MODE_) << POSITION_VAL(ADC_CR2_CONT))
<>	128:9bcdf88f62b0	959
<>	128:9bcdf88f62b0	960	/**
<>	128:9bcdf88f62b0	961	* @brief Configures the number of discontinuous conversions for the regular group channels.
<>	128:9bcdf88f62b0	962	* @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions.
<>	128:9bcdf88f62b0	963	* @retval None
<>	128:9bcdf88f62b0	964	*/
<>	128:9bcdf88f62b0	965	#define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) \
<>	128:9bcdf88f62b0	966	(((_NBR_DISCONTINUOUS_CONV_) - 1) << POSITION_VAL(ADC_CR1_DISCNUM))
<>	128:9bcdf88f62b0	967
<>	128:9bcdf88f62b0	968	/**
<>	128:9bcdf88f62b0	969	* @brief Enable ADC scan mode to convert multiple ranks with sequencer.
<>	128:9bcdf88f62b0	970	* @param _SCAN_MODE_: Scan conversion mode.
<>	128:9bcdf88f62b0	971	* @retval None
<>	128:9bcdf88f62b0	972	*/
<>	128:9bcdf88f62b0	973	/* Note: Scan mode is compared to ENABLE for legacy purpose, this parameter */
<>	128:9bcdf88f62b0	974	/* is equivalent to ADC_SCAN_ENABLE. */
<>	128:9bcdf88f62b0	975	#define ADC_CR1_SCAN_SET(_SCAN_MODE_) \
<>	128:9bcdf88f62b0	976	(( ((_SCAN_MODE_) == ADC_SCAN_ENABLE) \|\| ((_SCAN_MODE_) == ENABLE) \
<>	128:9bcdf88f62b0	977	)? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE) \
<>	128:9bcdf88f62b0	978	)
<>	128:9bcdf88f62b0	979
<>	128:9bcdf88f62b0	980
<>	128:9bcdf88f62b0	981	#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) \|\| \
<>	128:9bcdf88f62b0	982	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2) \|\| \
<>	128:9bcdf88f62b0	983	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4) )
<>	128:9bcdf88f62b0	984
<>	128:9bcdf88f62b0	985	#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) \|\| \
<>	128:9bcdf88f62b0	986	((RESOLUTION) == ADC_RESOLUTION_10B) \|\| \
<>	128:9bcdf88f62b0	987	((RESOLUTION) == ADC_RESOLUTION_8B) \|\| \
<>	128:9bcdf88f62b0	988	((RESOLUTION) == ADC_RESOLUTION_6B) )
<>	128:9bcdf88f62b0	989
<>	128:9bcdf88f62b0	990	#define IS_ADC_RESOLUTION_8_6_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_8B) \|\| \
<>	128:9bcdf88f62b0	991	((RESOLUTION) == ADC_RESOLUTION_6B) )
<>	128:9bcdf88f62b0	992
<>	128:9bcdf88f62b0	993	#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) \|\| \
<>	128:9bcdf88f62b0	994	((ALIGN) == ADC_DATAALIGN_LEFT) )
<>	128:9bcdf88f62b0	995
<>	128:9bcdf88f62b0	996	#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) \|\| \
<>	128:9bcdf88f62b0	997	((SCAN_MODE) == ADC_SCAN_ENABLE) )
<>	128:9bcdf88f62b0	998
<>	128:9bcdf88f62b0	999	#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) \|\| \
<>	128:9bcdf88f62b0	1000	((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) \|\| \
<>	128:9bcdf88f62b0	1001	((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) \|\| \
<>	128:9bcdf88f62b0	1002	((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) )
<>	128:9bcdf88f62b0	1003
<>	128:9bcdf88f62b0	1004	#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) \|\| \
<>	128:9bcdf88f62b0	1005	((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) \|\| \
<>	128:9bcdf88f62b0	1006	((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) \|\| \
<>	128:9bcdf88f62b0	1007	((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) \|\| \
<>	128:9bcdf88f62b0	1008	((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC3) \|\| \
<>	128:9bcdf88f62b0	1009	((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) \|\| \
<>	128:9bcdf88f62b0	1010	((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) \|\| \
<>	128:9bcdf88f62b0	1011	((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) \|\| \
<>	128:9bcdf88f62b0	1012	((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) \|\| \
<>	128:9bcdf88f62b0	1013	((REGTRIG) == ADC_EXTERNALTRIGCONV_T9_CC2) \|\| \
<>	128:9bcdf88f62b0	1014	((REGTRIG) == ADC_EXTERNALTRIGCONV_T9_TRGO) \|\| \
<>	128:9bcdf88f62b0	1015	((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) \|\| \
<>	128:9bcdf88f62b0	1016	((REGTRIG) == ADC_SOFTWARE_START) )
<>	128:9bcdf88f62b0	1017
<>	128:9bcdf88f62b0	1018	#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) \|\| \
<>	128:9bcdf88f62b0	1019	((EOC_SELECTION) == ADC_EOC_SEQ_CONV) )
<>	128:9bcdf88f62b0	1020
<>	128:9bcdf88f62b0	1021	#define IS_ADC_AUTOWAIT(AUTOWAIT) (((AUTOWAIT) == ADC_AUTOWAIT_DISABLE) \|\| \
<>	128:9bcdf88f62b0	1022	((AUTOWAIT) == ADC_AUTOWAIT_UNTIL_DATA_READ) \|\| \
<>	128:9bcdf88f62b0	1023	((AUTOWAIT) == ADC_AUTOWAIT_7_APBCLOCKCYCLES) \|\| \
<>	128:9bcdf88f62b0	1024	((AUTOWAIT) == ADC_AUTOWAIT_15_APBCLOCKCYCLES) \|\| \
<>	128:9bcdf88f62b0	1025	((AUTOWAIT) == ADC_AUTOWAIT_31_APBCLOCKCYCLES) \|\| \
<>	128:9bcdf88f62b0	1026	((AUTOWAIT) == ADC_AUTOWAIT_63_APBCLOCKCYCLES) \|\| \
<>	128:9bcdf88f62b0	1027	((AUTOWAIT) == ADC_AUTOWAIT_127_APBCLOCKCYCLES) \|\| \
<>	128:9bcdf88f62b0	1028	((AUTOWAIT) == ADC_AUTOWAIT_255_APBCLOCKCYCLES) )
<>	128:9bcdf88f62b0	1029
<>	128:9bcdf88f62b0	1030	#define IS_ADC_AUTOPOWEROFF(AUTOPOWEROFF) (((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_DISABLE) \|\| \
<>	128:9bcdf88f62b0	1031	((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_IDLE_PHASE) \|\| \
<>	128:9bcdf88f62b0	1032	((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_DELAY_PHASE) \|\| \
<>	128:9bcdf88f62b0	1033	((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_IDLE_DELAY_PHASES) )
<>	128:9bcdf88f62b0	1034
<>	128:9bcdf88f62b0	1035	#if defined(STM32L100xC) \|\| defined (STM32L151xC) \|\| defined (STM32L152xC) \|\| defined (STM32L162xC) \|\| defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD) \|\| defined(STM32L151xE) \|\| defined(STM32L151xDX) \|\| defined (STM32L152xE) \|\| defined (STM32L152xDX) \|\| defined (STM32L162xE) \|\| defined (STM32L162xDX)
<>	128:9bcdf88f62b0	1036
<>	128:9bcdf88f62b0	1037	#define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A) \|\| \
<>	128:9bcdf88f62b0	1038	((BANK) == ADC_CHANNELS_BANK_B) )
<>	128:9bcdf88f62b0	1039	#else
<>	128:9bcdf88f62b0	1040
<>	128:9bcdf88f62b0	1041	#define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A))
<>	128:9bcdf88f62b0	1042	#endif /* STM32L100xC \|\| STM32L151xC \|\| STM32L152xC \|\| STM32L162xC \|\| STM32L151xCA \|\| STM32L151xD \|\| STM32L152xCA \|\| STM32L152xD \|\| STM32L162xCA \|\| STM32L162xD \|\| STM32L151xE \|\| STM32L151xDX \|\| STM32L152xE \|\| STM32L152xDX \|\| STM32L162xE \|\| STM32L162xDX */
<>	128:9bcdf88f62b0	1043
<>	128:9bcdf88f62b0	1044	#if defined(STM32L100xB) \|\| defined (STM32L151xB) \|\| defined (STM32L152xB) \|\| defined(STM32L100xBA) \|\| defined (STM32L151xBA) \|\| defined (STM32L152xBA) \|\| defined(STM32L100xC) \|\| defined (STM32L151xC) \|\| defined (STM32L152xC) \|\| defined (STM32L162xC)
<>	128:9bcdf88f62b0	1045	#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) \|\| \
<>	128:9bcdf88f62b0	1046	((CHANNEL) == ADC_CHANNEL_1) \|\| \
<>	128:9bcdf88f62b0	1047	((CHANNEL) == ADC_CHANNEL_2) \|\| \
<>	128:9bcdf88f62b0	1048	((CHANNEL) == ADC_CHANNEL_3) \|\| \
<>	128:9bcdf88f62b0	1049	((CHANNEL) == ADC_CHANNEL_4) \|\| \
<>	128:9bcdf88f62b0	1050	((CHANNEL) == ADC_CHANNEL_5) \|\| \
<>	128:9bcdf88f62b0	1051	((CHANNEL) == ADC_CHANNEL_6) \|\| \
<>	128:9bcdf88f62b0	1052	((CHANNEL) == ADC_CHANNEL_7) \|\| \
<>	128:9bcdf88f62b0	1053	((CHANNEL) == ADC_CHANNEL_8) \|\| \
<>	128:9bcdf88f62b0	1054	((CHANNEL) == ADC_CHANNEL_9) \|\| \
<>	128:9bcdf88f62b0	1055	((CHANNEL) == ADC_CHANNEL_10) \|\| \
<>	128:9bcdf88f62b0	1056	((CHANNEL) == ADC_CHANNEL_11) \|\| \
<>	128:9bcdf88f62b0	1057	((CHANNEL) == ADC_CHANNEL_12) \|\| \
<>	128:9bcdf88f62b0	1058	((CHANNEL) == ADC_CHANNEL_13) \|\| \
<>	128:9bcdf88f62b0	1059	((CHANNEL) == ADC_CHANNEL_14) \|\| \
<>	128:9bcdf88f62b0	1060	((CHANNEL) == ADC_CHANNEL_15) \|\| \
<>	128:9bcdf88f62b0	1061	((CHANNEL) == ADC_CHANNEL_16) \|\| \
<>	128:9bcdf88f62b0	1062	((CHANNEL) == ADC_CHANNEL_17) \|\| \
<>	128:9bcdf88f62b0	1063	((CHANNEL) == ADC_CHANNEL_18) \|\| \
<>	128:9bcdf88f62b0	1064	((CHANNEL) == ADC_CHANNEL_19) \|\| \
<>	128:9bcdf88f62b0	1065	((CHANNEL) == ADC_CHANNEL_20) \|\| \
<>	128:9bcdf88f62b0	1066	((CHANNEL) == ADC_CHANNEL_21) \|\| \
<>	128:9bcdf88f62b0	1067	((CHANNEL) == ADC_CHANNEL_22) \|\| \
<>	128:9bcdf88f62b0	1068	((CHANNEL) == ADC_CHANNEL_23) \|\| \
<>	128:9bcdf88f62b0	1069	((CHANNEL) == ADC_CHANNEL_24) \|\| \
<>	128:9bcdf88f62b0	1070	((CHANNEL) == ADC_CHANNEL_25) \|\| \
<>	128:9bcdf88f62b0	1071	((CHANNEL) == ADC_CHANNEL_26) )
<>	128:9bcdf88f62b0	1072	#endif /* STM32L100xB \|\| STM32L151xB \|\| STM32L152xB \|\| STM32L100xBA \|\| STM32L151xBA \|\| STM32L152xBA \|\| STM32L100xC \|\| STM32L151xC \|\| STM32L152xC \|\| STM32L162xC */
<>	128:9bcdf88f62b0	1073	#if defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD) \|\| defined(STM32L151xE) \|\| defined(STM32L151xDX) \|\| defined (STM32L152xE) \|\| defined (STM32L152xDX) \|\| defined (STM32L162xE) \|\| defined (STM32L162xDX)
<>	128:9bcdf88f62b0	1074	#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) \|\| \
<>	128:9bcdf88f62b0	1075	((CHANNEL) == ADC_CHANNEL_1) \|\| \
<>	128:9bcdf88f62b0	1076	((CHANNEL) == ADC_CHANNEL_2) \|\| \
<>	128:9bcdf88f62b0	1077	((CHANNEL) == ADC_CHANNEL_3) \|\| \
<>	128:9bcdf88f62b0	1078	((CHANNEL) == ADC_CHANNEL_4) \|\| \
<>	128:9bcdf88f62b0	1079	((CHANNEL) == ADC_CHANNEL_5) \|\| \
<>	128:9bcdf88f62b0	1080	((CHANNEL) == ADC_CHANNEL_6) \|\| \
<>	128:9bcdf88f62b0	1081	((CHANNEL) == ADC_CHANNEL_7) \|\| \
<>	128:9bcdf88f62b0	1082	((CHANNEL) == ADC_CHANNEL_8) \|\| \
<>	128:9bcdf88f62b0	1083	((CHANNEL) == ADC_CHANNEL_9) \|\| \
<>	128:9bcdf88f62b0	1084	((CHANNEL) == ADC_CHANNEL_10) \|\| \
<>	128:9bcdf88f62b0	1085	((CHANNEL) == ADC_CHANNEL_11) \|\| \
<>	128:9bcdf88f62b0	1086	((CHANNEL) == ADC_CHANNEL_12) \|\| \
<>	128:9bcdf88f62b0	1087	((CHANNEL) == ADC_CHANNEL_13) \|\| \
<>	128:9bcdf88f62b0	1088	((CHANNEL) == ADC_CHANNEL_14) \|\| \
<>	128:9bcdf88f62b0	1089	((CHANNEL) == ADC_CHANNEL_15) \|\| \
<>	128:9bcdf88f62b0	1090	((CHANNEL) == ADC_CHANNEL_16) \|\| \
<>	128:9bcdf88f62b0	1091	((CHANNEL) == ADC_CHANNEL_17) \|\| \
<>	128:9bcdf88f62b0	1092	((CHANNEL) == ADC_CHANNEL_18) \|\| \
<>	128:9bcdf88f62b0	1093	((CHANNEL) == ADC_CHANNEL_19) \|\| \
<>	128:9bcdf88f62b0	1094	((CHANNEL) == ADC_CHANNEL_20) \|\| \
<>	128:9bcdf88f62b0	1095	((CHANNEL) == ADC_CHANNEL_21) \|\| \
<>	128:9bcdf88f62b0	1096	((CHANNEL) == ADC_CHANNEL_22) \|\| \
<>	128:9bcdf88f62b0	1097	((CHANNEL) == ADC_CHANNEL_23) \|\| \
<>	128:9bcdf88f62b0	1098	((CHANNEL) == ADC_CHANNEL_24) \|\| \
<>	128:9bcdf88f62b0	1099	((CHANNEL) == ADC_CHANNEL_25) \|\| \
<>	128:9bcdf88f62b0	1100	((CHANNEL) == ADC_CHANNEL_26) \|\| \
<>	128:9bcdf88f62b0	1101	((CHANNEL) == ADC_CHANNEL_27) \|\| \
<>	128:9bcdf88f62b0	1102	((CHANNEL) == ADC_CHANNEL_28) \|\| \
<>	128:9bcdf88f62b0	1103	((CHANNEL) == ADC_CHANNEL_29) \|\| \
<>	128:9bcdf88f62b0	1104	((CHANNEL) == ADC_CHANNEL_30) \|\| \
<>	128:9bcdf88f62b0	1105	((CHANNEL) == ADC_CHANNEL_31) )
<>	128:9bcdf88f62b0	1106	#endif /* STM32L151xCA \|\| STM32L151xD \|\| STM32L152xCA \|\| STM32L152xD \|\| STM32L162xCA \|\| STM32L162xD \|\| STM32L151xE \|\| STM32L151xDX \|\| STM32L152xE \|\| STM32L152xDX \|\| STM32L162xE \|\| STM32L162xDX */
<>	128:9bcdf88f62b0	1107
<>	128:9bcdf88f62b0	1108	#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_4CYCLES) \|\| \
<>	128:9bcdf88f62b0	1109	((TIME) == ADC_SAMPLETIME_9CYCLES) \|\| \
<>	128:9bcdf88f62b0	1110	((TIME) == ADC_SAMPLETIME_16CYCLES) \|\| \
<>	128:9bcdf88f62b0	1111	((TIME) == ADC_SAMPLETIME_24CYCLES) \|\| \
<>	128:9bcdf88f62b0	1112	((TIME) == ADC_SAMPLETIME_48CYCLES) \|\| \
<>	128:9bcdf88f62b0	1113	((TIME) == ADC_SAMPLETIME_96CYCLES) \|\| \
<>	128:9bcdf88f62b0	1114	((TIME) == ADC_SAMPLETIME_192CYCLES) \|\| \
<>	128:9bcdf88f62b0	1115	((TIME) == ADC_SAMPLETIME_384CYCLES) )
<>	128:9bcdf88f62b0	1116
<>	128:9bcdf88f62b0	1117	#if defined(STM32L100xC) \|\| defined (STM32L151xC) \|\| defined (STM32L152xC) \|\| defined (STM32L162xC) \|\| defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD) \|\| defined(STM32L151xE) \|\| defined(STM32L151xDX) \|\| defined (STM32L152xE) \|\| defined (STM32L152xDX) \|\| defined (STM32L162xE) \|\| defined (STM32L162xDX)
<>	128:9bcdf88f62b0	1118
<>	128:9bcdf88f62b0	1119	#define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) \|\| \
<>	128:9bcdf88f62b0	1120	((CHANNEL) == ADC_REGULAR_RANK_2 ) \|\| \
<>	128:9bcdf88f62b0	1121	((CHANNEL) == ADC_REGULAR_RANK_3 ) \|\| \
<>	128:9bcdf88f62b0	1122	((CHANNEL) == ADC_REGULAR_RANK_4 ) \|\| \
<>	128:9bcdf88f62b0	1123	((CHANNEL) == ADC_REGULAR_RANK_5 ) \|\| \
<>	128:9bcdf88f62b0	1124	((CHANNEL) == ADC_REGULAR_RANK_6 ) \|\| \
<>	128:9bcdf88f62b0	1125	((CHANNEL) == ADC_REGULAR_RANK_7 ) \|\| \
<>	128:9bcdf88f62b0	1126	((CHANNEL) == ADC_REGULAR_RANK_8 ) \|\| \
<>	128:9bcdf88f62b0	1127	((CHANNEL) == ADC_REGULAR_RANK_9 ) \|\| \
<>	128:9bcdf88f62b0	1128	((CHANNEL) == ADC_REGULAR_RANK_10) \|\| \
<>	128:9bcdf88f62b0	1129	((CHANNEL) == ADC_REGULAR_RANK_11) \|\| \
<>	128:9bcdf88f62b0	1130	((CHANNEL) == ADC_REGULAR_RANK_12) \|\| \
<>	128:9bcdf88f62b0	1131	((CHANNEL) == ADC_REGULAR_RANK_13) \|\| \
<>	128:9bcdf88f62b0	1132	((CHANNEL) == ADC_REGULAR_RANK_14) \|\| \
<>	128:9bcdf88f62b0	1133	((CHANNEL) == ADC_REGULAR_RANK_15) \|\| \
<>	128:9bcdf88f62b0	1134	((CHANNEL) == ADC_REGULAR_RANK_16) \|\| \
<>	128:9bcdf88f62b0	1135	((CHANNEL) == ADC_REGULAR_RANK_17) \|\| \
<>	128:9bcdf88f62b0	1136	((CHANNEL) == ADC_REGULAR_RANK_18) \|\| \
<>	128:9bcdf88f62b0	1137	((CHANNEL) == ADC_REGULAR_RANK_19) \|\| \
<>	128:9bcdf88f62b0	1138	((CHANNEL) == ADC_REGULAR_RANK_20) \|\| \
<>	128:9bcdf88f62b0	1139	((CHANNEL) == ADC_REGULAR_RANK_21) \|\| \
<>	128:9bcdf88f62b0	1140	((CHANNEL) == ADC_REGULAR_RANK_22) \|\| \
<>	128:9bcdf88f62b0	1141	((CHANNEL) == ADC_REGULAR_RANK_23) \|\| \
<>	128:9bcdf88f62b0	1142	((CHANNEL) == ADC_REGULAR_RANK_24) \|\| \
<>	128:9bcdf88f62b0	1143	((CHANNEL) == ADC_REGULAR_RANK_25) \|\| \
<>	128:9bcdf88f62b0	1144	((CHANNEL) == ADC_REGULAR_RANK_26) \|\| \
<>	128:9bcdf88f62b0	1145	((CHANNEL) == ADC_REGULAR_RANK_27) \|\| \
<>	128:9bcdf88f62b0	1146	((CHANNEL) == ADC_REGULAR_RANK_28) )
<>	128:9bcdf88f62b0	1147	#else
<>	128:9bcdf88f62b0	1148
<>	128:9bcdf88f62b0	1149	#define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) \|\| \
<>	128:9bcdf88f62b0	1150	((CHANNEL) == ADC_REGULAR_RANK_2 ) \|\| \
<>	128:9bcdf88f62b0	1151	((CHANNEL) == ADC_REGULAR_RANK_3 ) \|\| \
<>	128:9bcdf88f62b0	1152	((CHANNEL) == ADC_REGULAR_RANK_4 ) \|\| \
<>	128:9bcdf88f62b0	1153	((CHANNEL) == ADC_REGULAR_RANK_5 ) \|\| \
<>	128:9bcdf88f62b0	1154	((CHANNEL) == ADC_REGULAR_RANK_6 ) \|\| \
<>	128:9bcdf88f62b0	1155	((CHANNEL) == ADC_REGULAR_RANK_7 ) \|\| \
<>	128:9bcdf88f62b0	1156	((CHANNEL) == ADC_REGULAR_RANK_8 ) \|\| \
<>	128:9bcdf88f62b0	1157	((CHANNEL) == ADC_REGULAR_RANK_9 ) \|\| \
<>	128:9bcdf88f62b0	1158	((CHANNEL) == ADC_REGULAR_RANK_10) \|\| \
<>	128:9bcdf88f62b0	1159	((CHANNEL) == ADC_REGULAR_RANK_11) \|\| \
<>	128:9bcdf88f62b0	1160	((CHANNEL) == ADC_REGULAR_RANK_12) \|\| \
<>	128:9bcdf88f62b0	1161	((CHANNEL) == ADC_REGULAR_RANK_13) \|\| \
<>	128:9bcdf88f62b0	1162	((CHANNEL) == ADC_REGULAR_RANK_14) \|\| \
<>	128:9bcdf88f62b0	1163	((CHANNEL) == ADC_REGULAR_RANK_15) \|\| \
<>	128:9bcdf88f62b0	1164	((CHANNEL) == ADC_REGULAR_RANK_16) \|\| \
<>	128:9bcdf88f62b0	1165	((CHANNEL) == ADC_REGULAR_RANK_17) \|\| \
<>	128:9bcdf88f62b0	1166	((CHANNEL) == ADC_REGULAR_RANK_18) \|\| \
<>	128:9bcdf88f62b0	1167	((CHANNEL) == ADC_REGULAR_RANK_19) \|\| \
<>	128:9bcdf88f62b0	1168	((CHANNEL) == ADC_REGULAR_RANK_20) \|\| \
<>	128:9bcdf88f62b0	1169	((CHANNEL) == ADC_REGULAR_RANK_21) \|\| \
<>	128:9bcdf88f62b0	1170	((CHANNEL) == ADC_REGULAR_RANK_22) \|\| \
<>	128:9bcdf88f62b0	1171	((CHANNEL) == ADC_REGULAR_RANK_23) \|\| \
<>	128:9bcdf88f62b0	1172	((CHANNEL) == ADC_REGULAR_RANK_24) \|\| \
<>	128:9bcdf88f62b0	1173	((CHANNEL) == ADC_REGULAR_RANK_25) \|\| \
<>	128:9bcdf88f62b0	1174	((CHANNEL) == ADC_REGULAR_RANK_26) \|\| \
<>	128:9bcdf88f62b0	1175	((CHANNEL) == ADC_REGULAR_RANK_27) )
<>	128:9bcdf88f62b0	1176	#endif /* STM32L100xC \|\| STM32L151xC \|\| STM32L152xC \|\| STM32L162xC \|\| STM32L151xCA \|\| STM32L151xD \|\| STM32L152xCA \|\| STM32L152xD \|\| STM32L162xCA \|\| STM32L162xD \|\| STM32L151xE \|\| STM32L151xDX \|\| STM32L152xE \|\| STM32L152xDX \|\| STM32L162xE \|\| STM32L162xDX */
<>	128:9bcdf88f62b0	1177
<>	128:9bcdf88f62b0	1178	#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) \|\| \
<>	128:9bcdf88f62b0	1179	((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) \|\| \
<>	128:9bcdf88f62b0	1180	((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) \|\| \
<>	128:9bcdf88f62b0	1181	((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) \|\| \
<>	128:9bcdf88f62b0	1182	((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) \|\| \
<>	128:9bcdf88f62b0	1183	((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) \|\| \
<>	128:9bcdf88f62b0	1184	((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
<>	128:9bcdf88f62b0	1185
<>	128:9bcdf88f62b0	1186	#define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) \|\| \
<>	128:9bcdf88f62b0	1187	((CONVERSION) == ADC_INJECTED_GROUP) \|\| \
<>	128:9bcdf88f62b0	1188	((CONVERSION) == ADC_REGULAR_INJECTED_GROUP) )
<>	128:9bcdf88f62b0	1189
<>	128:9bcdf88f62b0	1190	#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) \|\| \
<>	128:9bcdf88f62b0	1191	((EVENT) == ADC_FLAG_OVR) )
<>	128:9bcdf88f62b0	1192
<>	128:9bcdf88f62b0	1193	/**
<>	128:9bcdf88f62b0	1194	* @brief Verify that a ADC data is within range corresponding to
<>	128:9bcdf88f62b0	1195	* ADC resolution.
<>	128:9bcdf88f62b0	1196	* @param __RESOLUTION__: ADC resolution (12, 10, 8 or 6 bits).
<>	128:9bcdf88f62b0	1197	* @param __ADC_DATA__: value checked against the resolution.
<>	128:9bcdf88f62b0	1198	* @retval SET: ADC data is within range corresponding to ADC resolution
<>	128:9bcdf88f62b0	1199	* RESET: ADC data is not within range corresponding to ADC resolution
<>	128:9bcdf88f62b0	1200	*
<>	128:9bcdf88f62b0	1201	*/
<>	128:9bcdf88f62b0	1202	#define IS_ADC_RANGE(__RESOLUTION__, __ADC_DATA__) \
<>	128:9bcdf88f62b0	1203	((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_DATA__) <= ((uint32_t)0x0FFF))) \|\| \
<>	128:9bcdf88f62b0	1204	(((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_DATA__) <= ((uint32_t)0x03FF))) \|\| \
<>	128:9bcdf88f62b0	1205	(((__RESOLUTION__) == ADC_RESOLUTION_8B) && ((__ADC_DATA__) <= ((uint32_t)0x00FF))) \|\| \
<>	128:9bcdf88f62b0	1206	(((__RESOLUTION__) == ADC_RESOLUTION_6B) && ((__ADC_DATA__) <= ((uint32_t)0x003F))) )
<>	128:9bcdf88f62b0	1207
<>	128:9bcdf88f62b0	1208
<>	128:9bcdf88f62b0	1209	#if defined(STM32L100xC) \|\| defined (STM32L151xC) \|\| defined (STM32L152xC) \|\| defined (STM32L162xC) \|\| defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD) \|\| defined(STM32L151xE) \|\| defined(STM32L151xDX) \|\| defined (STM32L152xE) \|\| defined (STM32L152xDX) \|\| defined (STM32L162xE) \|\| defined (STM32L162xDX)
<>	128:9bcdf88f62b0	1210	#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)28)))
<>	128:9bcdf88f62b0	1211	#else
<>	128:9bcdf88f62b0	1212	#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)27)))
<>	128:9bcdf88f62b0	1213	#endif
<>	128:9bcdf88f62b0	1214
<>	128:9bcdf88f62b0	1215	#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
<>	128:9bcdf88f62b0	1216
<>	128:9bcdf88f62b0	1217	/**
<>	128:9bcdf88f62b0	1218	* @}
<>	128:9bcdf88f62b0	1219	*/
<>	128:9bcdf88f62b0	1220
<>	128:9bcdf88f62b0	1221
<>	128:9bcdf88f62b0	1222	/* Include ADC HAL Extension module */
<>	128:9bcdf88f62b0	1223	#include "stm32l1xx_hal_adc_ex.h"
<>	128:9bcdf88f62b0	1224
<>	128:9bcdf88f62b0	1225	/* Exported functions --------------------------------------------------------*/
<>	128:9bcdf88f62b0	1226	/** @addtogroup ADC_Exported_Functions
<>	128:9bcdf88f62b0	1227	* @{
<>	128:9bcdf88f62b0	1228	*/
<>	128:9bcdf88f62b0	1229
<>	128:9bcdf88f62b0	1230	/** @addtogroup ADC_Exported_Functions_Group1
<>	128:9bcdf88f62b0	1231	* @{
<>	128:9bcdf88f62b0	1232	*/
<>	128:9bcdf88f62b0	1233
<>	128:9bcdf88f62b0	1234
<>	128:9bcdf88f62b0	1235	/* Initialization and de-initialization functions **********************************/
<>	128:9bcdf88f62b0	1236	HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
<>	128:9bcdf88f62b0	1237	HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
<>	128:9bcdf88f62b0	1238	void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
<>	128:9bcdf88f62b0	1239	void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
<>	128:9bcdf88f62b0	1240	/**
<>	128:9bcdf88f62b0	1241	* @}
<>	128:9bcdf88f62b0	1242	*/
<>	128:9bcdf88f62b0	1243
<>	128:9bcdf88f62b0	1244	/* IO operation functions *****************************************************/
<>	128:9bcdf88f62b0	1245
<>	128:9bcdf88f62b0	1246	/** @addtogroup ADC_Exported_Functions_Group2
<>	128:9bcdf88f62b0	1247	* @{
<>	128:9bcdf88f62b0	1248	*/
<>	128:9bcdf88f62b0	1249
<>	128:9bcdf88f62b0	1250
<>	128:9bcdf88f62b0	1251	/* Blocking mode: Polling */
<>	128:9bcdf88f62b0	1252	HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
<>	128:9bcdf88f62b0	1253	HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
<>	128:9bcdf88f62b0	1254	HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
<>	128:9bcdf88f62b0	1255	HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
<>	128:9bcdf88f62b0	1256
<>	128:9bcdf88f62b0	1257	/* Non-blocking mode: Interruption */
<>	128:9bcdf88f62b0	1258	HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
<>	128:9bcdf88f62b0	1259	HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
<>	128:9bcdf88f62b0	1260
<>	128:9bcdf88f62b0	1261	/* Non-blocking mode: DMA */
<>	128:9bcdf88f62b0	1262	HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
<>	128:9bcdf88f62b0	1263	HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
<>	128:9bcdf88f62b0	1264
<>	128:9bcdf88f62b0	1265	/* ADC retrieve conversion value intended to be used with polling or interruption */
<>	128:9bcdf88f62b0	1266	uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
<>	128:9bcdf88f62b0	1267
<>	128:9bcdf88f62b0	1268	/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
<>	128:9bcdf88f62b0	1269	void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
<>	128:9bcdf88f62b0	1270	void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
<>	128:9bcdf88f62b0	1271	void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
<>	128:9bcdf88f62b0	1272	void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
<>	128:9bcdf88f62b0	1273	void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
<>	128:9bcdf88f62b0	1274	/**
<>	128:9bcdf88f62b0	1275	* @}
<>	128:9bcdf88f62b0	1276	*/
<>	128:9bcdf88f62b0	1277
<>	128:9bcdf88f62b0	1278
<>	128:9bcdf88f62b0	1279	/* Peripheral Control functions ***********************************************/
<>	128:9bcdf88f62b0	1280	/** @addtogroup ADC_Exported_Functions_Group3
<>	128:9bcdf88f62b0	1281	* @{
<>	128:9bcdf88f62b0	1282	*/
<>	128:9bcdf88f62b0	1283	HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
<>	128:9bcdf88f62b0	1284	HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
<>	128:9bcdf88f62b0	1285	/**
<>	128:9bcdf88f62b0	1286	* @}
<>	128:9bcdf88f62b0	1287	*/
<>	128:9bcdf88f62b0	1288
<>	128:9bcdf88f62b0	1289
<>	128:9bcdf88f62b0	1290	/* Peripheral State functions *************************************************/
<>	128:9bcdf88f62b0	1291	/** @addtogroup ADC_Exported_Functions_Group4
<>	128:9bcdf88f62b0	1292	* @{
<>	128:9bcdf88f62b0	1293	*/
<>	128:9bcdf88f62b0	1294	uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
<>	128:9bcdf88f62b0	1295	uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
<>	128:9bcdf88f62b0	1296	/**
<>	128:9bcdf88f62b0	1297	* @}
<>	128:9bcdf88f62b0	1298	*/
<>	128:9bcdf88f62b0	1299
<>	128:9bcdf88f62b0	1300
<>	128:9bcdf88f62b0	1301	/**
<>	128:9bcdf88f62b0	1302	* @}
<>	128:9bcdf88f62b0	1303	*/
<>	128:9bcdf88f62b0	1304
<>	128:9bcdf88f62b0	1305
<>	128:9bcdf88f62b0	1306	/* Internal HAL driver functions **********************************************/
<>	128:9bcdf88f62b0	1307	/** @addtogroup ADC_Private_Functions
<>	128:9bcdf88f62b0	1308	* @{
<>	128:9bcdf88f62b0	1309	*/
<>	128:9bcdf88f62b0	1310
<>	128:9bcdf88f62b0	1311	HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
<>	128:9bcdf88f62b0	1312	HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc);
<>	128:9bcdf88f62b0	1313	/**
<>	128:9bcdf88f62b0	1314	* @}
<>	128:9bcdf88f62b0	1315	*/
<>	128:9bcdf88f62b0	1316
<>	128:9bcdf88f62b0	1317
<>	128:9bcdf88f62b0	1318	/**
<>	128:9bcdf88f62b0	1319	* @}
<>	128:9bcdf88f62b0	1320	*/
<>	128:9bcdf88f62b0	1321
<>	128:9bcdf88f62b0	1322	/**
<>	128:9bcdf88f62b0	1323	* @}
<>	128:9bcdf88f62b0	1324	*/
<>	128:9bcdf88f62b0	1325
<>	128:9bcdf88f62b0	1326	#ifdef __cplusplus
<>	128:9bcdf88f62b0	1327	}
<>	128:9bcdf88f62b0	1328	#endif
<>	128:9bcdf88f62b0	1329
<>	128:9bcdf88f62b0	1330
<>	128:9bcdf88f62b0	1331	#endif /* __STM32L1xx_HAL_ADC_H */
<>	128:9bcdf88f62b0	1332
<>	128:9bcdf88f62b0	1333	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/