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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_KL05Z/clk_freqs.h@78:ed8466a608b4, 2014-02-18 (annotated)

Committer:
emilmont
Date:
Tue Feb 18 15:02:39 2014 +0000
Revision:
78:ed8466a608b4
Add KL05Z Target

Fix LPC11XX InterruptIn

Fix NUCLEO boards us_ticker

Fix NUCLEO_L152RE AnalogOut

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 78:ed8466a608b4 1 /* mbed Microcontroller Library
emilmont 78:ed8466a608b4 2 * Copyright (c) 2006-2013 ARM Limited
emilmont 78:ed8466a608b4 3 *
emilmont 78:ed8466a608b4 4 * Licensed under the Apache License, Version 2.0 (the "License");
emilmont 78:ed8466a608b4 5 * you may not use this file except in compliance with the License.
emilmont 78:ed8466a608b4 6 * You may obtain a copy of the License at
emilmont 78:ed8466a608b4 7 *
emilmont 78:ed8466a608b4 8 * http://www.apache.org/licenses/LICENSE-2.0
emilmont 78:ed8466a608b4 9 *
emilmont 78:ed8466a608b4 10 * Unless required by applicable law or agreed to in writing, software
emilmont 78:ed8466a608b4 11 * distributed under the License is distributed on an "AS IS" BASIS,
emilmont 78:ed8466a608b4 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
emilmont 78:ed8466a608b4 13 * See the License for the specific language governing permissions and
emilmont 78:ed8466a608b4 14 * limitations under the License.
emilmont 78:ed8466a608b4 15 */
emilmont 78:ed8466a608b4 16 #ifndef MBED_CLK_FREQS_H
emilmont 78:ed8466a608b4 17 #define MBED_CLK_FREQS_H
emilmont 78:ed8466a608b4 18
emilmont 78:ed8466a608b4 19 #ifdef __cplusplus
emilmont 78:ed8466a608b4 20 extern "C" {
emilmont 78:ed8466a608b4 21 #endif
emilmont 78:ed8466a608b4 22
emilmont 78:ed8466a608b4 23 #include "PeripheralPins.h"
emilmont 78:ed8466a608b4 24
emilmont 78:ed8466a608b4 25 //Get the peripheral bus clock frequency
emilmont 78:ed8466a608b4 26 static inline uint32_t bus_frequency(void) {
emilmont 78:ed8466a608b4 27 return SystemCoreClock / (((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT) + 1);
emilmont 78:ed8466a608b4 28 }
emilmont 78:ed8466a608b4 29
emilmont 78:ed8466a608b4 30 //Get external oscillator (crystal) frequency
emilmont 78:ed8466a608b4 31 static uint32_t extosc_frequency(void) {
emilmont 78:ed8466a608b4 32 uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT));
emilmont 78:ed8466a608b4 33
emilmont 78:ed8466a608b4 34 if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(2)) //MCG clock = external reference clock
emilmont 78:ed8466a608b4 35 return MCGClock;
emilmont 78:ed8466a608b4 36
emilmont 78:ed8466a608b4 37 uint32_t divider, multiplier;
emilmont 78:ed8466a608b4 38 #ifdef MCG_C5_PLLCLKEN0_MASK //PLL available
emilmont 78:ed8466a608b4 39 if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0)) { //PLL/FLL is selected
emilmont 78:ed8466a608b4 40 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { //FLL is selected
emilmont 78:ed8466a608b4 41 #endif
emilmont 78:ed8466a608b4 42 if ((MCG->S & MCG_S_IREFST_MASK) == 0x0u) { //FLL uses external reference
emilmont 78:ed8466a608b4 43 divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
emilmont 78:ed8466a608b4 44 if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u)
emilmont 78:ed8466a608b4 45 divider <<= 5u;
emilmont 78:ed8466a608b4 46 /* Select correct multiplier to calculate the MCG output clock */
emilmont 78:ed8466a608b4 47 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
emilmont 78:ed8466a608b4 48 case 0x0u:
emilmont 78:ed8466a608b4 49 multiplier = 640u;
emilmont 78:ed8466a608b4 50 break;
emilmont 78:ed8466a608b4 51 case 0x20u:
emilmont 78:ed8466a608b4 52 multiplier = 1280u;
emilmont 78:ed8466a608b4 53 break;
emilmont 78:ed8466a608b4 54 case 0x40u:
emilmont 78:ed8466a608b4 55 multiplier = 1920u;
emilmont 78:ed8466a608b4 56 break;
emilmont 78:ed8466a608b4 57 case 0x60u:
emilmont 78:ed8466a608b4 58 multiplier = 2560u;
emilmont 78:ed8466a608b4 59 break;
emilmont 78:ed8466a608b4 60 case 0x80u:
emilmont 78:ed8466a608b4 61 multiplier = 732u;
emilmont 78:ed8466a608b4 62 break;
emilmont 78:ed8466a608b4 63 case 0xA0u:
emilmont 78:ed8466a608b4 64 multiplier = 1464u;
emilmont 78:ed8466a608b4 65 break;
emilmont 78:ed8466a608b4 66 case 0xC0u:
emilmont 78:ed8466a608b4 67 multiplier = 2197u;
emilmont 78:ed8466a608b4 68 break;
emilmont 78:ed8466a608b4 69 case 0xE0u:
emilmont 78:ed8466a608b4 70 default:
emilmont 78:ed8466a608b4 71 multiplier = 2929u;
emilmont 78:ed8466a608b4 72 break;
emilmont 78:ed8466a608b4 73 }
emilmont 78:ed8466a608b4 74
emilmont 78:ed8466a608b4 75 return MCGClock * divider / multiplier;
emilmont 78:ed8466a608b4 76 }
emilmont 78:ed8466a608b4 77 #ifdef MCG_C5_PLLCLKEN0_MASK
emilmont 78:ed8466a608b4 78 } else { //PLL is selected
emilmont 78:ed8466a608b4 79 divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
emilmont 78:ed8466a608b4 80 multiplier = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
emilmont 78:ed8466a608b4 81 return MCGClock * divider / multiplier;
emilmont 78:ed8466a608b4 82 }
emilmont 78:ed8466a608b4 83 }
emilmont 78:ed8466a608b4 84 #endif
emilmont 78:ed8466a608b4 85
emilmont 78:ed8466a608b4 86 //In all other cases either there is no crystal or we cannot determine it
emilmont 78:ed8466a608b4 87 //For example when the FLL is running on the internal reference, and there is also an
emilmont 78:ed8466a608b4 88 //external crystal. However these are unlikely situations
emilmont 78:ed8466a608b4 89 return 0;
emilmont 78:ed8466a608b4 90 }
emilmont 78:ed8466a608b4 91
emilmont 78:ed8466a608b4 92 //Get MCG PLL/2 or FLL frequency, depending on which one is active, sets PLLFLLSEL bit
emilmont 78:ed8466a608b4 93 static uint32_t mcgpllfll_frequency(void) {
emilmont 78:ed8466a608b4 94 if ((MCG->C1 & MCG_C1_CLKS_MASK) != MCG_C1_CLKS(0)) //PLL/FLL is not selected
emilmont 78:ed8466a608b4 95 return 0;
emilmont 78:ed8466a608b4 96
emilmont 78:ed8466a608b4 97 uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT));
emilmont 78:ed8466a608b4 98 #ifdef MCG_C5_PLLCLKEN0_MASK
emilmont 78:ed8466a608b4 99 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { //FLL is selected
emilmont 78:ed8466a608b4 100 SIM->SOPT2 &= ~SIM_SOPT2_PLLFLLSEL_MASK; //MCG peripheral clock is FLL output
emilmont 78:ed8466a608b4 101 #endif
emilmont 78:ed8466a608b4 102 return MCGClock;
emilmont 78:ed8466a608b4 103 #ifdef MCG_C5_PLLCLKEN0_MASK
emilmont 78:ed8466a608b4 104 } else { //PLL is selected
emilmont 78:ed8466a608b4 105 SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; //MCG peripheral clock is PLL output
emilmont 78:ed8466a608b4 106 return (MCGClock >> 1);
emilmont 78:ed8466a608b4 107 }
emilmont 78:ed8466a608b4 108 #endif
emilmont 78:ed8466a608b4 109
emilmont 78:ed8466a608b4 110 //It is possible the SystemCoreClock isn't running on the PLL, and the PLL is still active
emilmont 78:ed8466a608b4 111 //for the peripherals, this is however an unlikely setup
emilmont 78:ed8466a608b4 112 }
emilmont 78:ed8466a608b4 113
emilmont 78:ed8466a608b4 114 #ifdef __cplusplus
emilmont 78:ed8466a608b4 115 }
emilmont 78:ed8466a608b4 116 #endif
emilmont 78:ed8466a608b4 117
emilmont 78:ed8466a608b4 118 #endif