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TARGET_STEVAL_3DP001V1/core_cm23.h@170:e95d10626187, 2018-09-06 (annotated)

Committer:: AnnaBridge
Date:: Thu Sep 06 13:39:34 2018 +0100
Revision:: 170:e95d10626187
Parent:: 169:a7c7b631e539

mbed library. Release version 163

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	161:aa5281ff4a02	1	/************************************************************************//
AnnaBridge	161:aa5281ff4a02	2	* @file core_cm23.h
AnnaBridge	161:aa5281ff4a02	3	* @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File
Anna Bridge	169:a7c7b631e539	4	* @version V5.0.4
Anna Bridge	169:a7c7b631e539	5	* @date 10. January 2018
AnnaBridge	161:aa5281ff4a02	6	******************************************************************************/
AnnaBridge	161:aa5281ff4a02	7	/*
Anna Bridge	169:a7c7b631e539	8	* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
AnnaBridge	161:aa5281ff4a02	9	*
AnnaBridge	161:aa5281ff4a02	10	* SPDX-License-Identifier: Apache-2.0
AnnaBridge	161:aa5281ff4a02	11	*
AnnaBridge	161:aa5281ff4a02	12	* Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge	161:aa5281ff4a02	13	* not use this file except in compliance with the License.
AnnaBridge	161:aa5281ff4a02	14	* You may obtain a copy of the License at
AnnaBridge	161:aa5281ff4a02	15	*
AnnaBridge	161:aa5281ff4a02	16	* www.apache.org/licenses/LICENSE-2.0
AnnaBridge	161:aa5281ff4a02	17	*
AnnaBridge	161:aa5281ff4a02	18	* Unless required by applicable law or agreed to in writing, software
AnnaBridge	161:aa5281ff4a02	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge	161:aa5281ff4a02	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge	161:aa5281ff4a02	21	* See the License for the specific language governing permissions and
AnnaBridge	161:aa5281ff4a02	22	* limitations under the License.
AnnaBridge	161:aa5281ff4a02	23	*/
AnnaBridge	161:aa5281ff4a02	24
AnnaBridge	161:aa5281ff4a02	25	#if defined ( __ICCARM__ )
Anna Bridge	169:a7c7b631e539	26	#pragma system_include /* treat file as system include file for MISRA check */
Anna Bridge	169:a7c7b631e539	27	#elif defined (__clang__)
AnnaBridge	161:aa5281ff4a02	28	#pragma clang system_header /* treat file as system include file */
AnnaBridge	161:aa5281ff4a02	29	#endif
AnnaBridge	161:aa5281ff4a02	30
AnnaBridge	161:aa5281ff4a02	31	#ifndef __CORE_CM23_H_GENERIC
AnnaBridge	161:aa5281ff4a02	32	#define __CORE_CM23_H_GENERIC
AnnaBridge	161:aa5281ff4a02	33
AnnaBridge	161:aa5281ff4a02	34	#include <stdint.h>
AnnaBridge	161:aa5281ff4a02	35
AnnaBridge	161:aa5281ff4a02	36	#ifdef __cplusplus
AnnaBridge	161:aa5281ff4a02	37	extern "C" {
AnnaBridge	161:aa5281ff4a02	38	#endif
AnnaBridge	161:aa5281ff4a02	39
AnnaBridge	161:aa5281ff4a02	40	/**
AnnaBridge	161:aa5281ff4a02	41	\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
AnnaBridge	161:aa5281ff4a02	42	CMSIS violates the following MISRA-C:2004 rules:
AnnaBridge	161:aa5281ff4a02	43
AnnaBridge	161:aa5281ff4a02	44	\li Required Rule 8.5, object/function definition in header file.<br>
AnnaBridge	161:aa5281ff4a02	45	Function definitions in header files are used to allow 'inlining'.
AnnaBridge	161:aa5281ff4a02	46
AnnaBridge	161:aa5281ff4a02	47	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
AnnaBridge	161:aa5281ff4a02	48	Unions are used for effective representation of core registers.
AnnaBridge	161:aa5281ff4a02	49
AnnaBridge	161:aa5281ff4a02	50	\li Advisory Rule 19.7, Function-like macro defined.<br>
AnnaBridge	161:aa5281ff4a02	51	Function-like macros are used to allow more efficient code.
AnnaBridge	161:aa5281ff4a02	52	*/
AnnaBridge	161:aa5281ff4a02	53
AnnaBridge	161:aa5281ff4a02	54
AnnaBridge	161:aa5281ff4a02	55	/*******************************************************************************
AnnaBridge	161:aa5281ff4a02	56	* CMSIS definitions
AnnaBridge	161:aa5281ff4a02	57	******************************************************************************/
AnnaBridge	161:aa5281ff4a02	58	/**
AnnaBridge	161:aa5281ff4a02	59	\ingroup Cortex_M23
AnnaBridge	161:aa5281ff4a02	60	@{
AnnaBridge	161:aa5281ff4a02	61	*/
AnnaBridge	161:aa5281ff4a02	62
AnnaBridge	161:aa5281ff4a02	63	#include "cmsis_version.h"
AnnaBridge	161:aa5281ff4a02	64
AnnaBridge	161:aa5281ff4a02	65	/* CMSIS definitions */
AnnaBridge	161:aa5281ff4a02	66	#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /!< \deprecated [31:16] CMSIS HAL main version /
AnnaBridge	161:aa5281ff4a02	67	#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /!< \deprecated [15:0] CMSIS HAL sub version /
AnnaBridge	161:aa5281ff4a02	68	#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) \| \
AnnaBridge	161:aa5281ff4a02	69	__CM23_CMSIS_VERSION_SUB ) /!< \deprecated CMSIS HAL version number /
AnnaBridge	161:aa5281ff4a02	70
AnnaBridge	161:aa5281ff4a02	71	#define __CORTEX_M (23U) /!< Cortex-M Core /
AnnaBridge	161:aa5281ff4a02	72
AnnaBridge	161:aa5281ff4a02	73	/** __FPU_USED indicates whether an FPU is used or not.
AnnaBridge	161:aa5281ff4a02	74	This core does not support an FPU at all
AnnaBridge	161:aa5281ff4a02	75	*/
AnnaBridge	161:aa5281ff4a02	76	#define __FPU_USED 0U
AnnaBridge	161:aa5281ff4a02	77
AnnaBridge	161:aa5281ff4a02	78	#if defined ( __CC_ARM )
AnnaBridge	161:aa5281ff4a02	79	#if defined __TARGET_FPU_VFP
AnnaBridge	161:aa5281ff4a02	80	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	161:aa5281ff4a02	81	#endif
AnnaBridge	161:aa5281ff4a02	82
AnnaBridge	161:aa5281ff4a02	83	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge	161:aa5281ff4a02	84	#if defined __ARM_PCS_VFP
AnnaBridge	161:aa5281ff4a02	85	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	161:aa5281ff4a02	86	#endif
AnnaBridge	161:aa5281ff4a02	87
AnnaBridge	161:aa5281ff4a02	88	#elif defined ( __GNUC__ )
AnnaBridge	161:aa5281ff4a02	89	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge	161:aa5281ff4a02	90	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	161:aa5281ff4a02	91	#endif
AnnaBridge	161:aa5281ff4a02	92
AnnaBridge	161:aa5281ff4a02	93	#elif defined ( __ICCARM__ )
AnnaBridge	161:aa5281ff4a02	94	#if defined __ARMVFP__
AnnaBridge	161:aa5281ff4a02	95	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	161:aa5281ff4a02	96	#endif
AnnaBridge	161:aa5281ff4a02	97
AnnaBridge	161:aa5281ff4a02	98	#elif defined ( __TI_ARM__ )
AnnaBridge	161:aa5281ff4a02	99	#if defined __TI_VFP_SUPPORT__
AnnaBridge	161:aa5281ff4a02	100	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	161:aa5281ff4a02	101	#endif
AnnaBridge	161:aa5281ff4a02	102
AnnaBridge	161:aa5281ff4a02	103	#elif defined ( __TASKING__ )
AnnaBridge	161:aa5281ff4a02	104	#if defined __FPU_VFP__
AnnaBridge	161:aa5281ff4a02	105	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	161:aa5281ff4a02	106	#endif
AnnaBridge	161:aa5281ff4a02	107
AnnaBridge	161:aa5281ff4a02	108	#elif defined ( __CSMC__ )
AnnaBridge	161:aa5281ff4a02	109	#if ( __CSMC__ & 0x400U)
AnnaBridge	161:aa5281ff4a02	110	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	161:aa5281ff4a02	111	#endif
AnnaBridge	161:aa5281ff4a02	112
AnnaBridge	161:aa5281ff4a02	113	#endif
AnnaBridge	161:aa5281ff4a02	114
AnnaBridge	161:aa5281ff4a02	115	#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge	161:aa5281ff4a02	116
AnnaBridge	161:aa5281ff4a02	117
AnnaBridge	161:aa5281ff4a02	118	#ifdef __cplusplus
AnnaBridge	161:aa5281ff4a02	119	}
AnnaBridge	161:aa5281ff4a02	120	#endif
AnnaBridge	161:aa5281ff4a02	121
AnnaBridge	161:aa5281ff4a02	122	#endif /* __CORE_CM23_H_GENERIC */
AnnaBridge	161:aa5281ff4a02	123
AnnaBridge	161:aa5281ff4a02	124	#ifndef __CMSIS_GENERIC
AnnaBridge	161:aa5281ff4a02	125
AnnaBridge	161:aa5281ff4a02	126	#ifndef __CORE_CM23_H_DEPENDANT
AnnaBridge	161:aa5281ff4a02	127	#define __CORE_CM23_H_DEPENDANT
AnnaBridge	161:aa5281ff4a02	128
AnnaBridge	161:aa5281ff4a02	129	#ifdef __cplusplus
AnnaBridge	161:aa5281ff4a02	130	extern "C" {
AnnaBridge	161:aa5281ff4a02	131	#endif
AnnaBridge	161:aa5281ff4a02	132
AnnaBridge	161:aa5281ff4a02	133	/* check device defines and use defaults */
AnnaBridge	161:aa5281ff4a02	134	#if defined __CHECK_DEVICE_DEFINES
AnnaBridge	161:aa5281ff4a02	135	#ifndef __CM23_REV
AnnaBridge	161:aa5281ff4a02	136	#define __CM23_REV 0x0000U
AnnaBridge	161:aa5281ff4a02	137	#warning "__CM23_REV not defined in device header file; using default!"
AnnaBridge	161:aa5281ff4a02	138	#endif
AnnaBridge	161:aa5281ff4a02	139
AnnaBridge	161:aa5281ff4a02	140	#ifndef __FPU_PRESENT
AnnaBridge	161:aa5281ff4a02	141	#define __FPU_PRESENT 0U
AnnaBridge	161:aa5281ff4a02	142	#warning "__FPU_PRESENT not defined in device header file; using default!"
AnnaBridge	161:aa5281ff4a02	143	#endif
AnnaBridge	161:aa5281ff4a02	144
AnnaBridge	161:aa5281ff4a02	145	#ifndef __MPU_PRESENT
AnnaBridge	161:aa5281ff4a02	146	#define __MPU_PRESENT 0U
AnnaBridge	161:aa5281ff4a02	147	#warning "__MPU_PRESENT not defined in device header file; using default!"
AnnaBridge	161:aa5281ff4a02	148	#endif
AnnaBridge	161:aa5281ff4a02	149
AnnaBridge	161:aa5281ff4a02	150	#ifndef __SAUREGION_PRESENT
AnnaBridge	161:aa5281ff4a02	151	#define __SAUREGION_PRESENT 0U
AnnaBridge	161:aa5281ff4a02	152	#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
AnnaBridge	161:aa5281ff4a02	153	#endif
AnnaBridge	161:aa5281ff4a02	154
AnnaBridge	161:aa5281ff4a02	155	#ifndef __VTOR_PRESENT
AnnaBridge	161:aa5281ff4a02	156	#define __VTOR_PRESENT 0U
AnnaBridge	161:aa5281ff4a02	157	#warning "__VTOR_PRESENT not defined in device header file; using default!"
AnnaBridge	161:aa5281ff4a02	158	#endif
AnnaBridge	161:aa5281ff4a02	159
AnnaBridge	161:aa5281ff4a02	160	#ifndef __NVIC_PRIO_BITS
AnnaBridge	161:aa5281ff4a02	161	#define __NVIC_PRIO_BITS 2U
AnnaBridge	161:aa5281ff4a02	162	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
AnnaBridge	161:aa5281ff4a02	163	#endif
AnnaBridge	161:aa5281ff4a02	164
AnnaBridge	161:aa5281ff4a02	165	#ifndef __Vendor_SysTickConfig
AnnaBridge	161:aa5281ff4a02	166	#define __Vendor_SysTickConfig 0U
AnnaBridge	161:aa5281ff4a02	167	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
AnnaBridge	161:aa5281ff4a02	168	#endif
AnnaBridge	161:aa5281ff4a02	169
AnnaBridge	161:aa5281ff4a02	170	#ifndef __ETM_PRESENT
AnnaBridge	161:aa5281ff4a02	171	#define __ETM_PRESENT 0U
AnnaBridge	161:aa5281ff4a02	172	#warning "__ETM_PRESENT not defined in device header file; using default!"
AnnaBridge	161:aa5281ff4a02	173	#endif
AnnaBridge	161:aa5281ff4a02	174
AnnaBridge	161:aa5281ff4a02	175	#ifndef __MTB_PRESENT
AnnaBridge	161:aa5281ff4a02	176	#define __MTB_PRESENT 0U
AnnaBridge	161:aa5281ff4a02	177	#warning "__MTB_PRESENT not defined in device header file; using default!"
AnnaBridge	161:aa5281ff4a02	178	#endif
AnnaBridge	161:aa5281ff4a02	179
AnnaBridge	161:aa5281ff4a02	180	#endif
AnnaBridge	161:aa5281ff4a02	181
AnnaBridge	161:aa5281ff4a02	182	/* IO definitions (access restrictions to peripheral registers) */
AnnaBridge	161:aa5281ff4a02	183	/**
AnnaBridge	161:aa5281ff4a02	184	\defgroup CMSIS_glob_defs CMSIS Global Defines
AnnaBridge	161:aa5281ff4a02	185
AnnaBridge	161:aa5281ff4a02	186	<strong>IO Type Qualifiers</strong> are used
AnnaBridge	161:aa5281ff4a02	187	\li to specify the access to peripheral variables.
AnnaBridge	161:aa5281ff4a02	188	\li for automatic generation of peripheral register debug information.
AnnaBridge	161:aa5281ff4a02	189	*/
AnnaBridge	161:aa5281ff4a02	190	#ifdef __cplusplus
AnnaBridge	161:aa5281ff4a02	191	#define __I volatile /!< Defines 'read only' permissions /
AnnaBridge	161:aa5281ff4a02	192	#else
AnnaBridge	161:aa5281ff4a02	193	#define __I volatile const /!< Defines 'read only' permissions /
AnnaBridge	161:aa5281ff4a02	194	#endif
AnnaBridge	161:aa5281ff4a02	195	#define __O volatile /!< Defines 'write only' permissions /
AnnaBridge	161:aa5281ff4a02	196	#define __IO volatile /!< Defines 'read / write' permissions /
AnnaBridge	161:aa5281ff4a02	197
AnnaBridge	161:aa5281ff4a02	198	/* following defines should be used for structure members */
AnnaBridge	161:aa5281ff4a02	199	#define __IM volatile const /! Defines 'read only' structure member permissions /
AnnaBridge	161:aa5281ff4a02	200	#define __OM volatile /! Defines 'write only' structure member permissions /
AnnaBridge	161:aa5281ff4a02	201	#define __IOM volatile /! Defines 'read / write' structure member permissions /
AnnaBridge	161:aa5281ff4a02	202
AnnaBridge	161:aa5281ff4a02	203	/@} end of group Cortex_M23 /
AnnaBridge	161:aa5281ff4a02	204
AnnaBridge	161:aa5281ff4a02	205
AnnaBridge	161:aa5281ff4a02	206
AnnaBridge	161:aa5281ff4a02	207	/*******************************************************************************
AnnaBridge	161:aa5281ff4a02	208	* Register Abstraction
AnnaBridge	161:aa5281ff4a02	209	Core Register contain:
AnnaBridge	161:aa5281ff4a02	210	- Core Register
AnnaBridge	161:aa5281ff4a02	211	- Core NVIC Register
AnnaBridge	161:aa5281ff4a02	212	- Core SCB Register
AnnaBridge	161:aa5281ff4a02	213	- Core SysTick Register
AnnaBridge	161:aa5281ff4a02	214	- Core Debug Register
AnnaBridge	161:aa5281ff4a02	215	- Core MPU Register
AnnaBridge	161:aa5281ff4a02	216	- Core SAU Register
AnnaBridge	161:aa5281ff4a02	217	******************************************************************************/
AnnaBridge	161:aa5281ff4a02	218	/**
AnnaBridge	161:aa5281ff4a02	219	\defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge	161:aa5281ff4a02	220	\brief Type definitions and defines for Cortex-M processor based devices.
AnnaBridge	161:aa5281ff4a02	221	*/
AnnaBridge	161:aa5281ff4a02	222
AnnaBridge	161:aa5281ff4a02	223	/**
AnnaBridge	161:aa5281ff4a02	224	\ingroup CMSIS_core_register
AnnaBridge	161:aa5281ff4a02	225	\defgroup CMSIS_CORE Status and Control Registers
AnnaBridge	161:aa5281ff4a02	226	\brief Core Register type definitions.
AnnaBridge	161:aa5281ff4a02	227	@{
AnnaBridge	161:aa5281ff4a02	228	*/
AnnaBridge	161:aa5281ff4a02	229
AnnaBridge	161:aa5281ff4a02	230	/**
AnnaBridge	161:aa5281ff4a02	231	\brief Union type to access the Application Program Status Register (APSR).
AnnaBridge	161:aa5281ff4a02	232	*/
AnnaBridge	161:aa5281ff4a02	233	typedef union
AnnaBridge	161:aa5281ff4a02	234	{
AnnaBridge	161:aa5281ff4a02	235	struct
AnnaBridge	161:aa5281ff4a02	236	{
AnnaBridge	161:aa5281ff4a02	237	uint32_t _reserved0:28; /!< bit: 0..27 Reserved /
AnnaBridge	161:aa5281ff4a02	238	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
AnnaBridge	161:aa5281ff4a02	239	uint32_t C:1; /!< bit: 29 Carry condition code flag /
AnnaBridge	161:aa5281ff4a02	240	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
AnnaBridge	161:aa5281ff4a02	241	uint32_t N:1; /!< bit: 31 Negative condition code flag /
AnnaBridge	161:aa5281ff4a02	242	} b; /!< Structure used for bit access /
AnnaBridge	161:aa5281ff4a02	243	uint32_t w; /!< Type used for word access /
AnnaBridge	161:aa5281ff4a02	244	} APSR_Type;
AnnaBridge	161:aa5281ff4a02	245
AnnaBridge	161:aa5281ff4a02	246	/* APSR Register Definitions */
AnnaBridge	161:aa5281ff4a02	247	#define APSR_N_Pos 31U /!< APSR: N Position /
AnnaBridge	161:aa5281ff4a02	248	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
AnnaBridge	161:aa5281ff4a02	249
AnnaBridge	161:aa5281ff4a02	250	#define APSR_Z_Pos 30U /!< APSR: Z Position /
AnnaBridge	161:aa5281ff4a02	251	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
AnnaBridge	161:aa5281ff4a02	252
AnnaBridge	161:aa5281ff4a02	253	#define APSR_C_Pos 29U /!< APSR: C Position /
AnnaBridge	161:aa5281ff4a02	254	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
AnnaBridge	161:aa5281ff4a02	255
AnnaBridge	161:aa5281ff4a02	256	#define APSR_V_Pos 28U /!< APSR: V Position /
AnnaBridge	161:aa5281ff4a02	257	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
AnnaBridge	161:aa5281ff4a02	258
AnnaBridge	161:aa5281ff4a02	259
AnnaBridge	161:aa5281ff4a02	260	/**
AnnaBridge	161:aa5281ff4a02	261	\brief Union type to access the Interrupt Program Status Register (IPSR).
AnnaBridge	161:aa5281ff4a02	262	*/
AnnaBridge	161:aa5281ff4a02	263	typedef union
AnnaBridge	161:aa5281ff4a02	264	{
AnnaBridge	161:aa5281ff4a02	265	struct
AnnaBridge	161:aa5281ff4a02	266	{
AnnaBridge	161:aa5281ff4a02	267	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
AnnaBridge	161:aa5281ff4a02	268	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
AnnaBridge	161:aa5281ff4a02	269	} b; /!< Structure used for bit access /
AnnaBridge	161:aa5281ff4a02	270	uint32_t w; /!< Type used for word access /
AnnaBridge	161:aa5281ff4a02	271	} IPSR_Type;
AnnaBridge	161:aa5281ff4a02	272
AnnaBridge	161:aa5281ff4a02	273	/* IPSR Register Definitions */
AnnaBridge	161:aa5281ff4a02	274	#define IPSR_ISR_Pos 0U /!< IPSR: ISR Position /
AnnaBridge	161:aa5281ff4a02	275	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
AnnaBridge	161:aa5281ff4a02	276
AnnaBridge	161:aa5281ff4a02	277
AnnaBridge	161:aa5281ff4a02	278	/**
AnnaBridge	161:aa5281ff4a02	279	\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
AnnaBridge	161:aa5281ff4a02	280	*/
AnnaBridge	161:aa5281ff4a02	281	typedef union
AnnaBridge	161:aa5281ff4a02	282	{
AnnaBridge	161:aa5281ff4a02	283	struct
AnnaBridge	161:aa5281ff4a02	284	{
AnnaBridge	161:aa5281ff4a02	285	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
AnnaBridge	161:aa5281ff4a02	286	uint32_t _reserved0:15; /!< bit: 9..23 Reserved /
AnnaBridge	161:aa5281ff4a02	287	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
AnnaBridge	161:aa5281ff4a02	288	uint32_t _reserved1:3; /!< bit: 25..27 Reserved /
AnnaBridge	161:aa5281ff4a02	289	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
AnnaBridge	161:aa5281ff4a02	290	uint32_t C:1; /!< bit: 29 Carry condition code flag /
AnnaBridge	161:aa5281ff4a02	291	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
AnnaBridge	161:aa5281ff4a02	292	uint32_t N:1; /!< bit: 31 Negative condition code flag /
AnnaBridge	161:aa5281ff4a02	293	} b; /!< Structure used for bit access /
AnnaBridge	161:aa5281ff4a02	294	uint32_t w; /!< Type used for word access /
AnnaBridge	161:aa5281ff4a02	295	} xPSR_Type;
AnnaBridge	161:aa5281ff4a02	296
AnnaBridge	161:aa5281ff4a02	297	/* xPSR Register Definitions */
AnnaBridge	161:aa5281ff4a02	298	#define xPSR_N_Pos 31U /!< xPSR: N Position /
AnnaBridge	161:aa5281ff4a02	299	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
AnnaBridge	161:aa5281ff4a02	300
AnnaBridge	161:aa5281ff4a02	301	#define xPSR_Z_Pos 30U /!< xPSR: Z Position /
AnnaBridge	161:aa5281ff4a02	302	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
AnnaBridge	161:aa5281ff4a02	303
AnnaBridge	161:aa5281ff4a02	304	#define xPSR_C_Pos 29U /!< xPSR: C Position /
AnnaBridge	161:aa5281ff4a02	305	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
AnnaBridge	161:aa5281ff4a02	306
AnnaBridge	161:aa5281ff4a02	307	#define xPSR_V_Pos 28U /!< xPSR: V Position /
AnnaBridge	161:aa5281ff4a02	308	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
AnnaBridge	161:aa5281ff4a02	309
AnnaBridge	161:aa5281ff4a02	310	#define xPSR_T_Pos 24U /!< xPSR: T Position /
AnnaBridge	161:aa5281ff4a02	311	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
AnnaBridge	161:aa5281ff4a02	312
AnnaBridge	161:aa5281ff4a02	313	#define xPSR_ISR_Pos 0U /!< xPSR: ISR Position /
AnnaBridge	161:aa5281ff4a02	314	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
AnnaBridge	161:aa5281ff4a02	315
AnnaBridge	161:aa5281ff4a02	316
AnnaBridge	161:aa5281ff4a02	317	/**
AnnaBridge	161:aa5281ff4a02	318	\brief Union type to access the Control Registers (CONTROL).
AnnaBridge	161:aa5281ff4a02	319	*/
AnnaBridge	161:aa5281ff4a02	320	typedef union
AnnaBridge	161:aa5281ff4a02	321	{
AnnaBridge	161:aa5281ff4a02	322	struct
AnnaBridge	161:aa5281ff4a02	323	{
AnnaBridge	161:aa5281ff4a02	324	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
AnnaBridge	161:aa5281ff4a02	325	uint32_t SPSEL:1; /!< bit: 1 Stack-pointer select /
AnnaBridge	161:aa5281ff4a02	326	uint32_t _reserved1:30; /!< bit: 2..31 Reserved /
AnnaBridge	161:aa5281ff4a02	327	} b; /!< Structure used for bit access /
AnnaBridge	161:aa5281ff4a02	328	uint32_t w; /!< Type used for word access /
AnnaBridge	161:aa5281ff4a02	329	} CONTROL_Type;
AnnaBridge	161:aa5281ff4a02	330
AnnaBridge	161:aa5281ff4a02	331	/* CONTROL Register Definitions */
AnnaBridge	161:aa5281ff4a02	332	#define CONTROL_SPSEL_Pos 1U /!< CONTROL: SPSEL Position /
AnnaBridge	161:aa5281ff4a02	333	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
AnnaBridge	161:aa5281ff4a02	334
AnnaBridge	161:aa5281ff4a02	335	#define CONTROL_nPRIV_Pos 0U /!< CONTROL: nPRIV Position /
AnnaBridge	161:aa5281ff4a02	336	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
AnnaBridge	161:aa5281ff4a02	337
AnnaBridge	161:aa5281ff4a02	338	/@} end of group CMSIS_CORE /
AnnaBridge	161:aa5281ff4a02	339
AnnaBridge	161:aa5281ff4a02	340
AnnaBridge	161:aa5281ff4a02	341	/**
AnnaBridge	161:aa5281ff4a02	342	\ingroup CMSIS_core_register
AnnaBridge	161:aa5281ff4a02	343	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge	161:aa5281ff4a02	344	\brief Type definitions for the NVIC Registers
AnnaBridge	161:aa5281ff4a02	345	@{
AnnaBridge	161:aa5281ff4a02	346	*/
AnnaBridge	161:aa5281ff4a02	347
AnnaBridge	161:aa5281ff4a02	348	/**
AnnaBridge	161:aa5281ff4a02	349	\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
AnnaBridge	161:aa5281ff4a02	350	*/
AnnaBridge	161:aa5281ff4a02	351	typedef struct
AnnaBridge	161:aa5281ff4a02	352	{
AnnaBridge	161:aa5281ff4a02	353	__IOM uint32_t ISER[16U]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
AnnaBridge	161:aa5281ff4a02	354	uint32_t RESERVED0[16U];
AnnaBridge	161:aa5281ff4a02	355	__IOM uint32_t ICER[16U]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
AnnaBridge	161:aa5281ff4a02	356	uint32_t RSERVED1[16U];
AnnaBridge	161:aa5281ff4a02	357	__IOM uint32_t ISPR[16U]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
AnnaBridge	161:aa5281ff4a02	358	uint32_t RESERVED2[16U];
AnnaBridge	161:aa5281ff4a02	359	__IOM uint32_t ICPR[16U]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
AnnaBridge	161:aa5281ff4a02	360	uint32_t RESERVED3[16U];
AnnaBridge	161:aa5281ff4a02	361	__IOM uint32_t IABR[16U]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
AnnaBridge	161:aa5281ff4a02	362	uint32_t RESERVED4[16U];
AnnaBridge	161:aa5281ff4a02	363	__IOM uint32_t ITNS[16U]; /!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register /
AnnaBridge	161:aa5281ff4a02	364	uint32_t RESERVED5[16U];
AnnaBridge	161:aa5281ff4a02	365	__IOM uint32_t IPR[124U]; /!< Offset: 0x300 (R/W) Interrupt Priority Register /
AnnaBridge	161:aa5281ff4a02	366	} NVIC_Type;
AnnaBridge	161:aa5281ff4a02	367
AnnaBridge	161:aa5281ff4a02	368	/@} end of group CMSIS_NVIC /
AnnaBridge	161:aa5281ff4a02	369
AnnaBridge	161:aa5281ff4a02	370
AnnaBridge	161:aa5281ff4a02	371	/**
AnnaBridge	161:aa5281ff4a02	372	\ingroup CMSIS_core_register
AnnaBridge	161:aa5281ff4a02	373	\defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge	161:aa5281ff4a02	374	\brief Type definitions for the System Control Block Registers
AnnaBridge	161:aa5281ff4a02	375	@{
AnnaBridge	161:aa5281ff4a02	376	*/
AnnaBridge	161:aa5281ff4a02	377
AnnaBridge	161:aa5281ff4a02	378	/**
AnnaBridge	161:aa5281ff4a02	379	\brief Structure type to access the System Control Block (SCB).
AnnaBridge	161:aa5281ff4a02	380	*/
AnnaBridge	161:aa5281ff4a02	381	typedef struct
AnnaBridge	161:aa5281ff4a02	382	{
AnnaBridge	161:aa5281ff4a02	383	__IM uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
AnnaBridge	161:aa5281ff4a02	384	__IOM uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
AnnaBridge	161:aa5281ff4a02	385	#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge	161:aa5281ff4a02	386	__IOM uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
AnnaBridge	161:aa5281ff4a02	387	#else
AnnaBridge	161:aa5281ff4a02	388	uint32_t RESERVED0;
AnnaBridge	161:aa5281ff4a02	389	#endif
AnnaBridge	161:aa5281ff4a02	390	__IOM uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
AnnaBridge	161:aa5281ff4a02	391	__IOM uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
AnnaBridge	161:aa5281ff4a02	392	__IOM uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
AnnaBridge	161:aa5281ff4a02	393	uint32_t RESERVED1;
AnnaBridge	161:aa5281ff4a02	394	__IOM uint32_t SHPR[2U]; /!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED /
AnnaBridge	161:aa5281ff4a02	395	__IOM uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
AnnaBridge	161:aa5281ff4a02	396	} SCB_Type;
AnnaBridge	161:aa5281ff4a02	397
AnnaBridge	161:aa5281ff4a02	398	/* SCB CPUID Register Definitions */
AnnaBridge	161:aa5281ff4a02	399	#define SCB_CPUID_IMPLEMENTER_Pos 24U /!< SCB CPUID: IMPLEMENTER Position /
AnnaBridge	161:aa5281ff4a02	400	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
AnnaBridge	161:aa5281ff4a02	401
AnnaBridge	161:aa5281ff4a02	402	#define SCB_CPUID_VARIANT_Pos 20U /!< SCB CPUID: VARIANT Position /
AnnaBridge	161:aa5281ff4a02	403	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
AnnaBridge	161:aa5281ff4a02	404
AnnaBridge	161:aa5281ff4a02	405	#define SCB_CPUID_ARCHITECTURE_Pos 16U /!< SCB CPUID: ARCHITECTURE Position /
AnnaBridge	161:aa5281ff4a02	406	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
AnnaBridge	161:aa5281ff4a02	407
AnnaBridge	161:aa5281ff4a02	408	#define SCB_CPUID_PARTNO_Pos 4U /!< SCB CPUID: PARTNO Position /
AnnaBridge	161:aa5281ff4a02	409	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
AnnaBridge	161:aa5281ff4a02	410
AnnaBridge	161:aa5281ff4a02	411	#define SCB_CPUID_REVISION_Pos 0U /!< SCB CPUID: REVISION Position /
AnnaBridge	161:aa5281ff4a02	412	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
AnnaBridge	161:aa5281ff4a02	413
AnnaBridge	161:aa5281ff4a02	414	/* SCB Interrupt Control State Register Definitions */
AnnaBridge	161:aa5281ff4a02	415	#define SCB_ICSR_PENDNMISET_Pos 31U /!< SCB ICSR: PENDNMISET Position /
AnnaBridge	161:aa5281ff4a02	416	#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /!< SCB ICSR: PENDNMISET Mask /
AnnaBridge	161:aa5281ff4a02	417
AnnaBridge	161:aa5281ff4a02	418	#define SCB_ICSR_PENDNMICLR_Pos 30U /!< SCB ICSR: PENDNMICLR Position /
AnnaBridge	161:aa5281ff4a02	419	#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /!< SCB ICSR: PENDNMICLR Mask /
AnnaBridge	161:aa5281ff4a02	420
AnnaBridge	161:aa5281ff4a02	421	#define SCB_ICSR_PENDSVSET_Pos 28U /!< SCB ICSR: PENDSVSET Position /
AnnaBridge	161:aa5281ff4a02	422	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
AnnaBridge	161:aa5281ff4a02	423
AnnaBridge	161:aa5281ff4a02	424	#define SCB_ICSR_PENDSVCLR_Pos 27U /!< SCB ICSR: PENDSVCLR Position /
AnnaBridge	161:aa5281ff4a02	425	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
AnnaBridge	161:aa5281ff4a02	426
AnnaBridge	161:aa5281ff4a02	427	#define SCB_ICSR_PENDSTSET_Pos 26U /!< SCB ICSR: PENDSTSET Position /
AnnaBridge	161:aa5281ff4a02	428	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
AnnaBridge	161:aa5281ff4a02	429
AnnaBridge	161:aa5281ff4a02	430	#define SCB_ICSR_PENDSTCLR_Pos 25U /!< SCB ICSR: PENDSTCLR Position /
AnnaBridge	161:aa5281ff4a02	431	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
AnnaBridge	161:aa5281ff4a02	432
AnnaBridge	161:aa5281ff4a02	433	#define SCB_ICSR_STTNS_Pos 24U /!< SCB ICSR: STTNS Position (Security Extension) /
AnnaBridge	161:aa5281ff4a02	434	#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /!< SCB ICSR: STTNS Mask (Security Extension) /
AnnaBridge	161:aa5281ff4a02	435
AnnaBridge	161:aa5281ff4a02	436	#define SCB_ICSR_ISRPREEMPT_Pos 23U /!< SCB ICSR: ISRPREEMPT Position /
AnnaBridge	161:aa5281ff4a02	437	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
AnnaBridge	161:aa5281ff4a02	438
AnnaBridge	161:aa5281ff4a02	439	#define SCB_ICSR_ISRPENDING_Pos 22U /!< SCB ICSR: ISRPENDING Position /
AnnaBridge	161:aa5281ff4a02	440	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
AnnaBridge	161:aa5281ff4a02	441
AnnaBridge	161:aa5281ff4a02	442	#define SCB_ICSR_VECTPENDING_Pos 12U /!< SCB ICSR: VECTPENDING Position /
AnnaBridge	161:aa5281ff4a02	443	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
AnnaBridge	161:aa5281ff4a02	444
AnnaBridge	161:aa5281ff4a02	445	#define SCB_ICSR_RETTOBASE_Pos 11U /!< SCB ICSR: RETTOBASE Position /
AnnaBridge	161:aa5281ff4a02	446	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
AnnaBridge	161:aa5281ff4a02	447
AnnaBridge	161:aa5281ff4a02	448	#define SCB_ICSR_VECTACTIVE_Pos 0U /!< SCB ICSR: VECTACTIVE Position /
AnnaBridge	161:aa5281ff4a02	449	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
AnnaBridge	161:aa5281ff4a02	450
AnnaBridge	161:aa5281ff4a02	451	#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge	161:aa5281ff4a02	452	/* SCB Vector Table Offset Register Definitions */
AnnaBridge	161:aa5281ff4a02	453	#define SCB_VTOR_TBLOFF_Pos 7U /!< SCB VTOR: TBLOFF Position /
AnnaBridge	161:aa5281ff4a02	454	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
AnnaBridge	161:aa5281ff4a02	455	#endif
AnnaBridge	161:aa5281ff4a02	456
AnnaBridge	161:aa5281ff4a02	457	/* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge	161:aa5281ff4a02	458	#define SCB_AIRCR_VECTKEY_Pos 16U /!< SCB AIRCR: VECTKEY Position /
AnnaBridge	161:aa5281ff4a02	459	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
AnnaBridge	161:aa5281ff4a02	460
AnnaBridge	161:aa5281ff4a02	461	#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /!< SCB AIRCR: VECTKEYSTAT Position /
AnnaBridge	161:aa5281ff4a02	462	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
AnnaBridge	161:aa5281ff4a02	463
AnnaBridge	161:aa5281ff4a02	464	#define SCB_AIRCR_ENDIANESS_Pos 15U /!< SCB AIRCR: ENDIANESS Position /
AnnaBridge	161:aa5281ff4a02	465	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
AnnaBridge	161:aa5281ff4a02	466
AnnaBridge	161:aa5281ff4a02	467	#define SCB_AIRCR_PRIS_Pos 14U /!< SCB AIRCR: PRIS Position /
AnnaBridge	161:aa5281ff4a02	468	#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /!< SCB AIRCR: PRIS Mask /
AnnaBridge	161:aa5281ff4a02	469
AnnaBridge	161:aa5281ff4a02	470	#define SCB_AIRCR_BFHFNMINS_Pos 13U /!< SCB AIRCR: BFHFNMINS Position /
AnnaBridge	161:aa5281ff4a02	471	#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /!< SCB AIRCR: BFHFNMINS Mask /
AnnaBridge	161:aa5281ff4a02	472
AnnaBridge	161:aa5281ff4a02	473	#define SCB_AIRCR_SYSRESETREQS_Pos 3U /!< SCB AIRCR: SYSRESETREQS Position /
AnnaBridge	161:aa5281ff4a02	474	#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /!< SCB AIRCR: SYSRESETREQS Mask /
AnnaBridge	161:aa5281ff4a02	475
AnnaBridge	161:aa5281ff4a02	476	#define SCB_AIRCR_SYSRESETREQ_Pos 2U /!< SCB AIRCR: SYSRESETREQ Position /
AnnaBridge	161:aa5281ff4a02	477	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
AnnaBridge	161:aa5281ff4a02	478
AnnaBridge	161:aa5281ff4a02	479	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /!< SCB AIRCR: VECTCLRACTIVE Position /
AnnaBridge	161:aa5281ff4a02	480	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
AnnaBridge	161:aa5281ff4a02	481
AnnaBridge	161:aa5281ff4a02	482	/* SCB System Control Register Definitions */
AnnaBridge	161:aa5281ff4a02	483	#define SCB_SCR_SEVONPEND_Pos 4U /!< SCB SCR: SEVONPEND Position /
AnnaBridge	161:aa5281ff4a02	484	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
AnnaBridge	161:aa5281ff4a02	485
AnnaBridge	161:aa5281ff4a02	486	#define SCB_SCR_SLEEPDEEPS_Pos 3U /!< SCB SCR: SLEEPDEEPS Position /
AnnaBridge	161:aa5281ff4a02	487	#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /!< SCB SCR: SLEEPDEEPS Mask /
AnnaBridge	161:aa5281ff4a02	488
AnnaBridge	161:aa5281ff4a02	489	#define SCB_SCR_SLEEPDEEP_Pos 2U /!< SCB SCR: SLEEPDEEP Position /
AnnaBridge	161:aa5281ff4a02	490	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
AnnaBridge	161:aa5281ff4a02	491
AnnaBridge	161:aa5281ff4a02	492	#define SCB_SCR_SLEEPONEXIT_Pos 1U /!< SCB SCR: SLEEPONEXIT Position /
AnnaBridge	161:aa5281ff4a02	493	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
AnnaBridge	161:aa5281ff4a02	494
AnnaBridge	161:aa5281ff4a02	495	/* SCB Configuration Control Register Definitions */
AnnaBridge	161:aa5281ff4a02	496	#define SCB_CCR_BP_Pos 18U /!< SCB CCR: BP Position /
AnnaBridge	161:aa5281ff4a02	497	#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /!< SCB CCR: BP Mask /
AnnaBridge	161:aa5281ff4a02	498
AnnaBridge	161:aa5281ff4a02	499	#define SCB_CCR_IC_Pos 17U /!< SCB CCR: IC Position /
AnnaBridge	161:aa5281ff4a02	500	#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /!< SCB CCR: IC Mask /
AnnaBridge	161:aa5281ff4a02	501
AnnaBridge	161:aa5281ff4a02	502	#define SCB_CCR_DC_Pos 16U /!< SCB CCR: DC Position /
AnnaBridge	161:aa5281ff4a02	503	#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /!< SCB CCR: DC Mask /
AnnaBridge	161:aa5281ff4a02	504
AnnaBridge	161:aa5281ff4a02	505	#define SCB_CCR_STKOFHFNMIGN_Pos 10U /!< SCB CCR: STKOFHFNMIGN Position /
AnnaBridge	161:aa5281ff4a02	506	#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /!< SCB CCR: STKOFHFNMIGN Mask /
AnnaBridge	161:aa5281ff4a02	507
AnnaBridge	161:aa5281ff4a02	508	#define SCB_CCR_BFHFNMIGN_Pos 8U /!< SCB CCR: BFHFNMIGN Position /
AnnaBridge	161:aa5281ff4a02	509	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
AnnaBridge	161:aa5281ff4a02	510
AnnaBridge	161:aa5281ff4a02	511	#define SCB_CCR_DIV_0_TRP_Pos 4U /!< SCB CCR: DIV_0_TRP Position /
AnnaBridge	161:aa5281ff4a02	512	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
AnnaBridge	161:aa5281ff4a02	513
AnnaBridge	161:aa5281ff4a02	514	#define SCB_CCR_UNALIGN_TRP_Pos 3U /!< SCB CCR: UNALIGN_TRP Position /
AnnaBridge	161:aa5281ff4a02	515	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
AnnaBridge	161:aa5281ff4a02	516
AnnaBridge	161:aa5281ff4a02	517	#define SCB_CCR_USERSETMPEND_Pos 1U /!< SCB CCR: USERSETMPEND Position /
AnnaBridge	161:aa5281ff4a02	518	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
AnnaBridge	161:aa5281ff4a02	519
AnnaBridge	161:aa5281ff4a02	520	/* SCB System Handler Control and State Register Definitions */
AnnaBridge	161:aa5281ff4a02	521	#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /!< SCB SHCSR: HARDFAULTPENDED Position /
AnnaBridge	161:aa5281ff4a02	522	#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /!< SCB SHCSR: HARDFAULTPENDED Mask /
AnnaBridge	161:aa5281ff4a02	523
AnnaBridge	161:aa5281ff4a02	524	#define SCB_SHCSR_SVCALLPENDED_Pos 15U /!< SCB SHCSR: SVCALLPENDED Position /
AnnaBridge	161:aa5281ff4a02	525	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
AnnaBridge	161:aa5281ff4a02	526
AnnaBridge	161:aa5281ff4a02	527	#define SCB_SHCSR_SYSTICKACT_Pos 11U /!< SCB SHCSR: SYSTICKACT Position /
AnnaBridge	161:aa5281ff4a02	528	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
AnnaBridge	161:aa5281ff4a02	529
AnnaBridge	161:aa5281ff4a02	530	#define SCB_SHCSR_PENDSVACT_Pos 10U /!< SCB SHCSR: PENDSVACT Position /
AnnaBridge	161:aa5281ff4a02	531	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
AnnaBridge	161:aa5281ff4a02	532
AnnaBridge	161:aa5281ff4a02	533	#define SCB_SHCSR_SVCALLACT_Pos 7U /!< SCB SHCSR: SVCALLACT Position /
AnnaBridge	161:aa5281ff4a02	534	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
AnnaBridge	161:aa5281ff4a02	535
AnnaBridge	161:aa5281ff4a02	536	#define SCB_SHCSR_NMIACT_Pos 5U /!< SCB SHCSR: NMIACT Position /
AnnaBridge	161:aa5281ff4a02	537	#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /!< SCB SHCSR: NMIACT Mask /
AnnaBridge	161:aa5281ff4a02	538
AnnaBridge	161:aa5281ff4a02	539	#define SCB_SHCSR_HARDFAULTACT_Pos 2U /!< SCB SHCSR: HARDFAULTACT Position /
AnnaBridge	161:aa5281ff4a02	540	#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /!< SCB SHCSR: HARDFAULTACT Mask /
AnnaBridge	161:aa5281ff4a02	541
AnnaBridge	161:aa5281ff4a02	542	/@} end of group CMSIS_SCB /
AnnaBridge	161:aa5281ff4a02	543
AnnaBridge	161:aa5281ff4a02	544
AnnaBridge	161:aa5281ff4a02	545	/**
AnnaBridge	161:aa5281ff4a02	546	\ingroup CMSIS_core_register
AnnaBridge	161:aa5281ff4a02	547	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge	161:aa5281ff4a02	548	\brief Type definitions for the System Timer Registers.
AnnaBridge	161:aa5281ff4a02	549	@{
AnnaBridge	161:aa5281ff4a02	550	*/
AnnaBridge	161:aa5281ff4a02	551
AnnaBridge	161:aa5281ff4a02	552	/**
AnnaBridge	161:aa5281ff4a02	553	\brief Structure type to access the System Timer (SysTick).
AnnaBridge	161:aa5281ff4a02	554	*/
AnnaBridge	161:aa5281ff4a02	555	typedef struct
AnnaBridge	161:aa5281ff4a02	556	{
AnnaBridge	161:aa5281ff4a02	557	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
AnnaBridge	161:aa5281ff4a02	558	__IOM uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
AnnaBridge	161:aa5281ff4a02	559	__IOM uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
AnnaBridge	161:aa5281ff4a02	560	__IM uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
AnnaBridge	161:aa5281ff4a02	561	} SysTick_Type;
AnnaBridge	161:aa5281ff4a02	562
AnnaBridge	161:aa5281ff4a02	563	/* SysTick Control / Status Register Definitions */
AnnaBridge	161:aa5281ff4a02	564	#define SysTick_CTRL_COUNTFLAG_Pos 16U /!< SysTick CTRL: COUNTFLAG Position /
AnnaBridge	161:aa5281ff4a02	565	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
AnnaBridge	161:aa5281ff4a02	566
AnnaBridge	161:aa5281ff4a02	567	#define SysTick_CTRL_CLKSOURCE_Pos 2U /!< SysTick CTRL: CLKSOURCE Position /
AnnaBridge	161:aa5281ff4a02	568	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
AnnaBridge	161:aa5281ff4a02	569
AnnaBridge	161:aa5281ff4a02	570	#define SysTick_CTRL_TICKINT_Pos 1U /!< SysTick CTRL: TICKINT Position /
AnnaBridge	161:aa5281ff4a02	571	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
AnnaBridge	161:aa5281ff4a02	572
AnnaBridge	161:aa5281ff4a02	573	#define SysTick_CTRL_ENABLE_Pos 0U /!< SysTick CTRL: ENABLE Position /
AnnaBridge	161:aa5281ff4a02	574	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
AnnaBridge	161:aa5281ff4a02	575
AnnaBridge	161:aa5281ff4a02	576	/* SysTick Reload Register Definitions */
AnnaBridge	161:aa5281ff4a02	577	#define SysTick_LOAD_RELOAD_Pos 0U /!< SysTick LOAD: RELOAD Position /
AnnaBridge	161:aa5281ff4a02	578	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
AnnaBridge	161:aa5281ff4a02	579
AnnaBridge	161:aa5281ff4a02	580	/* SysTick Current Register Definitions */
AnnaBridge	161:aa5281ff4a02	581	#define SysTick_VAL_CURRENT_Pos 0U /!< SysTick VAL: CURRENT Position /
AnnaBridge	161:aa5281ff4a02	582	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
AnnaBridge	161:aa5281ff4a02	583
AnnaBridge	161:aa5281ff4a02	584	/* SysTick Calibration Register Definitions */
AnnaBridge	161:aa5281ff4a02	585	#define SysTick_CALIB_NOREF_Pos 31U /!< SysTick CALIB: NOREF Position /
AnnaBridge	161:aa5281ff4a02	586	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
AnnaBridge	161:aa5281ff4a02	587
AnnaBridge	161:aa5281ff4a02	588	#define SysTick_CALIB_SKEW_Pos 30U /!< SysTick CALIB: SKEW Position /
AnnaBridge	161:aa5281ff4a02	589	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
AnnaBridge	161:aa5281ff4a02	590
AnnaBridge	161:aa5281ff4a02	591	#define SysTick_CALIB_TENMS_Pos 0U /!< SysTick CALIB: TENMS Position /
AnnaBridge	161:aa5281ff4a02	592	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
AnnaBridge	161:aa5281ff4a02	593
AnnaBridge	161:aa5281ff4a02	594	/@} end of group CMSIS_SysTick /
AnnaBridge	161:aa5281ff4a02	595
AnnaBridge	161:aa5281ff4a02	596
AnnaBridge	161:aa5281ff4a02	597	/**
AnnaBridge	161:aa5281ff4a02	598	\ingroup CMSIS_core_register
AnnaBridge	161:aa5281ff4a02	599	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
AnnaBridge	161:aa5281ff4a02	600	\brief Type definitions for the Data Watchpoint and Trace (DWT)
AnnaBridge	161:aa5281ff4a02	601	@{
AnnaBridge	161:aa5281ff4a02	602	*/
AnnaBridge	161:aa5281ff4a02	603
AnnaBridge	161:aa5281ff4a02	604	/**
AnnaBridge	161:aa5281ff4a02	605	\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
AnnaBridge	161:aa5281ff4a02	606	*/
AnnaBridge	161:aa5281ff4a02	607	typedef struct
AnnaBridge	161:aa5281ff4a02	608	{
AnnaBridge	161:aa5281ff4a02	609	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
AnnaBridge	161:aa5281ff4a02	610	uint32_t RESERVED0[6U];
AnnaBridge	161:aa5281ff4a02	611	__IM uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
AnnaBridge	161:aa5281ff4a02	612	__IOM uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
AnnaBridge	161:aa5281ff4a02	613	uint32_t RESERVED1[1U];
AnnaBridge	161:aa5281ff4a02	614	__IOM uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
AnnaBridge	161:aa5281ff4a02	615	uint32_t RESERVED2[1U];
AnnaBridge	161:aa5281ff4a02	616	__IOM uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
AnnaBridge	161:aa5281ff4a02	617	uint32_t RESERVED3[1U];
AnnaBridge	161:aa5281ff4a02	618	__IOM uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
AnnaBridge	161:aa5281ff4a02	619	uint32_t RESERVED4[1U];
AnnaBridge	161:aa5281ff4a02	620	__IOM uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
AnnaBridge	161:aa5281ff4a02	621	uint32_t RESERVED5[1U];
AnnaBridge	161:aa5281ff4a02	622	__IOM uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
AnnaBridge	161:aa5281ff4a02	623	uint32_t RESERVED6[1U];
AnnaBridge	161:aa5281ff4a02	624	__IOM uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
AnnaBridge	161:aa5281ff4a02	625	uint32_t RESERVED7[1U];
AnnaBridge	161:aa5281ff4a02	626	__IOM uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
AnnaBridge	161:aa5281ff4a02	627	uint32_t RESERVED8[1U];
AnnaBridge	161:aa5281ff4a02	628	__IOM uint32_t COMP4; /!< Offset: 0x060 (R/W) Comparator Register 4 /
AnnaBridge	161:aa5281ff4a02	629	uint32_t RESERVED9[1U];
AnnaBridge	161:aa5281ff4a02	630	__IOM uint32_t FUNCTION4; /!< Offset: 0x068 (R/W) Function Register 4 /
AnnaBridge	161:aa5281ff4a02	631	uint32_t RESERVED10[1U];
AnnaBridge	161:aa5281ff4a02	632	__IOM uint32_t COMP5; /!< Offset: 0x070 (R/W) Comparator Register 5 /
AnnaBridge	161:aa5281ff4a02	633	uint32_t RESERVED11[1U];
AnnaBridge	161:aa5281ff4a02	634	__IOM uint32_t FUNCTION5; /!< Offset: 0x078 (R/W) Function Register 5 /
AnnaBridge	161:aa5281ff4a02	635	uint32_t RESERVED12[1U];
AnnaBridge	161:aa5281ff4a02	636	__IOM uint32_t COMP6; /!< Offset: 0x080 (R/W) Comparator Register 6 /
AnnaBridge	161:aa5281ff4a02	637	uint32_t RESERVED13[1U];
AnnaBridge	161:aa5281ff4a02	638	__IOM uint32_t FUNCTION6; /!< Offset: 0x088 (R/W) Function Register 6 /
AnnaBridge	161:aa5281ff4a02	639	uint32_t RESERVED14[1U];
AnnaBridge	161:aa5281ff4a02	640	__IOM uint32_t COMP7; /!< Offset: 0x090 (R/W) Comparator Register 7 /
AnnaBridge	161:aa5281ff4a02	641	uint32_t RESERVED15[1U];
AnnaBridge	161:aa5281ff4a02	642	__IOM uint32_t FUNCTION7; /!< Offset: 0x098 (R/W) Function Register 7 /
AnnaBridge	161:aa5281ff4a02	643	uint32_t RESERVED16[1U];
AnnaBridge	161:aa5281ff4a02	644	__IOM uint32_t COMP8; /!< Offset: 0x0A0 (R/W) Comparator Register 8 /
AnnaBridge	161:aa5281ff4a02	645	uint32_t RESERVED17[1U];
AnnaBridge	161:aa5281ff4a02	646	__IOM uint32_t FUNCTION8; /!< Offset: 0x0A8 (R/W) Function Register 8 /
AnnaBridge	161:aa5281ff4a02	647	uint32_t RESERVED18[1U];
AnnaBridge	161:aa5281ff4a02	648	__IOM uint32_t COMP9; /!< Offset: 0x0B0 (R/W) Comparator Register 9 /
AnnaBridge	161:aa5281ff4a02	649	uint32_t RESERVED19[1U];
AnnaBridge	161:aa5281ff4a02	650	__IOM uint32_t FUNCTION9; /!< Offset: 0x0B8 (R/W) Function Register 9 /
AnnaBridge	161:aa5281ff4a02	651	uint32_t RESERVED20[1U];
AnnaBridge	161:aa5281ff4a02	652	__IOM uint32_t COMP10; /!< Offset: 0x0C0 (R/W) Comparator Register 10 /
AnnaBridge	161:aa5281ff4a02	653	uint32_t RESERVED21[1U];
AnnaBridge	161:aa5281ff4a02	654	__IOM uint32_t FUNCTION10; /!< Offset: 0x0C8 (R/W) Function Register 10 /
AnnaBridge	161:aa5281ff4a02	655	uint32_t RESERVED22[1U];
AnnaBridge	161:aa5281ff4a02	656	__IOM uint32_t COMP11; /!< Offset: 0x0D0 (R/W) Comparator Register 11 /
AnnaBridge	161:aa5281ff4a02	657	uint32_t RESERVED23[1U];
AnnaBridge	161:aa5281ff4a02	658	__IOM uint32_t FUNCTION11; /!< Offset: 0x0D8 (R/W) Function Register 11 /
AnnaBridge	161:aa5281ff4a02	659	uint32_t RESERVED24[1U];
AnnaBridge	161:aa5281ff4a02	660	__IOM uint32_t COMP12; /!< Offset: 0x0E0 (R/W) Comparator Register 12 /
AnnaBridge	161:aa5281ff4a02	661	uint32_t RESERVED25[1U];
AnnaBridge	161:aa5281ff4a02	662	__IOM uint32_t FUNCTION12; /!< Offset: 0x0E8 (R/W) Function Register 12 /
AnnaBridge	161:aa5281ff4a02	663	uint32_t RESERVED26[1U];
AnnaBridge	161:aa5281ff4a02	664	__IOM uint32_t COMP13; /!< Offset: 0x0F0 (R/W) Comparator Register 13 /
AnnaBridge	161:aa5281ff4a02	665	uint32_t RESERVED27[1U];
AnnaBridge	161:aa5281ff4a02	666	__IOM uint32_t FUNCTION13; /!< Offset: 0x0F8 (R/W) Function Register 13 /
AnnaBridge	161:aa5281ff4a02	667	uint32_t RESERVED28[1U];
AnnaBridge	161:aa5281ff4a02	668	__IOM uint32_t COMP14; /!< Offset: 0x100 (R/W) Comparator Register 14 /
AnnaBridge	161:aa5281ff4a02	669	uint32_t RESERVED29[1U];
AnnaBridge	161:aa5281ff4a02	670	__IOM uint32_t FUNCTION14; /!< Offset: 0x108 (R/W) Function Register 14 /
AnnaBridge	161:aa5281ff4a02	671	uint32_t RESERVED30[1U];
AnnaBridge	161:aa5281ff4a02	672	__IOM uint32_t COMP15; /!< Offset: 0x110 (R/W) Comparator Register 15 /
AnnaBridge	161:aa5281ff4a02	673	uint32_t RESERVED31[1U];
AnnaBridge	161:aa5281ff4a02	674	__IOM uint32_t FUNCTION15; /!< Offset: 0x118 (R/W) Function Register 15 /
AnnaBridge	161:aa5281ff4a02	675	} DWT_Type;
AnnaBridge	161:aa5281ff4a02	676
AnnaBridge	161:aa5281ff4a02	677	/* DWT Control Register Definitions */
AnnaBridge	161:aa5281ff4a02	678	#define DWT_CTRL_NUMCOMP_Pos 28U /!< DWT CTRL: NUMCOMP Position /
AnnaBridge	161:aa5281ff4a02	679	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
AnnaBridge	161:aa5281ff4a02	680
AnnaBridge	161:aa5281ff4a02	681	#define DWT_CTRL_NOTRCPKT_Pos 27U /!< DWT CTRL: NOTRCPKT Position /
AnnaBridge	161:aa5281ff4a02	682	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
AnnaBridge	161:aa5281ff4a02	683
AnnaBridge	161:aa5281ff4a02	684	#define DWT_CTRL_NOEXTTRIG_Pos 26U /!< DWT CTRL: NOEXTTRIG Position /
AnnaBridge	161:aa5281ff4a02	685	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
AnnaBridge	161:aa5281ff4a02	686
AnnaBridge	161:aa5281ff4a02	687	#define DWT_CTRL_NOCYCCNT_Pos 25U /!< DWT CTRL: NOCYCCNT Position /
AnnaBridge	161:aa5281ff4a02	688	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
AnnaBridge	161:aa5281ff4a02	689
AnnaBridge	161:aa5281ff4a02	690	#define DWT_CTRL_NOPRFCNT_Pos 24U /!< DWT CTRL: NOPRFCNT Position /
AnnaBridge	161:aa5281ff4a02	691	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
AnnaBridge	161:aa5281ff4a02	692
AnnaBridge	161:aa5281ff4a02	693	/* DWT Comparator Function Register Definitions */
AnnaBridge	161:aa5281ff4a02	694	#define DWT_FUNCTION_ID_Pos 27U /!< DWT FUNCTION: ID Position /
AnnaBridge	161:aa5281ff4a02	695	#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /!< DWT FUNCTION: ID Mask /
AnnaBridge	161:aa5281ff4a02	696
AnnaBridge	161:aa5281ff4a02	697	#define DWT_FUNCTION_MATCHED_Pos 24U /!< DWT FUNCTION: MATCHED Position /
AnnaBridge	161:aa5281ff4a02	698	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
AnnaBridge	161:aa5281ff4a02	699
AnnaBridge	161:aa5281ff4a02	700	#define DWT_FUNCTION_DATAVSIZE_Pos 10U /!< DWT FUNCTION: DATAVSIZE Position /
AnnaBridge	161:aa5281ff4a02	701	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
AnnaBridge	161:aa5281ff4a02	702
AnnaBridge	161:aa5281ff4a02	703	#define DWT_FUNCTION_ACTION_Pos 4U /!< DWT FUNCTION: ACTION Position /
AnnaBridge	161:aa5281ff4a02	704	#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /!< DWT FUNCTION: ACTION Mask /
AnnaBridge	161:aa5281ff4a02	705
AnnaBridge	161:aa5281ff4a02	706	#define DWT_FUNCTION_MATCH_Pos 0U /!< DWT FUNCTION: MATCH Position /
AnnaBridge	161:aa5281ff4a02	707	#define DWT_FUNCTION_MATCH_Msk (0xFUL /<< DWT_FUNCTION_MATCH_Pos/) /!< DWT FUNCTION: MATCH Mask /
AnnaBridge	161:aa5281ff4a02	708
AnnaBridge	161:aa5281ff4a02	709	/@}/ /* end of group CMSIS_DWT */
AnnaBridge	161:aa5281ff4a02	710
AnnaBridge	161:aa5281ff4a02	711
AnnaBridge	161:aa5281ff4a02	712	/**
AnnaBridge	161:aa5281ff4a02	713	\ingroup CMSIS_core_register
AnnaBridge	161:aa5281ff4a02	714	\defgroup CMSIS_TPI Trace Port Interface (TPI)
AnnaBridge	161:aa5281ff4a02	715	\brief Type definitions for the Trace Port Interface (TPI)
AnnaBridge	161:aa5281ff4a02	716	@{
AnnaBridge	161:aa5281ff4a02	717	*/
AnnaBridge	161:aa5281ff4a02	718
AnnaBridge	161:aa5281ff4a02	719	/**
AnnaBridge	161:aa5281ff4a02	720	\brief Structure type to access the Trace Port Interface Register (TPI).
AnnaBridge	161:aa5281ff4a02	721	*/
AnnaBridge	161:aa5281ff4a02	722	typedef struct
AnnaBridge	161:aa5281ff4a02	723	{
AnnaBridge	161:aa5281ff4a02	724	__IOM uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
AnnaBridge	161:aa5281ff4a02	725	__IOM uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
AnnaBridge	161:aa5281ff4a02	726	uint32_t RESERVED0[2U];
AnnaBridge	161:aa5281ff4a02	727	__IOM uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
AnnaBridge	161:aa5281ff4a02	728	uint32_t RESERVED1[55U];
AnnaBridge	161:aa5281ff4a02	729	__IOM uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
AnnaBridge	161:aa5281ff4a02	730	uint32_t RESERVED2[131U];
AnnaBridge	161:aa5281ff4a02	731	__IM uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
AnnaBridge	161:aa5281ff4a02	732	__IOM uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
AnnaBridge	161:aa5281ff4a02	733	__IM uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
AnnaBridge	161:aa5281ff4a02	734	uint32_t RESERVED3[759U];
AnnaBridge	161:aa5281ff4a02	735	__IM uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
AnnaBridge	161:aa5281ff4a02	736	__IM uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
AnnaBridge	161:aa5281ff4a02	737	__IM uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
AnnaBridge	161:aa5281ff4a02	738	uint32_t RESERVED4[1U];
AnnaBridge	161:aa5281ff4a02	739	__IM uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
AnnaBridge	161:aa5281ff4a02	740	__IM uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
AnnaBridge	161:aa5281ff4a02	741	__IOM uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
AnnaBridge	161:aa5281ff4a02	742	uint32_t RESERVED5[39U];
AnnaBridge	161:aa5281ff4a02	743	__IOM uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
AnnaBridge	161:aa5281ff4a02	744	__IOM uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
AnnaBridge	161:aa5281ff4a02	745	uint32_t RESERVED7[8U];
AnnaBridge	161:aa5281ff4a02	746	__IM uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
AnnaBridge	161:aa5281ff4a02	747	__IM uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
AnnaBridge	161:aa5281ff4a02	748	} TPI_Type;
AnnaBridge	161:aa5281ff4a02	749
AnnaBridge	161:aa5281ff4a02	750	/* TPI Asynchronous Clock Prescaler Register Definitions */
Anna Bridge	169:a7c7b631e539	751	#define TPI_ACPR_PRESCALER_Pos 0U /!< @Deprecated TPI ACPR: PRESCALER Position /
Anna Bridge	169:a7c7b631e539	752	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< @Deprecated TPI ACPR: PRESCALER Mask /
Anna Bridge	169:a7c7b631e539	753
Anna Bridge	169:a7c7b631e539	754	#define TPI_ACPR_SWOSCALER_Pos 0U /!< TPI ACPR: SWOSCALER Position /
Anna Bridge	169:a7c7b631e539	755	#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /<< TPI_ACPR_SWOSCALER_Pos/) /!< TPI ACPR: SWOSCALER Mask /
AnnaBridge	161:aa5281ff4a02	756
AnnaBridge	161:aa5281ff4a02	757	/* TPI Selected Pin Protocol Register Definitions */
AnnaBridge	161:aa5281ff4a02	758	#define TPI_SPPR_TXMODE_Pos 0U /!< TPI SPPR: TXMODE Position /
AnnaBridge	161:aa5281ff4a02	759	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
AnnaBridge	161:aa5281ff4a02	760
AnnaBridge	161:aa5281ff4a02	761	/* TPI Formatter and Flush Status Register Definitions */
AnnaBridge	161:aa5281ff4a02	762	#define TPI_FFSR_FtNonStop_Pos 3U /!< TPI FFSR: FtNonStop Position /
AnnaBridge	161:aa5281ff4a02	763	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
AnnaBridge	161:aa5281ff4a02	764
AnnaBridge	161:aa5281ff4a02	765	#define TPI_FFSR_TCPresent_Pos 2U /!< TPI FFSR: TCPresent Position /
AnnaBridge	161:aa5281ff4a02	766	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
AnnaBridge	161:aa5281ff4a02	767
AnnaBridge	161:aa5281ff4a02	768	#define TPI_FFSR_FtStopped_Pos 1U /!< TPI FFSR: FtStopped Position /
AnnaBridge	161:aa5281ff4a02	769	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
AnnaBridge	161:aa5281ff4a02	770
AnnaBridge	161:aa5281ff4a02	771	#define TPI_FFSR_FlInProg_Pos 0U /!< TPI FFSR: FlInProg Position /
AnnaBridge	161:aa5281ff4a02	772	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
AnnaBridge	161:aa5281ff4a02	773
AnnaBridge	161:aa5281ff4a02	774	/* TPI Formatter and Flush Control Register Definitions */
AnnaBridge	161:aa5281ff4a02	775	#define TPI_FFCR_TrigIn_Pos 8U /!< TPI FFCR: TrigIn Position /
AnnaBridge	161:aa5281ff4a02	776	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
AnnaBridge	161:aa5281ff4a02	777
AnnaBridge	161:aa5281ff4a02	778	#define TPI_FFCR_EnFCont_Pos 1U /!< TPI FFCR: EnFCont Position /
AnnaBridge	161:aa5281ff4a02	779	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
AnnaBridge	161:aa5281ff4a02	780
AnnaBridge	161:aa5281ff4a02	781	/* TPI TRIGGER Register Definitions */
AnnaBridge	161:aa5281ff4a02	782	#define TPI_TRIGGER_TRIGGER_Pos 0U /!< TPI TRIGGER: TRIGGER Position /
AnnaBridge	161:aa5281ff4a02	783	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
AnnaBridge	161:aa5281ff4a02	784
AnnaBridge	161:aa5281ff4a02	785	/* TPI Integration ETM Data Register Definitions (FIFO0) */
AnnaBridge	161:aa5281ff4a02	786	#define TPI_FIFO0_ITM_ATVALID_Pos 29U /!< TPI FIFO0: ITM_ATVALID Position /
AnnaBridge	161:aa5281ff4a02	787	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
AnnaBridge	161:aa5281ff4a02	788
AnnaBridge	161:aa5281ff4a02	789	#define TPI_FIFO0_ITM_bytecount_Pos 27U /!< TPI FIFO0: ITM_bytecount Position /
AnnaBridge	161:aa5281ff4a02	790	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
AnnaBridge	161:aa5281ff4a02	791
AnnaBridge	161:aa5281ff4a02	792	#define TPI_FIFO0_ETM_ATVALID_Pos 26U /!< TPI FIFO0: ETM_ATVALID Position /
AnnaBridge	161:aa5281ff4a02	793	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
AnnaBridge	161:aa5281ff4a02	794
AnnaBridge	161:aa5281ff4a02	795	#define TPI_FIFO0_ETM_bytecount_Pos 24U /!< TPI FIFO0: ETM_bytecount Position /
AnnaBridge	161:aa5281ff4a02	796	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
AnnaBridge	161:aa5281ff4a02	797
AnnaBridge	161:aa5281ff4a02	798	#define TPI_FIFO0_ETM2_Pos 16U /!< TPI FIFO0: ETM2 Position /
AnnaBridge	161:aa5281ff4a02	799	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
AnnaBridge	161:aa5281ff4a02	800
AnnaBridge	161:aa5281ff4a02	801	#define TPI_FIFO0_ETM1_Pos 8U /!< TPI FIFO0: ETM1 Position /
AnnaBridge	161:aa5281ff4a02	802	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
AnnaBridge	161:aa5281ff4a02	803
AnnaBridge	161:aa5281ff4a02	804	#define TPI_FIFO0_ETM0_Pos 0U /!< TPI FIFO0: ETM0 Position /
AnnaBridge	161:aa5281ff4a02	805	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
AnnaBridge	161:aa5281ff4a02	806
AnnaBridge	161:aa5281ff4a02	807	/* TPI ITATBCTR2 Register Definitions */
AnnaBridge	161:aa5281ff4a02	808	#define TPI_ITATBCTR2_ATREADY_Pos 0U /!< TPI ITATBCTR2: ATREADY Position /
AnnaBridge	161:aa5281ff4a02	809	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
AnnaBridge	161:aa5281ff4a02	810
AnnaBridge	161:aa5281ff4a02	811	/* TPI Integration ITM Data Register Definitions (FIFO1) */
AnnaBridge	161:aa5281ff4a02	812	#define TPI_FIFO1_ITM_ATVALID_Pos 29U /!< TPI FIFO1: ITM_ATVALID Position /
AnnaBridge	161:aa5281ff4a02	813	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
AnnaBridge	161:aa5281ff4a02	814
AnnaBridge	161:aa5281ff4a02	815	#define TPI_FIFO1_ITM_bytecount_Pos 27U /!< TPI FIFO1: ITM_bytecount Position /
AnnaBridge	161:aa5281ff4a02	816	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
AnnaBridge	161:aa5281ff4a02	817
AnnaBridge	161:aa5281ff4a02	818	#define TPI_FIFO1_ETM_ATVALID_Pos 26U /!< TPI FIFO1: ETM_ATVALID Position /
AnnaBridge	161:aa5281ff4a02	819	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
AnnaBridge	161:aa5281ff4a02	820
AnnaBridge	161:aa5281ff4a02	821	#define TPI_FIFO1_ETM_bytecount_Pos 24U /!< TPI FIFO1: ETM_bytecount Position /
AnnaBridge	161:aa5281ff4a02	822	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
AnnaBridge	161:aa5281ff4a02	823
AnnaBridge	161:aa5281ff4a02	824	#define TPI_FIFO1_ITM2_Pos 16U /!< TPI FIFO1: ITM2 Position /
AnnaBridge	161:aa5281ff4a02	825	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
AnnaBridge	161:aa5281ff4a02	826
AnnaBridge	161:aa5281ff4a02	827	#define TPI_FIFO1_ITM1_Pos 8U /!< TPI FIFO1: ITM1 Position /
AnnaBridge	161:aa5281ff4a02	828	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
AnnaBridge	161:aa5281ff4a02	829
AnnaBridge	161:aa5281ff4a02	830	#define TPI_FIFO1_ITM0_Pos 0U /!< TPI FIFO1: ITM0 Position /
AnnaBridge	161:aa5281ff4a02	831	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
AnnaBridge	161:aa5281ff4a02	832
AnnaBridge	161:aa5281ff4a02	833	/* TPI ITATBCTR0 Register Definitions */
AnnaBridge	161:aa5281ff4a02	834	#define TPI_ITATBCTR0_ATREADY_Pos 0U /!< TPI ITATBCTR0: ATREADY Position /
AnnaBridge	161:aa5281ff4a02	835	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
AnnaBridge	161:aa5281ff4a02	836
AnnaBridge	161:aa5281ff4a02	837	/* TPI Integration Mode Control Register Definitions */
AnnaBridge	161:aa5281ff4a02	838	#define TPI_ITCTRL_Mode_Pos 0U /!< TPI ITCTRL: Mode Position /
AnnaBridge	161:aa5281ff4a02	839	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
AnnaBridge	161:aa5281ff4a02	840
AnnaBridge	161:aa5281ff4a02	841	/* TPI DEVID Register Definitions */
AnnaBridge	161:aa5281ff4a02	842	#define TPI_DEVID_NRZVALID_Pos 11U /!< TPI DEVID: NRZVALID Position /
AnnaBridge	161:aa5281ff4a02	843	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
AnnaBridge	161:aa5281ff4a02	844
AnnaBridge	161:aa5281ff4a02	845	#define TPI_DEVID_MANCVALID_Pos 10U /!< TPI DEVID: MANCVALID Position /
AnnaBridge	161:aa5281ff4a02	846	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
AnnaBridge	161:aa5281ff4a02	847
AnnaBridge	161:aa5281ff4a02	848	#define TPI_DEVID_PTINVALID_Pos 9U /!< TPI DEVID: PTINVALID Position /
AnnaBridge	161:aa5281ff4a02	849	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
AnnaBridge	161:aa5281ff4a02	850
AnnaBridge	161:aa5281ff4a02	851	#define TPI_DEVID_MinBufSz_Pos 6U /!< TPI DEVID: MinBufSz Position /
AnnaBridge	161:aa5281ff4a02	852	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
AnnaBridge	161:aa5281ff4a02	853
AnnaBridge	161:aa5281ff4a02	854	#define TPI_DEVID_AsynClkIn_Pos 5U /!< TPI DEVID: AsynClkIn Position /
AnnaBridge	161:aa5281ff4a02	855	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
AnnaBridge	161:aa5281ff4a02	856
AnnaBridge	161:aa5281ff4a02	857	#define TPI_DEVID_NrTraceInput_Pos 0U /!< TPI DEVID: NrTraceInput Position /
AnnaBridge	161:aa5281ff4a02	858	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
AnnaBridge	161:aa5281ff4a02	859
AnnaBridge	161:aa5281ff4a02	860	/* TPI DEVTYPE Register Definitions */
AnnaBridge	161:aa5281ff4a02	861	#define TPI_DEVTYPE_MajorType_Pos 4U /!< TPI DEVTYPE: MajorType Position /
AnnaBridge	161:aa5281ff4a02	862	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
AnnaBridge	161:aa5281ff4a02	863
AnnaBridge	161:aa5281ff4a02	864	#define TPI_DEVTYPE_SubType_Pos 0U /!< TPI DEVTYPE: SubType Position /
AnnaBridge	161:aa5281ff4a02	865	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
AnnaBridge	161:aa5281ff4a02	866
AnnaBridge	161:aa5281ff4a02	867	/@}/ /* end of group CMSIS_TPI */
AnnaBridge	161:aa5281ff4a02	868
AnnaBridge	161:aa5281ff4a02	869
AnnaBridge	161:aa5281ff4a02	870	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge	161:aa5281ff4a02	871	/**
AnnaBridge	161:aa5281ff4a02	872	\ingroup CMSIS_core_register
AnnaBridge	161:aa5281ff4a02	873	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
AnnaBridge	161:aa5281ff4a02	874	\brief Type definitions for the Memory Protection Unit (MPU)
AnnaBridge	161:aa5281ff4a02	875	@{
AnnaBridge	161:aa5281ff4a02	876	*/
AnnaBridge	161:aa5281ff4a02	877
AnnaBridge	161:aa5281ff4a02	878	/**
AnnaBridge	161:aa5281ff4a02	879	\brief Structure type to access the Memory Protection Unit (MPU).
AnnaBridge	161:aa5281ff4a02	880	*/
AnnaBridge	161:aa5281ff4a02	881	typedef struct
AnnaBridge	161:aa5281ff4a02	882	{
AnnaBridge	161:aa5281ff4a02	883	__IM uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
AnnaBridge	161:aa5281ff4a02	884	__IOM uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
AnnaBridge	161:aa5281ff4a02	885	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region Number Register /
AnnaBridge	161:aa5281ff4a02	886	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
AnnaBridge	161:aa5281ff4a02	887	__IOM uint32_t RLAR; /!< Offset: 0x010 (R/W) MPU Region Limit Address Register /
AnnaBridge	161:aa5281ff4a02	888	uint32_t RESERVED0[7U];
AnnaBridge	161:aa5281ff4a02	889	union {
AnnaBridge	161:aa5281ff4a02	890	__IOM uint32_t MAIR[2];
AnnaBridge	161:aa5281ff4a02	891	struct {
AnnaBridge	161:aa5281ff4a02	892	__IOM uint32_t MAIR0; /!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 /
AnnaBridge	161:aa5281ff4a02	893	__IOM uint32_t MAIR1; /!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 /
AnnaBridge	161:aa5281ff4a02	894	};
AnnaBridge	161:aa5281ff4a02	895	};
AnnaBridge	161:aa5281ff4a02	896	} MPU_Type;
AnnaBridge	161:aa5281ff4a02	897
AnnaBridge	161:aa5281ff4a02	898	#define MPU_TYPE_RALIASES 1U
AnnaBridge	161:aa5281ff4a02	899
AnnaBridge	161:aa5281ff4a02	900	/* MPU Type Register Definitions */
AnnaBridge	161:aa5281ff4a02	901	#define MPU_TYPE_IREGION_Pos 16U /!< MPU TYPE: IREGION Position /
AnnaBridge	161:aa5281ff4a02	902	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
AnnaBridge	161:aa5281ff4a02	903
AnnaBridge	161:aa5281ff4a02	904	#define MPU_TYPE_DREGION_Pos 8U /!< MPU TYPE: DREGION Position /
AnnaBridge	161:aa5281ff4a02	905	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
AnnaBridge	161:aa5281ff4a02	906
AnnaBridge	161:aa5281ff4a02	907	#define MPU_TYPE_SEPARATE_Pos 0U /!< MPU TYPE: SEPARATE Position /
AnnaBridge	161:aa5281ff4a02	908	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
AnnaBridge	161:aa5281ff4a02	909
AnnaBridge	161:aa5281ff4a02	910	/* MPU Control Register Definitions */
AnnaBridge	161:aa5281ff4a02	911	#define MPU_CTRL_PRIVDEFENA_Pos 2U /!< MPU CTRL: PRIVDEFENA Position /
AnnaBridge	161:aa5281ff4a02	912	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
AnnaBridge	161:aa5281ff4a02	913
AnnaBridge	161:aa5281ff4a02	914	#define MPU_CTRL_HFNMIENA_Pos 1U /!< MPU CTRL: HFNMIENA Position /
AnnaBridge	161:aa5281ff4a02	915	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
AnnaBridge	161:aa5281ff4a02	916
AnnaBridge	161:aa5281ff4a02	917	#define MPU_CTRL_ENABLE_Pos 0U /!< MPU CTRL: ENABLE Position /
AnnaBridge	161:aa5281ff4a02	918	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
AnnaBridge	161:aa5281ff4a02	919
AnnaBridge	161:aa5281ff4a02	920	/* MPU Region Number Register Definitions */
AnnaBridge	161:aa5281ff4a02	921	#define MPU_RNR_REGION_Pos 0U /!< MPU RNR: REGION Position /
AnnaBridge	161:aa5281ff4a02	922	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
AnnaBridge	161:aa5281ff4a02	923
AnnaBridge	161:aa5281ff4a02	924	/* MPU Region Base Address Register Definitions */
AnnaBridge	161:aa5281ff4a02	925	#define MPU_RBAR_BASE_Pos 5U /!< MPU RBAR: BASE Position /
AnnaBridge	161:aa5281ff4a02	926	#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /!< MPU RBAR: BASE Mask /
AnnaBridge	161:aa5281ff4a02	927
AnnaBridge	161:aa5281ff4a02	928	#define MPU_RBAR_SH_Pos 3U /!< MPU RBAR: SH Position /
AnnaBridge	161:aa5281ff4a02	929	#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /!< MPU RBAR: SH Mask /
AnnaBridge	161:aa5281ff4a02	930
AnnaBridge	161:aa5281ff4a02	931	#define MPU_RBAR_AP_Pos 1U /!< MPU RBAR: AP Position /
AnnaBridge	161:aa5281ff4a02	932	#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /!< MPU RBAR: AP Mask /
AnnaBridge	161:aa5281ff4a02	933
AnnaBridge	161:aa5281ff4a02	934	#define MPU_RBAR_XN_Pos 0U /!< MPU RBAR: XN Position /
AnnaBridge	161:aa5281ff4a02	935	#define MPU_RBAR_XN_Msk (01UL /<< MPU_RBAR_XN_Pos/) /!< MPU RBAR: XN Mask /
AnnaBridge	161:aa5281ff4a02	936
AnnaBridge	161:aa5281ff4a02	937	/* MPU Region Limit Address Register Definitions */
AnnaBridge	161:aa5281ff4a02	938	#define MPU_RLAR_LIMIT_Pos 5U /!< MPU RLAR: LIMIT Position /
AnnaBridge	161:aa5281ff4a02	939	#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /!< MPU RLAR: LIMIT Mask /
AnnaBridge	161:aa5281ff4a02	940
AnnaBridge	161:aa5281ff4a02	941	#define MPU_RLAR_AttrIndx_Pos 1U /!< MPU RLAR: AttrIndx Position /
AnnaBridge	161:aa5281ff4a02	942	#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /!< MPU RLAR: AttrIndx Mask /
AnnaBridge	161:aa5281ff4a02	943
AnnaBridge	161:aa5281ff4a02	944	#define MPU_RLAR_EN_Pos 0U /!< MPU RLAR: EN Position /
AnnaBridge	161:aa5281ff4a02	945	#define MPU_RLAR_EN_Msk (1UL /<< MPU_RLAR_EN_Pos/) /!< MPU RLAR: EN Mask /
AnnaBridge	161:aa5281ff4a02	946
AnnaBridge	161:aa5281ff4a02	947	/* MPU Memory Attribute Indirection Register 0 Definitions */
AnnaBridge	161:aa5281ff4a02	948	#define MPU_MAIR0_Attr3_Pos 24U /!< MPU MAIR0: Attr3 Position /
AnnaBridge	161:aa5281ff4a02	949	#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /!< MPU MAIR0: Attr3 Mask /
AnnaBridge	161:aa5281ff4a02	950
AnnaBridge	161:aa5281ff4a02	951	#define MPU_MAIR0_Attr2_Pos 16U /!< MPU MAIR0: Attr2 Position /
AnnaBridge	161:aa5281ff4a02	952	#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /!< MPU MAIR0: Attr2 Mask /
AnnaBridge	161:aa5281ff4a02	953
AnnaBridge	161:aa5281ff4a02	954	#define MPU_MAIR0_Attr1_Pos 8U /!< MPU MAIR0: Attr1 Position /
AnnaBridge	161:aa5281ff4a02	955	#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /!< MPU MAIR0: Attr1 Mask /
AnnaBridge	161:aa5281ff4a02	956
AnnaBridge	161:aa5281ff4a02	957	#define MPU_MAIR0_Attr0_Pos 0U /!< MPU MAIR0: Attr0 Position /
AnnaBridge	161:aa5281ff4a02	958	#define MPU_MAIR0_Attr0_Msk (0xFFUL /<< MPU_MAIR0_Attr0_Pos/) /!< MPU MAIR0: Attr0 Mask /
AnnaBridge	161:aa5281ff4a02	959
AnnaBridge	161:aa5281ff4a02	960	/* MPU Memory Attribute Indirection Register 1 Definitions */
AnnaBridge	161:aa5281ff4a02	961	#define MPU_MAIR1_Attr7_Pos 24U /!< MPU MAIR1: Attr7 Position /
AnnaBridge	161:aa5281ff4a02	962	#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /!< MPU MAIR1: Attr7 Mask /
AnnaBridge	161:aa5281ff4a02	963
AnnaBridge	161:aa5281ff4a02	964	#define MPU_MAIR1_Attr6_Pos 16U /!< MPU MAIR1: Attr6 Position /
AnnaBridge	161:aa5281ff4a02	965	#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /!< MPU MAIR1: Attr6 Mask /
AnnaBridge	161:aa5281ff4a02	966
AnnaBridge	161:aa5281ff4a02	967	#define MPU_MAIR1_Attr5_Pos 8U /!< MPU MAIR1: Attr5 Position /
AnnaBridge	161:aa5281ff4a02	968	#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /!< MPU MAIR1: Attr5 Mask /
AnnaBridge	161:aa5281ff4a02	969
AnnaBridge	161:aa5281ff4a02	970	#define MPU_MAIR1_Attr4_Pos 0U /!< MPU MAIR1: Attr4 Position /
AnnaBridge	161:aa5281ff4a02	971	#define MPU_MAIR1_Attr4_Msk (0xFFUL /<< MPU_MAIR1_Attr4_Pos/) /!< MPU MAIR1: Attr4 Mask /
AnnaBridge	161:aa5281ff4a02	972
AnnaBridge	161:aa5281ff4a02	973	/@} end of group CMSIS_MPU /
AnnaBridge	161:aa5281ff4a02	974	#endif
AnnaBridge	161:aa5281ff4a02	975
AnnaBridge	161:aa5281ff4a02	976
AnnaBridge	161:aa5281ff4a02	977	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	161:aa5281ff4a02	978	/**
AnnaBridge	161:aa5281ff4a02	979	\ingroup CMSIS_core_register
AnnaBridge	161:aa5281ff4a02	980	\defgroup CMSIS_SAU Security Attribution Unit (SAU)
AnnaBridge	161:aa5281ff4a02	981	\brief Type definitions for the Security Attribution Unit (SAU)
AnnaBridge	161:aa5281ff4a02	982	@{
AnnaBridge	161:aa5281ff4a02	983	*/
AnnaBridge	161:aa5281ff4a02	984
AnnaBridge	161:aa5281ff4a02	985	/**
AnnaBridge	161:aa5281ff4a02	986	\brief Structure type to access the Security Attribution Unit (SAU).
AnnaBridge	161:aa5281ff4a02	987	*/
AnnaBridge	161:aa5281ff4a02	988	typedef struct
AnnaBridge	161:aa5281ff4a02	989	{
AnnaBridge	161:aa5281ff4a02	990	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SAU Control Register /
AnnaBridge	161:aa5281ff4a02	991	__IM uint32_t TYPE; /!< Offset: 0x004 (R/ ) SAU Type Register /
AnnaBridge	161:aa5281ff4a02	992	#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
AnnaBridge	161:aa5281ff4a02	993	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) SAU Region Number Register /
AnnaBridge	161:aa5281ff4a02	994	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) SAU Region Base Address Register /
AnnaBridge	161:aa5281ff4a02	995	__IOM uint32_t RLAR; /!< Offset: 0x010 (R/W) SAU Region Limit Address Register /
AnnaBridge	161:aa5281ff4a02	996	#endif
AnnaBridge	161:aa5281ff4a02	997	} SAU_Type;
AnnaBridge	161:aa5281ff4a02	998
AnnaBridge	161:aa5281ff4a02	999	/* SAU Control Register Definitions */
AnnaBridge	161:aa5281ff4a02	1000	#define SAU_CTRL_ALLNS_Pos 1U /!< SAU CTRL: ALLNS Position /
AnnaBridge	161:aa5281ff4a02	1001	#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /!< SAU CTRL: ALLNS Mask /
AnnaBridge	161:aa5281ff4a02	1002
AnnaBridge	161:aa5281ff4a02	1003	#define SAU_CTRL_ENABLE_Pos 0U /!< SAU CTRL: ENABLE Position /
AnnaBridge	161:aa5281ff4a02	1004	#define SAU_CTRL_ENABLE_Msk (1UL /<< SAU_CTRL_ENABLE_Pos/) /!< SAU CTRL: ENABLE Mask /
AnnaBridge	161:aa5281ff4a02	1005
AnnaBridge	161:aa5281ff4a02	1006	/* SAU Type Register Definitions */
AnnaBridge	161:aa5281ff4a02	1007	#define SAU_TYPE_SREGION_Pos 0U /!< SAU TYPE: SREGION Position /
AnnaBridge	161:aa5281ff4a02	1008	#define SAU_TYPE_SREGION_Msk (0xFFUL /<< SAU_TYPE_SREGION_Pos/) /!< SAU TYPE: SREGION Mask /
AnnaBridge	161:aa5281ff4a02	1009
AnnaBridge	161:aa5281ff4a02	1010	#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
AnnaBridge	161:aa5281ff4a02	1011	/* SAU Region Number Register Definitions */
AnnaBridge	161:aa5281ff4a02	1012	#define SAU_RNR_REGION_Pos 0U /!< SAU RNR: REGION Position /
AnnaBridge	161:aa5281ff4a02	1013	#define SAU_RNR_REGION_Msk (0xFFUL /<< SAU_RNR_REGION_Pos/) /!< SAU RNR: REGION Mask /
AnnaBridge	161:aa5281ff4a02	1014
AnnaBridge	161:aa5281ff4a02	1015	/* SAU Region Base Address Register Definitions */
AnnaBridge	161:aa5281ff4a02	1016	#define SAU_RBAR_BADDR_Pos 5U /!< SAU RBAR: BADDR Position /
AnnaBridge	161:aa5281ff4a02	1017	#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /!< SAU RBAR: BADDR Mask /
AnnaBridge	161:aa5281ff4a02	1018
AnnaBridge	161:aa5281ff4a02	1019	/* SAU Region Limit Address Register Definitions */
AnnaBridge	161:aa5281ff4a02	1020	#define SAU_RLAR_LADDR_Pos 5U /!< SAU RLAR: LADDR Position /
AnnaBridge	161:aa5281ff4a02	1021	#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /!< SAU RLAR: LADDR Mask /
AnnaBridge	161:aa5281ff4a02	1022
AnnaBridge	161:aa5281ff4a02	1023	#define SAU_RLAR_NSC_Pos 1U /!< SAU RLAR: NSC Position /
AnnaBridge	161:aa5281ff4a02	1024	#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /!< SAU RLAR: NSC Mask /
AnnaBridge	161:aa5281ff4a02	1025
AnnaBridge	161:aa5281ff4a02	1026	#define SAU_RLAR_ENABLE_Pos 0U /!< SAU RLAR: ENABLE Position /
AnnaBridge	161:aa5281ff4a02	1027	#define SAU_RLAR_ENABLE_Msk (1UL /<< SAU_RLAR_ENABLE_Pos/) /!< SAU RLAR: ENABLE Mask /
AnnaBridge	161:aa5281ff4a02	1028
AnnaBridge	161:aa5281ff4a02	1029	#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
AnnaBridge	161:aa5281ff4a02	1030
AnnaBridge	161:aa5281ff4a02	1031	/@} end of group CMSIS_SAU /
AnnaBridge	161:aa5281ff4a02	1032	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge	161:aa5281ff4a02	1033
AnnaBridge	161:aa5281ff4a02	1034
AnnaBridge	161:aa5281ff4a02	1035	/**
AnnaBridge	161:aa5281ff4a02	1036	\ingroup CMSIS_core_register
AnnaBridge	161:aa5281ff4a02	1037	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge	161:aa5281ff4a02	1038	\brief Type definitions for the Core Debug Registers
AnnaBridge	161:aa5281ff4a02	1039	@{
AnnaBridge	161:aa5281ff4a02	1040	*/
AnnaBridge	161:aa5281ff4a02	1041
AnnaBridge	161:aa5281ff4a02	1042	/**
AnnaBridge	161:aa5281ff4a02	1043	\brief Structure type to access the Core Debug Register (CoreDebug).
AnnaBridge	161:aa5281ff4a02	1044	*/
AnnaBridge	161:aa5281ff4a02	1045	typedef struct
AnnaBridge	161:aa5281ff4a02	1046	{
AnnaBridge	161:aa5281ff4a02	1047	__IOM uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
AnnaBridge	161:aa5281ff4a02	1048	__OM uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
AnnaBridge	161:aa5281ff4a02	1049	__IOM uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
AnnaBridge	161:aa5281ff4a02	1050	__IOM uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
AnnaBridge	161:aa5281ff4a02	1051	uint32_t RESERVED4[1U];
AnnaBridge	161:aa5281ff4a02	1052	__IOM uint32_t DAUTHCTRL; /!< Offset: 0x014 (R/W) Debug Authentication Control Register /
AnnaBridge	161:aa5281ff4a02	1053	__IOM uint32_t DSCSR; /!< Offset: 0x018 (R/W) Debug Security Control and Status Register /
AnnaBridge	161:aa5281ff4a02	1054	} CoreDebug_Type;
AnnaBridge	161:aa5281ff4a02	1055
AnnaBridge	161:aa5281ff4a02	1056	/* Debug Halting Control and Status Register Definitions */
AnnaBridge	161:aa5281ff4a02	1057	#define CoreDebug_DHCSR_DBGKEY_Pos 16U /!< CoreDebug DHCSR: DBGKEY Position /
AnnaBridge	161:aa5281ff4a02	1058	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
AnnaBridge	161:aa5281ff4a02	1059
AnnaBridge	161:aa5281ff4a02	1060	#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /!< CoreDebug DHCSR: S_RESTART_ST Position /
AnnaBridge	161:aa5281ff4a02	1061	#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /!< CoreDebug DHCSR: S_RESTART_ST Mask /
AnnaBridge	161:aa5281ff4a02	1062
AnnaBridge	161:aa5281ff4a02	1063	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /!< CoreDebug DHCSR: S_RESET_ST Position /
AnnaBridge	161:aa5281ff4a02	1064	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
AnnaBridge	161:aa5281ff4a02	1065
AnnaBridge	161:aa5281ff4a02	1066	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /!< CoreDebug DHCSR: S_RETIRE_ST Position /
AnnaBridge	161:aa5281ff4a02	1067	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
AnnaBridge	161:aa5281ff4a02	1068
AnnaBridge	161:aa5281ff4a02	1069	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /!< CoreDebug DHCSR: S_LOCKUP Position /
AnnaBridge	161:aa5281ff4a02	1070	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
AnnaBridge	161:aa5281ff4a02	1071
AnnaBridge	161:aa5281ff4a02	1072	#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /!< CoreDebug DHCSR: S_SLEEP Position /
AnnaBridge	161:aa5281ff4a02	1073	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
AnnaBridge	161:aa5281ff4a02	1074
AnnaBridge	161:aa5281ff4a02	1075	#define CoreDebug_DHCSR_S_HALT_Pos 17U /!< CoreDebug DHCSR: S_HALT Position /
AnnaBridge	161:aa5281ff4a02	1076	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
AnnaBridge	161:aa5281ff4a02	1077
AnnaBridge	161:aa5281ff4a02	1078	#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /!< CoreDebug DHCSR: S_REGRDY Position /
AnnaBridge	161:aa5281ff4a02	1079	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
AnnaBridge	161:aa5281ff4a02	1080
AnnaBridge	161:aa5281ff4a02	1081	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /!< CoreDebug DHCSR: C_MASKINTS Position /
AnnaBridge	161:aa5281ff4a02	1082	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
AnnaBridge	161:aa5281ff4a02	1083
AnnaBridge	161:aa5281ff4a02	1084	#define CoreDebug_DHCSR_C_STEP_Pos 2U /!< CoreDebug DHCSR: C_STEP Position /
AnnaBridge	161:aa5281ff4a02	1085	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
AnnaBridge	161:aa5281ff4a02	1086
AnnaBridge	161:aa5281ff4a02	1087	#define CoreDebug_DHCSR_C_HALT_Pos 1U /!< CoreDebug DHCSR: C_HALT Position /
AnnaBridge	161:aa5281ff4a02	1088	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
AnnaBridge	161:aa5281ff4a02	1089
AnnaBridge	161:aa5281ff4a02	1090	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /!< CoreDebug DHCSR: C_DEBUGEN Position /
AnnaBridge	161:aa5281ff4a02	1091	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
AnnaBridge	161:aa5281ff4a02	1092
AnnaBridge	161:aa5281ff4a02	1093	/* Debug Core Register Selector Register Definitions */
AnnaBridge	161:aa5281ff4a02	1094	#define CoreDebug_DCRSR_REGWnR_Pos 16U /!< CoreDebug DCRSR: REGWnR Position /
AnnaBridge	161:aa5281ff4a02	1095	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
AnnaBridge	161:aa5281ff4a02	1096
AnnaBridge	161:aa5281ff4a02	1097	#define CoreDebug_DCRSR_REGSEL_Pos 0U /!< CoreDebug DCRSR: REGSEL Position /
AnnaBridge	161:aa5281ff4a02	1098	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
AnnaBridge	161:aa5281ff4a02	1099
AnnaBridge	161:aa5281ff4a02	1100	/* Debug Exception and Monitor Control Register */
AnnaBridge	161:aa5281ff4a02	1101	#define CoreDebug_DEMCR_DWTENA_Pos 24U /!< CoreDebug DEMCR: DWTENA Position /
AnnaBridge	161:aa5281ff4a02	1102	#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /!< CoreDebug DEMCR: DWTENA Mask /
AnnaBridge	161:aa5281ff4a02	1103
AnnaBridge	161:aa5281ff4a02	1104	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /!< CoreDebug DEMCR: VC_HARDERR Position /
AnnaBridge	161:aa5281ff4a02	1105	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
AnnaBridge	161:aa5281ff4a02	1106
AnnaBridge	161:aa5281ff4a02	1107	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /!< CoreDebug DEMCR: VC_CORERESET Position /
AnnaBridge	161:aa5281ff4a02	1108	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
AnnaBridge	161:aa5281ff4a02	1109
AnnaBridge	161:aa5281ff4a02	1110	/* Debug Authentication Control Register Definitions */
AnnaBridge	161:aa5281ff4a02	1111	#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position /
AnnaBridge	161:aa5281ff4a02	1112	#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask /
AnnaBridge	161:aa5281ff4a02	1113
AnnaBridge	161:aa5281ff4a02	1114	#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /!< CoreDebug DAUTHCTRL: SPNIDENSEL Position /
AnnaBridge	161:aa5281ff4a02	1115	#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask /
AnnaBridge	161:aa5281ff4a02	1116
AnnaBridge	161:aa5281ff4a02	1117	#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /!< CoreDebug DAUTHCTRL: INTSPIDEN Position /
AnnaBridge	161:aa5281ff4a02	1118	#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /!< CoreDebug DAUTHCTRL: INTSPIDEN Mask /
AnnaBridge	161:aa5281ff4a02	1119
AnnaBridge	161:aa5281ff4a02	1120	#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /!< CoreDebug DAUTHCTRL: SPIDENSEL Position /
AnnaBridge	161:aa5281ff4a02	1121	#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/) /!< CoreDebug DAUTHCTRL: SPIDENSEL Mask /
AnnaBridge	161:aa5281ff4a02	1122
AnnaBridge	161:aa5281ff4a02	1123	/* Debug Security Control and Status Register Definitions */
AnnaBridge	161:aa5281ff4a02	1124	#define CoreDebug_DSCSR_CDS_Pos 16U /!< CoreDebug DSCSR: CDS Position /
AnnaBridge	161:aa5281ff4a02	1125	#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /!< CoreDebug DSCSR: CDS Mask /
AnnaBridge	161:aa5281ff4a02	1126
AnnaBridge	161:aa5281ff4a02	1127	#define CoreDebug_DSCSR_SBRSEL_Pos 1U /!< CoreDebug DSCSR: SBRSEL Position /
AnnaBridge	161:aa5281ff4a02	1128	#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /!< CoreDebug DSCSR: SBRSEL Mask /
AnnaBridge	161:aa5281ff4a02	1129
AnnaBridge	161:aa5281ff4a02	1130	#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /!< CoreDebug DSCSR: SBRSELEN Position /
AnnaBridge	161:aa5281ff4a02	1131	#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/) /!< CoreDebug DSCSR: SBRSELEN Mask /
AnnaBridge	161:aa5281ff4a02	1132
AnnaBridge	161:aa5281ff4a02	1133	/@} end of group CMSIS_CoreDebug /
AnnaBridge	161:aa5281ff4a02	1134
AnnaBridge	161:aa5281ff4a02	1135
AnnaBridge	161:aa5281ff4a02	1136	/**
AnnaBridge	161:aa5281ff4a02	1137	\ingroup CMSIS_core_register
AnnaBridge	161:aa5281ff4a02	1138	\defgroup CMSIS_core_bitfield Core register bit field macros
AnnaBridge	161:aa5281ff4a02	1139	\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
AnnaBridge	161:aa5281ff4a02	1140	@{
AnnaBridge	161:aa5281ff4a02	1141	*/
AnnaBridge	161:aa5281ff4a02	1142
AnnaBridge	161:aa5281ff4a02	1143	/**
AnnaBridge	161:aa5281ff4a02	1144	\brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge	161:aa5281ff4a02	1145	\param[in] field Name of the register bit field.
AnnaBridge	161:aa5281ff4a02	1146	\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge	161:aa5281ff4a02	1147	\return Masked and shifted value.
AnnaBridge	161:aa5281ff4a02	1148	*/
AnnaBridge	161:aa5281ff4a02	1149	#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge	161:aa5281ff4a02	1150
AnnaBridge	161:aa5281ff4a02	1151	/**
AnnaBridge	161:aa5281ff4a02	1152	\brief Mask and shift a register value to extract a bit filed value.
AnnaBridge	161:aa5281ff4a02	1153	\param[in] field Name of the register bit field.
AnnaBridge	161:aa5281ff4a02	1154	\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge	161:aa5281ff4a02	1155	\return Masked and shifted bit field value.
AnnaBridge	161:aa5281ff4a02	1156	*/
AnnaBridge	161:aa5281ff4a02	1157	#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge	161:aa5281ff4a02	1158
AnnaBridge	161:aa5281ff4a02	1159	/@} end of group CMSIS_core_bitfield /
AnnaBridge	161:aa5281ff4a02	1160
AnnaBridge	161:aa5281ff4a02	1161
AnnaBridge	161:aa5281ff4a02	1162	/**
AnnaBridge	161:aa5281ff4a02	1163	\ingroup CMSIS_core_register
AnnaBridge	161:aa5281ff4a02	1164	\defgroup CMSIS_core_base Core Definitions
AnnaBridge	161:aa5281ff4a02	1165	\brief Definitions for base addresses, unions, and structures.
AnnaBridge	161:aa5281ff4a02	1166	@{
AnnaBridge	161:aa5281ff4a02	1167	*/
AnnaBridge	161:aa5281ff4a02	1168
AnnaBridge	161:aa5281ff4a02	1169	/* Memory mapping of Core Hardware */
AnnaBridge	161:aa5281ff4a02	1170	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
AnnaBridge	161:aa5281ff4a02	1171	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
AnnaBridge	161:aa5281ff4a02	1172	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
AnnaBridge	161:aa5281ff4a02	1173	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
AnnaBridge	161:aa5281ff4a02	1174	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
AnnaBridge	161:aa5281ff4a02	1175	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
AnnaBridge	161:aa5281ff4a02	1176	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
AnnaBridge	161:aa5281ff4a02	1177
AnnaBridge	161:aa5281ff4a02	1178
AnnaBridge	161:aa5281ff4a02	1179	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
AnnaBridge	161:aa5281ff4a02	1180	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
AnnaBridge	161:aa5281ff4a02	1181	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
AnnaBridge	161:aa5281ff4a02	1182	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
AnnaBridge	161:aa5281ff4a02	1183	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
AnnaBridge	161:aa5281ff4a02	1184	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE ) /!< Core Debug configuration struct */
AnnaBridge	161:aa5281ff4a02	1185
AnnaBridge	161:aa5281ff4a02	1186	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge	161:aa5281ff4a02	1187	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
AnnaBridge	161:aa5281ff4a02	1188	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
AnnaBridge	161:aa5281ff4a02	1189	#endif
AnnaBridge	161:aa5281ff4a02	1190
AnnaBridge	161:aa5281ff4a02	1191	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	161:aa5281ff4a02	1192	#define SAU_BASE (SCS_BASE + 0x0DD0UL) /!< Security Attribution Unit /
AnnaBridge	161:aa5281ff4a02	1193	#define SAU ((SAU_Type ) SAU_BASE ) /!< Security Attribution Unit */
AnnaBridge	161:aa5281ff4a02	1194	#endif
AnnaBridge	161:aa5281ff4a02	1195
AnnaBridge	161:aa5281ff4a02	1196	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	161:aa5281ff4a02	1197	#define SCS_BASE_NS (0xE002E000UL) /!< System Control Space Base Address (non-secure address space) /
AnnaBridge	161:aa5281ff4a02	1198	#define CoreDebug_BASE_NS (0xE002EDF0UL) /!< Core Debug Base Address (non-secure address space) /
AnnaBridge	161:aa5281ff4a02	1199	#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /!< SysTick Base Address (non-secure address space) /
AnnaBridge	161:aa5281ff4a02	1200	#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /!< NVIC Base Address (non-secure address space) /
AnnaBridge	161:aa5281ff4a02	1201	#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /!< System Control Block Base Address (non-secure address space) /
AnnaBridge	161:aa5281ff4a02	1202
AnnaBridge	161:aa5281ff4a02	1203	#define SCB_NS ((SCB_Type ) SCB_BASE_NS ) /!< SCB configuration struct (non-secure address space) */
AnnaBridge	161:aa5281ff4a02	1204	#define SysTick_NS ((SysTick_Type ) SysTick_BASE_NS ) /!< SysTick configuration struct (non-secure address space) */
AnnaBridge	161:aa5281ff4a02	1205	#define NVIC_NS ((NVIC_Type ) NVIC_BASE_NS ) /!< NVIC configuration struct (non-secure address space) */
AnnaBridge	161:aa5281ff4a02	1206	#define CoreDebug_NS ((CoreDebug_Type ) CoreDebug_BASE_NS) /!< Core Debug configuration struct (non-secure address space) */
AnnaBridge	161:aa5281ff4a02	1207
AnnaBridge	161:aa5281ff4a02	1208	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge	161:aa5281ff4a02	1209	#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /!< Memory Protection Unit (non-secure address space) /
AnnaBridge	161:aa5281ff4a02	1210	#define MPU_NS ((MPU_Type ) MPU_BASE_NS ) /!< Memory Protection Unit (non-secure address space) */
AnnaBridge	161:aa5281ff4a02	1211	#endif
AnnaBridge	161:aa5281ff4a02	1212
AnnaBridge	161:aa5281ff4a02	1213	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge	161:aa5281ff4a02	1214	/@} /
AnnaBridge	161:aa5281ff4a02	1215
AnnaBridge	161:aa5281ff4a02	1216
AnnaBridge	161:aa5281ff4a02	1217
AnnaBridge	161:aa5281ff4a02	1218	/*******************************************************************************
AnnaBridge	161:aa5281ff4a02	1219	* Hardware Abstraction Layer
AnnaBridge	161:aa5281ff4a02	1220	Core Function Interface contains:
AnnaBridge	161:aa5281ff4a02	1221	- Core NVIC Functions
AnnaBridge	161:aa5281ff4a02	1222	- Core SysTick Functions
AnnaBridge	161:aa5281ff4a02	1223	- Core Register Access Functions
AnnaBridge	161:aa5281ff4a02	1224	******************************************************************************/
AnnaBridge	161:aa5281ff4a02	1225	/**
AnnaBridge	161:aa5281ff4a02	1226	\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
AnnaBridge	161:aa5281ff4a02	1227	*/
AnnaBridge	161:aa5281ff4a02	1228
AnnaBridge	161:aa5281ff4a02	1229
AnnaBridge	161:aa5281ff4a02	1230
AnnaBridge	161:aa5281ff4a02	1231	/* ########################## NVIC functions #################################### */
AnnaBridge	161:aa5281ff4a02	1232	/**
AnnaBridge	161:aa5281ff4a02	1233	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	161:aa5281ff4a02	1234	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge	161:aa5281ff4a02	1235	\brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge	161:aa5281ff4a02	1236	@{
AnnaBridge	161:aa5281ff4a02	1237	*/
AnnaBridge	161:aa5281ff4a02	1238
AnnaBridge	161:aa5281ff4a02	1239	#ifdef CMSIS_NVIC_VIRTUAL
AnnaBridge	161:aa5281ff4a02	1240	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge	161:aa5281ff4a02	1241	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
AnnaBridge	161:aa5281ff4a02	1242	#endif
AnnaBridge	161:aa5281ff4a02	1243	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge	161:aa5281ff4a02	1244	#else
AnnaBridge	161:aa5281ff4a02	1245	/#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 /
AnnaBridge	161:aa5281ff4a02	1246	/#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 /
AnnaBridge	161:aa5281ff4a02	1247	#define NVIC_EnableIRQ __NVIC_EnableIRQ
AnnaBridge	161:aa5281ff4a02	1248	#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
AnnaBridge	161:aa5281ff4a02	1249	#define NVIC_DisableIRQ __NVIC_DisableIRQ
AnnaBridge	161:aa5281ff4a02	1250	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
AnnaBridge	161:aa5281ff4a02	1251	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
AnnaBridge	161:aa5281ff4a02	1252	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
AnnaBridge	161:aa5281ff4a02	1253	#define NVIC_GetActive __NVIC_GetActive
AnnaBridge	161:aa5281ff4a02	1254	#define NVIC_SetPriority __NVIC_SetPriority
AnnaBridge	161:aa5281ff4a02	1255	#define NVIC_GetPriority __NVIC_GetPriority
AnnaBridge	161:aa5281ff4a02	1256	#define NVIC_SystemReset __NVIC_SystemReset
AnnaBridge	161:aa5281ff4a02	1257	#endif /* CMSIS_NVIC_VIRTUAL */
AnnaBridge	161:aa5281ff4a02	1258
AnnaBridge	161:aa5281ff4a02	1259	#ifdef CMSIS_VECTAB_VIRTUAL
AnnaBridge	161:aa5281ff4a02	1260	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge	161:aa5281ff4a02	1261	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
AnnaBridge	161:aa5281ff4a02	1262	#endif
AnnaBridge	161:aa5281ff4a02	1263	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge	161:aa5281ff4a02	1264	#else
AnnaBridge	161:aa5281ff4a02	1265	#define NVIC_SetVector __NVIC_SetVector
AnnaBridge	161:aa5281ff4a02	1266	#define NVIC_GetVector __NVIC_GetVector
AnnaBridge	161:aa5281ff4a02	1267	#endif /* (CMSIS_VECTAB_VIRTUAL) */
AnnaBridge	161:aa5281ff4a02	1268
AnnaBridge	161:aa5281ff4a02	1269	#define NVIC_USER_IRQ_OFFSET 16
AnnaBridge	161:aa5281ff4a02	1270
AnnaBridge	161:aa5281ff4a02	1271
Anna Bridge	169:a7c7b631e539	1272	/* Interrupt Priorities are WORD accessible only under Armv6-M */
AnnaBridge	161:aa5281ff4a02	1273	/* The following MACROS handle generation of the register offset and byte masks */
AnnaBridge	161:aa5281ff4a02	1274	#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
AnnaBridge	161:aa5281ff4a02	1275	#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
AnnaBridge	161:aa5281ff4a02	1276	#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
AnnaBridge	161:aa5281ff4a02	1277
AnnaBridge	161:aa5281ff4a02	1278
AnnaBridge	161:aa5281ff4a02	1279	/**
AnnaBridge	161:aa5281ff4a02	1280	\brief Enable Interrupt
AnnaBridge	161:aa5281ff4a02	1281	\details Enables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge	161:aa5281ff4a02	1282	\param [in] IRQn Device specific interrupt number.
AnnaBridge	161:aa5281ff4a02	1283	\note IRQn must not be negative.
AnnaBridge	161:aa5281ff4a02	1284	*/
AnnaBridge	161:aa5281ff4a02	1285	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge	161:aa5281ff4a02	1286	{
AnnaBridge	161:aa5281ff4a02	1287	if ((int32_t)(IRQn) >= 0)
AnnaBridge	161:aa5281ff4a02	1288	{
Anna Bridge	169:a7c7b631e539	1289	NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	161:aa5281ff4a02	1290	}
AnnaBridge	161:aa5281ff4a02	1291	}
AnnaBridge	161:aa5281ff4a02	1292
AnnaBridge	161:aa5281ff4a02	1293
AnnaBridge	161:aa5281ff4a02	1294	/**
AnnaBridge	161:aa5281ff4a02	1295	\brief Get Interrupt Enable status
AnnaBridge	161:aa5281ff4a02	1296	\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
AnnaBridge	161:aa5281ff4a02	1297	\param [in] IRQn Device specific interrupt number.
AnnaBridge	161:aa5281ff4a02	1298	\return 0 Interrupt is not enabled.
AnnaBridge	161:aa5281ff4a02	1299	\return 1 Interrupt is enabled.
AnnaBridge	161:aa5281ff4a02	1300	\note IRQn must not be negative.
AnnaBridge	161:aa5281ff4a02	1301	*/
AnnaBridge	161:aa5281ff4a02	1302	__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
AnnaBridge	161:aa5281ff4a02	1303	{
AnnaBridge	161:aa5281ff4a02	1304	if ((int32_t)(IRQn) >= 0)
AnnaBridge	161:aa5281ff4a02	1305	{
Anna Bridge	169:a7c7b631e539	1306	return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	161:aa5281ff4a02	1307	}
AnnaBridge	161:aa5281ff4a02	1308	else
AnnaBridge	161:aa5281ff4a02	1309	{
AnnaBridge	161:aa5281ff4a02	1310	return(0U);
AnnaBridge	161:aa5281ff4a02	1311	}
AnnaBridge	161:aa5281ff4a02	1312	}
AnnaBridge	161:aa5281ff4a02	1313
AnnaBridge	161:aa5281ff4a02	1314
AnnaBridge	161:aa5281ff4a02	1315	/**
AnnaBridge	161:aa5281ff4a02	1316	\brief Disable Interrupt
AnnaBridge	161:aa5281ff4a02	1317	\details Disables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge	161:aa5281ff4a02	1318	\param [in] IRQn Device specific interrupt number.
AnnaBridge	161:aa5281ff4a02	1319	\note IRQn must not be negative.
AnnaBridge	161:aa5281ff4a02	1320	*/
AnnaBridge	161:aa5281ff4a02	1321	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge	161:aa5281ff4a02	1322	{
AnnaBridge	161:aa5281ff4a02	1323	if ((int32_t)(IRQn) >= 0)
AnnaBridge	161:aa5281ff4a02	1324	{
Anna Bridge	169:a7c7b631e539	1325	NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	161:aa5281ff4a02	1326	__DSB();
AnnaBridge	161:aa5281ff4a02	1327	__ISB();
AnnaBridge	161:aa5281ff4a02	1328	}
AnnaBridge	161:aa5281ff4a02	1329	}
AnnaBridge	161:aa5281ff4a02	1330
AnnaBridge	161:aa5281ff4a02	1331
AnnaBridge	161:aa5281ff4a02	1332	/**
AnnaBridge	161:aa5281ff4a02	1333	\brief Get Pending Interrupt
AnnaBridge	161:aa5281ff4a02	1334	\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
AnnaBridge	161:aa5281ff4a02	1335	\param [in] IRQn Device specific interrupt number.
AnnaBridge	161:aa5281ff4a02	1336	\return 0 Interrupt status is not pending.
AnnaBridge	161:aa5281ff4a02	1337	\return 1 Interrupt status is pending.
AnnaBridge	161:aa5281ff4a02	1338	\note IRQn must not be negative.
AnnaBridge	161:aa5281ff4a02	1339	*/
AnnaBridge	161:aa5281ff4a02	1340	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
AnnaBridge	161:aa5281ff4a02	1341	{
AnnaBridge	161:aa5281ff4a02	1342	if ((int32_t)(IRQn) >= 0)
AnnaBridge	161:aa5281ff4a02	1343	{
Anna Bridge	169:a7c7b631e539	1344	return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	161:aa5281ff4a02	1345	}
AnnaBridge	161:aa5281ff4a02	1346	else
AnnaBridge	161:aa5281ff4a02	1347	{
AnnaBridge	161:aa5281ff4a02	1348	return(0U);
AnnaBridge	161:aa5281ff4a02	1349	}
AnnaBridge	161:aa5281ff4a02	1350	}
AnnaBridge	161:aa5281ff4a02	1351
AnnaBridge	161:aa5281ff4a02	1352
AnnaBridge	161:aa5281ff4a02	1353	/**
AnnaBridge	161:aa5281ff4a02	1354	\brief Set Pending Interrupt
AnnaBridge	161:aa5281ff4a02	1355	\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge	161:aa5281ff4a02	1356	\param [in] IRQn Device specific interrupt number.
AnnaBridge	161:aa5281ff4a02	1357	\note IRQn must not be negative.
AnnaBridge	161:aa5281ff4a02	1358	*/
AnnaBridge	161:aa5281ff4a02	1359	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge	161:aa5281ff4a02	1360	{
AnnaBridge	161:aa5281ff4a02	1361	if ((int32_t)(IRQn) >= 0)
AnnaBridge	161:aa5281ff4a02	1362	{
Anna Bridge	169:a7c7b631e539	1363	NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	161:aa5281ff4a02	1364	}
AnnaBridge	161:aa5281ff4a02	1365	}
AnnaBridge	161:aa5281ff4a02	1366
AnnaBridge	161:aa5281ff4a02	1367
AnnaBridge	161:aa5281ff4a02	1368	/**
AnnaBridge	161:aa5281ff4a02	1369	\brief Clear Pending Interrupt
AnnaBridge	161:aa5281ff4a02	1370	\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge	161:aa5281ff4a02	1371	\param [in] IRQn Device specific interrupt number.
AnnaBridge	161:aa5281ff4a02	1372	\note IRQn must not be negative.
AnnaBridge	161:aa5281ff4a02	1373	*/
AnnaBridge	161:aa5281ff4a02	1374	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge	161:aa5281ff4a02	1375	{
AnnaBridge	161:aa5281ff4a02	1376	if ((int32_t)(IRQn) >= 0)
AnnaBridge	161:aa5281ff4a02	1377	{
Anna Bridge	169:a7c7b631e539	1378	NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	161:aa5281ff4a02	1379	}
AnnaBridge	161:aa5281ff4a02	1380	}
AnnaBridge	161:aa5281ff4a02	1381
AnnaBridge	161:aa5281ff4a02	1382
AnnaBridge	161:aa5281ff4a02	1383	/**
AnnaBridge	161:aa5281ff4a02	1384	\brief Get Active Interrupt
AnnaBridge	161:aa5281ff4a02	1385	\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
AnnaBridge	161:aa5281ff4a02	1386	\param [in] IRQn Device specific interrupt number.
AnnaBridge	161:aa5281ff4a02	1387	\return 0 Interrupt status is not active.
AnnaBridge	161:aa5281ff4a02	1388	\return 1 Interrupt status is active.
AnnaBridge	161:aa5281ff4a02	1389	\note IRQn must not be negative.
AnnaBridge	161:aa5281ff4a02	1390	*/
AnnaBridge	161:aa5281ff4a02	1391	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
AnnaBridge	161:aa5281ff4a02	1392	{
AnnaBridge	161:aa5281ff4a02	1393	if ((int32_t)(IRQn) >= 0)
AnnaBridge	161:aa5281ff4a02	1394	{
Anna Bridge	169:a7c7b631e539	1395	return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	161:aa5281ff4a02	1396	}
AnnaBridge	161:aa5281ff4a02	1397	else
AnnaBridge	161:aa5281ff4a02	1398	{
AnnaBridge	161:aa5281ff4a02	1399	return(0U);
AnnaBridge	161:aa5281ff4a02	1400	}
AnnaBridge	161:aa5281ff4a02	1401	}
AnnaBridge	161:aa5281ff4a02	1402
AnnaBridge	161:aa5281ff4a02	1403
AnnaBridge	161:aa5281ff4a02	1404	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	161:aa5281ff4a02	1405	/**
AnnaBridge	161:aa5281ff4a02	1406	\brief Get Interrupt Target State
AnnaBridge	161:aa5281ff4a02	1407	\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
AnnaBridge	161:aa5281ff4a02	1408	\param [in] IRQn Device specific interrupt number.
AnnaBridge	161:aa5281ff4a02	1409	\return 0 if interrupt is assigned to Secure
AnnaBridge	161:aa5281ff4a02	1410	\return 1 if interrupt is assigned to Non Secure
AnnaBridge	161:aa5281ff4a02	1411	\note IRQn must not be negative.
AnnaBridge	161:aa5281ff4a02	1412	*/
AnnaBridge	161:aa5281ff4a02	1413	__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
AnnaBridge	161:aa5281ff4a02	1414	{
AnnaBridge	161:aa5281ff4a02	1415	if ((int32_t)(IRQn) >= 0)
AnnaBridge	161:aa5281ff4a02	1416	{
Anna Bridge	169:a7c7b631e539	1417	return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	161:aa5281ff4a02	1418	}
AnnaBridge	161:aa5281ff4a02	1419	else
AnnaBridge	161:aa5281ff4a02	1420	{
AnnaBridge	161:aa5281ff4a02	1421	return(0U);
AnnaBridge	161:aa5281ff4a02	1422	}
AnnaBridge	161:aa5281ff4a02	1423	}
AnnaBridge	161:aa5281ff4a02	1424
AnnaBridge	161:aa5281ff4a02	1425
AnnaBridge	161:aa5281ff4a02	1426	/**
AnnaBridge	161:aa5281ff4a02	1427	\brief Set Interrupt Target State
AnnaBridge	161:aa5281ff4a02	1428	\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
AnnaBridge	161:aa5281ff4a02	1429	\param [in] IRQn Device specific interrupt number.
AnnaBridge	161:aa5281ff4a02	1430	\return 0 if interrupt is assigned to Secure
AnnaBridge	161:aa5281ff4a02	1431	1 if interrupt is assigned to Non Secure
AnnaBridge	161:aa5281ff4a02	1432	\note IRQn must not be negative.
AnnaBridge	161:aa5281ff4a02	1433	*/
AnnaBridge	161:aa5281ff4a02	1434	__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
AnnaBridge	161:aa5281ff4a02	1435	{
AnnaBridge	161:aa5281ff4a02	1436	if ((int32_t)(IRQn) >= 0)
AnnaBridge	161:aa5281ff4a02	1437	{
Anna Bridge	169:a7c7b631e539	1438	NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] \|= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
Anna Bridge	169:a7c7b631e539	1439	return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	161:aa5281ff4a02	1440	}
AnnaBridge	161:aa5281ff4a02	1441	else
AnnaBridge	161:aa5281ff4a02	1442	{
AnnaBridge	161:aa5281ff4a02	1443	return(0U);
AnnaBridge	161:aa5281ff4a02	1444	}
AnnaBridge	161:aa5281ff4a02	1445	}
AnnaBridge	161:aa5281ff4a02	1446
AnnaBridge	161:aa5281ff4a02	1447
AnnaBridge	161:aa5281ff4a02	1448	/**
AnnaBridge	161:aa5281ff4a02	1449	\brief Clear Interrupt Target State
AnnaBridge	161:aa5281ff4a02	1450	\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
AnnaBridge	161:aa5281ff4a02	1451	\param [in] IRQn Device specific interrupt number.
AnnaBridge	161:aa5281ff4a02	1452	\return 0 if interrupt is assigned to Secure
AnnaBridge	161:aa5281ff4a02	1453	1 if interrupt is assigned to Non Secure
AnnaBridge	161:aa5281ff4a02	1454	\note IRQn must not be negative.
AnnaBridge	161:aa5281ff4a02	1455	*/
AnnaBridge	161:aa5281ff4a02	1456	__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
AnnaBridge	161:aa5281ff4a02	1457	{
AnnaBridge	161:aa5281ff4a02	1458	if ((int32_t)(IRQn) >= 0)
AnnaBridge	161:aa5281ff4a02	1459	{
Anna Bridge	169:a7c7b631e539	1460	NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
Anna Bridge	169:a7c7b631e539	1461	return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	161:aa5281ff4a02	1462	}
AnnaBridge	161:aa5281ff4a02	1463	else
AnnaBridge	161:aa5281ff4a02	1464	{
AnnaBridge	161:aa5281ff4a02	1465	return(0U);
AnnaBridge	161:aa5281ff4a02	1466	}
AnnaBridge	161:aa5281ff4a02	1467	}
AnnaBridge	161:aa5281ff4a02	1468	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge	161:aa5281ff4a02	1469
AnnaBridge	161:aa5281ff4a02	1470
AnnaBridge	161:aa5281ff4a02	1471	/**
AnnaBridge	161:aa5281ff4a02	1472	\brief Set Interrupt Priority
AnnaBridge	161:aa5281ff4a02	1473	\details Sets the priority of a device specific interrupt or a processor exception.
AnnaBridge	161:aa5281ff4a02	1474	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	161:aa5281ff4a02	1475	or negative to specify a processor exception.
AnnaBridge	161:aa5281ff4a02	1476	\param [in] IRQn Interrupt number.
AnnaBridge	161:aa5281ff4a02	1477	\param [in] priority Priority to set.
AnnaBridge	161:aa5281ff4a02	1478	\note The priority cannot be set for every processor exception.
AnnaBridge	161:aa5281ff4a02	1479	*/
AnnaBridge	161:aa5281ff4a02	1480	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge	161:aa5281ff4a02	1481	{
AnnaBridge	161:aa5281ff4a02	1482	if ((int32_t)(IRQn) >= 0)
AnnaBridge	161:aa5281ff4a02	1483	{
AnnaBridge	161:aa5281ff4a02	1484	NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) \|
AnnaBridge	161:aa5281ff4a02	1485	(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge	161:aa5281ff4a02	1486	}
AnnaBridge	161:aa5281ff4a02	1487	else
AnnaBridge	161:aa5281ff4a02	1488	{
AnnaBridge	161:aa5281ff4a02	1489	SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) \|
AnnaBridge	161:aa5281ff4a02	1490	(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge	161:aa5281ff4a02	1491	}
AnnaBridge	161:aa5281ff4a02	1492	}
AnnaBridge	161:aa5281ff4a02	1493
AnnaBridge	161:aa5281ff4a02	1494
AnnaBridge	161:aa5281ff4a02	1495	/**
AnnaBridge	161:aa5281ff4a02	1496	\brief Get Interrupt Priority
AnnaBridge	161:aa5281ff4a02	1497	\details Reads the priority of a device specific interrupt or a processor exception.
AnnaBridge	161:aa5281ff4a02	1498	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	161:aa5281ff4a02	1499	or negative to specify a processor exception.
AnnaBridge	161:aa5281ff4a02	1500	\param [in] IRQn Interrupt number.
AnnaBridge	161:aa5281ff4a02	1501	\return Interrupt Priority.
AnnaBridge	161:aa5281ff4a02	1502	Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge	161:aa5281ff4a02	1503	*/
AnnaBridge	161:aa5281ff4a02	1504	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge	161:aa5281ff4a02	1505	{
AnnaBridge	161:aa5281ff4a02	1506
AnnaBridge	161:aa5281ff4a02	1507	if ((int32_t)(IRQn) >= 0)
AnnaBridge	161:aa5281ff4a02	1508	{
AnnaBridge	161:aa5281ff4a02	1509	return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge	161:aa5281ff4a02	1510	}
AnnaBridge	161:aa5281ff4a02	1511	else
AnnaBridge	161:aa5281ff4a02	1512	{
AnnaBridge	161:aa5281ff4a02	1513	return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge	161:aa5281ff4a02	1514	}
AnnaBridge	161:aa5281ff4a02	1515	}
AnnaBridge	161:aa5281ff4a02	1516
AnnaBridge	161:aa5281ff4a02	1517
AnnaBridge	161:aa5281ff4a02	1518	/**
AnnaBridge	161:aa5281ff4a02	1519	\brief Set Interrupt Vector
AnnaBridge	161:aa5281ff4a02	1520	\details Sets an interrupt vector in SRAM based interrupt vector table.
AnnaBridge	161:aa5281ff4a02	1521	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	161:aa5281ff4a02	1522	or negative to specify a processor exception.
AnnaBridge	161:aa5281ff4a02	1523	VTOR must been relocated to SRAM before.
AnnaBridge	161:aa5281ff4a02	1524	If VTOR is not present address 0 must be mapped to SRAM.
AnnaBridge	161:aa5281ff4a02	1525	\param [in] IRQn Interrupt number
AnnaBridge	161:aa5281ff4a02	1526	\param [in] vector Address of interrupt handler function
AnnaBridge	161:aa5281ff4a02	1527	*/
AnnaBridge	161:aa5281ff4a02	1528	__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
AnnaBridge	161:aa5281ff4a02	1529	{
AnnaBridge	161:aa5281ff4a02	1530	#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge	161:aa5281ff4a02	1531	uint32_t vectors = (uint32_t )SCB->VTOR;
AnnaBridge	161:aa5281ff4a02	1532	#else
AnnaBridge	161:aa5281ff4a02	1533	uint32_t vectors = (uint32_t )0x0U;
AnnaBridge	161:aa5281ff4a02	1534	#endif
AnnaBridge	161:aa5281ff4a02	1535	vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
AnnaBridge	161:aa5281ff4a02	1536	}
AnnaBridge	161:aa5281ff4a02	1537
AnnaBridge	161:aa5281ff4a02	1538
AnnaBridge	161:aa5281ff4a02	1539	/**
AnnaBridge	161:aa5281ff4a02	1540	\brief Get Interrupt Vector
AnnaBridge	161:aa5281ff4a02	1541	\details Reads an interrupt vector from interrupt vector table.
AnnaBridge	161:aa5281ff4a02	1542	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	161:aa5281ff4a02	1543	or negative to specify a processor exception.
AnnaBridge	161:aa5281ff4a02	1544	\param [in] IRQn Interrupt number.
AnnaBridge	161:aa5281ff4a02	1545	\return Address of interrupt handler function
AnnaBridge	161:aa5281ff4a02	1546	*/
AnnaBridge	161:aa5281ff4a02	1547	__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
AnnaBridge	161:aa5281ff4a02	1548	{
AnnaBridge	161:aa5281ff4a02	1549	#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge	161:aa5281ff4a02	1550	uint32_t vectors = (uint32_t )SCB->VTOR;
AnnaBridge	161:aa5281ff4a02	1551	#else
AnnaBridge	161:aa5281ff4a02	1552	uint32_t vectors = (uint32_t )0x0U;
AnnaBridge	161:aa5281ff4a02	1553	#endif
AnnaBridge	161:aa5281ff4a02	1554	return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
AnnaBridge	161:aa5281ff4a02	1555	}
AnnaBridge	161:aa5281ff4a02	1556
AnnaBridge	161:aa5281ff4a02	1557
AnnaBridge	161:aa5281ff4a02	1558	/**
AnnaBridge	161:aa5281ff4a02	1559	\brief System Reset
AnnaBridge	161:aa5281ff4a02	1560	\details Initiates a system reset request to reset the MCU.
AnnaBridge	161:aa5281ff4a02	1561	*/
AnnaBridge	161:aa5281ff4a02	1562	__STATIC_INLINE void __NVIC_SystemReset(void)
AnnaBridge	161:aa5281ff4a02	1563	{
AnnaBridge	161:aa5281ff4a02	1564	__DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge	161:aa5281ff4a02	1565	buffered write are completed before reset */
AnnaBridge	161:aa5281ff4a02	1566	SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
AnnaBridge	161:aa5281ff4a02	1567	SCB_AIRCR_SYSRESETREQ_Msk);
AnnaBridge	161:aa5281ff4a02	1568	__DSB(); /* Ensure completion of memory access */
AnnaBridge	161:aa5281ff4a02	1569
AnnaBridge	161:aa5281ff4a02	1570	for(;;) /* wait until reset */
AnnaBridge	161:aa5281ff4a02	1571	{
AnnaBridge	161:aa5281ff4a02	1572	__NOP();
AnnaBridge	161:aa5281ff4a02	1573	}
AnnaBridge	161:aa5281ff4a02	1574	}
AnnaBridge	161:aa5281ff4a02	1575
AnnaBridge	161:aa5281ff4a02	1576	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	161:aa5281ff4a02	1577	/**
AnnaBridge	161:aa5281ff4a02	1578	\brief Enable Interrupt (non-secure)
AnnaBridge	161:aa5281ff4a02	1579	\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
AnnaBridge	161:aa5281ff4a02	1580	\param [in] IRQn Device specific interrupt number.
AnnaBridge	161:aa5281ff4a02	1581	\note IRQn must not be negative.
AnnaBridge	161:aa5281ff4a02	1582	*/
AnnaBridge	161:aa5281ff4a02	1583	__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
AnnaBridge	161:aa5281ff4a02	1584	{
AnnaBridge	161:aa5281ff4a02	1585	if ((int32_t)(IRQn) >= 0)
AnnaBridge	161:aa5281ff4a02	1586	{
Anna Bridge	169:a7c7b631e539	1587	NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	161:aa5281ff4a02	1588	}
AnnaBridge	161:aa5281ff4a02	1589	}
AnnaBridge	161:aa5281ff4a02	1590
AnnaBridge	161:aa5281ff4a02	1591
AnnaBridge	161:aa5281ff4a02	1592	/**
AnnaBridge	161:aa5281ff4a02	1593	\brief Get Interrupt Enable status (non-secure)
AnnaBridge	161:aa5281ff4a02	1594	\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
AnnaBridge	161:aa5281ff4a02	1595	\param [in] IRQn Device specific interrupt number.
AnnaBridge	161:aa5281ff4a02	1596	\return 0 Interrupt is not enabled.
AnnaBridge	161:aa5281ff4a02	1597	\return 1 Interrupt is enabled.
AnnaBridge	161:aa5281ff4a02	1598	\note IRQn must not be negative.
AnnaBridge	161:aa5281ff4a02	1599	*/
AnnaBridge	161:aa5281ff4a02	1600	__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
AnnaBridge	161:aa5281ff4a02	1601	{
AnnaBridge	161:aa5281ff4a02	1602	if ((int32_t)(IRQn) >= 0)
AnnaBridge	161:aa5281ff4a02	1603	{
Anna Bridge	169:a7c7b631e539	1604	return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	161:aa5281ff4a02	1605	}
AnnaBridge	161:aa5281ff4a02	1606	else
AnnaBridge	161:aa5281ff4a02	1607	{
AnnaBridge	161:aa5281ff4a02	1608	return(0U);
AnnaBridge	161:aa5281ff4a02	1609	}
AnnaBridge	161:aa5281ff4a02	1610	}
AnnaBridge	161:aa5281ff4a02	1611
AnnaBridge	161:aa5281ff4a02	1612
AnnaBridge	161:aa5281ff4a02	1613	/**
AnnaBridge	161:aa5281ff4a02	1614	\brief Disable Interrupt (non-secure)
AnnaBridge	161:aa5281ff4a02	1615	\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
AnnaBridge	161:aa5281ff4a02	1616	\param [in] IRQn Device specific interrupt number.
AnnaBridge	161:aa5281ff4a02	1617	\note IRQn must not be negative.
AnnaBridge	161:aa5281ff4a02	1618	*/
AnnaBridge	161:aa5281ff4a02	1619	__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
AnnaBridge	161:aa5281ff4a02	1620	{
AnnaBridge	161:aa5281ff4a02	1621	if ((int32_t)(IRQn) >= 0)
AnnaBridge	161:aa5281ff4a02	1622	{
Anna Bridge	169:a7c7b631e539	1623	NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	161:aa5281ff4a02	1624	}
AnnaBridge	161:aa5281ff4a02	1625	}
AnnaBridge	161:aa5281ff4a02	1626
AnnaBridge	161:aa5281ff4a02	1627
AnnaBridge	161:aa5281ff4a02	1628	/**
AnnaBridge	161:aa5281ff4a02	1629	\brief Get Pending Interrupt (non-secure)
AnnaBridge	161:aa5281ff4a02	1630	\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
AnnaBridge	161:aa5281ff4a02	1631	\param [in] IRQn Device specific interrupt number.
AnnaBridge	161:aa5281ff4a02	1632	\return 0 Interrupt status is not pending.
AnnaBridge	161:aa5281ff4a02	1633	\return 1 Interrupt status is pending.
AnnaBridge	161:aa5281ff4a02	1634	\note IRQn must not be negative.
AnnaBridge	161:aa5281ff4a02	1635	*/
AnnaBridge	161:aa5281ff4a02	1636	__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
AnnaBridge	161:aa5281ff4a02	1637	{
AnnaBridge	161:aa5281ff4a02	1638	if ((int32_t)(IRQn) >= 0)
AnnaBridge	161:aa5281ff4a02	1639	{
Anna Bridge	169:a7c7b631e539	1640	return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	161:aa5281ff4a02	1641	}
AnnaBridge	161:aa5281ff4a02	1642	else
AnnaBridge	161:aa5281ff4a02	1643	{
AnnaBridge	161:aa5281ff4a02	1644	return(0U);
AnnaBridge	161:aa5281ff4a02	1645	}
AnnaBridge	161:aa5281ff4a02	1646	}
AnnaBridge	161:aa5281ff4a02	1647
AnnaBridge	161:aa5281ff4a02	1648
AnnaBridge	161:aa5281ff4a02	1649	/**
AnnaBridge	161:aa5281ff4a02	1650	\brief Set Pending Interrupt (non-secure)
AnnaBridge	161:aa5281ff4a02	1651	\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
AnnaBridge	161:aa5281ff4a02	1652	\param [in] IRQn Device specific interrupt number.
AnnaBridge	161:aa5281ff4a02	1653	\note IRQn must not be negative.
AnnaBridge	161:aa5281ff4a02	1654	*/
AnnaBridge	161:aa5281ff4a02	1655	__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
AnnaBridge	161:aa5281ff4a02	1656	{
AnnaBridge	161:aa5281ff4a02	1657	if ((int32_t)(IRQn) >= 0)
AnnaBridge	161:aa5281ff4a02	1658	{
Anna Bridge	169:a7c7b631e539	1659	NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	161:aa5281ff4a02	1660	}
AnnaBridge	161:aa5281ff4a02	1661	}
AnnaBridge	161:aa5281ff4a02	1662
AnnaBridge	161:aa5281ff4a02	1663
AnnaBridge	161:aa5281ff4a02	1664	/**
AnnaBridge	161:aa5281ff4a02	1665	\brief Clear Pending Interrupt (non-secure)
AnnaBridge	161:aa5281ff4a02	1666	\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
AnnaBridge	161:aa5281ff4a02	1667	\param [in] IRQn Device specific interrupt number.
AnnaBridge	161:aa5281ff4a02	1668	\note IRQn must not be negative.
AnnaBridge	161:aa5281ff4a02	1669	*/
AnnaBridge	161:aa5281ff4a02	1670	__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
AnnaBridge	161:aa5281ff4a02	1671	{
AnnaBridge	161:aa5281ff4a02	1672	if ((int32_t)(IRQn) >= 0)
AnnaBridge	161:aa5281ff4a02	1673	{
Anna Bridge	169:a7c7b631e539	1674	NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	161:aa5281ff4a02	1675	}
AnnaBridge	161:aa5281ff4a02	1676	}
AnnaBridge	161:aa5281ff4a02	1677
AnnaBridge	161:aa5281ff4a02	1678
AnnaBridge	161:aa5281ff4a02	1679	/**
AnnaBridge	161:aa5281ff4a02	1680	\brief Get Active Interrupt (non-secure)
AnnaBridge	161:aa5281ff4a02	1681	\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
AnnaBridge	161:aa5281ff4a02	1682	\param [in] IRQn Device specific interrupt number.
AnnaBridge	161:aa5281ff4a02	1683	\return 0 Interrupt status is not active.
AnnaBridge	161:aa5281ff4a02	1684	\return 1 Interrupt status is active.
AnnaBridge	161:aa5281ff4a02	1685	\note IRQn must not be negative.
AnnaBridge	161:aa5281ff4a02	1686	*/
AnnaBridge	161:aa5281ff4a02	1687	__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
AnnaBridge	161:aa5281ff4a02	1688	{
AnnaBridge	161:aa5281ff4a02	1689	if ((int32_t)(IRQn) >= 0)
AnnaBridge	161:aa5281ff4a02	1690	{
Anna Bridge	169:a7c7b631e539	1691	return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	161:aa5281ff4a02	1692	}
AnnaBridge	161:aa5281ff4a02	1693	else
AnnaBridge	161:aa5281ff4a02	1694	{
AnnaBridge	161:aa5281ff4a02	1695	return(0U);
AnnaBridge	161:aa5281ff4a02	1696	}
AnnaBridge	161:aa5281ff4a02	1697	}
AnnaBridge	161:aa5281ff4a02	1698
AnnaBridge	161:aa5281ff4a02	1699
AnnaBridge	161:aa5281ff4a02	1700	/**
AnnaBridge	161:aa5281ff4a02	1701	\brief Set Interrupt Priority (non-secure)
AnnaBridge	161:aa5281ff4a02	1702	\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
AnnaBridge	161:aa5281ff4a02	1703	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	161:aa5281ff4a02	1704	or negative to specify a processor exception.
AnnaBridge	161:aa5281ff4a02	1705	\param [in] IRQn Interrupt number.
AnnaBridge	161:aa5281ff4a02	1706	\param [in] priority Priority to set.
AnnaBridge	161:aa5281ff4a02	1707	\note The priority cannot be set for every non-secure processor exception.
AnnaBridge	161:aa5281ff4a02	1708	*/
AnnaBridge	161:aa5281ff4a02	1709	__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
AnnaBridge	161:aa5281ff4a02	1710	{
AnnaBridge	161:aa5281ff4a02	1711	if ((int32_t)(IRQn) >= 0)
AnnaBridge	161:aa5281ff4a02	1712	{
AnnaBridge	161:aa5281ff4a02	1713	NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) \|
AnnaBridge	161:aa5281ff4a02	1714	(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge	161:aa5281ff4a02	1715	}
AnnaBridge	161:aa5281ff4a02	1716	else
AnnaBridge	161:aa5281ff4a02	1717	{
AnnaBridge	161:aa5281ff4a02	1718	SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) \|
AnnaBridge	161:aa5281ff4a02	1719	(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge	161:aa5281ff4a02	1720	}
AnnaBridge	161:aa5281ff4a02	1721	}
AnnaBridge	161:aa5281ff4a02	1722
AnnaBridge	161:aa5281ff4a02	1723
AnnaBridge	161:aa5281ff4a02	1724	/**
AnnaBridge	161:aa5281ff4a02	1725	\brief Get Interrupt Priority (non-secure)
AnnaBridge	161:aa5281ff4a02	1726	\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
AnnaBridge	161:aa5281ff4a02	1727	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	161:aa5281ff4a02	1728	or negative to specify a processor exception.
AnnaBridge	161:aa5281ff4a02	1729	\param [in] IRQn Interrupt number.
AnnaBridge	161:aa5281ff4a02	1730	\return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge	161:aa5281ff4a02	1731	*/
AnnaBridge	161:aa5281ff4a02	1732	__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
AnnaBridge	161:aa5281ff4a02	1733	{
AnnaBridge	161:aa5281ff4a02	1734
AnnaBridge	161:aa5281ff4a02	1735	if ((int32_t)(IRQn) >= 0)
AnnaBridge	161:aa5281ff4a02	1736	{
AnnaBridge	161:aa5281ff4a02	1737	return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge	161:aa5281ff4a02	1738	}
AnnaBridge	161:aa5281ff4a02	1739	else
AnnaBridge	161:aa5281ff4a02	1740	{
AnnaBridge	161:aa5281ff4a02	1741	return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge	161:aa5281ff4a02	1742	}
AnnaBridge	161:aa5281ff4a02	1743	}
AnnaBridge	161:aa5281ff4a02	1744	#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
AnnaBridge	161:aa5281ff4a02	1745
AnnaBridge	161:aa5281ff4a02	1746	/@} end of CMSIS_Core_NVICFunctions /
AnnaBridge	161:aa5281ff4a02	1747
AnnaBridge	161:aa5281ff4a02	1748	/* ########################## MPU functions #################################### */
AnnaBridge	161:aa5281ff4a02	1749
AnnaBridge	161:aa5281ff4a02	1750	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge	161:aa5281ff4a02	1751
AnnaBridge	161:aa5281ff4a02	1752	#include "mpu_armv8.h"
AnnaBridge	161:aa5281ff4a02	1753
AnnaBridge	161:aa5281ff4a02	1754	#endif
AnnaBridge	161:aa5281ff4a02	1755
AnnaBridge	161:aa5281ff4a02	1756	/* ########################## FPU functions #################################### */
AnnaBridge	161:aa5281ff4a02	1757	/**
AnnaBridge	161:aa5281ff4a02	1758	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	161:aa5281ff4a02	1759	\defgroup CMSIS_Core_FpuFunctions FPU Functions
AnnaBridge	161:aa5281ff4a02	1760	\brief Function that provides FPU type.
AnnaBridge	161:aa5281ff4a02	1761	@{
AnnaBridge	161:aa5281ff4a02	1762	*/
AnnaBridge	161:aa5281ff4a02	1763
AnnaBridge	161:aa5281ff4a02	1764	/**
AnnaBridge	161:aa5281ff4a02	1765	\brief get FPU type
AnnaBridge	161:aa5281ff4a02	1766	\details returns the FPU type
AnnaBridge	161:aa5281ff4a02	1767	\returns
AnnaBridge	161:aa5281ff4a02	1768	- \b 0: No FPU
AnnaBridge	161:aa5281ff4a02	1769	- \b 1: Single precision FPU
AnnaBridge	161:aa5281ff4a02	1770	- \b 2: Double + Single precision FPU
AnnaBridge	161:aa5281ff4a02	1771	*/
AnnaBridge	161:aa5281ff4a02	1772	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
AnnaBridge	161:aa5281ff4a02	1773	{
AnnaBridge	161:aa5281ff4a02	1774	return 0U; /* No FPU */
AnnaBridge	161:aa5281ff4a02	1775	}
AnnaBridge	161:aa5281ff4a02	1776
AnnaBridge	161:aa5281ff4a02	1777
AnnaBridge	161:aa5281ff4a02	1778	/@} end of CMSIS_Core_FpuFunctions /
AnnaBridge	161:aa5281ff4a02	1779
AnnaBridge	161:aa5281ff4a02	1780
AnnaBridge	161:aa5281ff4a02	1781
AnnaBridge	161:aa5281ff4a02	1782	/* ########################## SAU functions #################################### */
AnnaBridge	161:aa5281ff4a02	1783	/**
AnnaBridge	161:aa5281ff4a02	1784	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	161:aa5281ff4a02	1785	\defgroup CMSIS_Core_SAUFunctions SAU Functions
AnnaBridge	161:aa5281ff4a02	1786	\brief Functions that configure the SAU.
AnnaBridge	161:aa5281ff4a02	1787	@{
AnnaBridge	161:aa5281ff4a02	1788	*/
AnnaBridge	161:aa5281ff4a02	1789
AnnaBridge	161:aa5281ff4a02	1790	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	161:aa5281ff4a02	1791
AnnaBridge	161:aa5281ff4a02	1792	/**
AnnaBridge	161:aa5281ff4a02	1793	\brief Enable SAU
AnnaBridge	161:aa5281ff4a02	1794	\details Enables the Security Attribution Unit (SAU).
AnnaBridge	161:aa5281ff4a02	1795	*/
AnnaBridge	161:aa5281ff4a02	1796	__STATIC_INLINE void TZ_SAU_Enable(void)
AnnaBridge	161:aa5281ff4a02	1797	{
AnnaBridge	161:aa5281ff4a02	1798	SAU->CTRL \|= (SAU_CTRL_ENABLE_Msk);
AnnaBridge	161:aa5281ff4a02	1799	}
AnnaBridge	161:aa5281ff4a02	1800
AnnaBridge	161:aa5281ff4a02	1801
AnnaBridge	161:aa5281ff4a02	1802
AnnaBridge	161:aa5281ff4a02	1803	/**
AnnaBridge	161:aa5281ff4a02	1804	\brief Disable SAU
AnnaBridge	161:aa5281ff4a02	1805	\details Disables the Security Attribution Unit (SAU).
AnnaBridge	161:aa5281ff4a02	1806	*/
AnnaBridge	161:aa5281ff4a02	1807	__STATIC_INLINE void TZ_SAU_Disable(void)
AnnaBridge	161:aa5281ff4a02	1808	{
AnnaBridge	161:aa5281ff4a02	1809	SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
AnnaBridge	161:aa5281ff4a02	1810	}
AnnaBridge	161:aa5281ff4a02	1811
AnnaBridge	161:aa5281ff4a02	1812	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge	161:aa5281ff4a02	1813
AnnaBridge	161:aa5281ff4a02	1814	/@} end of CMSIS_Core_SAUFunctions /
AnnaBridge	161:aa5281ff4a02	1815
AnnaBridge	161:aa5281ff4a02	1816
AnnaBridge	161:aa5281ff4a02	1817
AnnaBridge	161:aa5281ff4a02	1818
AnnaBridge	161:aa5281ff4a02	1819	/* ################################## SysTick function ############################################ */
AnnaBridge	161:aa5281ff4a02	1820	/**
AnnaBridge	161:aa5281ff4a02	1821	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	161:aa5281ff4a02	1822	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge	161:aa5281ff4a02	1823	\brief Functions that configure the System.
AnnaBridge	161:aa5281ff4a02	1824	@{
AnnaBridge	161:aa5281ff4a02	1825	*/
AnnaBridge	161:aa5281ff4a02	1826
AnnaBridge	161:aa5281ff4a02	1827	#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
AnnaBridge	161:aa5281ff4a02	1828
AnnaBridge	161:aa5281ff4a02	1829	/**
AnnaBridge	161:aa5281ff4a02	1830	\brief System Tick Configuration
AnnaBridge	161:aa5281ff4a02	1831	\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge	161:aa5281ff4a02	1832	Counter is in free running mode to generate periodic interrupts.
AnnaBridge	161:aa5281ff4a02	1833	\param [in] ticks Number of ticks between two interrupts.
AnnaBridge	161:aa5281ff4a02	1834	\return 0 Function succeeded.
AnnaBridge	161:aa5281ff4a02	1835	\return 1 Function failed.
AnnaBridge	161:aa5281ff4a02	1836	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge	161:aa5281ff4a02	1837	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge	161:aa5281ff4a02	1838	must contain a vendor-specific implementation of this function.
AnnaBridge	161:aa5281ff4a02	1839	*/
AnnaBridge	161:aa5281ff4a02	1840	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
AnnaBridge	161:aa5281ff4a02	1841	{
AnnaBridge	161:aa5281ff4a02	1842	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge	161:aa5281ff4a02	1843	{
AnnaBridge	161:aa5281ff4a02	1844	return (1UL); /* Reload value impossible */
AnnaBridge	161:aa5281ff4a02	1845	}
AnnaBridge	161:aa5281ff4a02	1846
AnnaBridge	161:aa5281ff4a02	1847	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge	161:aa5281ff4a02	1848	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge	161:aa5281ff4a02	1849	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge	161:aa5281ff4a02	1850	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
AnnaBridge	161:aa5281ff4a02	1851	SysTick_CTRL_TICKINT_Msk \|
AnnaBridge	161:aa5281ff4a02	1852	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge	161:aa5281ff4a02	1853	return (0UL); /* Function successful */
AnnaBridge	161:aa5281ff4a02	1854	}
AnnaBridge	161:aa5281ff4a02	1855
AnnaBridge	161:aa5281ff4a02	1856	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	161:aa5281ff4a02	1857	/**
AnnaBridge	161:aa5281ff4a02	1858	\brief System Tick Configuration (non-secure)
AnnaBridge	161:aa5281ff4a02	1859	\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
AnnaBridge	161:aa5281ff4a02	1860	Counter is in free running mode to generate periodic interrupts.
AnnaBridge	161:aa5281ff4a02	1861	\param [in] ticks Number of ticks between two interrupts.
AnnaBridge	161:aa5281ff4a02	1862	\return 0 Function succeeded.
AnnaBridge	161:aa5281ff4a02	1863	\return 1 Function failed.
AnnaBridge	161:aa5281ff4a02	1864	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge	161:aa5281ff4a02	1865	function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge	161:aa5281ff4a02	1866	must contain a vendor-specific implementation of this function.
AnnaBridge	161:aa5281ff4a02	1867
AnnaBridge	161:aa5281ff4a02	1868	*/
AnnaBridge	161:aa5281ff4a02	1869	__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
AnnaBridge	161:aa5281ff4a02	1870	{
AnnaBridge	161:aa5281ff4a02	1871	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge	161:aa5281ff4a02	1872	{
AnnaBridge	161:aa5281ff4a02	1873	return (1UL); /* Reload value impossible */
AnnaBridge	161:aa5281ff4a02	1874	}
AnnaBridge	161:aa5281ff4a02	1875
AnnaBridge	161:aa5281ff4a02	1876	SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge	161:aa5281ff4a02	1877	TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge	161:aa5281ff4a02	1878	SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge	161:aa5281ff4a02	1879	SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
AnnaBridge	161:aa5281ff4a02	1880	SysTick_CTRL_TICKINT_Msk \|
AnnaBridge	161:aa5281ff4a02	1881	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge	161:aa5281ff4a02	1882	return (0UL); /* Function successful */
AnnaBridge	161:aa5281ff4a02	1883	}
AnnaBridge	161:aa5281ff4a02	1884	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge	161:aa5281ff4a02	1885
AnnaBridge	161:aa5281ff4a02	1886	#endif
AnnaBridge	161:aa5281ff4a02	1887
AnnaBridge	161:aa5281ff4a02	1888	/@} end of CMSIS_Core_SysTickFunctions /
AnnaBridge	161:aa5281ff4a02	1889
AnnaBridge	161:aa5281ff4a02	1890
AnnaBridge	161:aa5281ff4a02	1891
AnnaBridge	161:aa5281ff4a02	1892
AnnaBridge	161:aa5281ff4a02	1893	#ifdef __cplusplus
AnnaBridge	161:aa5281ff4a02	1894	}
AnnaBridge	161:aa5281ff4a02	1895	#endif
AnnaBridge	161:aa5281ff4a02	1896
AnnaBridge	161:aa5281ff4a02	1897	#endif /* __CORE_CM23_H_DEPENDANT */
AnnaBridge	161:aa5281ff4a02	1898
AnnaBridge	161:aa5281ff4a02	1899	#endif /* __CMSIS_GENERIC */