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TARGET_SAKURAIO_EVB_01/core_cm33.h@170:e95d10626187, 2018-09-06 (annotated)

Committer:: AnnaBridge
Date:: Thu Sep 06 13:39:34 2018 +0100
Revision:: 170:e95d10626187
Parent:: 169:a7c7b631e539

mbed library. Release version 163

Who changed what in which revision?

User	Revision	Line number	New contents of line
Anna Bridge	160:5571c4ff569f	1	/************************************************************************//
Anna Bridge	160:5571c4ff569f	2	* @file core_cm33.h
Anna Bridge	160:5571c4ff569f	3	* @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File
Anna Bridge	169:a7c7b631e539	4	* @version V5.0.5
Anna Bridge	169:a7c7b631e539	5	* @date 08. January 2018
Anna Bridge	160:5571c4ff569f	6	******************************************************************************/
Anna Bridge	160:5571c4ff569f	7	/*
Anna Bridge	160:5571c4ff569f	8	* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
Anna Bridge	160:5571c4ff569f	9	*
Anna Bridge	160:5571c4ff569f	10	* SPDX-License-Identifier: Apache-2.0
Anna Bridge	160:5571c4ff569f	11	*
Anna Bridge	160:5571c4ff569f	12	* Licensed under the Apache License, Version 2.0 (the License); you may
Anna Bridge	160:5571c4ff569f	13	* not use this file except in compliance with the License.
Anna Bridge	160:5571c4ff569f	14	* You may obtain a copy of the License at
Anna Bridge	160:5571c4ff569f	15	*
Anna Bridge	160:5571c4ff569f	16	* www.apache.org/licenses/LICENSE-2.0
Anna Bridge	160:5571c4ff569f	17	*
Anna Bridge	160:5571c4ff569f	18	* Unless required by applicable law or agreed to in writing, software
Anna Bridge	160:5571c4ff569f	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
Anna Bridge	160:5571c4ff569f	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Anna Bridge	160:5571c4ff569f	21	* See the License for the specific language governing permissions and
Anna Bridge	160:5571c4ff569f	22	* limitations under the License.
Anna Bridge	160:5571c4ff569f	23	*/
Anna Bridge	160:5571c4ff569f	24
Anna Bridge	160:5571c4ff569f	25	#if defined ( __ICCARM__ )
Anna Bridge	169:a7c7b631e539	26	#pragma system_include /* treat file as system include file for MISRA check */
Anna Bridge	169:a7c7b631e539	27	#elif defined (__clang__)
Anna Bridge	160:5571c4ff569f	28	#pragma clang system_header /* treat file as system include file */
Anna Bridge	160:5571c4ff569f	29	#endif
Anna Bridge	160:5571c4ff569f	30
Anna Bridge	160:5571c4ff569f	31	#ifndef __CORE_CM33_H_GENERIC
Anna Bridge	160:5571c4ff569f	32	#define __CORE_CM33_H_GENERIC
Anna Bridge	160:5571c4ff569f	33
Anna Bridge	160:5571c4ff569f	34	#include <stdint.h>
Anna Bridge	160:5571c4ff569f	35
Anna Bridge	160:5571c4ff569f	36	#ifdef __cplusplus
Anna Bridge	160:5571c4ff569f	37	extern "C" {
Anna Bridge	160:5571c4ff569f	38	#endif
Anna Bridge	160:5571c4ff569f	39
Anna Bridge	160:5571c4ff569f	40	/**
Anna Bridge	160:5571c4ff569f	41	\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Anna Bridge	160:5571c4ff569f	42	CMSIS violates the following MISRA-C:2004 rules:
Anna Bridge	160:5571c4ff569f	43
Anna Bridge	160:5571c4ff569f	44	\li Required Rule 8.5, object/function definition in header file.<br>
Anna Bridge	160:5571c4ff569f	45	Function definitions in header files are used to allow 'inlining'.
Anna Bridge	160:5571c4ff569f	46
Anna Bridge	160:5571c4ff569f	47	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Anna Bridge	160:5571c4ff569f	48	Unions are used for effective representation of core registers.
Anna Bridge	160:5571c4ff569f	49
Anna Bridge	160:5571c4ff569f	50	\li Advisory Rule 19.7, Function-like macro defined.<br>
Anna Bridge	160:5571c4ff569f	51	Function-like macros are used to allow more efficient code.
Anna Bridge	160:5571c4ff569f	52	*/
Anna Bridge	160:5571c4ff569f	53
Anna Bridge	160:5571c4ff569f	54
Anna Bridge	160:5571c4ff569f	55	/*******************************************************************************
Anna Bridge	160:5571c4ff569f	56	* CMSIS definitions
Anna Bridge	160:5571c4ff569f	57	******************************************************************************/
Anna Bridge	160:5571c4ff569f	58	/**
Anna Bridge	160:5571c4ff569f	59	\ingroup Cortex_M33
Anna Bridge	160:5571c4ff569f	60	@{
Anna Bridge	160:5571c4ff569f	61	*/
Anna Bridge	160:5571c4ff569f	62
Anna Bridge	160:5571c4ff569f	63	#include "cmsis_version.h"
Anna Bridge	160:5571c4ff569f	64
Anna Bridge	160:5571c4ff569f	65	/* CMSIS CM33 definitions */
Anna Bridge	160:5571c4ff569f	66	#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /!< \deprecated [31:16] CMSIS HAL main version /
Anna Bridge	160:5571c4ff569f	67	#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /!< \deprecated [15:0] CMSIS HAL sub version /
Anna Bridge	160:5571c4ff569f	68	#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) \| \
Anna Bridge	160:5571c4ff569f	69	__CM33_CMSIS_VERSION_SUB ) /!< \deprecated CMSIS HAL version number /
Anna Bridge	160:5571c4ff569f	70
Anna Bridge	160:5571c4ff569f	71	#define __CORTEX_M (33U) /!< Cortex-M Core /
Anna Bridge	160:5571c4ff569f	72
Anna Bridge	160:5571c4ff569f	73	/** __FPU_USED indicates whether an FPU is used or not.
Anna Bridge	160:5571c4ff569f	74	For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
Anna Bridge	160:5571c4ff569f	75	*/
Anna Bridge	160:5571c4ff569f	76	#if defined ( __CC_ARM )
Anna Bridge	169:a7c7b631e539	77	#if defined (__TARGET_FPU_VFP)
Anna Bridge	160:5571c4ff569f	78	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
Anna Bridge	160:5571c4ff569f	79	#define __FPU_USED 1U
Anna Bridge	160:5571c4ff569f	80	#else
Anna Bridge	160:5571c4ff569f	81	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge	160:5571c4ff569f	82	#define __FPU_USED 0U
Anna Bridge	160:5571c4ff569f	83	#endif
Anna Bridge	160:5571c4ff569f	84	#else
Anna Bridge	160:5571c4ff569f	85	#define __FPU_USED 0U
Anna Bridge	160:5571c4ff569f	86	#endif
Anna Bridge	160:5571c4ff569f	87
Anna Bridge	169:a7c7b631e539	88	#if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
Anna Bridge	169:a7c7b631e539	89	#if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
Anna Bridge	160:5571c4ff569f	90	#define __DSP_USED 1U
Anna Bridge	160:5571c4ff569f	91	#else
Anna Bridge	160:5571c4ff569f	92	#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
Anna Bridge	160:5571c4ff569f	93	#define __DSP_USED 0U
Anna Bridge	160:5571c4ff569f	94	#endif
Anna Bridge	160:5571c4ff569f	95	#else
Anna Bridge	160:5571c4ff569f	96	#define __DSP_USED 0U
Anna Bridge	160:5571c4ff569f	97	#endif
Anna Bridge	160:5571c4ff569f	98
Anna Bridge	160:5571c4ff569f	99	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
Anna Bridge	169:a7c7b631e539	100	#if defined (__ARM_PCS_VFP)
Anna Bridge	160:5571c4ff569f	101	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
Anna Bridge	160:5571c4ff569f	102	#define __FPU_USED 1U
Anna Bridge	160:5571c4ff569f	103	#else
Anna Bridge	160:5571c4ff569f	104	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge	160:5571c4ff569f	105	#define __FPU_USED 0U
Anna Bridge	160:5571c4ff569f	106	#endif
Anna Bridge	160:5571c4ff569f	107	#else
Anna Bridge	160:5571c4ff569f	108	#define __FPU_USED 0U
Anna Bridge	160:5571c4ff569f	109	#endif
Anna Bridge	160:5571c4ff569f	110
Anna Bridge	169:a7c7b631e539	111	#if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
Anna Bridge	169:a7c7b631e539	112	#if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
Anna Bridge	160:5571c4ff569f	113	#define __DSP_USED 1U
Anna Bridge	160:5571c4ff569f	114	#else
Anna Bridge	160:5571c4ff569f	115	#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
Anna Bridge	160:5571c4ff569f	116	#define __DSP_USED 0U
Anna Bridge	160:5571c4ff569f	117	#endif
Anna Bridge	160:5571c4ff569f	118	#else
Anna Bridge	160:5571c4ff569f	119	#define __DSP_USED 0U
Anna Bridge	160:5571c4ff569f	120	#endif
Anna Bridge	160:5571c4ff569f	121
Anna Bridge	160:5571c4ff569f	122	#elif defined ( __GNUC__ )
Anna Bridge	160:5571c4ff569f	123	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
Anna Bridge	160:5571c4ff569f	124	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
Anna Bridge	160:5571c4ff569f	125	#define __FPU_USED 1U
Anna Bridge	160:5571c4ff569f	126	#else
Anna Bridge	160:5571c4ff569f	127	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge	160:5571c4ff569f	128	#define __FPU_USED 0U
Anna Bridge	160:5571c4ff569f	129	#endif
Anna Bridge	160:5571c4ff569f	130	#else
Anna Bridge	160:5571c4ff569f	131	#define __FPU_USED 0U
Anna Bridge	160:5571c4ff569f	132	#endif
Anna Bridge	160:5571c4ff569f	133
Anna Bridge	169:a7c7b631e539	134	#if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
Anna Bridge	169:a7c7b631e539	135	#if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
Anna Bridge	160:5571c4ff569f	136	#define __DSP_USED 1U
Anna Bridge	160:5571c4ff569f	137	#else
Anna Bridge	160:5571c4ff569f	138	#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
Anna Bridge	160:5571c4ff569f	139	#define __DSP_USED 0U
Anna Bridge	160:5571c4ff569f	140	#endif
Anna Bridge	160:5571c4ff569f	141	#else
Anna Bridge	160:5571c4ff569f	142	#define __DSP_USED 0U
Anna Bridge	160:5571c4ff569f	143	#endif
Anna Bridge	160:5571c4ff569f	144
Anna Bridge	160:5571c4ff569f	145	#elif defined ( __ICCARM__ )
Anna Bridge	169:a7c7b631e539	146	#if defined (__ARMVFP__)
Anna Bridge	160:5571c4ff569f	147	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
Anna Bridge	160:5571c4ff569f	148	#define __FPU_USED 1U
Anna Bridge	160:5571c4ff569f	149	#else
Anna Bridge	160:5571c4ff569f	150	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge	160:5571c4ff569f	151	#define __FPU_USED 0U
Anna Bridge	160:5571c4ff569f	152	#endif
Anna Bridge	160:5571c4ff569f	153	#else
Anna Bridge	160:5571c4ff569f	154	#define __FPU_USED 0U
Anna Bridge	160:5571c4ff569f	155	#endif
Anna Bridge	160:5571c4ff569f	156
Anna Bridge	169:a7c7b631e539	157	#if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
Anna Bridge	169:a7c7b631e539	158	#if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
Anna Bridge	160:5571c4ff569f	159	#define __DSP_USED 1U
Anna Bridge	160:5571c4ff569f	160	#else
Anna Bridge	160:5571c4ff569f	161	#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
Anna Bridge	160:5571c4ff569f	162	#define __DSP_USED 0U
Anna Bridge	160:5571c4ff569f	163	#endif
Anna Bridge	160:5571c4ff569f	164	#else
Anna Bridge	160:5571c4ff569f	165	#define __DSP_USED 0U
Anna Bridge	160:5571c4ff569f	166	#endif
Anna Bridge	160:5571c4ff569f	167
Anna Bridge	160:5571c4ff569f	168	#elif defined ( __TI_ARM__ )
Anna Bridge	169:a7c7b631e539	169	#if defined (__TI_VFP_SUPPORT__)
Anna Bridge	160:5571c4ff569f	170	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
Anna Bridge	160:5571c4ff569f	171	#define __FPU_USED 1U
Anna Bridge	160:5571c4ff569f	172	#else
Anna Bridge	160:5571c4ff569f	173	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge	160:5571c4ff569f	174	#define __FPU_USED 0U
Anna Bridge	160:5571c4ff569f	175	#endif
Anna Bridge	160:5571c4ff569f	176	#else
Anna Bridge	160:5571c4ff569f	177	#define __FPU_USED 0U
Anna Bridge	160:5571c4ff569f	178	#endif
Anna Bridge	160:5571c4ff569f	179
Anna Bridge	160:5571c4ff569f	180	#elif defined ( __TASKING__ )
Anna Bridge	169:a7c7b631e539	181	#if defined (__FPU_VFP__)
Anna Bridge	160:5571c4ff569f	182	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
Anna Bridge	160:5571c4ff569f	183	#define __FPU_USED 1U
Anna Bridge	160:5571c4ff569f	184	#else
Anna Bridge	160:5571c4ff569f	185	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge	160:5571c4ff569f	186	#define __FPU_USED 0U
Anna Bridge	160:5571c4ff569f	187	#endif
Anna Bridge	160:5571c4ff569f	188	#else
Anna Bridge	160:5571c4ff569f	189	#define __FPU_USED 0U
Anna Bridge	160:5571c4ff569f	190	#endif
Anna Bridge	160:5571c4ff569f	191
Anna Bridge	160:5571c4ff569f	192	#elif defined ( __CSMC__ )
Anna Bridge	160:5571c4ff569f	193	#if ( __CSMC__ & 0x400U)
Anna Bridge	160:5571c4ff569f	194	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
Anna Bridge	160:5571c4ff569f	195	#define __FPU_USED 1U
Anna Bridge	160:5571c4ff569f	196	#else
Anna Bridge	160:5571c4ff569f	197	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge	160:5571c4ff569f	198	#define __FPU_USED 0U
Anna Bridge	160:5571c4ff569f	199	#endif
Anna Bridge	160:5571c4ff569f	200	#else
Anna Bridge	160:5571c4ff569f	201	#define __FPU_USED 0U
Anna Bridge	160:5571c4ff569f	202	#endif
Anna Bridge	160:5571c4ff569f	203
Anna Bridge	160:5571c4ff569f	204	#endif
Anna Bridge	160:5571c4ff569f	205
Anna Bridge	160:5571c4ff569f	206	#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
Anna Bridge	160:5571c4ff569f	207
Anna Bridge	160:5571c4ff569f	208
Anna Bridge	160:5571c4ff569f	209	#ifdef __cplusplus
Anna Bridge	160:5571c4ff569f	210	}
Anna Bridge	160:5571c4ff569f	211	#endif
Anna Bridge	160:5571c4ff569f	212
Anna Bridge	160:5571c4ff569f	213	#endif /* __CORE_CM33_H_GENERIC */
Anna Bridge	160:5571c4ff569f	214
Anna Bridge	160:5571c4ff569f	215	#ifndef __CMSIS_GENERIC
Anna Bridge	160:5571c4ff569f	216
Anna Bridge	160:5571c4ff569f	217	#ifndef __CORE_CM33_H_DEPENDANT
Anna Bridge	160:5571c4ff569f	218	#define __CORE_CM33_H_DEPENDANT
Anna Bridge	160:5571c4ff569f	219
Anna Bridge	160:5571c4ff569f	220	#ifdef __cplusplus
Anna Bridge	160:5571c4ff569f	221	extern "C" {
Anna Bridge	160:5571c4ff569f	222	#endif
Anna Bridge	160:5571c4ff569f	223
Anna Bridge	160:5571c4ff569f	224	/* check device defines and use defaults */
Anna Bridge	160:5571c4ff569f	225	#if defined __CHECK_DEVICE_DEFINES
Anna Bridge	160:5571c4ff569f	226	#ifndef __CM33_REV
Anna Bridge	160:5571c4ff569f	227	#define __CM33_REV 0x0000U
Anna Bridge	160:5571c4ff569f	228	#warning "__CM33_REV not defined in device header file; using default!"
Anna Bridge	160:5571c4ff569f	229	#endif
Anna Bridge	160:5571c4ff569f	230
Anna Bridge	160:5571c4ff569f	231	#ifndef __FPU_PRESENT
Anna Bridge	160:5571c4ff569f	232	#define __FPU_PRESENT 0U
Anna Bridge	160:5571c4ff569f	233	#warning "__FPU_PRESENT not defined in device header file; using default!"
Anna Bridge	160:5571c4ff569f	234	#endif
Anna Bridge	160:5571c4ff569f	235
Anna Bridge	160:5571c4ff569f	236	#ifndef __MPU_PRESENT
Anna Bridge	160:5571c4ff569f	237	#define __MPU_PRESENT 0U
Anna Bridge	160:5571c4ff569f	238	#warning "__MPU_PRESENT not defined in device header file; using default!"
Anna Bridge	160:5571c4ff569f	239	#endif
Anna Bridge	160:5571c4ff569f	240
Anna Bridge	160:5571c4ff569f	241	#ifndef __SAUREGION_PRESENT
Anna Bridge	160:5571c4ff569f	242	#define __SAUREGION_PRESENT 0U
Anna Bridge	160:5571c4ff569f	243	#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
Anna Bridge	160:5571c4ff569f	244	#endif
Anna Bridge	160:5571c4ff569f	245
Anna Bridge	160:5571c4ff569f	246	#ifndef __DSP_PRESENT
Anna Bridge	160:5571c4ff569f	247	#define __DSP_PRESENT 0U
Anna Bridge	160:5571c4ff569f	248	#warning "__DSP_PRESENT not defined in device header file; using default!"
Anna Bridge	160:5571c4ff569f	249	#endif
Anna Bridge	160:5571c4ff569f	250
Anna Bridge	160:5571c4ff569f	251	#ifndef __NVIC_PRIO_BITS
Anna Bridge	160:5571c4ff569f	252	#define __NVIC_PRIO_BITS 3U
Anna Bridge	160:5571c4ff569f	253	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Anna Bridge	160:5571c4ff569f	254	#endif
Anna Bridge	160:5571c4ff569f	255
Anna Bridge	160:5571c4ff569f	256	#ifndef __Vendor_SysTickConfig
Anna Bridge	160:5571c4ff569f	257	#define __Vendor_SysTickConfig 0U
Anna Bridge	160:5571c4ff569f	258	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Anna Bridge	160:5571c4ff569f	259	#endif
Anna Bridge	160:5571c4ff569f	260	#endif
Anna Bridge	160:5571c4ff569f	261
Anna Bridge	160:5571c4ff569f	262	/* IO definitions (access restrictions to peripheral registers) */
Anna Bridge	160:5571c4ff569f	263	/**
Anna Bridge	160:5571c4ff569f	264	\defgroup CMSIS_glob_defs CMSIS Global Defines
Anna Bridge	160:5571c4ff569f	265
Anna Bridge	160:5571c4ff569f	266	<strong>IO Type Qualifiers</strong> are used
Anna Bridge	160:5571c4ff569f	267	\li to specify the access to peripheral variables.
Anna Bridge	160:5571c4ff569f	268	\li for automatic generation of peripheral register debug information.
Anna Bridge	160:5571c4ff569f	269	*/
Anna Bridge	160:5571c4ff569f	270	#ifdef __cplusplus
Anna Bridge	160:5571c4ff569f	271	#define __I volatile /!< Defines 'read only' permissions /
Anna Bridge	160:5571c4ff569f	272	#else
Anna Bridge	160:5571c4ff569f	273	#define __I volatile const /!< Defines 'read only' permissions /
Anna Bridge	160:5571c4ff569f	274	#endif
Anna Bridge	160:5571c4ff569f	275	#define __O volatile /!< Defines 'write only' permissions /
Anna Bridge	160:5571c4ff569f	276	#define __IO volatile /!< Defines 'read / write' permissions /
Anna Bridge	160:5571c4ff569f	277
Anna Bridge	160:5571c4ff569f	278	/* following defines should be used for structure members */
Anna Bridge	160:5571c4ff569f	279	#define __IM volatile const /! Defines 'read only' structure member permissions /
Anna Bridge	160:5571c4ff569f	280	#define __OM volatile /! Defines 'write only' structure member permissions /
Anna Bridge	160:5571c4ff569f	281	#define __IOM volatile /! Defines 'read / write' structure member permissions /
Anna Bridge	160:5571c4ff569f	282
Anna Bridge	160:5571c4ff569f	283	/@} end of group Cortex_M33 /
Anna Bridge	160:5571c4ff569f	284
Anna Bridge	160:5571c4ff569f	285
Anna Bridge	160:5571c4ff569f	286
Anna Bridge	160:5571c4ff569f	287	/*******************************************************************************
Anna Bridge	160:5571c4ff569f	288	* Register Abstraction
Anna Bridge	160:5571c4ff569f	289	Core Register contain:
Anna Bridge	160:5571c4ff569f	290	- Core Register
Anna Bridge	160:5571c4ff569f	291	- Core NVIC Register
Anna Bridge	160:5571c4ff569f	292	- Core SCB Register
Anna Bridge	160:5571c4ff569f	293	- Core SysTick Register
Anna Bridge	160:5571c4ff569f	294	- Core Debug Register
Anna Bridge	160:5571c4ff569f	295	- Core MPU Register
Anna Bridge	160:5571c4ff569f	296	- Core SAU Register
Anna Bridge	160:5571c4ff569f	297	- Core FPU Register
Anna Bridge	160:5571c4ff569f	298	******************************************************************************/
Anna Bridge	160:5571c4ff569f	299	/**
Anna Bridge	160:5571c4ff569f	300	\defgroup CMSIS_core_register Defines and Type Definitions
Anna Bridge	160:5571c4ff569f	301	\brief Type definitions and defines for Cortex-M processor based devices.
Anna Bridge	160:5571c4ff569f	302	*/
Anna Bridge	160:5571c4ff569f	303
Anna Bridge	160:5571c4ff569f	304	/**
Anna Bridge	160:5571c4ff569f	305	\ingroup CMSIS_core_register
Anna Bridge	160:5571c4ff569f	306	\defgroup CMSIS_CORE Status and Control Registers
Anna Bridge	160:5571c4ff569f	307	\brief Core Register type definitions.
Anna Bridge	160:5571c4ff569f	308	@{
Anna Bridge	160:5571c4ff569f	309	*/
Anna Bridge	160:5571c4ff569f	310
Anna Bridge	160:5571c4ff569f	311	/**
Anna Bridge	160:5571c4ff569f	312	\brief Union type to access the Application Program Status Register (APSR).
Anna Bridge	160:5571c4ff569f	313	*/
Anna Bridge	160:5571c4ff569f	314	typedef union
Anna Bridge	160:5571c4ff569f	315	{
Anna Bridge	160:5571c4ff569f	316	struct
Anna Bridge	160:5571c4ff569f	317	{
Anna Bridge	160:5571c4ff569f	318	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
Anna Bridge	160:5571c4ff569f	319	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
Anna Bridge	160:5571c4ff569f	320	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
Anna Bridge	160:5571c4ff569f	321	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
Anna Bridge	160:5571c4ff569f	322	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
Anna Bridge	160:5571c4ff569f	323	uint32_t C:1; /!< bit: 29 Carry condition code flag /
Anna Bridge	160:5571c4ff569f	324	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
Anna Bridge	160:5571c4ff569f	325	uint32_t N:1; /!< bit: 31 Negative condition code flag /
Anna Bridge	160:5571c4ff569f	326	} b; /!< Structure used for bit access /
Anna Bridge	160:5571c4ff569f	327	uint32_t w; /!< Type used for word access /
Anna Bridge	160:5571c4ff569f	328	} APSR_Type;
Anna Bridge	160:5571c4ff569f	329
Anna Bridge	160:5571c4ff569f	330	/* APSR Register Definitions */
Anna Bridge	160:5571c4ff569f	331	#define APSR_N_Pos 31U /!< APSR: N Position /
Anna Bridge	160:5571c4ff569f	332	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
Anna Bridge	160:5571c4ff569f	333
Anna Bridge	160:5571c4ff569f	334	#define APSR_Z_Pos 30U /!< APSR: Z Position /
Anna Bridge	160:5571c4ff569f	335	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
Anna Bridge	160:5571c4ff569f	336
Anna Bridge	160:5571c4ff569f	337	#define APSR_C_Pos 29U /!< APSR: C Position /
Anna Bridge	160:5571c4ff569f	338	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
Anna Bridge	160:5571c4ff569f	339
Anna Bridge	160:5571c4ff569f	340	#define APSR_V_Pos 28U /!< APSR: V Position /
Anna Bridge	160:5571c4ff569f	341	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
Anna Bridge	160:5571c4ff569f	342
Anna Bridge	160:5571c4ff569f	343	#define APSR_Q_Pos 27U /!< APSR: Q Position /
Anna Bridge	160:5571c4ff569f	344	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
Anna Bridge	160:5571c4ff569f	345
Anna Bridge	160:5571c4ff569f	346	#define APSR_GE_Pos 16U /!< APSR: GE Position /
Anna Bridge	160:5571c4ff569f	347	#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /!< APSR: GE Mask /
Anna Bridge	160:5571c4ff569f	348
Anna Bridge	160:5571c4ff569f	349
Anna Bridge	160:5571c4ff569f	350	/**
Anna Bridge	160:5571c4ff569f	351	\brief Union type to access the Interrupt Program Status Register (IPSR).
Anna Bridge	160:5571c4ff569f	352	*/
Anna Bridge	160:5571c4ff569f	353	typedef union
Anna Bridge	160:5571c4ff569f	354	{
Anna Bridge	160:5571c4ff569f	355	struct
Anna Bridge	160:5571c4ff569f	356	{
Anna Bridge	160:5571c4ff569f	357	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
Anna Bridge	160:5571c4ff569f	358	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
Anna Bridge	160:5571c4ff569f	359	} b; /!< Structure used for bit access /
Anna Bridge	160:5571c4ff569f	360	uint32_t w; /!< Type used for word access /
Anna Bridge	160:5571c4ff569f	361	} IPSR_Type;
Anna Bridge	160:5571c4ff569f	362
Anna Bridge	160:5571c4ff569f	363	/* IPSR Register Definitions */
Anna Bridge	160:5571c4ff569f	364	#define IPSR_ISR_Pos 0U /!< IPSR: ISR Position /
Anna Bridge	160:5571c4ff569f	365	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
Anna Bridge	160:5571c4ff569f	366
Anna Bridge	160:5571c4ff569f	367
Anna Bridge	160:5571c4ff569f	368	/**
Anna Bridge	160:5571c4ff569f	369	\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Anna Bridge	160:5571c4ff569f	370	*/
Anna Bridge	160:5571c4ff569f	371	typedef union
Anna Bridge	160:5571c4ff569f	372	{
Anna Bridge	160:5571c4ff569f	373	struct
Anna Bridge	160:5571c4ff569f	374	{
Anna Bridge	160:5571c4ff569f	375	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
Anna Bridge	160:5571c4ff569f	376	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
Anna Bridge	160:5571c4ff569f	377	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
Anna Bridge	160:5571c4ff569f	378	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
Anna Bridge	160:5571c4ff569f	379	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
Anna Bridge	160:5571c4ff569f	380	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
Anna Bridge	160:5571c4ff569f	381	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
Anna Bridge	160:5571c4ff569f	382	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
Anna Bridge	160:5571c4ff569f	383	uint32_t C:1; /!< bit: 29 Carry condition code flag /
Anna Bridge	160:5571c4ff569f	384	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
Anna Bridge	160:5571c4ff569f	385	uint32_t N:1; /!< bit: 31 Negative condition code flag /
Anna Bridge	160:5571c4ff569f	386	} b; /!< Structure used for bit access /
Anna Bridge	160:5571c4ff569f	387	uint32_t w; /!< Type used for word access /
Anna Bridge	160:5571c4ff569f	388	} xPSR_Type;
Anna Bridge	160:5571c4ff569f	389
Anna Bridge	160:5571c4ff569f	390	/* xPSR Register Definitions */
Anna Bridge	160:5571c4ff569f	391	#define xPSR_N_Pos 31U /!< xPSR: N Position /
Anna Bridge	160:5571c4ff569f	392	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
Anna Bridge	160:5571c4ff569f	393
Anna Bridge	160:5571c4ff569f	394	#define xPSR_Z_Pos 30U /!< xPSR: Z Position /
Anna Bridge	160:5571c4ff569f	395	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
Anna Bridge	160:5571c4ff569f	396
Anna Bridge	160:5571c4ff569f	397	#define xPSR_C_Pos 29U /!< xPSR: C Position /
Anna Bridge	160:5571c4ff569f	398	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
Anna Bridge	160:5571c4ff569f	399
Anna Bridge	160:5571c4ff569f	400	#define xPSR_V_Pos 28U /!< xPSR: V Position /
Anna Bridge	160:5571c4ff569f	401	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
Anna Bridge	160:5571c4ff569f	402
Anna Bridge	160:5571c4ff569f	403	#define xPSR_Q_Pos 27U /!< xPSR: Q Position /
Anna Bridge	160:5571c4ff569f	404	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
Anna Bridge	160:5571c4ff569f	405
Anna Bridge	160:5571c4ff569f	406	#define xPSR_IT_Pos 25U /!< xPSR: IT Position /
Anna Bridge	160:5571c4ff569f	407	#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /!< xPSR: IT Mask /
Anna Bridge	160:5571c4ff569f	408
Anna Bridge	160:5571c4ff569f	409	#define xPSR_T_Pos 24U /!< xPSR: T Position /
Anna Bridge	160:5571c4ff569f	410	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
Anna Bridge	160:5571c4ff569f	411
Anna Bridge	160:5571c4ff569f	412	#define xPSR_GE_Pos 16U /!< xPSR: GE Position /
Anna Bridge	160:5571c4ff569f	413	#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /!< xPSR: GE Mask /
Anna Bridge	160:5571c4ff569f	414
Anna Bridge	160:5571c4ff569f	415	#define xPSR_ISR_Pos 0U /!< xPSR: ISR Position /
Anna Bridge	160:5571c4ff569f	416	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
Anna Bridge	160:5571c4ff569f	417
Anna Bridge	160:5571c4ff569f	418
Anna Bridge	160:5571c4ff569f	419	/**
Anna Bridge	160:5571c4ff569f	420	\brief Union type to access the Control Registers (CONTROL).
Anna Bridge	160:5571c4ff569f	421	*/
Anna Bridge	160:5571c4ff569f	422	typedef union
Anna Bridge	160:5571c4ff569f	423	{
Anna Bridge	160:5571c4ff569f	424	struct
Anna Bridge	160:5571c4ff569f	425	{
Anna Bridge	160:5571c4ff569f	426	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
Anna Bridge	160:5571c4ff569f	427	uint32_t SPSEL:1; /!< bit: 1 Stack-pointer select /
Anna Bridge	160:5571c4ff569f	428	uint32_t FPCA:1; /!< bit: 2 Floating-point context active /
Anna Bridge	160:5571c4ff569f	429	uint32_t SFPA:1; /!< bit: 3 Secure floating-point active /
Anna Bridge	160:5571c4ff569f	430	uint32_t _reserved1:28; /!< bit: 4..31 Reserved /
Anna Bridge	160:5571c4ff569f	431	} b; /!< Structure used for bit access /
Anna Bridge	160:5571c4ff569f	432	uint32_t w; /!< Type used for word access /
Anna Bridge	160:5571c4ff569f	433	} CONTROL_Type;
Anna Bridge	160:5571c4ff569f	434
Anna Bridge	160:5571c4ff569f	435	/* CONTROL Register Definitions */
Anna Bridge	160:5571c4ff569f	436	#define CONTROL_SFPA_Pos 3U /!< CONTROL: SFPA Position /
Anna Bridge	160:5571c4ff569f	437	#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /!< CONTROL: SFPA Mask /
Anna Bridge	160:5571c4ff569f	438
Anna Bridge	160:5571c4ff569f	439	#define CONTROL_FPCA_Pos 2U /!< CONTROL: FPCA Position /
Anna Bridge	160:5571c4ff569f	440	#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /!< CONTROL: FPCA Mask /
Anna Bridge	160:5571c4ff569f	441
Anna Bridge	160:5571c4ff569f	442	#define CONTROL_SPSEL_Pos 1U /!< CONTROL: SPSEL Position /
Anna Bridge	160:5571c4ff569f	443	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
Anna Bridge	160:5571c4ff569f	444
Anna Bridge	160:5571c4ff569f	445	#define CONTROL_nPRIV_Pos 0U /!< CONTROL: nPRIV Position /
Anna Bridge	160:5571c4ff569f	446	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
Anna Bridge	160:5571c4ff569f	447
Anna Bridge	160:5571c4ff569f	448	/@} end of group CMSIS_CORE /
Anna Bridge	160:5571c4ff569f	449
Anna Bridge	160:5571c4ff569f	450
Anna Bridge	160:5571c4ff569f	451	/**
Anna Bridge	160:5571c4ff569f	452	\ingroup CMSIS_core_register
Anna Bridge	160:5571c4ff569f	453	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Anna Bridge	160:5571c4ff569f	454	\brief Type definitions for the NVIC Registers
Anna Bridge	160:5571c4ff569f	455	@{
Anna Bridge	160:5571c4ff569f	456	*/
Anna Bridge	160:5571c4ff569f	457
Anna Bridge	160:5571c4ff569f	458	/**
Anna Bridge	160:5571c4ff569f	459	\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Anna Bridge	160:5571c4ff569f	460	*/
Anna Bridge	160:5571c4ff569f	461	typedef struct
Anna Bridge	160:5571c4ff569f	462	{
Anna Bridge	160:5571c4ff569f	463	__IOM uint32_t ISER[16U]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
Anna Bridge	160:5571c4ff569f	464	uint32_t RESERVED0[16U];
Anna Bridge	160:5571c4ff569f	465	__IOM uint32_t ICER[16U]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
Anna Bridge	160:5571c4ff569f	466	uint32_t RSERVED1[16U];
Anna Bridge	160:5571c4ff569f	467	__IOM uint32_t ISPR[16U]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
Anna Bridge	160:5571c4ff569f	468	uint32_t RESERVED2[16U];
Anna Bridge	160:5571c4ff569f	469	__IOM uint32_t ICPR[16U]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
Anna Bridge	160:5571c4ff569f	470	uint32_t RESERVED3[16U];
Anna Bridge	160:5571c4ff569f	471	__IOM uint32_t IABR[16U]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
Anna Bridge	160:5571c4ff569f	472	uint32_t RESERVED4[16U];
Anna Bridge	160:5571c4ff569f	473	__IOM uint32_t ITNS[16U]; /!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register /
Anna Bridge	160:5571c4ff569f	474	uint32_t RESERVED5[16U];
Anna Bridge	160:5571c4ff569f	475	__IOM uint8_t IPR[496U]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
Anna Bridge	160:5571c4ff569f	476	uint32_t RESERVED6[580U];
Anna Bridge	160:5571c4ff569f	477	__OM uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
Anna Bridge	160:5571c4ff569f	478	} NVIC_Type;
Anna Bridge	160:5571c4ff569f	479
Anna Bridge	160:5571c4ff569f	480	/* Software Triggered Interrupt Register Definitions */
Anna Bridge	160:5571c4ff569f	481	#define NVIC_STIR_INTID_Pos 0U /!< STIR: INTLINESNUM Position /
Anna Bridge	160:5571c4ff569f	482	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
Anna Bridge	160:5571c4ff569f	483
Anna Bridge	160:5571c4ff569f	484	/@} end of group CMSIS_NVIC /
Anna Bridge	160:5571c4ff569f	485
Anna Bridge	160:5571c4ff569f	486
Anna Bridge	160:5571c4ff569f	487	/**
Anna Bridge	160:5571c4ff569f	488	\ingroup CMSIS_core_register
Anna Bridge	160:5571c4ff569f	489	\defgroup CMSIS_SCB System Control Block (SCB)
Anna Bridge	160:5571c4ff569f	490	\brief Type definitions for the System Control Block Registers
Anna Bridge	160:5571c4ff569f	491	@{
Anna Bridge	160:5571c4ff569f	492	*/
Anna Bridge	160:5571c4ff569f	493
Anna Bridge	160:5571c4ff569f	494	/**
Anna Bridge	160:5571c4ff569f	495	\brief Structure type to access the System Control Block (SCB).
Anna Bridge	160:5571c4ff569f	496	*/
Anna Bridge	160:5571c4ff569f	497	typedef struct
Anna Bridge	160:5571c4ff569f	498	{
Anna Bridge	160:5571c4ff569f	499	__IM uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
Anna Bridge	160:5571c4ff569f	500	__IOM uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
Anna Bridge	160:5571c4ff569f	501	__IOM uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
Anna Bridge	160:5571c4ff569f	502	__IOM uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
Anna Bridge	160:5571c4ff569f	503	__IOM uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
Anna Bridge	160:5571c4ff569f	504	__IOM uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
Anna Bridge	160:5571c4ff569f	505	__IOM uint8_t SHPR[12U]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
Anna Bridge	160:5571c4ff569f	506	__IOM uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
Anna Bridge	160:5571c4ff569f	507	__IOM uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
Anna Bridge	160:5571c4ff569f	508	__IOM uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
Anna Bridge	160:5571c4ff569f	509	__IOM uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
Anna Bridge	160:5571c4ff569f	510	__IOM uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
Anna Bridge	160:5571c4ff569f	511	__IOM uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
Anna Bridge	160:5571c4ff569f	512	__IOM uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
Anna Bridge	160:5571c4ff569f	513	__IM uint32_t ID_PFR[2U]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
Anna Bridge	160:5571c4ff569f	514	__IM uint32_t ID_DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
Anna Bridge	160:5571c4ff569f	515	__IM uint32_t ID_ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
Anna Bridge	160:5571c4ff569f	516	__IM uint32_t ID_MMFR[4U]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
Anna Bridge	160:5571c4ff569f	517	__IM uint32_t ID_ISAR[6U]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
Anna Bridge	160:5571c4ff569f	518	__IM uint32_t CLIDR; /!< Offset: 0x078 (R/ ) Cache Level ID register /
Anna Bridge	160:5571c4ff569f	519	__IM uint32_t CTR; /!< Offset: 0x07C (R/ ) Cache Type register /
Anna Bridge	160:5571c4ff569f	520	__IM uint32_t CCSIDR; /!< Offset: 0x080 (R/ ) Cache Size ID Register /
Anna Bridge	160:5571c4ff569f	521	__IOM uint32_t CSSELR; /!< Offset: 0x084 (R/W) Cache Size Selection Register /
Anna Bridge	160:5571c4ff569f	522	__IOM uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
Anna Bridge	160:5571c4ff569f	523	__IOM uint32_t NSACR; /!< Offset: 0x08C (R/W) Non-Secure Access Control Register /
Anna Bridge	160:5571c4ff569f	524	uint32_t RESERVED3[92U];
Anna Bridge	160:5571c4ff569f	525	__OM uint32_t STIR; /!< Offset: 0x200 ( /W) Software Triggered Interrupt Register /
Anna Bridge	160:5571c4ff569f	526	uint32_t RESERVED4[15U];
Anna Bridge	160:5571c4ff569f	527	__IM uint32_t MVFR0; /!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 /
Anna Bridge	160:5571c4ff569f	528	__IM uint32_t MVFR1; /!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 /
Anna Bridge	160:5571c4ff569f	529	__IM uint32_t MVFR2; /!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 /
Anna Bridge	160:5571c4ff569f	530	uint32_t RESERVED5[1U];
Anna Bridge	160:5571c4ff569f	531	__OM uint32_t ICIALLU; /!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU /
Anna Bridge	160:5571c4ff569f	532	uint32_t RESERVED6[1U];
Anna Bridge	160:5571c4ff569f	533	__OM uint32_t ICIMVAU; /!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU /
Anna Bridge	160:5571c4ff569f	534	__OM uint32_t DCIMVAC; /!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC /
Anna Bridge	160:5571c4ff569f	535	__OM uint32_t DCISW; /!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way /
Anna Bridge	160:5571c4ff569f	536	__OM uint32_t DCCMVAU; /!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU /
Anna Bridge	160:5571c4ff569f	537	__OM uint32_t DCCMVAC; /!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC /
Anna Bridge	160:5571c4ff569f	538	__OM uint32_t DCCSW; /!< Offset: 0x26C ( /W) D-Cache Clean by Set-way /
Anna Bridge	160:5571c4ff569f	539	__OM uint32_t DCCIMVAC; /!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC /
Anna Bridge	160:5571c4ff569f	540	__OM uint32_t DCCISW; /!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way /
Anna Bridge	160:5571c4ff569f	541	uint32_t RESERVED7[6U];
Anna Bridge	160:5571c4ff569f	542	__IOM uint32_t ITCMCR; /!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register /
Anna Bridge	160:5571c4ff569f	543	__IOM uint32_t DTCMCR; /!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers /
Anna Bridge	160:5571c4ff569f	544	__IOM uint32_t AHBPCR; /!< Offset: 0x298 (R/W) AHBP Control Register /
Anna Bridge	160:5571c4ff569f	545	__IOM uint32_t CACR; /!< Offset: 0x29C (R/W) L1 Cache Control Register /
Anna Bridge	160:5571c4ff569f	546	__IOM uint32_t AHBSCR; /!< Offset: 0x2A0 (R/W) AHB Slave Control Register /
Anna Bridge	160:5571c4ff569f	547	uint32_t RESERVED8[1U];
Anna Bridge	160:5571c4ff569f	548	__IOM uint32_t ABFSR; /!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register /
Anna Bridge	160:5571c4ff569f	549	} SCB_Type;
Anna Bridge	160:5571c4ff569f	550
Anna Bridge	160:5571c4ff569f	551	/* SCB CPUID Register Definitions */
Anna Bridge	160:5571c4ff569f	552	#define SCB_CPUID_IMPLEMENTER_Pos 24U /!< SCB CPUID: IMPLEMENTER Position /
Anna Bridge	160:5571c4ff569f	553	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
Anna Bridge	160:5571c4ff569f	554
Anna Bridge	160:5571c4ff569f	555	#define SCB_CPUID_VARIANT_Pos 20U /!< SCB CPUID: VARIANT Position /
Anna Bridge	160:5571c4ff569f	556	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
Anna Bridge	160:5571c4ff569f	557
Anna Bridge	160:5571c4ff569f	558	#define SCB_CPUID_ARCHITECTURE_Pos 16U /!< SCB CPUID: ARCHITECTURE Position /
Anna Bridge	160:5571c4ff569f	559	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
Anna Bridge	160:5571c4ff569f	560
Anna Bridge	160:5571c4ff569f	561	#define SCB_CPUID_PARTNO_Pos 4U /!< SCB CPUID: PARTNO Position /
Anna Bridge	160:5571c4ff569f	562	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
Anna Bridge	160:5571c4ff569f	563
Anna Bridge	160:5571c4ff569f	564	#define SCB_CPUID_REVISION_Pos 0U /!< SCB CPUID: REVISION Position /
Anna Bridge	160:5571c4ff569f	565	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
Anna Bridge	160:5571c4ff569f	566
Anna Bridge	160:5571c4ff569f	567	/* SCB Interrupt Control State Register Definitions */
Anna Bridge	160:5571c4ff569f	568	#define SCB_ICSR_PENDNMISET_Pos 31U /!< SCB ICSR: PENDNMISET Position /
Anna Bridge	160:5571c4ff569f	569	#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /!< SCB ICSR: PENDNMISET Mask /
Anna Bridge	160:5571c4ff569f	570
Anna Bridge	160:5571c4ff569f	571	#define SCB_ICSR_PENDNMICLR_Pos 30U /!< SCB ICSR: PENDNMICLR Position /
Anna Bridge	160:5571c4ff569f	572	#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /!< SCB ICSR: PENDNMICLR Mask /
Anna Bridge	160:5571c4ff569f	573
Anna Bridge	160:5571c4ff569f	574	#define SCB_ICSR_PENDSVSET_Pos 28U /!< SCB ICSR: PENDSVSET Position /
Anna Bridge	160:5571c4ff569f	575	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
Anna Bridge	160:5571c4ff569f	576
Anna Bridge	160:5571c4ff569f	577	#define SCB_ICSR_PENDSVCLR_Pos 27U /!< SCB ICSR: PENDSVCLR Position /
Anna Bridge	160:5571c4ff569f	578	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
Anna Bridge	160:5571c4ff569f	579
Anna Bridge	160:5571c4ff569f	580	#define SCB_ICSR_PENDSTSET_Pos 26U /!< SCB ICSR: PENDSTSET Position /
Anna Bridge	160:5571c4ff569f	581	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
Anna Bridge	160:5571c4ff569f	582
Anna Bridge	160:5571c4ff569f	583	#define SCB_ICSR_PENDSTCLR_Pos 25U /!< SCB ICSR: PENDSTCLR Position /
Anna Bridge	160:5571c4ff569f	584	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
Anna Bridge	160:5571c4ff569f	585
Anna Bridge	160:5571c4ff569f	586	#define SCB_ICSR_STTNS_Pos 24U /!< SCB ICSR: STTNS Position (Security Extension) /
Anna Bridge	160:5571c4ff569f	587	#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /!< SCB ICSR: STTNS Mask (Security Extension) /
Anna Bridge	160:5571c4ff569f	588
Anna Bridge	160:5571c4ff569f	589	#define SCB_ICSR_ISRPREEMPT_Pos 23U /!< SCB ICSR: ISRPREEMPT Position /
Anna Bridge	160:5571c4ff569f	590	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
Anna Bridge	160:5571c4ff569f	591
Anna Bridge	160:5571c4ff569f	592	#define SCB_ICSR_ISRPENDING_Pos 22U /!< SCB ICSR: ISRPENDING Position /
Anna Bridge	160:5571c4ff569f	593	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
Anna Bridge	160:5571c4ff569f	594
Anna Bridge	160:5571c4ff569f	595	#define SCB_ICSR_VECTPENDING_Pos 12U /!< SCB ICSR: VECTPENDING Position /
Anna Bridge	160:5571c4ff569f	596	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
Anna Bridge	160:5571c4ff569f	597
Anna Bridge	160:5571c4ff569f	598	#define SCB_ICSR_RETTOBASE_Pos 11U /!< SCB ICSR: RETTOBASE Position /
Anna Bridge	160:5571c4ff569f	599	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
Anna Bridge	160:5571c4ff569f	600
Anna Bridge	160:5571c4ff569f	601	#define SCB_ICSR_VECTACTIVE_Pos 0U /!< SCB ICSR: VECTACTIVE Position /
Anna Bridge	160:5571c4ff569f	602	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
Anna Bridge	160:5571c4ff569f	603
Anna Bridge	160:5571c4ff569f	604	/* SCB Vector Table Offset Register Definitions */
Anna Bridge	160:5571c4ff569f	605	#define SCB_VTOR_TBLOFF_Pos 7U /!< SCB VTOR: TBLOFF Position /
Anna Bridge	160:5571c4ff569f	606	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
Anna Bridge	160:5571c4ff569f	607
Anna Bridge	160:5571c4ff569f	608	/* SCB Application Interrupt and Reset Control Register Definitions */
Anna Bridge	160:5571c4ff569f	609	#define SCB_AIRCR_VECTKEY_Pos 16U /!< SCB AIRCR: VECTKEY Position /
Anna Bridge	160:5571c4ff569f	610	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
Anna Bridge	160:5571c4ff569f	611
Anna Bridge	160:5571c4ff569f	612	#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /!< SCB AIRCR: VECTKEYSTAT Position /
Anna Bridge	160:5571c4ff569f	613	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
Anna Bridge	160:5571c4ff569f	614
Anna Bridge	160:5571c4ff569f	615	#define SCB_AIRCR_ENDIANESS_Pos 15U /!< SCB AIRCR: ENDIANESS Position /
Anna Bridge	160:5571c4ff569f	616	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
Anna Bridge	160:5571c4ff569f	617
Anna Bridge	160:5571c4ff569f	618	#define SCB_AIRCR_PRIS_Pos 14U /!< SCB AIRCR: PRIS Position /
Anna Bridge	160:5571c4ff569f	619	#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /!< SCB AIRCR: PRIS Mask /
Anna Bridge	160:5571c4ff569f	620
Anna Bridge	160:5571c4ff569f	621	#define SCB_AIRCR_BFHFNMINS_Pos 13U /!< SCB AIRCR: BFHFNMINS Position /
Anna Bridge	160:5571c4ff569f	622	#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /!< SCB AIRCR: BFHFNMINS Mask /
Anna Bridge	160:5571c4ff569f	623
Anna Bridge	160:5571c4ff569f	624	#define SCB_AIRCR_PRIGROUP_Pos 8U /!< SCB AIRCR: PRIGROUP Position /
Anna Bridge	160:5571c4ff569f	625	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
Anna Bridge	160:5571c4ff569f	626
Anna Bridge	160:5571c4ff569f	627	#define SCB_AIRCR_SYSRESETREQS_Pos 3U /!< SCB AIRCR: SYSRESETREQS Position /
Anna Bridge	160:5571c4ff569f	628	#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /!< SCB AIRCR: SYSRESETREQS Mask /
Anna Bridge	160:5571c4ff569f	629
Anna Bridge	160:5571c4ff569f	630	#define SCB_AIRCR_SYSRESETREQ_Pos 2U /!< SCB AIRCR: SYSRESETREQ Position /
Anna Bridge	160:5571c4ff569f	631	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
Anna Bridge	160:5571c4ff569f	632
Anna Bridge	160:5571c4ff569f	633	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /!< SCB AIRCR: VECTCLRACTIVE Position /
Anna Bridge	160:5571c4ff569f	634	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
Anna Bridge	160:5571c4ff569f	635
Anna Bridge	160:5571c4ff569f	636	/* SCB System Control Register Definitions */
Anna Bridge	160:5571c4ff569f	637	#define SCB_SCR_SEVONPEND_Pos 4U /!< SCB SCR: SEVONPEND Position /
Anna Bridge	160:5571c4ff569f	638	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
Anna Bridge	160:5571c4ff569f	639
Anna Bridge	160:5571c4ff569f	640	#define SCB_SCR_SLEEPDEEPS_Pos 3U /!< SCB SCR: SLEEPDEEPS Position /
Anna Bridge	160:5571c4ff569f	641	#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /!< SCB SCR: SLEEPDEEPS Mask /
Anna Bridge	160:5571c4ff569f	642
Anna Bridge	160:5571c4ff569f	643	#define SCB_SCR_SLEEPDEEP_Pos 2U /!< SCB SCR: SLEEPDEEP Position /
Anna Bridge	160:5571c4ff569f	644	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
Anna Bridge	160:5571c4ff569f	645
Anna Bridge	160:5571c4ff569f	646	#define SCB_SCR_SLEEPONEXIT_Pos 1U /!< SCB SCR: SLEEPONEXIT Position /
Anna Bridge	160:5571c4ff569f	647	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
Anna Bridge	160:5571c4ff569f	648
Anna Bridge	160:5571c4ff569f	649	/* SCB Configuration Control Register Definitions */
Anna Bridge	160:5571c4ff569f	650	#define SCB_CCR_BP_Pos 18U /!< SCB CCR: BP Position /
Anna Bridge	160:5571c4ff569f	651	#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /!< SCB CCR: BP Mask /
Anna Bridge	160:5571c4ff569f	652
Anna Bridge	160:5571c4ff569f	653	#define SCB_CCR_IC_Pos 17U /!< SCB CCR: IC Position /
Anna Bridge	160:5571c4ff569f	654	#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /!< SCB CCR: IC Mask /
Anna Bridge	160:5571c4ff569f	655
Anna Bridge	160:5571c4ff569f	656	#define SCB_CCR_DC_Pos 16U /!< SCB CCR: DC Position /
Anna Bridge	160:5571c4ff569f	657	#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /!< SCB CCR: DC Mask /
Anna Bridge	160:5571c4ff569f	658
Anna Bridge	160:5571c4ff569f	659	#define SCB_CCR_STKOFHFNMIGN_Pos 10U /!< SCB CCR: STKOFHFNMIGN Position /
Anna Bridge	160:5571c4ff569f	660	#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /!< SCB CCR: STKOFHFNMIGN Mask /
Anna Bridge	160:5571c4ff569f	661
Anna Bridge	160:5571c4ff569f	662	#define SCB_CCR_BFHFNMIGN_Pos 8U /!< SCB CCR: BFHFNMIGN Position /
Anna Bridge	160:5571c4ff569f	663	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
Anna Bridge	160:5571c4ff569f	664
Anna Bridge	160:5571c4ff569f	665	#define SCB_CCR_DIV_0_TRP_Pos 4U /!< SCB CCR: DIV_0_TRP Position /
Anna Bridge	160:5571c4ff569f	666	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
Anna Bridge	160:5571c4ff569f	667
Anna Bridge	160:5571c4ff569f	668	#define SCB_CCR_UNALIGN_TRP_Pos 3U /!< SCB CCR: UNALIGN_TRP Position /
Anna Bridge	160:5571c4ff569f	669	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
Anna Bridge	160:5571c4ff569f	670
Anna Bridge	160:5571c4ff569f	671	#define SCB_CCR_USERSETMPEND_Pos 1U /!< SCB CCR: USERSETMPEND Position /
Anna Bridge	160:5571c4ff569f	672	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
Anna Bridge	160:5571c4ff569f	673
Anna Bridge	160:5571c4ff569f	674	/* SCB System Handler Control and State Register Definitions */
Anna Bridge	160:5571c4ff569f	675	#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /!< SCB SHCSR: HARDFAULTPENDED Position /
Anna Bridge	160:5571c4ff569f	676	#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /!< SCB SHCSR: HARDFAULTPENDED Mask /
Anna Bridge	160:5571c4ff569f	677
Anna Bridge	160:5571c4ff569f	678	#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /!< SCB SHCSR: SECUREFAULTPENDED Position /
Anna Bridge	160:5571c4ff569f	679	#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /!< SCB SHCSR: SECUREFAULTPENDED Mask /
Anna Bridge	160:5571c4ff569f	680
Anna Bridge	160:5571c4ff569f	681	#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /!< SCB SHCSR: SECUREFAULTENA Position /
Anna Bridge	160:5571c4ff569f	682	#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /!< SCB SHCSR: SECUREFAULTENA Mask /
Anna Bridge	160:5571c4ff569f	683
Anna Bridge	160:5571c4ff569f	684	#define SCB_SHCSR_USGFAULTENA_Pos 18U /!< SCB SHCSR: USGFAULTENA Position /
Anna Bridge	160:5571c4ff569f	685	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
Anna Bridge	160:5571c4ff569f	686
Anna Bridge	160:5571c4ff569f	687	#define SCB_SHCSR_BUSFAULTENA_Pos 17U /!< SCB SHCSR: BUSFAULTENA Position /
Anna Bridge	160:5571c4ff569f	688	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
Anna Bridge	160:5571c4ff569f	689
Anna Bridge	160:5571c4ff569f	690	#define SCB_SHCSR_MEMFAULTENA_Pos 16U /!< SCB SHCSR: MEMFAULTENA Position /
Anna Bridge	160:5571c4ff569f	691	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
Anna Bridge	160:5571c4ff569f	692
Anna Bridge	160:5571c4ff569f	693	#define SCB_SHCSR_SVCALLPENDED_Pos 15U /!< SCB SHCSR: SVCALLPENDED Position /
Anna Bridge	160:5571c4ff569f	694	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
Anna Bridge	160:5571c4ff569f	695
Anna Bridge	160:5571c4ff569f	696	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /!< SCB SHCSR: BUSFAULTPENDED Position /
Anna Bridge	160:5571c4ff569f	697	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
Anna Bridge	160:5571c4ff569f	698
Anna Bridge	160:5571c4ff569f	699	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /!< SCB SHCSR: MEMFAULTPENDED Position /
Anna Bridge	160:5571c4ff569f	700	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
Anna Bridge	160:5571c4ff569f	701
Anna Bridge	160:5571c4ff569f	702	#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /!< SCB SHCSR: USGFAULTPENDED Position /
Anna Bridge	160:5571c4ff569f	703	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
Anna Bridge	160:5571c4ff569f	704
Anna Bridge	160:5571c4ff569f	705	#define SCB_SHCSR_SYSTICKACT_Pos 11U /!< SCB SHCSR: SYSTICKACT Position /
Anna Bridge	160:5571c4ff569f	706	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
Anna Bridge	160:5571c4ff569f	707
Anna Bridge	160:5571c4ff569f	708	#define SCB_SHCSR_PENDSVACT_Pos 10U /!< SCB SHCSR: PENDSVACT Position /
Anna Bridge	160:5571c4ff569f	709	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
Anna Bridge	160:5571c4ff569f	710
Anna Bridge	160:5571c4ff569f	711	#define SCB_SHCSR_MONITORACT_Pos 8U /!< SCB SHCSR: MONITORACT Position /
Anna Bridge	160:5571c4ff569f	712	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
Anna Bridge	160:5571c4ff569f	713
Anna Bridge	160:5571c4ff569f	714	#define SCB_SHCSR_SVCALLACT_Pos 7U /!< SCB SHCSR: SVCALLACT Position /
Anna Bridge	160:5571c4ff569f	715	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
Anna Bridge	160:5571c4ff569f	716
Anna Bridge	160:5571c4ff569f	717	#define SCB_SHCSR_NMIACT_Pos 5U /!< SCB SHCSR: NMIACT Position /
Anna Bridge	160:5571c4ff569f	718	#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /!< SCB SHCSR: NMIACT Mask /
Anna Bridge	160:5571c4ff569f	719
Anna Bridge	160:5571c4ff569f	720	#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /!< SCB SHCSR: SECUREFAULTACT Position /
Anna Bridge	160:5571c4ff569f	721	#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /!< SCB SHCSR: SECUREFAULTACT Mask /
Anna Bridge	160:5571c4ff569f	722
Anna Bridge	160:5571c4ff569f	723	#define SCB_SHCSR_USGFAULTACT_Pos 3U /!< SCB SHCSR: USGFAULTACT Position /
Anna Bridge	160:5571c4ff569f	724	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
Anna Bridge	160:5571c4ff569f	725
Anna Bridge	160:5571c4ff569f	726	#define SCB_SHCSR_HARDFAULTACT_Pos 2U /!< SCB SHCSR: HARDFAULTACT Position /
Anna Bridge	160:5571c4ff569f	727	#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /!< SCB SHCSR: HARDFAULTACT Mask /
Anna Bridge	160:5571c4ff569f	728
Anna Bridge	160:5571c4ff569f	729	#define SCB_SHCSR_BUSFAULTACT_Pos 1U /!< SCB SHCSR: BUSFAULTACT Position /
Anna Bridge	160:5571c4ff569f	730	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
Anna Bridge	160:5571c4ff569f	731
Anna Bridge	160:5571c4ff569f	732	#define SCB_SHCSR_MEMFAULTACT_Pos 0U /!< SCB SHCSR: MEMFAULTACT Position /
Anna Bridge	160:5571c4ff569f	733	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
Anna Bridge	160:5571c4ff569f	734
Anna Bridge	160:5571c4ff569f	735	/* SCB Configurable Fault Status Register Definitions */
Anna Bridge	160:5571c4ff569f	736	#define SCB_CFSR_USGFAULTSR_Pos 16U /!< SCB CFSR: Usage Fault Status Register Position /
Anna Bridge	160:5571c4ff569f	737	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
Anna Bridge	160:5571c4ff569f	738
Anna Bridge	160:5571c4ff569f	739	#define SCB_CFSR_BUSFAULTSR_Pos 8U /!< SCB CFSR: Bus Fault Status Register Position /
Anna Bridge	160:5571c4ff569f	740	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
Anna Bridge	160:5571c4ff569f	741
Anna Bridge	160:5571c4ff569f	742	#define SCB_CFSR_MEMFAULTSR_Pos 0U /!< SCB CFSR: Memory Manage Fault Status Register Position /
Anna Bridge	160:5571c4ff569f	743	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
Anna Bridge	160:5571c4ff569f	744
Anna Bridge	160:5571c4ff569f	745	/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
Anna Bridge	160:5571c4ff569f	746	#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /!< SCB CFSR (MMFSR): MMARVALID Position /
Anna Bridge	160:5571c4ff569f	747	#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /!< SCB CFSR (MMFSR): MMARVALID Mask /
Anna Bridge	160:5571c4ff569f	748
Anna Bridge	160:5571c4ff569f	749	#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /!< SCB CFSR (MMFSR): MLSPERR Position /
Anna Bridge	160:5571c4ff569f	750	#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /!< SCB CFSR (MMFSR): MLSPERR Mask /
Anna Bridge	160:5571c4ff569f	751
Anna Bridge	160:5571c4ff569f	752	#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /!< SCB CFSR (MMFSR): MSTKERR Position /
Anna Bridge	160:5571c4ff569f	753	#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /!< SCB CFSR (MMFSR): MSTKERR Mask /
Anna Bridge	160:5571c4ff569f	754
Anna Bridge	160:5571c4ff569f	755	#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /!< SCB CFSR (MMFSR): MUNSTKERR Position /
Anna Bridge	160:5571c4ff569f	756	#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /!< SCB CFSR (MMFSR): MUNSTKERR Mask /
Anna Bridge	160:5571c4ff569f	757
Anna Bridge	160:5571c4ff569f	758	#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /!< SCB CFSR (MMFSR): DACCVIOL Position /
Anna Bridge	160:5571c4ff569f	759	#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /!< SCB CFSR (MMFSR): DACCVIOL Mask /
Anna Bridge	160:5571c4ff569f	760
Anna Bridge	160:5571c4ff569f	761	#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /!< SCB CFSR (MMFSR): IACCVIOL Position /
Anna Bridge	160:5571c4ff569f	762	#define SCB_CFSR_IACCVIOL_Msk (1UL /<< SCB_CFSR_IACCVIOL_Pos/) /!< SCB CFSR (MMFSR): IACCVIOL Mask /
Anna Bridge	160:5571c4ff569f	763
Anna Bridge	160:5571c4ff569f	764	/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
Anna Bridge	160:5571c4ff569f	765	#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /!< SCB CFSR (BFSR): BFARVALID Position /
Anna Bridge	160:5571c4ff569f	766	#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /!< SCB CFSR (BFSR): BFARVALID Mask /
Anna Bridge	160:5571c4ff569f	767
Anna Bridge	160:5571c4ff569f	768	#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /!< SCB CFSR (BFSR): LSPERR Position /
Anna Bridge	160:5571c4ff569f	769	#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /!< SCB CFSR (BFSR): LSPERR Mask /
Anna Bridge	160:5571c4ff569f	770
Anna Bridge	160:5571c4ff569f	771	#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /!< SCB CFSR (BFSR): STKERR Position /
Anna Bridge	160:5571c4ff569f	772	#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /!< SCB CFSR (BFSR): STKERR Mask /
Anna Bridge	160:5571c4ff569f	773
Anna Bridge	160:5571c4ff569f	774	#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /!< SCB CFSR (BFSR): UNSTKERR Position /
Anna Bridge	160:5571c4ff569f	775	#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /!< SCB CFSR (BFSR): UNSTKERR Mask /
Anna Bridge	160:5571c4ff569f	776
Anna Bridge	160:5571c4ff569f	777	#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /!< SCB CFSR (BFSR): IMPRECISERR Position /
Anna Bridge	160:5571c4ff569f	778	#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /!< SCB CFSR (BFSR): IMPRECISERR Mask /
Anna Bridge	160:5571c4ff569f	779
Anna Bridge	160:5571c4ff569f	780	#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /!< SCB CFSR (BFSR): PRECISERR Position /
Anna Bridge	160:5571c4ff569f	781	#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /!< SCB CFSR (BFSR): PRECISERR Mask /
Anna Bridge	160:5571c4ff569f	782
Anna Bridge	160:5571c4ff569f	783	#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /!< SCB CFSR (BFSR): IBUSERR Position /
Anna Bridge	160:5571c4ff569f	784	#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /!< SCB CFSR (BFSR): IBUSERR Mask /
Anna Bridge	160:5571c4ff569f	785
Anna Bridge	160:5571c4ff569f	786	/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
Anna Bridge	160:5571c4ff569f	787	#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /!< SCB CFSR (UFSR): DIVBYZERO Position /
Anna Bridge	160:5571c4ff569f	788	#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /!< SCB CFSR (UFSR): DIVBYZERO Mask /
Anna Bridge	160:5571c4ff569f	789
Anna Bridge	160:5571c4ff569f	790	#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /!< SCB CFSR (UFSR): UNALIGNED Position /
Anna Bridge	160:5571c4ff569f	791	#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /!< SCB CFSR (UFSR): UNALIGNED Mask /
Anna Bridge	160:5571c4ff569f	792
Anna Bridge	160:5571c4ff569f	793	#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /!< SCB CFSR (UFSR): STKOF Position /
Anna Bridge	160:5571c4ff569f	794	#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /!< SCB CFSR (UFSR): STKOF Mask /
Anna Bridge	160:5571c4ff569f	795
Anna Bridge	160:5571c4ff569f	796	#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /!< SCB CFSR (UFSR): NOCP Position /
Anna Bridge	160:5571c4ff569f	797	#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /!< SCB CFSR (UFSR): NOCP Mask /
Anna Bridge	160:5571c4ff569f	798
Anna Bridge	160:5571c4ff569f	799	#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /!< SCB CFSR (UFSR): INVPC Position /
Anna Bridge	160:5571c4ff569f	800	#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /!< SCB CFSR (UFSR): INVPC Mask /
Anna Bridge	160:5571c4ff569f	801
Anna Bridge	160:5571c4ff569f	802	#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /!< SCB CFSR (UFSR): INVSTATE Position /
Anna Bridge	160:5571c4ff569f	803	#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /!< SCB CFSR (UFSR): INVSTATE Mask /
Anna Bridge	160:5571c4ff569f	804
Anna Bridge	160:5571c4ff569f	805	#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /!< SCB CFSR (UFSR): UNDEFINSTR Position /
Anna Bridge	160:5571c4ff569f	806	#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /!< SCB CFSR (UFSR): UNDEFINSTR Mask /
Anna Bridge	160:5571c4ff569f	807
Anna Bridge	160:5571c4ff569f	808	/* SCB Hard Fault Status Register Definitions */
Anna Bridge	160:5571c4ff569f	809	#define SCB_HFSR_DEBUGEVT_Pos 31U /!< SCB HFSR: DEBUGEVT Position /
Anna Bridge	160:5571c4ff569f	810	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
Anna Bridge	160:5571c4ff569f	811
Anna Bridge	160:5571c4ff569f	812	#define SCB_HFSR_FORCED_Pos 30U /!< SCB HFSR: FORCED Position /
Anna Bridge	160:5571c4ff569f	813	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
Anna Bridge	160:5571c4ff569f	814
Anna Bridge	160:5571c4ff569f	815	#define SCB_HFSR_VECTTBL_Pos 1U /!< SCB HFSR: VECTTBL Position /
Anna Bridge	160:5571c4ff569f	816	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
Anna Bridge	160:5571c4ff569f	817
Anna Bridge	160:5571c4ff569f	818	/* SCB Debug Fault Status Register Definitions */
Anna Bridge	160:5571c4ff569f	819	#define SCB_DFSR_EXTERNAL_Pos 4U /!< SCB DFSR: EXTERNAL Position /
Anna Bridge	160:5571c4ff569f	820	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
Anna Bridge	160:5571c4ff569f	821
Anna Bridge	160:5571c4ff569f	822	#define SCB_DFSR_VCATCH_Pos 3U /!< SCB DFSR: VCATCH Position /
Anna Bridge	160:5571c4ff569f	823	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
Anna Bridge	160:5571c4ff569f	824
Anna Bridge	160:5571c4ff569f	825	#define SCB_DFSR_DWTTRAP_Pos 2U /!< SCB DFSR: DWTTRAP Position /
Anna Bridge	160:5571c4ff569f	826	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
Anna Bridge	160:5571c4ff569f	827
Anna Bridge	160:5571c4ff569f	828	#define SCB_DFSR_BKPT_Pos 1U /!< SCB DFSR: BKPT Position /
Anna Bridge	160:5571c4ff569f	829	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
Anna Bridge	160:5571c4ff569f	830
Anna Bridge	160:5571c4ff569f	831	#define SCB_DFSR_HALTED_Pos 0U /!< SCB DFSR: HALTED Position /
Anna Bridge	160:5571c4ff569f	832	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
Anna Bridge	160:5571c4ff569f	833
Anna Bridge	160:5571c4ff569f	834	/* SCB Non-Secure Access Control Register Definitions */
Anna Bridge	160:5571c4ff569f	835	#define SCB_NSACR_CP11_Pos 11U /!< SCB NSACR: CP11 Position /
Anna Bridge	160:5571c4ff569f	836	#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /!< SCB NSACR: CP11 Mask /
Anna Bridge	160:5571c4ff569f	837
Anna Bridge	160:5571c4ff569f	838	#define SCB_NSACR_CP10_Pos 10U /!< SCB NSACR: CP10 Position /
Anna Bridge	160:5571c4ff569f	839	#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /!< SCB NSACR: CP10 Mask /
Anna Bridge	160:5571c4ff569f	840
Anna Bridge	160:5571c4ff569f	841	#define SCB_NSACR_CPn_Pos 0U /!< SCB NSACR: CPn Position /
Anna Bridge	160:5571c4ff569f	842	#define SCB_NSACR_CPn_Msk (1UL /<< SCB_NSACR_CPn_Pos/) /!< SCB NSACR: CPn Mask /
Anna Bridge	160:5571c4ff569f	843
Anna Bridge	160:5571c4ff569f	844	/* SCB Cache Level ID Register Definitions */
Anna Bridge	160:5571c4ff569f	845	#define SCB_CLIDR_LOUU_Pos 27U /!< SCB CLIDR: LoUU Position /
Anna Bridge	160:5571c4ff569f	846	#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /!< SCB CLIDR: LoUU Mask /
Anna Bridge	160:5571c4ff569f	847
Anna Bridge	160:5571c4ff569f	848	#define SCB_CLIDR_LOC_Pos 24U /!< SCB CLIDR: LoC Position /
Anna Bridge	160:5571c4ff569f	849	#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /!< SCB CLIDR: LoC Mask /
Anna Bridge	160:5571c4ff569f	850
Anna Bridge	160:5571c4ff569f	851	/* SCB Cache Type Register Definitions */
Anna Bridge	160:5571c4ff569f	852	#define SCB_CTR_FORMAT_Pos 29U /!< SCB CTR: Format Position /
Anna Bridge	160:5571c4ff569f	853	#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /!< SCB CTR: Format Mask /
Anna Bridge	160:5571c4ff569f	854
Anna Bridge	160:5571c4ff569f	855	#define SCB_CTR_CWG_Pos 24U /!< SCB CTR: CWG Position /
Anna Bridge	160:5571c4ff569f	856	#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /!< SCB CTR: CWG Mask /
Anna Bridge	160:5571c4ff569f	857
Anna Bridge	160:5571c4ff569f	858	#define SCB_CTR_ERG_Pos 20U /!< SCB CTR: ERG Position /
Anna Bridge	160:5571c4ff569f	859	#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /!< SCB CTR: ERG Mask /
Anna Bridge	160:5571c4ff569f	860
Anna Bridge	160:5571c4ff569f	861	#define SCB_CTR_DMINLINE_Pos 16U /!< SCB CTR: DminLine Position /
Anna Bridge	160:5571c4ff569f	862	#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /!< SCB CTR: DminLine Mask /
Anna Bridge	160:5571c4ff569f	863
Anna Bridge	160:5571c4ff569f	864	#define SCB_CTR_IMINLINE_Pos 0U /!< SCB CTR: ImInLine Position /
Anna Bridge	160:5571c4ff569f	865	#define SCB_CTR_IMINLINE_Msk (0xFUL /<< SCB_CTR_IMINLINE_Pos/) /!< SCB CTR: ImInLine Mask /
Anna Bridge	160:5571c4ff569f	866
Anna Bridge	160:5571c4ff569f	867	/* SCB Cache Size ID Register Definitions */
Anna Bridge	160:5571c4ff569f	868	#define SCB_CCSIDR_WT_Pos 31U /!< SCB CCSIDR: WT Position /
Anna Bridge	160:5571c4ff569f	869	#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /!< SCB CCSIDR: WT Mask /
Anna Bridge	160:5571c4ff569f	870
Anna Bridge	160:5571c4ff569f	871	#define SCB_CCSIDR_WB_Pos 30U /!< SCB CCSIDR: WB Position /
Anna Bridge	160:5571c4ff569f	872	#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /!< SCB CCSIDR: WB Mask /
Anna Bridge	160:5571c4ff569f	873
Anna Bridge	160:5571c4ff569f	874	#define SCB_CCSIDR_RA_Pos 29U /!< SCB CCSIDR: RA Position /
Anna Bridge	160:5571c4ff569f	875	#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /!< SCB CCSIDR: RA Mask /
Anna Bridge	160:5571c4ff569f	876
Anna Bridge	160:5571c4ff569f	877	#define SCB_CCSIDR_WA_Pos 28U /!< SCB CCSIDR: WA Position /
Anna Bridge	160:5571c4ff569f	878	#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /!< SCB CCSIDR: WA Mask /
Anna Bridge	160:5571c4ff569f	879
Anna Bridge	160:5571c4ff569f	880	#define SCB_CCSIDR_NUMSETS_Pos 13U /!< SCB CCSIDR: NumSets Position /
Anna Bridge	160:5571c4ff569f	881	#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /!< SCB CCSIDR: NumSets Mask /
Anna Bridge	160:5571c4ff569f	882
Anna Bridge	160:5571c4ff569f	883	#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /!< SCB CCSIDR: Associativity Position /
Anna Bridge	160:5571c4ff569f	884	#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /!< SCB CCSIDR: Associativity Mask /
Anna Bridge	160:5571c4ff569f	885
Anna Bridge	160:5571c4ff569f	886	#define SCB_CCSIDR_LINESIZE_Pos 0U /!< SCB CCSIDR: LineSize Position /
Anna Bridge	160:5571c4ff569f	887	#define SCB_CCSIDR_LINESIZE_Msk (7UL /<< SCB_CCSIDR_LINESIZE_Pos/) /!< SCB CCSIDR: LineSize Mask /
Anna Bridge	160:5571c4ff569f	888
Anna Bridge	160:5571c4ff569f	889	/* SCB Cache Size Selection Register Definitions */
Anna Bridge	160:5571c4ff569f	890	#define SCB_CSSELR_LEVEL_Pos 1U /!< SCB CSSELR: Level Position /
Anna Bridge	160:5571c4ff569f	891	#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /!< SCB CSSELR: Level Mask /
Anna Bridge	160:5571c4ff569f	892
Anna Bridge	160:5571c4ff569f	893	#define SCB_CSSELR_IND_Pos 0U /!< SCB CSSELR: InD Position /
Anna Bridge	160:5571c4ff569f	894	#define SCB_CSSELR_IND_Msk (1UL /<< SCB_CSSELR_IND_Pos/) /!< SCB CSSELR: InD Mask /
Anna Bridge	160:5571c4ff569f	895
Anna Bridge	160:5571c4ff569f	896	/* SCB Software Triggered Interrupt Register Definitions */
Anna Bridge	160:5571c4ff569f	897	#define SCB_STIR_INTID_Pos 0U /!< SCB STIR: INTID Position /
Anna Bridge	160:5571c4ff569f	898	#define SCB_STIR_INTID_Msk (0x1FFUL /<< SCB_STIR_INTID_Pos/) /!< SCB STIR: INTID Mask /
Anna Bridge	160:5571c4ff569f	899
Anna Bridge	160:5571c4ff569f	900	/* SCB D-Cache Invalidate by Set-way Register Definitions */
Anna Bridge	160:5571c4ff569f	901	#define SCB_DCISW_WAY_Pos 30U /!< SCB DCISW: Way Position /
Anna Bridge	160:5571c4ff569f	902	#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /!< SCB DCISW: Way Mask /
Anna Bridge	160:5571c4ff569f	903
Anna Bridge	160:5571c4ff569f	904	#define SCB_DCISW_SET_Pos 5U /!< SCB DCISW: Set Position /
Anna Bridge	160:5571c4ff569f	905	#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /!< SCB DCISW: Set Mask /
Anna Bridge	160:5571c4ff569f	906
Anna Bridge	160:5571c4ff569f	907	/* SCB D-Cache Clean by Set-way Register Definitions */
Anna Bridge	160:5571c4ff569f	908	#define SCB_DCCSW_WAY_Pos 30U /!< SCB DCCSW: Way Position /
Anna Bridge	160:5571c4ff569f	909	#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /!< SCB DCCSW: Way Mask /
Anna Bridge	160:5571c4ff569f	910
Anna Bridge	160:5571c4ff569f	911	#define SCB_DCCSW_SET_Pos 5U /!< SCB DCCSW: Set Position /
Anna Bridge	160:5571c4ff569f	912	#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /!< SCB DCCSW: Set Mask /
Anna Bridge	160:5571c4ff569f	913
Anna Bridge	160:5571c4ff569f	914	/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
Anna Bridge	160:5571c4ff569f	915	#define SCB_DCCISW_WAY_Pos 30U /!< SCB DCCISW: Way Position /
Anna Bridge	160:5571c4ff569f	916	#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /!< SCB DCCISW: Way Mask /
Anna Bridge	160:5571c4ff569f	917
Anna Bridge	160:5571c4ff569f	918	#define SCB_DCCISW_SET_Pos 5U /!< SCB DCCISW: Set Position /
Anna Bridge	160:5571c4ff569f	919	#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /!< SCB DCCISW: Set Mask /
Anna Bridge	160:5571c4ff569f	920
Anna Bridge	160:5571c4ff569f	921	/* Instruction Tightly-Coupled Memory Control Register Definitions */
Anna Bridge	160:5571c4ff569f	922	#define SCB_ITCMCR_SZ_Pos 3U /!< SCB ITCMCR: SZ Position /
Anna Bridge	160:5571c4ff569f	923	#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /!< SCB ITCMCR: SZ Mask /
Anna Bridge	160:5571c4ff569f	924
Anna Bridge	160:5571c4ff569f	925	#define SCB_ITCMCR_RETEN_Pos 2U /!< SCB ITCMCR: RETEN Position /
Anna Bridge	160:5571c4ff569f	926	#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /!< SCB ITCMCR: RETEN Mask /
Anna Bridge	160:5571c4ff569f	927
Anna Bridge	160:5571c4ff569f	928	#define SCB_ITCMCR_RMW_Pos 1U /!< SCB ITCMCR: RMW Position /
Anna Bridge	160:5571c4ff569f	929	#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /!< SCB ITCMCR: RMW Mask /
Anna Bridge	160:5571c4ff569f	930
Anna Bridge	160:5571c4ff569f	931	#define SCB_ITCMCR_EN_Pos 0U /!< SCB ITCMCR: EN Position /
Anna Bridge	160:5571c4ff569f	932	#define SCB_ITCMCR_EN_Msk (1UL /<< SCB_ITCMCR_EN_Pos/) /!< SCB ITCMCR: EN Mask /
Anna Bridge	160:5571c4ff569f	933
Anna Bridge	160:5571c4ff569f	934	/* Data Tightly-Coupled Memory Control Register Definitions */
Anna Bridge	160:5571c4ff569f	935	#define SCB_DTCMCR_SZ_Pos 3U /!< SCB DTCMCR: SZ Position /
Anna Bridge	160:5571c4ff569f	936	#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /!< SCB DTCMCR: SZ Mask /
Anna Bridge	160:5571c4ff569f	937
Anna Bridge	160:5571c4ff569f	938	#define SCB_DTCMCR_RETEN_Pos 2U /!< SCB DTCMCR: RETEN Position /
Anna Bridge	160:5571c4ff569f	939	#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /!< SCB DTCMCR: RETEN Mask /
Anna Bridge	160:5571c4ff569f	940
Anna Bridge	160:5571c4ff569f	941	#define SCB_DTCMCR_RMW_Pos 1U /!< SCB DTCMCR: RMW Position /
Anna Bridge	160:5571c4ff569f	942	#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /!< SCB DTCMCR: RMW Mask /
Anna Bridge	160:5571c4ff569f	943
Anna Bridge	160:5571c4ff569f	944	#define SCB_DTCMCR_EN_Pos 0U /!< SCB DTCMCR: EN Position /
Anna Bridge	160:5571c4ff569f	945	#define SCB_DTCMCR_EN_Msk (1UL /<< SCB_DTCMCR_EN_Pos/) /!< SCB DTCMCR: EN Mask /
Anna Bridge	160:5571c4ff569f	946
Anna Bridge	160:5571c4ff569f	947	/* AHBP Control Register Definitions */
Anna Bridge	160:5571c4ff569f	948	#define SCB_AHBPCR_SZ_Pos 1U /!< SCB AHBPCR: SZ Position /
Anna Bridge	160:5571c4ff569f	949	#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /!< SCB AHBPCR: SZ Mask /
Anna Bridge	160:5571c4ff569f	950
Anna Bridge	160:5571c4ff569f	951	#define SCB_AHBPCR_EN_Pos 0U /!< SCB AHBPCR: EN Position /
Anna Bridge	160:5571c4ff569f	952	#define SCB_AHBPCR_EN_Msk (1UL /<< SCB_AHBPCR_EN_Pos/) /!< SCB AHBPCR: EN Mask /
Anna Bridge	160:5571c4ff569f	953
Anna Bridge	160:5571c4ff569f	954	/* L1 Cache Control Register Definitions */
Anna Bridge	160:5571c4ff569f	955	#define SCB_CACR_FORCEWT_Pos 2U /!< SCB CACR: FORCEWT Position /
Anna Bridge	160:5571c4ff569f	956	#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /!< SCB CACR: FORCEWT Mask /
Anna Bridge	160:5571c4ff569f	957
Anna Bridge	160:5571c4ff569f	958	#define SCB_CACR_ECCEN_Pos 1U /!< SCB CACR: ECCEN Position /
Anna Bridge	160:5571c4ff569f	959	#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /!< SCB CACR: ECCEN Mask /
Anna Bridge	160:5571c4ff569f	960
Anna Bridge	160:5571c4ff569f	961	#define SCB_CACR_SIWT_Pos 0U /!< SCB CACR: SIWT Position /
Anna Bridge	160:5571c4ff569f	962	#define SCB_CACR_SIWT_Msk (1UL /<< SCB_CACR_SIWT_Pos/) /!< SCB CACR: SIWT Mask /
Anna Bridge	160:5571c4ff569f	963
Anna Bridge	160:5571c4ff569f	964	/* AHBS Control Register Definitions */
Anna Bridge	160:5571c4ff569f	965	#define SCB_AHBSCR_INITCOUNT_Pos 11U /!< SCB AHBSCR: INITCOUNT Position /
Anna Bridge	160:5571c4ff569f	966	#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /!< SCB AHBSCR: INITCOUNT Mask /
Anna Bridge	160:5571c4ff569f	967
Anna Bridge	160:5571c4ff569f	968	#define SCB_AHBSCR_TPRI_Pos 2U /!< SCB AHBSCR: TPRI Position /
Anna Bridge	160:5571c4ff569f	969	#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /!< SCB AHBSCR: TPRI Mask /
Anna Bridge	160:5571c4ff569f	970
Anna Bridge	160:5571c4ff569f	971	#define SCB_AHBSCR_CTL_Pos 0U /!< SCB AHBSCR: CTL Position/
Anna Bridge	160:5571c4ff569f	972	#define SCB_AHBSCR_CTL_Msk (3UL /<< SCB_AHBPCR_CTL_Pos/) /!< SCB AHBSCR: CTL Mask /
Anna Bridge	160:5571c4ff569f	973
Anna Bridge	160:5571c4ff569f	974	/* Auxiliary Bus Fault Status Register Definitions */
Anna Bridge	160:5571c4ff569f	975	#define SCB_ABFSR_AXIMTYPE_Pos 8U /!< SCB ABFSR: AXIMTYPE Position/
Anna Bridge	160:5571c4ff569f	976	#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /!< SCB ABFSR: AXIMTYPE Mask /
Anna Bridge	160:5571c4ff569f	977
Anna Bridge	160:5571c4ff569f	978	#define SCB_ABFSR_EPPB_Pos 4U /!< SCB ABFSR: EPPB Position/
Anna Bridge	160:5571c4ff569f	979	#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /!< SCB ABFSR: EPPB Mask /
Anna Bridge	160:5571c4ff569f	980
Anna Bridge	160:5571c4ff569f	981	#define SCB_ABFSR_AXIM_Pos 3U /!< SCB ABFSR: AXIM Position/
Anna Bridge	160:5571c4ff569f	982	#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /!< SCB ABFSR: AXIM Mask /
Anna Bridge	160:5571c4ff569f	983
Anna Bridge	160:5571c4ff569f	984	#define SCB_ABFSR_AHBP_Pos 2U /!< SCB ABFSR: AHBP Position/
Anna Bridge	160:5571c4ff569f	985	#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /!< SCB ABFSR: AHBP Mask /
Anna Bridge	160:5571c4ff569f	986
Anna Bridge	160:5571c4ff569f	987	#define SCB_ABFSR_DTCM_Pos 1U /!< SCB ABFSR: DTCM Position/
Anna Bridge	160:5571c4ff569f	988	#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /!< SCB ABFSR: DTCM Mask /
Anna Bridge	160:5571c4ff569f	989
Anna Bridge	160:5571c4ff569f	990	#define SCB_ABFSR_ITCM_Pos 0U /!< SCB ABFSR: ITCM Position/
Anna Bridge	160:5571c4ff569f	991	#define SCB_ABFSR_ITCM_Msk (1UL /<< SCB_ABFSR_ITCM_Pos/) /!< SCB ABFSR: ITCM Mask /
Anna Bridge	160:5571c4ff569f	992
Anna Bridge	160:5571c4ff569f	993	/@} end of group CMSIS_SCB /
Anna Bridge	160:5571c4ff569f	994
Anna Bridge	160:5571c4ff569f	995
Anna Bridge	160:5571c4ff569f	996	/**
Anna Bridge	160:5571c4ff569f	997	\ingroup CMSIS_core_register
Anna Bridge	160:5571c4ff569f	998	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
Anna Bridge	160:5571c4ff569f	999	\brief Type definitions for the System Control and ID Register not in the SCB
Anna Bridge	160:5571c4ff569f	1000	@{
Anna Bridge	160:5571c4ff569f	1001	*/
Anna Bridge	160:5571c4ff569f	1002
Anna Bridge	160:5571c4ff569f	1003	/**
Anna Bridge	160:5571c4ff569f	1004	\brief Structure type to access the System Control and ID Register not in the SCB.
Anna Bridge	160:5571c4ff569f	1005	*/
Anna Bridge	160:5571c4ff569f	1006	typedef struct
Anna Bridge	160:5571c4ff569f	1007	{
Anna Bridge	160:5571c4ff569f	1008	uint32_t RESERVED0[1U];
Anna Bridge	160:5571c4ff569f	1009	__IM uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
Anna Bridge	160:5571c4ff569f	1010	__IOM uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
Anna Bridge	160:5571c4ff569f	1011	__IOM uint32_t CPPWR; /!< Offset: 0x00C (R/W) Coprocessor Power Control Register /
Anna Bridge	160:5571c4ff569f	1012	} SCnSCB_Type;
Anna Bridge	160:5571c4ff569f	1013
Anna Bridge	160:5571c4ff569f	1014	/* Interrupt Controller Type Register Definitions */
Anna Bridge	160:5571c4ff569f	1015	#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /!< ICTR: INTLINESNUM Position /
Anna Bridge	160:5571c4ff569f	1016	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
Anna Bridge	160:5571c4ff569f	1017
Anna Bridge	160:5571c4ff569f	1018	/@} end of group CMSIS_SCnotSCB /
Anna Bridge	160:5571c4ff569f	1019
Anna Bridge	160:5571c4ff569f	1020
Anna Bridge	160:5571c4ff569f	1021	/**
Anna Bridge	160:5571c4ff569f	1022	\ingroup CMSIS_core_register
Anna Bridge	160:5571c4ff569f	1023	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
Anna Bridge	160:5571c4ff569f	1024	\brief Type definitions for the System Timer Registers.
Anna Bridge	160:5571c4ff569f	1025	@{
Anna Bridge	160:5571c4ff569f	1026	*/
Anna Bridge	160:5571c4ff569f	1027
Anna Bridge	160:5571c4ff569f	1028	/**
Anna Bridge	160:5571c4ff569f	1029	\brief Structure type to access the System Timer (SysTick).
Anna Bridge	160:5571c4ff569f	1030	*/
Anna Bridge	160:5571c4ff569f	1031	typedef struct
Anna Bridge	160:5571c4ff569f	1032	{
Anna Bridge	160:5571c4ff569f	1033	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
Anna Bridge	160:5571c4ff569f	1034	__IOM uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
Anna Bridge	160:5571c4ff569f	1035	__IOM uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
Anna Bridge	160:5571c4ff569f	1036	__IM uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
Anna Bridge	160:5571c4ff569f	1037	} SysTick_Type;
Anna Bridge	160:5571c4ff569f	1038
Anna Bridge	160:5571c4ff569f	1039	/* SysTick Control / Status Register Definitions */
Anna Bridge	160:5571c4ff569f	1040	#define SysTick_CTRL_COUNTFLAG_Pos 16U /!< SysTick CTRL: COUNTFLAG Position /
Anna Bridge	160:5571c4ff569f	1041	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
Anna Bridge	160:5571c4ff569f	1042
Anna Bridge	160:5571c4ff569f	1043	#define SysTick_CTRL_CLKSOURCE_Pos 2U /!< SysTick CTRL: CLKSOURCE Position /
Anna Bridge	160:5571c4ff569f	1044	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
Anna Bridge	160:5571c4ff569f	1045
Anna Bridge	160:5571c4ff569f	1046	#define SysTick_CTRL_TICKINT_Pos 1U /!< SysTick CTRL: TICKINT Position /
Anna Bridge	160:5571c4ff569f	1047	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
Anna Bridge	160:5571c4ff569f	1048
Anna Bridge	160:5571c4ff569f	1049	#define SysTick_CTRL_ENABLE_Pos 0U /!< SysTick CTRL: ENABLE Position /
Anna Bridge	160:5571c4ff569f	1050	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
Anna Bridge	160:5571c4ff569f	1051
Anna Bridge	160:5571c4ff569f	1052	/* SysTick Reload Register Definitions */
Anna Bridge	160:5571c4ff569f	1053	#define SysTick_LOAD_RELOAD_Pos 0U /!< SysTick LOAD: RELOAD Position /
Anna Bridge	160:5571c4ff569f	1054	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
Anna Bridge	160:5571c4ff569f	1055
Anna Bridge	160:5571c4ff569f	1056	/* SysTick Current Register Definitions */
Anna Bridge	160:5571c4ff569f	1057	#define SysTick_VAL_CURRENT_Pos 0U /!< SysTick VAL: CURRENT Position /
Anna Bridge	160:5571c4ff569f	1058	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
Anna Bridge	160:5571c4ff569f	1059
Anna Bridge	160:5571c4ff569f	1060	/* SysTick Calibration Register Definitions */
Anna Bridge	160:5571c4ff569f	1061	#define SysTick_CALIB_NOREF_Pos 31U /!< SysTick CALIB: NOREF Position /
Anna Bridge	160:5571c4ff569f	1062	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
Anna Bridge	160:5571c4ff569f	1063
Anna Bridge	160:5571c4ff569f	1064	#define SysTick_CALIB_SKEW_Pos 30U /!< SysTick CALIB: SKEW Position /
Anna Bridge	160:5571c4ff569f	1065	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
Anna Bridge	160:5571c4ff569f	1066
Anna Bridge	160:5571c4ff569f	1067	#define SysTick_CALIB_TENMS_Pos 0U /!< SysTick CALIB: TENMS Position /
Anna Bridge	160:5571c4ff569f	1068	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
Anna Bridge	160:5571c4ff569f	1069
Anna Bridge	160:5571c4ff569f	1070	/@} end of group CMSIS_SysTick /
Anna Bridge	160:5571c4ff569f	1071
Anna Bridge	160:5571c4ff569f	1072
Anna Bridge	160:5571c4ff569f	1073	/**
Anna Bridge	160:5571c4ff569f	1074	\ingroup CMSIS_core_register
Anna Bridge	160:5571c4ff569f	1075	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
Anna Bridge	160:5571c4ff569f	1076	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
Anna Bridge	160:5571c4ff569f	1077	@{
Anna Bridge	160:5571c4ff569f	1078	*/
Anna Bridge	160:5571c4ff569f	1079
Anna Bridge	160:5571c4ff569f	1080	/**
Anna Bridge	160:5571c4ff569f	1081	\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Anna Bridge	160:5571c4ff569f	1082	*/
Anna Bridge	160:5571c4ff569f	1083	typedef struct
Anna Bridge	160:5571c4ff569f	1084	{
Anna Bridge	160:5571c4ff569f	1085	__OM union
Anna Bridge	160:5571c4ff569f	1086	{
Anna Bridge	160:5571c4ff569f	1087	__OM uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
Anna Bridge	160:5571c4ff569f	1088	__OM uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
Anna Bridge	160:5571c4ff569f	1089	__OM uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
Anna Bridge	160:5571c4ff569f	1090	} PORT [32U]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
Anna Bridge	160:5571c4ff569f	1091	uint32_t RESERVED0[864U];
Anna Bridge	160:5571c4ff569f	1092	__IOM uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
Anna Bridge	160:5571c4ff569f	1093	uint32_t RESERVED1[15U];
Anna Bridge	160:5571c4ff569f	1094	__IOM uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
Anna Bridge	160:5571c4ff569f	1095	uint32_t RESERVED2[15U];
Anna Bridge	160:5571c4ff569f	1096	__IOM uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
Anna Bridge	160:5571c4ff569f	1097	uint32_t RESERVED3[29U];
Anna Bridge	160:5571c4ff569f	1098	__OM uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
Anna Bridge	160:5571c4ff569f	1099	__IM uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
Anna Bridge	160:5571c4ff569f	1100	__IOM uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
Anna Bridge	160:5571c4ff569f	1101	uint32_t RESERVED4[43U];
Anna Bridge	160:5571c4ff569f	1102	__OM uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
Anna Bridge	160:5571c4ff569f	1103	__IM uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
Anna Bridge	160:5571c4ff569f	1104	uint32_t RESERVED5[1U];
Anna Bridge	160:5571c4ff569f	1105	__IM uint32_t DEVARCH; /!< Offset: 0xFBC (R/ ) ITM Device Architecture Register /
Anna Bridge	160:5571c4ff569f	1106	uint32_t RESERVED6[4U];
Anna Bridge	160:5571c4ff569f	1107	__IM uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
Anna Bridge	160:5571c4ff569f	1108	__IM uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
Anna Bridge	160:5571c4ff569f	1109	__IM uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
Anna Bridge	160:5571c4ff569f	1110	__IM uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
Anna Bridge	160:5571c4ff569f	1111	__IM uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
Anna Bridge	160:5571c4ff569f	1112	__IM uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
Anna Bridge	160:5571c4ff569f	1113	__IM uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
Anna Bridge	160:5571c4ff569f	1114	__IM uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
Anna Bridge	160:5571c4ff569f	1115	__IM uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
Anna Bridge	160:5571c4ff569f	1116	__IM uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
Anna Bridge	160:5571c4ff569f	1117	__IM uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
Anna Bridge	160:5571c4ff569f	1118	__IM uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
Anna Bridge	160:5571c4ff569f	1119	} ITM_Type;
Anna Bridge	160:5571c4ff569f	1120
Anna Bridge	160:5571c4ff569f	1121	/* ITM Stimulus Port Register Definitions */
Anna Bridge	160:5571c4ff569f	1122	#define ITM_STIM_DISABLED_Pos 1U /!< ITM STIM: DISABLED Position /
Anna Bridge	160:5571c4ff569f	1123	#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /!< ITM STIM: DISABLED Mask /
Anna Bridge	160:5571c4ff569f	1124
Anna Bridge	160:5571c4ff569f	1125	#define ITM_STIM_FIFOREADY_Pos 0U /!< ITM STIM: FIFOREADY Position /
Anna Bridge	160:5571c4ff569f	1126	#define ITM_STIM_FIFOREADY_Msk (0x1UL /<< ITM_STIM_FIFOREADY_Pos/) /!< ITM STIM: FIFOREADY Mask /
Anna Bridge	160:5571c4ff569f	1127
Anna Bridge	160:5571c4ff569f	1128	/* ITM Trace Privilege Register Definitions */
Anna Bridge	160:5571c4ff569f	1129	#define ITM_TPR_PRIVMASK_Pos 0U /!< ITM TPR: PRIVMASK Position /
Anna Bridge	169:a7c7b631e539	1130	#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
Anna Bridge	160:5571c4ff569f	1131
Anna Bridge	160:5571c4ff569f	1132	/* ITM Trace Control Register Definitions */
Anna Bridge	160:5571c4ff569f	1133	#define ITM_TCR_BUSY_Pos 23U /!< ITM TCR: BUSY Position /
Anna Bridge	160:5571c4ff569f	1134	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
Anna Bridge	160:5571c4ff569f	1135
Anna Bridge	160:5571c4ff569f	1136	#define ITM_TCR_TRACEBUSID_Pos 16U /!< ITM TCR: ATBID Position /
Anna Bridge	160:5571c4ff569f	1137	#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /!< ITM TCR: ATBID Mask /
Anna Bridge	160:5571c4ff569f	1138
Anna Bridge	160:5571c4ff569f	1139	#define ITM_TCR_GTSFREQ_Pos 10U /!< ITM TCR: Global timestamp frequency Position /
Anna Bridge	160:5571c4ff569f	1140	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
Anna Bridge	160:5571c4ff569f	1141
Anna Bridge	160:5571c4ff569f	1142	#define ITM_TCR_TSPRESCALE_Pos 8U /!< ITM TCR: TSPRESCALE Position /
Anna Bridge	160:5571c4ff569f	1143	#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /!< ITM TCR: TSPRESCALE Mask /
Anna Bridge	160:5571c4ff569f	1144
Anna Bridge	160:5571c4ff569f	1145	#define ITM_TCR_STALLENA_Pos 5U /!< ITM TCR: STALLENA Position /
Anna Bridge	160:5571c4ff569f	1146	#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /!< ITM TCR: STALLENA Mask /
Anna Bridge	160:5571c4ff569f	1147
Anna Bridge	160:5571c4ff569f	1148	#define ITM_TCR_SWOENA_Pos 4U /!< ITM TCR: SWOENA Position /
Anna Bridge	160:5571c4ff569f	1149	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
Anna Bridge	160:5571c4ff569f	1150
Anna Bridge	160:5571c4ff569f	1151	#define ITM_TCR_DWTENA_Pos 3U /!< ITM TCR: DWTENA Position /
Anna Bridge	160:5571c4ff569f	1152	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
Anna Bridge	160:5571c4ff569f	1153
Anna Bridge	160:5571c4ff569f	1154	#define ITM_TCR_SYNCENA_Pos 2U /!< ITM TCR: SYNCENA Position /
Anna Bridge	160:5571c4ff569f	1155	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
Anna Bridge	160:5571c4ff569f	1156
Anna Bridge	160:5571c4ff569f	1157	#define ITM_TCR_TSENA_Pos 1U /!< ITM TCR: TSENA Position /
Anna Bridge	160:5571c4ff569f	1158	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
Anna Bridge	160:5571c4ff569f	1159
Anna Bridge	160:5571c4ff569f	1160	#define ITM_TCR_ITMENA_Pos 0U /!< ITM TCR: ITM Enable bit Position /
Anna Bridge	160:5571c4ff569f	1161	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
Anna Bridge	160:5571c4ff569f	1162
Anna Bridge	160:5571c4ff569f	1163	/* ITM Integration Write Register Definitions */
Anna Bridge	160:5571c4ff569f	1164	#define ITM_IWR_ATVALIDM_Pos 0U /!< ITM IWR: ATVALIDM Position /
Anna Bridge	160:5571c4ff569f	1165	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
Anna Bridge	160:5571c4ff569f	1166
Anna Bridge	160:5571c4ff569f	1167	/* ITM Integration Read Register Definitions */
Anna Bridge	160:5571c4ff569f	1168	#define ITM_IRR_ATREADYM_Pos 0U /!< ITM IRR: ATREADYM Position /
Anna Bridge	160:5571c4ff569f	1169	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
Anna Bridge	160:5571c4ff569f	1170
Anna Bridge	160:5571c4ff569f	1171	/* ITM Integration Mode Control Register Definitions */
Anna Bridge	160:5571c4ff569f	1172	#define ITM_IMCR_INTEGRATION_Pos 0U /!< ITM IMCR: INTEGRATION Position /
Anna Bridge	160:5571c4ff569f	1173	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
Anna Bridge	160:5571c4ff569f	1174
Anna Bridge	160:5571c4ff569f	1175	/* ITM Lock Status Register Definitions */
Anna Bridge	160:5571c4ff569f	1176	#define ITM_LSR_ByteAcc_Pos 2U /!< ITM LSR: ByteAcc Position /
Anna Bridge	160:5571c4ff569f	1177	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
Anna Bridge	160:5571c4ff569f	1178
Anna Bridge	160:5571c4ff569f	1179	#define ITM_LSR_Access_Pos 1U /!< ITM LSR: Access Position /
Anna Bridge	160:5571c4ff569f	1180	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
Anna Bridge	160:5571c4ff569f	1181
Anna Bridge	160:5571c4ff569f	1182	#define ITM_LSR_Present_Pos 0U /!< ITM LSR: Present Position /
Anna Bridge	160:5571c4ff569f	1183	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
Anna Bridge	160:5571c4ff569f	1184
Anna Bridge	160:5571c4ff569f	1185	/@}/ /* end of group CMSIS_ITM */
Anna Bridge	160:5571c4ff569f	1186
Anna Bridge	160:5571c4ff569f	1187
Anna Bridge	160:5571c4ff569f	1188	/**
Anna Bridge	160:5571c4ff569f	1189	\ingroup CMSIS_core_register
Anna Bridge	160:5571c4ff569f	1190	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
Anna Bridge	160:5571c4ff569f	1191	\brief Type definitions for the Data Watchpoint and Trace (DWT)
Anna Bridge	160:5571c4ff569f	1192	@{
Anna Bridge	160:5571c4ff569f	1193	*/
Anna Bridge	160:5571c4ff569f	1194
Anna Bridge	160:5571c4ff569f	1195	/**
Anna Bridge	160:5571c4ff569f	1196	\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
Anna Bridge	160:5571c4ff569f	1197	*/
Anna Bridge	160:5571c4ff569f	1198	typedef struct
Anna Bridge	160:5571c4ff569f	1199	{
Anna Bridge	160:5571c4ff569f	1200	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
Anna Bridge	160:5571c4ff569f	1201	__IOM uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
Anna Bridge	160:5571c4ff569f	1202	__IOM uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
Anna Bridge	160:5571c4ff569f	1203	__IOM uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
Anna Bridge	160:5571c4ff569f	1204	__IOM uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
Anna Bridge	160:5571c4ff569f	1205	__IOM uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
Anna Bridge	160:5571c4ff569f	1206	__IOM uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
Anna Bridge	160:5571c4ff569f	1207	__IM uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
Anna Bridge	160:5571c4ff569f	1208	__IOM uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
Anna Bridge	160:5571c4ff569f	1209	uint32_t RESERVED1[1U];
Anna Bridge	160:5571c4ff569f	1210	__IOM uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
Anna Bridge	160:5571c4ff569f	1211	uint32_t RESERVED2[1U];
Anna Bridge	160:5571c4ff569f	1212	__IOM uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
Anna Bridge	160:5571c4ff569f	1213	uint32_t RESERVED3[1U];
Anna Bridge	160:5571c4ff569f	1214	__IOM uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
Anna Bridge	160:5571c4ff569f	1215	uint32_t RESERVED4[1U];
Anna Bridge	160:5571c4ff569f	1216	__IOM uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
Anna Bridge	160:5571c4ff569f	1217	uint32_t RESERVED5[1U];
Anna Bridge	160:5571c4ff569f	1218	__IOM uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
Anna Bridge	160:5571c4ff569f	1219	uint32_t RESERVED6[1U];
Anna Bridge	160:5571c4ff569f	1220	__IOM uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
Anna Bridge	160:5571c4ff569f	1221	uint32_t RESERVED7[1U];
Anna Bridge	160:5571c4ff569f	1222	__IOM uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
Anna Bridge	160:5571c4ff569f	1223	uint32_t RESERVED8[1U];
Anna Bridge	160:5571c4ff569f	1224	__IOM uint32_t COMP4; /!< Offset: 0x060 (R/W) Comparator Register 4 /
Anna Bridge	160:5571c4ff569f	1225	uint32_t RESERVED9[1U];
Anna Bridge	160:5571c4ff569f	1226	__IOM uint32_t FUNCTION4; /!< Offset: 0x068 (R/W) Function Register 4 /
Anna Bridge	160:5571c4ff569f	1227	uint32_t RESERVED10[1U];
Anna Bridge	160:5571c4ff569f	1228	__IOM uint32_t COMP5; /!< Offset: 0x070 (R/W) Comparator Register 5 /
Anna Bridge	160:5571c4ff569f	1229	uint32_t RESERVED11[1U];
Anna Bridge	160:5571c4ff569f	1230	__IOM uint32_t FUNCTION5; /!< Offset: 0x078 (R/W) Function Register 5 /
Anna Bridge	160:5571c4ff569f	1231	uint32_t RESERVED12[1U];
Anna Bridge	160:5571c4ff569f	1232	__IOM uint32_t COMP6; /!< Offset: 0x080 (R/W) Comparator Register 6 /
Anna Bridge	160:5571c4ff569f	1233	uint32_t RESERVED13[1U];
Anna Bridge	160:5571c4ff569f	1234	__IOM uint32_t FUNCTION6; /!< Offset: 0x088 (R/W) Function Register 6 /
Anna Bridge	160:5571c4ff569f	1235	uint32_t RESERVED14[1U];
Anna Bridge	160:5571c4ff569f	1236	__IOM uint32_t COMP7; /!< Offset: 0x090 (R/W) Comparator Register 7 /
Anna Bridge	160:5571c4ff569f	1237	uint32_t RESERVED15[1U];
Anna Bridge	160:5571c4ff569f	1238	__IOM uint32_t FUNCTION7; /!< Offset: 0x098 (R/W) Function Register 7 /
Anna Bridge	160:5571c4ff569f	1239	uint32_t RESERVED16[1U];
Anna Bridge	160:5571c4ff569f	1240	__IOM uint32_t COMP8; /!< Offset: 0x0A0 (R/W) Comparator Register 8 /
Anna Bridge	160:5571c4ff569f	1241	uint32_t RESERVED17[1U];
Anna Bridge	160:5571c4ff569f	1242	__IOM uint32_t FUNCTION8; /!< Offset: 0x0A8 (R/W) Function Register 8 /
Anna Bridge	160:5571c4ff569f	1243	uint32_t RESERVED18[1U];
Anna Bridge	160:5571c4ff569f	1244	__IOM uint32_t COMP9; /!< Offset: 0x0B0 (R/W) Comparator Register 9 /
Anna Bridge	160:5571c4ff569f	1245	uint32_t RESERVED19[1U];
Anna Bridge	160:5571c4ff569f	1246	__IOM uint32_t FUNCTION9; /!< Offset: 0x0B8 (R/W) Function Register 9 /
Anna Bridge	160:5571c4ff569f	1247	uint32_t RESERVED20[1U];
Anna Bridge	160:5571c4ff569f	1248	__IOM uint32_t COMP10; /!< Offset: 0x0C0 (R/W) Comparator Register 10 /
Anna Bridge	160:5571c4ff569f	1249	uint32_t RESERVED21[1U];
Anna Bridge	160:5571c4ff569f	1250	__IOM uint32_t FUNCTION10; /!< Offset: 0x0C8 (R/W) Function Register 10 /
Anna Bridge	160:5571c4ff569f	1251	uint32_t RESERVED22[1U];
Anna Bridge	160:5571c4ff569f	1252	__IOM uint32_t COMP11; /!< Offset: 0x0D0 (R/W) Comparator Register 11 /
Anna Bridge	160:5571c4ff569f	1253	uint32_t RESERVED23[1U];
Anna Bridge	160:5571c4ff569f	1254	__IOM uint32_t FUNCTION11; /!< Offset: 0x0D8 (R/W) Function Register 11 /
Anna Bridge	160:5571c4ff569f	1255	uint32_t RESERVED24[1U];
Anna Bridge	160:5571c4ff569f	1256	__IOM uint32_t COMP12; /!< Offset: 0x0E0 (R/W) Comparator Register 12 /
Anna Bridge	160:5571c4ff569f	1257	uint32_t RESERVED25[1U];
Anna Bridge	160:5571c4ff569f	1258	__IOM uint32_t FUNCTION12; /!< Offset: 0x0E8 (R/W) Function Register 12 /
Anna Bridge	160:5571c4ff569f	1259	uint32_t RESERVED26[1U];
Anna Bridge	160:5571c4ff569f	1260	__IOM uint32_t COMP13; /!< Offset: 0x0F0 (R/W) Comparator Register 13 /
Anna Bridge	160:5571c4ff569f	1261	uint32_t RESERVED27[1U];
Anna Bridge	160:5571c4ff569f	1262	__IOM uint32_t FUNCTION13; /!< Offset: 0x0F8 (R/W) Function Register 13 /
Anna Bridge	160:5571c4ff569f	1263	uint32_t RESERVED28[1U];
Anna Bridge	160:5571c4ff569f	1264	__IOM uint32_t COMP14; /!< Offset: 0x100 (R/W) Comparator Register 14 /
Anna Bridge	160:5571c4ff569f	1265	uint32_t RESERVED29[1U];
Anna Bridge	160:5571c4ff569f	1266	__IOM uint32_t FUNCTION14; /!< Offset: 0x108 (R/W) Function Register 14 /
Anna Bridge	160:5571c4ff569f	1267	uint32_t RESERVED30[1U];
Anna Bridge	160:5571c4ff569f	1268	__IOM uint32_t COMP15; /!< Offset: 0x110 (R/W) Comparator Register 15 /
Anna Bridge	160:5571c4ff569f	1269	uint32_t RESERVED31[1U];
Anna Bridge	160:5571c4ff569f	1270	__IOM uint32_t FUNCTION15; /!< Offset: 0x118 (R/W) Function Register 15 /
Anna Bridge	160:5571c4ff569f	1271	uint32_t RESERVED32[934U];
Anna Bridge	160:5571c4ff569f	1272	__IM uint32_t LSR; /!< Offset: 0xFB4 (R ) Lock Status Register /
Anna Bridge	160:5571c4ff569f	1273	uint32_t RESERVED33[1U];
Anna Bridge	160:5571c4ff569f	1274	__IM uint32_t DEVARCH; /!< Offset: 0xFBC (R/ ) Device Architecture Register /
Anna Bridge	160:5571c4ff569f	1275	} DWT_Type;
Anna Bridge	160:5571c4ff569f	1276
Anna Bridge	160:5571c4ff569f	1277	/* DWT Control Register Definitions */
Anna Bridge	160:5571c4ff569f	1278	#define DWT_CTRL_NUMCOMP_Pos 28U /!< DWT CTRL: NUMCOMP Position /
Anna Bridge	160:5571c4ff569f	1279	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
Anna Bridge	160:5571c4ff569f	1280
Anna Bridge	160:5571c4ff569f	1281	#define DWT_CTRL_NOTRCPKT_Pos 27U /!< DWT CTRL: NOTRCPKT Position /
Anna Bridge	160:5571c4ff569f	1282	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
Anna Bridge	160:5571c4ff569f	1283
Anna Bridge	160:5571c4ff569f	1284	#define DWT_CTRL_NOEXTTRIG_Pos 26U /!< DWT CTRL: NOEXTTRIG Position /
Anna Bridge	160:5571c4ff569f	1285	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
Anna Bridge	160:5571c4ff569f	1286
Anna Bridge	160:5571c4ff569f	1287	#define DWT_CTRL_NOCYCCNT_Pos 25U /!< DWT CTRL: NOCYCCNT Position /
Anna Bridge	160:5571c4ff569f	1288	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
Anna Bridge	160:5571c4ff569f	1289
Anna Bridge	160:5571c4ff569f	1290	#define DWT_CTRL_NOPRFCNT_Pos 24U /!< DWT CTRL: NOPRFCNT Position /
Anna Bridge	160:5571c4ff569f	1291	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
Anna Bridge	160:5571c4ff569f	1292
Anna Bridge	160:5571c4ff569f	1293	#define DWT_CTRL_CYCDISS_Pos 23U /!< DWT CTRL: CYCDISS Position /
Anna Bridge	160:5571c4ff569f	1294	#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /!< DWT CTRL: CYCDISS Mask /
Anna Bridge	160:5571c4ff569f	1295
Anna Bridge	160:5571c4ff569f	1296	#define DWT_CTRL_CYCEVTENA_Pos 22U /!< DWT CTRL: CYCEVTENA Position /
Anna Bridge	160:5571c4ff569f	1297	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
Anna Bridge	160:5571c4ff569f	1298
Anna Bridge	160:5571c4ff569f	1299	#define DWT_CTRL_FOLDEVTENA_Pos 21U /!< DWT CTRL: FOLDEVTENA Position /
Anna Bridge	160:5571c4ff569f	1300	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
Anna Bridge	160:5571c4ff569f	1301
Anna Bridge	160:5571c4ff569f	1302	#define DWT_CTRL_LSUEVTENA_Pos 20U /!< DWT CTRL: LSUEVTENA Position /
Anna Bridge	160:5571c4ff569f	1303	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
Anna Bridge	160:5571c4ff569f	1304
Anna Bridge	160:5571c4ff569f	1305	#define DWT_CTRL_SLEEPEVTENA_Pos 19U /!< DWT CTRL: SLEEPEVTENA Position /
Anna Bridge	160:5571c4ff569f	1306	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
Anna Bridge	160:5571c4ff569f	1307
Anna Bridge	160:5571c4ff569f	1308	#define DWT_CTRL_EXCEVTENA_Pos 18U /!< DWT CTRL: EXCEVTENA Position /
Anna Bridge	160:5571c4ff569f	1309	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
Anna Bridge	160:5571c4ff569f	1310
Anna Bridge	160:5571c4ff569f	1311	#define DWT_CTRL_CPIEVTENA_Pos 17U /!< DWT CTRL: CPIEVTENA Position /
Anna Bridge	160:5571c4ff569f	1312	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
Anna Bridge	160:5571c4ff569f	1313
Anna Bridge	160:5571c4ff569f	1314	#define DWT_CTRL_EXCTRCENA_Pos 16U /!< DWT CTRL: EXCTRCENA Position /
Anna Bridge	160:5571c4ff569f	1315	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
Anna Bridge	160:5571c4ff569f	1316
Anna Bridge	160:5571c4ff569f	1317	#define DWT_CTRL_PCSAMPLENA_Pos 12U /!< DWT CTRL: PCSAMPLENA Position /
Anna Bridge	160:5571c4ff569f	1318	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
Anna Bridge	160:5571c4ff569f	1319
Anna Bridge	160:5571c4ff569f	1320	#define DWT_CTRL_SYNCTAP_Pos 10U /!< DWT CTRL: SYNCTAP Position /
Anna Bridge	160:5571c4ff569f	1321	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
Anna Bridge	160:5571c4ff569f	1322
Anna Bridge	160:5571c4ff569f	1323	#define DWT_CTRL_CYCTAP_Pos 9U /!< DWT CTRL: CYCTAP Position /
Anna Bridge	160:5571c4ff569f	1324	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
Anna Bridge	160:5571c4ff569f	1325
Anna Bridge	160:5571c4ff569f	1326	#define DWT_CTRL_POSTINIT_Pos 5U /!< DWT CTRL: POSTINIT Position /
Anna Bridge	160:5571c4ff569f	1327	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
Anna Bridge	160:5571c4ff569f	1328
Anna Bridge	160:5571c4ff569f	1329	#define DWT_CTRL_POSTPRESET_Pos 1U /!< DWT CTRL: POSTPRESET Position /
Anna Bridge	160:5571c4ff569f	1330	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
Anna Bridge	160:5571c4ff569f	1331
Anna Bridge	160:5571c4ff569f	1332	#define DWT_CTRL_CYCCNTENA_Pos 0U /!< DWT CTRL: CYCCNTENA Position /
Anna Bridge	160:5571c4ff569f	1333	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
Anna Bridge	160:5571c4ff569f	1334
Anna Bridge	160:5571c4ff569f	1335	/* DWT CPI Count Register Definitions */
Anna Bridge	160:5571c4ff569f	1336	#define DWT_CPICNT_CPICNT_Pos 0U /!< DWT CPICNT: CPICNT Position /
Anna Bridge	160:5571c4ff569f	1337	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
Anna Bridge	160:5571c4ff569f	1338
Anna Bridge	160:5571c4ff569f	1339	/* DWT Exception Overhead Count Register Definitions */
Anna Bridge	160:5571c4ff569f	1340	#define DWT_EXCCNT_EXCCNT_Pos 0U /!< DWT EXCCNT: EXCCNT Position /
Anna Bridge	160:5571c4ff569f	1341	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
Anna Bridge	160:5571c4ff569f	1342
Anna Bridge	160:5571c4ff569f	1343	/* DWT Sleep Count Register Definitions */
Anna Bridge	160:5571c4ff569f	1344	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /!< DWT SLEEPCNT: SLEEPCNT Position /
Anna Bridge	160:5571c4ff569f	1345	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
Anna Bridge	160:5571c4ff569f	1346
Anna Bridge	160:5571c4ff569f	1347	/* DWT LSU Count Register Definitions */
Anna Bridge	160:5571c4ff569f	1348	#define DWT_LSUCNT_LSUCNT_Pos 0U /!< DWT LSUCNT: LSUCNT Position /
Anna Bridge	160:5571c4ff569f	1349	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
Anna Bridge	160:5571c4ff569f	1350
Anna Bridge	160:5571c4ff569f	1351	/* DWT Folded-instruction Count Register Definitions */
Anna Bridge	160:5571c4ff569f	1352	#define DWT_FOLDCNT_FOLDCNT_Pos 0U /!< DWT FOLDCNT: FOLDCNT Position /
Anna Bridge	160:5571c4ff569f	1353	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
Anna Bridge	160:5571c4ff569f	1354
Anna Bridge	160:5571c4ff569f	1355	/* DWT Comparator Function Register Definitions */
Anna Bridge	160:5571c4ff569f	1356	#define DWT_FUNCTION_ID_Pos 27U /!< DWT FUNCTION: ID Position /
Anna Bridge	160:5571c4ff569f	1357	#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /!< DWT FUNCTION: ID Mask /
Anna Bridge	160:5571c4ff569f	1358
Anna Bridge	160:5571c4ff569f	1359	#define DWT_FUNCTION_MATCHED_Pos 24U /!< DWT FUNCTION: MATCHED Position /
Anna Bridge	160:5571c4ff569f	1360	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
Anna Bridge	160:5571c4ff569f	1361
Anna Bridge	160:5571c4ff569f	1362	#define DWT_FUNCTION_DATAVSIZE_Pos 10U /!< DWT FUNCTION: DATAVSIZE Position /
Anna Bridge	160:5571c4ff569f	1363	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
Anna Bridge	160:5571c4ff569f	1364
Anna Bridge	160:5571c4ff569f	1365	#define DWT_FUNCTION_ACTION_Pos 4U /!< DWT FUNCTION: ACTION Position /
Anna Bridge	160:5571c4ff569f	1366	#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /!< DWT FUNCTION: ACTION Mask /
Anna Bridge	160:5571c4ff569f	1367
Anna Bridge	160:5571c4ff569f	1368	#define DWT_FUNCTION_MATCH_Pos 0U /!< DWT FUNCTION: MATCH Position /
Anna Bridge	160:5571c4ff569f	1369	#define DWT_FUNCTION_MATCH_Msk (0xFUL /<< DWT_FUNCTION_MATCH_Pos/) /!< DWT FUNCTION: MATCH Mask /
Anna Bridge	160:5571c4ff569f	1370
Anna Bridge	160:5571c4ff569f	1371	/@}/ /* end of group CMSIS_DWT */
Anna Bridge	160:5571c4ff569f	1372
Anna Bridge	160:5571c4ff569f	1373
Anna Bridge	160:5571c4ff569f	1374	/**
Anna Bridge	160:5571c4ff569f	1375	\ingroup CMSIS_core_register
Anna Bridge	160:5571c4ff569f	1376	\defgroup CMSIS_TPI Trace Port Interface (TPI)
Anna Bridge	160:5571c4ff569f	1377	\brief Type definitions for the Trace Port Interface (TPI)
Anna Bridge	160:5571c4ff569f	1378	@{
Anna Bridge	160:5571c4ff569f	1379	*/
Anna Bridge	160:5571c4ff569f	1380
Anna Bridge	160:5571c4ff569f	1381	/**
Anna Bridge	160:5571c4ff569f	1382	\brief Structure type to access the Trace Port Interface Register (TPI).
Anna Bridge	160:5571c4ff569f	1383	*/
Anna Bridge	160:5571c4ff569f	1384	typedef struct
Anna Bridge	160:5571c4ff569f	1385	{
Anna Bridge	160:5571c4ff569f	1386	__IOM uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
Anna Bridge	160:5571c4ff569f	1387	__IOM uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
Anna Bridge	160:5571c4ff569f	1388	uint32_t RESERVED0[2U];
Anna Bridge	160:5571c4ff569f	1389	__IOM uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
Anna Bridge	160:5571c4ff569f	1390	uint32_t RESERVED1[55U];
Anna Bridge	160:5571c4ff569f	1391	__IOM uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
Anna Bridge	160:5571c4ff569f	1392	uint32_t RESERVED2[131U];
Anna Bridge	160:5571c4ff569f	1393	__IM uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
Anna Bridge	160:5571c4ff569f	1394	__IOM uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
Anna Bridge	160:5571c4ff569f	1395	__IM uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
Anna Bridge	160:5571c4ff569f	1396	uint32_t RESERVED3[759U];
Anna Bridge	160:5571c4ff569f	1397	__IM uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
Anna Bridge	160:5571c4ff569f	1398	__IM uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
Anna Bridge	160:5571c4ff569f	1399	__IM uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
Anna Bridge	160:5571c4ff569f	1400	uint32_t RESERVED4[1U];
Anna Bridge	160:5571c4ff569f	1401	__IM uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
Anna Bridge	160:5571c4ff569f	1402	__IM uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
Anna Bridge	160:5571c4ff569f	1403	__IOM uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
Anna Bridge	160:5571c4ff569f	1404	uint32_t RESERVED5[39U];
Anna Bridge	160:5571c4ff569f	1405	__IOM uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
Anna Bridge	160:5571c4ff569f	1406	__IOM uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
Anna Bridge	160:5571c4ff569f	1407	uint32_t RESERVED7[8U];
Anna Bridge	160:5571c4ff569f	1408	__IM uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
Anna Bridge	160:5571c4ff569f	1409	__IM uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
Anna Bridge	160:5571c4ff569f	1410	} TPI_Type;
Anna Bridge	160:5571c4ff569f	1411
Anna Bridge	160:5571c4ff569f	1412	/* TPI Asynchronous Clock Prescaler Register Definitions */
Anna Bridge	169:a7c7b631e539	1413	#define TPI_ACPR_PRESCALER_Pos 0U /!< @Deprecated TPI ACPR: PRESCALER Position /
Anna Bridge	169:a7c7b631e539	1414	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< @Deprecated TPI ACPR: PRESCALER Mask /
Anna Bridge	169:a7c7b631e539	1415
Anna Bridge	169:a7c7b631e539	1416	#define TPI_ACPR_SWOSCALER_Pos 0U /!< TPI ACPR: SWOSCALER Position /
Anna Bridge	169:a7c7b631e539	1417	#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /<< TPI_ACPR_SWOSCALER_Pos/) /!< TPI ACPR: SWOSCALER Mask /
Anna Bridge	160:5571c4ff569f	1418
Anna Bridge	160:5571c4ff569f	1419	/* TPI Selected Pin Protocol Register Definitions */
Anna Bridge	160:5571c4ff569f	1420	#define TPI_SPPR_TXMODE_Pos 0U /!< TPI SPPR: TXMODE Position /
Anna Bridge	160:5571c4ff569f	1421	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
Anna Bridge	160:5571c4ff569f	1422
Anna Bridge	160:5571c4ff569f	1423	/* TPI Formatter and Flush Status Register Definitions */
Anna Bridge	160:5571c4ff569f	1424	#define TPI_FFSR_FtNonStop_Pos 3U /!< TPI FFSR: FtNonStop Position /
Anna Bridge	160:5571c4ff569f	1425	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
Anna Bridge	160:5571c4ff569f	1426
Anna Bridge	160:5571c4ff569f	1427	#define TPI_FFSR_TCPresent_Pos 2U /!< TPI FFSR: TCPresent Position /
Anna Bridge	160:5571c4ff569f	1428	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
Anna Bridge	160:5571c4ff569f	1429
Anna Bridge	160:5571c4ff569f	1430	#define TPI_FFSR_FtStopped_Pos 1U /!< TPI FFSR: FtStopped Position /
Anna Bridge	160:5571c4ff569f	1431	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
Anna Bridge	160:5571c4ff569f	1432
Anna Bridge	160:5571c4ff569f	1433	#define TPI_FFSR_FlInProg_Pos 0U /!< TPI FFSR: FlInProg Position /
Anna Bridge	160:5571c4ff569f	1434	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
Anna Bridge	160:5571c4ff569f	1435
Anna Bridge	160:5571c4ff569f	1436	/* TPI Formatter and Flush Control Register Definitions */
Anna Bridge	160:5571c4ff569f	1437	#define TPI_FFCR_TrigIn_Pos 8U /!< TPI FFCR: TrigIn Position /
Anna Bridge	160:5571c4ff569f	1438	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
Anna Bridge	160:5571c4ff569f	1439
Anna Bridge	160:5571c4ff569f	1440	#define TPI_FFCR_EnFCont_Pos 1U /!< TPI FFCR: EnFCont Position /
Anna Bridge	160:5571c4ff569f	1441	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
Anna Bridge	160:5571c4ff569f	1442
Anna Bridge	160:5571c4ff569f	1443	/* TPI TRIGGER Register Definitions */
Anna Bridge	160:5571c4ff569f	1444	#define TPI_TRIGGER_TRIGGER_Pos 0U /!< TPI TRIGGER: TRIGGER Position /
Anna Bridge	160:5571c4ff569f	1445	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
Anna Bridge	160:5571c4ff569f	1446
Anna Bridge	160:5571c4ff569f	1447	/* TPI Integration ETM Data Register Definitions (FIFO0) */
Anna Bridge	160:5571c4ff569f	1448	#define TPI_FIFO0_ITM_ATVALID_Pos 29U /!< TPI FIFO0: ITM_ATVALID Position /
Anna Bridge	160:5571c4ff569f	1449	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
Anna Bridge	160:5571c4ff569f	1450
Anna Bridge	160:5571c4ff569f	1451	#define TPI_FIFO0_ITM_bytecount_Pos 27U /!< TPI FIFO0: ITM_bytecount Position /
Anna Bridge	160:5571c4ff569f	1452	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
Anna Bridge	160:5571c4ff569f	1453
Anna Bridge	160:5571c4ff569f	1454	#define TPI_FIFO0_ETM_ATVALID_Pos 26U /!< TPI FIFO0: ETM_ATVALID Position /
Anna Bridge	160:5571c4ff569f	1455	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
Anna Bridge	160:5571c4ff569f	1456
Anna Bridge	160:5571c4ff569f	1457	#define TPI_FIFO0_ETM_bytecount_Pos 24U /!< TPI FIFO0: ETM_bytecount Position /
Anna Bridge	160:5571c4ff569f	1458	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
Anna Bridge	160:5571c4ff569f	1459
Anna Bridge	160:5571c4ff569f	1460	#define TPI_FIFO0_ETM2_Pos 16U /!< TPI FIFO0: ETM2 Position /
Anna Bridge	160:5571c4ff569f	1461	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
Anna Bridge	160:5571c4ff569f	1462
Anna Bridge	160:5571c4ff569f	1463	#define TPI_FIFO0_ETM1_Pos 8U /!< TPI FIFO0: ETM1 Position /
Anna Bridge	160:5571c4ff569f	1464	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
Anna Bridge	160:5571c4ff569f	1465
Anna Bridge	160:5571c4ff569f	1466	#define TPI_FIFO0_ETM0_Pos 0U /!< TPI FIFO0: ETM0 Position /
Anna Bridge	160:5571c4ff569f	1467	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
Anna Bridge	160:5571c4ff569f	1468
Anna Bridge	160:5571c4ff569f	1469	/* TPI ITATBCTR2 Register Definitions */
Anna Bridge	160:5571c4ff569f	1470	#define TPI_ITATBCTR2_ATREADY_Pos 0U /!< TPI ITATBCTR2: ATREADY Position /
Anna Bridge	160:5571c4ff569f	1471	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
Anna Bridge	160:5571c4ff569f	1472
Anna Bridge	160:5571c4ff569f	1473	/* TPI Integration ITM Data Register Definitions (FIFO1) */
Anna Bridge	160:5571c4ff569f	1474	#define TPI_FIFO1_ITM_ATVALID_Pos 29U /!< TPI FIFO1: ITM_ATVALID Position /
Anna Bridge	160:5571c4ff569f	1475	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
Anna Bridge	160:5571c4ff569f	1476
Anna Bridge	160:5571c4ff569f	1477	#define TPI_FIFO1_ITM_bytecount_Pos 27U /!< TPI FIFO1: ITM_bytecount Position /
Anna Bridge	160:5571c4ff569f	1478	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
Anna Bridge	160:5571c4ff569f	1479
Anna Bridge	160:5571c4ff569f	1480	#define TPI_FIFO1_ETM_ATVALID_Pos 26U /!< TPI FIFO1: ETM_ATVALID Position /
Anna Bridge	160:5571c4ff569f	1481	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
Anna Bridge	160:5571c4ff569f	1482
Anna Bridge	160:5571c4ff569f	1483	#define TPI_FIFO1_ETM_bytecount_Pos 24U /!< TPI FIFO1: ETM_bytecount Position /
Anna Bridge	160:5571c4ff569f	1484	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
Anna Bridge	160:5571c4ff569f	1485
Anna Bridge	160:5571c4ff569f	1486	#define TPI_FIFO1_ITM2_Pos 16U /!< TPI FIFO1: ITM2 Position /
Anna Bridge	160:5571c4ff569f	1487	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
Anna Bridge	160:5571c4ff569f	1488
Anna Bridge	160:5571c4ff569f	1489	#define TPI_FIFO1_ITM1_Pos 8U /!< TPI FIFO1: ITM1 Position /
Anna Bridge	160:5571c4ff569f	1490	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
Anna Bridge	160:5571c4ff569f	1491
Anna Bridge	160:5571c4ff569f	1492	#define TPI_FIFO1_ITM0_Pos 0U /!< TPI FIFO1: ITM0 Position /
Anna Bridge	160:5571c4ff569f	1493	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
Anna Bridge	160:5571c4ff569f	1494
Anna Bridge	160:5571c4ff569f	1495	/* TPI ITATBCTR0 Register Definitions */
Anna Bridge	160:5571c4ff569f	1496	#define TPI_ITATBCTR0_ATREADY_Pos 0U /!< TPI ITATBCTR0: ATREADY Position /
Anna Bridge	160:5571c4ff569f	1497	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
Anna Bridge	160:5571c4ff569f	1498
Anna Bridge	160:5571c4ff569f	1499	/* TPI Integration Mode Control Register Definitions */
Anna Bridge	160:5571c4ff569f	1500	#define TPI_ITCTRL_Mode_Pos 0U /!< TPI ITCTRL: Mode Position /
Anna Bridge	160:5571c4ff569f	1501	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
Anna Bridge	160:5571c4ff569f	1502
Anna Bridge	160:5571c4ff569f	1503	/* TPI DEVID Register Definitions */
Anna Bridge	160:5571c4ff569f	1504	#define TPI_DEVID_NRZVALID_Pos 11U /!< TPI DEVID: NRZVALID Position /
Anna Bridge	160:5571c4ff569f	1505	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
Anna Bridge	160:5571c4ff569f	1506
Anna Bridge	160:5571c4ff569f	1507	#define TPI_DEVID_MANCVALID_Pos 10U /!< TPI DEVID: MANCVALID Position /
Anna Bridge	160:5571c4ff569f	1508	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
Anna Bridge	160:5571c4ff569f	1509
Anna Bridge	160:5571c4ff569f	1510	#define TPI_DEVID_PTINVALID_Pos 9U /!< TPI DEVID: PTINVALID Position /
Anna Bridge	160:5571c4ff569f	1511	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
Anna Bridge	160:5571c4ff569f	1512
Anna Bridge	160:5571c4ff569f	1513	#define TPI_DEVID_MinBufSz_Pos 6U /!< TPI DEVID: MinBufSz Position /
Anna Bridge	160:5571c4ff569f	1514	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
Anna Bridge	160:5571c4ff569f	1515
Anna Bridge	160:5571c4ff569f	1516	#define TPI_DEVID_AsynClkIn_Pos 5U /!< TPI DEVID: AsynClkIn Position /
Anna Bridge	160:5571c4ff569f	1517	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
Anna Bridge	160:5571c4ff569f	1518
Anna Bridge	160:5571c4ff569f	1519	#define TPI_DEVID_NrTraceInput_Pos 0U /!< TPI DEVID: NrTraceInput Position /
Anna Bridge	160:5571c4ff569f	1520	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
Anna Bridge	160:5571c4ff569f	1521
Anna Bridge	160:5571c4ff569f	1522	/* TPI DEVTYPE Register Definitions */
Anna Bridge	160:5571c4ff569f	1523	#define TPI_DEVTYPE_MajorType_Pos 4U /!< TPI DEVTYPE: MajorType Position /
Anna Bridge	160:5571c4ff569f	1524	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
Anna Bridge	160:5571c4ff569f	1525
Anna Bridge	160:5571c4ff569f	1526	#define TPI_DEVTYPE_SubType_Pos 0U /!< TPI DEVTYPE: SubType Position /
Anna Bridge	160:5571c4ff569f	1527	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
Anna Bridge	160:5571c4ff569f	1528
Anna Bridge	160:5571c4ff569f	1529	/@}/ /* end of group CMSIS_TPI */
Anna Bridge	160:5571c4ff569f	1530
Anna Bridge	160:5571c4ff569f	1531
Anna Bridge	160:5571c4ff569f	1532	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge	160:5571c4ff569f	1533	/**
Anna Bridge	160:5571c4ff569f	1534	\ingroup CMSIS_core_register
Anna Bridge	160:5571c4ff569f	1535	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
Anna Bridge	160:5571c4ff569f	1536	\brief Type definitions for the Memory Protection Unit (MPU)
Anna Bridge	160:5571c4ff569f	1537	@{
Anna Bridge	160:5571c4ff569f	1538	*/
Anna Bridge	160:5571c4ff569f	1539
Anna Bridge	160:5571c4ff569f	1540	/**
Anna Bridge	160:5571c4ff569f	1541	\brief Structure type to access the Memory Protection Unit (MPU).
Anna Bridge	160:5571c4ff569f	1542	*/
Anna Bridge	160:5571c4ff569f	1543	typedef struct
Anna Bridge	160:5571c4ff569f	1544	{
Anna Bridge	160:5571c4ff569f	1545	__IM uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
Anna Bridge	160:5571c4ff569f	1546	__IOM uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
Anna Bridge	160:5571c4ff569f	1547	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region Number Register /
Anna Bridge	160:5571c4ff569f	1548	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
Anna Bridge	160:5571c4ff569f	1549	__IOM uint32_t RLAR; /!< Offset: 0x010 (R/W) MPU Region Limit Address Register /
Anna Bridge	160:5571c4ff569f	1550	__IOM uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 /
Anna Bridge	160:5571c4ff569f	1551	__IOM uint32_t RLAR_A1; /!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 /
Anna Bridge	160:5571c4ff569f	1552	__IOM uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 /
Anna Bridge	160:5571c4ff569f	1553	__IOM uint32_t RLAR_A2; /!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 /
Anna Bridge	160:5571c4ff569f	1554	__IOM uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 /
Anna Bridge	160:5571c4ff569f	1555	__IOM uint32_t RLAR_A3; /!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 /
Anna Bridge	160:5571c4ff569f	1556	uint32_t RESERVED0[1];
Anna Bridge	160:5571c4ff569f	1557	union {
Anna Bridge	160:5571c4ff569f	1558	__IOM uint32_t MAIR[2];
Anna Bridge	160:5571c4ff569f	1559	struct {
Anna Bridge	160:5571c4ff569f	1560	__IOM uint32_t MAIR0; /!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 /
Anna Bridge	160:5571c4ff569f	1561	__IOM uint32_t MAIR1; /!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 /
Anna Bridge	160:5571c4ff569f	1562	};
Anna Bridge	160:5571c4ff569f	1563	};
Anna Bridge	160:5571c4ff569f	1564	} MPU_Type;
Anna Bridge	160:5571c4ff569f	1565
Anna Bridge	160:5571c4ff569f	1566	#define MPU_TYPE_RALIASES 4U
Anna Bridge	160:5571c4ff569f	1567
Anna Bridge	160:5571c4ff569f	1568	/* MPU Type Register Definitions */
Anna Bridge	160:5571c4ff569f	1569	#define MPU_TYPE_IREGION_Pos 16U /!< MPU TYPE: IREGION Position /
Anna Bridge	160:5571c4ff569f	1570	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
Anna Bridge	160:5571c4ff569f	1571
Anna Bridge	160:5571c4ff569f	1572	#define MPU_TYPE_DREGION_Pos 8U /!< MPU TYPE: DREGION Position /
Anna Bridge	160:5571c4ff569f	1573	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
Anna Bridge	160:5571c4ff569f	1574
Anna Bridge	160:5571c4ff569f	1575	#define MPU_TYPE_SEPARATE_Pos 0U /!< MPU TYPE: SEPARATE Position /
Anna Bridge	160:5571c4ff569f	1576	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
Anna Bridge	160:5571c4ff569f	1577
Anna Bridge	160:5571c4ff569f	1578	/* MPU Control Register Definitions */
Anna Bridge	160:5571c4ff569f	1579	#define MPU_CTRL_PRIVDEFENA_Pos 2U /!< MPU CTRL: PRIVDEFENA Position /
Anna Bridge	160:5571c4ff569f	1580	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
Anna Bridge	160:5571c4ff569f	1581
Anna Bridge	160:5571c4ff569f	1582	#define MPU_CTRL_HFNMIENA_Pos 1U /!< MPU CTRL: HFNMIENA Position /
Anna Bridge	160:5571c4ff569f	1583	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
Anna Bridge	160:5571c4ff569f	1584
Anna Bridge	160:5571c4ff569f	1585	#define MPU_CTRL_ENABLE_Pos 0U /!< MPU CTRL: ENABLE Position /
Anna Bridge	160:5571c4ff569f	1586	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
Anna Bridge	160:5571c4ff569f	1587
Anna Bridge	160:5571c4ff569f	1588	/* MPU Region Number Register Definitions */
Anna Bridge	160:5571c4ff569f	1589	#define MPU_RNR_REGION_Pos 0U /!< MPU RNR: REGION Position /
Anna Bridge	160:5571c4ff569f	1590	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
Anna Bridge	160:5571c4ff569f	1591
Anna Bridge	160:5571c4ff569f	1592	/* MPU Region Base Address Register Definitions */
Anna Bridge	160:5571c4ff569f	1593	#define MPU_RBAR_BASE_Pos 5U /!< MPU RBAR: ADDR Position /
Anna Bridge	160:5571c4ff569f	1594	#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /!< MPU RBAR: ADDR Mask /
Anna Bridge	160:5571c4ff569f	1595
Anna Bridge	160:5571c4ff569f	1596	#define MPU_RBAR_SH_Pos 3U /!< MPU RBAR: SH Position /
Anna Bridge	160:5571c4ff569f	1597	#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /!< MPU RBAR: SH Mask /
Anna Bridge	160:5571c4ff569f	1598
Anna Bridge	160:5571c4ff569f	1599	#define MPU_RBAR_AP_Pos 1U /!< MPU RBAR: AP Position /
Anna Bridge	160:5571c4ff569f	1600	#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /!< MPU RBAR: AP Mask /
Anna Bridge	160:5571c4ff569f	1601
Anna Bridge	160:5571c4ff569f	1602	#define MPU_RBAR_XN_Pos 0U /!< MPU RBAR: XN Position /
Anna Bridge	160:5571c4ff569f	1603	#define MPU_RBAR_XN_Msk (01UL /<< MPU_RBAR_XN_Pos/) /!< MPU RBAR: XN Mask /
Anna Bridge	160:5571c4ff569f	1604
Anna Bridge	160:5571c4ff569f	1605	/* MPU Region Limit Address Register Definitions */
Anna Bridge	160:5571c4ff569f	1606	#define MPU_RLAR_LIMIT_Pos 5U /!< MPU RLAR: LIMIT Position /
Anna Bridge	160:5571c4ff569f	1607	#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /!< MPU RLAR: LIMIT Mask /
Anna Bridge	160:5571c4ff569f	1608
Anna Bridge	160:5571c4ff569f	1609	#define MPU_RLAR_AttrIndx_Pos 1U /!< MPU RLAR: AttrIndx Position /
Anna Bridge	160:5571c4ff569f	1610	#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /!< MPU RLAR: AttrIndx Mask /
Anna Bridge	160:5571c4ff569f	1611
Anna Bridge	160:5571c4ff569f	1612	#define MPU_RLAR_EN_Pos 0U /!< MPU RLAR: Region enable bit Position /
Anna Bridge	160:5571c4ff569f	1613	#define MPU_RLAR_EN_Msk (1UL /<< MPU_RLAR_EN_Pos/) /!< MPU RLAR: Region enable bit Disable Mask /
Anna Bridge	160:5571c4ff569f	1614
Anna Bridge	160:5571c4ff569f	1615	/* MPU Memory Attribute Indirection Register 0 Definitions */
Anna Bridge	160:5571c4ff569f	1616	#define MPU_MAIR0_Attr3_Pos 24U /!< MPU MAIR0: Attr3 Position /
Anna Bridge	160:5571c4ff569f	1617	#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /!< MPU MAIR0: Attr3 Mask /
Anna Bridge	160:5571c4ff569f	1618
Anna Bridge	160:5571c4ff569f	1619	#define MPU_MAIR0_Attr2_Pos 16U /!< MPU MAIR0: Attr2 Position /
Anna Bridge	160:5571c4ff569f	1620	#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /!< MPU MAIR0: Attr2 Mask /
Anna Bridge	160:5571c4ff569f	1621
Anna Bridge	160:5571c4ff569f	1622	#define MPU_MAIR0_Attr1_Pos 8U /!< MPU MAIR0: Attr1 Position /
Anna Bridge	160:5571c4ff569f	1623	#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /!< MPU MAIR0: Attr1 Mask /
Anna Bridge	160:5571c4ff569f	1624
Anna Bridge	160:5571c4ff569f	1625	#define MPU_MAIR0_Attr0_Pos 0U /!< MPU MAIR0: Attr0 Position /
Anna Bridge	160:5571c4ff569f	1626	#define MPU_MAIR0_Attr0_Msk (0xFFUL /<< MPU_MAIR0_Attr0_Pos/) /!< MPU MAIR0: Attr0 Mask /
Anna Bridge	160:5571c4ff569f	1627
Anna Bridge	160:5571c4ff569f	1628	/* MPU Memory Attribute Indirection Register 1 Definitions */
Anna Bridge	160:5571c4ff569f	1629	#define MPU_MAIR1_Attr7_Pos 24U /!< MPU MAIR1: Attr7 Position /
Anna Bridge	160:5571c4ff569f	1630	#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /!< MPU MAIR1: Attr7 Mask /
Anna Bridge	160:5571c4ff569f	1631
Anna Bridge	160:5571c4ff569f	1632	#define MPU_MAIR1_Attr6_Pos 16U /!< MPU MAIR1: Attr6 Position /
Anna Bridge	160:5571c4ff569f	1633	#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /!< MPU MAIR1: Attr6 Mask /
Anna Bridge	160:5571c4ff569f	1634
Anna Bridge	160:5571c4ff569f	1635	#define MPU_MAIR1_Attr5_Pos 8U /!< MPU MAIR1: Attr5 Position /
Anna Bridge	160:5571c4ff569f	1636	#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /!< MPU MAIR1: Attr5 Mask /
Anna Bridge	160:5571c4ff569f	1637
Anna Bridge	160:5571c4ff569f	1638	#define MPU_MAIR1_Attr4_Pos 0U /!< MPU MAIR1: Attr4 Position /
Anna Bridge	160:5571c4ff569f	1639	#define MPU_MAIR1_Attr4_Msk (0xFFUL /<< MPU_MAIR1_Attr4_Pos/) /!< MPU MAIR1: Attr4 Mask /
Anna Bridge	160:5571c4ff569f	1640
Anna Bridge	160:5571c4ff569f	1641	/@} end of group CMSIS_MPU /
Anna Bridge	160:5571c4ff569f	1642	#endif
Anna Bridge	160:5571c4ff569f	1643
Anna Bridge	160:5571c4ff569f	1644
Anna Bridge	160:5571c4ff569f	1645	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Anna Bridge	160:5571c4ff569f	1646	/**
Anna Bridge	160:5571c4ff569f	1647	\ingroup CMSIS_core_register
Anna Bridge	160:5571c4ff569f	1648	\defgroup CMSIS_SAU Security Attribution Unit (SAU)
Anna Bridge	160:5571c4ff569f	1649	\brief Type definitions for the Security Attribution Unit (SAU)
Anna Bridge	160:5571c4ff569f	1650	@{
Anna Bridge	160:5571c4ff569f	1651	*/
Anna Bridge	160:5571c4ff569f	1652
Anna Bridge	160:5571c4ff569f	1653	/**
Anna Bridge	160:5571c4ff569f	1654	\brief Structure type to access the Security Attribution Unit (SAU).
Anna Bridge	160:5571c4ff569f	1655	*/
Anna Bridge	160:5571c4ff569f	1656	typedef struct
Anna Bridge	160:5571c4ff569f	1657	{
Anna Bridge	160:5571c4ff569f	1658	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SAU Control Register /
Anna Bridge	160:5571c4ff569f	1659	__IM uint32_t TYPE; /!< Offset: 0x004 (R/ ) SAU Type Register /
Anna Bridge	160:5571c4ff569f	1660	#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
Anna Bridge	160:5571c4ff569f	1661	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) SAU Region Number Register /
Anna Bridge	160:5571c4ff569f	1662	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) SAU Region Base Address Register /
Anna Bridge	160:5571c4ff569f	1663	__IOM uint32_t RLAR; /!< Offset: 0x010 (R/W) SAU Region Limit Address Register /
Anna Bridge	160:5571c4ff569f	1664	#else
Anna Bridge	160:5571c4ff569f	1665	uint32_t RESERVED0[3];
Anna Bridge	160:5571c4ff569f	1666	#endif
Anna Bridge	160:5571c4ff569f	1667	__IOM uint32_t SFSR; /!< Offset: 0x014 (R/W) Secure Fault Status Register /
Anna Bridge	160:5571c4ff569f	1668	__IOM uint32_t SFAR; /!< Offset: 0x018 (R/W) Secure Fault Address Register /
Anna Bridge	160:5571c4ff569f	1669	} SAU_Type;
Anna Bridge	160:5571c4ff569f	1670
Anna Bridge	160:5571c4ff569f	1671	/* SAU Control Register Definitions */
Anna Bridge	160:5571c4ff569f	1672	#define SAU_CTRL_ALLNS_Pos 1U /!< SAU CTRL: ALLNS Position /
Anna Bridge	160:5571c4ff569f	1673	#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /!< SAU CTRL: ALLNS Mask /
Anna Bridge	160:5571c4ff569f	1674
Anna Bridge	160:5571c4ff569f	1675	#define SAU_CTRL_ENABLE_Pos 0U /!< SAU CTRL: ENABLE Position /
Anna Bridge	160:5571c4ff569f	1676	#define SAU_CTRL_ENABLE_Msk (1UL /<< SAU_CTRL_ENABLE_Pos/) /!< SAU CTRL: ENABLE Mask /
Anna Bridge	160:5571c4ff569f	1677
Anna Bridge	160:5571c4ff569f	1678	/* SAU Type Register Definitions */
Anna Bridge	160:5571c4ff569f	1679	#define SAU_TYPE_SREGION_Pos 0U /!< SAU TYPE: SREGION Position /
Anna Bridge	160:5571c4ff569f	1680	#define SAU_TYPE_SREGION_Msk (0xFFUL /<< SAU_TYPE_SREGION_Pos/) /!< SAU TYPE: SREGION Mask /
Anna Bridge	160:5571c4ff569f	1681
Anna Bridge	160:5571c4ff569f	1682	#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
Anna Bridge	160:5571c4ff569f	1683	/* SAU Region Number Register Definitions */
Anna Bridge	160:5571c4ff569f	1684	#define SAU_RNR_REGION_Pos 0U /!< SAU RNR: REGION Position /
Anna Bridge	160:5571c4ff569f	1685	#define SAU_RNR_REGION_Msk (0xFFUL /<< SAU_RNR_REGION_Pos/) /!< SAU RNR: REGION Mask /
Anna Bridge	160:5571c4ff569f	1686
Anna Bridge	160:5571c4ff569f	1687	/* SAU Region Base Address Register Definitions */
Anna Bridge	160:5571c4ff569f	1688	#define SAU_RBAR_BADDR_Pos 5U /!< SAU RBAR: BADDR Position /
Anna Bridge	160:5571c4ff569f	1689	#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /!< SAU RBAR: BADDR Mask /
Anna Bridge	160:5571c4ff569f	1690
Anna Bridge	160:5571c4ff569f	1691	/* SAU Region Limit Address Register Definitions */
Anna Bridge	160:5571c4ff569f	1692	#define SAU_RLAR_LADDR_Pos 5U /!< SAU RLAR: LADDR Position /
Anna Bridge	160:5571c4ff569f	1693	#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /!< SAU RLAR: LADDR Mask /
Anna Bridge	160:5571c4ff569f	1694
Anna Bridge	160:5571c4ff569f	1695	#define SAU_RLAR_NSC_Pos 1U /!< SAU RLAR: NSC Position /
Anna Bridge	160:5571c4ff569f	1696	#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /!< SAU RLAR: NSC Mask /
Anna Bridge	160:5571c4ff569f	1697
Anna Bridge	160:5571c4ff569f	1698	#define SAU_RLAR_ENABLE_Pos 0U /!< SAU RLAR: ENABLE Position /
Anna Bridge	160:5571c4ff569f	1699	#define SAU_RLAR_ENABLE_Msk (1UL /<< SAU_RLAR_ENABLE_Pos/) /!< SAU RLAR: ENABLE Mask /
Anna Bridge	160:5571c4ff569f	1700
Anna Bridge	160:5571c4ff569f	1701	#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
Anna Bridge	160:5571c4ff569f	1702
Anna Bridge	160:5571c4ff569f	1703	/* Secure Fault Status Register Definitions */
Anna Bridge	160:5571c4ff569f	1704	#define SAU_SFSR_LSERR_Pos 7U /!< SAU SFSR: LSERR Position /
Anna Bridge	160:5571c4ff569f	1705	#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /!< SAU SFSR: LSERR Mask /
Anna Bridge	160:5571c4ff569f	1706
Anna Bridge	160:5571c4ff569f	1707	#define SAU_SFSR_SFARVALID_Pos 6U /!< SAU SFSR: SFARVALID Position /
Anna Bridge	160:5571c4ff569f	1708	#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /!< SAU SFSR: SFARVALID Mask /
Anna Bridge	160:5571c4ff569f	1709
Anna Bridge	160:5571c4ff569f	1710	#define SAU_SFSR_LSPERR_Pos 5U /!< SAU SFSR: LSPERR Position /
Anna Bridge	160:5571c4ff569f	1711	#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /!< SAU SFSR: LSPERR Mask /
Anna Bridge	160:5571c4ff569f	1712
Anna Bridge	160:5571c4ff569f	1713	#define SAU_SFSR_INVTRAN_Pos 4U /!< SAU SFSR: INVTRAN Position /
Anna Bridge	160:5571c4ff569f	1714	#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /!< SAU SFSR: INVTRAN Mask /
Anna Bridge	160:5571c4ff569f	1715
Anna Bridge	160:5571c4ff569f	1716	#define SAU_SFSR_AUVIOL_Pos 3U /!< SAU SFSR: AUVIOL Position /
Anna Bridge	160:5571c4ff569f	1717	#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /!< SAU SFSR: AUVIOL Mask /
Anna Bridge	160:5571c4ff569f	1718
Anna Bridge	160:5571c4ff569f	1719	#define SAU_SFSR_INVER_Pos 2U /!< SAU SFSR: INVER Position /
Anna Bridge	160:5571c4ff569f	1720	#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /!< SAU SFSR: INVER Mask /
Anna Bridge	160:5571c4ff569f	1721
Anna Bridge	160:5571c4ff569f	1722	#define SAU_SFSR_INVIS_Pos 1U /!< SAU SFSR: INVIS Position /
Anna Bridge	160:5571c4ff569f	1723	#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /!< SAU SFSR: INVIS Mask /
Anna Bridge	160:5571c4ff569f	1724
Anna Bridge	160:5571c4ff569f	1725	#define SAU_SFSR_INVEP_Pos 0U /!< SAU SFSR: INVEP Position /
Anna Bridge	160:5571c4ff569f	1726	#define SAU_SFSR_INVEP_Msk (1UL /<< SAU_SFSR_INVEP_Pos/) /!< SAU SFSR: INVEP Mask /
Anna Bridge	160:5571c4ff569f	1727
Anna Bridge	160:5571c4ff569f	1728	/@} end of group CMSIS_SAU /
Anna Bridge	160:5571c4ff569f	1729	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
Anna Bridge	160:5571c4ff569f	1730
Anna Bridge	160:5571c4ff569f	1731
Anna Bridge	160:5571c4ff569f	1732	/**
Anna Bridge	160:5571c4ff569f	1733	\ingroup CMSIS_core_register
Anna Bridge	160:5571c4ff569f	1734	\defgroup CMSIS_FPU Floating Point Unit (FPU)
Anna Bridge	160:5571c4ff569f	1735	\brief Type definitions for the Floating Point Unit (FPU)
Anna Bridge	160:5571c4ff569f	1736	@{
Anna Bridge	160:5571c4ff569f	1737	*/
Anna Bridge	160:5571c4ff569f	1738
Anna Bridge	160:5571c4ff569f	1739	/**
Anna Bridge	160:5571c4ff569f	1740	\brief Structure type to access the Floating Point Unit (FPU).
Anna Bridge	160:5571c4ff569f	1741	*/
Anna Bridge	160:5571c4ff569f	1742	typedef struct
Anna Bridge	160:5571c4ff569f	1743	{
Anna Bridge	160:5571c4ff569f	1744	uint32_t RESERVED0[1U];
Anna Bridge	160:5571c4ff569f	1745	__IOM uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
Anna Bridge	160:5571c4ff569f	1746	__IOM uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
Anna Bridge	160:5571c4ff569f	1747	__IOM uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
Anna Bridge	160:5571c4ff569f	1748	__IM uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
Anna Bridge	160:5571c4ff569f	1749	__IM uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
Anna Bridge	160:5571c4ff569f	1750	} FPU_Type;
Anna Bridge	160:5571c4ff569f	1751
Anna Bridge	160:5571c4ff569f	1752	/* Floating-Point Context Control Register Definitions */
Anna Bridge	160:5571c4ff569f	1753	#define FPU_FPCCR_ASPEN_Pos 31U /!< FPCCR: ASPEN bit Position /
Anna Bridge	160:5571c4ff569f	1754	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
Anna Bridge	160:5571c4ff569f	1755
Anna Bridge	160:5571c4ff569f	1756	#define FPU_FPCCR_LSPEN_Pos 30U /!< FPCCR: LSPEN Position /
Anna Bridge	160:5571c4ff569f	1757	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
Anna Bridge	160:5571c4ff569f	1758
Anna Bridge	160:5571c4ff569f	1759	#define FPU_FPCCR_LSPENS_Pos 29U /!< FPCCR: LSPENS Position /
Anna Bridge	160:5571c4ff569f	1760	#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /!< FPCCR: LSPENS bit Mask /
Anna Bridge	160:5571c4ff569f	1761
Anna Bridge	160:5571c4ff569f	1762	#define FPU_FPCCR_CLRONRET_Pos 28U /!< FPCCR: CLRONRET Position /
Anna Bridge	160:5571c4ff569f	1763	#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /!< FPCCR: CLRONRET bit Mask /
Anna Bridge	160:5571c4ff569f	1764
Anna Bridge	160:5571c4ff569f	1765	#define FPU_FPCCR_CLRONRETS_Pos 27U /!< FPCCR: CLRONRETS Position /
Anna Bridge	160:5571c4ff569f	1766	#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /!< FPCCR: CLRONRETS bit Mask /
Anna Bridge	160:5571c4ff569f	1767
Anna Bridge	160:5571c4ff569f	1768	#define FPU_FPCCR_TS_Pos 26U /!< FPCCR: TS Position /
Anna Bridge	160:5571c4ff569f	1769	#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /!< FPCCR: TS bit Mask /
Anna Bridge	160:5571c4ff569f	1770
Anna Bridge	160:5571c4ff569f	1771	#define FPU_FPCCR_UFRDY_Pos 10U /!< FPCCR: UFRDY Position /
Anna Bridge	160:5571c4ff569f	1772	#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /!< FPCCR: UFRDY bit Mask /
Anna Bridge	160:5571c4ff569f	1773
Anna Bridge	160:5571c4ff569f	1774	#define FPU_FPCCR_SPLIMVIOL_Pos 9U /!< FPCCR: SPLIMVIOL Position /
Anna Bridge	160:5571c4ff569f	1775	#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /!< FPCCR: SPLIMVIOL bit Mask /
Anna Bridge	160:5571c4ff569f	1776
Anna Bridge	160:5571c4ff569f	1777	#define FPU_FPCCR_MONRDY_Pos 8U /!< FPCCR: MONRDY Position /
Anna Bridge	160:5571c4ff569f	1778	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
Anna Bridge	160:5571c4ff569f	1779
Anna Bridge	160:5571c4ff569f	1780	#define FPU_FPCCR_SFRDY_Pos 7U /!< FPCCR: SFRDY Position /
Anna Bridge	160:5571c4ff569f	1781	#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /!< FPCCR: SFRDY bit Mask /
Anna Bridge	160:5571c4ff569f	1782
Anna Bridge	160:5571c4ff569f	1783	#define FPU_FPCCR_BFRDY_Pos 6U /!< FPCCR: BFRDY Position /
Anna Bridge	160:5571c4ff569f	1784	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
Anna Bridge	160:5571c4ff569f	1785
Anna Bridge	160:5571c4ff569f	1786	#define FPU_FPCCR_MMRDY_Pos 5U /!< FPCCR: MMRDY Position /
Anna Bridge	160:5571c4ff569f	1787	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
Anna Bridge	160:5571c4ff569f	1788
Anna Bridge	160:5571c4ff569f	1789	#define FPU_FPCCR_HFRDY_Pos 4U /!< FPCCR: HFRDY Position /
Anna Bridge	160:5571c4ff569f	1790	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
Anna Bridge	160:5571c4ff569f	1791
Anna Bridge	160:5571c4ff569f	1792	#define FPU_FPCCR_THREAD_Pos 3U /!< FPCCR: processor mode bit Position /
Anna Bridge	160:5571c4ff569f	1793	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
Anna Bridge	160:5571c4ff569f	1794
Anna Bridge	160:5571c4ff569f	1795	#define FPU_FPCCR_S_Pos 2U /!< FPCCR: Security status of the FP context bit Position /
Anna Bridge	160:5571c4ff569f	1796	#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /!< FPCCR: Security status of the FP context bit Mask /
Anna Bridge	160:5571c4ff569f	1797
Anna Bridge	160:5571c4ff569f	1798	#define FPU_FPCCR_USER_Pos 1U /!< FPCCR: privilege level bit Position /
Anna Bridge	160:5571c4ff569f	1799	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
Anna Bridge	160:5571c4ff569f	1800
Anna Bridge	160:5571c4ff569f	1801	#define FPU_FPCCR_LSPACT_Pos 0U /!< FPCCR: Lazy state preservation active bit Position /
Anna Bridge	160:5571c4ff569f	1802	#define FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/) /!< FPCCR: Lazy state preservation active bit Mask /
Anna Bridge	160:5571c4ff569f	1803
Anna Bridge	160:5571c4ff569f	1804	/* Floating-Point Context Address Register Definitions */
Anna Bridge	160:5571c4ff569f	1805	#define FPU_FPCAR_ADDRESS_Pos 3U /!< FPCAR: ADDRESS bit Position /
Anna Bridge	160:5571c4ff569f	1806	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
Anna Bridge	160:5571c4ff569f	1807
Anna Bridge	160:5571c4ff569f	1808	/* Floating-Point Default Status Control Register Definitions */
Anna Bridge	160:5571c4ff569f	1809	#define FPU_FPDSCR_AHP_Pos 26U /!< FPDSCR: AHP bit Position /
Anna Bridge	160:5571c4ff569f	1810	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
Anna Bridge	160:5571c4ff569f	1811
Anna Bridge	160:5571c4ff569f	1812	#define FPU_FPDSCR_DN_Pos 25U /!< FPDSCR: DN bit Position /
Anna Bridge	160:5571c4ff569f	1813	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
Anna Bridge	160:5571c4ff569f	1814
Anna Bridge	160:5571c4ff569f	1815	#define FPU_FPDSCR_FZ_Pos 24U /!< FPDSCR: FZ bit Position /
Anna Bridge	160:5571c4ff569f	1816	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
Anna Bridge	160:5571c4ff569f	1817
Anna Bridge	160:5571c4ff569f	1818	#define FPU_FPDSCR_RMode_Pos 22U /!< FPDSCR: RMode bit Position /
Anna Bridge	160:5571c4ff569f	1819	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
Anna Bridge	160:5571c4ff569f	1820
Anna Bridge	160:5571c4ff569f	1821	/* Media and FP Feature Register 0 Definitions */
Anna Bridge	160:5571c4ff569f	1822	#define FPU_MVFR0_FP_rounding_modes_Pos 28U /!< MVFR0: FP rounding modes bits Position /
Anna Bridge	160:5571c4ff569f	1823	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
Anna Bridge	160:5571c4ff569f	1824
Anna Bridge	160:5571c4ff569f	1825	#define FPU_MVFR0_Short_vectors_Pos 24U /!< MVFR0: Short vectors bits Position /
Anna Bridge	160:5571c4ff569f	1826	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
Anna Bridge	160:5571c4ff569f	1827
Anna Bridge	160:5571c4ff569f	1828	#define FPU_MVFR0_Square_root_Pos 20U /!< MVFR0: Square root bits Position /
Anna Bridge	160:5571c4ff569f	1829	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
Anna Bridge	160:5571c4ff569f	1830
Anna Bridge	160:5571c4ff569f	1831	#define FPU_MVFR0_Divide_Pos 16U /!< MVFR0: Divide bits Position /
Anna Bridge	160:5571c4ff569f	1832	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
Anna Bridge	160:5571c4ff569f	1833
Anna Bridge	160:5571c4ff569f	1834	#define FPU_MVFR0_FP_excep_trapping_Pos 12U /!< MVFR0: FP exception trapping bits Position /
Anna Bridge	160:5571c4ff569f	1835	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
Anna Bridge	160:5571c4ff569f	1836
Anna Bridge	160:5571c4ff569f	1837	#define FPU_MVFR0_Double_precision_Pos 8U /!< MVFR0: Double-precision bits Position /
Anna Bridge	160:5571c4ff569f	1838	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
Anna Bridge	160:5571c4ff569f	1839
Anna Bridge	160:5571c4ff569f	1840	#define FPU_MVFR0_Single_precision_Pos 4U /!< MVFR0: Single-precision bits Position /
Anna Bridge	160:5571c4ff569f	1841	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
Anna Bridge	160:5571c4ff569f	1842
Anna Bridge	160:5571c4ff569f	1843	#define FPU_MVFR0_A_SIMD_registers_Pos 0U /!< MVFR0: A_SIMD registers bits Position /
Anna Bridge	160:5571c4ff569f	1844	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/) /!< MVFR0: A_SIMD registers bits Mask /
Anna Bridge	160:5571c4ff569f	1845
Anna Bridge	160:5571c4ff569f	1846	/* Media and FP Feature Register 1 Definitions */
Anna Bridge	160:5571c4ff569f	1847	#define FPU_MVFR1_FP_fused_MAC_Pos 28U /!< MVFR1: FP fused MAC bits Position /
Anna Bridge	160:5571c4ff569f	1848	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
Anna Bridge	160:5571c4ff569f	1849
Anna Bridge	160:5571c4ff569f	1850	#define FPU_MVFR1_FP_HPFP_Pos 24U /!< MVFR1: FP HPFP bits Position /
Anna Bridge	160:5571c4ff569f	1851	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
Anna Bridge	160:5571c4ff569f	1852
Anna Bridge	160:5571c4ff569f	1853	#define FPU_MVFR1_D_NaN_mode_Pos 4U /!< MVFR1: D_NaN mode bits Position /
Anna Bridge	160:5571c4ff569f	1854	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
Anna Bridge	160:5571c4ff569f	1855
Anna Bridge	160:5571c4ff569f	1856	#define FPU_MVFR1_FtZ_mode_Pos 0U /!< MVFR1: FtZ mode bits Position /
Anna Bridge	160:5571c4ff569f	1857	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/) /!< MVFR1: FtZ mode bits Mask /
Anna Bridge	160:5571c4ff569f	1858
Anna Bridge	160:5571c4ff569f	1859	/@} end of group CMSIS_FPU /
Anna Bridge	160:5571c4ff569f	1860
Anna Bridge	160:5571c4ff569f	1861
Anna Bridge	160:5571c4ff569f	1862	/**
Anna Bridge	160:5571c4ff569f	1863	\ingroup CMSIS_core_register
Anna Bridge	160:5571c4ff569f	1864	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Anna Bridge	160:5571c4ff569f	1865	\brief Type definitions for the Core Debug Registers
Anna Bridge	160:5571c4ff569f	1866	@{
Anna Bridge	160:5571c4ff569f	1867	*/
Anna Bridge	160:5571c4ff569f	1868
Anna Bridge	160:5571c4ff569f	1869	/**
Anna Bridge	160:5571c4ff569f	1870	\brief Structure type to access the Core Debug Register (CoreDebug).
Anna Bridge	160:5571c4ff569f	1871	*/
Anna Bridge	160:5571c4ff569f	1872	typedef struct
Anna Bridge	160:5571c4ff569f	1873	{
Anna Bridge	160:5571c4ff569f	1874	__IOM uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
Anna Bridge	160:5571c4ff569f	1875	__OM uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
Anna Bridge	160:5571c4ff569f	1876	__IOM uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
Anna Bridge	160:5571c4ff569f	1877	__IOM uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
Anna Bridge	160:5571c4ff569f	1878	uint32_t RESERVED4[1U];
Anna Bridge	160:5571c4ff569f	1879	__IOM uint32_t DAUTHCTRL; /!< Offset: 0x014 (R/W) Debug Authentication Control Register /
Anna Bridge	160:5571c4ff569f	1880	__IOM uint32_t DSCSR; /!< Offset: 0x018 (R/W) Debug Security Control and Status Register /
Anna Bridge	160:5571c4ff569f	1881	} CoreDebug_Type;
Anna Bridge	160:5571c4ff569f	1882
Anna Bridge	160:5571c4ff569f	1883	/* Debug Halting Control and Status Register Definitions */
Anna Bridge	160:5571c4ff569f	1884	#define CoreDebug_DHCSR_DBGKEY_Pos 16U /!< CoreDebug DHCSR: DBGKEY Position /
Anna Bridge	160:5571c4ff569f	1885	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
Anna Bridge	160:5571c4ff569f	1886
Anna Bridge	160:5571c4ff569f	1887	#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /!< CoreDebug DHCSR: S_RESTART_ST Position /
Anna Bridge	160:5571c4ff569f	1888	#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /!< CoreDebug DHCSR: S_RESTART_ST Mask /
Anna Bridge	160:5571c4ff569f	1889
Anna Bridge	160:5571c4ff569f	1890	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /!< CoreDebug DHCSR: S_RESET_ST Position /
Anna Bridge	160:5571c4ff569f	1891	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
Anna Bridge	160:5571c4ff569f	1892
Anna Bridge	160:5571c4ff569f	1893	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /!< CoreDebug DHCSR: S_RETIRE_ST Position /
Anna Bridge	160:5571c4ff569f	1894	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
Anna Bridge	160:5571c4ff569f	1895
Anna Bridge	160:5571c4ff569f	1896	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /!< CoreDebug DHCSR: S_LOCKUP Position /
Anna Bridge	160:5571c4ff569f	1897	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
Anna Bridge	160:5571c4ff569f	1898
Anna Bridge	160:5571c4ff569f	1899	#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /!< CoreDebug DHCSR: S_SLEEP Position /
Anna Bridge	160:5571c4ff569f	1900	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
Anna Bridge	160:5571c4ff569f	1901
Anna Bridge	160:5571c4ff569f	1902	#define CoreDebug_DHCSR_S_HALT_Pos 17U /!< CoreDebug DHCSR: S_HALT Position /
Anna Bridge	160:5571c4ff569f	1903	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
Anna Bridge	160:5571c4ff569f	1904
Anna Bridge	160:5571c4ff569f	1905	#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /!< CoreDebug DHCSR: S_REGRDY Position /
Anna Bridge	160:5571c4ff569f	1906	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
Anna Bridge	160:5571c4ff569f	1907
Anna Bridge	160:5571c4ff569f	1908	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /!< CoreDebug DHCSR: C_SNAPSTALL Position /
Anna Bridge	160:5571c4ff569f	1909	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
Anna Bridge	160:5571c4ff569f	1910
Anna Bridge	160:5571c4ff569f	1911	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /!< CoreDebug DHCSR: C_MASKINTS Position /
Anna Bridge	160:5571c4ff569f	1912	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
Anna Bridge	160:5571c4ff569f	1913
Anna Bridge	160:5571c4ff569f	1914	#define CoreDebug_DHCSR_C_STEP_Pos 2U /!< CoreDebug DHCSR: C_STEP Position /
Anna Bridge	160:5571c4ff569f	1915	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
Anna Bridge	160:5571c4ff569f	1916
Anna Bridge	160:5571c4ff569f	1917	#define CoreDebug_DHCSR_C_HALT_Pos 1U /!< CoreDebug DHCSR: C_HALT Position /
Anna Bridge	160:5571c4ff569f	1918	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
Anna Bridge	160:5571c4ff569f	1919
Anna Bridge	160:5571c4ff569f	1920	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /!< CoreDebug DHCSR: C_DEBUGEN Position /
Anna Bridge	160:5571c4ff569f	1921	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
Anna Bridge	160:5571c4ff569f	1922
Anna Bridge	160:5571c4ff569f	1923	/* Debug Core Register Selector Register Definitions */
Anna Bridge	160:5571c4ff569f	1924	#define CoreDebug_DCRSR_REGWnR_Pos 16U /!< CoreDebug DCRSR: REGWnR Position /
Anna Bridge	160:5571c4ff569f	1925	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
Anna Bridge	160:5571c4ff569f	1926
Anna Bridge	160:5571c4ff569f	1927	#define CoreDebug_DCRSR_REGSEL_Pos 0U /!< CoreDebug DCRSR: REGSEL Position /
Anna Bridge	160:5571c4ff569f	1928	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
Anna Bridge	160:5571c4ff569f	1929
Anna Bridge	160:5571c4ff569f	1930	/* Debug Exception and Monitor Control Register Definitions */
Anna Bridge	160:5571c4ff569f	1931	#define CoreDebug_DEMCR_TRCENA_Pos 24U /!< CoreDebug DEMCR: TRCENA Position /
Anna Bridge	160:5571c4ff569f	1932	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
Anna Bridge	160:5571c4ff569f	1933
Anna Bridge	160:5571c4ff569f	1934	#define CoreDebug_DEMCR_MON_REQ_Pos 19U /!< CoreDebug DEMCR: MON_REQ Position /
Anna Bridge	160:5571c4ff569f	1935	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
Anna Bridge	160:5571c4ff569f	1936
Anna Bridge	160:5571c4ff569f	1937	#define CoreDebug_DEMCR_MON_STEP_Pos 18U /!< CoreDebug DEMCR: MON_STEP Position /
Anna Bridge	160:5571c4ff569f	1938	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
Anna Bridge	160:5571c4ff569f	1939
Anna Bridge	160:5571c4ff569f	1940	#define CoreDebug_DEMCR_MON_PEND_Pos 17U /!< CoreDebug DEMCR: MON_PEND Position /
Anna Bridge	160:5571c4ff569f	1941	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
Anna Bridge	160:5571c4ff569f	1942
Anna Bridge	160:5571c4ff569f	1943	#define CoreDebug_DEMCR_MON_EN_Pos 16U /!< CoreDebug DEMCR: MON_EN Position /
Anna Bridge	160:5571c4ff569f	1944	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
Anna Bridge	160:5571c4ff569f	1945
Anna Bridge	160:5571c4ff569f	1946	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /!< CoreDebug DEMCR: VC_HARDERR Position /
Anna Bridge	160:5571c4ff569f	1947	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
Anna Bridge	160:5571c4ff569f	1948
Anna Bridge	160:5571c4ff569f	1949	#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /!< CoreDebug DEMCR: VC_INTERR Position /
Anna Bridge	160:5571c4ff569f	1950	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
Anna Bridge	160:5571c4ff569f	1951
Anna Bridge	160:5571c4ff569f	1952	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /!< CoreDebug DEMCR: VC_BUSERR Position /
Anna Bridge	160:5571c4ff569f	1953	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
Anna Bridge	160:5571c4ff569f	1954
Anna Bridge	160:5571c4ff569f	1955	#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /!< CoreDebug DEMCR: VC_STATERR Position /
Anna Bridge	160:5571c4ff569f	1956	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
Anna Bridge	160:5571c4ff569f	1957
Anna Bridge	160:5571c4ff569f	1958	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /!< CoreDebug DEMCR: VC_CHKERR Position /
Anna Bridge	160:5571c4ff569f	1959	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
Anna Bridge	160:5571c4ff569f	1960
Anna Bridge	160:5571c4ff569f	1961	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /!< CoreDebug DEMCR: VC_NOCPERR Position /
Anna Bridge	160:5571c4ff569f	1962	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
Anna Bridge	160:5571c4ff569f	1963
Anna Bridge	160:5571c4ff569f	1964	#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /!< CoreDebug DEMCR: VC_MMERR Position /
Anna Bridge	160:5571c4ff569f	1965	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
Anna Bridge	160:5571c4ff569f	1966
Anna Bridge	160:5571c4ff569f	1967	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /!< CoreDebug DEMCR: VC_CORERESET Position /
Anna Bridge	160:5571c4ff569f	1968	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
Anna Bridge	160:5571c4ff569f	1969
Anna Bridge	160:5571c4ff569f	1970	/* Debug Authentication Control Register Definitions */
Anna Bridge	160:5571c4ff569f	1971	#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position /
Anna Bridge	160:5571c4ff569f	1972	#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask /
Anna Bridge	160:5571c4ff569f	1973
Anna Bridge	160:5571c4ff569f	1974	#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /!< CoreDebug DAUTHCTRL: SPNIDENSEL Position /
Anna Bridge	160:5571c4ff569f	1975	#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask /
Anna Bridge	160:5571c4ff569f	1976
Anna Bridge	160:5571c4ff569f	1977	#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /!< CoreDebug DAUTHCTRL: INTSPIDEN Position /
Anna Bridge	160:5571c4ff569f	1978	#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /!< CoreDebug DAUTHCTRL: INTSPIDEN Mask /
Anna Bridge	160:5571c4ff569f	1979
Anna Bridge	160:5571c4ff569f	1980	#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /!< CoreDebug DAUTHCTRL: SPIDENSEL Position /
Anna Bridge	160:5571c4ff569f	1981	#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/) /!< CoreDebug DAUTHCTRL: SPIDENSEL Mask /
Anna Bridge	160:5571c4ff569f	1982
Anna Bridge	160:5571c4ff569f	1983	/* Debug Security Control and Status Register Definitions */
Anna Bridge	160:5571c4ff569f	1984	#define CoreDebug_DSCSR_CDS_Pos 16U /!< CoreDebug DSCSR: CDS Position /
Anna Bridge	160:5571c4ff569f	1985	#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /!< CoreDebug DSCSR: CDS Mask /
Anna Bridge	160:5571c4ff569f	1986
Anna Bridge	160:5571c4ff569f	1987	#define CoreDebug_DSCSR_SBRSEL_Pos 1U /!< CoreDebug DSCSR: SBRSEL Position /
Anna Bridge	160:5571c4ff569f	1988	#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /!< CoreDebug DSCSR: SBRSEL Mask /
Anna Bridge	160:5571c4ff569f	1989
Anna Bridge	160:5571c4ff569f	1990	#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /!< CoreDebug DSCSR: SBRSELEN Position /
Anna Bridge	160:5571c4ff569f	1991	#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/) /!< CoreDebug DSCSR: SBRSELEN Mask /
Anna Bridge	160:5571c4ff569f	1992
Anna Bridge	160:5571c4ff569f	1993	/@} end of group CMSIS_CoreDebug /
Anna Bridge	160:5571c4ff569f	1994
Anna Bridge	160:5571c4ff569f	1995
Anna Bridge	160:5571c4ff569f	1996	/**
Anna Bridge	160:5571c4ff569f	1997	\ingroup CMSIS_core_register
Anna Bridge	160:5571c4ff569f	1998	\defgroup CMSIS_core_bitfield Core register bit field macros
Anna Bridge	160:5571c4ff569f	1999	\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
Anna Bridge	160:5571c4ff569f	2000	@{
Anna Bridge	160:5571c4ff569f	2001	*/
Anna Bridge	160:5571c4ff569f	2002
Anna Bridge	160:5571c4ff569f	2003	/**
Anna Bridge	160:5571c4ff569f	2004	\brief Mask and shift a bit field value for use in a register bit range.
Anna Bridge	160:5571c4ff569f	2005	\param[in] field Name of the register bit field.
Anna Bridge	160:5571c4ff569f	2006	\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
Anna Bridge	160:5571c4ff569f	2007	\return Masked and shifted value.
Anna Bridge	160:5571c4ff569f	2008	*/
Anna Bridge	160:5571c4ff569f	2009	#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
Anna Bridge	160:5571c4ff569f	2010
Anna Bridge	160:5571c4ff569f	2011	/**
Anna Bridge	160:5571c4ff569f	2012	\brief Mask and shift a register value to extract a bit filed value.
Anna Bridge	160:5571c4ff569f	2013	\param[in] field Name of the register bit field.
Anna Bridge	160:5571c4ff569f	2014	\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
Anna Bridge	160:5571c4ff569f	2015	\return Masked and shifted bit field value.
Anna Bridge	160:5571c4ff569f	2016	*/
Anna Bridge	160:5571c4ff569f	2017	#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
Anna Bridge	160:5571c4ff569f	2018
Anna Bridge	160:5571c4ff569f	2019	/@} end of group CMSIS_core_bitfield /
Anna Bridge	160:5571c4ff569f	2020
Anna Bridge	160:5571c4ff569f	2021
Anna Bridge	160:5571c4ff569f	2022	/**
Anna Bridge	160:5571c4ff569f	2023	\ingroup CMSIS_core_register
Anna Bridge	160:5571c4ff569f	2024	\defgroup CMSIS_core_base Core Definitions
Anna Bridge	160:5571c4ff569f	2025	\brief Definitions for base addresses, unions, and structures.
Anna Bridge	160:5571c4ff569f	2026	@{
Anna Bridge	160:5571c4ff569f	2027	*/
Anna Bridge	160:5571c4ff569f	2028
Anna Bridge	160:5571c4ff569f	2029	/* Memory mapping of Core Hardware */
Anna Bridge	160:5571c4ff569f	2030	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
Anna Bridge	160:5571c4ff569f	2031	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
Anna Bridge	160:5571c4ff569f	2032	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
Anna Bridge	160:5571c4ff569f	2033	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
Anna Bridge	160:5571c4ff569f	2034	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
Anna Bridge	160:5571c4ff569f	2035	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
Anna Bridge	160:5571c4ff569f	2036	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
Anna Bridge	160:5571c4ff569f	2037	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
Anna Bridge	160:5571c4ff569f	2038
Anna Bridge	160:5571c4ff569f	2039	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
Anna Bridge	160:5571c4ff569f	2040	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
Anna Bridge	160:5571c4ff569f	2041	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
Anna Bridge	160:5571c4ff569f	2042	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
Anna Bridge	160:5571c4ff569f	2043	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
Anna Bridge	160:5571c4ff569f	2044	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
Anna Bridge	160:5571c4ff569f	2045	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
Anna Bridge	160:5571c4ff569f	2046	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE ) /!< Core Debug configuration struct */
Anna Bridge	160:5571c4ff569f	2047
Anna Bridge	160:5571c4ff569f	2048	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge	160:5571c4ff569f	2049	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
Anna Bridge	160:5571c4ff569f	2050	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
Anna Bridge	160:5571c4ff569f	2051	#endif
Anna Bridge	160:5571c4ff569f	2052
Anna Bridge	160:5571c4ff569f	2053	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Anna Bridge	160:5571c4ff569f	2054	#define SAU_BASE (SCS_BASE + 0x0DD0UL) /!< Security Attribution Unit /
Anna Bridge	160:5571c4ff569f	2055	#define SAU ((SAU_Type ) SAU_BASE ) /!< Security Attribution Unit */
Anna Bridge	160:5571c4ff569f	2056	#endif
Anna Bridge	160:5571c4ff569f	2057
Anna Bridge	160:5571c4ff569f	2058	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
Anna Bridge	160:5571c4ff569f	2059	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
Anna Bridge	160:5571c4ff569f	2060
Anna Bridge	160:5571c4ff569f	2061	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Anna Bridge	160:5571c4ff569f	2062	#define SCS_BASE_NS (0xE002E000UL) /!< System Control Space Base Address (non-secure address space) /
Anna Bridge	160:5571c4ff569f	2063	#define CoreDebug_BASE_NS (0xE002EDF0UL) /!< Core Debug Base Address (non-secure address space) /
Anna Bridge	160:5571c4ff569f	2064	#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /!< SysTick Base Address (non-secure address space) /
Anna Bridge	160:5571c4ff569f	2065	#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /!< NVIC Base Address (non-secure address space) /
Anna Bridge	160:5571c4ff569f	2066	#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /!< System Control Block Base Address (non-secure address space) /
Anna Bridge	160:5571c4ff569f	2067
Anna Bridge	160:5571c4ff569f	2068	#define SCnSCB_NS ((SCnSCB_Type ) SCS_BASE_NS ) /!< System control Register not in SCB(non-secure address space) */
Anna Bridge	160:5571c4ff569f	2069	#define SCB_NS ((SCB_Type ) SCB_BASE_NS ) /!< SCB configuration struct (non-secure address space) */
Anna Bridge	160:5571c4ff569f	2070	#define SysTick_NS ((SysTick_Type ) SysTick_BASE_NS ) /!< SysTick configuration struct (non-secure address space) */
Anna Bridge	160:5571c4ff569f	2071	#define NVIC_NS ((NVIC_Type ) NVIC_BASE_NS ) /!< NVIC configuration struct (non-secure address space) */
Anna Bridge	160:5571c4ff569f	2072	#define CoreDebug_NS ((CoreDebug_Type ) CoreDebug_BASE_NS) /!< Core Debug configuration struct (non-secure address space) */
Anna Bridge	160:5571c4ff569f	2073
Anna Bridge	160:5571c4ff569f	2074	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge	160:5571c4ff569f	2075	#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /!< Memory Protection Unit (non-secure address space) /
Anna Bridge	160:5571c4ff569f	2076	#define MPU_NS ((MPU_Type ) MPU_BASE_NS ) /!< Memory Protection Unit (non-secure address space) */
Anna Bridge	160:5571c4ff569f	2077	#endif
Anna Bridge	160:5571c4ff569f	2078
Anna Bridge	160:5571c4ff569f	2079	#define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /!< Floating Point Unit (non-secure address space) /
Anna Bridge	160:5571c4ff569f	2080	#define FPU_NS ((FPU_Type ) FPU_BASE_NS ) /!< Floating Point Unit (non-secure address space) */
Anna Bridge	160:5571c4ff569f	2081
Anna Bridge	160:5571c4ff569f	2082	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
Anna Bridge	160:5571c4ff569f	2083	/@} /
Anna Bridge	160:5571c4ff569f	2084
Anna Bridge	160:5571c4ff569f	2085
Anna Bridge	160:5571c4ff569f	2086
Anna Bridge	160:5571c4ff569f	2087	/*******************************************************************************
Anna Bridge	160:5571c4ff569f	2088	* Hardware Abstraction Layer
Anna Bridge	160:5571c4ff569f	2089	Core Function Interface contains:
Anna Bridge	160:5571c4ff569f	2090	- Core NVIC Functions
Anna Bridge	160:5571c4ff569f	2091	- Core SysTick Functions
Anna Bridge	160:5571c4ff569f	2092	- Core Debug Functions
Anna Bridge	160:5571c4ff569f	2093	- Core Register Access Functions
Anna Bridge	160:5571c4ff569f	2094	******************************************************************************/
Anna Bridge	160:5571c4ff569f	2095	/**
Anna Bridge	160:5571c4ff569f	2096	\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Anna Bridge	160:5571c4ff569f	2097	*/
Anna Bridge	160:5571c4ff569f	2098
Anna Bridge	160:5571c4ff569f	2099
Anna Bridge	160:5571c4ff569f	2100
Anna Bridge	160:5571c4ff569f	2101	/* ########################## NVIC functions #################################### */
Anna Bridge	160:5571c4ff569f	2102	/**
Anna Bridge	160:5571c4ff569f	2103	\ingroup CMSIS_Core_FunctionInterface
Anna Bridge	160:5571c4ff569f	2104	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
Anna Bridge	160:5571c4ff569f	2105	\brief Functions that manage interrupts and exceptions via the NVIC.
Anna Bridge	160:5571c4ff569f	2106	@{
Anna Bridge	160:5571c4ff569f	2107	*/
Anna Bridge	160:5571c4ff569f	2108
Anna Bridge	160:5571c4ff569f	2109	#ifdef CMSIS_NVIC_VIRTUAL
Anna Bridge	160:5571c4ff569f	2110	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
Anna Bridge	160:5571c4ff569f	2111	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
Anna Bridge	160:5571c4ff569f	2112	#endif
Anna Bridge	160:5571c4ff569f	2113	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
Anna Bridge	160:5571c4ff569f	2114	#else
Anna Bridge	160:5571c4ff569f	2115	#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
Anna Bridge	160:5571c4ff569f	2116	#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
Anna Bridge	160:5571c4ff569f	2117	#define NVIC_EnableIRQ __NVIC_EnableIRQ
Anna Bridge	160:5571c4ff569f	2118	#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
Anna Bridge	160:5571c4ff569f	2119	#define NVIC_DisableIRQ __NVIC_DisableIRQ
Anna Bridge	160:5571c4ff569f	2120	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
Anna Bridge	160:5571c4ff569f	2121	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
Anna Bridge	160:5571c4ff569f	2122	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
Anna Bridge	160:5571c4ff569f	2123	#define NVIC_GetActive __NVIC_GetActive
Anna Bridge	160:5571c4ff569f	2124	#define NVIC_SetPriority __NVIC_SetPriority
Anna Bridge	160:5571c4ff569f	2125	#define NVIC_GetPriority __NVIC_GetPriority
Anna Bridge	160:5571c4ff569f	2126	#define NVIC_SystemReset __NVIC_SystemReset
Anna Bridge	160:5571c4ff569f	2127	#endif /* CMSIS_NVIC_VIRTUAL */
Anna Bridge	160:5571c4ff569f	2128
Anna Bridge	160:5571c4ff569f	2129	#ifdef CMSIS_VECTAB_VIRTUAL
Anna Bridge	160:5571c4ff569f	2130	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
Anna Bridge	160:5571c4ff569f	2131	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
Anna Bridge	160:5571c4ff569f	2132	#endif
Anna Bridge	160:5571c4ff569f	2133	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
Anna Bridge	160:5571c4ff569f	2134	#else
Anna Bridge	160:5571c4ff569f	2135	#define NVIC_SetVector __NVIC_SetVector
Anna Bridge	160:5571c4ff569f	2136	#define NVIC_GetVector __NVIC_GetVector
Anna Bridge	160:5571c4ff569f	2137	#endif /* (CMSIS_VECTAB_VIRTUAL) */
Anna Bridge	160:5571c4ff569f	2138
Anna Bridge	160:5571c4ff569f	2139	#define NVIC_USER_IRQ_OFFSET 16
Anna Bridge	160:5571c4ff569f	2140
Anna Bridge	160:5571c4ff569f	2141
Anna Bridge	160:5571c4ff569f	2142
Anna Bridge	160:5571c4ff569f	2143	/**
Anna Bridge	160:5571c4ff569f	2144	\brief Set Priority Grouping
Anna Bridge	160:5571c4ff569f	2145	\details Sets the priority grouping field using the required unlock sequence.
Anna Bridge	160:5571c4ff569f	2146	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Anna Bridge	160:5571c4ff569f	2147	Only values from 0..7 are used.
Anna Bridge	160:5571c4ff569f	2148	In case of a conflict between priority grouping and available
Anna Bridge	160:5571c4ff569f	2149	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Anna Bridge	160:5571c4ff569f	2150	\param [in] PriorityGroup Priority grouping field.
Anna Bridge	160:5571c4ff569f	2151	*/
Anna Bridge	160:5571c4ff569f	2152	__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Anna Bridge	160:5571c4ff569f	2153	{
Anna Bridge	160:5571c4ff569f	2154	uint32_t reg_value;
Anna Bridge	160:5571c4ff569f	2155	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Anna Bridge	160:5571c4ff569f	2156
Anna Bridge	160:5571c4ff569f	2157	reg_value = SCB->AIRCR; /* read old register configuration */
Anna Bridge	160:5571c4ff569f	2158	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
Anna Bridge	160:5571c4ff569f	2159	reg_value = (reg_value \|
Anna Bridge	160:5571c4ff569f	2160	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
Anna Bridge	169:a7c7b631e539	2161	(PriorityGroupTmp << 8U) ); /* Insert write key and priority group */
Anna Bridge	160:5571c4ff569f	2162	SCB->AIRCR = reg_value;
Anna Bridge	160:5571c4ff569f	2163	}
Anna Bridge	160:5571c4ff569f	2164
Anna Bridge	160:5571c4ff569f	2165
Anna Bridge	160:5571c4ff569f	2166	/**
Anna Bridge	160:5571c4ff569f	2167	\brief Get Priority Grouping
Anna Bridge	160:5571c4ff569f	2168	\details Reads the priority grouping field from the NVIC Interrupt Controller.
Anna Bridge	160:5571c4ff569f	2169	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
Anna Bridge	160:5571c4ff569f	2170	*/
Anna Bridge	160:5571c4ff569f	2171	__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
Anna Bridge	160:5571c4ff569f	2172	{
Anna Bridge	160:5571c4ff569f	2173	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
Anna Bridge	160:5571c4ff569f	2174	}
Anna Bridge	160:5571c4ff569f	2175
Anna Bridge	160:5571c4ff569f	2176
Anna Bridge	160:5571c4ff569f	2177	/**
Anna Bridge	160:5571c4ff569f	2178	\brief Enable Interrupt
Anna Bridge	160:5571c4ff569f	2179	\details Enables a device specific interrupt in the NVIC interrupt controller.
Anna Bridge	160:5571c4ff569f	2180	\param [in] IRQn Device specific interrupt number.
Anna Bridge	160:5571c4ff569f	2181	\note IRQn must not be negative.
Anna Bridge	160:5571c4ff569f	2182	*/
Anna Bridge	160:5571c4ff569f	2183	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Anna Bridge	160:5571c4ff569f	2184	{
Anna Bridge	160:5571c4ff569f	2185	if ((int32_t)(IRQn) >= 0)
Anna Bridge	160:5571c4ff569f	2186	{
Anna Bridge	169:a7c7b631e539	2187	NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge	160:5571c4ff569f	2188	}
Anna Bridge	160:5571c4ff569f	2189	}
Anna Bridge	160:5571c4ff569f	2190
Anna Bridge	160:5571c4ff569f	2191
Anna Bridge	160:5571c4ff569f	2192	/**
Anna Bridge	160:5571c4ff569f	2193	\brief Get Interrupt Enable status
Anna Bridge	160:5571c4ff569f	2194	\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
Anna Bridge	160:5571c4ff569f	2195	\param [in] IRQn Device specific interrupt number.
Anna Bridge	160:5571c4ff569f	2196	\return 0 Interrupt is not enabled.
Anna Bridge	160:5571c4ff569f	2197	\return 1 Interrupt is enabled.
Anna Bridge	160:5571c4ff569f	2198	\note IRQn must not be negative.
Anna Bridge	160:5571c4ff569f	2199	*/
Anna Bridge	160:5571c4ff569f	2200	__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Anna Bridge	160:5571c4ff569f	2201	{
Anna Bridge	160:5571c4ff569f	2202	if ((int32_t)(IRQn) >= 0)
Anna Bridge	160:5571c4ff569f	2203	{
Anna Bridge	169:a7c7b631e539	2204	return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge	160:5571c4ff569f	2205	}
Anna Bridge	160:5571c4ff569f	2206	else
Anna Bridge	160:5571c4ff569f	2207	{
Anna Bridge	160:5571c4ff569f	2208	return(0U);
Anna Bridge	160:5571c4ff569f	2209	}
Anna Bridge	160:5571c4ff569f	2210	}
Anna Bridge	160:5571c4ff569f	2211
Anna Bridge	160:5571c4ff569f	2212
Anna Bridge	160:5571c4ff569f	2213	/**
Anna Bridge	160:5571c4ff569f	2214	\brief Disable Interrupt
Anna Bridge	160:5571c4ff569f	2215	\details Disables a device specific interrupt in the NVIC interrupt controller.
Anna Bridge	160:5571c4ff569f	2216	\param [in] IRQn Device specific interrupt number.
Anna Bridge	160:5571c4ff569f	2217	\note IRQn must not be negative.
Anna Bridge	160:5571c4ff569f	2218	*/
Anna Bridge	160:5571c4ff569f	2219	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Anna Bridge	160:5571c4ff569f	2220	{
Anna Bridge	160:5571c4ff569f	2221	if ((int32_t)(IRQn) >= 0)
Anna Bridge	160:5571c4ff569f	2222	{
Anna Bridge	169:a7c7b631e539	2223	NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge	160:5571c4ff569f	2224	__DSB();
Anna Bridge	160:5571c4ff569f	2225	__ISB();
Anna Bridge	160:5571c4ff569f	2226	}
Anna Bridge	160:5571c4ff569f	2227	}
Anna Bridge	160:5571c4ff569f	2228
Anna Bridge	160:5571c4ff569f	2229
Anna Bridge	160:5571c4ff569f	2230	/**
Anna Bridge	160:5571c4ff569f	2231	\brief Get Pending Interrupt
Anna Bridge	160:5571c4ff569f	2232	\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
Anna Bridge	160:5571c4ff569f	2233	\param [in] IRQn Device specific interrupt number.
Anna Bridge	160:5571c4ff569f	2234	\return 0 Interrupt status is not pending.
Anna Bridge	160:5571c4ff569f	2235	\return 1 Interrupt status is pending.
Anna Bridge	160:5571c4ff569f	2236	\note IRQn must not be negative.
Anna Bridge	160:5571c4ff569f	2237	*/
Anna Bridge	160:5571c4ff569f	2238	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Anna Bridge	160:5571c4ff569f	2239	{
Anna Bridge	160:5571c4ff569f	2240	if ((int32_t)(IRQn) >= 0)
Anna Bridge	160:5571c4ff569f	2241	{
Anna Bridge	169:a7c7b631e539	2242	return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge	160:5571c4ff569f	2243	}
Anna Bridge	160:5571c4ff569f	2244	else
Anna Bridge	160:5571c4ff569f	2245	{
Anna Bridge	160:5571c4ff569f	2246	return(0U);
Anna Bridge	160:5571c4ff569f	2247	}
Anna Bridge	160:5571c4ff569f	2248	}
Anna Bridge	160:5571c4ff569f	2249
Anna Bridge	160:5571c4ff569f	2250
Anna Bridge	160:5571c4ff569f	2251	/**
Anna Bridge	160:5571c4ff569f	2252	\brief Set Pending Interrupt
Anna Bridge	160:5571c4ff569f	2253	\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
Anna Bridge	160:5571c4ff569f	2254	\param [in] IRQn Device specific interrupt number.
Anna Bridge	160:5571c4ff569f	2255	\note IRQn must not be negative.
Anna Bridge	160:5571c4ff569f	2256	*/
Anna Bridge	160:5571c4ff569f	2257	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Anna Bridge	160:5571c4ff569f	2258	{
Anna Bridge	160:5571c4ff569f	2259	if ((int32_t)(IRQn) >= 0)
Anna Bridge	160:5571c4ff569f	2260	{
Anna Bridge	169:a7c7b631e539	2261	NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge	160:5571c4ff569f	2262	}
Anna Bridge	160:5571c4ff569f	2263	}
Anna Bridge	160:5571c4ff569f	2264
Anna Bridge	160:5571c4ff569f	2265
Anna Bridge	160:5571c4ff569f	2266	/**
Anna Bridge	160:5571c4ff569f	2267	\brief Clear Pending Interrupt
Anna Bridge	160:5571c4ff569f	2268	\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
Anna Bridge	160:5571c4ff569f	2269	\param [in] IRQn Device specific interrupt number.
Anna Bridge	160:5571c4ff569f	2270	\note IRQn must not be negative.
Anna Bridge	160:5571c4ff569f	2271	*/
Anna Bridge	160:5571c4ff569f	2272	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Anna Bridge	160:5571c4ff569f	2273	{
Anna Bridge	160:5571c4ff569f	2274	if ((int32_t)(IRQn) >= 0)
Anna Bridge	160:5571c4ff569f	2275	{
Anna Bridge	169:a7c7b631e539	2276	NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge	160:5571c4ff569f	2277	}
Anna Bridge	160:5571c4ff569f	2278	}
Anna Bridge	160:5571c4ff569f	2279
Anna Bridge	160:5571c4ff569f	2280
Anna Bridge	160:5571c4ff569f	2281	/**
Anna Bridge	160:5571c4ff569f	2282	\brief Get Active Interrupt
Anna Bridge	160:5571c4ff569f	2283	\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
Anna Bridge	160:5571c4ff569f	2284	\param [in] IRQn Device specific interrupt number.
Anna Bridge	160:5571c4ff569f	2285	\return 0 Interrupt status is not active.
Anna Bridge	160:5571c4ff569f	2286	\return 1 Interrupt status is active.
Anna Bridge	160:5571c4ff569f	2287	\note IRQn must not be negative.
Anna Bridge	160:5571c4ff569f	2288	*/
Anna Bridge	160:5571c4ff569f	2289	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
Anna Bridge	160:5571c4ff569f	2290	{
Anna Bridge	160:5571c4ff569f	2291	if ((int32_t)(IRQn) >= 0)
Anna Bridge	160:5571c4ff569f	2292	{
Anna Bridge	169:a7c7b631e539	2293	return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge	160:5571c4ff569f	2294	}
Anna Bridge	160:5571c4ff569f	2295	else
Anna Bridge	160:5571c4ff569f	2296	{
Anna Bridge	160:5571c4ff569f	2297	return(0U);
Anna Bridge	160:5571c4ff569f	2298	}
Anna Bridge	160:5571c4ff569f	2299	}
Anna Bridge	160:5571c4ff569f	2300
Anna Bridge	160:5571c4ff569f	2301
Anna Bridge	160:5571c4ff569f	2302	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Anna Bridge	160:5571c4ff569f	2303	/**
Anna Bridge	160:5571c4ff569f	2304	\brief Get Interrupt Target State
Anna Bridge	160:5571c4ff569f	2305	\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
Anna Bridge	160:5571c4ff569f	2306	\param [in] IRQn Device specific interrupt number.
Anna Bridge	160:5571c4ff569f	2307	\return 0 if interrupt is assigned to Secure
Anna Bridge	160:5571c4ff569f	2308	\return 1 if interrupt is assigned to Non Secure
Anna Bridge	160:5571c4ff569f	2309	\note IRQn must not be negative.
Anna Bridge	160:5571c4ff569f	2310	*/
Anna Bridge	160:5571c4ff569f	2311	__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
Anna Bridge	160:5571c4ff569f	2312	{
Anna Bridge	160:5571c4ff569f	2313	if ((int32_t)(IRQn) >= 0)
Anna Bridge	160:5571c4ff569f	2314	{
Anna Bridge	169:a7c7b631e539	2315	return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge	160:5571c4ff569f	2316	}
Anna Bridge	160:5571c4ff569f	2317	else
Anna Bridge	160:5571c4ff569f	2318	{
Anna Bridge	160:5571c4ff569f	2319	return(0U);
Anna Bridge	160:5571c4ff569f	2320	}
Anna Bridge	160:5571c4ff569f	2321	}
Anna Bridge	160:5571c4ff569f	2322
Anna Bridge	160:5571c4ff569f	2323
Anna Bridge	160:5571c4ff569f	2324	/**
Anna Bridge	160:5571c4ff569f	2325	\brief Set Interrupt Target State
Anna Bridge	160:5571c4ff569f	2326	\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
Anna Bridge	160:5571c4ff569f	2327	\param [in] IRQn Device specific interrupt number.
Anna Bridge	160:5571c4ff569f	2328	\return 0 if interrupt is assigned to Secure
Anna Bridge	160:5571c4ff569f	2329	1 if interrupt is assigned to Non Secure
Anna Bridge	160:5571c4ff569f	2330	\note IRQn must not be negative.
Anna Bridge	160:5571c4ff569f	2331	*/
Anna Bridge	160:5571c4ff569f	2332	__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
Anna Bridge	160:5571c4ff569f	2333	{
Anna Bridge	160:5571c4ff569f	2334	if ((int32_t)(IRQn) >= 0)
Anna Bridge	160:5571c4ff569f	2335	{
Anna Bridge	169:a7c7b631e539	2336	NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] \|= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
Anna Bridge	169:a7c7b631e539	2337	return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge	160:5571c4ff569f	2338	}
Anna Bridge	160:5571c4ff569f	2339	else
Anna Bridge	160:5571c4ff569f	2340	{
Anna Bridge	160:5571c4ff569f	2341	return(0U);
Anna Bridge	160:5571c4ff569f	2342	}
Anna Bridge	160:5571c4ff569f	2343	}
Anna Bridge	160:5571c4ff569f	2344
Anna Bridge	160:5571c4ff569f	2345
Anna Bridge	160:5571c4ff569f	2346	/**
Anna Bridge	160:5571c4ff569f	2347	\brief Clear Interrupt Target State
Anna Bridge	160:5571c4ff569f	2348	\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
Anna Bridge	160:5571c4ff569f	2349	\param [in] IRQn Device specific interrupt number.
Anna Bridge	160:5571c4ff569f	2350	\return 0 if interrupt is assigned to Secure
Anna Bridge	160:5571c4ff569f	2351	1 if interrupt is assigned to Non Secure
Anna Bridge	160:5571c4ff569f	2352	\note IRQn must not be negative.
Anna Bridge	160:5571c4ff569f	2353	*/
Anna Bridge	160:5571c4ff569f	2354	__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
Anna Bridge	160:5571c4ff569f	2355	{
Anna Bridge	160:5571c4ff569f	2356	if ((int32_t)(IRQn) >= 0)
Anna Bridge	160:5571c4ff569f	2357	{
Anna Bridge	169:a7c7b631e539	2358	NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
Anna Bridge	169:a7c7b631e539	2359	return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge	160:5571c4ff569f	2360	}
Anna Bridge	160:5571c4ff569f	2361	else
Anna Bridge	160:5571c4ff569f	2362	{
Anna Bridge	160:5571c4ff569f	2363	return(0U);
Anna Bridge	160:5571c4ff569f	2364	}
Anna Bridge	160:5571c4ff569f	2365	}
Anna Bridge	160:5571c4ff569f	2366	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
Anna Bridge	160:5571c4ff569f	2367
Anna Bridge	160:5571c4ff569f	2368
Anna Bridge	160:5571c4ff569f	2369	/**
Anna Bridge	160:5571c4ff569f	2370	\brief Set Interrupt Priority
Anna Bridge	160:5571c4ff569f	2371	\details Sets the priority of a device specific interrupt or a processor exception.
Anna Bridge	160:5571c4ff569f	2372	The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge	160:5571c4ff569f	2373	or negative to specify a processor exception.
Anna Bridge	160:5571c4ff569f	2374	\param [in] IRQn Interrupt number.
Anna Bridge	160:5571c4ff569f	2375	\param [in] priority Priority to set.
Anna Bridge	160:5571c4ff569f	2376	\note The priority cannot be set for every processor exception.
Anna Bridge	160:5571c4ff569f	2377	*/
Anna Bridge	160:5571c4ff569f	2378	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Anna Bridge	160:5571c4ff569f	2379	{
Anna Bridge	160:5571c4ff569f	2380	if ((int32_t)(IRQn) >= 0)
Anna Bridge	160:5571c4ff569f	2381	{
Anna Bridge	169:a7c7b631e539	2382	NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Anna Bridge	160:5571c4ff569f	2383	}
Anna Bridge	160:5571c4ff569f	2384	else
Anna Bridge	160:5571c4ff569f	2385	{
Anna Bridge	169:a7c7b631e539	2386	SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Anna Bridge	160:5571c4ff569f	2387	}
Anna Bridge	160:5571c4ff569f	2388	}
Anna Bridge	160:5571c4ff569f	2389
Anna Bridge	160:5571c4ff569f	2390
Anna Bridge	160:5571c4ff569f	2391	/**
Anna Bridge	160:5571c4ff569f	2392	\brief Get Interrupt Priority
Anna Bridge	160:5571c4ff569f	2393	\details Reads the priority of a device specific interrupt or a processor exception.
Anna Bridge	160:5571c4ff569f	2394	The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge	160:5571c4ff569f	2395	or negative to specify a processor exception.
Anna Bridge	160:5571c4ff569f	2396	\param [in] IRQn Interrupt number.
Anna Bridge	160:5571c4ff569f	2397	\return Interrupt Priority.
Anna Bridge	160:5571c4ff569f	2398	Value is aligned automatically to the implemented priority bits of the microcontroller.
Anna Bridge	160:5571c4ff569f	2399	*/
Anna Bridge	160:5571c4ff569f	2400	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Anna Bridge	160:5571c4ff569f	2401	{
Anna Bridge	160:5571c4ff569f	2402
Anna Bridge	160:5571c4ff569f	2403	if ((int32_t)(IRQn) >= 0)
Anna Bridge	160:5571c4ff569f	2404	{
Anna Bridge	169:a7c7b631e539	2405	return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
Anna Bridge	160:5571c4ff569f	2406	}
Anna Bridge	160:5571c4ff569f	2407	else
Anna Bridge	160:5571c4ff569f	2408	{
Anna Bridge	169:a7c7b631e539	2409	return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
Anna Bridge	160:5571c4ff569f	2410	}
Anna Bridge	160:5571c4ff569f	2411	}
Anna Bridge	160:5571c4ff569f	2412
Anna Bridge	160:5571c4ff569f	2413
Anna Bridge	160:5571c4ff569f	2414	/**
Anna Bridge	160:5571c4ff569f	2415	\brief Encode Priority
Anna Bridge	160:5571c4ff569f	2416	\details Encodes the priority for an interrupt with the given priority group,
Anna Bridge	160:5571c4ff569f	2417	preemptive priority value, and subpriority value.
Anna Bridge	160:5571c4ff569f	2418	In case of a conflict between priority grouping and available
Anna Bridge	160:5571c4ff569f	2419	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Anna Bridge	160:5571c4ff569f	2420	\param [in] PriorityGroup Used priority group.
Anna Bridge	160:5571c4ff569f	2421	\param [in] PreemptPriority Preemptive priority value (starting from 0).
Anna Bridge	160:5571c4ff569f	2422	\param [in] SubPriority Subpriority value (starting from 0).
Anna Bridge	160:5571c4ff569f	2423	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
Anna Bridge	160:5571c4ff569f	2424	*/
Anna Bridge	160:5571c4ff569f	2425	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Anna Bridge	160:5571c4ff569f	2426	{
Anna Bridge	160:5571c4ff569f	2427	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Anna Bridge	160:5571c4ff569f	2428	uint32_t PreemptPriorityBits;
Anna Bridge	160:5571c4ff569f	2429	uint32_t SubPriorityBits;
Anna Bridge	160:5571c4ff569f	2430
Anna Bridge	160:5571c4ff569f	2431	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Anna Bridge	160:5571c4ff569f	2432	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Anna Bridge	160:5571c4ff569f	2433
Anna Bridge	160:5571c4ff569f	2434	return (
Anna Bridge	160:5571c4ff569f	2435	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
Anna Bridge	160:5571c4ff569f	2436	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
Anna Bridge	160:5571c4ff569f	2437	);
Anna Bridge	160:5571c4ff569f	2438	}
Anna Bridge	160:5571c4ff569f	2439
Anna Bridge	160:5571c4ff569f	2440
Anna Bridge	160:5571c4ff569f	2441	/**
Anna Bridge	160:5571c4ff569f	2442	\brief Decode Priority
Anna Bridge	160:5571c4ff569f	2443	\details Decodes an interrupt priority value with a given priority group to
Anna Bridge	160:5571c4ff569f	2444	preemptive priority value and subpriority value.
Anna Bridge	160:5571c4ff569f	2445	In case of a conflict between priority grouping and available
Anna Bridge	160:5571c4ff569f	2446	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
Anna Bridge	160:5571c4ff569f	2447	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
Anna Bridge	160:5571c4ff569f	2448	\param [in] PriorityGroup Used priority group.
Anna Bridge	160:5571c4ff569f	2449	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
Anna Bridge	160:5571c4ff569f	2450	\param [out] pSubPriority Subpriority value (starting from 0).
Anna Bridge	160:5571c4ff569f	2451	*/
Anna Bridge	160:5571c4ff569f	2452	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
Anna Bridge	160:5571c4ff569f	2453	{
Anna Bridge	160:5571c4ff569f	2454	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Anna Bridge	160:5571c4ff569f	2455	uint32_t PreemptPriorityBits;
Anna Bridge	160:5571c4ff569f	2456	uint32_t SubPriorityBits;
Anna Bridge	160:5571c4ff569f	2457
Anna Bridge	160:5571c4ff569f	2458	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Anna Bridge	160:5571c4ff569f	2459	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Anna Bridge	160:5571c4ff569f	2460
Anna Bridge	160:5571c4ff569f	2461	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
Anna Bridge	160:5571c4ff569f	2462	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
Anna Bridge	160:5571c4ff569f	2463	}
Anna Bridge	160:5571c4ff569f	2464
Anna Bridge	160:5571c4ff569f	2465
Anna Bridge	160:5571c4ff569f	2466	/**
Anna Bridge	160:5571c4ff569f	2467	\brief Set Interrupt Vector
Anna Bridge	160:5571c4ff569f	2468	\details Sets an interrupt vector in SRAM based interrupt vector table.
Anna Bridge	160:5571c4ff569f	2469	The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge	160:5571c4ff569f	2470	or negative to specify a processor exception.
Anna Bridge	160:5571c4ff569f	2471	VTOR must been relocated to SRAM before.
Anna Bridge	160:5571c4ff569f	2472	\param [in] IRQn Interrupt number
Anna Bridge	160:5571c4ff569f	2473	\param [in] vector Address of interrupt handler function
Anna Bridge	160:5571c4ff569f	2474	*/
Anna Bridge	160:5571c4ff569f	2475	__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Anna Bridge	160:5571c4ff569f	2476	{
Anna Bridge	160:5571c4ff569f	2477	uint32_t vectors = (uint32_t )SCB->VTOR;
Anna Bridge	160:5571c4ff569f	2478	vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
Anna Bridge	160:5571c4ff569f	2479	}
Anna Bridge	160:5571c4ff569f	2480
Anna Bridge	160:5571c4ff569f	2481
Anna Bridge	160:5571c4ff569f	2482	/**
Anna Bridge	160:5571c4ff569f	2483	\brief Get Interrupt Vector
Anna Bridge	160:5571c4ff569f	2484	\details Reads an interrupt vector from interrupt vector table.
Anna Bridge	160:5571c4ff569f	2485	The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge	160:5571c4ff569f	2486	or negative to specify a processor exception.
Anna Bridge	160:5571c4ff569f	2487	\param [in] IRQn Interrupt number.
Anna Bridge	160:5571c4ff569f	2488	\return Address of interrupt handler function
Anna Bridge	160:5571c4ff569f	2489	*/
Anna Bridge	160:5571c4ff569f	2490	__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Anna Bridge	160:5571c4ff569f	2491	{
Anna Bridge	160:5571c4ff569f	2492	uint32_t vectors = (uint32_t )SCB->VTOR;
Anna Bridge	160:5571c4ff569f	2493	return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
Anna Bridge	160:5571c4ff569f	2494	}
Anna Bridge	160:5571c4ff569f	2495
Anna Bridge	160:5571c4ff569f	2496
Anna Bridge	160:5571c4ff569f	2497	/**
Anna Bridge	160:5571c4ff569f	2498	\brief System Reset
Anna Bridge	160:5571c4ff569f	2499	\details Initiates a system reset request to reset the MCU.
Anna Bridge	160:5571c4ff569f	2500	*/
Anna Bridge	160:5571c4ff569f	2501	__STATIC_INLINE void __NVIC_SystemReset(void)
Anna Bridge	160:5571c4ff569f	2502	{
Anna Bridge	160:5571c4ff569f	2503	__DSB(); /* Ensure all outstanding memory accesses included
Anna Bridge	160:5571c4ff569f	2504	buffered write are completed before reset */
Anna Bridge	160:5571c4ff569f	2505	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
Anna Bridge	160:5571c4ff569f	2506	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
Anna Bridge	160:5571c4ff569f	2507	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
Anna Bridge	160:5571c4ff569f	2508	__DSB(); /* Ensure completion of memory access */
Anna Bridge	160:5571c4ff569f	2509
Anna Bridge	160:5571c4ff569f	2510	for(;;) /* wait until reset */
Anna Bridge	160:5571c4ff569f	2511	{
Anna Bridge	160:5571c4ff569f	2512	__NOP();
Anna Bridge	160:5571c4ff569f	2513	}
Anna Bridge	160:5571c4ff569f	2514	}
Anna Bridge	160:5571c4ff569f	2515
Anna Bridge	160:5571c4ff569f	2516	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Anna Bridge	160:5571c4ff569f	2517	/**
Anna Bridge	160:5571c4ff569f	2518	\brief Set Priority Grouping (non-secure)
Anna Bridge	160:5571c4ff569f	2519	\details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
Anna Bridge	160:5571c4ff569f	2520	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Anna Bridge	160:5571c4ff569f	2521	Only values from 0..7 are used.
Anna Bridge	160:5571c4ff569f	2522	In case of a conflict between priority grouping and available
Anna Bridge	160:5571c4ff569f	2523	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Anna Bridge	160:5571c4ff569f	2524	\param [in] PriorityGroup Priority grouping field.
Anna Bridge	160:5571c4ff569f	2525	*/
Anna Bridge	160:5571c4ff569f	2526	__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
Anna Bridge	160:5571c4ff569f	2527	{
Anna Bridge	160:5571c4ff569f	2528	uint32_t reg_value;
Anna Bridge	160:5571c4ff569f	2529	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Anna Bridge	160:5571c4ff569f	2530
Anna Bridge	169:a7c7b631e539	2531	reg_value = SCB_NS->AIRCR; /* read old register configuration */
Anna Bridge	169:a7c7b631e539	2532	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
Anna Bridge	160:5571c4ff569f	2533	reg_value = (reg_value \|
Anna Bridge	160:5571c4ff569f	2534	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
Anna Bridge	169:a7c7b631e539	2535	(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
Anna Bridge	160:5571c4ff569f	2536	SCB_NS->AIRCR = reg_value;
Anna Bridge	160:5571c4ff569f	2537	}
Anna Bridge	160:5571c4ff569f	2538
Anna Bridge	160:5571c4ff569f	2539
Anna Bridge	160:5571c4ff569f	2540	/**
Anna Bridge	160:5571c4ff569f	2541	\brief Get Priority Grouping (non-secure)
Anna Bridge	160:5571c4ff569f	2542	\details Reads the priority grouping field from the non-secure NVIC when in secure state.
Anna Bridge	160:5571c4ff569f	2543	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
Anna Bridge	160:5571c4ff569f	2544	*/
Anna Bridge	160:5571c4ff569f	2545	__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
Anna Bridge	160:5571c4ff569f	2546	{
Anna Bridge	160:5571c4ff569f	2547	return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
Anna Bridge	160:5571c4ff569f	2548	}
Anna Bridge	160:5571c4ff569f	2549
Anna Bridge	160:5571c4ff569f	2550
Anna Bridge	160:5571c4ff569f	2551	/**
Anna Bridge	160:5571c4ff569f	2552	\brief Enable Interrupt (non-secure)
Anna Bridge	160:5571c4ff569f	2553	\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
Anna Bridge	160:5571c4ff569f	2554	\param [in] IRQn Device specific interrupt number.
Anna Bridge	160:5571c4ff569f	2555	\note IRQn must not be negative.
Anna Bridge	160:5571c4ff569f	2556	*/
Anna Bridge	160:5571c4ff569f	2557	__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
Anna Bridge	160:5571c4ff569f	2558	{
Anna Bridge	160:5571c4ff569f	2559	if ((int32_t)(IRQn) >= 0)
Anna Bridge	160:5571c4ff569f	2560	{
Anna Bridge	169:a7c7b631e539	2561	NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge	160:5571c4ff569f	2562	}
Anna Bridge	160:5571c4ff569f	2563	}
Anna Bridge	160:5571c4ff569f	2564
Anna Bridge	160:5571c4ff569f	2565
Anna Bridge	160:5571c4ff569f	2566	/**
Anna Bridge	160:5571c4ff569f	2567	\brief Get Interrupt Enable status (non-secure)
Anna Bridge	160:5571c4ff569f	2568	\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
Anna Bridge	160:5571c4ff569f	2569	\param [in] IRQn Device specific interrupt number.
Anna Bridge	160:5571c4ff569f	2570	\return 0 Interrupt is not enabled.
Anna Bridge	160:5571c4ff569f	2571	\return 1 Interrupt is enabled.
Anna Bridge	160:5571c4ff569f	2572	\note IRQn must not be negative.
Anna Bridge	160:5571c4ff569f	2573	*/
Anna Bridge	160:5571c4ff569f	2574	__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
Anna Bridge	160:5571c4ff569f	2575	{
Anna Bridge	160:5571c4ff569f	2576	if ((int32_t)(IRQn) >= 0)
Anna Bridge	160:5571c4ff569f	2577	{
Anna Bridge	169:a7c7b631e539	2578	return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge	160:5571c4ff569f	2579	}
Anna Bridge	160:5571c4ff569f	2580	else
Anna Bridge	160:5571c4ff569f	2581	{
Anna Bridge	160:5571c4ff569f	2582	return(0U);
Anna Bridge	160:5571c4ff569f	2583	}
Anna Bridge	160:5571c4ff569f	2584	}
Anna Bridge	160:5571c4ff569f	2585
Anna Bridge	160:5571c4ff569f	2586
Anna Bridge	160:5571c4ff569f	2587	/**
Anna Bridge	160:5571c4ff569f	2588	\brief Disable Interrupt (non-secure)
Anna Bridge	160:5571c4ff569f	2589	\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
Anna Bridge	160:5571c4ff569f	2590	\param [in] IRQn Device specific interrupt number.
Anna Bridge	160:5571c4ff569f	2591	\note IRQn must not be negative.
Anna Bridge	160:5571c4ff569f	2592	*/
Anna Bridge	160:5571c4ff569f	2593	__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
Anna Bridge	160:5571c4ff569f	2594	{
Anna Bridge	160:5571c4ff569f	2595	if ((int32_t)(IRQn) >= 0)
Anna Bridge	160:5571c4ff569f	2596	{
Anna Bridge	169:a7c7b631e539	2597	NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge	160:5571c4ff569f	2598	}
Anna Bridge	160:5571c4ff569f	2599	}
Anna Bridge	160:5571c4ff569f	2600
Anna Bridge	160:5571c4ff569f	2601
Anna Bridge	160:5571c4ff569f	2602	/**
Anna Bridge	160:5571c4ff569f	2603	\brief Get Pending Interrupt (non-secure)
Anna Bridge	160:5571c4ff569f	2604	\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
Anna Bridge	160:5571c4ff569f	2605	\param [in] IRQn Device specific interrupt number.
Anna Bridge	160:5571c4ff569f	2606	\return 0 Interrupt status is not pending.
Anna Bridge	160:5571c4ff569f	2607	\return 1 Interrupt status is pending.
Anna Bridge	160:5571c4ff569f	2608	\note IRQn must not be negative.
Anna Bridge	160:5571c4ff569f	2609	*/
Anna Bridge	160:5571c4ff569f	2610	__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
Anna Bridge	160:5571c4ff569f	2611	{
Anna Bridge	160:5571c4ff569f	2612	if ((int32_t)(IRQn) >= 0)
Anna Bridge	160:5571c4ff569f	2613	{
Anna Bridge	169:a7c7b631e539	2614	return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge	160:5571c4ff569f	2615	}
Anna Bridge	160:5571c4ff569f	2616	else
Anna Bridge	160:5571c4ff569f	2617	{
Anna Bridge	160:5571c4ff569f	2618	return(0U);
Anna Bridge	160:5571c4ff569f	2619	}
Anna Bridge	160:5571c4ff569f	2620	}
Anna Bridge	160:5571c4ff569f	2621
Anna Bridge	160:5571c4ff569f	2622
Anna Bridge	160:5571c4ff569f	2623	/**
Anna Bridge	160:5571c4ff569f	2624	\brief Set Pending Interrupt (non-secure)
Anna Bridge	160:5571c4ff569f	2625	\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
Anna Bridge	160:5571c4ff569f	2626	\param [in] IRQn Device specific interrupt number.
Anna Bridge	160:5571c4ff569f	2627	\note IRQn must not be negative.
Anna Bridge	160:5571c4ff569f	2628	*/
Anna Bridge	160:5571c4ff569f	2629	__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
Anna Bridge	160:5571c4ff569f	2630	{
Anna Bridge	160:5571c4ff569f	2631	if ((int32_t)(IRQn) >= 0)
Anna Bridge	160:5571c4ff569f	2632	{
Anna Bridge	169:a7c7b631e539	2633	NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge	160:5571c4ff569f	2634	}
Anna Bridge	160:5571c4ff569f	2635	}
Anna Bridge	160:5571c4ff569f	2636
Anna Bridge	160:5571c4ff569f	2637
Anna Bridge	160:5571c4ff569f	2638	/**
Anna Bridge	160:5571c4ff569f	2639	\brief Clear Pending Interrupt (non-secure)
Anna Bridge	160:5571c4ff569f	2640	\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
Anna Bridge	160:5571c4ff569f	2641	\param [in] IRQn Device specific interrupt number.
Anna Bridge	160:5571c4ff569f	2642	\note IRQn must not be negative.
Anna Bridge	160:5571c4ff569f	2643	*/
Anna Bridge	160:5571c4ff569f	2644	__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
Anna Bridge	160:5571c4ff569f	2645	{
Anna Bridge	160:5571c4ff569f	2646	if ((int32_t)(IRQn) >= 0)
Anna Bridge	160:5571c4ff569f	2647	{
Anna Bridge	169:a7c7b631e539	2648	NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge	160:5571c4ff569f	2649	}
Anna Bridge	160:5571c4ff569f	2650	}
Anna Bridge	160:5571c4ff569f	2651
Anna Bridge	160:5571c4ff569f	2652
Anna Bridge	160:5571c4ff569f	2653	/**
Anna Bridge	160:5571c4ff569f	2654	\brief Get Active Interrupt (non-secure)
Anna Bridge	160:5571c4ff569f	2655	\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
Anna Bridge	160:5571c4ff569f	2656	\param [in] IRQn Device specific interrupt number.
Anna Bridge	160:5571c4ff569f	2657	\return 0 Interrupt status is not active.
Anna Bridge	160:5571c4ff569f	2658	\return 1 Interrupt status is active.
Anna Bridge	160:5571c4ff569f	2659	\note IRQn must not be negative.
Anna Bridge	160:5571c4ff569f	2660	*/
Anna Bridge	160:5571c4ff569f	2661	__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
Anna Bridge	160:5571c4ff569f	2662	{
Anna Bridge	160:5571c4ff569f	2663	if ((int32_t)(IRQn) >= 0)
Anna Bridge	160:5571c4ff569f	2664	{
Anna Bridge	169:a7c7b631e539	2665	return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge	160:5571c4ff569f	2666	}
Anna Bridge	160:5571c4ff569f	2667	else
Anna Bridge	160:5571c4ff569f	2668	{
Anna Bridge	160:5571c4ff569f	2669	return(0U);
Anna Bridge	160:5571c4ff569f	2670	}
Anna Bridge	160:5571c4ff569f	2671	}
Anna Bridge	160:5571c4ff569f	2672
Anna Bridge	160:5571c4ff569f	2673
Anna Bridge	160:5571c4ff569f	2674	/**
Anna Bridge	160:5571c4ff569f	2675	\brief Set Interrupt Priority (non-secure)
Anna Bridge	160:5571c4ff569f	2676	\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
Anna Bridge	160:5571c4ff569f	2677	The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge	160:5571c4ff569f	2678	or negative to specify a processor exception.
Anna Bridge	160:5571c4ff569f	2679	\param [in] IRQn Interrupt number.
Anna Bridge	160:5571c4ff569f	2680	\param [in] priority Priority to set.
Anna Bridge	160:5571c4ff569f	2681	\note The priority cannot be set for every non-secure processor exception.
Anna Bridge	160:5571c4ff569f	2682	*/
Anna Bridge	160:5571c4ff569f	2683	__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
Anna Bridge	160:5571c4ff569f	2684	{
Anna Bridge	160:5571c4ff569f	2685	if ((int32_t)(IRQn) >= 0)
Anna Bridge	160:5571c4ff569f	2686	{
Anna Bridge	169:a7c7b631e539	2687	NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Anna Bridge	160:5571c4ff569f	2688	}
Anna Bridge	160:5571c4ff569f	2689	else
Anna Bridge	160:5571c4ff569f	2690	{
Anna Bridge	169:a7c7b631e539	2691	SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Anna Bridge	160:5571c4ff569f	2692	}
Anna Bridge	160:5571c4ff569f	2693	}
Anna Bridge	160:5571c4ff569f	2694
Anna Bridge	160:5571c4ff569f	2695
Anna Bridge	160:5571c4ff569f	2696	/**
Anna Bridge	160:5571c4ff569f	2697	\brief Get Interrupt Priority (non-secure)
Anna Bridge	160:5571c4ff569f	2698	\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
Anna Bridge	160:5571c4ff569f	2699	The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge	160:5571c4ff569f	2700	or negative to specify a processor exception.
Anna Bridge	160:5571c4ff569f	2701	\param [in] IRQn Interrupt number.
Anna Bridge	160:5571c4ff569f	2702	\return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
Anna Bridge	160:5571c4ff569f	2703	*/
Anna Bridge	160:5571c4ff569f	2704	__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
Anna Bridge	160:5571c4ff569f	2705	{
Anna Bridge	160:5571c4ff569f	2706
Anna Bridge	160:5571c4ff569f	2707	if ((int32_t)(IRQn) >= 0)
Anna Bridge	160:5571c4ff569f	2708	{
Anna Bridge	169:a7c7b631e539	2709	return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
Anna Bridge	160:5571c4ff569f	2710	}
Anna Bridge	160:5571c4ff569f	2711	else
Anna Bridge	160:5571c4ff569f	2712	{
Anna Bridge	169:a7c7b631e539	2713	return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
Anna Bridge	160:5571c4ff569f	2714	}
Anna Bridge	160:5571c4ff569f	2715	}
Anna Bridge	160:5571c4ff569f	2716	#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
Anna Bridge	160:5571c4ff569f	2717
Anna Bridge	160:5571c4ff569f	2718	/@} end of CMSIS_Core_NVICFunctions /
Anna Bridge	160:5571c4ff569f	2719
Anna Bridge	160:5571c4ff569f	2720	/* ########################## MPU functions #################################### */
Anna Bridge	160:5571c4ff569f	2721
Anna Bridge	160:5571c4ff569f	2722	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge	160:5571c4ff569f	2723
Anna Bridge	160:5571c4ff569f	2724	#include "mpu_armv8.h"
Anna Bridge	160:5571c4ff569f	2725
Anna Bridge	160:5571c4ff569f	2726	#endif
Anna Bridge	160:5571c4ff569f	2727
Anna Bridge	160:5571c4ff569f	2728	/* ########################## FPU functions #################################### */
Anna Bridge	160:5571c4ff569f	2729	/**
Anna Bridge	160:5571c4ff569f	2730	\ingroup CMSIS_Core_FunctionInterface
Anna Bridge	160:5571c4ff569f	2731	\defgroup CMSIS_Core_FpuFunctions FPU Functions
Anna Bridge	160:5571c4ff569f	2732	\brief Function that provides FPU type.
Anna Bridge	160:5571c4ff569f	2733	@{
Anna Bridge	160:5571c4ff569f	2734	*/
Anna Bridge	160:5571c4ff569f	2735
Anna Bridge	160:5571c4ff569f	2736	/**
Anna Bridge	160:5571c4ff569f	2737	\brief get FPU type
Anna Bridge	160:5571c4ff569f	2738	\details returns the FPU type
Anna Bridge	160:5571c4ff569f	2739	\returns
Anna Bridge	160:5571c4ff569f	2740	- \b 0: No FPU
Anna Bridge	160:5571c4ff569f	2741	- \b 1: Single precision FPU
Anna Bridge	160:5571c4ff569f	2742	- \b 2: Double + Single precision FPU
Anna Bridge	160:5571c4ff569f	2743	*/
Anna Bridge	160:5571c4ff569f	2744	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
Anna Bridge	160:5571c4ff569f	2745	{
Anna Bridge	160:5571c4ff569f	2746	uint32_t mvfr0;
Anna Bridge	160:5571c4ff569f	2747
Anna Bridge	160:5571c4ff569f	2748	mvfr0 = FPU->MVFR0;
Anna Bridge	160:5571c4ff569f	2749	if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk \| FPU_MVFR0_Double_precision_Msk)) == 0x220U)
Anna Bridge	160:5571c4ff569f	2750	{
Anna Bridge	160:5571c4ff569f	2751	return 2U; /* Double + Single precision FPU */
Anna Bridge	160:5571c4ff569f	2752	}
Anna Bridge	160:5571c4ff569f	2753	else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk \| FPU_MVFR0_Double_precision_Msk)) == 0x020U)
Anna Bridge	160:5571c4ff569f	2754	{
Anna Bridge	160:5571c4ff569f	2755	return 1U; /* Single precision FPU */
Anna Bridge	160:5571c4ff569f	2756	}
Anna Bridge	160:5571c4ff569f	2757	else
Anna Bridge	160:5571c4ff569f	2758	{
Anna Bridge	160:5571c4ff569f	2759	return 0U; /* No FPU */
Anna Bridge	160:5571c4ff569f	2760	}
Anna Bridge	160:5571c4ff569f	2761	}
Anna Bridge	160:5571c4ff569f	2762
Anna Bridge	160:5571c4ff569f	2763
Anna Bridge	160:5571c4ff569f	2764	/@} end of CMSIS_Core_FpuFunctions /
Anna Bridge	160:5571c4ff569f	2765
Anna Bridge	160:5571c4ff569f	2766
Anna Bridge	160:5571c4ff569f	2767
Anna Bridge	160:5571c4ff569f	2768	/* ########################## SAU functions #################################### */
Anna Bridge	160:5571c4ff569f	2769	/**
Anna Bridge	160:5571c4ff569f	2770	\ingroup CMSIS_Core_FunctionInterface
Anna Bridge	160:5571c4ff569f	2771	\defgroup CMSIS_Core_SAUFunctions SAU Functions
Anna Bridge	160:5571c4ff569f	2772	\brief Functions that configure the SAU.
Anna Bridge	160:5571c4ff569f	2773	@{
Anna Bridge	160:5571c4ff569f	2774	*/
Anna Bridge	160:5571c4ff569f	2775
Anna Bridge	160:5571c4ff569f	2776	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Anna Bridge	160:5571c4ff569f	2777
Anna Bridge	160:5571c4ff569f	2778	/**
Anna Bridge	160:5571c4ff569f	2779	\brief Enable SAU
Anna Bridge	160:5571c4ff569f	2780	\details Enables the Security Attribution Unit (SAU).
Anna Bridge	160:5571c4ff569f	2781	*/
Anna Bridge	160:5571c4ff569f	2782	__STATIC_INLINE void TZ_SAU_Enable(void)
Anna Bridge	160:5571c4ff569f	2783	{
Anna Bridge	160:5571c4ff569f	2784	SAU->CTRL \|= (SAU_CTRL_ENABLE_Msk);
Anna Bridge	160:5571c4ff569f	2785	}
Anna Bridge	160:5571c4ff569f	2786
Anna Bridge	160:5571c4ff569f	2787
Anna Bridge	160:5571c4ff569f	2788
Anna Bridge	160:5571c4ff569f	2789	/**
Anna Bridge	160:5571c4ff569f	2790	\brief Disable SAU
Anna Bridge	160:5571c4ff569f	2791	\details Disables the Security Attribution Unit (SAU).
Anna Bridge	160:5571c4ff569f	2792	*/
Anna Bridge	160:5571c4ff569f	2793	__STATIC_INLINE void TZ_SAU_Disable(void)
Anna Bridge	160:5571c4ff569f	2794	{
Anna Bridge	160:5571c4ff569f	2795	SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
Anna Bridge	160:5571c4ff569f	2796	}
Anna Bridge	160:5571c4ff569f	2797
Anna Bridge	160:5571c4ff569f	2798	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
Anna Bridge	160:5571c4ff569f	2799
Anna Bridge	160:5571c4ff569f	2800	/@} end of CMSIS_Core_SAUFunctions /
Anna Bridge	160:5571c4ff569f	2801
Anna Bridge	160:5571c4ff569f	2802
Anna Bridge	160:5571c4ff569f	2803
Anna Bridge	160:5571c4ff569f	2804
Anna Bridge	160:5571c4ff569f	2805	/* ################################## SysTick function ############################################ */
Anna Bridge	160:5571c4ff569f	2806	/**
Anna Bridge	160:5571c4ff569f	2807	\ingroup CMSIS_Core_FunctionInterface
Anna Bridge	160:5571c4ff569f	2808	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Anna Bridge	160:5571c4ff569f	2809	\brief Functions that configure the System.
Anna Bridge	160:5571c4ff569f	2810	@{
Anna Bridge	160:5571c4ff569f	2811	*/
Anna Bridge	160:5571c4ff569f	2812
Anna Bridge	160:5571c4ff569f	2813	#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
Anna Bridge	160:5571c4ff569f	2814
Anna Bridge	160:5571c4ff569f	2815	/**
Anna Bridge	160:5571c4ff569f	2816	\brief System Tick Configuration
Anna Bridge	160:5571c4ff569f	2817	\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Anna Bridge	160:5571c4ff569f	2818	Counter is in free running mode to generate periodic interrupts.
Anna Bridge	160:5571c4ff569f	2819	\param [in] ticks Number of ticks between two interrupts.
Anna Bridge	160:5571c4ff569f	2820	\return 0 Function succeeded.
Anna Bridge	160:5571c4ff569f	2821	\return 1 Function failed.
Anna Bridge	160:5571c4ff569f	2822	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Anna Bridge	160:5571c4ff569f	2823	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Anna Bridge	160:5571c4ff569f	2824	must contain a vendor-specific implementation of this function.
Anna Bridge	160:5571c4ff569f	2825	*/
Anna Bridge	160:5571c4ff569f	2826	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Anna Bridge	160:5571c4ff569f	2827	{
Anna Bridge	160:5571c4ff569f	2828	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
Anna Bridge	160:5571c4ff569f	2829	{
Anna Bridge	160:5571c4ff569f	2830	return (1UL); /* Reload value impossible */
Anna Bridge	160:5571c4ff569f	2831	}
Anna Bridge	160:5571c4ff569f	2832
Anna Bridge	160:5571c4ff569f	2833	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Anna Bridge	160:5571c4ff569f	2834	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Anna Bridge	160:5571c4ff569f	2835	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Anna Bridge	160:5571c4ff569f	2836	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
Anna Bridge	160:5571c4ff569f	2837	SysTick_CTRL_TICKINT_Msk \|
Anna Bridge	160:5571c4ff569f	2838	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Anna Bridge	160:5571c4ff569f	2839	return (0UL); /* Function successful */
Anna Bridge	160:5571c4ff569f	2840	}
Anna Bridge	160:5571c4ff569f	2841
Anna Bridge	160:5571c4ff569f	2842	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Anna Bridge	160:5571c4ff569f	2843	/**
Anna Bridge	160:5571c4ff569f	2844	\brief System Tick Configuration (non-secure)
Anna Bridge	160:5571c4ff569f	2845	\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
Anna Bridge	160:5571c4ff569f	2846	Counter is in free running mode to generate periodic interrupts.
Anna Bridge	160:5571c4ff569f	2847	\param [in] ticks Number of ticks between two interrupts.
Anna Bridge	160:5571c4ff569f	2848	\return 0 Function succeeded.
Anna Bridge	160:5571c4ff569f	2849	\return 1 Function failed.
Anna Bridge	160:5571c4ff569f	2850	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Anna Bridge	160:5571c4ff569f	2851	function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
Anna Bridge	160:5571c4ff569f	2852	must contain a vendor-specific implementation of this function.
Anna Bridge	160:5571c4ff569f	2853
Anna Bridge	160:5571c4ff569f	2854	*/
Anna Bridge	160:5571c4ff569f	2855	__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
Anna Bridge	160:5571c4ff569f	2856	{
Anna Bridge	160:5571c4ff569f	2857	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
Anna Bridge	160:5571c4ff569f	2858	{
Anna Bridge	160:5571c4ff569f	2859	return (1UL); /* Reload value impossible */
Anna Bridge	160:5571c4ff569f	2860	}
Anna Bridge	160:5571c4ff569f	2861
Anna Bridge	160:5571c4ff569f	2862	SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Anna Bridge	160:5571c4ff569f	2863	TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Anna Bridge	160:5571c4ff569f	2864	SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
Anna Bridge	160:5571c4ff569f	2865	SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
Anna Bridge	160:5571c4ff569f	2866	SysTick_CTRL_TICKINT_Msk \|
Anna Bridge	160:5571c4ff569f	2867	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Anna Bridge	160:5571c4ff569f	2868	return (0UL); /* Function successful */
Anna Bridge	160:5571c4ff569f	2869	}
Anna Bridge	160:5571c4ff569f	2870	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
Anna Bridge	160:5571c4ff569f	2871
Anna Bridge	160:5571c4ff569f	2872	#endif
Anna Bridge	160:5571c4ff569f	2873
Anna Bridge	160:5571c4ff569f	2874	/@} end of CMSIS_Core_SysTickFunctions /
Anna Bridge	160:5571c4ff569f	2875
Anna Bridge	160:5571c4ff569f	2876
Anna Bridge	160:5571c4ff569f	2877
Anna Bridge	160:5571c4ff569f	2878	/* ##################################### Debug In/Output function ########################################### */
Anna Bridge	160:5571c4ff569f	2879	/**
Anna Bridge	160:5571c4ff569f	2880	\ingroup CMSIS_Core_FunctionInterface
Anna Bridge	160:5571c4ff569f	2881	\defgroup CMSIS_core_DebugFunctions ITM Functions
Anna Bridge	160:5571c4ff569f	2882	\brief Functions that access the ITM debug interface.
Anna Bridge	160:5571c4ff569f	2883	@{
Anna Bridge	160:5571c4ff569f	2884	*/
Anna Bridge	160:5571c4ff569f	2885
Anna Bridge	160:5571c4ff569f	2886	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
Anna Bridge	160:5571c4ff569f	2887	#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
Anna Bridge	160:5571c4ff569f	2888
Anna Bridge	160:5571c4ff569f	2889
Anna Bridge	160:5571c4ff569f	2890	/**
Anna Bridge	160:5571c4ff569f	2891	\brief ITM Send Character
Anna Bridge	160:5571c4ff569f	2892	\details Transmits a character via the ITM channel 0, and
Anna Bridge	160:5571c4ff569f	2893	\li Just returns when no debugger is connected that has booked the output.
Anna Bridge	160:5571c4ff569f	2894	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
Anna Bridge	160:5571c4ff569f	2895	\param [in] ch Character to transmit.
Anna Bridge	160:5571c4ff569f	2896	\returns Character to transmit.
Anna Bridge	160:5571c4ff569f	2897	*/
Anna Bridge	160:5571c4ff569f	2898	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
Anna Bridge	160:5571c4ff569f	2899	{
Anna Bridge	160:5571c4ff569f	2900	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
Anna Bridge	160:5571c4ff569f	2901	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
Anna Bridge	160:5571c4ff569f	2902	{
Anna Bridge	160:5571c4ff569f	2903	while (ITM->PORT[0U].u32 == 0UL)
Anna Bridge	160:5571c4ff569f	2904	{
Anna Bridge	160:5571c4ff569f	2905	__NOP();
Anna Bridge	160:5571c4ff569f	2906	}
Anna Bridge	160:5571c4ff569f	2907	ITM->PORT[0U].u8 = (uint8_t)ch;
Anna Bridge	160:5571c4ff569f	2908	}
Anna Bridge	160:5571c4ff569f	2909	return (ch);
Anna Bridge	160:5571c4ff569f	2910	}
Anna Bridge	160:5571c4ff569f	2911
Anna Bridge	160:5571c4ff569f	2912
Anna Bridge	160:5571c4ff569f	2913	/**
Anna Bridge	160:5571c4ff569f	2914	\brief ITM Receive Character
Anna Bridge	160:5571c4ff569f	2915	\details Inputs a character via the external variable \ref ITM_RxBuffer.
Anna Bridge	160:5571c4ff569f	2916	\return Received character.
Anna Bridge	160:5571c4ff569f	2917	\return -1 No character pending.
Anna Bridge	160:5571c4ff569f	2918	*/
Anna Bridge	160:5571c4ff569f	2919	__STATIC_INLINE int32_t ITM_ReceiveChar (void)
Anna Bridge	160:5571c4ff569f	2920	{
Anna Bridge	160:5571c4ff569f	2921	int32_t ch = -1; /* no character available */
Anna Bridge	160:5571c4ff569f	2922
Anna Bridge	160:5571c4ff569f	2923	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
Anna Bridge	160:5571c4ff569f	2924	{
Anna Bridge	160:5571c4ff569f	2925	ch = ITM_RxBuffer;
Anna Bridge	160:5571c4ff569f	2926	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
Anna Bridge	160:5571c4ff569f	2927	}
Anna Bridge	160:5571c4ff569f	2928
Anna Bridge	160:5571c4ff569f	2929	return (ch);
Anna Bridge	160:5571c4ff569f	2930	}
Anna Bridge	160:5571c4ff569f	2931
Anna Bridge	160:5571c4ff569f	2932
Anna Bridge	160:5571c4ff569f	2933	/**
Anna Bridge	160:5571c4ff569f	2934	\brief ITM Check Character
Anna Bridge	160:5571c4ff569f	2935	\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
Anna Bridge	160:5571c4ff569f	2936	\return 0 No character available.
Anna Bridge	160:5571c4ff569f	2937	\return 1 Character available.
Anna Bridge	160:5571c4ff569f	2938	*/
Anna Bridge	160:5571c4ff569f	2939	__STATIC_INLINE int32_t ITM_CheckChar (void)
Anna Bridge	160:5571c4ff569f	2940	{
Anna Bridge	160:5571c4ff569f	2941
Anna Bridge	160:5571c4ff569f	2942	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
Anna Bridge	160:5571c4ff569f	2943	{
Anna Bridge	160:5571c4ff569f	2944	return (0); /* no character available */
Anna Bridge	160:5571c4ff569f	2945	}
Anna Bridge	160:5571c4ff569f	2946	else
Anna Bridge	160:5571c4ff569f	2947	{
Anna Bridge	160:5571c4ff569f	2948	return (1); /* character available */
Anna Bridge	160:5571c4ff569f	2949	}
Anna Bridge	160:5571c4ff569f	2950	}
Anna Bridge	160:5571c4ff569f	2951
Anna Bridge	160:5571c4ff569f	2952	/@} end of CMSIS_core_DebugFunctions /
Anna Bridge	160:5571c4ff569f	2953
Anna Bridge	160:5571c4ff569f	2954
Anna Bridge	160:5571c4ff569f	2955
Anna Bridge	160:5571c4ff569f	2956
Anna Bridge	160:5571c4ff569f	2957	#ifdef __cplusplus
Anna Bridge	160:5571c4ff569f	2958	}
Anna Bridge	160:5571c4ff569f	2959	#endif
Anna Bridge	160:5571c4ff569f	2960
Anna Bridge	160:5571c4ff569f	2961	#endif /* __CORE_CM33_H_DEPENDANT */
Anna Bridge	160:5571c4ff569f	2962
Anna Bridge	160:5571c4ff569f	2963	#endif /* __CMSIS_GENERIC */