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TARGET_SAKURAIO_EVB_01/core_cm0plus.h@170:e95d10626187, 2018-09-06 (annotated)

Committer:
AnnaBridge
Date:
Thu Sep 06 13:39:34 2018 +0100
Revision:
170:e95d10626187
Parent:
169:a7c7b631e539 
mbed library. Release version 163

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Anna Bridge 160:5571c4ff569f 1 /**************************************************************************//**
Anna Bridge 160:5571c4ff569f 2 * @file core_cm0plus.h
Anna Bridge 160:5571c4ff569f 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
Anna Bridge 169:a7c7b631e539 4 * @version V5.0.4
Anna Bridge 169:a7c7b631e539 5 * @date 10. January 2018
Anna Bridge 160:5571c4ff569f 6 ******************************************************************************/
Anna Bridge 160:5571c4ff569f 7 /*
Anna Bridge 169:a7c7b631e539 8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
Anna Bridge 160:5571c4ff569f 9 *
Anna Bridge 160:5571c4ff569f 10 * SPDX-License-Identifier: Apache-2.0
Anna Bridge 160:5571c4ff569f 11 *
Anna Bridge 160:5571c4ff569f 12 * Licensed under the Apache License, Version 2.0 (the License); you may
Anna Bridge 160:5571c4ff569f 13 * not use this file except in compliance with the License.
Anna Bridge 160:5571c4ff569f 14 * You may obtain a copy of the License at
Anna Bridge 160:5571c4ff569f 15 *
Anna Bridge 160:5571c4ff569f 16 * www.apache.org/licenses/LICENSE-2.0
Anna Bridge 160:5571c4ff569f 17 *
Anna Bridge 160:5571c4ff569f 18 * Unless required by applicable law or agreed to in writing, software
Anna Bridge 160:5571c4ff569f 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
Anna Bridge 160:5571c4ff569f 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Anna Bridge 160:5571c4ff569f 21 * See the License for the specific language governing permissions and
Anna Bridge 160:5571c4ff569f 22 * limitations under the License.
Anna Bridge 160:5571c4ff569f 23 */
Anna Bridge 160:5571c4ff569f 24
Anna Bridge 160:5571c4ff569f 25 #if defined ( __ICCARM__ )
Anna Bridge 169:a7c7b631e539 26 #pragma system_include /* treat file as system include file for MISRA check */
Anna Bridge 169:a7c7b631e539 27 #elif defined (__clang__)
Anna Bridge 160:5571c4ff569f 28 #pragma clang system_header /* treat file as system include file */
Anna Bridge 160:5571c4ff569f 29 #endif
Anna Bridge 160:5571c4ff569f 30
Anna Bridge 160:5571c4ff569f 31 #ifndef __CORE_CM0PLUS_H_GENERIC
Anna Bridge 160:5571c4ff569f 32 #define __CORE_CM0PLUS_H_GENERIC
Anna Bridge 160:5571c4ff569f 33
Anna Bridge 160:5571c4ff569f 34 #include <stdint.h>
Anna Bridge 160:5571c4ff569f 35
Anna Bridge 160:5571c4ff569f 36 #ifdef __cplusplus
Anna Bridge 160:5571c4ff569f 37 extern "C" {
Anna Bridge 160:5571c4ff569f 38 #endif
Anna Bridge 160:5571c4ff569f 39
Anna Bridge 160:5571c4ff569f 40 /**
Anna Bridge 160:5571c4ff569f 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Anna Bridge 160:5571c4ff569f 42 CMSIS violates the following MISRA-C:2004 rules:
Anna Bridge 160:5571c4ff569f 43
Anna Bridge 160:5571c4ff569f 44 \li Required Rule 8.5, object/function definition in header file.<br>
Anna Bridge 160:5571c4ff569f 45 Function definitions in header files are used to allow 'inlining'.
Anna Bridge 160:5571c4ff569f 46
Anna Bridge 160:5571c4ff569f 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Anna Bridge 160:5571c4ff569f 48 Unions are used for effective representation of core registers.
Anna Bridge 160:5571c4ff569f 49
Anna Bridge 160:5571c4ff569f 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
Anna Bridge 160:5571c4ff569f 51 Function-like macros are used to allow more efficient code.
Anna Bridge 160:5571c4ff569f 52 */
Anna Bridge 160:5571c4ff569f 53
Anna Bridge 160:5571c4ff569f 54
Anna Bridge 160:5571c4ff569f 55 /*******************************************************************************
Anna Bridge 160:5571c4ff569f 56 * CMSIS definitions
Anna Bridge 160:5571c4ff569f 57 ******************************************************************************/
Anna Bridge 160:5571c4ff569f 58 /**
Anna Bridge 160:5571c4ff569f 59 \ingroup Cortex-M0+
Anna Bridge 160:5571c4ff569f 60 @{
Anna Bridge 160:5571c4ff569f 61 */
Anna Bridge 160:5571c4ff569f 62
Anna Bridge 160:5571c4ff569f 63 #include "cmsis_version.h"
Anna Bridge 160:5571c4ff569f 64
Anna Bridge 160:5571c4ff569f 65 /* CMSIS CM0+ definitions */
Anna Bridge 160:5571c4ff569f 66 #define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
Anna Bridge 160:5571c4ff569f 67 #define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
Anna Bridge 160:5571c4ff569f 68 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
Anna Bridge 160:5571c4ff569f 69 __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
Anna Bridge 160:5571c4ff569f 70
Anna Bridge 160:5571c4ff569f 71 #define __CORTEX_M (0U) /*!< Cortex-M Core */
Anna Bridge 160:5571c4ff569f 72
Anna Bridge 160:5571c4ff569f 73 /** __FPU_USED indicates whether an FPU is used or not.
Anna Bridge 160:5571c4ff569f 74 This core does not support an FPU at all
Anna Bridge 160:5571c4ff569f 75 */
Anna Bridge 160:5571c4ff569f 76 #define __FPU_USED 0U
Anna Bridge 160:5571c4ff569f 77
Anna Bridge 160:5571c4ff569f 78 #if defined ( __CC_ARM )
Anna Bridge 160:5571c4ff569f 79 #if defined __TARGET_FPU_VFP
Anna Bridge 160:5571c4ff569f 80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 160:5571c4ff569f 81 #endif
Anna Bridge 160:5571c4ff569f 82
Anna Bridge 160:5571c4ff569f 83 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
Anna Bridge 160:5571c4ff569f 84 #if defined __ARM_PCS_VFP
Anna Bridge 160:5571c4ff569f 85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 160:5571c4ff569f 86 #endif
Anna Bridge 160:5571c4ff569f 87
Anna Bridge 160:5571c4ff569f 88 #elif defined ( __GNUC__ )
Anna Bridge 160:5571c4ff569f 89 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Anna Bridge 160:5571c4ff569f 90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 160:5571c4ff569f 91 #endif
Anna Bridge 160:5571c4ff569f 92
Anna Bridge 160:5571c4ff569f 93 #elif defined ( __ICCARM__ )
Anna Bridge 160:5571c4ff569f 94 #if defined __ARMVFP__
Anna Bridge 160:5571c4ff569f 95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 160:5571c4ff569f 96 #endif
Anna Bridge 160:5571c4ff569f 97
Anna Bridge 160:5571c4ff569f 98 #elif defined ( __TI_ARM__ )
Anna Bridge 160:5571c4ff569f 99 #if defined __TI_VFP_SUPPORT__
Anna Bridge 160:5571c4ff569f 100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 160:5571c4ff569f 101 #endif
Anna Bridge 160:5571c4ff569f 102
Anna Bridge 160:5571c4ff569f 103 #elif defined ( __TASKING__ )
Anna Bridge 160:5571c4ff569f 104 #if defined __FPU_VFP__
Anna Bridge 160:5571c4ff569f 105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 160:5571c4ff569f 106 #endif
Anna Bridge 160:5571c4ff569f 107
Anna Bridge 160:5571c4ff569f 108 #elif defined ( __CSMC__ )
Anna Bridge 160:5571c4ff569f 109 #if ( __CSMC__ & 0x400U)
Anna Bridge 160:5571c4ff569f 110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 160:5571c4ff569f 111 #endif
Anna Bridge 160:5571c4ff569f 112
Anna Bridge 160:5571c4ff569f 113 #endif
Anna Bridge 160:5571c4ff569f 114
Anna Bridge 160:5571c4ff569f 115 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
Anna Bridge 160:5571c4ff569f 116
Anna Bridge 160:5571c4ff569f 117
Anna Bridge 160:5571c4ff569f 118 #ifdef __cplusplus
Anna Bridge 160:5571c4ff569f 119 }
Anna Bridge 160:5571c4ff569f 120 #endif
Anna Bridge 160:5571c4ff569f 121
Anna Bridge 160:5571c4ff569f 122 #endif /* __CORE_CM0PLUS_H_GENERIC */
Anna Bridge 160:5571c4ff569f 123
Anna Bridge 160:5571c4ff569f 124 #ifndef __CMSIS_GENERIC
Anna Bridge 160:5571c4ff569f 125
Anna Bridge 160:5571c4ff569f 126 #ifndef __CORE_CM0PLUS_H_DEPENDANT
Anna Bridge 160:5571c4ff569f 127 #define __CORE_CM0PLUS_H_DEPENDANT
Anna Bridge 160:5571c4ff569f 128
Anna Bridge 160:5571c4ff569f 129 #ifdef __cplusplus
Anna Bridge 160:5571c4ff569f 130 extern "C" {
Anna Bridge 160:5571c4ff569f 131 #endif
Anna Bridge 160:5571c4ff569f 132
Anna Bridge 160:5571c4ff569f 133 /* check device defines and use defaults */
Anna Bridge 160:5571c4ff569f 134 #if defined __CHECK_DEVICE_DEFINES
Anna Bridge 160:5571c4ff569f 135 #ifndef __CM0PLUS_REV
Anna Bridge 160:5571c4ff569f 136 #define __CM0PLUS_REV 0x0000U
Anna Bridge 160:5571c4ff569f 137 #warning "__CM0PLUS_REV not defined in device header file; using default!"
Anna Bridge 160:5571c4ff569f 138 #endif
Anna Bridge 160:5571c4ff569f 139
Anna Bridge 160:5571c4ff569f 140 #ifndef __MPU_PRESENT
Anna Bridge 160:5571c4ff569f 141 #define __MPU_PRESENT 0U
Anna Bridge 160:5571c4ff569f 142 #warning "__MPU_PRESENT not defined in device header file; using default!"
Anna Bridge 160:5571c4ff569f 143 #endif
Anna Bridge 160:5571c4ff569f 144
Anna Bridge 160:5571c4ff569f 145 #ifndef __VTOR_PRESENT
Anna Bridge 160:5571c4ff569f 146 #define __VTOR_PRESENT 0U
Anna Bridge 160:5571c4ff569f 147 #warning "__VTOR_PRESENT not defined in device header file; using default!"
Anna Bridge 160:5571c4ff569f 148 #endif
Anna Bridge 160:5571c4ff569f 149
Anna Bridge 160:5571c4ff569f 150 #ifndef __NVIC_PRIO_BITS
Anna Bridge 160:5571c4ff569f 151 #define __NVIC_PRIO_BITS 2U
Anna Bridge 160:5571c4ff569f 152 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Anna Bridge 160:5571c4ff569f 153 #endif
Anna Bridge 160:5571c4ff569f 154
Anna Bridge 160:5571c4ff569f 155 #ifndef __Vendor_SysTickConfig
Anna Bridge 160:5571c4ff569f 156 #define __Vendor_SysTickConfig 0U
Anna Bridge 160:5571c4ff569f 157 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Anna Bridge 160:5571c4ff569f 158 #endif
Anna Bridge 160:5571c4ff569f 159 #endif
Anna Bridge 160:5571c4ff569f 160
Anna Bridge 160:5571c4ff569f 161 /* IO definitions (access restrictions to peripheral registers) */
Anna Bridge 160:5571c4ff569f 162 /**
Anna Bridge 160:5571c4ff569f 163 \defgroup CMSIS_glob_defs CMSIS Global Defines
Anna Bridge 160:5571c4ff569f 164
Anna Bridge 160:5571c4ff569f 165 <strong>IO Type Qualifiers</strong> are used
Anna Bridge 160:5571c4ff569f 166 \li to specify the access to peripheral variables.
Anna Bridge 160:5571c4ff569f 167 \li for automatic generation of peripheral register debug information.
Anna Bridge 160:5571c4ff569f 168 */
Anna Bridge 160:5571c4ff569f 169 #ifdef __cplusplus
Anna Bridge 160:5571c4ff569f 170 #define __I volatile /*!< Defines 'read only' permissions */
Anna Bridge 160:5571c4ff569f 171 #else
Anna Bridge 160:5571c4ff569f 172 #define __I volatile const /*!< Defines 'read only' permissions */
Anna Bridge 160:5571c4ff569f 173 #endif
Anna Bridge 160:5571c4ff569f 174 #define __O volatile /*!< Defines 'write only' permissions */
Anna Bridge 160:5571c4ff569f 175 #define __IO volatile /*!< Defines 'read / write' permissions */
Anna Bridge 160:5571c4ff569f 176
Anna Bridge 160:5571c4ff569f 177 /* following defines should be used for structure members */
Anna Bridge 160:5571c4ff569f 178 #define __IM volatile const /*! Defines 'read only' structure member permissions */
Anna Bridge 160:5571c4ff569f 179 #define __OM volatile /*! Defines 'write only' structure member permissions */
Anna Bridge 160:5571c4ff569f 180 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
Anna Bridge 160:5571c4ff569f 181
Anna Bridge 160:5571c4ff569f 182 /*@} end of group Cortex-M0+ */
Anna Bridge 160:5571c4ff569f 183
Anna Bridge 160:5571c4ff569f 184
Anna Bridge 160:5571c4ff569f 185
Anna Bridge 160:5571c4ff569f 186 /*******************************************************************************
Anna Bridge 160:5571c4ff569f 187 * Register Abstraction
Anna Bridge 160:5571c4ff569f 188 Core Register contain:
Anna Bridge 160:5571c4ff569f 189 - Core Register
Anna Bridge 160:5571c4ff569f 190 - Core NVIC Register
Anna Bridge 160:5571c4ff569f 191 - Core SCB Register
Anna Bridge 160:5571c4ff569f 192 - Core SysTick Register
Anna Bridge 160:5571c4ff569f 193 - Core MPU Register
Anna Bridge 160:5571c4ff569f 194 ******************************************************************************/
Anna Bridge 160:5571c4ff569f 195 /**
Anna Bridge 160:5571c4ff569f 196 \defgroup CMSIS_core_register Defines and Type Definitions
Anna Bridge 160:5571c4ff569f 197 \brief Type definitions and defines for Cortex-M processor based devices.
Anna Bridge 160:5571c4ff569f 198 */
Anna Bridge 160:5571c4ff569f 199
Anna Bridge 160:5571c4ff569f 200 /**
Anna Bridge 160:5571c4ff569f 201 \ingroup CMSIS_core_register
Anna Bridge 160:5571c4ff569f 202 \defgroup CMSIS_CORE Status and Control Registers
Anna Bridge 160:5571c4ff569f 203 \brief Core Register type definitions.
Anna Bridge 160:5571c4ff569f 204 @{
Anna Bridge 160:5571c4ff569f 205 */
Anna Bridge 160:5571c4ff569f 206
Anna Bridge 160:5571c4ff569f 207 /**
Anna Bridge 160:5571c4ff569f 208 \brief Union type to access the Application Program Status Register (APSR).
Anna Bridge 160:5571c4ff569f 209 */
Anna Bridge 160:5571c4ff569f 210 typedef union
Anna Bridge 160:5571c4ff569f 211 {
Anna Bridge 160:5571c4ff569f 212 struct
Anna Bridge 160:5571c4ff569f 213 {
Anna Bridge 160:5571c4ff569f 214 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
Anna Bridge 160:5571c4ff569f 215 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Anna Bridge 160:5571c4ff569f 216 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Anna Bridge 160:5571c4ff569f 217 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Anna Bridge 160:5571c4ff569f 218 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Anna Bridge 160:5571c4ff569f 219 } b; /*!< Structure used for bit access */
Anna Bridge 160:5571c4ff569f 220 uint32_t w; /*!< Type used for word access */
Anna Bridge 160:5571c4ff569f 221 } APSR_Type;
Anna Bridge 160:5571c4ff569f 222
Anna Bridge 160:5571c4ff569f 223 /* APSR Register Definitions */
Anna Bridge 160:5571c4ff569f 224 #define APSR_N_Pos 31U /*!< APSR: N Position */
Anna Bridge 160:5571c4ff569f 225 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Anna Bridge 160:5571c4ff569f 226
Anna Bridge 160:5571c4ff569f 227 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
Anna Bridge 160:5571c4ff569f 228 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Anna Bridge 160:5571c4ff569f 229
Anna Bridge 160:5571c4ff569f 230 #define APSR_C_Pos 29U /*!< APSR: C Position */
Anna Bridge 160:5571c4ff569f 231 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Anna Bridge 160:5571c4ff569f 232
Anna Bridge 160:5571c4ff569f 233 #define APSR_V_Pos 28U /*!< APSR: V Position */
Anna Bridge 160:5571c4ff569f 234 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Anna Bridge 160:5571c4ff569f 235
Anna Bridge 160:5571c4ff569f 236
Anna Bridge 160:5571c4ff569f 237 /**
Anna Bridge 160:5571c4ff569f 238 \brief Union type to access the Interrupt Program Status Register (IPSR).
Anna Bridge 160:5571c4ff569f 239 */
Anna Bridge 160:5571c4ff569f 240 typedef union
Anna Bridge 160:5571c4ff569f 241 {
Anna Bridge 160:5571c4ff569f 242 struct
Anna Bridge 160:5571c4ff569f 243 {
Anna Bridge 160:5571c4ff569f 244 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Anna Bridge 160:5571c4ff569f 245 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Anna Bridge 160:5571c4ff569f 246 } b; /*!< Structure used for bit access */
Anna Bridge 160:5571c4ff569f 247 uint32_t w; /*!< Type used for word access */
Anna Bridge 160:5571c4ff569f 248 } IPSR_Type;
Anna Bridge 160:5571c4ff569f 249
Anna Bridge 160:5571c4ff569f 250 /* IPSR Register Definitions */
Anna Bridge 160:5571c4ff569f 251 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
Anna Bridge 160:5571c4ff569f 252 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Anna Bridge 160:5571c4ff569f 253
Anna Bridge 160:5571c4ff569f 254
Anna Bridge 160:5571c4ff569f 255 /**
Anna Bridge 160:5571c4ff569f 256 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Anna Bridge 160:5571c4ff569f 257 */
Anna Bridge 160:5571c4ff569f 258 typedef union
Anna Bridge 160:5571c4ff569f 259 {
Anna Bridge 160:5571c4ff569f 260 struct
Anna Bridge 160:5571c4ff569f 261 {
Anna Bridge 160:5571c4ff569f 262 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Anna Bridge 160:5571c4ff569f 263 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
Anna Bridge 160:5571c4ff569f 264 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Anna Bridge 160:5571c4ff569f 265 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
Anna Bridge 160:5571c4ff569f 266 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Anna Bridge 160:5571c4ff569f 267 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Anna Bridge 160:5571c4ff569f 268 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Anna Bridge 160:5571c4ff569f 269 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Anna Bridge 160:5571c4ff569f 270 } b; /*!< Structure used for bit access */
Anna Bridge 160:5571c4ff569f 271 uint32_t w; /*!< Type used for word access */
Anna Bridge 160:5571c4ff569f 272 } xPSR_Type;
Anna Bridge 160:5571c4ff569f 273
Anna Bridge 160:5571c4ff569f 274 /* xPSR Register Definitions */
Anna Bridge 160:5571c4ff569f 275 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
Anna Bridge 160:5571c4ff569f 276 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Anna Bridge 160:5571c4ff569f 277
Anna Bridge 160:5571c4ff569f 278 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
Anna Bridge 160:5571c4ff569f 279 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Anna Bridge 160:5571c4ff569f 280
Anna Bridge 160:5571c4ff569f 281 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
Anna Bridge 160:5571c4ff569f 282 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Anna Bridge 160:5571c4ff569f 283
Anna Bridge 160:5571c4ff569f 284 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
Anna Bridge 160:5571c4ff569f 285 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Anna Bridge 160:5571c4ff569f 286
Anna Bridge 160:5571c4ff569f 287 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
Anna Bridge 160:5571c4ff569f 288 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Anna Bridge 160:5571c4ff569f 289
Anna Bridge 160:5571c4ff569f 290 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
Anna Bridge 160:5571c4ff569f 291 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Anna Bridge 160:5571c4ff569f 292
Anna Bridge 160:5571c4ff569f 293
Anna Bridge 160:5571c4ff569f 294 /**
Anna Bridge 160:5571c4ff569f 295 \brief Union type to access the Control Registers (CONTROL).
Anna Bridge 160:5571c4ff569f 296 */
Anna Bridge 160:5571c4ff569f 297 typedef union
Anna Bridge 160:5571c4ff569f 298 {
Anna Bridge 160:5571c4ff569f 299 struct
Anna Bridge 160:5571c4ff569f 300 {
Anna Bridge 160:5571c4ff569f 301 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
Anna Bridge 160:5571c4ff569f 302 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Anna Bridge 160:5571c4ff569f 303 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
Anna Bridge 160:5571c4ff569f 304 } b; /*!< Structure used for bit access */
Anna Bridge 160:5571c4ff569f 305 uint32_t w; /*!< Type used for word access */
Anna Bridge 160:5571c4ff569f 306 } CONTROL_Type;
Anna Bridge 160:5571c4ff569f 307
Anna Bridge 160:5571c4ff569f 308 /* CONTROL Register Definitions */
Anna Bridge 160:5571c4ff569f 309 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
Anna Bridge 160:5571c4ff569f 310 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Anna Bridge 160:5571c4ff569f 311
Anna Bridge 160:5571c4ff569f 312 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
Anna Bridge 160:5571c4ff569f 313 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
Anna Bridge 160:5571c4ff569f 314
Anna Bridge 160:5571c4ff569f 315 /*@} end of group CMSIS_CORE */
Anna Bridge 160:5571c4ff569f 316
Anna Bridge 160:5571c4ff569f 317
Anna Bridge 160:5571c4ff569f 318 /**
Anna Bridge 160:5571c4ff569f 319 \ingroup CMSIS_core_register
Anna Bridge 160:5571c4ff569f 320 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Anna Bridge 160:5571c4ff569f 321 \brief Type definitions for the NVIC Registers
Anna Bridge 160:5571c4ff569f 322 @{
Anna Bridge 160:5571c4ff569f 323 */
Anna Bridge 160:5571c4ff569f 324
Anna Bridge 160:5571c4ff569f 325 /**
Anna Bridge 160:5571c4ff569f 326 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Anna Bridge 160:5571c4ff569f 327 */
Anna Bridge 160:5571c4ff569f 328 typedef struct
Anna Bridge 160:5571c4ff569f 329 {
Anna Bridge 160:5571c4ff569f 330 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Anna Bridge 160:5571c4ff569f 331 uint32_t RESERVED0[31U];
Anna Bridge 160:5571c4ff569f 332 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Anna Bridge 160:5571c4ff569f 333 uint32_t RSERVED1[31U];
Anna Bridge 160:5571c4ff569f 334 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Anna Bridge 160:5571c4ff569f 335 uint32_t RESERVED2[31U];
Anna Bridge 160:5571c4ff569f 336 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Anna Bridge 160:5571c4ff569f 337 uint32_t RESERVED3[31U];
Anna Bridge 160:5571c4ff569f 338 uint32_t RESERVED4[64U];
Anna Bridge 160:5571c4ff569f 339 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
Anna Bridge 160:5571c4ff569f 340 } NVIC_Type;
Anna Bridge 160:5571c4ff569f 341
Anna Bridge 160:5571c4ff569f 342 /*@} end of group CMSIS_NVIC */
Anna Bridge 160:5571c4ff569f 343
Anna Bridge 160:5571c4ff569f 344
Anna Bridge 160:5571c4ff569f 345 /**
Anna Bridge 160:5571c4ff569f 346 \ingroup CMSIS_core_register
Anna Bridge 160:5571c4ff569f 347 \defgroup CMSIS_SCB System Control Block (SCB)
Anna Bridge 160:5571c4ff569f 348 \brief Type definitions for the System Control Block Registers
Anna Bridge 160:5571c4ff569f 349 @{
Anna Bridge 160:5571c4ff569f 350 */
Anna Bridge 160:5571c4ff569f 351
Anna Bridge 160:5571c4ff569f 352 /**
Anna Bridge 160:5571c4ff569f 353 \brief Structure type to access the System Control Block (SCB).
Anna Bridge 160:5571c4ff569f 354 */
Anna Bridge 160:5571c4ff569f 355 typedef struct
Anna Bridge 160:5571c4ff569f 356 {
Anna Bridge 160:5571c4ff569f 357 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Anna Bridge 160:5571c4ff569f 358 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Anna Bridge 160:5571c4ff569f 359 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
Anna Bridge 160:5571c4ff569f 360 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
Anna Bridge 160:5571c4ff569f 361 #else
Anna Bridge 160:5571c4ff569f 362 uint32_t RESERVED0;
Anna Bridge 160:5571c4ff569f 363 #endif
Anna Bridge 160:5571c4ff569f 364 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Anna Bridge 160:5571c4ff569f 365 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Anna Bridge 160:5571c4ff569f 366 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Anna Bridge 160:5571c4ff569f 367 uint32_t RESERVED1;
Anna Bridge 160:5571c4ff569f 368 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
Anna Bridge 160:5571c4ff569f 369 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Anna Bridge 160:5571c4ff569f 370 } SCB_Type;
Anna Bridge 160:5571c4ff569f 371
Anna Bridge 160:5571c4ff569f 372 /* SCB CPUID Register Definitions */
Anna Bridge 160:5571c4ff569f 373 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
Anna Bridge 160:5571c4ff569f 374 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Anna Bridge 160:5571c4ff569f 375
Anna Bridge 160:5571c4ff569f 376 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
Anna Bridge 160:5571c4ff569f 377 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Anna Bridge 160:5571c4ff569f 378
Anna Bridge 160:5571c4ff569f 379 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
Anna Bridge 160:5571c4ff569f 380 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Anna Bridge 160:5571c4ff569f 381
Anna Bridge 160:5571c4ff569f 382 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
Anna Bridge 160:5571c4ff569f 383 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Anna Bridge 160:5571c4ff569f 384
Anna Bridge 160:5571c4ff569f 385 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
Anna Bridge 160:5571c4ff569f 386 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
Anna Bridge 160:5571c4ff569f 387
Anna Bridge 160:5571c4ff569f 388 /* SCB Interrupt Control State Register Definitions */
Anna Bridge 160:5571c4ff569f 389 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
Anna Bridge 160:5571c4ff569f 390 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Anna Bridge 160:5571c4ff569f 391
Anna Bridge 160:5571c4ff569f 392 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
Anna Bridge 160:5571c4ff569f 393 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Anna Bridge 160:5571c4ff569f 394
Anna Bridge 160:5571c4ff569f 395 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
Anna Bridge 160:5571c4ff569f 396 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Anna Bridge 160:5571c4ff569f 397
Anna Bridge 160:5571c4ff569f 398 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
Anna Bridge 160:5571c4ff569f 399 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Anna Bridge 160:5571c4ff569f 400
Anna Bridge 160:5571c4ff569f 401 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
Anna Bridge 160:5571c4ff569f 402 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Anna Bridge 160:5571c4ff569f 403
Anna Bridge 160:5571c4ff569f 404 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
Anna Bridge 160:5571c4ff569f 405 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Anna Bridge 160:5571c4ff569f 406
Anna Bridge 160:5571c4ff569f 407 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
Anna Bridge 160:5571c4ff569f 408 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Anna Bridge 160:5571c4ff569f 409
Anna Bridge 160:5571c4ff569f 410 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
Anna Bridge 160:5571c4ff569f 411 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Anna Bridge 160:5571c4ff569f 412
Anna Bridge 160:5571c4ff569f 413 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
Anna Bridge 160:5571c4ff569f 414 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
Anna Bridge 160:5571c4ff569f 415
Anna Bridge 160:5571c4ff569f 416 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
Anna Bridge 160:5571c4ff569f 417 /* SCB Interrupt Control State Register Definitions */
Anna Bridge 160:5571c4ff569f 418 #define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
Anna Bridge 160:5571c4ff569f 419 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Anna Bridge 160:5571c4ff569f 420 #endif
Anna Bridge 160:5571c4ff569f 421
Anna Bridge 160:5571c4ff569f 422 /* SCB Application Interrupt and Reset Control Register Definitions */
Anna Bridge 160:5571c4ff569f 423 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
Anna Bridge 160:5571c4ff569f 424 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Anna Bridge 160:5571c4ff569f 425
Anna Bridge 160:5571c4ff569f 426 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
Anna Bridge 160:5571c4ff569f 427 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Anna Bridge 160:5571c4ff569f 428
Anna Bridge 160:5571c4ff569f 429 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
Anna Bridge 160:5571c4ff569f 430 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Anna Bridge 160:5571c4ff569f 431
Anna Bridge 160:5571c4ff569f 432 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
Anna Bridge 160:5571c4ff569f 433 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Anna Bridge 160:5571c4ff569f 434
Anna Bridge 160:5571c4ff569f 435 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
Anna Bridge 160:5571c4ff569f 436 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Anna Bridge 160:5571c4ff569f 437
Anna Bridge 160:5571c4ff569f 438 /* SCB System Control Register Definitions */
Anna Bridge 160:5571c4ff569f 439 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
Anna Bridge 160:5571c4ff569f 440 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Anna Bridge 160:5571c4ff569f 441
Anna Bridge 160:5571c4ff569f 442 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
Anna Bridge 160:5571c4ff569f 443 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Anna Bridge 160:5571c4ff569f 444
Anna Bridge 160:5571c4ff569f 445 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
Anna Bridge 160:5571c4ff569f 446 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Anna Bridge 160:5571c4ff569f 447
Anna Bridge 160:5571c4ff569f 448 /* SCB Configuration Control Register Definitions */
Anna Bridge 160:5571c4ff569f 449 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
Anna Bridge 160:5571c4ff569f 450 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Anna Bridge 160:5571c4ff569f 451
Anna Bridge 160:5571c4ff569f 452 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
Anna Bridge 160:5571c4ff569f 453 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Anna Bridge 160:5571c4ff569f 454
Anna Bridge 160:5571c4ff569f 455 /* SCB System Handler Control and State Register Definitions */
Anna Bridge 160:5571c4ff569f 456 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
Anna Bridge 160:5571c4ff569f 457 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Anna Bridge 160:5571c4ff569f 458
Anna Bridge 160:5571c4ff569f 459 /*@} end of group CMSIS_SCB */
Anna Bridge 160:5571c4ff569f 460
Anna Bridge 160:5571c4ff569f 461
Anna Bridge 160:5571c4ff569f 462 /**
Anna Bridge 160:5571c4ff569f 463 \ingroup CMSIS_core_register
Anna Bridge 160:5571c4ff569f 464 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Anna Bridge 160:5571c4ff569f 465 \brief Type definitions for the System Timer Registers.
Anna Bridge 160:5571c4ff569f 466 @{
Anna Bridge 160:5571c4ff569f 467 */
Anna Bridge 160:5571c4ff569f 468
Anna Bridge 160:5571c4ff569f 469 /**
Anna Bridge 160:5571c4ff569f 470 \brief Structure type to access the System Timer (SysTick).
Anna Bridge 160:5571c4ff569f 471 */
Anna Bridge 160:5571c4ff569f 472 typedef struct
Anna Bridge 160:5571c4ff569f 473 {
Anna Bridge 160:5571c4ff569f 474 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Anna Bridge 160:5571c4ff569f 475 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Anna Bridge 160:5571c4ff569f 476 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Anna Bridge 160:5571c4ff569f 477 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Anna Bridge 160:5571c4ff569f 478 } SysTick_Type;
Anna Bridge 160:5571c4ff569f 479
Anna Bridge 160:5571c4ff569f 480 /* SysTick Control / Status Register Definitions */
Anna Bridge 160:5571c4ff569f 481 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
Anna Bridge 160:5571c4ff569f 482 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Anna Bridge 160:5571c4ff569f 483
Anna Bridge 160:5571c4ff569f 484 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
Anna Bridge 160:5571c4ff569f 485 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Anna Bridge 160:5571c4ff569f 486
Anna Bridge 160:5571c4ff569f 487 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
Anna Bridge 160:5571c4ff569f 488 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Anna Bridge 160:5571c4ff569f 489
Anna Bridge 160:5571c4ff569f 490 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
Anna Bridge 160:5571c4ff569f 491 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
Anna Bridge 160:5571c4ff569f 492
Anna Bridge 160:5571c4ff569f 493 /* SysTick Reload Register Definitions */
Anna Bridge 160:5571c4ff569f 494 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
Anna Bridge 160:5571c4ff569f 495 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
Anna Bridge 160:5571c4ff569f 496
Anna Bridge 160:5571c4ff569f 497 /* SysTick Current Register Definitions */
Anna Bridge 160:5571c4ff569f 498 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
Anna Bridge 160:5571c4ff569f 499 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
Anna Bridge 160:5571c4ff569f 500
Anna Bridge 160:5571c4ff569f 501 /* SysTick Calibration Register Definitions */
Anna Bridge 160:5571c4ff569f 502 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
Anna Bridge 160:5571c4ff569f 503 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Anna Bridge 160:5571c4ff569f 504
Anna Bridge 160:5571c4ff569f 505 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
Anna Bridge 160:5571c4ff569f 506 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Anna Bridge 160:5571c4ff569f 507
Anna Bridge 160:5571c4ff569f 508 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
Anna Bridge 160:5571c4ff569f 509 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
Anna Bridge 160:5571c4ff569f 510
Anna Bridge 160:5571c4ff569f 511 /*@} end of group CMSIS_SysTick */
Anna Bridge 160:5571c4ff569f 512
Anna Bridge 160:5571c4ff569f 513 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge 160:5571c4ff569f 514 /**
Anna Bridge 160:5571c4ff569f 515 \ingroup CMSIS_core_register
Anna Bridge 160:5571c4ff569f 516 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
Anna Bridge 160:5571c4ff569f 517 \brief Type definitions for the Memory Protection Unit (MPU)
Anna Bridge 160:5571c4ff569f 518 @{
Anna Bridge 160:5571c4ff569f 519 */
Anna Bridge 160:5571c4ff569f 520
Anna Bridge 160:5571c4ff569f 521 /**
Anna Bridge 160:5571c4ff569f 522 \brief Structure type to access the Memory Protection Unit (MPU).
Anna Bridge 160:5571c4ff569f 523 */
Anna Bridge 160:5571c4ff569f 524 typedef struct
Anna Bridge 160:5571c4ff569f 525 {
Anna Bridge 160:5571c4ff569f 526 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
Anna Bridge 160:5571c4ff569f 527 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
Anna Bridge 160:5571c4ff569f 528 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
Anna Bridge 160:5571c4ff569f 529 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
Anna Bridge 160:5571c4ff569f 530 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
Anna Bridge 160:5571c4ff569f 531 } MPU_Type;
Anna Bridge 160:5571c4ff569f 532
Anna Bridge 160:5571c4ff569f 533 #define MPU_TYPE_RALIASES 1U
Anna Bridge 160:5571c4ff569f 534
Anna Bridge 160:5571c4ff569f 535 /* MPU Type Register Definitions */
Anna Bridge 160:5571c4ff569f 536 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
Anna Bridge 160:5571c4ff569f 537 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
Anna Bridge 160:5571c4ff569f 538
Anna Bridge 160:5571c4ff569f 539 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
Anna Bridge 160:5571c4ff569f 540 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
Anna Bridge 160:5571c4ff569f 541
Anna Bridge 160:5571c4ff569f 542 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
Anna Bridge 160:5571c4ff569f 543 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
Anna Bridge 160:5571c4ff569f 544
Anna Bridge 160:5571c4ff569f 545 /* MPU Control Register Definitions */
Anna Bridge 160:5571c4ff569f 546 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
Anna Bridge 160:5571c4ff569f 547 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
Anna Bridge 160:5571c4ff569f 548
Anna Bridge 160:5571c4ff569f 549 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
Anna Bridge 160:5571c4ff569f 550 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
Anna Bridge 160:5571c4ff569f 551
Anna Bridge 160:5571c4ff569f 552 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
Anna Bridge 160:5571c4ff569f 553 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
Anna Bridge 160:5571c4ff569f 554
Anna Bridge 160:5571c4ff569f 555 /* MPU Region Number Register Definitions */
Anna Bridge 160:5571c4ff569f 556 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
Anna Bridge 160:5571c4ff569f 557 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
Anna Bridge 160:5571c4ff569f 558
Anna Bridge 160:5571c4ff569f 559 /* MPU Region Base Address Register Definitions */
Anna Bridge 160:5571c4ff569f 560 #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
Anna Bridge 160:5571c4ff569f 561 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
Anna Bridge 160:5571c4ff569f 562
Anna Bridge 160:5571c4ff569f 563 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
Anna Bridge 160:5571c4ff569f 564 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
Anna Bridge 160:5571c4ff569f 565
Anna Bridge 160:5571c4ff569f 566 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
Anna Bridge 160:5571c4ff569f 567 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
Anna Bridge 160:5571c4ff569f 568
Anna Bridge 160:5571c4ff569f 569 /* MPU Region Attribute and Size Register Definitions */
Anna Bridge 160:5571c4ff569f 570 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
Anna Bridge 160:5571c4ff569f 571 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
Anna Bridge 160:5571c4ff569f 572
Anna Bridge 160:5571c4ff569f 573 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
Anna Bridge 160:5571c4ff569f 574 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
Anna Bridge 160:5571c4ff569f 575
Anna Bridge 160:5571c4ff569f 576 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
Anna Bridge 160:5571c4ff569f 577 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
Anna Bridge 160:5571c4ff569f 578
Anna Bridge 160:5571c4ff569f 579 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
Anna Bridge 160:5571c4ff569f 580 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
Anna Bridge 160:5571c4ff569f 581
Anna Bridge 160:5571c4ff569f 582 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
Anna Bridge 160:5571c4ff569f 583 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
Anna Bridge 160:5571c4ff569f 584
Anna Bridge 160:5571c4ff569f 585 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
Anna Bridge 160:5571c4ff569f 586 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
Anna Bridge 160:5571c4ff569f 587
Anna Bridge 160:5571c4ff569f 588 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
Anna Bridge 160:5571c4ff569f 589 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
Anna Bridge 160:5571c4ff569f 590
Anna Bridge 160:5571c4ff569f 591 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
Anna Bridge 160:5571c4ff569f 592 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
Anna Bridge 160:5571c4ff569f 593
Anna Bridge 160:5571c4ff569f 594 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
Anna Bridge 160:5571c4ff569f 595 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
Anna Bridge 160:5571c4ff569f 596
Anna Bridge 160:5571c4ff569f 597 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
Anna Bridge 160:5571c4ff569f 598 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
Anna Bridge 160:5571c4ff569f 599
Anna Bridge 160:5571c4ff569f 600 /*@} end of group CMSIS_MPU */
Anna Bridge 160:5571c4ff569f 601 #endif
Anna Bridge 160:5571c4ff569f 602
Anna Bridge 160:5571c4ff569f 603
Anna Bridge 160:5571c4ff569f 604 /**
Anna Bridge 160:5571c4ff569f 605 \ingroup CMSIS_core_register
Anna Bridge 160:5571c4ff569f 606 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Anna Bridge 160:5571c4ff569f 607 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Anna Bridge 160:5571c4ff569f 608 Therefore they are not covered by the Cortex-M0+ header file.
Anna Bridge 160:5571c4ff569f 609 @{
Anna Bridge 160:5571c4ff569f 610 */
Anna Bridge 160:5571c4ff569f 611 /*@} end of group CMSIS_CoreDebug */
Anna Bridge 160:5571c4ff569f 612
Anna Bridge 160:5571c4ff569f 613
Anna Bridge 160:5571c4ff569f 614 /**
Anna Bridge 160:5571c4ff569f 615 \ingroup CMSIS_core_register
Anna Bridge 160:5571c4ff569f 616 \defgroup CMSIS_core_bitfield Core register bit field macros
Anna Bridge 160:5571c4ff569f 617 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
Anna Bridge 160:5571c4ff569f 618 @{
Anna Bridge 160:5571c4ff569f 619 */
Anna Bridge 160:5571c4ff569f 620
Anna Bridge 160:5571c4ff569f 621 /**
Anna Bridge 160:5571c4ff569f 622 \brief Mask and shift a bit field value for use in a register bit range.
Anna Bridge 160:5571c4ff569f 623 \param[in] field Name of the register bit field.
Anna Bridge 160:5571c4ff569f 624 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
Anna Bridge 160:5571c4ff569f 625 \return Masked and shifted value.
Anna Bridge 160:5571c4ff569f 626 */
Anna Bridge 160:5571c4ff569f 627 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
Anna Bridge 160:5571c4ff569f 628
Anna Bridge 160:5571c4ff569f 629 /**
Anna Bridge 160:5571c4ff569f 630 \brief Mask and shift a register value to extract a bit filed value.
Anna Bridge 160:5571c4ff569f 631 \param[in] field Name of the register bit field.
Anna Bridge 160:5571c4ff569f 632 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
Anna Bridge 160:5571c4ff569f 633 \return Masked and shifted bit field value.
Anna Bridge 160:5571c4ff569f 634 */
Anna Bridge 160:5571c4ff569f 635 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
Anna Bridge 160:5571c4ff569f 636
Anna Bridge 160:5571c4ff569f 637 /*@} end of group CMSIS_core_bitfield */
Anna Bridge 160:5571c4ff569f 638
Anna Bridge 160:5571c4ff569f 639
Anna Bridge 160:5571c4ff569f 640 /**
Anna Bridge 160:5571c4ff569f 641 \ingroup CMSIS_core_register
Anna Bridge 160:5571c4ff569f 642 \defgroup CMSIS_core_base Core Definitions
Anna Bridge 160:5571c4ff569f 643 \brief Definitions for base addresses, unions, and structures.
Anna Bridge 160:5571c4ff569f 644 @{
Anna Bridge 160:5571c4ff569f 645 */
Anna Bridge 160:5571c4ff569f 646
Anna Bridge 160:5571c4ff569f 647 /* Memory mapping of Core Hardware */
Anna Bridge 160:5571c4ff569f 648 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Anna Bridge 160:5571c4ff569f 649 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Anna Bridge 160:5571c4ff569f 650 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Anna Bridge 160:5571c4ff569f 651 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Anna Bridge 160:5571c4ff569f 652
Anna Bridge 160:5571c4ff569f 653 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Anna Bridge 160:5571c4ff569f 654 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Anna Bridge 160:5571c4ff569f 655 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Anna Bridge 160:5571c4ff569f 656
Anna Bridge 160:5571c4ff569f 657 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge 160:5571c4ff569f 658 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
Anna Bridge 160:5571c4ff569f 659 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
Anna Bridge 160:5571c4ff569f 660 #endif
Anna Bridge 160:5571c4ff569f 661
Anna Bridge 160:5571c4ff569f 662 /*@} */
Anna Bridge 160:5571c4ff569f 663
Anna Bridge 160:5571c4ff569f 664
Anna Bridge 160:5571c4ff569f 665
Anna Bridge 160:5571c4ff569f 666 /*******************************************************************************
Anna Bridge 160:5571c4ff569f 667 * Hardware Abstraction Layer
Anna Bridge 160:5571c4ff569f 668 Core Function Interface contains:
Anna Bridge 160:5571c4ff569f 669 - Core NVIC Functions
Anna Bridge 160:5571c4ff569f 670 - Core SysTick Functions
Anna Bridge 160:5571c4ff569f 671 - Core Register Access Functions
Anna Bridge 160:5571c4ff569f 672 ******************************************************************************/
Anna Bridge 160:5571c4ff569f 673 /**
Anna Bridge 160:5571c4ff569f 674 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Anna Bridge 160:5571c4ff569f 675 */
Anna Bridge 160:5571c4ff569f 676
Anna Bridge 160:5571c4ff569f 677
Anna Bridge 160:5571c4ff569f 678
Anna Bridge 160:5571c4ff569f 679 /* ########################## NVIC functions #################################### */
Anna Bridge 160:5571c4ff569f 680 /**
Anna Bridge 160:5571c4ff569f 681 \ingroup CMSIS_Core_FunctionInterface
Anna Bridge 160:5571c4ff569f 682 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Anna Bridge 160:5571c4ff569f 683 \brief Functions that manage interrupts and exceptions via the NVIC.
Anna Bridge 160:5571c4ff569f 684 @{
Anna Bridge 160:5571c4ff569f 685 */
Anna Bridge 160:5571c4ff569f 686
Anna Bridge 160:5571c4ff569f 687 #ifdef CMSIS_NVIC_VIRTUAL
Anna Bridge 160:5571c4ff569f 688 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
Anna Bridge 160:5571c4ff569f 689 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
Anna Bridge 160:5571c4ff569f 690 #endif
Anna Bridge 160:5571c4ff569f 691 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
Anna Bridge 160:5571c4ff569f 692 #else
Anna Bridge 160:5571c4ff569f 693 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0+ */
Anna Bridge 160:5571c4ff569f 694 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0+ */
Anna Bridge 160:5571c4ff569f 695 #define NVIC_EnableIRQ __NVIC_EnableIRQ
Anna Bridge 160:5571c4ff569f 696 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
Anna Bridge 160:5571c4ff569f 697 #define NVIC_DisableIRQ __NVIC_DisableIRQ
Anna Bridge 160:5571c4ff569f 698 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
Anna Bridge 160:5571c4ff569f 699 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
Anna Bridge 160:5571c4ff569f 700 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
Anna Bridge 160:5571c4ff569f 701 /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */
Anna Bridge 160:5571c4ff569f 702 #define NVIC_SetPriority __NVIC_SetPriority
Anna Bridge 160:5571c4ff569f 703 #define NVIC_GetPriority __NVIC_GetPriority
Anna Bridge 160:5571c4ff569f 704 #define NVIC_SystemReset __NVIC_SystemReset
Anna Bridge 160:5571c4ff569f 705 #endif /* CMSIS_NVIC_VIRTUAL */
Anna Bridge 160:5571c4ff569f 706
Anna Bridge 160:5571c4ff569f 707 #ifdef CMSIS_VECTAB_VIRTUAL
Anna Bridge 160:5571c4ff569f 708 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
Anna Bridge 160:5571c4ff569f 709 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
Anna Bridge 160:5571c4ff569f 710 #endif
Anna Bridge 160:5571c4ff569f 711 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
Anna Bridge 160:5571c4ff569f 712 #else
Anna Bridge 160:5571c4ff569f 713 #define NVIC_SetVector __NVIC_SetVector
Anna Bridge 160:5571c4ff569f 714 #define NVIC_GetVector __NVIC_GetVector
Anna Bridge 160:5571c4ff569f 715 #endif /* (CMSIS_VECTAB_VIRTUAL) */
Anna Bridge 160:5571c4ff569f 716
Anna Bridge 160:5571c4ff569f 717 #define NVIC_USER_IRQ_OFFSET 16
Anna Bridge 160:5571c4ff569f 718
Anna Bridge 160:5571c4ff569f 719
Anna Bridge 169:a7c7b631e539 720 /* Interrupt Priorities are WORD accessible only under Armv6-M */
Anna Bridge 160:5571c4ff569f 721 /* The following MACROS handle generation of the register offset and byte masks */
Anna Bridge 160:5571c4ff569f 722 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
Anna Bridge 160:5571c4ff569f 723 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
Anna Bridge 160:5571c4ff569f 724 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
Anna Bridge 160:5571c4ff569f 725
Anna Bridge 160:5571c4ff569f 726
Anna Bridge 160:5571c4ff569f 727 /**
Anna Bridge 160:5571c4ff569f 728 \brief Enable Interrupt
Anna Bridge 160:5571c4ff569f 729 \details Enables a device specific interrupt in the NVIC interrupt controller.
Anna Bridge 160:5571c4ff569f 730 \param [in] IRQn Device specific interrupt number.
Anna Bridge 160:5571c4ff569f 731 \note IRQn must not be negative.
Anna Bridge 160:5571c4ff569f 732 */
Anna Bridge 160:5571c4ff569f 733 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Anna Bridge 160:5571c4ff569f 734 {
Anna Bridge 160:5571c4ff569f 735 if ((int32_t)(IRQn) >= 0)
Anna Bridge 160:5571c4ff569f 736 {
Anna Bridge 169:a7c7b631e539 737 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge 160:5571c4ff569f 738 }
Anna Bridge 160:5571c4ff569f 739 }
Anna Bridge 160:5571c4ff569f 740
Anna Bridge 160:5571c4ff569f 741
Anna Bridge 160:5571c4ff569f 742 /**
Anna Bridge 160:5571c4ff569f 743 \brief Get Interrupt Enable status
Anna Bridge 160:5571c4ff569f 744 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
Anna Bridge 160:5571c4ff569f 745 \param [in] IRQn Device specific interrupt number.
Anna Bridge 160:5571c4ff569f 746 \return 0 Interrupt is not enabled.
Anna Bridge 160:5571c4ff569f 747 \return 1 Interrupt is enabled.
Anna Bridge 160:5571c4ff569f 748 \note IRQn must not be negative.
Anna Bridge 160:5571c4ff569f 749 */
Anna Bridge 160:5571c4ff569f 750 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Anna Bridge 160:5571c4ff569f 751 {
Anna Bridge 160:5571c4ff569f 752 if ((int32_t)(IRQn) >= 0)
Anna Bridge 160:5571c4ff569f 753 {
Anna Bridge 169:a7c7b631e539 754 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge 160:5571c4ff569f 755 }
Anna Bridge 160:5571c4ff569f 756 else
Anna Bridge 160:5571c4ff569f 757 {
Anna Bridge 160:5571c4ff569f 758 return(0U);
Anna Bridge 160:5571c4ff569f 759 }
Anna Bridge 160:5571c4ff569f 760 }
Anna Bridge 160:5571c4ff569f 761
Anna Bridge 160:5571c4ff569f 762
Anna Bridge 160:5571c4ff569f 763 /**
Anna Bridge 160:5571c4ff569f 764 \brief Disable Interrupt
Anna Bridge 160:5571c4ff569f 765 \details Disables a device specific interrupt in the NVIC interrupt controller.
Anna Bridge 160:5571c4ff569f 766 \param [in] IRQn Device specific interrupt number.
Anna Bridge 160:5571c4ff569f 767 \note IRQn must not be negative.
Anna Bridge 160:5571c4ff569f 768 */
Anna Bridge 160:5571c4ff569f 769 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Anna Bridge 160:5571c4ff569f 770 {
Anna Bridge 160:5571c4ff569f 771 if ((int32_t)(IRQn) >= 0)
Anna Bridge 160:5571c4ff569f 772 {
Anna Bridge 169:a7c7b631e539 773 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge 160:5571c4ff569f 774 __DSB();
Anna Bridge 160:5571c4ff569f 775 __ISB();
Anna Bridge 160:5571c4ff569f 776 }
Anna Bridge 160:5571c4ff569f 777 }
Anna Bridge 160:5571c4ff569f 778
Anna Bridge 160:5571c4ff569f 779
Anna Bridge 160:5571c4ff569f 780 /**
Anna Bridge 160:5571c4ff569f 781 \brief Get Pending Interrupt
Anna Bridge 160:5571c4ff569f 782 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
Anna Bridge 160:5571c4ff569f 783 \param [in] IRQn Device specific interrupt number.
Anna Bridge 160:5571c4ff569f 784 \return 0 Interrupt status is not pending.
Anna Bridge 160:5571c4ff569f 785 \return 1 Interrupt status is pending.
Anna Bridge 160:5571c4ff569f 786 \note IRQn must not be negative.
Anna Bridge 160:5571c4ff569f 787 */
Anna Bridge 160:5571c4ff569f 788 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Anna Bridge 160:5571c4ff569f 789 {
Anna Bridge 160:5571c4ff569f 790 if ((int32_t)(IRQn) >= 0)
Anna Bridge 160:5571c4ff569f 791 {
Anna Bridge 169:a7c7b631e539 792 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge 160:5571c4ff569f 793 }
Anna Bridge 160:5571c4ff569f 794 else
Anna Bridge 160:5571c4ff569f 795 {
Anna Bridge 160:5571c4ff569f 796 return(0U);
Anna Bridge 160:5571c4ff569f 797 }
Anna Bridge 160:5571c4ff569f 798 }
Anna Bridge 160:5571c4ff569f 799
Anna Bridge 160:5571c4ff569f 800
Anna Bridge 160:5571c4ff569f 801 /**
Anna Bridge 160:5571c4ff569f 802 \brief Set Pending Interrupt
Anna Bridge 160:5571c4ff569f 803 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
Anna Bridge 160:5571c4ff569f 804 \param [in] IRQn Device specific interrupt number.
Anna Bridge 160:5571c4ff569f 805 \note IRQn must not be negative.
Anna Bridge 160:5571c4ff569f 806 */
Anna Bridge 160:5571c4ff569f 807 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Anna Bridge 160:5571c4ff569f 808 {
Anna Bridge 160:5571c4ff569f 809 if ((int32_t)(IRQn) >= 0)
Anna Bridge 160:5571c4ff569f 810 {
Anna Bridge 169:a7c7b631e539 811 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge 160:5571c4ff569f 812 }
Anna Bridge 160:5571c4ff569f 813 }
Anna Bridge 160:5571c4ff569f 814
Anna Bridge 160:5571c4ff569f 815
Anna Bridge 160:5571c4ff569f 816 /**
Anna Bridge 160:5571c4ff569f 817 \brief Clear Pending Interrupt
Anna Bridge 160:5571c4ff569f 818 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
Anna Bridge 160:5571c4ff569f 819 \param [in] IRQn Device specific interrupt number.
Anna Bridge 160:5571c4ff569f 820 \note IRQn must not be negative.
Anna Bridge 160:5571c4ff569f 821 */
Anna Bridge 160:5571c4ff569f 822 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Anna Bridge 160:5571c4ff569f 823 {
Anna Bridge 160:5571c4ff569f 824 if ((int32_t)(IRQn) >= 0)
Anna Bridge 160:5571c4ff569f 825 {
Anna Bridge 169:a7c7b631e539 826 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge 160:5571c4ff569f 827 }
Anna Bridge 160:5571c4ff569f 828 }
Anna Bridge 160:5571c4ff569f 829
Anna Bridge 160:5571c4ff569f 830
Anna Bridge 160:5571c4ff569f 831 /**
Anna Bridge 160:5571c4ff569f 832 \brief Set Interrupt Priority
Anna Bridge 160:5571c4ff569f 833 \details Sets the priority of a device specific interrupt or a processor exception.
Anna Bridge 160:5571c4ff569f 834 The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge 160:5571c4ff569f 835 or negative to specify a processor exception.
Anna Bridge 160:5571c4ff569f 836 \param [in] IRQn Interrupt number.
Anna Bridge 160:5571c4ff569f 837 \param [in] priority Priority to set.
Anna Bridge 160:5571c4ff569f 838 \note The priority cannot be set for every processor exception.
Anna Bridge 160:5571c4ff569f 839 */
Anna Bridge 160:5571c4ff569f 840 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Anna Bridge 160:5571c4ff569f 841 {
Anna Bridge 160:5571c4ff569f 842 if ((int32_t)(IRQn) >= 0)
Anna Bridge 160:5571c4ff569f 843 {
Anna Bridge 160:5571c4ff569f 844 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Anna Bridge 160:5571c4ff569f 845 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Anna Bridge 160:5571c4ff569f 846 }
Anna Bridge 160:5571c4ff569f 847 else
Anna Bridge 160:5571c4ff569f 848 {
Anna Bridge 160:5571c4ff569f 849 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Anna Bridge 160:5571c4ff569f 850 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Anna Bridge 160:5571c4ff569f 851 }
Anna Bridge 160:5571c4ff569f 852 }
Anna Bridge 160:5571c4ff569f 853
Anna Bridge 160:5571c4ff569f 854
Anna Bridge 160:5571c4ff569f 855 /**
Anna Bridge 160:5571c4ff569f 856 \brief Get Interrupt Priority
Anna Bridge 160:5571c4ff569f 857 \details Reads the priority of a device specific interrupt or a processor exception.
Anna Bridge 160:5571c4ff569f 858 The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge 160:5571c4ff569f 859 or negative to specify a processor exception.
Anna Bridge 160:5571c4ff569f 860 \param [in] IRQn Interrupt number.
Anna Bridge 160:5571c4ff569f 861 \return Interrupt Priority.
Anna Bridge 160:5571c4ff569f 862 Value is aligned automatically to the implemented priority bits of the microcontroller.
Anna Bridge 160:5571c4ff569f 863 */
Anna Bridge 160:5571c4ff569f 864 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Anna Bridge 160:5571c4ff569f 865 {
Anna Bridge 160:5571c4ff569f 866
Anna Bridge 160:5571c4ff569f 867 if ((int32_t)(IRQn) >= 0)
Anna Bridge 160:5571c4ff569f 868 {
Anna Bridge 160:5571c4ff569f 869 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
Anna Bridge 160:5571c4ff569f 870 }
Anna Bridge 160:5571c4ff569f 871 else
Anna Bridge 160:5571c4ff569f 872 {
Anna Bridge 160:5571c4ff569f 873 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
Anna Bridge 160:5571c4ff569f 874 }
Anna Bridge 160:5571c4ff569f 875 }
Anna Bridge 160:5571c4ff569f 876
Anna Bridge 160:5571c4ff569f 877
Anna Bridge 160:5571c4ff569f 878 /**
Anna Bridge 160:5571c4ff569f 879 \brief Set Interrupt Vector
Anna Bridge 160:5571c4ff569f 880 \details Sets an interrupt vector in SRAM based interrupt vector table.
Anna Bridge 160:5571c4ff569f 881 The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge 160:5571c4ff569f 882 or negative to specify a processor exception.
Anna Bridge 160:5571c4ff569f 883 VTOR must been relocated to SRAM before.
Anna Bridge 160:5571c4ff569f 884 If VTOR is not present address 0 must be mapped to SRAM.
Anna Bridge 160:5571c4ff569f 885 \param [in] IRQn Interrupt number
Anna Bridge 160:5571c4ff569f 886 \param [in] vector Address of interrupt handler function
Anna Bridge 160:5571c4ff569f 887 */
Anna Bridge 160:5571c4ff569f 888 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Anna Bridge 160:5571c4ff569f 889 {
Anna Bridge 160:5571c4ff569f 890 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
Anna Bridge 160:5571c4ff569f 891 uint32_t *vectors = (uint32_t *)SCB->VTOR;
Anna Bridge 160:5571c4ff569f 892 #else
Anna Bridge 160:5571c4ff569f 893 uint32_t *vectors = (uint32_t *)0x0U;
Anna Bridge 160:5571c4ff569f 894 #endif
Anna Bridge 160:5571c4ff569f 895 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
Anna Bridge 160:5571c4ff569f 896 }
Anna Bridge 160:5571c4ff569f 897
Anna Bridge 160:5571c4ff569f 898
Anna Bridge 160:5571c4ff569f 899 /**
Anna Bridge 160:5571c4ff569f 900 \brief Get Interrupt Vector
Anna Bridge 160:5571c4ff569f 901 \details Reads an interrupt vector from interrupt vector table.
Anna Bridge 160:5571c4ff569f 902 The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge 160:5571c4ff569f 903 or negative to specify a processor exception.
Anna Bridge 160:5571c4ff569f 904 \param [in] IRQn Interrupt number.
Anna Bridge 160:5571c4ff569f 905 \return Address of interrupt handler function
Anna Bridge 160:5571c4ff569f 906 */
Anna Bridge 160:5571c4ff569f 907 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Anna Bridge 160:5571c4ff569f 908 {
Anna Bridge 160:5571c4ff569f 909 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
Anna Bridge 160:5571c4ff569f 910 uint32_t *vectors = (uint32_t *)SCB->VTOR;
Anna Bridge 160:5571c4ff569f 911 #else
Anna Bridge 160:5571c4ff569f 912 uint32_t *vectors = (uint32_t *)0x0U;
Anna Bridge 160:5571c4ff569f 913 #endif
Anna Bridge 160:5571c4ff569f 914 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
Anna Bridge 160:5571c4ff569f 915
Anna Bridge 160:5571c4ff569f 916 }
Anna Bridge 160:5571c4ff569f 917
Anna Bridge 160:5571c4ff569f 918
Anna Bridge 160:5571c4ff569f 919 /**
Anna Bridge 160:5571c4ff569f 920 \brief System Reset
Anna Bridge 160:5571c4ff569f 921 \details Initiates a system reset request to reset the MCU.
Anna Bridge 160:5571c4ff569f 922 */
Anna Bridge 160:5571c4ff569f 923 __STATIC_INLINE void __NVIC_SystemReset(void)
Anna Bridge 160:5571c4ff569f 924 {
Anna Bridge 160:5571c4ff569f 925 __DSB(); /* Ensure all outstanding memory accesses included
Anna Bridge 160:5571c4ff569f 926 buffered write are completed before reset */
Anna Bridge 160:5571c4ff569f 927 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Anna Bridge 160:5571c4ff569f 928 SCB_AIRCR_SYSRESETREQ_Msk);
Anna Bridge 160:5571c4ff569f 929 __DSB(); /* Ensure completion of memory access */
Anna Bridge 160:5571c4ff569f 930
Anna Bridge 160:5571c4ff569f 931 for(;;) /* wait until reset */
Anna Bridge 160:5571c4ff569f 932 {
Anna Bridge 160:5571c4ff569f 933 __NOP();
Anna Bridge 160:5571c4ff569f 934 }
Anna Bridge 160:5571c4ff569f 935 }
Anna Bridge 160:5571c4ff569f 936
Anna Bridge 160:5571c4ff569f 937 /*@} end of CMSIS_Core_NVICFunctions */
Anna Bridge 160:5571c4ff569f 938
Anna Bridge 160:5571c4ff569f 939 /* ########################## MPU functions #################################### */
Anna Bridge 160:5571c4ff569f 940
Anna Bridge 160:5571c4ff569f 941 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge 160:5571c4ff569f 942
Anna Bridge 160:5571c4ff569f 943 #include "mpu_armv7.h"
Anna Bridge 160:5571c4ff569f 944
Anna Bridge 160:5571c4ff569f 945 #endif
Anna Bridge 160:5571c4ff569f 946
Anna Bridge 160:5571c4ff569f 947 /* ########################## FPU functions #################################### */
Anna Bridge 160:5571c4ff569f 948 /**
Anna Bridge 160:5571c4ff569f 949 \ingroup CMSIS_Core_FunctionInterface
Anna Bridge 160:5571c4ff569f 950 \defgroup CMSIS_Core_FpuFunctions FPU Functions
Anna Bridge 160:5571c4ff569f 951 \brief Function that provides FPU type.
Anna Bridge 160:5571c4ff569f 952 @{
Anna Bridge 160:5571c4ff569f 953 */
Anna Bridge 160:5571c4ff569f 954
Anna Bridge 160:5571c4ff569f 955 /**
Anna Bridge 160:5571c4ff569f 956 \brief get FPU type
Anna Bridge 160:5571c4ff569f 957 \details returns the FPU type
Anna Bridge 160:5571c4ff569f 958 \returns
Anna Bridge 160:5571c4ff569f 959 - \b 0: No FPU
Anna Bridge 160:5571c4ff569f 960 - \b 1: Single precision FPU
Anna Bridge 160:5571c4ff569f 961 - \b 2: Double + Single precision FPU
Anna Bridge 160:5571c4ff569f 962 */
Anna Bridge 160:5571c4ff569f 963 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
Anna Bridge 160:5571c4ff569f 964 {
Anna Bridge 160:5571c4ff569f 965 return 0U; /* No FPU */
Anna Bridge 160:5571c4ff569f 966 }
Anna Bridge 160:5571c4ff569f 967
Anna Bridge 160:5571c4ff569f 968
Anna Bridge 160:5571c4ff569f 969 /*@} end of CMSIS_Core_FpuFunctions */
Anna Bridge 160:5571c4ff569f 970
Anna Bridge 160:5571c4ff569f 971
Anna Bridge 160:5571c4ff569f 972
Anna Bridge 160:5571c4ff569f 973 /* ################################## SysTick function ############################################ */
Anna Bridge 160:5571c4ff569f 974 /**
Anna Bridge 160:5571c4ff569f 975 \ingroup CMSIS_Core_FunctionInterface
Anna Bridge 160:5571c4ff569f 976 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Anna Bridge 160:5571c4ff569f 977 \brief Functions that configure the System.
Anna Bridge 160:5571c4ff569f 978 @{
Anna Bridge 160:5571c4ff569f 979 */
Anna Bridge 160:5571c4ff569f 980
Anna Bridge 160:5571c4ff569f 981 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
Anna Bridge 160:5571c4ff569f 982
Anna Bridge 160:5571c4ff569f 983 /**
Anna Bridge 160:5571c4ff569f 984 \brief System Tick Configuration
Anna Bridge 160:5571c4ff569f 985 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Anna Bridge 160:5571c4ff569f 986 Counter is in free running mode to generate periodic interrupts.
Anna Bridge 160:5571c4ff569f 987 \param [in] ticks Number of ticks between two interrupts.
Anna Bridge 160:5571c4ff569f 988 \return 0 Function succeeded.
Anna Bridge 160:5571c4ff569f 989 \return 1 Function failed.
Anna Bridge 160:5571c4ff569f 990 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Anna Bridge 160:5571c4ff569f 991 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Anna Bridge 160:5571c4ff569f 992 must contain a vendor-specific implementation of this function.
Anna Bridge 160:5571c4ff569f 993 */
Anna Bridge 160:5571c4ff569f 994 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Anna Bridge 160:5571c4ff569f 995 {
Anna Bridge 160:5571c4ff569f 996 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
Anna Bridge 160:5571c4ff569f 997 {
Anna Bridge 160:5571c4ff569f 998 return (1UL); /* Reload value impossible */
Anna Bridge 160:5571c4ff569f 999 }
Anna Bridge 160:5571c4ff569f 1000
Anna Bridge 160:5571c4ff569f 1001 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Anna Bridge 160:5571c4ff569f 1002 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Anna Bridge 160:5571c4ff569f 1003 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Anna Bridge 160:5571c4ff569f 1004 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Anna Bridge 160:5571c4ff569f 1005 SysTick_CTRL_TICKINT_Msk |
Anna Bridge 160:5571c4ff569f 1006 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Anna Bridge 160:5571c4ff569f 1007 return (0UL); /* Function successful */
Anna Bridge 160:5571c4ff569f 1008 }
Anna Bridge 160:5571c4ff569f 1009
Anna Bridge 160:5571c4ff569f 1010 #endif
Anna Bridge 160:5571c4ff569f 1011
Anna Bridge 160:5571c4ff569f 1012 /*@} end of CMSIS_Core_SysTickFunctions */
Anna Bridge 160:5571c4ff569f 1013
Anna Bridge 160:5571c4ff569f 1014
Anna Bridge 160:5571c4ff569f 1015
Anna Bridge 160:5571c4ff569f 1016
Anna Bridge 160:5571c4ff569f 1017 #ifdef __cplusplus
Anna Bridge 160:5571c4ff569f 1018 }
Anna Bridge 160:5571c4ff569f 1019 #endif
Anna Bridge 160:5571c4ff569f 1020
Anna Bridge 160:5571c4ff569f 1021 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
Anna Bridge 160:5571c4ff569f 1022
Anna Bridge 160:5571c4ff569f 1023 #endif /* __CMSIS_GENERIC */